| File: | jdk/build/linux-x86_64-server-fastdebug/hotspot/variant-server/gensrc/adfiles/ad_x86_format.cpp |
| Warning: | line 10921, column 12 Value stored to 'idx5' during its initialization is never read |
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| 1 | #line 1 "ad_x86_format.cpp" |
| 2 | // |
| 3 | // Copyright (c) 2003, 2021, Oracle and/or its affiliates. All rights reserved. |
| 4 | // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 5 | // |
| 6 | // This code is free software; you can redistribute it and/or modify it |
| 7 | // under the terms of the GNU General Public License version 2 only, as |
| 8 | // published by the Free Software Foundation. |
| 9 | // |
| 10 | // This code is distributed in the hope that it will be useful, but WITHOUT |
| 11 | // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
| 13 | // version 2 for more details (a copy is included in the LICENSE file that |
| 14 | // accompanied this code). |
| 15 | // |
| 16 | // You should have received a copy of the GNU General Public License version |
| 17 | // 2 along with this work; if not, write to the Free Software Foundation, |
| 18 | // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
| 19 | // |
| 20 | // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
| 21 | // or visit www.oracle.com if you need additional information or have any |
| 22 | // questions. |
| 23 | // |
| 24 | // |
| 25 | |
| 26 | // Machine Generated File. Do Not Edit! |
| 27 | |
| 28 | #include "precompiled.hpp" |
| 29 | #include "adfiles/ad_x86.hpp" |
| 30 | #include "compiler/oopMap.hpp" |
| 31 | |
| 32 | #ifndef PRODUCT |
| 33 | void UniverseOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 34 | st->print("$$univ"); |
| 35 | } |
| 36 | void UniverseOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 37 | st->print("$$univ"); |
| 38 | } |
| 39 | #endif |
| 40 | |
| 41 | #ifndef PRODUCT |
| 42 | void sRegIOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 43 | } |
| 44 | void sRegIOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 45 | } |
| 46 | #endif |
| 47 | |
| 48 | #ifndef PRODUCT |
| 49 | void sRegPOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 50 | } |
| 51 | void sRegPOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 52 | } |
| 53 | #endif |
| 54 | |
| 55 | #ifndef PRODUCT |
| 56 | void sRegFOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 57 | } |
| 58 | void sRegFOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 59 | } |
| 60 | #endif |
| 61 | |
| 62 | #ifndef PRODUCT |
| 63 | void sRegDOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 64 | } |
| 65 | void sRegDOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 66 | } |
| 67 | #endif |
| 68 | |
| 69 | #ifndef PRODUCT |
| 70 | void sRegLOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 71 | } |
| 72 | void sRegLOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 73 | } |
| 74 | #endif |
| 75 | |
| 76 | #ifndef PRODUCT |
| 77 | void immIOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 78 | st->print("#%d", _c0); |
| 79 | } |
| 80 | void immIOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 81 | st->print("#%d", _c0); |
| 82 | } |
| 83 | #endif |
| 84 | |
| 85 | #ifndef PRODUCT |
| 86 | void immI_0Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 87 | st->print("#%d", _c0); |
| 88 | } |
| 89 | void immI_0Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 90 | st->print("#%d", _c0); |
| 91 | } |
| 92 | #endif |
| 93 | |
| 94 | #ifndef PRODUCT |
| 95 | void immI_1Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 96 | st->print("#%d", _c0); |
| 97 | } |
| 98 | void immI_1Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 99 | st->print("#%d", _c0); |
| 100 | } |
| 101 | #endif |
| 102 | |
| 103 | #ifndef PRODUCT |
| 104 | void immI_M1Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 105 | st->print("#%d", _c0); |
| 106 | } |
| 107 | void immI_M1Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 108 | st->print("#%d", _c0); |
| 109 | } |
| 110 | #endif |
| 111 | |
| 112 | #ifndef PRODUCT |
| 113 | void immI_2Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 114 | st->print("#%d", _c0); |
| 115 | } |
| 116 | void immI_2Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 117 | st->print("#%d", _c0); |
| 118 | } |
| 119 | #endif |
| 120 | |
| 121 | #ifndef PRODUCT |
| 122 | void immI_4Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 123 | st->print("#%d", _c0); |
| 124 | } |
| 125 | void immI_4Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 126 | st->print("#%d", _c0); |
| 127 | } |
| 128 | #endif |
| 129 | |
| 130 | #ifndef PRODUCT |
| 131 | void immI_8Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 132 | st->print("#%d", _c0); |
| 133 | } |
| 134 | void immI_8Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 135 | st->print("#%d", _c0); |
| 136 | } |
| 137 | #endif |
| 138 | |
| 139 | #ifndef PRODUCT |
| 140 | void immI2Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 141 | st->print("#%d", _c0); |
| 142 | } |
| 143 | void immI2Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 144 | st->print("#%d", _c0); |
| 145 | } |
| 146 | #endif |
| 147 | |
| 148 | #ifndef PRODUCT |
| 149 | void immU7Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 150 | st->print("#%d", _c0); |
| 151 | } |
| 152 | void immU7Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 153 | st->print("#%d", _c0); |
| 154 | } |
| 155 | #endif |
| 156 | |
| 157 | #ifndef PRODUCT |
| 158 | void immI8Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 159 | st->print("#%d", _c0); |
| 160 | } |
| 161 | void immI8Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 162 | st->print("#%d", _c0); |
| 163 | } |
| 164 | #endif |
| 165 | |
| 166 | #ifndef PRODUCT |
| 167 | void immU8Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 168 | st->print("#%d", _c0); |
| 169 | } |
| 170 | void immU8Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 171 | st->print("#%d", _c0); |
| 172 | } |
| 173 | #endif |
| 174 | |
| 175 | #ifndef PRODUCT |
| 176 | void immI16Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 177 | st->print("#%d", _c0); |
| 178 | } |
| 179 | void immI16Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 180 | st->print("#%d", _c0); |
| 181 | } |
| 182 | #endif |
| 183 | |
| 184 | #ifndef PRODUCT |
| 185 | void immU31Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 186 | st->print("#%d", _c0); |
| 187 | } |
| 188 | void immU31Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 189 | st->print("#%d", _c0); |
| 190 | } |
| 191 | #endif |
| 192 | |
| 193 | #ifndef PRODUCT |
| 194 | void immI_32Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 195 | st->print("#%d", _c0); |
| 196 | } |
| 197 | void immI_32Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 198 | st->print("#%d", _c0); |
| 199 | } |
| 200 | #endif |
| 201 | |
| 202 | #ifndef PRODUCT |
| 203 | void immI_64Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 204 | st->print("#%d", _c0); |
| 205 | } |
| 206 | void immI_64Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 207 | st->print("#%d", _c0); |
| 208 | } |
| 209 | #endif |
| 210 | |
| 211 | #ifndef PRODUCT |
| 212 | void immPOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 213 | if (_c0) _c0->dump_on(st); |
| 214 | } |
| 215 | void immPOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 216 | if (_c0) _c0->dump_on(st); |
| 217 | } |
| 218 | #endif |
| 219 | |
| 220 | #ifndef PRODUCT |
| 221 | void immP0Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 222 | if (_c0) _c0->dump_on(st); |
| 223 | } |
| 224 | void immP0Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 225 | if (_c0) _c0->dump_on(st); |
| 226 | } |
| 227 | #endif |
| 228 | |
| 229 | #ifndef PRODUCT |
| 230 | void immNOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 231 | if (_c0) _c0->dump_on(st); |
| 232 | } |
| 233 | void immNOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 234 | if (_c0) _c0->dump_on(st); |
| 235 | } |
| 236 | #endif |
| 237 | |
| 238 | #ifndef PRODUCT |
| 239 | void immNKlassOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 240 | if (_c0) _c0->dump_on(st); |
| 241 | } |
| 242 | void immNKlassOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 243 | if (_c0) _c0->dump_on(st); |
| 244 | } |
| 245 | #endif |
| 246 | |
| 247 | #ifndef PRODUCT |
| 248 | void immN0Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 249 | if (_c0) _c0->dump_on(st); |
| 250 | } |
| 251 | void immN0Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 252 | if (_c0) _c0->dump_on(st); |
| 253 | } |
| 254 | #endif |
| 255 | |
| 256 | #ifndef PRODUCT |
| 257 | void immP31Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 258 | if (_c0) _c0->dump_on(st); |
| 259 | } |
| 260 | void immP31Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 261 | if (_c0) _c0->dump_on(st); |
| 262 | } |
| 263 | #endif |
| 264 | |
| 265 | #ifndef PRODUCT |
| 266 | void immLOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 267 | st->print("#" INT64_FORMAT"%" "l" "d", (int64_t)_c0); |
| 268 | } |
| 269 | void immLOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 270 | st->print("#" INT64_FORMAT"%" "l" "d", (int64_t)_c0); |
| 271 | } |
| 272 | #endif |
| 273 | |
| 274 | #ifndef PRODUCT |
| 275 | void immL8Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 276 | st->print("#" INT64_FORMAT"%" "l" "d", (int64_t)_c0); |
| 277 | } |
| 278 | void immL8Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 279 | st->print("#" INT64_FORMAT"%" "l" "d", (int64_t)_c0); |
| 280 | } |
| 281 | #endif |
| 282 | |
| 283 | #ifndef PRODUCT |
| 284 | void immUL32Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 285 | st->print("#" INT64_FORMAT"%" "l" "d", (int64_t)_c0); |
| 286 | } |
| 287 | void immUL32Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 288 | st->print("#" INT64_FORMAT"%" "l" "d", (int64_t)_c0); |
| 289 | } |
| 290 | #endif |
| 291 | |
| 292 | #ifndef PRODUCT |
| 293 | void immL32Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 294 | st->print("#" INT64_FORMAT"%" "l" "d", (int64_t)_c0); |
| 295 | } |
| 296 | void immL32Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 297 | st->print("#" INT64_FORMAT"%" "l" "d", (int64_t)_c0); |
| 298 | } |
| 299 | #endif |
| 300 | |
| 301 | #ifndef PRODUCT |
| 302 | void immL_Pow2Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 303 | st->print("#" INT64_FORMAT"%" "l" "d", (int64_t)_c0); |
| 304 | } |
| 305 | void immL_Pow2Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 306 | st->print("#" INT64_FORMAT"%" "l" "d", (int64_t)_c0); |
| 307 | } |
| 308 | #endif |
| 309 | |
| 310 | #ifndef PRODUCT |
| 311 | void immL_NotPow2Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 312 | st->print("#" INT64_FORMAT"%" "l" "d", (int64_t)_c0); |
| 313 | } |
| 314 | void immL_NotPow2Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 315 | st->print("#" INT64_FORMAT"%" "l" "d", (int64_t)_c0); |
| 316 | } |
| 317 | #endif |
| 318 | |
| 319 | #ifndef PRODUCT |
| 320 | void immL0Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 321 | st->print("#" INT64_FORMAT"%" "l" "d", (int64_t)_c0); |
| 322 | } |
| 323 | void immL0Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 324 | st->print("#" INT64_FORMAT"%" "l" "d", (int64_t)_c0); |
| 325 | } |
| 326 | #endif |
| 327 | |
| 328 | #ifndef PRODUCT |
| 329 | void immL1Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 330 | st->print("#" INT64_FORMAT"%" "l" "d", (int64_t)_c0); |
| 331 | } |
| 332 | void immL1Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 333 | st->print("#" INT64_FORMAT"%" "l" "d", (int64_t)_c0); |
| 334 | } |
| 335 | #endif |
| 336 | |
| 337 | #ifndef PRODUCT |
| 338 | void immL_M1Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 339 | st->print("#" INT64_FORMAT"%" "l" "d", (int64_t)_c0); |
| 340 | } |
| 341 | void immL_M1Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 342 | st->print("#" INT64_FORMAT"%" "l" "d", (int64_t)_c0); |
| 343 | } |
| 344 | #endif |
| 345 | |
| 346 | #ifndef PRODUCT |
| 347 | void immL10Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 348 | st->print("#" INT64_FORMAT"%" "l" "d", (int64_t)_c0); |
| 349 | } |
| 350 | void immL10Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 351 | st->print("#" INT64_FORMAT"%" "l" "d", (int64_t)_c0); |
| 352 | } |
| 353 | #endif |
| 354 | |
| 355 | #ifndef PRODUCT |
| 356 | void immL_127Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 357 | st->print("#" INT64_FORMAT"%" "l" "d", (int64_t)_c0); |
| 358 | } |
| 359 | void immL_127Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 360 | st->print("#" INT64_FORMAT"%" "l" "d", (int64_t)_c0); |
| 361 | } |
| 362 | #endif |
| 363 | |
| 364 | #ifndef PRODUCT |
| 365 | void immL_32bitsOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 366 | st->print("#" INT64_FORMAT"%" "l" "d", (int64_t)_c0); |
| 367 | } |
| 368 | void immL_32bitsOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 369 | st->print("#" INT64_FORMAT"%" "l" "d", (int64_t)_c0); |
| 370 | } |
| 371 | #endif |
| 372 | |
| 373 | #ifndef PRODUCT |
| 374 | void immI_Pow2M1Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 375 | st->print("#%d", _c0); |
| 376 | } |
| 377 | void immI_Pow2M1Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 378 | st->print("#%d", _c0); |
| 379 | } |
| 380 | #endif |
| 381 | |
| 382 | #ifndef PRODUCT |
| 383 | void immF0Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 384 | st->print("#%f", _c0); |
| 385 | } |
| 386 | void immF0Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 387 | st->print("#%f", _c0); |
| 388 | } |
| 389 | #endif |
| 390 | |
| 391 | #ifndef PRODUCT |
| 392 | void immFOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 393 | st->print("#%f", _c0); |
| 394 | } |
| 395 | void immFOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 396 | st->print("#%f", _c0); |
| 397 | } |
| 398 | #endif |
| 399 | |
| 400 | #ifndef PRODUCT |
| 401 | void immD0Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 402 | st->print("#%f", _c0); |
| 403 | } |
| 404 | void immD0Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 405 | st->print("#%f", _c0); |
| 406 | } |
| 407 | #endif |
| 408 | |
| 409 | #ifndef PRODUCT |
| 410 | void immDOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 411 | st->print("#%f", _c0); |
| 412 | } |
| 413 | void immDOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 414 | st->print("#%f", _c0); |
| 415 | } |
| 416 | #endif |
| 417 | |
| 418 | #ifndef PRODUCT |
| 419 | void immI_16Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 420 | st->print("#%d", _c0); |
| 421 | } |
| 422 | void immI_16Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 423 | st->print("#%d", _c0); |
| 424 | } |
| 425 | #endif |
| 426 | |
| 427 | #ifndef PRODUCT |
| 428 | void immI_24Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 429 | st->print("#%d", _c0); |
| 430 | } |
| 431 | void immI_24Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 432 | st->print("#%d", _c0); |
| 433 | } |
| 434 | #endif |
| 435 | |
| 436 | #ifndef PRODUCT |
| 437 | void immI_255Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 438 | st->print("#%d", _c0); |
| 439 | } |
| 440 | void immI_255Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 441 | st->print("#%d", _c0); |
| 442 | } |
| 443 | #endif |
| 444 | |
| 445 | #ifndef PRODUCT |
| 446 | void immI_65535Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 447 | st->print("#%d", _c0); |
| 448 | } |
| 449 | void immI_65535Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 450 | st->print("#%d", _c0); |
| 451 | } |
| 452 | #endif |
| 453 | |
| 454 | #ifndef PRODUCT |
| 455 | void immL_255Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 456 | st->print("#" INT64_FORMAT"%" "l" "d", (int64_t)_c0); |
| 457 | } |
| 458 | void immL_255Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 459 | st->print("#" INT64_FORMAT"%" "l" "d", (int64_t)_c0); |
| 460 | } |
| 461 | #endif |
| 462 | |
| 463 | #ifndef PRODUCT |
| 464 | void immL_65535Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 465 | st->print("#" INT64_FORMAT"%" "l" "d", (int64_t)_c0); |
| 466 | } |
| 467 | void immL_65535Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 468 | st->print("#" INT64_FORMAT"%" "l" "d", (int64_t)_c0); |
| 469 | } |
| 470 | #endif |
| 471 | |
| 472 | #ifndef PRODUCT |
| 473 | void kRegOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 474 | { char reg_str[128]; |
| 475 | ra->dump_register(node,reg_str); |
| 476 | st->print("%s",reg_str); |
| 477 | } |
| 478 | } |
| 479 | void kRegOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 480 | { char reg_str[128]; |
| 481 | ra->dump_register(node->in(idx),reg_str); |
| 482 | st->print("%s",reg_str); |
| 483 | } |
| 484 | } |
| 485 | #endif |
| 486 | |
| 487 | #ifndef PRODUCT |
| 488 | void kReg_K1Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 489 | { char reg_str[128]; |
| 490 | ra->dump_register(node,reg_str); |
| 491 | st->print("%s",reg_str); |
| 492 | } |
| 493 | } |
| 494 | void kReg_K1Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 495 | { char reg_str[128]; |
| 496 | ra->dump_register(node->in(idx),reg_str); |
| 497 | st->print("%s",reg_str); |
| 498 | } |
| 499 | } |
| 500 | #endif |
| 501 | |
| 502 | #ifndef PRODUCT |
| 503 | void kReg_K2Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 504 | { char reg_str[128]; |
| 505 | ra->dump_register(node,reg_str); |
| 506 | st->print("%s",reg_str); |
| 507 | } |
| 508 | } |
| 509 | void kReg_K2Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 510 | { char reg_str[128]; |
| 511 | ra->dump_register(node->in(idx),reg_str); |
| 512 | st->print("%s",reg_str); |
| 513 | } |
| 514 | } |
| 515 | #endif |
| 516 | |
| 517 | #ifndef PRODUCT |
| 518 | void kReg_K3Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 519 | { char reg_str[128]; |
| 520 | ra->dump_register(node,reg_str); |
| 521 | st->print("%s",reg_str); |
| 522 | } |
| 523 | } |
| 524 | void kReg_K3Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 525 | { char reg_str[128]; |
| 526 | ra->dump_register(node->in(idx),reg_str); |
| 527 | st->print("%s",reg_str); |
| 528 | } |
| 529 | } |
| 530 | #endif |
| 531 | |
| 532 | #ifndef PRODUCT |
| 533 | void kReg_K4Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 534 | { char reg_str[128]; |
| 535 | ra->dump_register(node,reg_str); |
| 536 | st->print("%s",reg_str); |
| 537 | } |
| 538 | } |
| 539 | void kReg_K4Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 540 | { char reg_str[128]; |
| 541 | ra->dump_register(node->in(idx),reg_str); |
| 542 | st->print("%s",reg_str); |
| 543 | } |
| 544 | } |
| 545 | #endif |
| 546 | |
| 547 | #ifndef PRODUCT |
| 548 | void kReg_K5Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 549 | { char reg_str[128]; |
| 550 | ra->dump_register(node,reg_str); |
| 551 | st->print("%s",reg_str); |
| 552 | } |
| 553 | } |
| 554 | void kReg_K5Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 555 | { char reg_str[128]; |
| 556 | ra->dump_register(node->in(idx),reg_str); |
| 557 | st->print("%s",reg_str); |
| 558 | } |
| 559 | } |
| 560 | #endif |
| 561 | |
| 562 | #ifndef PRODUCT |
| 563 | void kReg_K6Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 564 | { char reg_str[128]; |
| 565 | ra->dump_register(node,reg_str); |
| 566 | st->print("%s",reg_str); |
| 567 | } |
| 568 | } |
| 569 | void kReg_K6Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 570 | { char reg_str[128]; |
| 571 | ra->dump_register(node->in(idx),reg_str); |
| 572 | st->print("%s",reg_str); |
| 573 | } |
| 574 | } |
| 575 | #endif |
| 576 | |
| 577 | #ifndef PRODUCT |
| 578 | void kReg_K7Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 579 | { char reg_str[128]; |
| 580 | ra->dump_register(node,reg_str); |
| 581 | st->print("%s",reg_str); |
| 582 | } |
| 583 | } |
| 584 | void kReg_K7Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 585 | { char reg_str[128]; |
| 586 | ra->dump_register(node->in(idx),reg_str); |
| 587 | st->print("%s",reg_str); |
| 588 | } |
| 589 | } |
| 590 | #endif |
| 591 | |
| 592 | #ifndef PRODUCT |
| 593 | void rRegIOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 594 | { char reg_str[128]; |
| 595 | ra->dump_register(node,reg_str); |
| 596 | st->print("%s",reg_str); |
| 597 | } |
| 598 | } |
| 599 | void rRegIOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 600 | { char reg_str[128]; |
| 601 | ra->dump_register(node->in(idx),reg_str); |
| 602 | st->print("%s",reg_str); |
| 603 | } |
| 604 | } |
| 605 | #endif |
| 606 | |
| 607 | #ifndef PRODUCT |
| 608 | void rax_RegIOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 609 | st->print_raw("RAX"); |
| 610 | } |
| 611 | void rax_RegIOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 612 | st->print_raw("RAX"); |
| 613 | } |
| 614 | #endif |
| 615 | |
| 616 | #ifndef PRODUCT |
| 617 | void rbx_RegIOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 618 | st->print_raw("RBX"); |
| 619 | } |
| 620 | void rbx_RegIOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 621 | st->print_raw("RBX"); |
| 622 | } |
| 623 | #endif |
| 624 | |
| 625 | #ifndef PRODUCT |
| 626 | void rcx_RegIOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 627 | st->print_raw("RCX"); |
| 628 | } |
| 629 | void rcx_RegIOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 630 | st->print_raw("RCX"); |
| 631 | } |
| 632 | #endif |
| 633 | |
| 634 | #ifndef PRODUCT |
| 635 | void rdx_RegIOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 636 | st->print_raw("RDX"); |
| 637 | } |
| 638 | void rdx_RegIOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 639 | st->print_raw("RDX"); |
| 640 | } |
| 641 | #endif |
| 642 | |
| 643 | #ifndef PRODUCT |
| 644 | void rdi_RegIOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 645 | st->print_raw("RDI"); |
| 646 | } |
| 647 | void rdi_RegIOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 648 | st->print_raw("RDI"); |
| 649 | } |
| 650 | #endif |
| 651 | |
| 652 | #ifndef PRODUCT |
| 653 | void no_rax_rdx_RegIOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 654 | { char reg_str[128]; |
| 655 | ra->dump_register(node,reg_str); |
| 656 | st->print("%s",reg_str); |
| 657 | } |
| 658 | } |
| 659 | void no_rax_rdx_RegIOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 660 | { char reg_str[128]; |
| 661 | ra->dump_register(node->in(idx),reg_str); |
| 662 | st->print("%s",reg_str); |
| 663 | } |
| 664 | } |
| 665 | #endif |
| 666 | |
| 667 | #ifndef PRODUCT |
| 668 | void any_RegPOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 669 | { char reg_str[128]; |
| 670 | ra->dump_register(node,reg_str); |
| 671 | st->print("%s",reg_str); |
| 672 | } |
| 673 | } |
| 674 | void any_RegPOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 675 | { char reg_str[128]; |
| 676 | ra->dump_register(node->in(idx),reg_str); |
| 677 | st->print("%s",reg_str); |
| 678 | } |
| 679 | } |
| 680 | #endif |
| 681 | |
| 682 | #ifndef PRODUCT |
| 683 | void rRegPOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 684 | { char reg_str[128]; |
| 685 | ra->dump_register(node,reg_str); |
| 686 | st->print("%s",reg_str); |
| 687 | } |
| 688 | } |
| 689 | void rRegPOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 690 | { char reg_str[128]; |
| 691 | ra->dump_register(node->in(idx),reg_str); |
| 692 | st->print("%s",reg_str); |
| 693 | } |
| 694 | } |
| 695 | #endif |
| 696 | |
| 697 | #ifndef PRODUCT |
| 698 | void rRegNOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 699 | { char reg_str[128]; |
| 700 | ra->dump_register(node,reg_str); |
| 701 | st->print("%s",reg_str); |
| 702 | } |
| 703 | } |
| 704 | void rRegNOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 705 | { char reg_str[128]; |
| 706 | ra->dump_register(node->in(idx),reg_str); |
| 707 | st->print("%s",reg_str); |
| 708 | } |
| 709 | } |
| 710 | #endif |
| 711 | |
| 712 | #ifndef PRODUCT |
| 713 | void no_rax_RegPOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 714 | { char reg_str[128]; |
| 715 | ra->dump_register(node,reg_str); |
| 716 | st->print("%s",reg_str); |
| 717 | } |
| 718 | } |
| 719 | void no_rax_RegPOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 720 | { char reg_str[128]; |
| 721 | ra->dump_register(node->in(idx),reg_str); |
| 722 | st->print("%s",reg_str); |
| 723 | } |
| 724 | } |
| 725 | #endif |
| 726 | |
| 727 | #ifndef PRODUCT |
| 728 | void no_rbp_RegPOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 729 | { char reg_str[128]; |
| 730 | ra->dump_register(node,reg_str); |
| 731 | st->print("%s",reg_str); |
| 732 | } |
| 733 | } |
| 734 | void no_rbp_RegPOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 735 | { char reg_str[128]; |
| 736 | ra->dump_register(node->in(idx),reg_str); |
| 737 | st->print("%s",reg_str); |
| 738 | } |
| 739 | } |
| 740 | #endif |
| 741 | |
| 742 | #ifndef PRODUCT |
| 743 | void no_rax_rbx_RegPOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 744 | { char reg_str[128]; |
| 745 | ra->dump_register(node,reg_str); |
| 746 | st->print("%s",reg_str); |
| 747 | } |
| 748 | } |
| 749 | void no_rax_rbx_RegPOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 750 | { char reg_str[128]; |
| 751 | ra->dump_register(node->in(idx),reg_str); |
| 752 | st->print("%s",reg_str); |
| 753 | } |
| 754 | } |
| 755 | #endif |
| 756 | |
| 757 | #ifndef PRODUCT |
| 758 | void rax_RegPOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 759 | { char reg_str[128]; |
| 760 | ra->dump_register(node,reg_str); |
| 761 | st->print("%s",reg_str); |
| 762 | } |
| 763 | } |
| 764 | void rax_RegPOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 765 | { char reg_str[128]; |
| 766 | ra->dump_register(node->in(idx),reg_str); |
| 767 | st->print("%s",reg_str); |
| 768 | } |
| 769 | } |
| 770 | #endif |
| 771 | |
| 772 | #ifndef PRODUCT |
| 773 | void rax_RegNOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 774 | { char reg_str[128]; |
| 775 | ra->dump_register(node,reg_str); |
| 776 | st->print("%s",reg_str); |
| 777 | } |
| 778 | } |
| 779 | void rax_RegNOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 780 | { char reg_str[128]; |
| 781 | ra->dump_register(node->in(idx),reg_str); |
| 782 | st->print("%s",reg_str); |
| 783 | } |
| 784 | } |
| 785 | #endif |
| 786 | |
| 787 | #ifndef PRODUCT |
| 788 | void rbx_RegPOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 789 | { char reg_str[128]; |
| 790 | ra->dump_register(node,reg_str); |
| 791 | st->print("%s",reg_str); |
| 792 | } |
| 793 | } |
| 794 | void rbx_RegPOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 795 | { char reg_str[128]; |
| 796 | ra->dump_register(node->in(idx),reg_str); |
| 797 | st->print("%s",reg_str); |
| 798 | } |
| 799 | } |
| 800 | #endif |
| 801 | |
| 802 | #ifndef PRODUCT |
| 803 | void rsi_RegPOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 804 | { char reg_str[128]; |
| 805 | ra->dump_register(node,reg_str); |
| 806 | st->print("%s",reg_str); |
| 807 | } |
| 808 | } |
| 809 | void rsi_RegPOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 810 | { char reg_str[128]; |
| 811 | ra->dump_register(node->in(idx),reg_str); |
| 812 | st->print("%s",reg_str); |
| 813 | } |
| 814 | } |
| 815 | #endif |
| 816 | |
| 817 | #ifndef PRODUCT |
| 818 | void rbp_RegPOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 819 | { char reg_str[128]; |
| 820 | ra->dump_register(node,reg_str); |
| 821 | st->print("%s",reg_str); |
| 822 | } |
| 823 | } |
| 824 | void rbp_RegPOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 825 | { char reg_str[128]; |
| 826 | ra->dump_register(node->in(idx),reg_str); |
| 827 | st->print("%s",reg_str); |
| 828 | } |
| 829 | } |
| 830 | #endif |
| 831 | |
| 832 | #ifndef PRODUCT |
| 833 | void rdi_RegPOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 834 | { char reg_str[128]; |
| 835 | ra->dump_register(node,reg_str); |
| 836 | st->print("%s",reg_str); |
| 837 | } |
| 838 | } |
| 839 | void rdi_RegPOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 840 | { char reg_str[128]; |
| 841 | ra->dump_register(node->in(idx),reg_str); |
| 842 | st->print("%s",reg_str); |
| 843 | } |
| 844 | } |
| 845 | #endif |
| 846 | |
| 847 | #ifndef PRODUCT |
| 848 | void r15_RegPOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 849 | { char reg_str[128]; |
| 850 | ra->dump_register(node,reg_str); |
| 851 | st->print("%s",reg_str); |
| 852 | } |
| 853 | } |
| 854 | void r15_RegPOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 855 | { char reg_str[128]; |
| 856 | ra->dump_register(node->in(idx),reg_str); |
| 857 | st->print("%s",reg_str); |
| 858 | } |
| 859 | } |
| 860 | #endif |
| 861 | |
| 862 | #ifndef PRODUCT |
| 863 | void rRegLOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 864 | { char reg_str[128]; |
| 865 | ra->dump_register(node,reg_str); |
| 866 | st->print("%s",reg_str); |
| 867 | } |
| 868 | } |
| 869 | void rRegLOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 870 | { char reg_str[128]; |
| 871 | ra->dump_register(node->in(idx),reg_str); |
| 872 | st->print("%s",reg_str); |
| 873 | } |
| 874 | } |
| 875 | #endif |
| 876 | |
| 877 | #ifndef PRODUCT |
| 878 | void no_rax_rdx_RegLOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 879 | { char reg_str[128]; |
| 880 | ra->dump_register(node,reg_str); |
| 881 | st->print("%s",reg_str); |
| 882 | } |
| 883 | } |
| 884 | void no_rax_rdx_RegLOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 885 | { char reg_str[128]; |
| 886 | ra->dump_register(node->in(idx),reg_str); |
| 887 | st->print("%s",reg_str); |
| 888 | } |
| 889 | } |
| 890 | #endif |
| 891 | |
| 892 | #ifndef PRODUCT |
| 893 | void no_rax_RegLOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 894 | { char reg_str[128]; |
| 895 | ra->dump_register(node,reg_str); |
| 896 | st->print("%s",reg_str); |
| 897 | } |
| 898 | } |
| 899 | void no_rax_RegLOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 900 | { char reg_str[128]; |
| 901 | ra->dump_register(node->in(idx),reg_str); |
| 902 | st->print("%s",reg_str); |
| 903 | } |
| 904 | } |
| 905 | #endif |
| 906 | |
| 907 | #ifndef PRODUCT |
| 908 | void rax_RegLOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 909 | st->print_raw("RAX"); |
| 910 | } |
| 911 | void rax_RegLOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 912 | st->print_raw("RAX"); |
| 913 | } |
| 914 | #endif |
| 915 | |
| 916 | #ifndef PRODUCT |
| 917 | void rcx_RegLOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 918 | { char reg_str[128]; |
| 919 | ra->dump_register(node,reg_str); |
| 920 | st->print("%s",reg_str); |
| 921 | } |
| 922 | } |
| 923 | void rcx_RegLOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 924 | { char reg_str[128]; |
| 925 | ra->dump_register(node->in(idx),reg_str); |
| 926 | st->print("%s",reg_str); |
| 927 | } |
| 928 | } |
| 929 | #endif |
| 930 | |
| 931 | #ifndef PRODUCT |
| 932 | void rdx_RegLOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 933 | { char reg_str[128]; |
| 934 | ra->dump_register(node,reg_str); |
| 935 | st->print("%s",reg_str); |
| 936 | } |
| 937 | } |
| 938 | void rdx_RegLOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 939 | { char reg_str[128]; |
| 940 | ra->dump_register(node->in(idx),reg_str); |
| 941 | st->print("%s",reg_str); |
| 942 | } |
| 943 | } |
| 944 | #endif |
| 945 | |
| 946 | #ifndef PRODUCT |
| 947 | void rFlagsRegOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 948 | st->print_raw("RFLAGS"); |
| 949 | } |
| 950 | void rFlagsRegOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 951 | st->print_raw("RFLAGS"); |
| 952 | } |
| 953 | #endif |
| 954 | |
| 955 | #ifndef PRODUCT |
| 956 | void rFlagsRegUOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 957 | st->print_raw("RFLAGS_U"); |
| 958 | } |
| 959 | void rFlagsRegUOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 960 | st->print_raw("RFLAGS_U"); |
| 961 | } |
| 962 | #endif |
| 963 | |
| 964 | #ifndef PRODUCT |
| 965 | void rFlagsRegUCFOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 966 | st->print_raw("RFLAGS_U_CF"); |
| 967 | } |
| 968 | void rFlagsRegUCFOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 969 | st->print_raw("RFLAGS_U_CF"); |
| 970 | } |
| 971 | #endif |
| 972 | |
| 973 | #ifndef PRODUCT |
| 974 | void regFOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 975 | { char reg_str[128]; |
| 976 | ra->dump_register(node,reg_str); |
| 977 | st->print("%s",reg_str); |
| 978 | } |
| 979 | } |
| 980 | void regFOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 981 | { char reg_str[128]; |
| 982 | ra->dump_register(node->in(idx),reg_str); |
| 983 | st->print("%s",reg_str); |
| 984 | } |
| 985 | } |
| 986 | #endif |
| 987 | |
| 988 | #ifndef PRODUCT |
| 989 | void legRegFOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 990 | { char reg_str[128]; |
| 991 | ra->dump_register(node,reg_str); |
| 992 | st->print("%s",reg_str); |
| 993 | } |
| 994 | } |
| 995 | void legRegFOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 996 | { char reg_str[128]; |
| 997 | ra->dump_register(node->in(idx),reg_str); |
| 998 | st->print("%s",reg_str); |
| 999 | } |
| 1000 | } |
| 1001 | #endif |
| 1002 | |
| 1003 | #ifndef PRODUCT |
| 1004 | void vlRegFOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 1005 | { char reg_str[128]; |
| 1006 | ra->dump_register(node,reg_str); |
| 1007 | st->print("%s",reg_str); |
| 1008 | } |
| 1009 | } |
| 1010 | void vlRegFOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 1011 | { char reg_str[128]; |
| 1012 | ra->dump_register(node->in(idx),reg_str); |
| 1013 | st->print("%s",reg_str); |
| 1014 | } |
| 1015 | } |
| 1016 | #endif |
| 1017 | |
| 1018 | #ifndef PRODUCT |
| 1019 | void regDOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 1020 | { char reg_str[128]; |
| 1021 | ra->dump_register(node,reg_str); |
| 1022 | st->print("%s",reg_str); |
| 1023 | } |
| 1024 | } |
| 1025 | void regDOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 1026 | { char reg_str[128]; |
| 1027 | ra->dump_register(node->in(idx),reg_str); |
| 1028 | st->print("%s",reg_str); |
| 1029 | } |
| 1030 | } |
| 1031 | #endif |
| 1032 | |
| 1033 | #ifndef PRODUCT |
| 1034 | void legRegDOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 1035 | { char reg_str[128]; |
| 1036 | ra->dump_register(node,reg_str); |
| 1037 | st->print("%s",reg_str); |
| 1038 | } |
| 1039 | } |
| 1040 | void legRegDOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 1041 | { char reg_str[128]; |
| 1042 | ra->dump_register(node->in(idx),reg_str); |
| 1043 | st->print("%s",reg_str); |
| 1044 | } |
| 1045 | } |
| 1046 | #endif |
| 1047 | |
| 1048 | #ifndef PRODUCT |
| 1049 | void vlRegDOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 1050 | { char reg_str[128]; |
| 1051 | ra->dump_register(node,reg_str); |
| 1052 | st->print("%s",reg_str); |
| 1053 | } |
| 1054 | } |
| 1055 | void vlRegDOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 1056 | { char reg_str[128]; |
| 1057 | ra->dump_register(node->in(idx),reg_str); |
| 1058 | st->print("%s",reg_str); |
| 1059 | } |
| 1060 | } |
| 1061 | #endif |
| 1062 | |
| 1063 | #ifndef PRODUCT |
| 1064 | void indirectOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 1065 | st->print_raw("["); |
| 1066 | { char reg_str[128]; |
| 1067 | ra->dump_register(node,reg_str); |
| 1068 | st->print("%s",reg_str); |
| 1069 | } |
| 1070 | st->print_raw("]"); |
| 1071 | } |
| 1072 | void indirectOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 1073 | st->print_raw("["); |
| 1074 | { char reg_str[128]; |
| 1075 | ra->dump_register(node->in(idx),reg_str); |
| 1076 | st->print("%s",reg_str); |
| 1077 | } |
| 1078 | st->print_raw("]"); |
| 1079 | } |
| 1080 | #endif |
| 1081 | |
| 1082 | #ifndef PRODUCT |
| 1083 | void indOffset8Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 1084 | st->print_raw("["); |
| 1085 | { char reg_str[128]; |
| 1086 | ra->dump_register(node,reg_str); |
| 1087 | st->print("%s",reg_str); |
| 1088 | } |
| 1089 | st->print_raw(" + "); |
| 1090 | st->print("#" INT64_FORMAT"%" "l" "d", (int64_t)_c0); |
| 1091 | st->print_raw(" (8-bit)]"); |
| 1092 | } |
| 1093 | void indOffset8Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 1094 | st->print_raw("["); |
| 1095 | { char reg_str[128]; |
| 1096 | ra->dump_register(node->in(idx),reg_str); |
| 1097 | st->print("%s",reg_str); |
| 1098 | } |
| 1099 | st->print_raw(" + "); |
| 1100 | st->print("#" INT64_FORMAT"%" "l" "d", (int64_t)_c0); |
| 1101 | st->print_raw(" (8-bit)]"); |
| 1102 | } |
| 1103 | #endif |
| 1104 | |
| 1105 | #ifndef PRODUCT |
| 1106 | void indOffset32Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 1107 | st->print_raw("["); |
| 1108 | { char reg_str[128]; |
| 1109 | ra->dump_register(node,reg_str); |
| 1110 | st->print("%s",reg_str); |
| 1111 | } |
| 1112 | st->print_raw(" + "); |
| 1113 | st->print("#" INT64_FORMAT"%" "l" "d", (int64_t)_c0); |
| 1114 | st->print_raw(" (32-bit)]"); |
| 1115 | } |
| 1116 | void indOffset32Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 1117 | st->print_raw("["); |
| 1118 | { char reg_str[128]; |
| 1119 | ra->dump_register(node->in(idx),reg_str); |
| 1120 | st->print("%s",reg_str); |
| 1121 | } |
| 1122 | st->print_raw(" + "); |
| 1123 | st->print("#" INT64_FORMAT"%" "l" "d", (int64_t)_c0); |
| 1124 | st->print_raw(" (32-bit)]"); |
| 1125 | } |
| 1126 | #endif |
| 1127 | |
| 1128 | #ifndef PRODUCT |
| 1129 | void indIndexOffsetOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 1130 | st->print_raw("["); |
| 1131 | { char reg_str[128]; |
| 1132 | ra->dump_register(node,reg_str); |
| 1133 | st->print("%s",reg_str); |
| 1134 | } |
| 1135 | st->print_raw(" + "); |
| 1136 | st->print("#" INT64_FORMAT"%" "l" "d", (int64_t)_c0); |
| 1137 | st->print_raw(" + "); |
| 1138 | { char reg_str[128]; |
| 1139 | ra->dump_register(node,reg_str); |
| 1140 | st->print("%s",reg_str); |
| 1141 | } |
| 1142 | st->print_raw("]"); |
| 1143 | } |
| 1144 | void indIndexOffsetOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 1145 | st->print_raw("["); |
| 1146 | { char reg_str[128]; |
| 1147 | ra->dump_register(node->in(idx),reg_str); |
| 1148 | st->print("%s",reg_str); |
| 1149 | } |
| 1150 | st->print_raw(" + "); |
| 1151 | st->print("#" INT64_FORMAT"%" "l" "d", (int64_t)_c0); |
| 1152 | st->print_raw(" + "); |
| 1153 | { char reg_str[128]; |
| 1154 | ra->dump_register(node->in(idx+1),reg_str); |
| 1155 | st->print("%s",reg_str); |
| 1156 | } |
| 1157 | st->print_raw("]"); |
| 1158 | } |
| 1159 | #endif |
| 1160 | |
| 1161 | #ifndef PRODUCT |
| 1162 | void indIndexOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 1163 | st->print_raw("["); |
| 1164 | { char reg_str[128]; |
| 1165 | ra->dump_register(node,reg_str); |
| 1166 | st->print("%s",reg_str); |
| 1167 | } |
| 1168 | st->print_raw(" + "); |
| 1169 | { char reg_str[128]; |
| 1170 | ra->dump_register(node,reg_str); |
| 1171 | st->print("%s",reg_str); |
| 1172 | } |
| 1173 | st->print_raw("]"); |
| 1174 | } |
| 1175 | void indIndexOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 1176 | st->print_raw("["); |
| 1177 | { char reg_str[128]; |
| 1178 | ra->dump_register(node->in(idx),reg_str); |
| 1179 | st->print("%s",reg_str); |
| 1180 | } |
| 1181 | st->print_raw(" + "); |
| 1182 | { char reg_str[128]; |
| 1183 | ra->dump_register(node->in(idx+1),reg_str); |
| 1184 | st->print("%s",reg_str); |
| 1185 | } |
| 1186 | st->print_raw("]"); |
| 1187 | } |
| 1188 | #endif |
| 1189 | |
| 1190 | #ifndef PRODUCT |
| 1191 | void indIndexScaleOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 1192 | st->print_raw("["); |
| 1193 | { char reg_str[128]; |
| 1194 | ra->dump_register(node,reg_str); |
| 1195 | st->print("%s",reg_str); |
| 1196 | } |
| 1197 | st->print_raw(" + "); |
| 1198 | { char reg_str[128]; |
| 1199 | ra->dump_register(node,reg_str); |
| 1200 | st->print("%s",reg_str); |
| 1201 | } |
| 1202 | st->print_raw(" << "); |
| 1203 | st->print("#%d", _c0); |
| 1204 | st->print_raw("]"); |
| 1205 | } |
| 1206 | void indIndexScaleOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 1207 | st->print_raw("["); |
| 1208 | { char reg_str[128]; |
| 1209 | ra->dump_register(node->in(idx),reg_str); |
| 1210 | st->print("%s",reg_str); |
| 1211 | } |
| 1212 | st->print_raw(" + "); |
| 1213 | { char reg_str[128]; |
| 1214 | ra->dump_register(node->in(idx+1),reg_str); |
| 1215 | st->print("%s",reg_str); |
| 1216 | } |
| 1217 | st->print_raw(" << "); |
| 1218 | st->print("#%d", _c0); |
| 1219 | st->print_raw("]"); |
| 1220 | } |
| 1221 | #endif |
| 1222 | |
| 1223 | #ifndef PRODUCT |
| 1224 | void indPosIndexScaleOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 1225 | st->print_raw("["); |
| 1226 | { char reg_str[128]; |
| 1227 | ra->dump_register(node,reg_str); |
| 1228 | st->print("%s",reg_str); |
| 1229 | } |
| 1230 | st->print_raw(" + pos "); |
| 1231 | { char reg_str[128]; |
| 1232 | ra->dump_register(node,reg_str); |
| 1233 | st->print("%s",reg_str); |
| 1234 | } |
| 1235 | st->print_raw(" << "); |
| 1236 | st->print("#%d", _c0); |
| 1237 | st->print_raw("]"); |
| 1238 | } |
| 1239 | void indPosIndexScaleOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 1240 | st->print_raw("["); |
| 1241 | { char reg_str[128]; |
| 1242 | ra->dump_register(node->in(idx),reg_str); |
| 1243 | st->print("%s",reg_str); |
| 1244 | } |
| 1245 | st->print_raw(" + pos "); |
| 1246 | { char reg_str[128]; |
| 1247 | ra->dump_register(node->in(idx+1),reg_str); |
| 1248 | st->print("%s",reg_str); |
| 1249 | } |
| 1250 | st->print_raw(" << "); |
| 1251 | st->print("#%d", _c0); |
| 1252 | st->print_raw("]"); |
| 1253 | } |
| 1254 | #endif |
| 1255 | |
| 1256 | #ifndef PRODUCT |
| 1257 | void indIndexScaleOffsetOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 1258 | st->print_raw("["); |
| 1259 | { char reg_str[128]; |
| 1260 | ra->dump_register(node,reg_str); |
| 1261 | st->print("%s",reg_str); |
| 1262 | } |
| 1263 | st->print_raw(" + "); |
| 1264 | st->print("#" INT64_FORMAT"%" "l" "d", (int64_t)_c1); |
| 1265 | st->print_raw(" + "); |
| 1266 | { char reg_str[128]; |
| 1267 | ra->dump_register(node,reg_str); |
| 1268 | st->print("%s",reg_str); |
| 1269 | } |
| 1270 | st->print_raw(" << "); |
| 1271 | st->print("#%d", _c0); |
| 1272 | st->print_raw("]"); |
| 1273 | } |
| 1274 | void indIndexScaleOffsetOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 1275 | st->print_raw("["); |
| 1276 | { char reg_str[128]; |
| 1277 | ra->dump_register(node->in(idx),reg_str); |
| 1278 | st->print("%s",reg_str); |
| 1279 | } |
| 1280 | st->print_raw(" + "); |
| 1281 | st->print("#" INT64_FORMAT"%" "l" "d", (int64_t)_c1); |
| 1282 | st->print_raw(" + "); |
| 1283 | { char reg_str[128]; |
| 1284 | ra->dump_register(node->in(idx+1),reg_str); |
| 1285 | st->print("%s",reg_str); |
| 1286 | } |
| 1287 | st->print_raw(" << "); |
| 1288 | st->print("#%d", _c0); |
| 1289 | st->print_raw("]"); |
| 1290 | } |
| 1291 | #endif |
| 1292 | |
| 1293 | #ifndef PRODUCT |
| 1294 | void indPosIndexOffsetOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 1295 | st->print_raw("["); |
| 1296 | { char reg_str[128]; |
| 1297 | ra->dump_register(node,reg_str); |
| 1298 | st->print("%s",reg_str); |
| 1299 | } |
| 1300 | st->print_raw(" + "); |
| 1301 | st->print("#" INT64_FORMAT"%" "l" "d", (int64_t)_c0); |
| 1302 | st->print_raw(" + "); |
| 1303 | { char reg_str[128]; |
| 1304 | ra->dump_register(node,reg_str); |
| 1305 | st->print("%s",reg_str); |
| 1306 | } |
| 1307 | st->print_raw("]"); |
| 1308 | } |
| 1309 | void indPosIndexOffsetOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 1310 | st->print_raw("["); |
| 1311 | { char reg_str[128]; |
| 1312 | ra->dump_register(node->in(idx),reg_str); |
| 1313 | st->print("%s",reg_str); |
| 1314 | } |
| 1315 | st->print_raw(" + "); |
| 1316 | st->print("#" INT64_FORMAT"%" "l" "d", (int64_t)_c0); |
| 1317 | st->print_raw(" + "); |
| 1318 | { char reg_str[128]; |
| 1319 | ra->dump_register(node->in(idx+1),reg_str); |
| 1320 | st->print("%s",reg_str); |
| 1321 | } |
| 1322 | st->print_raw("]"); |
| 1323 | } |
| 1324 | #endif |
| 1325 | |
| 1326 | #ifndef PRODUCT |
| 1327 | void indPosIndexScaleOffsetOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 1328 | st->print_raw("["); |
| 1329 | { char reg_str[128]; |
| 1330 | ra->dump_register(node,reg_str); |
| 1331 | st->print("%s",reg_str); |
| 1332 | } |
| 1333 | st->print_raw(" + "); |
| 1334 | st->print("#" INT64_FORMAT"%" "l" "d", (int64_t)_c1); |
| 1335 | st->print_raw(" + "); |
| 1336 | { char reg_str[128]; |
| 1337 | ra->dump_register(node,reg_str); |
| 1338 | st->print("%s",reg_str); |
| 1339 | } |
| 1340 | st->print_raw(" << "); |
| 1341 | st->print("#%d", _c0); |
| 1342 | st->print_raw("]"); |
| 1343 | } |
| 1344 | void indPosIndexScaleOffsetOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 1345 | st->print_raw("["); |
| 1346 | { char reg_str[128]; |
| 1347 | ra->dump_register(node->in(idx),reg_str); |
| 1348 | st->print("%s",reg_str); |
| 1349 | } |
| 1350 | st->print_raw(" + "); |
| 1351 | st->print("#" INT64_FORMAT"%" "l" "d", (int64_t)_c1); |
| 1352 | st->print_raw(" + "); |
| 1353 | { char reg_str[128]; |
| 1354 | ra->dump_register(node->in(idx+1),reg_str); |
| 1355 | st->print("%s",reg_str); |
| 1356 | } |
| 1357 | st->print_raw(" << "); |
| 1358 | st->print("#%d", _c0); |
| 1359 | st->print_raw("]"); |
| 1360 | } |
| 1361 | #endif |
| 1362 | |
| 1363 | #ifndef PRODUCT |
| 1364 | void indCompressedOopOffsetOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 1365 | st->print_raw("[R12 + "); |
| 1366 | { char reg_str[128]; |
| 1367 | ra->dump_register(node,reg_str); |
| 1368 | st->print("%s",reg_str); |
| 1369 | } |
| 1370 | st->print_raw(" << 3 + "); |
| 1371 | st->print("#" INT64_FORMAT"%" "l" "d", (int64_t)_c0); |
| 1372 | st->print_raw("] (compressed oop addressing)"); |
| 1373 | } |
| 1374 | void indCompressedOopOffsetOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 1375 | st->print_raw("[R12 + "); |
| 1376 | { char reg_str[128]; |
| 1377 | ra->dump_register(node->in(idx),reg_str); |
| 1378 | st->print("%s",reg_str); |
| 1379 | } |
| 1380 | st->print_raw(" << 3 + "); |
| 1381 | st->print("#" INT64_FORMAT"%" "l" "d", (int64_t)_c0); |
| 1382 | st->print_raw("] (compressed oop addressing)"); |
| 1383 | } |
| 1384 | #endif |
| 1385 | |
| 1386 | #ifndef PRODUCT |
| 1387 | void indirectNarrowOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 1388 | st->print_raw("["); |
| 1389 | { char reg_str[128]; |
| 1390 | ra->dump_register(node,reg_str); |
| 1391 | st->print("%s",reg_str); |
| 1392 | } |
| 1393 | st->print_raw("]"); |
| 1394 | } |
| 1395 | void indirectNarrowOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 1396 | st->print_raw("["); |
| 1397 | { char reg_str[128]; |
| 1398 | ra->dump_register(node->in(idx),reg_str); |
| 1399 | st->print("%s",reg_str); |
| 1400 | } |
| 1401 | st->print_raw("]"); |
| 1402 | } |
| 1403 | #endif |
| 1404 | |
| 1405 | #ifndef PRODUCT |
| 1406 | void indOffset8NarrowOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 1407 | st->print_raw("["); |
| 1408 | { char reg_str[128]; |
| 1409 | ra->dump_register(node,reg_str); |
| 1410 | st->print("%s",reg_str); |
| 1411 | } |
| 1412 | st->print_raw(" + "); |
| 1413 | st->print("#" INT64_FORMAT"%" "l" "d", (int64_t)_c0); |
| 1414 | st->print_raw(" (8-bit)]"); |
| 1415 | } |
| 1416 | void indOffset8NarrowOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 1417 | st->print_raw("["); |
| 1418 | { char reg_str[128]; |
| 1419 | ra->dump_register(node->in(idx),reg_str); |
| 1420 | st->print("%s",reg_str); |
| 1421 | } |
| 1422 | st->print_raw(" + "); |
| 1423 | st->print("#" INT64_FORMAT"%" "l" "d", (int64_t)_c0); |
| 1424 | st->print_raw(" (8-bit)]"); |
| 1425 | } |
| 1426 | #endif |
| 1427 | |
| 1428 | #ifndef PRODUCT |
| 1429 | void indOffset32NarrowOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 1430 | st->print_raw("["); |
| 1431 | { char reg_str[128]; |
| 1432 | ra->dump_register(node,reg_str); |
| 1433 | st->print("%s",reg_str); |
| 1434 | } |
| 1435 | st->print_raw(" + "); |
| 1436 | st->print("#" INT64_FORMAT"%" "l" "d", (int64_t)_c0); |
| 1437 | st->print_raw(" (32-bit)]"); |
| 1438 | } |
| 1439 | void indOffset32NarrowOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 1440 | st->print_raw("["); |
| 1441 | { char reg_str[128]; |
| 1442 | ra->dump_register(node->in(idx),reg_str); |
| 1443 | st->print("%s",reg_str); |
| 1444 | } |
| 1445 | st->print_raw(" + "); |
| 1446 | st->print("#" INT64_FORMAT"%" "l" "d", (int64_t)_c0); |
| 1447 | st->print_raw(" (32-bit)]"); |
| 1448 | } |
| 1449 | #endif |
| 1450 | |
| 1451 | #ifndef PRODUCT |
| 1452 | void indIndexOffsetNarrowOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 1453 | st->print_raw("["); |
| 1454 | { char reg_str[128]; |
| 1455 | ra->dump_register(node,reg_str); |
| 1456 | st->print("%s",reg_str); |
| 1457 | } |
| 1458 | st->print_raw(" + "); |
| 1459 | st->print("#" INT64_FORMAT"%" "l" "d", (int64_t)_c0); |
| 1460 | st->print_raw(" + "); |
| 1461 | { char reg_str[128]; |
| 1462 | ra->dump_register(node,reg_str); |
| 1463 | st->print("%s",reg_str); |
| 1464 | } |
| 1465 | st->print_raw("]"); |
| 1466 | } |
| 1467 | void indIndexOffsetNarrowOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 1468 | st->print_raw("["); |
| 1469 | { char reg_str[128]; |
| 1470 | ra->dump_register(node->in(idx),reg_str); |
| 1471 | st->print("%s",reg_str); |
| 1472 | } |
| 1473 | st->print_raw(" + "); |
| 1474 | st->print("#" INT64_FORMAT"%" "l" "d", (int64_t)_c0); |
| 1475 | st->print_raw(" + "); |
| 1476 | { char reg_str[128]; |
| 1477 | ra->dump_register(node->in(idx+1),reg_str); |
| 1478 | st->print("%s",reg_str); |
| 1479 | } |
| 1480 | st->print_raw("]"); |
| 1481 | } |
| 1482 | #endif |
| 1483 | |
| 1484 | #ifndef PRODUCT |
| 1485 | void indIndexNarrowOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 1486 | st->print_raw("["); |
| 1487 | { char reg_str[128]; |
| 1488 | ra->dump_register(node,reg_str); |
| 1489 | st->print("%s",reg_str); |
| 1490 | } |
| 1491 | st->print_raw(" + "); |
| 1492 | { char reg_str[128]; |
| 1493 | ra->dump_register(node,reg_str); |
| 1494 | st->print("%s",reg_str); |
| 1495 | } |
| 1496 | st->print_raw("]"); |
| 1497 | } |
| 1498 | void indIndexNarrowOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 1499 | st->print_raw("["); |
| 1500 | { char reg_str[128]; |
| 1501 | ra->dump_register(node->in(idx),reg_str); |
| 1502 | st->print("%s",reg_str); |
| 1503 | } |
| 1504 | st->print_raw(" + "); |
| 1505 | { char reg_str[128]; |
| 1506 | ra->dump_register(node->in(idx+1),reg_str); |
| 1507 | st->print("%s",reg_str); |
| 1508 | } |
| 1509 | st->print_raw("]"); |
| 1510 | } |
| 1511 | #endif |
| 1512 | |
| 1513 | #ifndef PRODUCT |
| 1514 | void indIndexScaleNarrowOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 1515 | st->print_raw("["); |
| 1516 | { char reg_str[128]; |
| 1517 | ra->dump_register(node,reg_str); |
| 1518 | st->print("%s",reg_str); |
| 1519 | } |
| 1520 | st->print_raw(" + "); |
| 1521 | { char reg_str[128]; |
| 1522 | ra->dump_register(node,reg_str); |
| 1523 | st->print("%s",reg_str); |
| 1524 | } |
| 1525 | st->print_raw(" << "); |
| 1526 | st->print("#%d", _c0); |
| 1527 | st->print_raw("]"); |
| 1528 | } |
| 1529 | void indIndexScaleNarrowOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 1530 | st->print_raw("["); |
| 1531 | { char reg_str[128]; |
| 1532 | ra->dump_register(node->in(idx),reg_str); |
| 1533 | st->print("%s",reg_str); |
| 1534 | } |
| 1535 | st->print_raw(" + "); |
| 1536 | { char reg_str[128]; |
| 1537 | ra->dump_register(node->in(idx+1),reg_str); |
| 1538 | st->print("%s",reg_str); |
| 1539 | } |
| 1540 | st->print_raw(" << "); |
| 1541 | st->print("#%d", _c0); |
| 1542 | st->print_raw("]"); |
| 1543 | } |
| 1544 | #endif |
| 1545 | |
| 1546 | #ifndef PRODUCT |
| 1547 | void indIndexScaleOffsetNarrowOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 1548 | st->print_raw("["); |
| 1549 | { char reg_str[128]; |
| 1550 | ra->dump_register(node,reg_str); |
| 1551 | st->print("%s",reg_str); |
| 1552 | } |
| 1553 | st->print_raw(" + "); |
| 1554 | st->print("#" INT64_FORMAT"%" "l" "d", (int64_t)_c1); |
| 1555 | st->print_raw(" + "); |
| 1556 | { char reg_str[128]; |
| 1557 | ra->dump_register(node,reg_str); |
| 1558 | st->print("%s",reg_str); |
| 1559 | } |
| 1560 | st->print_raw(" << "); |
| 1561 | st->print("#%d", _c0); |
| 1562 | st->print_raw("]"); |
| 1563 | } |
| 1564 | void indIndexScaleOffsetNarrowOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 1565 | st->print_raw("["); |
| 1566 | { char reg_str[128]; |
| 1567 | ra->dump_register(node->in(idx),reg_str); |
| 1568 | st->print("%s",reg_str); |
| 1569 | } |
| 1570 | st->print_raw(" + "); |
| 1571 | st->print("#" INT64_FORMAT"%" "l" "d", (int64_t)_c1); |
| 1572 | st->print_raw(" + "); |
| 1573 | { char reg_str[128]; |
| 1574 | ra->dump_register(node->in(idx+1),reg_str); |
| 1575 | st->print("%s",reg_str); |
| 1576 | } |
| 1577 | st->print_raw(" << "); |
| 1578 | st->print("#%d", _c0); |
| 1579 | st->print_raw("]"); |
| 1580 | } |
| 1581 | #endif |
| 1582 | |
| 1583 | #ifndef PRODUCT |
| 1584 | void indPosIndexOffsetNarrowOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 1585 | st->print_raw("["); |
| 1586 | { char reg_str[128]; |
| 1587 | ra->dump_register(node,reg_str); |
| 1588 | st->print("%s",reg_str); |
| 1589 | } |
| 1590 | st->print_raw(" + "); |
| 1591 | st->print("#" INT64_FORMAT"%" "l" "d", (int64_t)_c0); |
| 1592 | st->print_raw(" + "); |
| 1593 | { char reg_str[128]; |
| 1594 | ra->dump_register(node,reg_str); |
| 1595 | st->print("%s",reg_str); |
| 1596 | } |
| 1597 | st->print_raw("]"); |
| 1598 | } |
| 1599 | void indPosIndexOffsetNarrowOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 1600 | st->print_raw("["); |
| 1601 | { char reg_str[128]; |
| 1602 | ra->dump_register(node->in(idx),reg_str); |
| 1603 | st->print("%s",reg_str); |
| 1604 | } |
| 1605 | st->print_raw(" + "); |
| 1606 | st->print("#" INT64_FORMAT"%" "l" "d", (int64_t)_c0); |
| 1607 | st->print_raw(" + "); |
| 1608 | { char reg_str[128]; |
| 1609 | ra->dump_register(node->in(idx+1),reg_str); |
| 1610 | st->print("%s",reg_str); |
| 1611 | } |
| 1612 | st->print_raw("]"); |
| 1613 | } |
| 1614 | #endif |
| 1615 | |
| 1616 | #ifndef PRODUCT |
| 1617 | void indPosIndexScaleOffsetNarrowOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 1618 | st->print_raw("["); |
| 1619 | { char reg_str[128]; |
| 1620 | ra->dump_register(node,reg_str); |
| 1621 | st->print("%s",reg_str); |
| 1622 | } |
| 1623 | st->print_raw(" + "); |
| 1624 | st->print("#" INT64_FORMAT"%" "l" "d", (int64_t)_c1); |
| 1625 | st->print_raw(" + "); |
| 1626 | { char reg_str[128]; |
| 1627 | ra->dump_register(node,reg_str); |
| 1628 | st->print("%s",reg_str); |
| 1629 | } |
| 1630 | st->print_raw(" << "); |
| 1631 | st->print("#%d", _c0); |
| 1632 | st->print_raw("]"); |
| 1633 | } |
| 1634 | void indPosIndexScaleOffsetNarrowOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 1635 | st->print_raw("["); |
| 1636 | { char reg_str[128]; |
| 1637 | ra->dump_register(node->in(idx),reg_str); |
| 1638 | st->print("%s",reg_str); |
| 1639 | } |
| 1640 | st->print_raw(" + "); |
| 1641 | st->print("#" INT64_FORMAT"%" "l" "d", (int64_t)_c1); |
| 1642 | st->print_raw(" + "); |
| 1643 | { char reg_str[128]; |
| 1644 | ra->dump_register(node->in(idx+1),reg_str); |
| 1645 | st->print("%s",reg_str); |
| 1646 | } |
| 1647 | st->print_raw(" << "); |
| 1648 | st->print("#%d", _c0); |
| 1649 | st->print_raw("]"); |
| 1650 | } |
| 1651 | #endif |
| 1652 | |
| 1653 | #ifndef PRODUCT |
| 1654 | void stackSlotPOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 1655 | st->print_raw("["); |
| 1656 | { char reg_str[128]; |
| 1657 | ra->dump_register(node,reg_str); |
| 1658 | st->print("%s",reg_str); |
| 1659 | } |
| 1660 | st->print_raw("]"); |
| 1661 | } |
| 1662 | void stackSlotPOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 1663 | st->print_raw("["); |
| 1664 | { char reg_str[128]; |
| 1665 | ra->dump_register(node->in(idx),reg_str); |
| 1666 | st->print("%s",reg_str); |
| 1667 | } |
| 1668 | st->print_raw("]"); |
| 1669 | } |
| 1670 | #endif |
| 1671 | |
| 1672 | #ifndef PRODUCT |
| 1673 | void stackSlotIOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 1674 | st->print_raw("["); |
| 1675 | { char reg_str[128]; |
| 1676 | ra->dump_register(node,reg_str); |
| 1677 | st->print("%s",reg_str); |
| 1678 | } |
| 1679 | st->print_raw("]"); |
| 1680 | } |
| 1681 | void stackSlotIOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 1682 | st->print_raw("["); |
| 1683 | { char reg_str[128]; |
| 1684 | ra->dump_register(node->in(idx),reg_str); |
| 1685 | st->print("%s",reg_str); |
| 1686 | } |
| 1687 | st->print_raw("]"); |
| 1688 | } |
| 1689 | #endif |
| 1690 | |
| 1691 | #ifndef PRODUCT |
| 1692 | void stackSlotFOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 1693 | st->print_raw("["); |
| 1694 | { char reg_str[128]; |
| 1695 | ra->dump_register(node,reg_str); |
| 1696 | st->print("%s",reg_str); |
| 1697 | } |
| 1698 | st->print_raw("]"); |
| 1699 | } |
| 1700 | void stackSlotFOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 1701 | st->print_raw("["); |
| 1702 | { char reg_str[128]; |
| 1703 | ra->dump_register(node->in(idx),reg_str); |
| 1704 | st->print("%s",reg_str); |
| 1705 | } |
| 1706 | st->print_raw("]"); |
| 1707 | } |
| 1708 | #endif |
| 1709 | |
| 1710 | #ifndef PRODUCT |
| 1711 | void stackSlotDOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 1712 | st->print_raw("["); |
| 1713 | { char reg_str[128]; |
| 1714 | ra->dump_register(node,reg_str); |
| 1715 | st->print("%s",reg_str); |
| 1716 | } |
| 1717 | st->print_raw("]"); |
| 1718 | } |
| 1719 | void stackSlotDOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 1720 | st->print_raw("["); |
| 1721 | { char reg_str[128]; |
| 1722 | ra->dump_register(node->in(idx),reg_str); |
| 1723 | st->print("%s",reg_str); |
| 1724 | } |
| 1725 | st->print_raw("]"); |
| 1726 | } |
| 1727 | #endif |
| 1728 | |
| 1729 | #ifndef PRODUCT |
| 1730 | void stackSlotLOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 1731 | st->print_raw("["); |
| 1732 | { char reg_str[128]; |
| 1733 | ra->dump_register(node,reg_str); |
| 1734 | st->print("%s",reg_str); |
| 1735 | } |
| 1736 | st->print_raw("]"); |
| 1737 | } |
| 1738 | void stackSlotLOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 1739 | st->print_raw("["); |
| 1740 | { char reg_str[128]; |
| 1741 | ra->dump_register(node->in(idx),reg_str); |
| 1742 | st->print("%s",reg_str); |
| 1743 | } |
| 1744 | st->print_raw("]"); |
| 1745 | } |
| 1746 | #endif |
| 1747 | |
| 1748 | #ifndef PRODUCT |
| 1749 | void cmpOpOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 1750 | st->print_raw(""); |
| 1751 | if( _c0 == BoolTest::eq ) st->print_raw("e"); |
| 1752 | else if( _c0 == BoolTest::ne ) st->print_raw("ne"); |
| 1753 | else if( _c0 == BoolTest::le ) st->print_raw("le"); |
| 1754 | else if( _c0 == BoolTest::ge ) st->print_raw("ge"); |
| 1755 | else if( _c0 == BoolTest::lt ) st->print_raw("l"); |
| 1756 | else if( _c0 == BoolTest::gt ) st->print_raw("g"); |
| 1757 | else if( _c0 == BoolTest::overflow ) st->print_raw("o"); |
| 1758 | else if( _c0 == BoolTest::no_overflow ) st->print_raw("no"); |
| 1759 | } |
| 1760 | void cmpOpOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 1761 | st->print_raw(""); |
| 1762 | if( _c0 == BoolTest::eq ) st->print_raw("e"); |
| 1763 | else if( _c0 == BoolTest::ne ) st->print_raw("ne"); |
| 1764 | else if( _c0 == BoolTest::le ) st->print_raw("le"); |
| 1765 | else if( _c0 == BoolTest::ge ) st->print_raw("ge"); |
| 1766 | else if( _c0 == BoolTest::lt ) st->print_raw("l"); |
| 1767 | else if( _c0 == BoolTest::gt ) st->print_raw("g"); |
| 1768 | else if( _c0 == BoolTest::overflow ) st->print_raw("o"); |
| 1769 | else if( _c0 == BoolTest::no_overflow ) st->print_raw("no"); |
| 1770 | } |
| 1771 | #endif |
| 1772 | |
| 1773 | #ifndef PRODUCT |
| 1774 | void cmpOpUOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 1775 | st->print_raw(""); |
| 1776 | if( _c0 == BoolTest::eq ) st->print_raw("e"); |
| 1777 | else if( _c0 == BoolTest::ne ) st->print_raw("ne"); |
| 1778 | else if( _c0 == BoolTest::le ) st->print_raw("be"); |
| 1779 | else if( _c0 == BoolTest::ge ) st->print_raw("nb"); |
| 1780 | else if( _c0 == BoolTest::lt ) st->print_raw("b"); |
| 1781 | else if( _c0 == BoolTest::gt ) st->print_raw("nbe"); |
| 1782 | else if( _c0 == BoolTest::overflow ) st->print_raw("o"); |
| 1783 | else if( _c0 == BoolTest::no_overflow ) st->print_raw("no"); |
| 1784 | } |
| 1785 | void cmpOpUOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 1786 | st->print_raw(""); |
| 1787 | if( _c0 == BoolTest::eq ) st->print_raw("e"); |
| 1788 | else if( _c0 == BoolTest::ne ) st->print_raw("ne"); |
| 1789 | else if( _c0 == BoolTest::le ) st->print_raw("be"); |
| 1790 | else if( _c0 == BoolTest::ge ) st->print_raw("nb"); |
| 1791 | else if( _c0 == BoolTest::lt ) st->print_raw("b"); |
| 1792 | else if( _c0 == BoolTest::gt ) st->print_raw("nbe"); |
| 1793 | else if( _c0 == BoolTest::overflow ) st->print_raw("o"); |
| 1794 | else if( _c0 == BoolTest::no_overflow ) st->print_raw("no"); |
| 1795 | } |
| 1796 | #endif |
| 1797 | |
| 1798 | #ifndef PRODUCT |
| 1799 | void cmpOpUCFOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 1800 | st->print_raw(""); |
| 1801 | if( _c0 == BoolTest::eq ) st->print_raw("e"); |
| 1802 | else if( _c0 == BoolTest::ne ) st->print_raw("ne"); |
| 1803 | else if( _c0 == BoolTest::le ) st->print_raw("be"); |
| 1804 | else if( _c0 == BoolTest::ge ) st->print_raw("nb"); |
| 1805 | else if( _c0 == BoolTest::lt ) st->print_raw("b"); |
| 1806 | else if( _c0 == BoolTest::gt ) st->print_raw("nbe"); |
| 1807 | else if( _c0 == BoolTest::overflow ) st->print_raw("o"); |
| 1808 | else if( _c0 == BoolTest::no_overflow ) st->print_raw("no"); |
| 1809 | } |
| 1810 | void cmpOpUCFOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 1811 | st->print_raw(""); |
| 1812 | if( _c0 == BoolTest::eq ) st->print_raw("e"); |
| 1813 | else if( _c0 == BoolTest::ne ) st->print_raw("ne"); |
| 1814 | else if( _c0 == BoolTest::le ) st->print_raw("be"); |
| 1815 | else if( _c0 == BoolTest::ge ) st->print_raw("nb"); |
| 1816 | else if( _c0 == BoolTest::lt ) st->print_raw("b"); |
| 1817 | else if( _c0 == BoolTest::gt ) st->print_raw("nbe"); |
| 1818 | else if( _c0 == BoolTest::overflow ) st->print_raw("o"); |
| 1819 | else if( _c0 == BoolTest::no_overflow ) st->print_raw("no"); |
| 1820 | } |
| 1821 | #endif |
| 1822 | |
| 1823 | #ifndef PRODUCT |
| 1824 | void cmpOpUCF2Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 1825 | st->print_raw(""); |
| 1826 | if( _c0 == BoolTest::eq ) st->print_raw("e"); |
| 1827 | else if( _c0 == BoolTest::ne ) st->print_raw("ne"); |
| 1828 | else if( _c0 == BoolTest::le ) st->print_raw("be"); |
| 1829 | else if( _c0 == BoolTest::ge ) st->print_raw("nb"); |
| 1830 | else if( _c0 == BoolTest::lt ) st->print_raw("b"); |
| 1831 | else if( _c0 == BoolTest::gt ) st->print_raw("nbe"); |
| 1832 | else if( _c0 == BoolTest::overflow ) st->print_raw("o"); |
| 1833 | else if( _c0 == BoolTest::no_overflow ) st->print_raw("no"); |
| 1834 | } |
| 1835 | void cmpOpUCF2Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 1836 | st->print_raw(""); |
| 1837 | if( _c0 == BoolTest::eq ) st->print_raw("e"); |
| 1838 | else if( _c0 == BoolTest::ne ) st->print_raw("ne"); |
| 1839 | else if( _c0 == BoolTest::le ) st->print_raw("be"); |
| 1840 | else if( _c0 == BoolTest::ge ) st->print_raw("nb"); |
| 1841 | else if( _c0 == BoolTest::lt ) st->print_raw("b"); |
| 1842 | else if( _c0 == BoolTest::gt ) st->print_raw("nbe"); |
| 1843 | else if( _c0 == BoolTest::overflow ) st->print_raw("o"); |
| 1844 | else if( _c0 == BoolTest::no_overflow ) st->print_raw("no"); |
| 1845 | } |
| 1846 | #endif |
| 1847 | |
| 1848 | #ifndef PRODUCT |
| 1849 | void rxmm0Oper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 1850 | { char reg_str[128]; |
| 1851 | ra->dump_register(node,reg_str); |
| 1852 | st->print("%s",reg_str); |
| 1853 | } |
| 1854 | } |
| 1855 | void rxmm0Oper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 1856 | { char reg_str[128]; |
| 1857 | ra->dump_register(node->in(idx),reg_str); |
| 1858 | st->print("%s",reg_str); |
| 1859 | } |
| 1860 | } |
| 1861 | #endif |
| 1862 | |
| 1863 | #ifndef PRODUCT |
| 1864 | void vecOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 1865 | { char reg_str[128]; |
| 1866 | ra->dump_register(node,reg_str); |
| 1867 | st->print("%s",reg_str); |
| 1868 | } |
| 1869 | } |
| 1870 | void vecOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 1871 | { char reg_str[128]; |
| 1872 | ra->dump_register(node->in(idx),reg_str); |
| 1873 | st->print("%s",reg_str); |
| 1874 | } |
| 1875 | } |
| 1876 | #endif |
| 1877 | |
| 1878 | #ifndef PRODUCT |
| 1879 | void legVecOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 1880 | { char reg_str[128]; |
| 1881 | ra->dump_register(node,reg_str); |
| 1882 | st->print("%s",reg_str); |
| 1883 | } |
| 1884 | } |
| 1885 | void legVecOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 1886 | { char reg_str[128]; |
| 1887 | ra->dump_register(node->in(idx),reg_str); |
| 1888 | st->print("%s",reg_str); |
| 1889 | } |
| 1890 | } |
| 1891 | #endif |
| 1892 | |
| 1893 | #ifndef PRODUCT |
| 1894 | void vecSOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 1895 | { char reg_str[128]; |
| 1896 | ra->dump_register(node,reg_str); |
| 1897 | st->print("%s",reg_str); |
| 1898 | } |
| 1899 | } |
| 1900 | void vecSOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 1901 | { char reg_str[128]; |
| 1902 | ra->dump_register(node->in(idx),reg_str); |
| 1903 | st->print("%s",reg_str); |
| 1904 | } |
| 1905 | } |
| 1906 | #endif |
| 1907 | |
| 1908 | #ifndef PRODUCT |
| 1909 | void legVecSOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 1910 | { char reg_str[128]; |
| 1911 | ra->dump_register(node,reg_str); |
| 1912 | st->print("%s",reg_str); |
| 1913 | } |
| 1914 | } |
| 1915 | void legVecSOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 1916 | { char reg_str[128]; |
| 1917 | ra->dump_register(node->in(idx),reg_str); |
| 1918 | st->print("%s",reg_str); |
| 1919 | } |
| 1920 | } |
| 1921 | #endif |
| 1922 | |
| 1923 | #ifndef PRODUCT |
| 1924 | void vecDOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 1925 | { char reg_str[128]; |
| 1926 | ra->dump_register(node,reg_str); |
| 1927 | st->print("%s",reg_str); |
| 1928 | } |
| 1929 | } |
| 1930 | void vecDOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 1931 | { char reg_str[128]; |
| 1932 | ra->dump_register(node->in(idx),reg_str); |
| 1933 | st->print("%s",reg_str); |
| 1934 | } |
| 1935 | } |
| 1936 | #endif |
| 1937 | |
| 1938 | #ifndef PRODUCT |
| 1939 | void legVecDOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 1940 | { char reg_str[128]; |
| 1941 | ra->dump_register(node,reg_str); |
| 1942 | st->print("%s",reg_str); |
| 1943 | } |
| 1944 | } |
| 1945 | void legVecDOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 1946 | { char reg_str[128]; |
| 1947 | ra->dump_register(node->in(idx),reg_str); |
| 1948 | st->print("%s",reg_str); |
| 1949 | } |
| 1950 | } |
| 1951 | #endif |
| 1952 | |
| 1953 | #ifndef PRODUCT |
| 1954 | void vecXOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 1955 | { char reg_str[128]; |
| 1956 | ra->dump_register(node,reg_str); |
| 1957 | st->print("%s",reg_str); |
| 1958 | } |
| 1959 | } |
| 1960 | void vecXOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 1961 | { char reg_str[128]; |
| 1962 | ra->dump_register(node->in(idx),reg_str); |
| 1963 | st->print("%s",reg_str); |
| 1964 | } |
| 1965 | } |
| 1966 | #endif |
| 1967 | |
| 1968 | #ifndef PRODUCT |
| 1969 | void legVecXOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 1970 | { char reg_str[128]; |
| 1971 | ra->dump_register(node,reg_str); |
| 1972 | st->print("%s",reg_str); |
| 1973 | } |
| 1974 | } |
| 1975 | void legVecXOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 1976 | { char reg_str[128]; |
| 1977 | ra->dump_register(node->in(idx),reg_str); |
| 1978 | st->print("%s",reg_str); |
| 1979 | } |
| 1980 | } |
| 1981 | #endif |
| 1982 | |
| 1983 | #ifndef PRODUCT |
| 1984 | void vecYOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 1985 | { char reg_str[128]; |
| 1986 | ra->dump_register(node,reg_str); |
| 1987 | st->print("%s",reg_str); |
| 1988 | } |
| 1989 | } |
| 1990 | void vecYOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 1991 | { char reg_str[128]; |
| 1992 | ra->dump_register(node->in(idx),reg_str); |
| 1993 | st->print("%s",reg_str); |
| 1994 | } |
| 1995 | } |
| 1996 | #endif |
| 1997 | |
| 1998 | #ifndef PRODUCT |
| 1999 | void legVecYOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 2000 | { char reg_str[128]; |
| 2001 | ra->dump_register(node,reg_str); |
| 2002 | st->print("%s",reg_str); |
| 2003 | } |
| 2004 | } |
| 2005 | void legVecYOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 2006 | { char reg_str[128]; |
| 2007 | ra->dump_register(node->in(idx),reg_str); |
| 2008 | st->print("%s",reg_str); |
| 2009 | } |
| 2010 | } |
| 2011 | #endif |
| 2012 | |
| 2013 | #ifndef PRODUCT |
| 2014 | void vecZOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 2015 | { char reg_str[128]; |
| 2016 | ra->dump_register(node,reg_str); |
| 2017 | st->print("%s",reg_str); |
| 2018 | } |
| 2019 | } |
| 2020 | void vecZOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 2021 | { char reg_str[128]; |
| 2022 | ra->dump_register(node->in(idx),reg_str); |
| 2023 | st->print("%s",reg_str); |
| 2024 | } |
| 2025 | } |
| 2026 | #endif |
| 2027 | |
| 2028 | #ifndef PRODUCT |
| 2029 | void legVecZOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 2030 | { char reg_str[128]; |
| 2031 | ra->dump_register(node,reg_str); |
| 2032 | st->print("%s",reg_str); |
| 2033 | } |
| 2034 | } |
| 2035 | void legVecZOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 2036 | { char reg_str[128]; |
| 2037 | ra->dump_register(node->in(idx),reg_str); |
| 2038 | st->print("%s",reg_str); |
| 2039 | } |
| 2040 | } |
| 2041 | #endif |
| 2042 | |
| 2043 | #ifndef PRODUCT |
| 2044 | void cmpOp_vcmppdOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { |
| 2045 | st->print_raw(""); |
| 2046 | if( _c0 == BoolTest::eq ) st->print_raw("eq"); |
| 2047 | else if( _c0 == BoolTest::ne ) st->print_raw("ne"); |
| 2048 | else if( _c0 == BoolTest::le ) st->print_raw("le"); |
| 2049 | else if( _c0 == BoolTest::ge ) st->print_raw("ge"); |
| 2050 | else if( _c0 == BoolTest::lt ) st->print_raw("lt"); |
| 2051 | else if( _c0 == BoolTest::gt ) st->print_raw("gt"); |
| 2052 | else if( _c0 == BoolTest::overflow ) st->print_raw("o"); |
| 2053 | else if( _c0 == BoolTest::no_overflow ) st->print_raw("no"); |
| 2054 | } |
| 2055 | void cmpOp_vcmppdOper::ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { |
| 2056 | st->print_raw(""); |
| 2057 | if( _c0 == BoolTest::eq ) st->print_raw("eq"); |
| 2058 | else if( _c0 == BoolTest::ne ) st->print_raw("ne"); |
| 2059 | else if( _c0 == BoolTest::le ) st->print_raw("le"); |
| 2060 | else if( _c0 == BoolTest::ge ) st->print_raw("ge"); |
| 2061 | else if( _c0 == BoolTest::lt ) st->print_raw("lt"); |
| 2062 | else if( _c0 == BoolTest::gt ) st->print_raw("gt"); |
| 2063 | else if( _c0 == BoolTest::overflow ) st->print_raw("o"); |
| 2064 | else if( _c0 == BoolTest::no_overflow ) st->print_raw("no"); |
| 2065 | } |
| 2066 | #endif |
| 2067 | #ifndef PRODUCT |
| 2068 | void MoveF2VLNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 2069 | // Start at oper_input_base() and count operands |
| 2070 | unsigned idx0 = 1; |
| 2071 | unsigned idx1 = 1; // src |
| 2072 | st->print_raw("movss "); |
| 2073 | opnd_array(0)->int_format(ra, this, st); // dst |
| 2074 | st->print_raw(","); |
| 2075 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 2076 | st->print_raw("\t! load float (4 bytes)"); |
| 2077 | } |
| 2078 | #endif |
| 2079 | #ifndef PRODUCT |
| 2080 | void MoveF2LEGNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 2081 | // Start at oper_input_base() and count operands |
| 2082 | unsigned idx0 = 1; |
| 2083 | unsigned idx1 = 1; // src |
| 2084 | st->print_raw("movss "); |
| 2085 | opnd_array(0)->int_format(ra, this, st); // dst |
| 2086 | st->print_raw(","); |
| 2087 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 2088 | st->print_raw("\t# if src != dst load float (4 bytes)"); |
| 2089 | } |
| 2090 | #endif |
| 2091 | #ifndef PRODUCT |
| 2092 | void MoveVL2FNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 2093 | // Start at oper_input_base() and count operands |
| 2094 | unsigned idx0 = 1; |
| 2095 | unsigned idx1 = 1; // src |
| 2096 | st->print_raw("movss "); |
| 2097 | opnd_array(0)->int_format(ra, this, st); // dst |
| 2098 | st->print_raw(","); |
| 2099 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 2100 | st->print_raw("\t! load float (4 bytes)"); |
| 2101 | } |
| 2102 | #endif |
| 2103 | #ifndef PRODUCT |
| 2104 | void MoveLEG2FNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 2105 | // Start at oper_input_base() and count operands |
| 2106 | unsigned idx0 = 1; |
| 2107 | unsigned idx1 = 1; // src |
| 2108 | st->print_raw("movss "); |
| 2109 | opnd_array(0)->int_format(ra, this, st); // dst |
| 2110 | st->print_raw(","); |
| 2111 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 2112 | st->print_raw("\t# if src != dst load float (4 bytes)"); |
| 2113 | } |
| 2114 | #endif |
| 2115 | #ifndef PRODUCT |
| 2116 | void MoveD2VLNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 2117 | // Start at oper_input_base() and count operands |
| 2118 | unsigned idx0 = 1; |
| 2119 | unsigned idx1 = 1; // src |
| 2120 | st->print_raw("movsd "); |
| 2121 | opnd_array(0)->int_format(ra, this, st); // dst |
| 2122 | st->print_raw(","); |
| 2123 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 2124 | st->print_raw("\t! load double (8 bytes)"); |
| 2125 | } |
| 2126 | #endif |
| 2127 | #ifndef PRODUCT |
| 2128 | void MoveD2LEGNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 2129 | // Start at oper_input_base() and count operands |
| 2130 | unsigned idx0 = 1; |
| 2131 | unsigned idx1 = 1; // src |
| 2132 | st->print_raw("movsd "); |
| 2133 | opnd_array(0)->int_format(ra, this, st); // dst |
| 2134 | st->print_raw(","); |
| 2135 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 2136 | st->print_raw("\t# if src != dst load double (8 bytes)"); |
| 2137 | } |
| 2138 | #endif |
| 2139 | #ifndef PRODUCT |
| 2140 | void MoveVL2DNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 2141 | // Start at oper_input_base() and count operands |
| 2142 | unsigned idx0 = 1; |
| 2143 | unsigned idx1 = 1; // src |
| 2144 | st->print_raw("movsd "); |
| 2145 | opnd_array(0)->int_format(ra, this, st); // dst |
| 2146 | st->print_raw(","); |
| 2147 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 2148 | st->print_raw("\t! load double (8 bytes)"); |
| 2149 | } |
| 2150 | #endif |
| 2151 | #ifndef PRODUCT |
| 2152 | void MoveLEG2DNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 2153 | // Start at oper_input_base() and count operands |
| 2154 | unsigned idx0 = 1; |
| 2155 | unsigned idx1 = 1; // src |
| 2156 | st->print_raw("movsd "); |
| 2157 | opnd_array(0)->int_format(ra, this, st); // dst |
| 2158 | st->print_raw(","); |
| 2159 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 2160 | st->print_raw("\t# if src != dst load double (8 bytes)"); |
| 2161 | } |
| 2162 | #endif |
| 2163 | #ifndef PRODUCT |
| 2164 | void loadBNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 2165 | // Start at oper_input_base() and count operands |
| 2166 | unsigned idx0 = 2; |
| 2167 | unsigned idx1 = 2; // mem |
| 2168 | st->print_raw("movsbl "); |
| 2169 | opnd_array(0)->int_format(ra, this, st); // dst |
| 2170 | st->print_raw(", "); |
| 2171 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 2172 | st->print_raw("\t# byte"); |
| 2173 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 2174 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 2175 | st->print(" ! Field: "); |
| 2176 | if (f->is_volatile()) |
| 2177 | st->print("volatile "); |
| 2178 | f->holder()->name()->print_symbol_on(st); |
| 2179 | st->print("."); |
| 2180 | f->name()->print_symbol_on(st); |
| 2181 | if (f->is_constant()) |
| 2182 | st->print(" (constant)"); |
| 2183 | } else { |
| 2184 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 2185 | st->print(" volatile!"); |
| 2186 | } |
| 2187 | } |
| 2188 | #endif |
| 2189 | #ifndef PRODUCT |
| 2190 | void loadB2LNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 2191 | // Start at oper_input_base() and count operands |
| 2192 | unsigned idx0 = 2; |
| 2193 | unsigned idx1 = 2; // mem |
| 2194 | st->print_raw("movsbq "); |
| 2195 | opnd_array(0)->int_format(ra, this, st); // dst |
| 2196 | st->print_raw(", "); |
| 2197 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 2198 | st->print_raw("\t# byte -> long"); |
| 2199 | } |
| 2200 | #endif |
| 2201 | #ifndef PRODUCT |
| 2202 | void loadUBNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 2203 | // Start at oper_input_base() and count operands |
| 2204 | unsigned idx0 = 2; |
| 2205 | unsigned idx1 = 2; // mem |
| 2206 | st->print_raw("movzbl "); |
| 2207 | opnd_array(0)->int_format(ra, this, st); // dst |
| 2208 | st->print_raw(", "); |
| 2209 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 2210 | st->print_raw("\t# ubyte"); |
| 2211 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 2212 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 2213 | st->print(" ! Field: "); |
| 2214 | if (f->is_volatile()) |
| 2215 | st->print("volatile "); |
| 2216 | f->holder()->name()->print_symbol_on(st); |
| 2217 | st->print("."); |
| 2218 | f->name()->print_symbol_on(st); |
| 2219 | if (f->is_constant()) |
| 2220 | st->print(" (constant)"); |
| 2221 | } else { |
| 2222 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 2223 | st->print(" volatile!"); |
| 2224 | } |
| 2225 | } |
| 2226 | #endif |
| 2227 | #ifndef PRODUCT |
| 2228 | void loadUB2LNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 2229 | // Start at oper_input_base() and count operands |
| 2230 | unsigned idx0 = 2; |
| 2231 | unsigned idx1 = 2; // mem |
| 2232 | st->print_raw("movzbq "); |
| 2233 | opnd_array(0)->int_format(ra, this, st); // dst |
| 2234 | st->print_raw(", "); |
| 2235 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 2236 | st->print_raw("\t# ubyte -> long"); |
| 2237 | } |
| 2238 | #endif |
| 2239 | #ifndef PRODUCT |
| 2240 | void loadUB2L_immINode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 2241 | // Start at oper_input_base() and count operands |
| 2242 | unsigned idx0 = 2; |
| 2243 | unsigned idx1 = 2; // mem |
| 2244 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask |
| 2245 | st->print_raw("movzbq "); |
| 2246 | opnd_array(0)->int_format(ra, this, st); // dst |
| 2247 | st->print_raw(", "); |
| 2248 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 2249 | st->print_raw("\t# ubyte & 32-bit mask -> long\n\t"); |
| 2250 | st->print_raw("andl "); |
| 2251 | opnd_array(0)->int_format(ra, this, st); // dst |
| 2252 | st->print_raw(", right_n_bits("); |
| 2253 | opnd_array(2)->ext_format(ra, this,idx2, st); // mask |
| 2254 | st->print_raw(", 8)"); |
| 2255 | } |
| 2256 | #endif |
| 2257 | #ifndef PRODUCT |
| 2258 | void loadSNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 2259 | // Start at oper_input_base() and count operands |
| 2260 | unsigned idx0 = 2; |
| 2261 | unsigned idx1 = 2; // mem |
| 2262 | st->print_raw("movswl "); |
| 2263 | opnd_array(0)->int_format(ra, this, st); // dst |
| 2264 | st->print_raw(", "); |
| 2265 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 2266 | st->print_raw("\t# short"); |
| 2267 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 2268 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 2269 | st->print(" ! Field: "); |
| 2270 | if (f->is_volatile()) |
| 2271 | st->print("volatile "); |
| 2272 | f->holder()->name()->print_symbol_on(st); |
| 2273 | st->print("."); |
| 2274 | f->name()->print_symbol_on(st); |
| 2275 | if (f->is_constant()) |
| 2276 | st->print(" (constant)"); |
| 2277 | } else { |
| 2278 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 2279 | st->print(" volatile!"); |
| 2280 | } |
| 2281 | } |
| 2282 | #endif |
| 2283 | #ifndef PRODUCT |
| 2284 | void loadS2BNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 2285 | // Start at oper_input_base() and count operands |
| 2286 | unsigned idx0 = 2; |
| 2287 | unsigned idx1 = 2; // mem |
| 2288 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // twentyfour |
| 2289 | st->print_raw("movsbl "); |
| 2290 | opnd_array(0)->int_format(ra, this, st); // dst |
| 2291 | st->print_raw(", "); |
| 2292 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 2293 | st->print_raw("\t# short -> byte"); |
| 2294 | } |
| 2295 | #endif |
| 2296 | #ifndef PRODUCT |
| 2297 | void loadS2LNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 2298 | // Start at oper_input_base() and count operands |
| 2299 | unsigned idx0 = 2; |
| 2300 | unsigned idx1 = 2; // mem |
| 2301 | st->print_raw("movswq "); |
| 2302 | opnd_array(0)->int_format(ra, this, st); // dst |
| 2303 | st->print_raw(", "); |
| 2304 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 2305 | st->print_raw("\t# short -> long"); |
| 2306 | } |
| 2307 | #endif |
| 2308 | #ifndef PRODUCT |
| 2309 | void loadUSNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 2310 | // Start at oper_input_base() and count operands |
| 2311 | unsigned idx0 = 2; |
| 2312 | unsigned idx1 = 2; // mem |
| 2313 | st->print_raw("movzwl "); |
| 2314 | opnd_array(0)->int_format(ra, this, st); // dst |
| 2315 | st->print_raw(", "); |
| 2316 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 2317 | st->print_raw("\t# ushort/char"); |
| 2318 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 2319 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 2320 | st->print(" ! Field: "); |
| 2321 | if (f->is_volatile()) |
| 2322 | st->print("volatile "); |
| 2323 | f->holder()->name()->print_symbol_on(st); |
| 2324 | st->print("."); |
| 2325 | f->name()->print_symbol_on(st); |
| 2326 | if (f->is_constant()) |
| 2327 | st->print(" (constant)"); |
| 2328 | } else { |
| 2329 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 2330 | st->print(" volatile!"); |
| 2331 | } |
| 2332 | } |
| 2333 | #endif |
| 2334 | #ifndef PRODUCT |
| 2335 | void loadUS2BNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 2336 | // Start at oper_input_base() and count operands |
| 2337 | unsigned idx0 = 2; |
| 2338 | unsigned idx1 = 2; // mem |
| 2339 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // twentyfour |
| 2340 | st->print_raw("movsbl "); |
| 2341 | opnd_array(0)->int_format(ra, this, st); // dst |
| 2342 | st->print_raw(", "); |
| 2343 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 2344 | st->print_raw("\t# ushort -> byte"); |
| 2345 | } |
| 2346 | #endif |
| 2347 | #ifndef PRODUCT |
| 2348 | void loadUS2LNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 2349 | // Start at oper_input_base() and count operands |
| 2350 | unsigned idx0 = 2; |
| 2351 | unsigned idx1 = 2; // mem |
| 2352 | st->print_raw("movzwq "); |
| 2353 | opnd_array(0)->int_format(ra, this, st); // dst |
| 2354 | st->print_raw(", "); |
| 2355 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 2356 | st->print_raw("\t# ushort/char -> long"); |
| 2357 | } |
| 2358 | #endif |
| 2359 | #ifndef PRODUCT |
| 2360 | void loadUS2L_immI_255Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 2361 | // Start at oper_input_base() and count operands |
| 2362 | unsigned idx0 = 2; |
| 2363 | unsigned idx1 = 2; // mem |
| 2364 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask |
| 2365 | st->print_raw("movzbq "); |
| 2366 | opnd_array(0)->int_format(ra, this, st); // dst |
| 2367 | st->print_raw(", "); |
| 2368 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 2369 | st->print_raw("\t# ushort/char & 0xFF -> long"); |
| 2370 | } |
| 2371 | #endif |
| 2372 | #ifndef PRODUCT |
| 2373 | void loadUS2L_immINode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 2374 | // Start at oper_input_base() and count operands |
| 2375 | unsigned idx0 = 2; |
| 2376 | unsigned idx1 = 2; // mem |
| 2377 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask |
| 2378 | st->print_raw("movzwq "); |
| 2379 | opnd_array(0)->int_format(ra, this, st); // dst |
| 2380 | st->print_raw(", "); |
| 2381 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 2382 | st->print_raw("\t# ushort/char & 32-bit mask -> long\n\t"); |
| 2383 | st->print_raw("andl "); |
| 2384 | opnd_array(0)->int_format(ra, this, st); // dst |
| 2385 | st->print_raw(", right_n_bits("); |
| 2386 | opnd_array(2)->ext_format(ra, this,idx2, st); // mask |
| 2387 | st->print_raw(", 16)"); |
| 2388 | } |
| 2389 | #endif |
| 2390 | #ifndef PRODUCT |
| 2391 | void loadINode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 2392 | // Start at oper_input_base() and count operands |
| 2393 | unsigned idx0 = 2; |
| 2394 | unsigned idx1 = 2; // mem |
| 2395 | st->print_raw("movl "); |
| 2396 | opnd_array(0)->int_format(ra, this, st); // dst |
| 2397 | st->print_raw(", "); |
| 2398 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 2399 | st->print_raw("\t# int"); |
| 2400 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 2401 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 2402 | st->print(" ! Field: "); |
| 2403 | if (f->is_volatile()) |
| 2404 | st->print("volatile "); |
| 2405 | f->holder()->name()->print_symbol_on(st); |
| 2406 | st->print("."); |
| 2407 | f->name()->print_symbol_on(st); |
| 2408 | if (f->is_constant()) |
| 2409 | st->print(" (constant)"); |
| 2410 | } else { |
| 2411 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 2412 | st->print(" volatile!"); |
| 2413 | } |
| 2414 | } |
| 2415 | #endif |
| 2416 | #ifndef PRODUCT |
| 2417 | void loadI2BNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 2418 | // Start at oper_input_base() and count operands |
| 2419 | unsigned idx0 = 2; |
| 2420 | unsigned idx1 = 2; // mem |
| 2421 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // twentyfour |
| 2422 | st->print_raw("movsbl "); |
| 2423 | opnd_array(0)->int_format(ra, this, st); // dst |
| 2424 | st->print_raw(", "); |
| 2425 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 2426 | st->print_raw("\t# int -> byte"); |
| 2427 | } |
| 2428 | #endif |
| 2429 | #ifndef PRODUCT |
| 2430 | void loadI2UBNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 2431 | // Start at oper_input_base() and count operands |
| 2432 | unsigned idx0 = 2; |
| 2433 | unsigned idx1 = 2; // mem |
| 2434 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask |
| 2435 | st->print_raw("movzbl "); |
| 2436 | opnd_array(0)->int_format(ra, this, st); // dst |
| 2437 | st->print_raw(", "); |
| 2438 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 2439 | st->print_raw("\t# int -> ubyte"); |
| 2440 | } |
| 2441 | #endif |
| 2442 | #ifndef PRODUCT |
| 2443 | void loadI2SNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 2444 | // Start at oper_input_base() and count operands |
| 2445 | unsigned idx0 = 2; |
| 2446 | unsigned idx1 = 2; // mem |
| 2447 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // sixteen |
| 2448 | st->print_raw("movswl "); |
| 2449 | opnd_array(0)->int_format(ra, this, st); // dst |
| 2450 | st->print_raw(", "); |
| 2451 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 2452 | st->print_raw("\t# int -> short"); |
| 2453 | } |
| 2454 | #endif |
| 2455 | #ifndef PRODUCT |
| 2456 | void loadI2USNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 2457 | // Start at oper_input_base() and count operands |
| 2458 | unsigned idx0 = 2; |
| 2459 | unsigned idx1 = 2; // mem |
| 2460 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask |
| 2461 | st->print_raw("movzwl "); |
| 2462 | opnd_array(0)->int_format(ra, this, st); // dst |
| 2463 | st->print_raw(", "); |
| 2464 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 2465 | st->print_raw("\t# int -> ushort/char"); |
| 2466 | } |
| 2467 | #endif |
| 2468 | #ifndef PRODUCT |
| 2469 | void loadI2LNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 2470 | // Start at oper_input_base() and count operands |
| 2471 | unsigned idx0 = 2; |
| 2472 | unsigned idx1 = 2; // mem |
| 2473 | st->print_raw("movslq "); |
| 2474 | opnd_array(0)->int_format(ra, this, st); // dst |
| 2475 | st->print_raw(", "); |
| 2476 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 2477 | st->print_raw("\t# int -> long"); |
| 2478 | } |
| 2479 | #endif |
| 2480 | #ifndef PRODUCT |
| 2481 | void loadI2L_immI_255Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 2482 | // Start at oper_input_base() and count operands |
| 2483 | unsigned idx0 = 2; |
| 2484 | unsigned idx1 = 2; // mem |
| 2485 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask |
| 2486 | st->print_raw("movzbq "); |
| 2487 | opnd_array(0)->int_format(ra, this, st); // dst |
| 2488 | st->print_raw(", "); |
| 2489 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 2490 | st->print_raw("\t# int & 0xFF -> long"); |
| 2491 | } |
| 2492 | #endif |
| 2493 | #ifndef PRODUCT |
| 2494 | void loadI2L_immI_65535Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 2495 | // Start at oper_input_base() and count operands |
| 2496 | unsigned idx0 = 2; |
| 2497 | unsigned idx1 = 2; // mem |
| 2498 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask |
| 2499 | st->print_raw("movzwq "); |
| 2500 | opnd_array(0)->int_format(ra, this, st); // dst |
| 2501 | st->print_raw(", "); |
| 2502 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 2503 | st->print_raw("\t# int & 0xFFFF -> long"); |
| 2504 | } |
| 2505 | #endif |
| 2506 | #ifndef PRODUCT |
| 2507 | void loadI2L_immU31Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 2508 | // Start at oper_input_base() and count operands |
| 2509 | unsigned idx0 = 2; |
| 2510 | unsigned idx1 = 2; // mem |
| 2511 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask |
| 2512 | st->print_raw("movl "); |
| 2513 | opnd_array(0)->int_format(ra, this, st); // dst |
| 2514 | st->print_raw(", "); |
| 2515 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 2516 | st->print_raw("\t# int & 31-bit mask -> long\n\t"); |
| 2517 | st->print_raw("andl "); |
| 2518 | opnd_array(0)->int_format(ra, this, st); // dst |
| 2519 | st->print_raw(", "); |
| 2520 | opnd_array(2)->ext_format(ra, this,idx2, st); // mask |
| 2521 | } |
| 2522 | #endif |
| 2523 | #ifndef PRODUCT |
| 2524 | void loadUI2LNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 2525 | // Start at oper_input_base() and count operands |
| 2526 | unsigned idx0 = 2; |
| 2527 | unsigned idx1 = 2; // mem |
| 2528 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask |
| 2529 | st->print_raw("movl "); |
| 2530 | opnd_array(0)->int_format(ra, this, st); // dst |
| 2531 | st->print_raw(", "); |
| 2532 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 2533 | st->print_raw("\t# uint -> long"); |
| 2534 | } |
| 2535 | #endif |
| 2536 | #ifndef PRODUCT |
| 2537 | void loadLNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 2538 | // Start at oper_input_base() and count operands |
| 2539 | unsigned idx0 = 2; |
| 2540 | unsigned idx1 = 2; // mem |
| 2541 | st->print_raw("movq "); |
| 2542 | opnd_array(0)->int_format(ra, this, st); // dst |
| 2543 | st->print_raw(", "); |
| 2544 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 2545 | st->print_raw("\t# long"); |
| 2546 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 2547 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 2548 | st->print(" ! Field: "); |
| 2549 | if (f->is_volatile()) |
| 2550 | st->print("volatile "); |
| 2551 | f->holder()->name()->print_symbol_on(st); |
| 2552 | st->print("."); |
| 2553 | f->name()->print_symbol_on(st); |
| 2554 | if (f->is_constant()) |
| 2555 | st->print(" (constant)"); |
| 2556 | } else { |
| 2557 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 2558 | st->print(" volatile!"); |
| 2559 | } |
| 2560 | } |
| 2561 | #endif |
| 2562 | #ifndef PRODUCT |
| 2563 | void loadRangeNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 2564 | // Start at oper_input_base() and count operands |
| 2565 | unsigned idx0 = 2; |
| 2566 | unsigned idx1 = 2; // mem |
| 2567 | st->print_raw("movl "); |
| 2568 | opnd_array(0)->int_format(ra, this, st); // dst |
| 2569 | st->print_raw(", "); |
| 2570 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 2571 | st->print_raw("\t# range"); |
| 2572 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 2573 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 2574 | st->print(" ! Field: "); |
| 2575 | if (f->is_volatile()) |
| 2576 | st->print("volatile "); |
| 2577 | f->holder()->name()->print_symbol_on(st); |
| 2578 | st->print("."); |
| 2579 | f->name()->print_symbol_on(st); |
| 2580 | if (f->is_constant()) |
| 2581 | st->print(" (constant)"); |
| 2582 | } else { |
| 2583 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 2584 | st->print(" volatile!"); |
| 2585 | } |
| 2586 | } |
| 2587 | #endif |
| 2588 | #ifndef PRODUCT |
| 2589 | void loadPNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 2590 | // Start at oper_input_base() and count operands |
| 2591 | unsigned idx0 = 2; |
| 2592 | unsigned idx1 = 2; // mem |
| 2593 | st->print_raw("movq "); |
| 2594 | opnd_array(0)->int_format(ra, this, st); // dst |
| 2595 | st->print_raw(", "); |
| 2596 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 2597 | st->print_raw("\t# ptr"); |
| 2598 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 2599 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 2600 | st->print(" ! Field: "); |
| 2601 | if (f->is_volatile()) |
| 2602 | st->print("volatile "); |
| 2603 | f->holder()->name()->print_symbol_on(st); |
| 2604 | st->print("."); |
| 2605 | f->name()->print_symbol_on(st); |
| 2606 | if (f->is_constant()) |
| 2607 | st->print(" (constant)"); |
| 2608 | } else { |
| 2609 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 2610 | st->print(" volatile!"); |
| 2611 | } |
| 2612 | } |
| 2613 | #endif |
| 2614 | #ifndef PRODUCT |
| 2615 | void loadNNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 2616 | // Start at oper_input_base() and count operands |
| 2617 | unsigned idx0 = 2; |
| 2618 | unsigned idx1 = 2; // mem |
| 2619 | st->print_raw("movl "); |
| 2620 | opnd_array(0)->int_format(ra, this, st); // dst |
| 2621 | st->print_raw(", "); |
| 2622 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 2623 | st->print_raw("\t# compressed ptr"); |
| 2624 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 2625 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 2626 | st->print(" ! Field: "); |
| 2627 | if (f->is_volatile()) |
| 2628 | st->print("volatile "); |
| 2629 | f->holder()->name()->print_symbol_on(st); |
| 2630 | st->print("."); |
| 2631 | f->name()->print_symbol_on(st); |
| 2632 | if (f->is_constant()) |
| 2633 | st->print(" (constant)"); |
| 2634 | } else { |
| 2635 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 2636 | st->print(" volatile!"); |
| 2637 | } |
| 2638 | } |
| 2639 | #endif |
| 2640 | #ifndef PRODUCT |
| 2641 | void loadKlassNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 2642 | // Start at oper_input_base() and count operands |
| 2643 | unsigned idx0 = 2; |
| 2644 | unsigned idx1 = 2; // mem |
| 2645 | st->print_raw("movq "); |
| 2646 | opnd_array(0)->int_format(ra, this, st); // dst |
| 2647 | st->print_raw(", "); |
| 2648 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 2649 | st->print_raw("\t# class"); |
| 2650 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 2651 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 2652 | st->print(" ! Field: "); |
| 2653 | if (f->is_volatile()) |
| 2654 | st->print("volatile "); |
| 2655 | f->holder()->name()->print_symbol_on(st); |
| 2656 | st->print("."); |
| 2657 | f->name()->print_symbol_on(st); |
| 2658 | if (f->is_constant()) |
| 2659 | st->print(" (constant)"); |
| 2660 | } else { |
| 2661 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 2662 | st->print(" volatile!"); |
| 2663 | } |
| 2664 | } |
| 2665 | #endif |
| 2666 | #ifndef PRODUCT |
| 2667 | void loadNKlassNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 2668 | // Start at oper_input_base() and count operands |
| 2669 | unsigned idx0 = 2; |
| 2670 | unsigned idx1 = 2; // mem |
| 2671 | st->print_raw("movl "); |
| 2672 | opnd_array(0)->int_format(ra, this, st); // dst |
| 2673 | st->print_raw(", "); |
| 2674 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 2675 | st->print_raw("\t# compressed klass ptr"); |
| 2676 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 2677 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 2678 | st->print(" ! Field: "); |
| 2679 | if (f->is_volatile()) |
| 2680 | st->print("volatile "); |
| 2681 | f->holder()->name()->print_symbol_on(st); |
| 2682 | st->print("."); |
| 2683 | f->name()->print_symbol_on(st); |
| 2684 | if (f->is_constant()) |
| 2685 | st->print(" (constant)"); |
| 2686 | } else { |
| 2687 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 2688 | st->print(" volatile!"); |
| 2689 | } |
| 2690 | } |
| 2691 | #endif |
| 2692 | #ifndef PRODUCT |
| 2693 | void loadFNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 2694 | // Start at oper_input_base() and count operands |
| 2695 | unsigned idx0 = 2; |
| 2696 | unsigned idx1 = 2; // mem |
| 2697 | st->print_raw("movss "); |
| 2698 | opnd_array(0)->int_format(ra, this, st); // dst |
| 2699 | st->print_raw(", "); |
| 2700 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 2701 | st->print_raw("\t# float"); |
| 2702 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 2703 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 2704 | st->print(" ! Field: "); |
| 2705 | if (f->is_volatile()) |
| 2706 | st->print("volatile "); |
| 2707 | f->holder()->name()->print_symbol_on(st); |
| 2708 | st->print("."); |
| 2709 | f->name()->print_symbol_on(st); |
| 2710 | if (f->is_constant()) |
| 2711 | st->print(" (constant)"); |
| 2712 | } else { |
| 2713 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 2714 | st->print(" volatile!"); |
| 2715 | } |
| 2716 | } |
| 2717 | #endif |
| 2718 | #ifndef PRODUCT |
| 2719 | void loadD_partialNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 2720 | // Start at oper_input_base() and count operands |
| 2721 | unsigned idx0 = 2; |
| 2722 | unsigned idx1 = 2; // mem |
| 2723 | st->print_raw("movlpd "); |
| 2724 | opnd_array(0)->int_format(ra, this, st); // dst |
| 2725 | st->print_raw(", "); |
| 2726 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 2727 | st->print_raw("\t# double"); |
| 2728 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 2729 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 2730 | st->print(" ! Field: "); |
| 2731 | if (f->is_volatile()) |
| 2732 | st->print("volatile "); |
| 2733 | f->holder()->name()->print_symbol_on(st); |
| 2734 | st->print("."); |
| 2735 | f->name()->print_symbol_on(st); |
| 2736 | if (f->is_constant()) |
| 2737 | st->print(" (constant)"); |
| 2738 | } else { |
| 2739 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 2740 | st->print(" volatile!"); |
| 2741 | } |
| 2742 | } |
| 2743 | #endif |
| 2744 | #ifndef PRODUCT |
| 2745 | void loadDNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 2746 | // Start at oper_input_base() and count operands |
| 2747 | unsigned idx0 = 2; |
| 2748 | unsigned idx1 = 2; // mem |
| 2749 | st->print_raw("movsd "); |
| 2750 | opnd_array(0)->int_format(ra, this, st); // dst |
| 2751 | st->print_raw(", "); |
| 2752 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 2753 | st->print_raw("\t# double"); |
| 2754 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 2755 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 2756 | st->print(" ! Field: "); |
| 2757 | if (f->is_volatile()) |
| 2758 | st->print("volatile "); |
| 2759 | f->holder()->name()->print_symbol_on(st); |
| 2760 | st->print("."); |
| 2761 | f->name()->print_symbol_on(st); |
| 2762 | if (f->is_constant()) |
| 2763 | st->print(" (constant)"); |
| 2764 | } else { |
| 2765 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 2766 | st->print(" volatile!"); |
| 2767 | } |
| 2768 | } |
| 2769 | #endif |
| 2770 | #ifndef PRODUCT |
| 2771 | void maxF_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 2772 | // Start at oper_input_base() and count operands |
| 2773 | unsigned idx0 = 1; |
| 2774 | unsigned idx1 = 1; // a |
| 2775 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // b |
| 2776 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp |
| 2777 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // atmp |
| 2778 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // btmp |
| 2779 | st->print_raw("vblendvps "); |
| 2780 | opnd_array(5)->ext_format(ra, this,idx5, st); // btmp |
| 2781 | st->print_raw(","); |
| 2782 | opnd_array(2)->ext_format(ra, this,idx2, st); // b |
| 2783 | st->print_raw(","); |
| 2784 | opnd_array(1)->ext_format(ra, this,idx1, st); // a |
| 2785 | st->print_raw(","); |
| 2786 | opnd_array(2)->ext_format(ra, this,idx2, st); // b |
| 2787 | st->print_raw(" \n\t"); |
| 2788 | st->print_raw("vblendvps "); |
| 2789 | opnd_array(4)->ext_format(ra, this,idx4, st); // atmp |
| 2790 | st->print_raw(","); |
| 2791 | opnd_array(1)->ext_format(ra, this,idx1, st); // a |
| 2792 | st->print_raw(","); |
| 2793 | opnd_array(2)->ext_format(ra, this,idx2, st); // b |
| 2794 | st->print_raw(","); |
| 2795 | opnd_array(2)->ext_format(ra, this,idx2, st); // b |
| 2796 | st->print_raw(" \n\t"); |
| 2797 | st->print_raw("vmaxss "); |
| 2798 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp |
| 2799 | st->print_raw(","); |
| 2800 | opnd_array(4)->ext_format(ra, this,idx4, st); // atmp |
| 2801 | st->print_raw(","); |
| 2802 | opnd_array(5)->ext_format(ra, this,idx5, st); // btmp |
| 2803 | st->print_raw(" \n\t"); |
| 2804 | st->print_raw("vcmpps.unordered "); |
| 2805 | opnd_array(5)->ext_format(ra, this,idx5, st); // btmp |
| 2806 | st->print_raw(","); |
| 2807 | opnd_array(4)->ext_format(ra, this,idx4, st); // atmp |
| 2808 | st->print_raw(","); |
| 2809 | opnd_array(4)->ext_format(ra, this,idx4, st); // atmp |
| 2810 | st->print_raw(" \n\t"); |
| 2811 | st->print_raw("vblendvps "); |
| 2812 | opnd_array(0)->int_format(ra, this, st); // dst |
| 2813 | st->print_raw(","); |
| 2814 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp |
| 2815 | st->print_raw(","); |
| 2816 | opnd_array(4)->ext_format(ra, this,idx4, st); // atmp |
| 2817 | st->print_raw(","); |
| 2818 | opnd_array(5)->ext_format(ra, this,idx5, st); // btmp |
| 2819 | st->print_raw(" \n\t"); |
| 2820 | } |
| 2821 | #endif |
| 2822 | #ifndef PRODUCT |
| 2823 | void maxF_reduction_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 2824 | // Start at oper_input_base() and count operands |
| 2825 | unsigned idx0 = 1; |
| 2826 | unsigned idx1 = 1; // a |
| 2827 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // b |
| 2828 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // xmmt |
| 2829 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp |
| 2830 | opnd_array(0)->int_format(ra, this, st); // dst |
| 2831 | st->print_raw(" = max("); |
| 2832 | opnd_array(1)->ext_format(ra, this,idx1, st); // a |
| 2833 | st->print_raw(", "); |
| 2834 | opnd_array(2)->ext_format(ra, this,idx2, st); // b |
| 2835 | st->print_raw(")\t# intrinsic (float)"); |
| 2836 | } |
| 2837 | #endif |
| 2838 | #ifndef PRODUCT |
| 2839 | void maxD_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 2840 | // Start at oper_input_base() and count operands |
| 2841 | unsigned idx0 = 1; |
| 2842 | unsigned idx1 = 1; // a |
| 2843 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // b |
| 2844 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp |
| 2845 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // atmp |
| 2846 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // btmp |
| 2847 | st->print_raw("vblendvpd "); |
| 2848 | opnd_array(5)->ext_format(ra, this,idx5, st); // btmp |
| 2849 | st->print_raw(","); |
| 2850 | opnd_array(2)->ext_format(ra, this,idx2, st); // b |
| 2851 | st->print_raw(","); |
| 2852 | opnd_array(1)->ext_format(ra, this,idx1, st); // a |
| 2853 | st->print_raw(","); |
| 2854 | opnd_array(2)->ext_format(ra, this,idx2, st); // b |
| 2855 | st->print_raw(" \n\t"); |
| 2856 | st->print_raw("vblendvpd "); |
| 2857 | opnd_array(4)->ext_format(ra, this,idx4, st); // atmp |
| 2858 | st->print_raw(","); |
| 2859 | opnd_array(1)->ext_format(ra, this,idx1, st); // a |
| 2860 | st->print_raw(","); |
| 2861 | opnd_array(2)->ext_format(ra, this,idx2, st); // b |
| 2862 | st->print_raw(","); |
| 2863 | opnd_array(2)->ext_format(ra, this,idx2, st); // b |
| 2864 | st->print_raw(" \n\t"); |
| 2865 | st->print_raw("vmaxsd "); |
| 2866 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp |
| 2867 | st->print_raw(","); |
| 2868 | opnd_array(4)->ext_format(ra, this,idx4, st); // atmp |
| 2869 | st->print_raw(","); |
| 2870 | opnd_array(5)->ext_format(ra, this,idx5, st); // btmp |
| 2871 | st->print_raw(" \n\t"); |
| 2872 | st->print_raw("vcmppd.unordered "); |
| 2873 | opnd_array(5)->ext_format(ra, this,idx5, st); // btmp |
| 2874 | st->print_raw(","); |
| 2875 | opnd_array(4)->ext_format(ra, this,idx4, st); // atmp |
| 2876 | st->print_raw(","); |
| 2877 | opnd_array(4)->ext_format(ra, this,idx4, st); // atmp |
| 2878 | st->print_raw(" \n\t"); |
| 2879 | st->print_raw("vblendvpd "); |
| 2880 | opnd_array(0)->int_format(ra, this, st); // dst |
| 2881 | st->print_raw(","); |
| 2882 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp |
| 2883 | st->print_raw(","); |
| 2884 | opnd_array(4)->ext_format(ra, this,idx4, st); // atmp |
| 2885 | st->print_raw(","); |
| 2886 | opnd_array(5)->ext_format(ra, this,idx5, st); // btmp |
| 2887 | st->print_raw(" \n\t"); |
| 2888 | } |
| 2889 | #endif |
| 2890 | #ifndef PRODUCT |
| 2891 | void maxD_reduction_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 2892 | // Start at oper_input_base() and count operands |
| 2893 | unsigned idx0 = 1; |
| 2894 | unsigned idx1 = 1; // a |
| 2895 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // b |
| 2896 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // xmmt |
| 2897 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp |
| 2898 | opnd_array(0)->int_format(ra, this, st); // dst |
| 2899 | st->print_raw(" = max("); |
| 2900 | opnd_array(1)->ext_format(ra, this,idx1, st); // a |
| 2901 | st->print_raw(", "); |
| 2902 | opnd_array(2)->ext_format(ra, this,idx2, st); // b |
| 2903 | st->print_raw(")\t# intrinsic (double)"); |
| 2904 | } |
| 2905 | #endif |
| 2906 | #ifndef PRODUCT |
| 2907 | void minF_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 2908 | // Start at oper_input_base() and count operands |
| 2909 | unsigned idx0 = 1; |
| 2910 | unsigned idx1 = 1; // a |
| 2911 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // b |
| 2912 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp |
| 2913 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // atmp |
| 2914 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // btmp |
| 2915 | st->print_raw("vblendvps "); |
| 2916 | opnd_array(4)->ext_format(ra, this,idx4, st); // atmp |
| 2917 | st->print_raw(","); |
| 2918 | opnd_array(1)->ext_format(ra, this,idx1, st); // a |
| 2919 | st->print_raw(","); |
| 2920 | opnd_array(2)->ext_format(ra, this,idx2, st); // b |
| 2921 | st->print_raw(","); |
| 2922 | opnd_array(1)->ext_format(ra, this,idx1, st); // a |
| 2923 | st->print_raw(" \n\t"); |
| 2924 | st->print_raw("vblendvps "); |
| 2925 | opnd_array(5)->ext_format(ra, this,idx5, st); // btmp |
| 2926 | st->print_raw(","); |
| 2927 | opnd_array(2)->ext_format(ra, this,idx2, st); // b |
| 2928 | st->print_raw(","); |
| 2929 | opnd_array(1)->ext_format(ra, this,idx1, st); // a |
| 2930 | st->print_raw(","); |
| 2931 | opnd_array(1)->ext_format(ra, this,idx1, st); // a |
| 2932 | st->print_raw(" \n\t"); |
| 2933 | st->print_raw("vminss "); |
| 2934 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp |
| 2935 | st->print_raw(","); |
| 2936 | opnd_array(4)->ext_format(ra, this,idx4, st); // atmp |
| 2937 | st->print_raw(","); |
| 2938 | opnd_array(5)->ext_format(ra, this,idx5, st); // btmp |
| 2939 | st->print_raw(" \n\t"); |
| 2940 | st->print_raw("vcmpps.unordered "); |
| 2941 | opnd_array(5)->ext_format(ra, this,idx5, st); // btmp |
| 2942 | st->print_raw(","); |
| 2943 | opnd_array(4)->ext_format(ra, this,idx4, st); // atmp |
| 2944 | st->print_raw(","); |
| 2945 | opnd_array(4)->ext_format(ra, this,idx4, st); // atmp |
| 2946 | st->print_raw(" \n\t"); |
| 2947 | st->print_raw("vblendvps "); |
| 2948 | opnd_array(0)->int_format(ra, this, st); // dst |
| 2949 | st->print_raw(","); |
| 2950 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp |
| 2951 | st->print_raw(","); |
| 2952 | opnd_array(4)->ext_format(ra, this,idx4, st); // atmp |
| 2953 | st->print_raw(","); |
| 2954 | opnd_array(5)->ext_format(ra, this,idx5, st); // btmp |
| 2955 | st->print_raw(" \n\t"); |
| 2956 | } |
| 2957 | #endif |
| 2958 | #ifndef PRODUCT |
| 2959 | void minF_reduction_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 2960 | // Start at oper_input_base() and count operands |
| 2961 | unsigned idx0 = 1; |
| 2962 | unsigned idx1 = 1; // a |
| 2963 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // b |
| 2964 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // xmmt |
| 2965 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp |
| 2966 | opnd_array(0)->int_format(ra, this, st); // dst |
| 2967 | st->print_raw(" = min("); |
| 2968 | opnd_array(1)->ext_format(ra, this,idx1, st); // a |
| 2969 | st->print_raw(", "); |
| 2970 | opnd_array(2)->ext_format(ra, this,idx2, st); // b |
| 2971 | st->print_raw(")\t# intrinsic (float)"); |
| 2972 | } |
| 2973 | #endif |
| 2974 | #ifndef PRODUCT |
| 2975 | void minD_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 2976 | // Start at oper_input_base() and count operands |
| 2977 | unsigned idx0 = 1; |
| 2978 | unsigned idx1 = 1; // a |
| 2979 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // b |
| 2980 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp |
| 2981 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // atmp |
| 2982 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // btmp |
| 2983 | st->print_raw("vblendvpd "); |
| 2984 | opnd_array(4)->ext_format(ra, this,idx4, st); // atmp |
| 2985 | st->print_raw(","); |
| 2986 | opnd_array(1)->ext_format(ra, this,idx1, st); // a |
| 2987 | st->print_raw(","); |
| 2988 | opnd_array(2)->ext_format(ra, this,idx2, st); // b |
| 2989 | st->print_raw(","); |
| 2990 | opnd_array(1)->ext_format(ra, this,idx1, st); // a |
| 2991 | st->print_raw(" \n\t"); |
| 2992 | st->print_raw("vblendvpd "); |
| 2993 | opnd_array(5)->ext_format(ra, this,idx5, st); // btmp |
| 2994 | st->print_raw(","); |
| 2995 | opnd_array(2)->ext_format(ra, this,idx2, st); // b |
| 2996 | st->print_raw(","); |
| 2997 | opnd_array(1)->ext_format(ra, this,idx1, st); // a |
| 2998 | st->print_raw(","); |
| 2999 | opnd_array(1)->ext_format(ra, this,idx1, st); // a |
| 3000 | st->print_raw(" \n\t"); |
| 3001 | st->print_raw("vminsd "); |
| 3002 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp |
| 3003 | st->print_raw(","); |
| 3004 | opnd_array(4)->ext_format(ra, this,idx4, st); // atmp |
| 3005 | st->print_raw(","); |
| 3006 | opnd_array(5)->ext_format(ra, this,idx5, st); // btmp |
| 3007 | st->print_raw(" \n\t"); |
| 3008 | st->print_raw("vcmppd.unordered "); |
| 3009 | opnd_array(5)->ext_format(ra, this,idx5, st); // btmp |
| 3010 | st->print_raw(","); |
| 3011 | opnd_array(4)->ext_format(ra, this,idx4, st); // atmp |
| 3012 | st->print_raw(","); |
| 3013 | opnd_array(4)->ext_format(ra, this,idx4, st); // atmp |
| 3014 | st->print_raw(" \n\t"); |
| 3015 | st->print_raw("vblendvpd "); |
| 3016 | opnd_array(0)->int_format(ra, this, st); // dst |
| 3017 | st->print_raw(","); |
| 3018 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp |
| 3019 | st->print_raw(","); |
| 3020 | opnd_array(4)->ext_format(ra, this,idx4, st); // atmp |
| 3021 | st->print_raw(","); |
| 3022 | opnd_array(5)->ext_format(ra, this,idx5, st); // btmp |
| 3023 | st->print_raw(" \n\t"); |
| 3024 | } |
| 3025 | #endif |
| 3026 | #ifndef PRODUCT |
| 3027 | void minD_reduction_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 3028 | // Start at oper_input_base() and count operands |
| 3029 | unsigned idx0 = 1; |
| 3030 | unsigned idx1 = 1; // a |
| 3031 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // b |
| 3032 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // xmmt |
| 3033 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp |
| 3034 | opnd_array(0)->int_format(ra, this, st); // dst |
| 3035 | st->print_raw(" = min("); |
| 3036 | opnd_array(1)->ext_format(ra, this,idx1, st); // a |
| 3037 | st->print_raw(", "); |
| 3038 | opnd_array(2)->ext_format(ra, this,idx2, st); // b |
| 3039 | st->print_raw(")\t# intrinsic (double)"); |
| 3040 | } |
| 3041 | #endif |
| 3042 | #ifndef PRODUCT |
| 3043 | void leaP8Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 3044 | // Start at oper_input_base() and count operands |
| 3045 | unsigned idx0 = 2; |
| 3046 | unsigned idx1 = 2; // mem |
| 3047 | st->print_raw("leaq "); |
| 3048 | opnd_array(0)->int_format(ra, this, st); // dst |
| 3049 | st->print_raw(", "); |
| 3050 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 3051 | st->print_raw("\t# ptr 8"); |
| 3052 | } |
| 3053 | #endif |
| 3054 | #ifndef PRODUCT |
| 3055 | void leaP32Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 3056 | // Start at oper_input_base() and count operands |
| 3057 | unsigned idx0 = 2; |
| 3058 | unsigned idx1 = 2; // mem |
| 3059 | st->print_raw("leaq "); |
| 3060 | opnd_array(0)->int_format(ra, this, st); // dst |
| 3061 | st->print_raw(", "); |
| 3062 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 3063 | st->print_raw("\t# ptr 32"); |
| 3064 | } |
| 3065 | #endif |
| 3066 | #ifndef PRODUCT |
| 3067 | void leaPIdxOffNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 3068 | // Start at oper_input_base() and count operands |
| 3069 | unsigned idx0 = 2; |
| 3070 | unsigned idx1 = 2; // mem |
| 3071 | st->print_raw("leaq "); |
| 3072 | opnd_array(0)->int_format(ra, this, st); // dst |
| 3073 | st->print_raw(", "); |
| 3074 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 3075 | st->print_raw("\t# ptr idxoff"); |
| 3076 | } |
| 3077 | #endif |
| 3078 | #ifndef PRODUCT |
| 3079 | void leaPIdxScaleNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 3080 | // Start at oper_input_base() and count operands |
| 3081 | unsigned idx0 = 2; |
| 3082 | unsigned idx1 = 2; // mem |
| 3083 | st->print_raw("leaq "); |
| 3084 | opnd_array(0)->int_format(ra, this, st); // dst |
| 3085 | st->print_raw(", "); |
| 3086 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 3087 | st->print_raw("\t# ptr idxscale"); |
| 3088 | } |
| 3089 | #endif |
| 3090 | #ifndef PRODUCT |
| 3091 | void leaPPosIdxScaleNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 3092 | // Start at oper_input_base() and count operands |
| 3093 | unsigned idx0 = 2; |
| 3094 | unsigned idx1 = 2; // mem |
| 3095 | st->print_raw("leaq "); |
| 3096 | opnd_array(0)->int_format(ra, this, st); // dst |
| 3097 | st->print_raw(", "); |
| 3098 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 3099 | st->print_raw("\t# ptr idxscale"); |
| 3100 | } |
| 3101 | #endif |
| 3102 | #ifndef PRODUCT |
| 3103 | void leaPIdxScaleOffNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 3104 | // Start at oper_input_base() and count operands |
| 3105 | unsigned idx0 = 2; |
| 3106 | unsigned idx1 = 2; // mem |
| 3107 | st->print_raw("leaq "); |
| 3108 | opnd_array(0)->int_format(ra, this, st); // dst |
| 3109 | st->print_raw(", "); |
| 3110 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 3111 | st->print_raw("\t# ptr idxscaleoff"); |
| 3112 | } |
| 3113 | #endif |
| 3114 | #ifndef PRODUCT |
| 3115 | void leaPPosIdxOffNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 3116 | // Start at oper_input_base() and count operands |
| 3117 | unsigned idx0 = 2; |
| 3118 | unsigned idx1 = 2; // mem |
| 3119 | st->print_raw("leaq "); |
| 3120 | opnd_array(0)->int_format(ra, this, st); // dst |
| 3121 | st->print_raw(", "); |
| 3122 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 3123 | st->print_raw("\t# ptr posidxoff"); |
| 3124 | } |
| 3125 | #endif |
| 3126 | #ifndef PRODUCT |
| 3127 | void leaPPosIdxScaleOffNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 3128 | // Start at oper_input_base() and count operands |
| 3129 | unsigned idx0 = 2; |
| 3130 | unsigned idx1 = 2; // mem |
| 3131 | st->print_raw("leaq "); |
| 3132 | opnd_array(0)->int_format(ra, this, st); // dst |
| 3133 | st->print_raw(", "); |
| 3134 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 3135 | st->print_raw("\t# ptr posidxscaleoff"); |
| 3136 | } |
| 3137 | #endif |
| 3138 | #ifndef PRODUCT |
| 3139 | void leaPCompressedOopOffsetNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 3140 | // Start at oper_input_base() and count operands |
| 3141 | unsigned idx0 = 2; |
| 3142 | unsigned idx1 = 2; // mem |
| 3143 | st->print_raw("leaq "); |
| 3144 | opnd_array(0)->int_format(ra, this, st); // dst |
| 3145 | st->print_raw(", "); |
| 3146 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 3147 | st->print_raw("\t# ptr compressedoopoff32"); |
| 3148 | } |
| 3149 | #endif |
| 3150 | #ifndef PRODUCT |
| 3151 | void leaP8NarrowNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 3152 | // Start at oper_input_base() and count operands |
| 3153 | unsigned idx0 = 2; |
| 3154 | unsigned idx1 = 2; // mem |
| 3155 | st->print_raw("leaq "); |
| 3156 | opnd_array(0)->int_format(ra, this, st); // dst |
| 3157 | st->print_raw(", "); |
| 3158 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 3159 | st->print_raw("\t# ptr off8narrow"); |
| 3160 | } |
| 3161 | #endif |
| 3162 | #ifndef PRODUCT |
| 3163 | void leaP32NarrowNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 3164 | // Start at oper_input_base() and count operands |
| 3165 | unsigned idx0 = 2; |
| 3166 | unsigned idx1 = 2; // mem |
| 3167 | st->print_raw("leaq "); |
| 3168 | opnd_array(0)->int_format(ra, this, st); // dst |
| 3169 | st->print_raw(", "); |
| 3170 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 3171 | st->print_raw("\t# ptr off32narrow"); |
| 3172 | } |
| 3173 | #endif |
| 3174 | #ifndef PRODUCT |
| 3175 | void leaPIdxOffNarrowNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 3176 | // Start at oper_input_base() and count operands |
| 3177 | unsigned idx0 = 2; |
| 3178 | unsigned idx1 = 2; // mem |
| 3179 | st->print_raw("leaq "); |
| 3180 | opnd_array(0)->int_format(ra, this, st); // dst |
| 3181 | st->print_raw(", "); |
| 3182 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 3183 | st->print_raw("\t# ptr idxoffnarrow"); |
| 3184 | } |
| 3185 | #endif |
| 3186 | #ifndef PRODUCT |
| 3187 | void leaPIdxScaleNarrowNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 3188 | // Start at oper_input_base() and count operands |
| 3189 | unsigned idx0 = 2; |
| 3190 | unsigned idx1 = 2; // mem |
| 3191 | st->print_raw("leaq "); |
| 3192 | opnd_array(0)->int_format(ra, this, st); // dst |
| 3193 | st->print_raw(", "); |
| 3194 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 3195 | st->print_raw("\t# ptr idxscalenarrow"); |
| 3196 | } |
| 3197 | #endif |
| 3198 | #ifndef PRODUCT |
| 3199 | void leaPIdxScaleOffNarrowNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 3200 | // Start at oper_input_base() and count operands |
| 3201 | unsigned idx0 = 2; |
| 3202 | unsigned idx1 = 2; // mem |
| 3203 | st->print_raw("leaq "); |
| 3204 | opnd_array(0)->int_format(ra, this, st); // dst |
| 3205 | st->print_raw(", "); |
| 3206 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 3207 | st->print_raw("\t# ptr idxscaleoffnarrow"); |
| 3208 | } |
| 3209 | #endif |
| 3210 | #ifndef PRODUCT |
| 3211 | void leaPPosIdxOffNarrowNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 3212 | // Start at oper_input_base() and count operands |
| 3213 | unsigned idx0 = 2; |
| 3214 | unsigned idx1 = 2; // mem |
| 3215 | st->print_raw("leaq "); |
| 3216 | opnd_array(0)->int_format(ra, this, st); // dst |
| 3217 | st->print_raw(", "); |
| 3218 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 3219 | st->print_raw("\t# ptr posidxoffnarrow"); |
| 3220 | } |
| 3221 | #endif |
| 3222 | #ifndef PRODUCT |
| 3223 | void leaPPosIdxScaleOffNarrowNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 3224 | // Start at oper_input_base() and count operands |
| 3225 | unsigned idx0 = 2; |
| 3226 | unsigned idx1 = 2; // mem |
| 3227 | st->print_raw("leaq "); |
| 3228 | opnd_array(0)->int_format(ra, this, st); // dst |
| 3229 | st->print_raw(", "); |
| 3230 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 3231 | st->print_raw("\t# ptr posidxscaleoffnarrow"); |
| 3232 | } |
| 3233 | #endif |
| 3234 | #ifndef PRODUCT |
| 3235 | void loadConINode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 3236 | // Start at oper_input_base() and count operands |
| 3237 | unsigned idx0 = 1; |
| 3238 | unsigned idx1 = 1; // src |
| 3239 | st->print_raw("movl "); |
| 3240 | opnd_array(0)->int_format(ra, this, st); // dst |
| 3241 | st->print_raw(", "); |
| 3242 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 3243 | st->print_raw("\t# int"); |
| 3244 | } |
| 3245 | #endif |
| 3246 | #ifndef PRODUCT |
| 3247 | void loadConI0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 3248 | // Start at oper_input_base() and count operands |
| 3249 | unsigned idx0 = 1; |
| 3250 | unsigned idx1 = 1; // src |
| 3251 | st->print_raw("xorl "); |
| 3252 | opnd_array(0)->int_format(ra, this, st); // dst |
| 3253 | st->print_raw(", "); |
| 3254 | opnd_array(0)->int_format(ra, this, st); // dst |
| 3255 | st->print_raw("\t# int"); |
| 3256 | } |
| 3257 | #endif |
| 3258 | #ifndef PRODUCT |
| 3259 | void loadConLNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 3260 | // Start at oper_input_base() and count operands |
| 3261 | unsigned idx0 = 1; |
| 3262 | unsigned idx1 = 1; // src |
| 3263 | st->print_raw("movq "); |
| 3264 | opnd_array(0)->int_format(ra, this, st); // dst |
| 3265 | st->print_raw(", "); |
| 3266 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 3267 | st->print_raw("\t# long"); |
| 3268 | } |
| 3269 | #endif |
| 3270 | #ifndef PRODUCT |
| 3271 | void loadConL0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 3272 | // Start at oper_input_base() and count operands |
| 3273 | unsigned idx0 = 1; |
| 3274 | unsigned idx1 = 1; // src |
| 3275 | st->print_raw("xorl "); |
| 3276 | opnd_array(0)->int_format(ra, this, st); // dst |
| 3277 | st->print_raw(", "); |
| 3278 | opnd_array(0)->int_format(ra, this, st); // dst |
| 3279 | st->print_raw("\t# long"); |
| 3280 | } |
| 3281 | #endif |
| 3282 | #ifndef PRODUCT |
| 3283 | void loadConUL32Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 3284 | // Start at oper_input_base() and count operands |
| 3285 | unsigned idx0 = 1; |
| 3286 | unsigned idx1 = 1; // src |
| 3287 | st->print_raw("movl "); |
| 3288 | opnd_array(0)->int_format(ra, this, st); // dst |
| 3289 | st->print_raw(", "); |
| 3290 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 3291 | st->print_raw("\t# long (unsigned 32-bit)"); |
| 3292 | } |
| 3293 | #endif |
| 3294 | #ifndef PRODUCT |
| 3295 | void loadConL32Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 3296 | // Start at oper_input_base() and count operands |
| 3297 | unsigned idx0 = 1; |
| 3298 | unsigned idx1 = 1; // src |
| 3299 | st->print_raw("movq "); |
| 3300 | opnd_array(0)->int_format(ra, this, st); // dst |
| 3301 | st->print_raw(", "); |
| 3302 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 3303 | st->print_raw("\t# long (32-bit)"); |
| 3304 | } |
| 3305 | #endif |
| 3306 | #ifndef PRODUCT |
| 3307 | void loadConPNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 3308 | // Start at oper_input_base() and count operands |
| 3309 | unsigned idx0 = 1; |
| 3310 | unsigned idx1 = 1; // con |
| 3311 | st->print_raw("movq "); |
| 3312 | opnd_array(0)->int_format(ra, this, st); // dst |
| 3313 | st->print_raw(", "); |
| 3314 | opnd_array(1)->ext_format(ra, this,idx1, st); // con |
| 3315 | st->print_raw("\t# ptr"); |
| 3316 | } |
| 3317 | #endif |
| 3318 | #ifndef PRODUCT |
| 3319 | void loadConP0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 3320 | // Start at oper_input_base() and count operands |
| 3321 | unsigned idx0 = 1; |
| 3322 | unsigned idx1 = 1; // src |
| 3323 | st->print_raw("xorl "); |
| 3324 | opnd_array(0)->int_format(ra, this, st); // dst |
| 3325 | st->print_raw(", "); |
| 3326 | opnd_array(0)->int_format(ra, this, st); // dst |
| 3327 | st->print_raw("\t# ptr"); |
| 3328 | } |
| 3329 | #endif |
| 3330 | #ifndef PRODUCT |
| 3331 | void loadConP31Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 3332 | // Start at oper_input_base() and count operands |
| 3333 | unsigned idx0 = 1; |
| 3334 | unsigned idx1 = 1; // src |
| 3335 | st->print_raw("movl "); |
| 3336 | opnd_array(0)->int_format(ra, this, st); // dst |
| 3337 | st->print_raw(", "); |
| 3338 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 3339 | st->print_raw("\t# ptr (positive 32-bit)"); |
| 3340 | } |
| 3341 | #endif |
| 3342 | #ifndef PRODUCT |
| 3343 | void loadConFNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 3344 | // Start at oper_input_base() and count operands |
| 3345 | unsigned idx0 = 1; |
| 3346 | unsigned idx1 = 1; // con |
| 3347 | st->print_raw("movss "); |
| 3348 | opnd_array(0)->int_format(ra, this, st); // dst |
| 3349 | st->print_raw(", ["); |
| 3350 | st->print("constant table base + #%d", constant_offset_unchecked()); |
| 3351 | st->print_raw("]\t# load from constant table: float="); |
| 3352 | opnd_array(1)->ext_format(ra, this,idx1, st); // con |
| 3353 | } |
| 3354 | #endif |
| 3355 | #ifndef PRODUCT |
| 3356 | void loadConN0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 3357 | // Start at oper_input_base() and count operands |
| 3358 | unsigned idx0 = 1; |
| 3359 | unsigned idx1 = 1; // src |
| 3360 | st->print_raw("xorq "); |
| 3361 | opnd_array(0)->int_format(ra, this, st); // dst |
| 3362 | st->print_raw(", "); |
| 3363 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 3364 | st->print_raw("\t# compressed NULL ptr"); |
| 3365 | } |
| 3366 | #endif |
| 3367 | #ifndef PRODUCT |
| 3368 | void loadConNNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 3369 | // Start at oper_input_base() and count operands |
| 3370 | unsigned idx0 = 1; |
| 3371 | unsigned idx1 = 1; // src |
| 3372 | st->print_raw("movl "); |
| 3373 | opnd_array(0)->int_format(ra, this, st); // dst |
| 3374 | st->print_raw(", "); |
| 3375 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 3376 | st->print_raw("\t# compressed ptr"); |
| 3377 | } |
| 3378 | #endif |
| 3379 | #ifndef PRODUCT |
| 3380 | void loadConNKlassNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 3381 | // Start at oper_input_base() and count operands |
| 3382 | unsigned idx0 = 1; |
| 3383 | unsigned idx1 = 1; // src |
| 3384 | st->print_raw("movl "); |
| 3385 | opnd_array(0)->int_format(ra, this, st); // dst |
| 3386 | st->print_raw(", "); |
| 3387 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 3388 | st->print_raw("\t# compressed klass ptr"); |
| 3389 | } |
| 3390 | #endif |
| 3391 | #ifndef PRODUCT |
| 3392 | void loadConF0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 3393 | // Start at oper_input_base() and count operands |
| 3394 | unsigned idx0 = 1; |
| 3395 | unsigned idx1 = 1; // src |
| 3396 | st->print_raw("xorps "); |
| 3397 | opnd_array(0)->int_format(ra, this, st); // dst |
| 3398 | st->print_raw(", "); |
| 3399 | opnd_array(0)->int_format(ra, this, st); // dst |
| 3400 | st->print_raw("\t# float 0.0"); |
| 3401 | } |
| 3402 | #endif |
| 3403 | #ifndef PRODUCT |
| 3404 | void loadConDNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 3405 | // Start at oper_input_base() and count operands |
| 3406 | unsigned idx0 = 1; |
| 3407 | unsigned idx1 = 1; // con |
| 3408 | st->print_raw("movsd "); |
| 3409 | opnd_array(0)->int_format(ra, this, st); // dst |
| 3410 | st->print_raw(", ["); |
| 3411 | st->print("constant table base + #%d", constant_offset_unchecked()); |
| 3412 | st->print_raw("]\t# load from constant table: double="); |
| 3413 | opnd_array(1)->ext_format(ra, this,idx1, st); // con |
| 3414 | } |
| 3415 | #endif |
| 3416 | #ifndef PRODUCT |
| 3417 | void loadConD0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 3418 | // Start at oper_input_base() and count operands |
| 3419 | unsigned idx0 = 1; |
| 3420 | unsigned idx1 = 1; // src |
| 3421 | st->print_raw("xorpd "); |
| 3422 | opnd_array(0)->int_format(ra, this, st); // dst |
| 3423 | st->print_raw(", "); |
| 3424 | opnd_array(0)->int_format(ra, this, st); // dst |
| 3425 | st->print_raw("\t# double 0.0"); |
| 3426 | } |
| 3427 | #endif |
| 3428 | #ifndef PRODUCT |
| 3429 | void loadSSINode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 3430 | // Start at oper_input_base() and count operands |
| 3431 | unsigned idx0 = 1; |
| 3432 | unsigned idx1 = 1; // src |
| 3433 | st->print_raw("movl "); |
| 3434 | opnd_array(0)->int_format(ra, this, st); // dst |
| 3435 | st->print_raw(", "); |
| 3436 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 3437 | st->print_raw("\t# int stk"); |
| 3438 | } |
| 3439 | #endif |
| 3440 | #ifndef PRODUCT |
| 3441 | void loadSSLNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 3442 | // Start at oper_input_base() and count operands |
| 3443 | unsigned idx0 = 1; |
| 3444 | unsigned idx1 = 1; // src |
| 3445 | st->print_raw("movq "); |
| 3446 | opnd_array(0)->int_format(ra, this, st); // dst |
| 3447 | st->print_raw(", "); |
| 3448 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 3449 | st->print_raw("\t# long stk"); |
| 3450 | } |
| 3451 | #endif |
| 3452 | #ifndef PRODUCT |
| 3453 | void loadSSPNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 3454 | // Start at oper_input_base() and count operands |
| 3455 | unsigned idx0 = 1; |
| 3456 | unsigned idx1 = 1; // src |
| 3457 | st->print_raw("movq "); |
| 3458 | opnd_array(0)->int_format(ra, this, st); // dst |
| 3459 | st->print_raw(", "); |
| 3460 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 3461 | st->print_raw("\t# ptr stk"); |
| 3462 | } |
| 3463 | #endif |
| 3464 | #ifndef PRODUCT |
| 3465 | void loadSSFNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 3466 | // Start at oper_input_base() and count operands |
| 3467 | unsigned idx0 = 1; |
| 3468 | unsigned idx1 = 1; // src |
| 3469 | st->print_raw("movss "); |
| 3470 | opnd_array(0)->int_format(ra, this, st); // dst |
| 3471 | st->print_raw(", "); |
| 3472 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 3473 | st->print_raw("\t# float stk"); |
| 3474 | } |
| 3475 | #endif |
| 3476 | #ifndef PRODUCT |
| 3477 | void loadSSDNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 3478 | // Start at oper_input_base() and count operands |
| 3479 | unsigned idx0 = 1; |
| 3480 | unsigned idx1 = 1; // src |
| 3481 | st->print_raw("movsd "); |
| 3482 | opnd_array(0)->int_format(ra, this, st); // dst |
| 3483 | st->print_raw(", "); |
| 3484 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 3485 | st->print_raw("\t# double stk"); |
| 3486 | } |
| 3487 | #endif |
| 3488 | #ifndef PRODUCT |
| 3489 | void prefetchAllocNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 3490 | // Start at oper_input_base() and count operands |
| 3491 | unsigned idx0 = 2; |
| 3492 | unsigned idx1 = 2; // |
| 3493 | st->print_raw("PREFETCHW "); |
| 3494 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 3495 | st->print_raw("\t# Prefetch allocation into level 1 cache and mark modified"); |
| 3496 | } |
| 3497 | #endif |
| 3498 | #ifndef PRODUCT |
| 3499 | void prefetchAllocNTANode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 3500 | // Start at oper_input_base() and count operands |
| 3501 | unsigned idx0 = 2; |
| 3502 | unsigned idx1 = 2; // |
| 3503 | st->print_raw("PREFETCHNTA "); |
| 3504 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 3505 | st->print_raw("\t# Prefetch allocation to non-temporal cache for write"); |
| 3506 | } |
| 3507 | #endif |
| 3508 | #ifndef PRODUCT |
| 3509 | void prefetchAllocT0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 3510 | // Start at oper_input_base() and count operands |
| 3511 | unsigned idx0 = 2; |
| 3512 | unsigned idx1 = 2; // |
| 3513 | st->print_raw("PREFETCHT0 "); |
| 3514 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 3515 | st->print_raw("\t# Prefetch allocation to level 1 and 2 caches for write"); |
| 3516 | } |
| 3517 | #endif |
| 3518 | #ifndef PRODUCT |
| 3519 | void prefetchAllocT2Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 3520 | // Start at oper_input_base() and count operands |
| 3521 | unsigned idx0 = 2; |
| 3522 | unsigned idx1 = 2; // |
| 3523 | st->print_raw("PREFETCHT2 "); |
| 3524 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 3525 | st->print_raw("\t# Prefetch allocation to level 2 cache for write"); |
| 3526 | } |
| 3527 | #endif |
| 3528 | #ifndef PRODUCT |
| 3529 | void storeBNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 3530 | // Start at oper_input_base() and count operands |
| 3531 | unsigned idx0 = 2; |
| 3532 | unsigned idx1 = 2; // mem |
| 3533 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 3534 | st->print_raw("movb "); |
| 3535 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 3536 | st->print_raw(", "); |
| 3537 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 3538 | st->print_raw("\t# byte"); |
| 3539 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 3540 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 3541 | st->print(" ! Field: "); |
| 3542 | if (f->is_volatile()) |
| 3543 | st->print("volatile "); |
| 3544 | f->holder()->name()->print_symbol_on(st); |
| 3545 | st->print("."); |
| 3546 | f->name()->print_symbol_on(st); |
| 3547 | if (f->is_constant()) |
| 3548 | st->print(" (constant)"); |
| 3549 | } else { |
| 3550 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 3551 | st->print(" volatile!"); |
| 3552 | } |
| 3553 | } |
| 3554 | #endif |
| 3555 | #ifndef PRODUCT |
| 3556 | void storeCNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 3557 | // Start at oper_input_base() and count operands |
| 3558 | unsigned idx0 = 2; |
| 3559 | unsigned idx1 = 2; // mem |
| 3560 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 3561 | st->print_raw("movw "); |
| 3562 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 3563 | st->print_raw(", "); |
| 3564 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 3565 | st->print_raw("\t# char/short"); |
| 3566 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 3567 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 3568 | st->print(" ! Field: "); |
| 3569 | if (f->is_volatile()) |
| 3570 | st->print("volatile "); |
| 3571 | f->holder()->name()->print_symbol_on(st); |
| 3572 | st->print("."); |
| 3573 | f->name()->print_symbol_on(st); |
| 3574 | if (f->is_constant()) |
| 3575 | st->print(" (constant)"); |
| 3576 | } else { |
| 3577 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 3578 | st->print(" volatile!"); |
| 3579 | } |
| 3580 | } |
| 3581 | #endif |
| 3582 | #ifndef PRODUCT |
| 3583 | void storeINode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 3584 | // Start at oper_input_base() and count operands |
| 3585 | unsigned idx0 = 2; |
| 3586 | unsigned idx1 = 2; // mem |
| 3587 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 3588 | st->print_raw("movl "); |
| 3589 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 3590 | st->print_raw(", "); |
| 3591 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 3592 | st->print_raw("\t# int"); |
| 3593 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 3594 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 3595 | st->print(" ! Field: "); |
| 3596 | if (f->is_volatile()) |
| 3597 | st->print("volatile "); |
| 3598 | f->holder()->name()->print_symbol_on(st); |
| 3599 | st->print("."); |
| 3600 | f->name()->print_symbol_on(st); |
| 3601 | if (f->is_constant()) |
| 3602 | st->print(" (constant)"); |
| 3603 | } else { |
| 3604 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 3605 | st->print(" volatile!"); |
| 3606 | } |
| 3607 | } |
| 3608 | #endif |
| 3609 | #ifndef PRODUCT |
| 3610 | void storeLNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 3611 | // Start at oper_input_base() and count operands |
| 3612 | unsigned idx0 = 2; |
| 3613 | unsigned idx1 = 2; // mem |
| 3614 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 3615 | st->print_raw("movq "); |
| 3616 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 3617 | st->print_raw(", "); |
| 3618 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 3619 | st->print_raw("\t# long"); |
| 3620 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 3621 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 3622 | st->print(" ! Field: "); |
| 3623 | if (f->is_volatile()) |
| 3624 | st->print("volatile "); |
| 3625 | f->holder()->name()->print_symbol_on(st); |
| 3626 | st->print("."); |
| 3627 | f->name()->print_symbol_on(st); |
| 3628 | if (f->is_constant()) |
| 3629 | st->print(" (constant)"); |
| 3630 | } else { |
| 3631 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 3632 | st->print(" volatile!"); |
| 3633 | } |
| 3634 | } |
| 3635 | #endif |
| 3636 | #ifndef PRODUCT |
| 3637 | void storePNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 3638 | // Start at oper_input_base() and count operands |
| 3639 | unsigned idx0 = 2; |
| 3640 | unsigned idx1 = 2; // mem |
| 3641 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 3642 | st->print_raw("movq "); |
| 3643 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 3644 | st->print_raw(", "); |
| 3645 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 3646 | st->print_raw("\t# ptr"); |
| 3647 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 3648 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 3649 | st->print(" ! Field: "); |
| 3650 | if (f->is_volatile()) |
| 3651 | st->print("volatile "); |
| 3652 | f->holder()->name()->print_symbol_on(st); |
| 3653 | st->print("."); |
| 3654 | f->name()->print_symbol_on(st); |
| 3655 | if (f->is_constant()) |
| 3656 | st->print(" (constant)"); |
| 3657 | } else { |
| 3658 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 3659 | st->print(" volatile!"); |
| 3660 | } |
| 3661 | } |
| 3662 | #endif |
| 3663 | #ifndef PRODUCT |
| 3664 | void storeImmP0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 3665 | // Start at oper_input_base() and count operands |
| 3666 | unsigned idx0 = 2; |
| 3667 | unsigned idx1 = 2; // mem |
| 3668 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero |
| 3669 | st->print_raw("movq "); |
| 3670 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 3671 | st->print_raw(", R12\t# ptr (R12_heapbase==0)"); |
| 3672 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 3673 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 3674 | st->print(" ! Field: "); |
| 3675 | if (f->is_volatile()) |
| 3676 | st->print("volatile "); |
| 3677 | f->holder()->name()->print_symbol_on(st); |
| 3678 | st->print("."); |
| 3679 | f->name()->print_symbol_on(st); |
| 3680 | if (f->is_constant()) |
| 3681 | st->print(" (constant)"); |
| 3682 | } else { |
| 3683 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 3684 | st->print(" volatile!"); |
| 3685 | } |
| 3686 | } |
| 3687 | #endif |
| 3688 | #ifndef PRODUCT |
| 3689 | void storeImmPNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 3690 | // Start at oper_input_base() and count operands |
| 3691 | unsigned idx0 = 2; |
| 3692 | unsigned idx1 = 2; // mem |
| 3693 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 3694 | st->print_raw("movq "); |
| 3695 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 3696 | st->print_raw(", "); |
| 3697 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 3698 | st->print_raw("\t# ptr"); |
| 3699 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 3700 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 3701 | st->print(" ! Field: "); |
| 3702 | if (f->is_volatile()) |
| 3703 | st->print("volatile "); |
| 3704 | f->holder()->name()->print_symbol_on(st); |
| 3705 | st->print("."); |
| 3706 | f->name()->print_symbol_on(st); |
| 3707 | if (f->is_constant()) |
| 3708 | st->print(" (constant)"); |
| 3709 | } else { |
| 3710 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 3711 | st->print(" volatile!"); |
| 3712 | } |
| 3713 | } |
| 3714 | #endif |
| 3715 | #ifndef PRODUCT |
| 3716 | void storeNNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 3717 | // Start at oper_input_base() and count operands |
| 3718 | unsigned idx0 = 2; |
| 3719 | unsigned idx1 = 2; // mem |
| 3720 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 3721 | st->print_raw("movl "); |
| 3722 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 3723 | st->print_raw(", "); |
| 3724 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 3725 | st->print_raw("\t# compressed ptr"); |
| 3726 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 3727 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 3728 | st->print(" ! Field: "); |
| 3729 | if (f->is_volatile()) |
| 3730 | st->print("volatile "); |
| 3731 | f->holder()->name()->print_symbol_on(st); |
| 3732 | st->print("."); |
| 3733 | f->name()->print_symbol_on(st); |
| 3734 | if (f->is_constant()) |
| 3735 | st->print(" (constant)"); |
| 3736 | } else { |
| 3737 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 3738 | st->print(" volatile!"); |
| 3739 | } |
| 3740 | } |
| 3741 | #endif |
| 3742 | #ifndef PRODUCT |
| 3743 | void storeNKlassNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 3744 | // Start at oper_input_base() and count operands |
| 3745 | unsigned idx0 = 2; |
| 3746 | unsigned idx1 = 2; // mem |
| 3747 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 3748 | st->print_raw("movl "); |
| 3749 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 3750 | st->print_raw(", "); |
| 3751 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 3752 | st->print_raw("\t# compressed klass ptr"); |
| 3753 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 3754 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 3755 | st->print(" ! Field: "); |
| 3756 | if (f->is_volatile()) |
| 3757 | st->print("volatile "); |
| 3758 | f->holder()->name()->print_symbol_on(st); |
| 3759 | st->print("."); |
| 3760 | f->name()->print_symbol_on(st); |
| 3761 | if (f->is_constant()) |
| 3762 | st->print(" (constant)"); |
| 3763 | } else { |
| 3764 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 3765 | st->print(" volatile!"); |
| 3766 | } |
| 3767 | } |
| 3768 | #endif |
| 3769 | #ifndef PRODUCT |
| 3770 | void storeImmN0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 3771 | // Start at oper_input_base() and count operands |
| 3772 | unsigned idx0 = 2; |
| 3773 | unsigned idx1 = 2; // mem |
| 3774 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero |
| 3775 | st->print_raw("movl "); |
| 3776 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 3777 | st->print_raw(", R12\t# compressed ptr (R12_heapbase==0)"); |
| 3778 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 3779 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 3780 | st->print(" ! Field: "); |
| 3781 | if (f->is_volatile()) |
| 3782 | st->print("volatile "); |
| 3783 | f->holder()->name()->print_symbol_on(st); |
| 3784 | st->print("."); |
| 3785 | f->name()->print_symbol_on(st); |
| 3786 | if (f->is_constant()) |
| 3787 | st->print(" (constant)"); |
| 3788 | } else { |
| 3789 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 3790 | st->print(" volatile!"); |
| 3791 | } |
| 3792 | } |
| 3793 | #endif |
| 3794 | #ifndef PRODUCT |
| 3795 | void storeImmNNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 3796 | // Start at oper_input_base() and count operands |
| 3797 | unsigned idx0 = 2; |
| 3798 | unsigned idx1 = 2; // mem |
| 3799 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 3800 | st->print_raw("movl "); |
| 3801 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 3802 | st->print_raw(", "); |
| 3803 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 3804 | st->print_raw("\t# compressed ptr"); |
| 3805 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 3806 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 3807 | st->print(" ! Field: "); |
| 3808 | if (f->is_volatile()) |
| 3809 | st->print("volatile "); |
| 3810 | f->holder()->name()->print_symbol_on(st); |
| 3811 | st->print("."); |
| 3812 | f->name()->print_symbol_on(st); |
| 3813 | if (f->is_constant()) |
| 3814 | st->print(" (constant)"); |
| 3815 | } else { |
| 3816 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 3817 | st->print(" volatile!"); |
| 3818 | } |
| 3819 | } |
| 3820 | #endif |
| 3821 | #ifndef PRODUCT |
| 3822 | void storeImmNKlassNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 3823 | // Start at oper_input_base() and count operands |
| 3824 | unsigned idx0 = 2; |
| 3825 | unsigned idx1 = 2; // mem |
| 3826 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 3827 | st->print_raw("movl "); |
| 3828 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 3829 | st->print_raw(", "); |
| 3830 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 3831 | st->print_raw("\t# compressed klass ptr"); |
| 3832 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 3833 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 3834 | st->print(" ! Field: "); |
| 3835 | if (f->is_volatile()) |
| 3836 | st->print("volatile "); |
| 3837 | f->holder()->name()->print_symbol_on(st); |
| 3838 | st->print("."); |
| 3839 | f->name()->print_symbol_on(st); |
| 3840 | if (f->is_constant()) |
| 3841 | st->print(" (constant)"); |
| 3842 | } else { |
| 3843 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 3844 | st->print(" volatile!"); |
| 3845 | } |
| 3846 | } |
| 3847 | #endif |
| 3848 | #ifndef PRODUCT |
| 3849 | void storeImmI0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 3850 | // Start at oper_input_base() and count operands |
| 3851 | unsigned idx0 = 2; |
| 3852 | unsigned idx1 = 2; // mem |
| 3853 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero |
| 3854 | st->print_raw("movl "); |
| 3855 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 3856 | st->print_raw(", R12\t# int (R12_heapbase==0)"); |
| 3857 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 3858 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 3859 | st->print(" ! Field: "); |
| 3860 | if (f->is_volatile()) |
| 3861 | st->print("volatile "); |
| 3862 | f->holder()->name()->print_symbol_on(st); |
| 3863 | st->print("."); |
| 3864 | f->name()->print_symbol_on(st); |
| 3865 | if (f->is_constant()) |
| 3866 | st->print(" (constant)"); |
| 3867 | } else { |
| 3868 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 3869 | st->print(" volatile!"); |
| 3870 | } |
| 3871 | } |
| 3872 | #endif |
| 3873 | #ifndef PRODUCT |
| 3874 | void storeImmINode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 3875 | // Start at oper_input_base() and count operands |
| 3876 | unsigned idx0 = 2; |
| 3877 | unsigned idx1 = 2; // mem |
| 3878 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 3879 | st->print_raw("movl "); |
| 3880 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 3881 | st->print_raw(", "); |
| 3882 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 3883 | st->print_raw("\t# int"); |
| 3884 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 3885 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 3886 | st->print(" ! Field: "); |
| 3887 | if (f->is_volatile()) |
| 3888 | st->print("volatile "); |
| 3889 | f->holder()->name()->print_symbol_on(st); |
| 3890 | st->print("."); |
| 3891 | f->name()->print_symbol_on(st); |
| 3892 | if (f->is_constant()) |
| 3893 | st->print(" (constant)"); |
| 3894 | } else { |
| 3895 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 3896 | st->print(" volatile!"); |
| 3897 | } |
| 3898 | } |
| 3899 | #endif |
| 3900 | #ifndef PRODUCT |
| 3901 | void storeImmL0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 3902 | // Start at oper_input_base() and count operands |
| 3903 | unsigned idx0 = 2; |
| 3904 | unsigned idx1 = 2; // mem |
| 3905 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero |
| 3906 | st->print_raw("movq "); |
| 3907 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 3908 | st->print_raw(", R12\t# long (R12_heapbase==0)"); |
| 3909 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 3910 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 3911 | st->print(" ! Field: "); |
| 3912 | if (f->is_volatile()) |
| 3913 | st->print("volatile "); |
| 3914 | f->holder()->name()->print_symbol_on(st); |
| 3915 | st->print("."); |
| 3916 | f->name()->print_symbol_on(st); |
| 3917 | if (f->is_constant()) |
| 3918 | st->print(" (constant)"); |
| 3919 | } else { |
| 3920 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 3921 | st->print(" volatile!"); |
| 3922 | } |
| 3923 | } |
| 3924 | #endif |
| 3925 | #ifndef PRODUCT |
| 3926 | void storeImmLNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 3927 | // Start at oper_input_base() and count operands |
| 3928 | unsigned idx0 = 2; |
| 3929 | unsigned idx1 = 2; // mem |
| 3930 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 3931 | st->print_raw("movq "); |
| 3932 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 3933 | st->print_raw(", "); |
| 3934 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 3935 | st->print_raw("\t# long"); |
| 3936 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 3937 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 3938 | st->print(" ! Field: "); |
| 3939 | if (f->is_volatile()) |
| 3940 | st->print("volatile "); |
| 3941 | f->holder()->name()->print_symbol_on(st); |
| 3942 | st->print("."); |
| 3943 | f->name()->print_symbol_on(st); |
| 3944 | if (f->is_constant()) |
| 3945 | st->print(" (constant)"); |
| 3946 | } else { |
| 3947 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 3948 | st->print(" volatile!"); |
| 3949 | } |
| 3950 | } |
| 3951 | #endif |
| 3952 | #ifndef PRODUCT |
| 3953 | void storeImmC0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 3954 | // Start at oper_input_base() and count operands |
| 3955 | unsigned idx0 = 2; |
| 3956 | unsigned idx1 = 2; // mem |
| 3957 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero |
| 3958 | st->print_raw("movw "); |
| 3959 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 3960 | st->print_raw(", R12\t# short/char (R12_heapbase==0)"); |
| 3961 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 3962 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 3963 | st->print(" ! Field: "); |
| 3964 | if (f->is_volatile()) |
| 3965 | st->print("volatile "); |
| 3966 | f->holder()->name()->print_symbol_on(st); |
| 3967 | st->print("."); |
| 3968 | f->name()->print_symbol_on(st); |
| 3969 | if (f->is_constant()) |
| 3970 | st->print(" (constant)"); |
| 3971 | } else { |
| 3972 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 3973 | st->print(" volatile!"); |
| 3974 | } |
| 3975 | } |
| 3976 | #endif |
| 3977 | #ifndef PRODUCT |
| 3978 | void storeImmI16Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 3979 | // Start at oper_input_base() and count operands |
| 3980 | unsigned idx0 = 2; |
| 3981 | unsigned idx1 = 2; // mem |
| 3982 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 3983 | st->print_raw("movw "); |
| 3984 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 3985 | st->print_raw(", "); |
| 3986 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 3987 | st->print_raw("\t# short/char"); |
| 3988 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 3989 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 3990 | st->print(" ! Field: "); |
| 3991 | if (f->is_volatile()) |
| 3992 | st->print("volatile "); |
| 3993 | f->holder()->name()->print_symbol_on(st); |
| 3994 | st->print("."); |
| 3995 | f->name()->print_symbol_on(st); |
| 3996 | if (f->is_constant()) |
| 3997 | st->print(" (constant)"); |
| 3998 | } else { |
| 3999 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 4000 | st->print(" volatile!"); |
| 4001 | } |
| 4002 | } |
| 4003 | #endif |
| 4004 | #ifndef PRODUCT |
| 4005 | void storeImmB0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4006 | // Start at oper_input_base() and count operands |
| 4007 | unsigned idx0 = 2; |
| 4008 | unsigned idx1 = 2; // mem |
| 4009 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero |
| 4010 | st->print_raw("movb "); |
| 4011 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 4012 | st->print_raw(", R12\t# short/char (R12_heapbase==0)"); |
| 4013 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 4014 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 4015 | st->print(" ! Field: "); |
| 4016 | if (f->is_volatile()) |
| 4017 | st->print("volatile "); |
| 4018 | f->holder()->name()->print_symbol_on(st); |
| 4019 | st->print("."); |
| 4020 | f->name()->print_symbol_on(st); |
| 4021 | if (f->is_constant()) |
| 4022 | st->print(" (constant)"); |
| 4023 | } else { |
| 4024 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 4025 | st->print(" volatile!"); |
| 4026 | } |
| 4027 | } |
| 4028 | #endif |
| 4029 | #ifndef PRODUCT |
| 4030 | void storeImmBNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4031 | // Start at oper_input_base() and count operands |
| 4032 | unsigned idx0 = 2; |
| 4033 | unsigned idx1 = 2; // mem |
| 4034 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 4035 | st->print_raw("movb "); |
| 4036 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 4037 | st->print_raw(", "); |
| 4038 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 4039 | st->print_raw("\t# byte"); |
| 4040 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 4041 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 4042 | st->print(" ! Field: "); |
| 4043 | if (f->is_volatile()) |
| 4044 | st->print("volatile "); |
| 4045 | f->holder()->name()->print_symbol_on(st); |
| 4046 | st->print("."); |
| 4047 | f->name()->print_symbol_on(st); |
| 4048 | if (f->is_constant()) |
| 4049 | st->print(" (constant)"); |
| 4050 | } else { |
| 4051 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 4052 | st->print(" volatile!"); |
| 4053 | } |
| 4054 | } |
| 4055 | #endif |
| 4056 | #ifndef PRODUCT |
| 4057 | void storeImmCM0_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4058 | // Start at oper_input_base() and count operands |
| 4059 | unsigned idx0 = 2; |
| 4060 | unsigned idx1 = 2; // mem |
| 4061 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero |
| 4062 | st->print_raw("movb "); |
| 4063 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 4064 | st->print_raw(", R12\t# CMS card-mark byte 0 (R12_heapbase==0)"); |
| 4065 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 4066 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 4067 | st->print(" ! Field: "); |
| 4068 | if (f->is_volatile()) |
| 4069 | st->print("volatile "); |
| 4070 | f->holder()->name()->print_symbol_on(st); |
| 4071 | st->print("."); |
| 4072 | f->name()->print_symbol_on(st); |
| 4073 | if (f->is_constant()) |
| 4074 | st->print(" (constant)"); |
| 4075 | } else { |
| 4076 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 4077 | st->print(" volatile!"); |
| 4078 | } |
| 4079 | } |
| 4080 | #endif |
| 4081 | #ifndef PRODUCT |
| 4082 | void storeImmCM0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4083 | // Start at oper_input_base() and count operands |
| 4084 | unsigned idx0 = 2; |
| 4085 | unsigned idx1 = 2; // mem |
| 4086 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 4087 | st->print_raw("movb "); |
| 4088 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 4089 | st->print_raw(", "); |
| 4090 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 4091 | st->print_raw("\t# CMS card-mark byte 0"); |
| 4092 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 4093 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 4094 | st->print(" ! Field: "); |
| 4095 | if (f->is_volatile()) |
| 4096 | st->print("volatile "); |
| 4097 | f->holder()->name()->print_symbol_on(st); |
| 4098 | st->print("."); |
| 4099 | f->name()->print_symbol_on(st); |
| 4100 | if (f->is_constant()) |
| 4101 | st->print(" (constant)"); |
| 4102 | } else { |
| 4103 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 4104 | st->print(" volatile!"); |
| 4105 | } |
| 4106 | } |
| 4107 | #endif |
| 4108 | #ifndef PRODUCT |
| 4109 | void storeFNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4110 | // Start at oper_input_base() and count operands |
| 4111 | unsigned idx0 = 2; |
| 4112 | unsigned idx1 = 2; // mem |
| 4113 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 4114 | st->print_raw("movss "); |
| 4115 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 4116 | st->print_raw(", "); |
| 4117 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 4118 | st->print_raw("\t# float"); |
| 4119 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 4120 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 4121 | st->print(" ! Field: "); |
| 4122 | if (f->is_volatile()) |
| 4123 | st->print("volatile "); |
| 4124 | f->holder()->name()->print_symbol_on(st); |
| 4125 | st->print("."); |
| 4126 | f->name()->print_symbol_on(st); |
| 4127 | if (f->is_constant()) |
| 4128 | st->print(" (constant)"); |
| 4129 | } else { |
| 4130 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 4131 | st->print(" volatile!"); |
| 4132 | } |
| 4133 | } |
| 4134 | #endif |
| 4135 | #ifndef PRODUCT |
| 4136 | void storeF0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4137 | // Start at oper_input_base() and count operands |
| 4138 | unsigned idx0 = 2; |
| 4139 | unsigned idx1 = 2; // mem |
| 4140 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero |
| 4141 | st->print_raw("movl "); |
| 4142 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 4143 | st->print_raw(", R12\t# float 0. (R12_heapbase==0)"); |
| 4144 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 4145 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 4146 | st->print(" ! Field: "); |
| 4147 | if (f->is_volatile()) |
| 4148 | st->print("volatile "); |
| 4149 | f->holder()->name()->print_symbol_on(st); |
| 4150 | st->print("."); |
| 4151 | f->name()->print_symbol_on(st); |
| 4152 | if (f->is_constant()) |
| 4153 | st->print(" (constant)"); |
| 4154 | } else { |
| 4155 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 4156 | st->print(" volatile!"); |
| 4157 | } |
| 4158 | } |
| 4159 | #endif |
| 4160 | #ifndef PRODUCT |
| 4161 | void storeF_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4162 | // Start at oper_input_base() and count operands |
| 4163 | unsigned idx0 = 2; |
| 4164 | unsigned idx1 = 2; // mem |
| 4165 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 4166 | st->print_raw("movl "); |
| 4167 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 4168 | st->print_raw(", "); |
| 4169 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 4170 | st->print_raw("\t# float"); |
| 4171 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 4172 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 4173 | st->print(" ! Field: "); |
| 4174 | if (f->is_volatile()) |
| 4175 | st->print("volatile "); |
| 4176 | f->holder()->name()->print_symbol_on(st); |
| 4177 | st->print("."); |
| 4178 | f->name()->print_symbol_on(st); |
| 4179 | if (f->is_constant()) |
| 4180 | st->print(" (constant)"); |
| 4181 | } else { |
| 4182 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 4183 | st->print(" volatile!"); |
| 4184 | } |
| 4185 | } |
| 4186 | #endif |
| 4187 | #ifndef PRODUCT |
| 4188 | void storeDNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4189 | // Start at oper_input_base() and count operands |
| 4190 | unsigned idx0 = 2; |
| 4191 | unsigned idx1 = 2; // mem |
| 4192 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 4193 | st->print_raw("movsd "); |
| 4194 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 4195 | st->print_raw(", "); |
| 4196 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 4197 | st->print_raw("\t# double"); |
| 4198 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 4199 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 4200 | st->print(" ! Field: "); |
| 4201 | if (f->is_volatile()) |
| 4202 | st->print("volatile "); |
| 4203 | f->holder()->name()->print_symbol_on(st); |
| 4204 | st->print("."); |
| 4205 | f->name()->print_symbol_on(st); |
| 4206 | if (f->is_constant()) |
| 4207 | st->print(" (constant)"); |
| 4208 | } else { |
| 4209 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 4210 | st->print(" volatile!"); |
| 4211 | } |
| 4212 | } |
| 4213 | #endif |
| 4214 | #ifndef PRODUCT |
| 4215 | void storeD0_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4216 | // Start at oper_input_base() and count operands |
| 4217 | unsigned idx0 = 2; |
| 4218 | unsigned idx1 = 2; // mem |
| 4219 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 4220 | st->print_raw("movq "); |
| 4221 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 4222 | st->print_raw(", "); |
| 4223 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 4224 | st->print_raw("\t# double 0."); |
| 4225 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 4226 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 4227 | st->print(" ! Field: "); |
| 4228 | if (f->is_volatile()) |
| 4229 | st->print("volatile "); |
| 4230 | f->holder()->name()->print_symbol_on(st); |
| 4231 | st->print("."); |
| 4232 | f->name()->print_symbol_on(st); |
| 4233 | if (f->is_constant()) |
| 4234 | st->print(" (constant)"); |
| 4235 | } else { |
| 4236 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 4237 | st->print(" volatile!"); |
| 4238 | } |
| 4239 | } |
| 4240 | #endif |
| 4241 | #ifndef PRODUCT |
| 4242 | void storeD0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4243 | // Start at oper_input_base() and count operands |
| 4244 | unsigned idx0 = 2; |
| 4245 | unsigned idx1 = 2; // mem |
| 4246 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero |
| 4247 | st->print_raw("movq "); |
| 4248 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 4249 | st->print_raw(", R12\t# double 0. (R12_heapbase==0)"); |
| 4250 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 4251 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 4252 | st->print(" ! Field: "); |
| 4253 | if (f->is_volatile()) |
| 4254 | st->print("volatile "); |
| 4255 | f->holder()->name()->print_symbol_on(st); |
| 4256 | st->print("."); |
| 4257 | f->name()->print_symbol_on(st); |
| 4258 | if (f->is_constant()) |
| 4259 | st->print(" (constant)"); |
| 4260 | } else { |
| 4261 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 4262 | st->print(" volatile!"); |
| 4263 | } |
| 4264 | } |
| 4265 | #endif |
| 4266 | #ifndef PRODUCT |
| 4267 | void storeSSINode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4268 | // Start at oper_input_base() and count operands |
| 4269 | unsigned idx0 = 1; |
| 4270 | unsigned idx1 = 1; // src |
| 4271 | st->print_raw("movl "); |
| 4272 | opnd_array(0)->int_format(ra, this, st); // dst |
| 4273 | st->print_raw(", "); |
| 4274 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 4275 | st->print_raw("\t# int stk"); |
| 4276 | } |
| 4277 | #endif |
| 4278 | #ifndef PRODUCT |
| 4279 | void storeSSLNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4280 | // Start at oper_input_base() and count operands |
| 4281 | unsigned idx0 = 1; |
| 4282 | unsigned idx1 = 1; // src |
| 4283 | st->print_raw("movq "); |
| 4284 | opnd_array(0)->int_format(ra, this, st); // dst |
| 4285 | st->print_raw(", "); |
| 4286 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 4287 | st->print_raw("\t# long stk"); |
| 4288 | } |
| 4289 | #endif |
| 4290 | #ifndef PRODUCT |
| 4291 | void storeSSPNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4292 | // Start at oper_input_base() and count operands |
| 4293 | unsigned idx0 = 1; |
| 4294 | unsigned idx1 = 1; // src |
| 4295 | st->print_raw("movq "); |
| 4296 | opnd_array(0)->int_format(ra, this, st); // dst |
| 4297 | st->print_raw(", "); |
| 4298 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 4299 | st->print_raw("\t# ptr stk"); |
| 4300 | } |
| 4301 | #endif |
| 4302 | #ifndef PRODUCT |
| 4303 | void storeSSFNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4304 | // Start at oper_input_base() and count operands |
| 4305 | unsigned idx0 = 1; |
| 4306 | unsigned idx1 = 1; // src |
| 4307 | st->print_raw("movss "); |
| 4308 | opnd_array(0)->int_format(ra, this, st); // dst |
| 4309 | st->print_raw(", "); |
| 4310 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 4311 | st->print_raw("\t# float stk"); |
| 4312 | } |
| 4313 | #endif |
| 4314 | #ifndef PRODUCT |
| 4315 | void storeSSDNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4316 | // Start at oper_input_base() and count operands |
| 4317 | unsigned idx0 = 1; |
| 4318 | unsigned idx1 = 1; // src |
| 4319 | st->print_raw("movsd "); |
| 4320 | opnd_array(0)->int_format(ra, this, st); // dst |
| 4321 | st->print_raw(", "); |
| 4322 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 4323 | st->print_raw("\t# double stk"); |
| 4324 | } |
| 4325 | #endif |
| 4326 | #ifndef PRODUCT |
| 4327 | void cacheWBNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4328 | // Start at oper_input_base() and count operands |
| 4329 | unsigned idx0 = 2; |
| 4330 | unsigned idx1 = 2; // |
| 4331 | st->print_raw("cache wb "); |
| 4332 | opnd_array(1)->ext_format(ra, this,idx1, st); // addr |
| 4333 | } |
| 4334 | #endif |
| 4335 | #ifndef PRODUCT |
| 4336 | void cacheWBPreSyncNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4337 | st->print_raw("cache wb presync"); |
| 4338 | } |
| 4339 | #endif |
| 4340 | #ifndef PRODUCT |
| 4341 | void cacheWBPostSyncNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4342 | st->print_raw("cache wb postsync"); |
| 4343 | } |
| 4344 | #endif |
| 4345 | #ifndef PRODUCT |
| 4346 | void bytes_reverse_intNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4347 | // Start at oper_input_base() and count operands |
| 4348 | unsigned idx0 = 1; |
| 4349 | unsigned idx1 = 1; // dst |
| 4350 | st->print_raw("bswapl "); |
| 4351 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 4352 | } |
| 4353 | #endif |
| 4354 | #ifndef PRODUCT |
| 4355 | void bytes_reverse_longNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4356 | // Start at oper_input_base() and count operands |
| 4357 | unsigned idx0 = 1; |
| 4358 | unsigned idx1 = 1; // dst |
| 4359 | st->print_raw("bswapq "); |
| 4360 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 4361 | } |
| 4362 | #endif |
| 4363 | #ifndef PRODUCT |
| 4364 | void bytes_reverse_unsigned_shortNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4365 | // Start at oper_input_base() and count operands |
| 4366 | unsigned idx0 = 1; |
| 4367 | unsigned idx1 = 1; // dst |
| 4368 | st->print_raw("bswapl "); |
| 4369 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 4370 | st->print_raw("\n\t"); |
| 4371 | st->print_raw("shrl "); |
| 4372 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 4373 | st->print_raw(",16\n\t"); |
| 4374 | } |
| 4375 | #endif |
| 4376 | #ifndef PRODUCT |
| 4377 | void bytes_reverse_shortNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4378 | // Start at oper_input_base() and count operands |
| 4379 | unsigned idx0 = 1; |
| 4380 | unsigned idx1 = 1; // dst |
| 4381 | st->print_raw("bswapl "); |
| 4382 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 4383 | st->print_raw("\n\t"); |
| 4384 | st->print_raw("sar "); |
| 4385 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 4386 | st->print_raw(",16\n\t"); |
| 4387 | } |
| 4388 | #endif |
| 4389 | #ifndef PRODUCT |
| 4390 | void countLeadingZerosINode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4391 | // Start at oper_input_base() and count operands |
| 4392 | unsigned idx0 = 1; |
| 4393 | unsigned idx1 = 1; // src |
| 4394 | st->print_raw("lzcntl "); |
| 4395 | opnd_array(0)->int_format(ra, this, st); // dst |
| 4396 | st->print_raw(", "); |
| 4397 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 4398 | st->print_raw("\t# count leading zeros (int)"); |
| 4399 | } |
| 4400 | #endif |
| 4401 | #ifndef PRODUCT |
| 4402 | void countLeadingZerosI_bsrNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4403 | // Start at oper_input_base() and count operands |
| 4404 | unsigned idx0 = 1; |
| 4405 | unsigned idx1 = 1; // src |
| 4406 | st->print_raw("bsrl "); |
| 4407 | opnd_array(0)->int_format(ra, this, st); // dst |
| 4408 | st->print_raw(", "); |
| 4409 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 4410 | st->print_raw("\t# count leading zeros (int)\n\t"); |
| 4411 | st->print_raw("jnz skip\n\t"); |
| 4412 | st->print_raw("movl "); |
| 4413 | opnd_array(0)->int_format(ra, this, st); // dst |
| 4414 | st->print_raw(", -1\n"); |
| 4415 | st->print_raw("skip:\n\t"); |
| 4416 | st->print_raw("negl "); |
| 4417 | opnd_array(0)->int_format(ra, this, st); // dst |
| 4418 | st->print_raw("\n\t"); |
| 4419 | st->print_raw("addl "); |
| 4420 | opnd_array(0)->int_format(ra, this, st); // dst |
| 4421 | st->print_raw(", 31"); |
| 4422 | } |
| 4423 | #endif |
| 4424 | #ifndef PRODUCT |
| 4425 | void countLeadingZerosLNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4426 | // Start at oper_input_base() and count operands |
| 4427 | unsigned idx0 = 1; |
| 4428 | unsigned idx1 = 1; // src |
| 4429 | st->print_raw("lzcntq "); |
| 4430 | opnd_array(0)->int_format(ra, this, st); // dst |
| 4431 | st->print_raw(", "); |
| 4432 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 4433 | st->print_raw("\t# count leading zeros (long)"); |
| 4434 | } |
| 4435 | #endif |
| 4436 | #ifndef PRODUCT |
| 4437 | void countLeadingZerosL_bsrNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4438 | // Start at oper_input_base() and count operands |
| 4439 | unsigned idx0 = 1; |
| 4440 | unsigned idx1 = 1; // src |
| 4441 | st->print_raw("bsrq "); |
| 4442 | opnd_array(0)->int_format(ra, this, st); // dst |
| 4443 | st->print_raw(", "); |
| 4444 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 4445 | st->print_raw("\t# count leading zeros (long)\n\t"); |
| 4446 | st->print_raw("jnz skip\n\t"); |
| 4447 | st->print_raw("movl "); |
| 4448 | opnd_array(0)->int_format(ra, this, st); // dst |
| 4449 | st->print_raw(", -1\n"); |
| 4450 | st->print_raw("skip:\n\t"); |
| 4451 | st->print_raw("negl "); |
| 4452 | opnd_array(0)->int_format(ra, this, st); // dst |
| 4453 | st->print_raw("\n\t"); |
| 4454 | st->print_raw("addl "); |
| 4455 | opnd_array(0)->int_format(ra, this, st); // dst |
| 4456 | st->print_raw(", 63"); |
| 4457 | } |
| 4458 | #endif |
| 4459 | #ifndef PRODUCT |
| 4460 | void countTrailingZerosINode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4461 | // Start at oper_input_base() and count operands |
| 4462 | unsigned idx0 = 1; |
| 4463 | unsigned idx1 = 1; // src |
| 4464 | st->print_raw("tzcntl "); |
| 4465 | opnd_array(0)->int_format(ra, this, st); // dst |
| 4466 | st->print_raw(", "); |
| 4467 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 4468 | st->print_raw("\t# count trailing zeros (int)"); |
| 4469 | } |
| 4470 | #endif |
| 4471 | #ifndef PRODUCT |
| 4472 | void countTrailingZerosI_bsfNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4473 | // Start at oper_input_base() and count operands |
| 4474 | unsigned idx0 = 1; |
| 4475 | unsigned idx1 = 1; // src |
| 4476 | st->print_raw("bsfl "); |
| 4477 | opnd_array(0)->int_format(ra, this, st); // dst |
| 4478 | st->print_raw(", "); |
| 4479 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 4480 | st->print_raw("\t# count trailing zeros (int)\n\t"); |
| 4481 | st->print_raw("jnz done\n\t"); |
| 4482 | st->print_raw("movl "); |
| 4483 | opnd_array(0)->int_format(ra, this, st); // dst |
| 4484 | st->print_raw(", 32\n"); |
| 4485 | st->print_raw("done:"); |
| 4486 | } |
| 4487 | #endif |
| 4488 | #ifndef PRODUCT |
| 4489 | void countTrailingZerosLNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4490 | // Start at oper_input_base() and count operands |
| 4491 | unsigned idx0 = 1; |
| 4492 | unsigned idx1 = 1; // src |
| 4493 | st->print_raw("tzcntq "); |
| 4494 | opnd_array(0)->int_format(ra, this, st); // dst |
| 4495 | st->print_raw(", "); |
| 4496 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 4497 | st->print_raw("\t# count trailing zeros (long)"); |
| 4498 | } |
| 4499 | #endif |
| 4500 | #ifndef PRODUCT |
| 4501 | void countTrailingZerosL_bsfNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4502 | // Start at oper_input_base() and count operands |
| 4503 | unsigned idx0 = 1; |
| 4504 | unsigned idx1 = 1; // src |
| 4505 | st->print_raw("bsfq "); |
| 4506 | opnd_array(0)->int_format(ra, this, st); // dst |
| 4507 | st->print_raw(", "); |
| 4508 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 4509 | st->print_raw("\t# count trailing zeros (long)\n\t"); |
| 4510 | st->print_raw("jnz done\n\t"); |
| 4511 | st->print_raw("movl "); |
| 4512 | opnd_array(0)->int_format(ra, this, st); // dst |
| 4513 | st->print_raw(", 64\n"); |
| 4514 | st->print_raw("done:"); |
| 4515 | } |
| 4516 | #endif |
| 4517 | #ifndef PRODUCT |
| 4518 | void popCountINode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4519 | // Start at oper_input_base() and count operands |
| 4520 | unsigned idx0 = 1; |
| 4521 | unsigned idx1 = 1; // src |
| 4522 | st->print_raw("popcnt "); |
| 4523 | opnd_array(0)->int_format(ra, this, st); // dst |
| 4524 | st->print_raw(", "); |
| 4525 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 4526 | } |
| 4527 | #endif |
| 4528 | #ifndef PRODUCT |
| 4529 | void popCountI_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4530 | // Start at oper_input_base() and count operands |
| 4531 | unsigned idx0 = 2; |
| 4532 | unsigned idx1 = 2; // mem |
| 4533 | st->print_raw("popcnt "); |
| 4534 | opnd_array(0)->int_format(ra, this, st); // dst |
| 4535 | st->print_raw(", "); |
| 4536 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 4537 | } |
| 4538 | #endif |
| 4539 | #ifndef PRODUCT |
| 4540 | void popCountLNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4541 | // Start at oper_input_base() and count operands |
| 4542 | unsigned idx0 = 1; |
| 4543 | unsigned idx1 = 1; // src |
| 4544 | st->print_raw("popcnt "); |
| 4545 | opnd_array(0)->int_format(ra, this, st); // dst |
| 4546 | st->print_raw(", "); |
| 4547 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 4548 | } |
| 4549 | #endif |
| 4550 | #ifndef PRODUCT |
| 4551 | void popCountL_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4552 | // Start at oper_input_base() and count operands |
| 4553 | unsigned idx0 = 2; |
| 4554 | unsigned idx1 = 2; // mem |
| 4555 | st->print_raw("popcnt "); |
| 4556 | opnd_array(0)->int_format(ra, this, st); // dst |
| 4557 | st->print_raw(", "); |
| 4558 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 4559 | } |
| 4560 | #endif |
| 4561 | #ifndef PRODUCT |
| 4562 | void membar_acquireNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4563 | st->print_raw("MEMBAR-acquire ! (empty encoding)"); |
| 4564 | } |
| 4565 | #endif |
| 4566 | #ifndef PRODUCT |
| 4567 | void membar_acquire_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4568 | st->print_raw("MEMBAR-acquire ! (empty encoding)"); |
| 4569 | } |
| 4570 | #endif |
| 4571 | #ifndef PRODUCT |
| 4572 | void membar_acquire_lockNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4573 | st->print_raw("MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)"); |
| 4574 | } |
| 4575 | #endif |
| 4576 | #ifndef PRODUCT |
| 4577 | void membar_releaseNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4578 | st->print_raw("MEMBAR-release ! (empty encoding)"); |
| 4579 | } |
| 4580 | #endif |
| 4581 | #ifndef PRODUCT |
| 4582 | void membar_release_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4583 | st->print_raw("MEMBAR-release ! (empty encoding)"); |
| 4584 | } |
| 4585 | #endif |
| 4586 | #ifndef PRODUCT |
| 4587 | void membar_release_lockNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4588 | st->print_raw("MEMBAR-release (a FastUnlock follows so empty encoding)"); |
| 4589 | } |
| 4590 | #endif |
| 4591 | #ifndef PRODUCT |
| 4592 | void membar_volatileNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4593 | st->print_raw("lock addl [rsp + #0], 0\t! membar_volatile"); |
| 4594 | } |
| 4595 | #endif |
| 4596 | #ifndef PRODUCT |
| 4597 | void unnecessary_membar_volatileNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4598 | st->print_raw("MEMBAR-volatile (unnecessary so empty encoding)"); |
| 4599 | } |
| 4600 | #endif |
| 4601 | #ifndef PRODUCT |
| 4602 | void membar_storestoreNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4603 | st->print_raw("MEMBAR-storestore (empty encoding)"); |
| 4604 | } |
| 4605 | #endif |
| 4606 | #ifndef PRODUCT |
| 4607 | void membar_storestore_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4608 | st->print_raw("MEMBAR-storestore (empty encoding)"); |
| 4609 | } |
| 4610 | #endif |
| 4611 | #ifndef PRODUCT |
| 4612 | void castX2PNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4613 | // Start at oper_input_base() and count operands |
| 4614 | unsigned idx0 = 1; |
| 4615 | unsigned idx1 = 1; // src |
| 4616 | st->print_raw("movq "); |
| 4617 | opnd_array(0)->int_format(ra, this, st); // dst |
| 4618 | st->print_raw(", "); |
| 4619 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 4620 | st->print_raw("\t# long->ptr"); |
| 4621 | } |
| 4622 | #endif |
| 4623 | #ifndef PRODUCT |
| 4624 | void castP2XNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4625 | // Start at oper_input_base() and count operands |
| 4626 | unsigned idx0 = 1; |
| 4627 | unsigned idx1 = 1; // src |
| 4628 | st->print_raw("movq "); |
| 4629 | opnd_array(0)->int_format(ra, this, st); // dst |
| 4630 | st->print_raw(", "); |
| 4631 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 4632 | st->print_raw("\t# ptr -> long"); |
| 4633 | } |
| 4634 | #endif |
| 4635 | #ifndef PRODUCT |
| 4636 | void convP2INode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4637 | // Start at oper_input_base() and count operands |
| 4638 | unsigned idx0 = 1; |
| 4639 | unsigned idx1 = 1; // src |
| 4640 | st->print_raw("movl "); |
| 4641 | opnd_array(0)->int_format(ra, this, st); // dst |
| 4642 | st->print_raw(", "); |
| 4643 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 4644 | st->print_raw("\t# ptr -> int"); |
| 4645 | } |
| 4646 | #endif |
| 4647 | #ifndef PRODUCT |
| 4648 | void convN2INode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4649 | // Start at oper_input_base() and count operands |
| 4650 | unsigned idx0 = 1; |
| 4651 | unsigned idx1 = 1; // src |
| 4652 | st->print_raw("movl "); |
| 4653 | opnd_array(0)->int_format(ra, this, st); // dst |
| 4654 | st->print_raw(", "); |
| 4655 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 4656 | st->print_raw("\t# compressed ptr -> int"); |
| 4657 | } |
| 4658 | #endif |
| 4659 | #ifndef PRODUCT |
| 4660 | void encodeHeapOopNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4661 | // Start at oper_input_base() and count operands |
| 4662 | unsigned idx0 = 1; |
| 4663 | unsigned idx1 = 1; // src |
| 4664 | st->print_raw("encode_heap_oop "); |
| 4665 | opnd_array(0)->int_format(ra, this, st); // dst |
| 4666 | st->print_raw(","); |
| 4667 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 4668 | } |
| 4669 | #endif |
| 4670 | #ifndef PRODUCT |
| 4671 | void encodeHeapOop_not_nullNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4672 | // Start at oper_input_base() and count operands |
| 4673 | unsigned idx0 = 1; |
| 4674 | unsigned idx1 = 1; // src |
| 4675 | st->print_raw("encode_heap_oop_not_null "); |
| 4676 | opnd_array(0)->int_format(ra, this, st); // dst |
| 4677 | st->print_raw(","); |
| 4678 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 4679 | } |
| 4680 | #endif |
| 4681 | #ifndef PRODUCT |
| 4682 | void decodeHeapOopNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4683 | // Start at oper_input_base() and count operands |
| 4684 | unsigned idx0 = 1; |
| 4685 | unsigned idx1 = 1; // src |
| 4686 | st->print_raw("decode_heap_oop "); |
| 4687 | opnd_array(0)->int_format(ra, this, st); // dst |
| 4688 | st->print_raw(","); |
| 4689 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 4690 | } |
| 4691 | #endif |
| 4692 | #ifndef PRODUCT |
| 4693 | void decodeHeapOop_not_nullNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4694 | // Start at oper_input_base() and count operands |
| 4695 | unsigned idx0 = 1; |
| 4696 | unsigned idx1 = 1; // src |
| 4697 | st->print_raw("decode_heap_oop_not_null "); |
| 4698 | opnd_array(0)->int_format(ra, this, st); // dst |
| 4699 | st->print_raw(","); |
| 4700 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 4701 | } |
| 4702 | #endif |
| 4703 | #ifndef PRODUCT |
| 4704 | void encodeKlass_not_nullNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4705 | // Start at oper_input_base() and count operands |
| 4706 | unsigned idx0 = 1; |
| 4707 | unsigned idx1 = 1; // src |
| 4708 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst |
| 4709 | st->print_raw("encode_and_move_klass_not_null "); |
| 4710 | opnd_array(2)->ext_format(ra, this,idx2, st); // dst |
| 4711 | st->print_raw(","); |
| 4712 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 4713 | } |
| 4714 | #endif |
| 4715 | #ifndef PRODUCT |
| 4716 | void decodeKlass_not_nullNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4717 | // Start at oper_input_base() and count operands |
| 4718 | unsigned idx0 = 1; |
| 4719 | unsigned idx1 = 1; // src |
| 4720 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst |
| 4721 | st->print_raw("decode_and_move_klass_not_null "); |
| 4722 | opnd_array(2)->ext_format(ra, this,idx2, st); // dst |
| 4723 | st->print_raw(","); |
| 4724 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 4725 | } |
| 4726 | #endif |
| 4727 | #ifndef PRODUCT |
| 4728 | void jumpXtnd_offsetNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4729 | // Start at oper_input_base() and count operands |
| 4730 | unsigned idx0 = 1; |
| 4731 | unsigned idx1 = 1; // shift |
| 4732 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dest |
| 4733 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // |
| 4734 | st->print_raw("leaq "); |
| 4735 | opnd_array(3)->ext_format(ra, this,idx3, st); // dest |
| 4736 | st->print_raw(", ["); |
| 4737 | st->print("constant table base + #%d", constant_offset_unchecked()); |
| 4738 | st->print_raw("]\n\t"); |
| 4739 | st->print_raw("jmp ["); |
| 4740 | opnd_array(3)->ext_format(ra, this,idx3, st); // dest |
| 4741 | st->print_raw(" + "); |
| 4742 | opnd_array(1)->ext_format(ra, this,idx1, st); // switch_val |
| 4743 | st->print_raw(" << "); |
| 4744 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 4745 | st->print_raw("]\n\t"); |
| 4746 | } |
| 4747 | #endif |
| 4748 | #ifndef PRODUCT |
| 4749 | void jumpXtnd_addrNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4750 | // Start at oper_input_base() and count operands |
| 4751 | unsigned idx0 = 1; |
| 4752 | unsigned idx1 = 1; // shift |
| 4753 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // offset |
| 4754 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dest |
| 4755 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // |
| 4756 | st->print_raw("leaq "); |
| 4757 | opnd_array(4)->ext_format(ra, this,idx4, st); // dest |
| 4758 | st->print_raw(", ["); |
| 4759 | st->print("constant table base + #%d", constant_offset_unchecked()); |
| 4760 | st->print_raw("]\n\t"); |
| 4761 | st->print_raw("jmp ["); |
| 4762 | opnd_array(4)->ext_format(ra, this,idx4, st); // dest |
| 4763 | st->print_raw(" + "); |
| 4764 | opnd_array(1)->ext_format(ra, this,idx1, st); // switch_val |
| 4765 | st->print_raw(" << "); |
| 4766 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 4767 | st->print_raw(" + "); |
| 4768 | opnd_array(3)->ext_format(ra, this,idx3, st); // offset |
| 4769 | st->print_raw("]\n\t"); |
| 4770 | } |
| 4771 | #endif |
| 4772 | #ifndef PRODUCT |
| 4773 | void jumpXtndNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4774 | // Start at oper_input_base() and count operands |
| 4775 | unsigned idx0 = 1; |
| 4776 | unsigned idx1 = 1; // dest |
| 4777 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // |
| 4778 | st->print_raw("leaq "); |
| 4779 | opnd_array(2)->ext_format(ra, this,idx2, st); // dest |
| 4780 | st->print_raw(", ["); |
| 4781 | st->print("constant table base + #%d", constant_offset_unchecked()); |
| 4782 | st->print_raw("]\n\t"); |
| 4783 | st->print_raw("jmp ["); |
| 4784 | opnd_array(2)->ext_format(ra, this,idx2, st); // dest |
| 4785 | st->print_raw(" + "); |
| 4786 | opnd_array(1)->ext_format(ra, this,idx1, st); // switch_val |
| 4787 | st->print_raw("]\n\t"); |
| 4788 | } |
| 4789 | #endif |
| 4790 | #ifndef PRODUCT |
| 4791 | void cmovI_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4792 | // Start at oper_input_base() and count operands |
| 4793 | unsigned idx0 = 1; |
| 4794 | unsigned idx1 = 1; // cop |
| 4795 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr |
| 4796 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 4797 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src |
| 4798 | st->print_raw("cmovl"); |
| 4799 | opnd_array(1)->ext_format(ra, this,idx1, st); // cop |
| 4800 | st->print_raw(" "); |
| 4801 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 4802 | st->print_raw(", "); |
| 4803 | opnd_array(4)->ext_format(ra, this,idx4, st); // src |
| 4804 | st->print_raw("\t# signed, int"); |
| 4805 | } |
| 4806 | #endif |
| 4807 | #ifndef PRODUCT |
| 4808 | void cmovI_regUNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4809 | // Start at oper_input_base() and count operands |
| 4810 | unsigned idx0 = 1; |
| 4811 | unsigned idx1 = 1; // cop |
| 4812 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr |
| 4813 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 4814 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src |
| 4815 | st->print_raw("cmovl"); |
| 4816 | opnd_array(1)->ext_format(ra, this,idx1, st); // cop |
| 4817 | st->print_raw(" "); |
| 4818 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 4819 | st->print_raw(", "); |
| 4820 | opnd_array(4)->ext_format(ra, this,idx4, st); // src |
| 4821 | st->print_raw("\t# unsigned, int"); |
| 4822 | } |
| 4823 | #endif |
| 4824 | #ifndef PRODUCT |
| 4825 | void cmovI_regUCFNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4826 | } |
| 4827 | #endif |
| 4828 | #ifndef PRODUCT |
| 4829 | void cmovI_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4830 | // Start at oper_input_base() and count operands |
| 4831 | unsigned idx0 = 2; |
| 4832 | unsigned idx1 = 2; // cop |
| 4833 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr |
| 4834 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 4835 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src |
| 4836 | st->print_raw("cmovl"); |
| 4837 | opnd_array(1)->ext_format(ra, this,idx1, st); // cop |
| 4838 | st->print_raw(" "); |
| 4839 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 4840 | st->print_raw(", "); |
| 4841 | opnd_array(4)->ext_format(ra, this,idx4, st); // src |
| 4842 | st->print_raw("\t# signed, int"); |
| 4843 | } |
| 4844 | #endif |
| 4845 | #ifndef PRODUCT |
| 4846 | void cmovI_memUNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4847 | // Start at oper_input_base() and count operands |
| 4848 | unsigned idx0 = 2; |
| 4849 | unsigned idx1 = 2; // cop |
| 4850 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr |
| 4851 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 4852 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src |
| 4853 | st->print_raw("cmovl"); |
| 4854 | opnd_array(1)->ext_format(ra, this,idx1, st); // cop |
| 4855 | st->print_raw(" "); |
| 4856 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 4857 | st->print_raw(", "); |
| 4858 | opnd_array(4)->ext_format(ra, this,idx4, st); // src |
| 4859 | st->print_raw("\t# unsigned, int"); |
| 4860 | } |
| 4861 | #endif |
| 4862 | #ifndef PRODUCT |
| 4863 | void cmovI_memUCFNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4864 | } |
| 4865 | #endif |
| 4866 | #ifndef PRODUCT |
| 4867 | void cmovN_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4868 | // Start at oper_input_base() and count operands |
| 4869 | unsigned idx0 = 1; |
| 4870 | unsigned idx1 = 1; // cop |
| 4871 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr |
| 4872 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 4873 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src |
| 4874 | st->print_raw("cmovl"); |
| 4875 | opnd_array(1)->ext_format(ra, this,idx1, st); // cop |
| 4876 | st->print_raw(" "); |
| 4877 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 4878 | st->print_raw(", "); |
| 4879 | opnd_array(4)->ext_format(ra, this,idx4, st); // src |
| 4880 | st->print_raw("\t# signed, compressed ptr"); |
| 4881 | } |
| 4882 | #endif |
| 4883 | #ifndef PRODUCT |
| 4884 | void cmovN_regUNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4885 | // Start at oper_input_base() and count operands |
| 4886 | unsigned idx0 = 1; |
| 4887 | unsigned idx1 = 1; // cop |
| 4888 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr |
| 4889 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 4890 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src |
| 4891 | st->print_raw("cmovl"); |
| 4892 | opnd_array(1)->ext_format(ra, this,idx1, st); // cop |
| 4893 | st->print_raw(" "); |
| 4894 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 4895 | st->print_raw(", "); |
| 4896 | opnd_array(4)->ext_format(ra, this,idx4, st); // src |
| 4897 | st->print_raw("\t# unsigned, compressed ptr"); |
| 4898 | } |
| 4899 | #endif |
| 4900 | #ifndef PRODUCT |
| 4901 | void cmovN_regUCFNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4902 | } |
| 4903 | #endif |
| 4904 | #ifndef PRODUCT |
| 4905 | void cmovP_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4906 | // Start at oper_input_base() and count operands |
| 4907 | unsigned idx0 = 1; |
| 4908 | unsigned idx1 = 1; // cop |
| 4909 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr |
| 4910 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 4911 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src |
| 4912 | st->print_raw("cmovq"); |
| 4913 | opnd_array(1)->ext_format(ra, this,idx1, st); // cop |
| 4914 | st->print_raw(" "); |
| 4915 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 4916 | st->print_raw(", "); |
| 4917 | opnd_array(4)->ext_format(ra, this,idx4, st); // src |
| 4918 | st->print_raw("\t# signed, ptr"); |
| 4919 | } |
| 4920 | #endif |
| 4921 | #ifndef PRODUCT |
| 4922 | void cmovP_regUNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4923 | // Start at oper_input_base() and count operands |
| 4924 | unsigned idx0 = 1; |
| 4925 | unsigned idx1 = 1; // cop |
| 4926 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr |
| 4927 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 4928 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src |
| 4929 | st->print_raw("cmovq"); |
| 4930 | opnd_array(1)->ext_format(ra, this,idx1, st); // cop |
| 4931 | st->print_raw(" "); |
| 4932 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 4933 | st->print_raw(", "); |
| 4934 | opnd_array(4)->ext_format(ra, this,idx4, st); // src |
| 4935 | st->print_raw("\t# unsigned, ptr"); |
| 4936 | } |
| 4937 | #endif |
| 4938 | #ifndef PRODUCT |
| 4939 | void cmovP_regUCFNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4940 | } |
| 4941 | #endif |
| 4942 | #ifndef PRODUCT |
| 4943 | void cmovL_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4944 | // Start at oper_input_base() and count operands |
| 4945 | unsigned idx0 = 1; |
| 4946 | unsigned idx1 = 1; // cop |
| 4947 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr |
| 4948 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 4949 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src |
| 4950 | st->print_raw("cmovq"); |
| 4951 | opnd_array(1)->ext_format(ra, this,idx1, st); // cop |
| 4952 | st->print_raw(" "); |
| 4953 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 4954 | st->print_raw(", "); |
| 4955 | opnd_array(4)->ext_format(ra, this,idx4, st); // src |
| 4956 | st->print_raw("\t# signed, long"); |
| 4957 | } |
| 4958 | #endif |
| 4959 | #ifndef PRODUCT |
| 4960 | void cmovL_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4961 | // Start at oper_input_base() and count operands |
| 4962 | unsigned idx0 = 2; |
| 4963 | unsigned idx1 = 2; // cop |
| 4964 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr |
| 4965 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 4966 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src |
| 4967 | st->print_raw("cmovq"); |
| 4968 | opnd_array(1)->ext_format(ra, this,idx1, st); // cop |
| 4969 | st->print_raw(" "); |
| 4970 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 4971 | st->print_raw(", "); |
| 4972 | opnd_array(4)->ext_format(ra, this,idx4, st); // src |
| 4973 | st->print_raw("\t# signed, long"); |
| 4974 | } |
| 4975 | #endif |
| 4976 | #ifndef PRODUCT |
| 4977 | void cmovL_regUNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4978 | // Start at oper_input_base() and count operands |
| 4979 | unsigned idx0 = 1; |
| 4980 | unsigned idx1 = 1; // cop |
| 4981 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr |
| 4982 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 4983 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src |
| 4984 | st->print_raw("cmovq"); |
| 4985 | opnd_array(1)->ext_format(ra, this,idx1, st); // cop |
| 4986 | st->print_raw(" "); |
| 4987 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 4988 | st->print_raw(", "); |
| 4989 | opnd_array(4)->ext_format(ra, this,idx4, st); // src |
| 4990 | st->print_raw("\t# unsigned, long"); |
| 4991 | } |
| 4992 | #endif |
| 4993 | #ifndef PRODUCT |
| 4994 | void cmovL_regUCFNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4995 | } |
| 4996 | #endif |
| 4997 | #ifndef PRODUCT |
| 4998 | void cmovL_memUNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 4999 | // Start at oper_input_base() and count operands |
| 5000 | unsigned idx0 = 2; |
| 5001 | unsigned idx1 = 2; // cop |
| 5002 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr |
| 5003 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 5004 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src |
| 5005 | st->print_raw("cmovq"); |
| 5006 | opnd_array(1)->ext_format(ra, this,idx1, st); // cop |
| 5007 | st->print_raw(" "); |
| 5008 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 5009 | st->print_raw(", "); |
| 5010 | opnd_array(4)->ext_format(ra, this,idx4, st); // src |
| 5011 | st->print_raw("\t# unsigned, long"); |
| 5012 | } |
| 5013 | #endif |
| 5014 | #ifndef PRODUCT |
| 5015 | void cmovL_memUCFNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 5016 | } |
| 5017 | #endif |
| 5018 | #ifndef PRODUCT |
| 5019 | void cmovF_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 5020 | // Start at oper_input_base() and count operands |
| 5021 | unsigned idx0 = 1; |
| 5022 | unsigned idx1 = 1; // cop |
| 5023 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr |
| 5024 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 5025 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src |
| 5026 | st->print_raw("jn"); |
| 5027 | opnd_array(1)->ext_format(ra, this,idx1, st); // cop |
| 5028 | st->print_raw(" skip\t# signed cmove float\n\t"); |
| 5029 | st->print_raw("movss "); |
| 5030 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 5031 | st->print_raw(", "); |
| 5032 | opnd_array(4)->ext_format(ra, this,idx4, st); // src |
| 5033 | st->print_raw("\n"); |
| 5034 | st->print_raw("skip:"); |
| 5035 | } |
| 5036 | #endif |
| 5037 | #ifndef PRODUCT |
| 5038 | void cmovF_regUNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 5039 | // Start at oper_input_base() and count operands |
| 5040 | unsigned idx0 = 1; |
| 5041 | unsigned idx1 = 1; // cop |
| 5042 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr |
| 5043 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 5044 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src |
| 5045 | st->print_raw("jn"); |
| 5046 | opnd_array(1)->ext_format(ra, this,idx1, st); // cop |
| 5047 | st->print_raw(" skip\t# unsigned cmove float\n\t"); |
| 5048 | st->print_raw("movss "); |
| 5049 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 5050 | st->print_raw(", "); |
| 5051 | opnd_array(4)->ext_format(ra, this,idx4, st); // src |
| 5052 | st->print_raw("\n"); |
| 5053 | st->print_raw("skip:"); |
| 5054 | } |
| 5055 | #endif |
| 5056 | #ifndef PRODUCT |
| 5057 | void cmovF_regUCFNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 5058 | } |
| 5059 | #endif |
| 5060 | #ifndef PRODUCT |
| 5061 | void cmovD_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 5062 | // Start at oper_input_base() and count operands |
| 5063 | unsigned idx0 = 1; |
| 5064 | unsigned idx1 = 1; // cop |
| 5065 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr |
| 5066 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 5067 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src |
| 5068 | st->print_raw("jn"); |
| 5069 | opnd_array(1)->ext_format(ra, this,idx1, st); // cop |
| 5070 | st->print_raw(" skip\t# signed cmove double\n\t"); |
| 5071 | st->print_raw("movsd "); |
| 5072 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 5073 | st->print_raw(", "); |
| 5074 | opnd_array(4)->ext_format(ra, this,idx4, st); // src |
| 5075 | st->print_raw("\n"); |
| 5076 | st->print_raw("skip:"); |
| 5077 | } |
| 5078 | #endif |
| 5079 | #ifndef PRODUCT |
| 5080 | void cmovD_regUNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 5081 | // Start at oper_input_base() and count operands |
| 5082 | unsigned idx0 = 1; |
| 5083 | unsigned idx1 = 1; // cop |
| 5084 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr |
| 5085 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 5086 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src |
| 5087 | st->print_raw("jn"); |
| 5088 | opnd_array(1)->ext_format(ra, this,idx1, st); // cop |
| 5089 | st->print_raw(" skip\t# unsigned cmove double\n\t"); |
| 5090 | st->print_raw("movsd "); |
| 5091 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 5092 | st->print_raw(", "); |
| 5093 | opnd_array(4)->ext_format(ra, this,idx4, st); // src |
| 5094 | st->print_raw("\n"); |
| 5095 | st->print_raw("skip:"); |
| 5096 | } |
| 5097 | #endif |
| 5098 | #ifndef PRODUCT |
| 5099 | void cmovD_regUCFNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 5100 | } |
| 5101 | #endif |
| 5102 | #ifndef PRODUCT |
| 5103 | void addI_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 5104 | // Start at oper_input_base() and count operands |
| 5105 | unsigned idx0 = 1; |
| 5106 | unsigned idx1 = 1; // dst |
| 5107 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 5108 | st->print_raw("addl "); |
| 5109 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 5110 | st->print_raw(", "); |
| 5111 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 5112 | st->print_raw("\t# int"); |
| 5113 | } |
| 5114 | #endif |
| 5115 | #ifndef PRODUCT |
| 5116 | void addI_rReg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 5117 | // Start at oper_input_base() and count operands |
| 5118 | unsigned idx0 = 1; |
| 5119 | unsigned idx1 = 1; // dst |
| 5120 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 5121 | st->print_raw("addl "); |
| 5122 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 5123 | st->print_raw(", "); |
| 5124 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 5125 | st->print_raw("\t# int"); |
| 5126 | } |
| 5127 | #endif |
| 5128 | #ifndef PRODUCT |
| 5129 | void addI_rReg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 5130 | // Start at oper_input_base() and count operands |
| 5131 | unsigned idx0 = 2; |
| 5132 | unsigned idx1 = 2; // dst |
| 5133 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 5134 | st->print_raw("addl "); |
| 5135 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 5136 | st->print_raw(", "); |
| 5137 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 5138 | st->print_raw("\t# int"); |
| 5139 | } |
| 5140 | #endif |
| 5141 | #ifndef PRODUCT |
| 5142 | void addI_rReg_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 5143 | // Start at oper_input_base() and count operands |
| 5144 | unsigned idx0 = 2; |
| 5145 | unsigned idx1 = 2; // src |
| 5146 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst |
| 5147 | st->print_raw("addl "); |
| 5148 | opnd_array(2)->ext_format(ra, this,idx2, st); // dst |
| 5149 | st->print_raw(", "); |
| 5150 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 5151 | st->print_raw("\t# int"); |
| 5152 | } |
| 5153 | #endif |
| 5154 | #ifndef PRODUCT |
| 5155 | void addI_mem_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 5156 | // Start at oper_input_base() and count operands |
| 5157 | unsigned idx0 = 2; |
| 5158 | unsigned idx1 = 2; // dst |
| 5159 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 5160 | st->print_raw("addl "); |
| 5161 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 5162 | st->print_raw(", "); |
| 5163 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 5164 | st->print_raw("\t# int"); |
| 5165 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 5166 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 5167 | st->print(" ! Field: "); |
| 5168 | if (f->is_volatile()) |
| 5169 | st->print("volatile "); |
| 5170 | f->holder()->name()->print_symbol_on(st); |
| 5171 | st->print("."); |
| 5172 | f->name()->print_symbol_on(st); |
| 5173 | if (f->is_constant()) |
| 5174 | st->print(" (constant)"); |
| 5175 | } else { |
| 5176 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 5177 | st->print(" volatile!"); |
| 5178 | } |
| 5179 | } |
| 5180 | #endif |
| 5181 | #ifndef PRODUCT |
| 5182 | void addI_mem_rReg_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 5183 | // Start at oper_input_base() and count operands |
| 5184 | unsigned idx0 = 2; |
| 5185 | unsigned idx1 = 2; // dst |
| 5186 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 5187 | st->print_raw("addl "); |
| 5188 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 5189 | st->print_raw(", "); |
| 5190 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 5191 | st->print_raw("\t# int"); |
| 5192 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 5193 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 5194 | st->print(" ! Field: "); |
| 5195 | if (f->is_volatile()) |
| 5196 | st->print("volatile "); |
| 5197 | f->holder()->name()->print_symbol_on(st); |
| 5198 | st->print("."); |
| 5199 | f->name()->print_symbol_on(st); |
| 5200 | if (f->is_constant()) |
| 5201 | st->print(" (constant)"); |
| 5202 | } else { |
| 5203 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 5204 | st->print(" volatile!"); |
| 5205 | } |
| 5206 | } |
| 5207 | #endif |
| 5208 | #ifndef PRODUCT |
| 5209 | void addI_mem_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 5210 | // Start at oper_input_base() and count operands |
| 5211 | unsigned idx0 = 2; |
| 5212 | unsigned idx1 = 2; // dst |
| 5213 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 5214 | st->print_raw("addl "); |
| 5215 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 5216 | st->print_raw(", "); |
| 5217 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 5218 | st->print_raw("\t# int"); |
| 5219 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 5220 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 5221 | st->print(" ! Field: "); |
| 5222 | if (f->is_volatile()) |
| 5223 | st->print("volatile "); |
| 5224 | f->holder()->name()->print_symbol_on(st); |
| 5225 | st->print("."); |
| 5226 | f->name()->print_symbol_on(st); |
| 5227 | if (f->is_constant()) |
| 5228 | st->print(" (constant)"); |
| 5229 | } else { |
| 5230 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 5231 | st->print(" volatile!"); |
| 5232 | } |
| 5233 | } |
| 5234 | #endif |
| 5235 | #ifndef PRODUCT |
| 5236 | void incI_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 5237 | // Start at oper_input_base() and count operands |
| 5238 | unsigned idx0 = 1; |
| 5239 | unsigned idx1 = 1; // dst |
| 5240 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 5241 | st->print_raw("incl "); |
| 5242 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 5243 | st->print_raw("\t# int"); |
| 5244 | } |
| 5245 | #endif |
| 5246 | #ifndef PRODUCT |
| 5247 | void incI_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 5248 | // Start at oper_input_base() and count operands |
| 5249 | unsigned idx0 = 2; |
| 5250 | unsigned idx1 = 2; // dst |
| 5251 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 5252 | st->print_raw("incl "); |
| 5253 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 5254 | st->print_raw("\t# int"); |
| 5255 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 5256 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 5257 | st->print(" ! Field: "); |
| 5258 | if (f->is_volatile()) |
| 5259 | st->print("volatile "); |
| 5260 | f->holder()->name()->print_symbol_on(st); |
| 5261 | st->print("."); |
| 5262 | f->name()->print_symbol_on(st); |
| 5263 | if (f->is_constant()) |
| 5264 | st->print(" (constant)"); |
| 5265 | } else { |
| 5266 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 5267 | st->print(" volatile!"); |
| 5268 | } |
| 5269 | } |
| 5270 | #endif |
| 5271 | #ifndef PRODUCT |
| 5272 | void decI_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 5273 | // Start at oper_input_base() and count operands |
| 5274 | unsigned idx0 = 1; |
| 5275 | unsigned idx1 = 1; // dst |
| 5276 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 5277 | st->print_raw("decl "); |
| 5278 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 5279 | st->print_raw("\t# int"); |
| 5280 | } |
| 5281 | #endif |
| 5282 | #ifndef PRODUCT |
| 5283 | void decI_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 5284 | // Start at oper_input_base() and count operands |
| 5285 | unsigned idx0 = 2; |
| 5286 | unsigned idx1 = 2; // dst |
| 5287 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 5288 | st->print_raw("decl "); |
| 5289 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 5290 | st->print_raw("\t# int"); |
| 5291 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 5292 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 5293 | st->print(" ! Field: "); |
| 5294 | if (f->is_volatile()) |
| 5295 | st->print("volatile "); |
| 5296 | f->holder()->name()->print_symbol_on(st); |
| 5297 | st->print("."); |
| 5298 | f->name()->print_symbol_on(st); |
| 5299 | if (f->is_constant()) |
| 5300 | st->print(" (constant)"); |
| 5301 | } else { |
| 5302 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 5303 | st->print(" volatile!"); |
| 5304 | } |
| 5305 | } |
| 5306 | #endif |
| 5307 | #ifndef PRODUCT |
| 5308 | void leaI_rReg_immINode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 5309 | // Start at oper_input_base() and count operands |
| 5310 | unsigned idx0 = 1; |
| 5311 | unsigned idx1 = 1; // src0 |
| 5312 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src1 |
| 5313 | st->print_raw("addr32 leal "); |
| 5314 | opnd_array(0)->int_format(ra, this, st); // dst |
| 5315 | st->print_raw(", ["); |
| 5316 | opnd_array(1)->ext_format(ra, this,idx1, st); // src0 |
| 5317 | st->print_raw(" + "); |
| 5318 | opnd_array(2)->ext_format(ra, this,idx2, st); // src1 |
| 5319 | st->print_raw("]\t# int"); |
| 5320 | } |
| 5321 | #endif |
| 5322 | #ifndef PRODUCT |
| 5323 | void addL_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 5324 | // Start at oper_input_base() and count operands |
| 5325 | unsigned idx0 = 1; |
| 5326 | unsigned idx1 = 1; // dst |
| 5327 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 5328 | st->print_raw("addq "); |
| 5329 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 5330 | st->print_raw(", "); |
| 5331 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 5332 | st->print_raw("\t# long"); |
| 5333 | } |
| 5334 | #endif |
| 5335 | #ifndef PRODUCT |
| 5336 | void addL_rReg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 5337 | // Start at oper_input_base() and count operands |
| 5338 | unsigned idx0 = 1; |
| 5339 | unsigned idx1 = 1; // dst |
| 5340 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 5341 | st->print_raw("addq "); |
| 5342 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 5343 | st->print_raw(", "); |
| 5344 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 5345 | st->print_raw("\t# long"); |
| 5346 | } |
| 5347 | #endif |
| 5348 | #ifndef PRODUCT |
| 5349 | void addL_rReg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 5350 | // Start at oper_input_base() and count operands |
| 5351 | unsigned idx0 = 2; |
| 5352 | unsigned idx1 = 2; // dst |
| 5353 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 5354 | st->print_raw("addq "); |
| 5355 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 5356 | st->print_raw(", "); |
| 5357 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 5358 | st->print_raw("\t# long"); |
| 5359 | } |
| 5360 | #endif |
| 5361 | #ifndef PRODUCT |
| 5362 | void addL_rReg_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 5363 | // Start at oper_input_base() and count operands |
| 5364 | unsigned idx0 = 2; |
| 5365 | unsigned idx1 = 2; // src |
| 5366 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst |
| 5367 | st->print_raw("addq "); |
| 5368 | opnd_array(2)->ext_format(ra, this,idx2, st); // dst |
| 5369 | st->print_raw(", "); |
| 5370 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 5371 | st->print_raw("\t# long"); |
| 5372 | } |
| 5373 | #endif |
| 5374 | #ifndef PRODUCT |
| 5375 | void addL_mem_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 5376 | // Start at oper_input_base() and count operands |
| 5377 | unsigned idx0 = 2; |
| 5378 | unsigned idx1 = 2; // dst |
| 5379 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 5380 | st->print_raw("addq "); |
| 5381 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 5382 | st->print_raw(", "); |
| 5383 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 5384 | st->print_raw("\t# long"); |
| 5385 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 5386 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 5387 | st->print(" ! Field: "); |
| 5388 | if (f->is_volatile()) |
| 5389 | st->print("volatile "); |
| 5390 | f->holder()->name()->print_symbol_on(st); |
| 5391 | st->print("."); |
| 5392 | f->name()->print_symbol_on(st); |
| 5393 | if (f->is_constant()) |
| 5394 | st->print(" (constant)"); |
| 5395 | } else { |
| 5396 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 5397 | st->print(" volatile!"); |
| 5398 | } |
| 5399 | } |
| 5400 | #endif |
| 5401 | #ifndef PRODUCT |
| 5402 | void addL_mem_rReg_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 5403 | // Start at oper_input_base() and count operands |
| 5404 | unsigned idx0 = 2; |
| 5405 | unsigned idx1 = 2; // dst |
| 5406 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 5407 | st->print_raw("addq "); |
| 5408 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 5409 | st->print_raw(", "); |
| 5410 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 5411 | st->print_raw("\t# long"); |
| 5412 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 5413 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 5414 | st->print(" ! Field: "); |
| 5415 | if (f->is_volatile()) |
| 5416 | st->print("volatile "); |
| 5417 | f->holder()->name()->print_symbol_on(st); |
| 5418 | st->print("."); |
| 5419 | f->name()->print_symbol_on(st); |
| 5420 | if (f->is_constant()) |
| 5421 | st->print(" (constant)"); |
| 5422 | } else { |
| 5423 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 5424 | st->print(" volatile!"); |
| 5425 | } |
| 5426 | } |
| 5427 | #endif |
| 5428 | #ifndef PRODUCT |
| 5429 | void addL_mem_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 5430 | // Start at oper_input_base() and count operands |
| 5431 | unsigned idx0 = 2; |
| 5432 | unsigned idx1 = 2; // dst |
| 5433 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 5434 | st->print_raw("addq "); |
| 5435 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 5436 | st->print_raw(", "); |
| 5437 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 5438 | st->print_raw("\t# long"); |
| 5439 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 5440 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 5441 | st->print(" ! Field: "); |
| 5442 | if (f->is_volatile()) |
| 5443 | st->print("volatile "); |
| 5444 | f->holder()->name()->print_symbol_on(st); |
| 5445 | st->print("."); |
| 5446 | f->name()->print_symbol_on(st); |
| 5447 | if (f->is_constant()) |
| 5448 | st->print(" (constant)"); |
| 5449 | } else { |
| 5450 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 5451 | st->print(" volatile!"); |
| 5452 | } |
| 5453 | } |
| 5454 | #endif |
| 5455 | #ifndef PRODUCT |
| 5456 | void incL_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 5457 | // Start at oper_input_base() and count operands |
| 5458 | unsigned idx0 = 1; |
| 5459 | unsigned idx1 = 1; // dst |
| 5460 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 5461 | st->print_raw("incq "); |
| 5462 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 5463 | st->print_raw("\t# long"); |
| 5464 | } |
| 5465 | #endif |
| 5466 | #ifndef PRODUCT |
| 5467 | void incL_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 5468 | // Start at oper_input_base() and count operands |
| 5469 | unsigned idx0 = 2; |
| 5470 | unsigned idx1 = 2; // dst |
| 5471 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 5472 | st->print_raw("incq "); |
| 5473 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 5474 | st->print_raw("\t# long"); |
| 5475 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 5476 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 5477 | st->print(" ! Field: "); |
| 5478 | if (f->is_volatile()) |
| 5479 | st->print("volatile "); |
| 5480 | f->holder()->name()->print_symbol_on(st); |
| 5481 | st->print("."); |
| 5482 | f->name()->print_symbol_on(st); |
| 5483 | if (f->is_constant()) |
| 5484 | st->print(" (constant)"); |
| 5485 | } else { |
| 5486 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 5487 | st->print(" volatile!"); |
| 5488 | } |
| 5489 | } |
| 5490 | #endif |
| 5491 | #ifndef PRODUCT |
| 5492 | void decL_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 5493 | // Start at oper_input_base() and count operands |
| 5494 | unsigned idx0 = 1; |
| 5495 | unsigned idx1 = 1; // dst |
| 5496 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 5497 | st->print_raw("decq "); |
| 5498 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 5499 | st->print_raw("\t# long"); |
| 5500 | } |
| 5501 | #endif |
| 5502 | #ifndef PRODUCT |
| 5503 | void decL_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 5504 | // Start at oper_input_base() and count operands |
| 5505 | unsigned idx0 = 2; |
| 5506 | unsigned idx1 = 2; // dst |
| 5507 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 5508 | st->print_raw("decq "); |
| 5509 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 5510 | st->print_raw("\t# long"); |
| 5511 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 5512 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 5513 | st->print(" ! Field: "); |
| 5514 | if (f->is_volatile()) |
| 5515 | st->print("volatile "); |
| 5516 | f->holder()->name()->print_symbol_on(st); |
| 5517 | st->print("."); |
| 5518 | f->name()->print_symbol_on(st); |
| 5519 | if (f->is_constant()) |
| 5520 | st->print(" (constant)"); |
| 5521 | } else { |
| 5522 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 5523 | st->print(" volatile!"); |
| 5524 | } |
| 5525 | } |
| 5526 | #endif |
| 5527 | #ifndef PRODUCT |
| 5528 | void leaL_rReg_immLNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 5529 | // Start at oper_input_base() and count operands |
| 5530 | unsigned idx0 = 1; |
| 5531 | unsigned idx1 = 1; // src0 |
| 5532 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src1 |
| 5533 | st->print_raw("leaq "); |
| 5534 | opnd_array(0)->int_format(ra, this, st); // dst |
| 5535 | st->print_raw(", ["); |
| 5536 | opnd_array(1)->ext_format(ra, this,idx1, st); // src0 |
| 5537 | st->print_raw(" + "); |
| 5538 | opnd_array(2)->ext_format(ra, this,idx2, st); // src1 |
| 5539 | st->print_raw("]\t# long"); |
| 5540 | } |
| 5541 | #endif |
| 5542 | #ifndef PRODUCT |
| 5543 | void addP_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 5544 | // Start at oper_input_base() and count operands |
| 5545 | unsigned idx0 = 2; |
| 5546 | unsigned idx1 = 2; // dst |
| 5547 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 5548 | st->print_raw("addq "); |
| 5549 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 5550 | st->print_raw(", "); |
| 5551 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 5552 | st->print_raw("\t# ptr"); |
| 5553 | } |
| 5554 | #endif |
| 5555 | #ifndef PRODUCT |
| 5556 | void addP_rReg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 5557 | // Start at oper_input_base() and count operands |
| 5558 | unsigned idx0 = 2; |
| 5559 | unsigned idx1 = 2; // dst |
| 5560 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 5561 | st->print_raw("addq "); |
| 5562 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 5563 | st->print_raw(", "); |
| 5564 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 5565 | st->print_raw("\t# ptr"); |
| 5566 | } |
| 5567 | #endif |
| 5568 | #ifndef PRODUCT |
| 5569 | void leaP_rReg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 5570 | // Start at oper_input_base() and count operands |
| 5571 | unsigned idx0 = 2; |
| 5572 | unsigned idx1 = 2; // src0 |
| 5573 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src1 |
| 5574 | st->print_raw("leaq "); |
| 5575 | opnd_array(0)->int_format(ra, this, st); // dst |
| 5576 | st->print_raw(", ["); |
| 5577 | opnd_array(1)->ext_format(ra, this,idx1, st); // src0 |
| 5578 | st->print_raw(" + "); |
| 5579 | opnd_array(2)->ext_format(ra, this,idx2, st); // src1 |
| 5580 | st->print_raw("]\t# ptr"); |
| 5581 | } |
| 5582 | #endif |
| 5583 | #ifndef PRODUCT |
| 5584 | void checkCastPPNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 5585 | // Start at oper_input_base() and count operands |
| 5586 | unsigned idx0 = 1; |
| 5587 | unsigned idx1 = 1; // dst |
| 5588 | st->print_raw("# checkcastPP of "); |
| 5589 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 5590 | } |
| 5591 | #endif |
| 5592 | #ifndef PRODUCT |
| 5593 | void castPPNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 5594 | // Start at oper_input_base() and count operands |
| 5595 | unsigned idx0 = 1; |
| 5596 | unsigned idx1 = 1; // dst |
| 5597 | st->print_raw("# castPP of "); |
| 5598 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 5599 | } |
| 5600 | #endif |
| 5601 | #ifndef PRODUCT |
| 5602 | void castIINode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 5603 | // Start at oper_input_base() and count operands |
| 5604 | unsigned idx0 = 1; |
| 5605 | unsigned idx1 = 1; // dst |
| 5606 | st->print_raw("# castII of "); |
| 5607 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 5608 | } |
| 5609 | #endif |
| 5610 | #ifndef PRODUCT |
| 5611 | void castLLNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 5612 | // Start at oper_input_base() and count operands |
| 5613 | unsigned idx0 = 1; |
| 5614 | unsigned idx1 = 1; // dst |
| 5615 | st->print_raw("# castLL of "); |
| 5616 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 5617 | } |
| 5618 | #endif |
| 5619 | #ifndef PRODUCT |
| 5620 | void castFFNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 5621 | // Start at oper_input_base() and count operands |
| 5622 | unsigned idx0 = 1; |
| 5623 | unsigned idx1 = 1; // dst |
| 5624 | st->print_raw("# castFF of "); |
| 5625 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 5626 | } |
| 5627 | #endif |
| 5628 | #ifndef PRODUCT |
| 5629 | void castDDNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 5630 | // Start at oper_input_base() and count operands |
| 5631 | unsigned idx0 = 1; |
| 5632 | unsigned idx1 = 1; // dst |
| 5633 | st->print_raw("# castDD of "); |
| 5634 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 5635 | } |
| 5636 | #endif |
| 5637 | #ifndef PRODUCT |
| 5638 | void loadPLockedNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 5639 | // Start at oper_input_base() and count operands |
| 5640 | unsigned idx0 = 2; |
| 5641 | unsigned idx1 = 2; // mem |
| 5642 | st->print_raw("movq "); |
| 5643 | opnd_array(0)->int_format(ra, this, st); // dst |
| 5644 | st->print_raw(", "); |
| 5645 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 5646 | st->print_raw("\t# ptr locked"); |
| 5647 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 5648 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 5649 | st->print(" ! Field: "); |
| 5650 | if (f->is_volatile()) |
| 5651 | st->print("volatile "); |
| 5652 | f->holder()->name()->print_symbol_on(st); |
| 5653 | st->print("."); |
| 5654 | f->name()->print_symbol_on(st); |
| 5655 | if (f->is_constant()) |
| 5656 | st->print(" (constant)"); |
| 5657 | } else { |
| 5658 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 5659 | st->print(" volatile!"); |
| 5660 | } |
| 5661 | } |
| 5662 | #endif |
| 5663 | #ifndef PRODUCT |
| 5664 | void storePConditionalNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 5665 | // Start at oper_input_base() and count operands |
| 5666 | unsigned idx0 = 2; |
| 5667 | unsigned idx1 = 2; // heap_top_ptr |
| 5668 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval |
| 5669 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval |
| 5670 | st->print_raw("cmpxchgq "); |
| 5671 | opnd_array(1)->ext_format(ra, this,idx1, st); // heap_top_ptr |
| 5672 | st->print_raw(", "); |
| 5673 | opnd_array(3)->ext_format(ra, this,idx3, st); // newval |
| 5674 | st->print_raw("\t# (ptr) "); |
| 5675 | st->print_raw("If rax == "); |
| 5676 | opnd_array(1)->ext_format(ra, this,idx1, st); // heap_top_ptr |
| 5677 | st->print_raw(" then store "); |
| 5678 | opnd_array(3)->ext_format(ra, this,idx3, st); // newval |
| 5679 | st->print_raw(" into "); |
| 5680 | opnd_array(1)->ext_format(ra, this,idx1, st); // heap_top_ptr |
| 5681 | } |
| 5682 | #endif |
| 5683 | #ifndef PRODUCT |
| 5684 | void storeIConditionalNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 5685 | // Start at oper_input_base() and count operands |
| 5686 | unsigned idx0 = 2; |
| 5687 | unsigned idx1 = 2; // mem |
| 5688 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval |
| 5689 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval |
| 5690 | st->print_raw("cmpxchgl "); |
| 5691 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 5692 | st->print_raw(", "); |
| 5693 | opnd_array(3)->ext_format(ra, this,idx3, st); // newval |
| 5694 | st->print_raw("\t# If rax == "); |
| 5695 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 5696 | st->print_raw(" then store "); |
| 5697 | opnd_array(3)->ext_format(ra, this,idx3, st); // newval |
| 5698 | st->print_raw(" into "); |
| 5699 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 5700 | } |
| 5701 | #endif |
| 5702 | #ifndef PRODUCT |
| 5703 | void storeLConditionalNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 5704 | // Start at oper_input_base() and count operands |
| 5705 | unsigned idx0 = 2; |
| 5706 | unsigned idx1 = 2; // mem |
| 5707 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval |
| 5708 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval |
| 5709 | st->print_raw("cmpxchgq "); |
| 5710 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 5711 | st->print_raw(", "); |
| 5712 | opnd_array(3)->ext_format(ra, this,idx3, st); // newval |
| 5713 | st->print_raw("\t# If rax == "); |
| 5714 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 5715 | st->print_raw(" then store "); |
| 5716 | opnd_array(3)->ext_format(ra, this,idx3, st); // newval |
| 5717 | st->print_raw(" into "); |
| 5718 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 5719 | } |
| 5720 | #endif |
| 5721 | #ifndef PRODUCT |
| 5722 | void compareAndSwapPNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 5723 | // Start at oper_input_base() and count operands |
| 5724 | unsigned idx0 = 2; |
| 5725 | unsigned idx1 = 2; // mem_ptr |
| 5726 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval |
| 5727 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval |
| 5728 | st->print_raw("cmpxchgq "); |
| 5729 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr |
| 5730 | st->print_raw(","); |
| 5731 | opnd_array(3)->ext_format(ra, this,idx3, st); // newval |
| 5732 | st->print_raw("\t# "); |
| 5733 | st->print_raw("If rax == "); |
| 5734 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr |
| 5735 | st->print_raw(" then store "); |
| 5736 | opnd_array(3)->ext_format(ra, this,idx3, st); // newval |
| 5737 | st->print_raw(" into "); |
| 5738 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr |
| 5739 | st->print_raw("\n\t"); |
| 5740 | st->print_raw("sete "); |
| 5741 | opnd_array(0)->int_format(ra, this, st); // res |
| 5742 | st->print_raw("\n\t"); |
| 5743 | st->print_raw("movzbl "); |
| 5744 | opnd_array(0)->int_format(ra, this, st); // res |
| 5745 | st->print_raw(", "); |
| 5746 | opnd_array(0)->int_format(ra, this, st); // res |
| 5747 | } |
| 5748 | #endif |
| 5749 | #ifndef PRODUCT |
| 5750 | void compareAndSwapP_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 5751 | // Start at oper_input_base() and count operands |
| 5752 | unsigned idx0 = 2; |
| 5753 | unsigned idx1 = 2; // mem_ptr |
| 5754 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval |
| 5755 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval |
| 5756 | st->print_raw("cmpxchgq "); |
| 5757 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr |
| 5758 | st->print_raw(","); |
| 5759 | opnd_array(3)->ext_format(ra, this,idx3, st); // newval |
| 5760 | st->print_raw("\t# "); |
| 5761 | st->print_raw("If rax == "); |
| 5762 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr |
| 5763 | st->print_raw(" then store "); |
| 5764 | opnd_array(3)->ext_format(ra, this,idx3, st); // newval |
| 5765 | st->print_raw(" into "); |
| 5766 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr |
| 5767 | st->print_raw("\n\t"); |
| 5768 | st->print_raw("sete "); |
| 5769 | opnd_array(0)->int_format(ra, this, st); // res |
| 5770 | st->print_raw("\n\t"); |
| 5771 | st->print_raw("movzbl "); |
| 5772 | opnd_array(0)->int_format(ra, this, st); // res |
| 5773 | st->print_raw(", "); |
| 5774 | opnd_array(0)->int_format(ra, this, st); // res |
| 5775 | } |
| 5776 | #endif |
| 5777 | #ifndef PRODUCT |
| 5778 | void compareAndSwapLNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 5779 | // Start at oper_input_base() and count operands |
| 5780 | unsigned idx0 = 2; |
| 5781 | unsigned idx1 = 2; // mem_ptr |
| 5782 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval |
| 5783 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval |
| 5784 | st->print_raw("cmpxchgq "); |
| 5785 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr |
| 5786 | st->print_raw(","); |
| 5787 | opnd_array(3)->ext_format(ra, this,idx3, st); // newval |
| 5788 | st->print_raw("\t# "); |
| 5789 | st->print_raw("If rax == "); |
| 5790 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr |
| 5791 | st->print_raw(" then store "); |
| 5792 | opnd_array(3)->ext_format(ra, this,idx3, st); // newval |
| 5793 | st->print_raw(" into "); |
| 5794 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr |
| 5795 | st->print_raw("\n\t"); |
| 5796 | st->print_raw("sete "); |
| 5797 | opnd_array(0)->int_format(ra, this, st); // res |
| 5798 | st->print_raw("\n\t"); |
| 5799 | st->print_raw("movzbl "); |
| 5800 | opnd_array(0)->int_format(ra, this, st); // res |
| 5801 | st->print_raw(", "); |
| 5802 | opnd_array(0)->int_format(ra, this, st); // res |
| 5803 | } |
| 5804 | #endif |
| 5805 | #ifndef PRODUCT |
| 5806 | void compareAndSwapL_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 5807 | // Start at oper_input_base() and count operands |
| 5808 | unsigned idx0 = 2; |
| 5809 | unsigned idx1 = 2; // mem_ptr |
| 5810 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval |
| 5811 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval |
| 5812 | st->print_raw("cmpxchgq "); |
| 5813 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr |
| 5814 | st->print_raw(","); |
| 5815 | opnd_array(3)->ext_format(ra, this,idx3, st); // newval |
| 5816 | st->print_raw("\t# "); |
| 5817 | st->print_raw("If rax == "); |
| 5818 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr |
| 5819 | st->print_raw(" then store "); |
| 5820 | opnd_array(3)->ext_format(ra, this,idx3, st); // newval |
| 5821 | st->print_raw(" into "); |
| 5822 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr |
| 5823 | st->print_raw("\n\t"); |
| 5824 | st->print_raw("sete "); |
| 5825 | opnd_array(0)->int_format(ra, this, st); // res |
| 5826 | st->print_raw("\n\t"); |
| 5827 | st->print_raw("movzbl "); |
| 5828 | opnd_array(0)->int_format(ra, this, st); // res |
| 5829 | st->print_raw(", "); |
| 5830 | opnd_array(0)->int_format(ra, this, st); // res |
| 5831 | } |
| 5832 | #endif |
| 5833 | #ifndef PRODUCT |
| 5834 | void compareAndSwapINode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 5835 | // Start at oper_input_base() and count operands |
| 5836 | unsigned idx0 = 2; |
| 5837 | unsigned idx1 = 2; // mem_ptr |
| 5838 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval |
| 5839 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval |
| 5840 | st->print_raw("cmpxchgl "); |
| 5841 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr |
| 5842 | st->print_raw(","); |
| 5843 | opnd_array(3)->ext_format(ra, this,idx3, st); // newval |
| 5844 | st->print_raw("\t# "); |
| 5845 | st->print_raw("If rax == "); |
| 5846 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr |
| 5847 | st->print_raw(" then store "); |
| 5848 | opnd_array(3)->ext_format(ra, this,idx3, st); // newval |
| 5849 | st->print_raw(" into "); |
| 5850 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr |
| 5851 | st->print_raw("\n\t"); |
| 5852 | st->print_raw("sete "); |
| 5853 | opnd_array(0)->int_format(ra, this, st); // res |
| 5854 | st->print_raw("\n\t"); |
| 5855 | st->print_raw("movzbl "); |
| 5856 | opnd_array(0)->int_format(ra, this, st); // res |
| 5857 | st->print_raw(", "); |
| 5858 | opnd_array(0)->int_format(ra, this, st); // res |
| 5859 | } |
| 5860 | #endif |
| 5861 | #ifndef PRODUCT |
| 5862 | void compareAndSwapI_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 5863 | // Start at oper_input_base() and count operands |
| 5864 | unsigned idx0 = 2; |
| 5865 | unsigned idx1 = 2; // mem_ptr |
| 5866 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval |
| 5867 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval |
| 5868 | st->print_raw("cmpxchgl "); |
| 5869 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr |
| 5870 | st->print_raw(","); |
| 5871 | opnd_array(3)->ext_format(ra, this,idx3, st); // newval |
| 5872 | st->print_raw("\t# "); |
| 5873 | st->print_raw("If rax == "); |
| 5874 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr |
| 5875 | st->print_raw(" then store "); |
| 5876 | opnd_array(3)->ext_format(ra, this,idx3, st); // newval |
| 5877 | st->print_raw(" into "); |
| 5878 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr |
| 5879 | st->print_raw("\n\t"); |
| 5880 | st->print_raw("sete "); |
| 5881 | opnd_array(0)->int_format(ra, this, st); // res |
| 5882 | st->print_raw("\n\t"); |
| 5883 | st->print_raw("movzbl "); |
| 5884 | opnd_array(0)->int_format(ra, this, st); // res |
| 5885 | st->print_raw(", "); |
| 5886 | opnd_array(0)->int_format(ra, this, st); // res |
| 5887 | } |
| 5888 | #endif |
| 5889 | #ifndef PRODUCT |
| 5890 | void compareAndSwapBNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 5891 | // Start at oper_input_base() and count operands |
| 5892 | unsigned idx0 = 2; |
| 5893 | unsigned idx1 = 2; // mem_ptr |
| 5894 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval |
| 5895 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval |
| 5896 | st->print_raw("cmpxchgb "); |
| 5897 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr |
| 5898 | st->print_raw(","); |
| 5899 | opnd_array(3)->ext_format(ra, this,idx3, st); // newval |
| 5900 | st->print_raw("\t# "); |
| 5901 | st->print_raw("If rax == "); |
| 5902 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr |
| 5903 | st->print_raw(" then store "); |
| 5904 | opnd_array(3)->ext_format(ra, this,idx3, st); // newval |
| 5905 | st->print_raw(" into "); |
| 5906 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr |
| 5907 | st->print_raw("\n\t"); |
| 5908 | st->print_raw("sete "); |
| 5909 | opnd_array(0)->int_format(ra, this, st); // res |
| 5910 | st->print_raw("\n\t"); |
| 5911 | st->print_raw("movzbl "); |
| 5912 | opnd_array(0)->int_format(ra, this, st); // res |
| 5913 | st->print_raw(", "); |
| 5914 | opnd_array(0)->int_format(ra, this, st); // res |
| 5915 | } |
| 5916 | #endif |
| 5917 | #ifndef PRODUCT |
| 5918 | void compareAndSwapB_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 5919 | // Start at oper_input_base() and count operands |
| 5920 | unsigned idx0 = 2; |
| 5921 | unsigned idx1 = 2; // mem_ptr |
| 5922 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval |
| 5923 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval |
| 5924 | st->print_raw("cmpxchgb "); |
| 5925 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr |
| 5926 | st->print_raw(","); |
| 5927 | opnd_array(3)->ext_format(ra, this,idx3, st); // newval |
| 5928 | st->print_raw("\t# "); |
| 5929 | st->print_raw("If rax == "); |
| 5930 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr |
| 5931 | st->print_raw(" then store "); |
| 5932 | opnd_array(3)->ext_format(ra, this,idx3, st); // newval |
| 5933 | st->print_raw(" into "); |
| 5934 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr |
| 5935 | st->print_raw("\n\t"); |
| 5936 | st->print_raw("sete "); |
| 5937 | opnd_array(0)->int_format(ra, this, st); // res |
| 5938 | st->print_raw("\n\t"); |
| 5939 | st->print_raw("movzbl "); |
| 5940 | opnd_array(0)->int_format(ra, this, st); // res |
| 5941 | st->print_raw(", "); |
| 5942 | opnd_array(0)->int_format(ra, this, st); // res |
| 5943 | } |
| 5944 | #endif |
| 5945 | #ifndef PRODUCT |
| 5946 | void compareAndSwapSNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 5947 | // Start at oper_input_base() and count operands |
| 5948 | unsigned idx0 = 2; |
| 5949 | unsigned idx1 = 2; // mem_ptr |
| 5950 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval |
| 5951 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval |
| 5952 | st->print_raw("cmpxchgw "); |
| 5953 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr |
| 5954 | st->print_raw(","); |
| 5955 | opnd_array(3)->ext_format(ra, this,idx3, st); // newval |
| 5956 | st->print_raw("\t# "); |
| 5957 | st->print_raw("If rax == "); |
| 5958 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr |
| 5959 | st->print_raw(" then store "); |
| 5960 | opnd_array(3)->ext_format(ra, this,idx3, st); // newval |
| 5961 | st->print_raw(" into "); |
| 5962 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr |
| 5963 | st->print_raw("\n\t"); |
| 5964 | st->print_raw("sete "); |
| 5965 | opnd_array(0)->int_format(ra, this, st); // res |
| 5966 | st->print_raw("\n\t"); |
| 5967 | st->print_raw("movzbl "); |
| 5968 | opnd_array(0)->int_format(ra, this, st); // res |
| 5969 | st->print_raw(", "); |
| 5970 | opnd_array(0)->int_format(ra, this, st); // res |
| 5971 | } |
| 5972 | #endif |
| 5973 | #ifndef PRODUCT |
| 5974 | void compareAndSwapS_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 5975 | // Start at oper_input_base() and count operands |
| 5976 | unsigned idx0 = 2; |
| 5977 | unsigned idx1 = 2; // mem_ptr |
| 5978 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval |
| 5979 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval |
| 5980 | st->print_raw("cmpxchgw "); |
| 5981 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr |
| 5982 | st->print_raw(","); |
| 5983 | opnd_array(3)->ext_format(ra, this,idx3, st); // newval |
| 5984 | st->print_raw("\t# "); |
| 5985 | st->print_raw("If rax == "); |
| 5986 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr |
| 5987 | st->print_raw(" then store "); |
| 5988 | opnd_array(3)->ext_format(ra, this,idx3, st); // newval |
| 5989 | st->print_raw(" into "); |
| 5990 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr |
| 5991 | st->print_raw("\n\t"); |
| 5992 | st->print_raw("sete "); |
| 5993 | opnd_array(0)->int_format(ra, this, st); // res |
| 5994 | st->print_raw("\n\t"); |
| 5995 | st->print_raw("movzbl "); |
| 5996 | opnd_array(0)->int_format(ra, this, st); // res |
| 5997 | st->print_raw(", "); |
| 5998 | opnd_array(0)->int_format(ra, this, st); // res |
| 5999 | } |
| 6000 | #endif |
| 6001 | #ifndef PRODUCT |
| 6002 | void compareAndSwapNNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 6003 | // Start at oper_input_base() and count operands |
| 6004 | unsigned idx0 = 2; |
| 6005 | unsigned idx1 = 2; // mem_ptr |
| 6006 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval |
| 6007 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval |
| 6008 | st->print_raw("cmpxchgl "); |
| 6009 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr |
| 6010 | st->print_raw(","); |
| 6011 | opnd_array(3)->ext_format(ra, this,idx3, st); // newval |
| 6012 | st->print_raw("\t# "); |
| 6013 | st->print_raw("If rax == "); |
| 6014 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr |
| 6015 | st->print_raw(" then store "); |
| 6016 | opnd_array(3)->ext_format(ra, this,idx3, st); // newval |
| 6017 | st->print_raw(" into "); |
| 6018 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr |
| 6019 | st->print_raw("\n\t"); |
| 6020 | st->print_raw("sete "); |
| 6021 | opnd_array(0)->int_format(ra, this, st); // res |
| 6022 | st->print_raw("\n\t"); |
| 6023 | st->print_raw("movzbl "); |
| 6024 | opnd_array(0)->int_format(ra, this, st); // res |
| 6025 | st->print_raw(", "); |
| 6026 | opnd_array(0)->int_format(ra, this, st); // res |
| 6027 | } |
| 6028 | #endif |
| 6029 | #ifndef PRODUCT |
| 6030 | void compareAndSwapN_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 6031 | // Start at oper_input_base() and count operands |
| 6032 | unsigned idx0 = 2; |
| 6033 | unsigned idx1 = 2; // mem_ptr |
| 6034 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval |
| 6035 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval |
| 6036 | st->print_raw("cmpxchgl "); |
| 6037 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr |
| 6038 | st->print_raw(","); |
| 6039 | opnd_array(3)->ext_format(ra, this,idx3, st); // newval |
| 6040 | st->print_raw("\t# "); |
| 6041 | st->print_raw("If rax == "); |
| 6042 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr |
| 6043 | st->print_raw(" then store "); |
| 6044 | opnd_array(3)->ext_format(ra, this,idx3, st); // newval |
| 6045 | st->print_raw(" into "); |
| 6046 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr |
| 6047 | st->print_raw("\n\t"); |
| 6048 | st->print_raw("sete "); |
| 6049 | opnd_array(0)->int_format(ra, this, st); // res |
| 6050 | st->print_raw("\n\t"); |
| 6051 | st->print_raw("movzbl "); |
| 6052 | opnd_array(0)->int_format(ra, this, st); // res |
| 6053 | st->print_raw(", "); |
| 6054 | opnd_array(0)->int_format(ra, this, st); // res |
| 6055 | } |
| 6056 | #endif |
| 6057 | #ifndef PRODUCT |
| 6058 | void compareAndExchangeBNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 6059 | // Start at oper_input_base() and count operands |
| 6060 | unsigned idx0 = 2; |
| 6061 | unsigned idx1 = 2; // mem_ptr |
| 6062 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval |
| 6063 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval |
| 6064 | st->print_raw("cmpxchgb "); |
| 6065 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr |
| 6066 | st->print_raw(","); |
| 6067 | opnd_array(3)->ext_format(ra, this,idx3, st); // newval |
| 6068 | st->print_raw("\t# "); |
| 6069 | st->print_raw("If rax == "); |
| 6070 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr |
| 6071 | st->print_raw(" then store "); |
| 6072 | opnd_array(3)->ext_format(ra, this,idx3, st); // newval |
| 6073 | st->print_raw(" into "); |
| 6074 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr |
| 6075 | st->print_raw("\n\t"); |
| 6076 | } |
| 6077 | #endif |
| 6078 | #ifndef PRODUCT |
| 6079 | void compareAndExchangeSNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 6080 | // Start at oper_input_base() and count operands |
| 6081 | unsigned idx0 = 2; |
| 6082 | unsigned idx1 = 2; // mem_ptr |
| 6083 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval |
| 6084 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval |
| 6085 | st->print_raw("cmpxchgw "); |
| 6086 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr |
| 6087 | st->print_raw(","); |
| 6088 | opnd_array(3)->ext_format(ra, this,idx3, st); // newval |
| 6089 | st->print_raw("\t# "); |
| 6090 | st->print_raw("If rax == "); |
| 6091 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr |
| 6092 | st->print_raw(" then store "); |
| 6093 | opnd_array(3)->ext_format(ra, this,idx3, st); // newval |
| 6094 | st->print_raw(" into "); |
| 6095 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr |
| 6096 | st->print_raw("\n\t"); |
| 6097 | } |
| 6098 | #endif |
| 6099 | #ifndef PRODUCT |
| 6100 | void compareAndExchangeINode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 6101 | // Start at oper_input_base() and count operands |
| 6102 | unsigned idx0 = 2; |
| 6103 | unsigned idx1 = 2; // mem_ptr |
| 6104 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval |
| 6105 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval |
| 6106 | st->print_raw("cmpxchgl "); |
| 6107 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr |
| 6108 | st->print_raw(","); |
| 6109 | opnd_array(3)->ext_format(ra, this,idx3, st); // newval |
| 6110 | st->print_raw("\t# "); |
| 6111 | st->print_raw("If rax == "); |
| 6112 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr |
| 6113 | st->print_raw(" then store "); |
| 6114 | opnd_array(3)->ext_format(ra, this,idx3, st); // newval |
| 6115 | st->print_raw(" into "); |
| 6116 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr |
| 6117 | st->print_raw("\n\t"); |
| 6118 | } |
| 6119 | #endif |
| 6120 | #ifndef PRODUCT |
| 6121 | void compareAndExchangeLNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 6122 | // Start at oper_input_base() and count operands |
| 6123 | unsigned idx0 = 2; |
| 6124 | unsigned idx1 = 2; // mem_ptr |
| 6125 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval |
| 6126 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval |
| 6127 | st->print_raw("cmpxchgq "); |
| 6128 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr |
| 6129 | st->print_raw(","); |
| 6130 | opnd_array(3)->ext_format(ra, this,idx3, st); // newval |
| 6131 | st->print_raw("\t# "); |
| 6132 | st->print_raw("If rax == "); |
| 6133 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr |
| 6134 | st->print_raw(" then store "); |
| 6135 | opnd_array(3)->ext_format(ra, this,idx3, st); // newval |
| 6136 | st->print_raw(" into "); |
| 6137 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr |
| 6138 | st->print_raw("\n\t"); |
| 6139 | } |
| 6140 | #endif |
| 6141 | #ifndef PRODUCT |
| 6142 | void compareAndExchangeNNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 6143 | // Start at oper_input_base() and count operands |
| 6144 | unsigned idx0 = 2; |
| 6145 | unsigned idx1 = 2; // mem_ptr |
| 6146 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval |
| 6147 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval |
| 6148 | st->print_raw("cmpxchgl "); |
| 6149 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr |
| 6150 | st->print_raw(","); |
| 6151 | opnd_array(3)->ext_format(ra, this,idx3, st); // newval |
| 6152 | st->print_raw("\t# "); |
| 6153 | st->print_raw("If rax == "); |
| 6154 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr |
| 6155 | st->print_raw(" then store "); |
| 6156 | opnd_array(3)->ext_format(ra, this,idx3, st); // newval |
| 6157 | st->print_raw(" into "); |
| 6158 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr |
| 6159 | st->print_raw("\n\t"); |
| 6160 | } |
| 6161 | #endif |
| 6162 | #ifndef PRODUCT |
| 6163 | void compareAndExchangePNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 6164 | // Start at oper_input_base() and count operands |
| 6165 | unsigned idx0 = 2; |
| 6166 | unsigned idx1 = 2; // mem_ptr |
| 6167 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval |
| 6168 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval |
| 6169 | st->print_raw("cmpxchgq "); |
| 6170 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr |
| 6171 | st->print_raw(","); |
| 6172 | opnd_array(3)->ext_format(ra, this,idx3, st); // newval |
| 6173 | st->print_raw("\t# "); |
| 6174 | st->print_raw("If rax == "); |
| 6175 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr |
| 6176 | st->print_raw(" then store "); |
| 6177 | opnd_array(3)->ext_format(ra, this,idx3, st); // newval |
| 6178 | st->print_raw(" into "); |
| 6179 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr |
| 6180 | st->print_raw("\n\t"); |
| 6181 | } |
| 6182 | #endif |
| 6183 | #ifndef PRODUCT |
| 6184 | void xaddB_no_resNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 6185 | // Start at oper_input_base() and count operands |
| 6186 | unsigned idx0 = 2; |
| 6187 | unsigned idx1 = 2; // mem |
| 6188 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // add |
| 6189 | st->print_raw("ADDB ["); |
| 6190 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 6191 | st->print_raw("],"); |
| 6192 | opnd_array(2)->ext_format(ra, this,idx2, st); // add |
| 6193 | } |
| 6194 | #endif |
| 6195 | #ifndef PRODUCT |
| 6196 | void xaddBNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 6197 | // Start at oper_input_base() and count operands |
| 6198 | unsigned idx0 = 2; |
| 6199 | unsigned idx1 = 2; // mem |
| 6200 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // newval |
| 6201 | st->print_raw("XADDB ["); |
| 6202 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 6203 | st->print_raw("],"); |
| 6204 | opnd_array(2)->ext_format(ra, this,idx2, st); // newval |
| 6205 | } |
| 6206 | #endif |
| 6207 | #ifndef PRODUCT |
| 6208 | void xaddS_no_resNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 6209 | // Start at oper_input_base() and count operands |
| 6210 | unsigned idx0 = 2; |
| 6211 | unsigned idx1 = 2; // mem |
| 6212 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // add |
| 6213 | st->print_raw("ADDW ["); |
| 6214 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 6215 | st->print_raw("],"); |
| 6216 | opnd_array(2)->ext_format(ra, this,idx2, st); // add |
| 6217 | } |
| 6218 | #endif |
| 6219 | #ifndef PRODUCT |
| 6220 | void xaddSNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 6221 | // Start at oper_input_base() and count operands |
| 6222 | unsigned idx0 = 2; |
| 6223 | unsigned idx1 = 2; // mem |
| 6224 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // newval |
| 6225 | st->print_raw("XADDW ["); |
| 6226 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 6227 | st->print_raw("],"); |
| 6228 | opnd_array(2)->ext_format(ra, this,idx2, st); // newval |
| 6229 | } |
| 6230 | #endif |
| 6231 | #ifndef PRODUCT |
| 6232 | void xaddI_no_resNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 6233 | // Start at oper_input_base() and count operands |
| 6234 | unsigned idx0 = 2; |
| 6235 | unsigned idx1 = 2; // mem |
| 6236 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // add |
| 6237 | st->print_raw("ADDL ["); |
| 6238 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 6239 | st->print_raw("],"); |
| 6240 | opnd_array(2)->ext_format(ra, this,idx2, st); // add |
| 6241 | } |
| 6242 | #endif |
| 6243 | #ifndef PRODUCT |
| 6244 | void xaddINode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 6245 | // Start at oper_input_base() and count operands |
| 6246 | unsigned idx0 = 2; |
| 6247 | unsigned idx1 = 2; // mem |
| 6248 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // newval |
| 6249 | st->print_raw("XADDL ["); |
| 6250 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 6251 | st->print_raw("],"); |
| 6252 | opnd_array(2)->ext_format(ra, this,idx2, st); // newval |
| 6253 | } |
| 6254 | #endif |
| 6255 | #ifndef PRODUCT |
| 6256 | void xaddL_no_resNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 6257 | // Start at oper_input_base() and count operands |
| 6258 | unsigned idx0 = 2; |
| 6259 | unsigned idx1 = 2; // mem |
| 6260 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // add |
| 6261 | st->print_raw("ADDQ ["); |
| 6262 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 6263 | st->print_raw("],"); |
| 6264 | opnd_array(2)->ext_format(ra, this,idx2, st); // add |
| 6265 | } |
| 6266 | #endif |
| 6267 | #ifndef PRODUCT |
| 6268 | void xaddLNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 6269 | // Start at oper_input_base() and count operands |
| 6270 | unsigned idx0 = 2; |
| 6271 | unsigned idx1 = 2; // mem |
| 6272 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // newval |
| 6273 | st->print_raw("XADDQ ["); |
| 6274 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 6275 | st->print_raw("],"); |
| 6276 | opnd_array(2)->ext_format(ra, this,idx2, st); // newval |
| 6277 | } |
| 6278 | #endif |
| 6279 | #ifndef PRODUCT |
| 6280 | void xchgBNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 6281 | // Start at oper_input_base() and count operands |
| 6282 | unsigned idx0 = 2; |
| 6283 | unsigned idx1 = 2; // mem |
| 6284 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // newval |
| 6285 | st->print_raw("XCHGB "); |
| 6286 | opnd_array(2)->ext_format(ra, this,idx2, st); // newval |
| 6287 | st->print_raw(",["); |
| 6288 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 6289 | st->print_raw("]"); |
| 6290 | } |
| 6291 | #endif |
| 6292 | #ifndef PRODUCT |
| 6293 | void xchgSNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 6294 | // Start at oper_input_base() and count operands |
| 6295 | unsigned idx0 = 2; |
| 6296 | unsigned idx1 = 2; // mem |
| 6297 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // newval |
| 6298 | st->print_raw("XCHGW "); |
| 6299 | opnd_array(2)->ext_format(ra, this,idx2, st); // newval |
| 6300 | st->print_raw(",["); |
| 6301 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 6302 | st->print_raw("]"); |
| 6303 | } |
| 6304 | #endif |
| 6305 | #ifndef PRODUCT |
| 6306 | void xchgINode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 6307 | // Start at oper_input_base() and count operands |
| 6308 | unsigned idx0 = 2; |
| 6309 | unsigned idx1 = 2; // mem |
| 6310 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // newval |
| 6311 | st->print_raw("XCHGL "); |
| 6312 | opnd_array(2)->ext_format(ra, this,idx2, st); // newval |
| 6313 | st->print_raw(",["); |
| 6314 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 6315 | st->print_raw("]"); |
| 6316 | } |
| 6317 | #endif |
| 6318 | #ifndef PRODUCT |
| 6319 | void xchgLNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 6320 | // Start at oper_input_base() and count operands |
| 6321 | unsigned idx0 = 2; |
| 6322 | unsigned idx1 = 2; // mem |
| 6323 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // newval |
| 6324 | st->print_raw("XCHGL "); |
| 6325 | opnd_array(2)->ext_format(ra, this,idx2, st); // newval |
| 6326 | st->print_raw(",["); |
| 6327 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 6328 | st->print_raw("]"); |
| 6329 | } |
| 6330 | #endif |
| 6331 | #ifndef PRODUCT |
| 6332 | void xchgPNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 6333 | // Start at oper_input_base() and count operands |
| 6334 | unsigned idx0 = 2; |
| 6335 | unsigned idx1 = 2; // mem |
| 6336 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // newval |
| 6337 | st->print_raw("XCHGQ "); |
| 6338 | opnd_array(2)->ext_format(ra, this,idx2, st); // newval |
| 6339 | st->print_raw(",["); |
| 6340 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 6341 | st->print_raw("]"); |
| 6342 | } |
| 6343 | #endif |
| 6344 | #ifndef PRODUCT |
| 6345 | void xchgNNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 6346 | // Start at oper_input_base() and count operands |
| 6347 | unsigned idx0 = 2; |
| 6348 | unsigned idx1 = 2; // mem |
| 6349 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // newval |
| 6350 | st->print_raw("XCHGL "); |
| 6351 | opnd_array(2)->ext_format(ra, this,idx2, st); // newval |
| 6352 | st->print_raw(","); |
| 6353 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 6354 | st->print_raw("]"); |
| 6355 | } |
| 6356 | #endif |
| 6357 | #ifndef PRODUCT |
| 6358 | void absI_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 6359 | // Start at oper_input_base() and count operands |
| 6360 | unsigned idx0 = 1; |
| 6361 | unsigned idx1 = 1; // src |
| 6362 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst |
| 6363 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp |
| 6364 | st->print_raw("movl "); |
| 6365 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp |
| 6366 | st->print_raw(", "); |
| 6367 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 6368 | st->print_raw("\n\t"); |
| 6369 | st->print_raw("sarl "); |
| 6370 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp |
| 6371 | st->print_raw(", 31\n\t"); |
| 6372 | st->print_raw("movl "); |
| 6373 | opnd_array(2)->ext_format(ra, this,idx2, st); // dst |
| 6374 | st->print_raw(", "); |
| 6375 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 6376 | st->print_raw("\n\t"); |
| 6377 | st->print_raw("xorl "); |
| 6378 | opnd_array(2)->ext_format(ra, this,idx2, st); // dst |
| 6379 | st->print_raw(", "); |
| 6380 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp |
| 6381 | st->print_raw("\n\t"); |
| 6382 | st->print_raw("subl "); |
| 6383 | opnd_array(2)->ext_format(ra, this,idx2, st); // dst |
| 6384 | st->print_raw(", "); |
| 6385 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp |
| 6386 | st->print_raw("\n"); |
| 6387 | } |
| 6388 | #endif |
| 6389 | #ifndef PRODUCT |
| 6390 | void absL_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 6391 | // Start at oper_input_base() and count operands |
| 6392 | unsigned idx0 = 1; |
| 6393 | unsigned idx1 = 1; // src |
| 6394 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst |
| 6395 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp |
| 6396 | st->print_raw("movq "); |
| 6397 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp |
| 6398 | st->print_raw(", "); |
| 6399 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 6400 | st->print_raw("\n\t"); |
| 6401 | st->print_raw("sarq "); |
| 6402 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp |
| 6403 | st->print_raw(", 63\n\t"); |
| 6404 | st->print_raw("movq "); |
| 6405 | opnd_array(2)->ext_format(ra, this,idx2, st); // dst |
| 6406 | st->print_raw(", "); |
| 6407 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 6408 | st->print_raw("\n\t"); |
| 6409 | st->print_raw("xorq "); |
| 6410 | opnd_array(2)->ext_format(ra, this,idx2, st); // dst |
| 6411 | st->print_raw(", "); |
| 6412 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp |
| 6413 | st->print_raw("\n\t"); |
| 6414 | st->print_raw("subq "); |
| 6415 | opnd_array(2)->ext_format(ra, this,idx2, st); // dst |
| 6416 | st->print_raw(", "); |
| 6417 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp |
| 6418 | st->print_raw("\n"); |
| 6419 | } |
| 6420 | #endif |
| 6421 | #ifndef PRODUCT |
| 6422 | void subI_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 6423 | // Start at oper_input_base() and count operands |
| 6424 | unsigned idx0 = 1; |
| 6425 | unsigned idx1 = 1; // dst |
| 6426 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 6427 | st->print_raw("subl "); |
| 6428 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 6429 | st->print_raw(", "); |
| 6430 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 6431 | st->print_raw("\t# int"); |
| 6432 | } |
| 6433 | #endif |
| 6434 | #ifndef PRODUCT |
| 6435 | void subI_rReg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 6436 | // Start at oper_input_base() and count operands |
| 6437 | unsigned idx0 = 1; |
| 6438 | unsigned idx1 = 1; // dst |
| 6439 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 6440 | st->print_raw("subl "); |
| 6441 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 6442 | st->print_raw(", "); |
| 6443 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 6444 | st->print_raw("\t# int"); |
| 6445 | } |
| 6446 | #endif |
| 6447 | #ifndef PRODUCT |
| 6448 | void subI_rReg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 6449 | // Start at oper_input_base() and count operands |
| 6450 | unsigned idx0 = 2; |
| 6451 | unsigned idx1 = 2; // dst |
| 6452 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 6453 | st->print_raw("subl "); |
| 6454 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 6455 | st->print_raw(", "); |
| 6456 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 6457 | st->print_raw("\t# int"); |
| 6458 | } |
| 6459 | #endif |
| 6460 | #ifndef PRODUCT |
| 6461 | void subI_mem_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 6462 | // Start at oper_input_base() and count operands |
| 6463 | unsigned idx0 = 2; |
| 6464 | unsigned idx1 = 2; // dst |
| 6465 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 6466 | st->print_raw("subl "); |
| 6467 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 6468 | st->print_raw(", "); |
| 6469 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 6470 | st->print_raw("\t# int"); |
| 6471 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 6472 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 6473 | st->print(" ! Field: "); |
| 6474 | if (f->is_volatile()) |
| 6475 | st->print("volatile "); |
| 6476 | f->holder()->name()->print_symbol_on(st); |
| 6477 | st->print("."); |
| 6478 | f->name()->print_symbol_on(st); |
| 6479 | if (f->is_constant()) |
| 6480 | st->print(" (constant)"); |
| 6481 | } else { |
| 6482 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 6483 | st->print(" volatile!"); |
| 6484 | } |
| 6485 | } |
| 6486 | #endif |
| 6487 | #ifndef PRODUCT |
| 6488 | void subI_mem_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 6489 | // Start at oper_input_base() and count operands |
| 6490 | unsigned idx0 = 2; |
| 6491 | unsigned idx1 = 2; // dst |
| 6492 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 6493 | st->print_raw("subl "); |
| 6494 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 6495 | st->print_raw(", "); |
| 6496 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 6497 | st->print_raw("\t# int"); |
| 6498 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 6499 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 6500 | st->print(" ! Field: "); |
| 6501 | if (f->is_volatile()) |
| 6502 | st->print("volatile "); |
| 6503 | f->holder()->name()->print_symbol_on(st); |
| 6504 | st->print("."); |
| 6505 | f->name()->print_symbol_on(st); |
| 6506 | if (f->is_constant()) |
| 6507 | st->print(" (constant)"); |
| 6508 | } else { |
| 6509 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 6510 | st->print(" volatile!"); |
| 6511 | } |
| 6512 | } |
| 6513 | #endif |
| 6514 | #ifndef PRODUCT |
| 6515 | void subL_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 6516 | // Start at oper_input_base() and count operands |
| 6517 | unsigned idx0 = 1; |
| 6518 | unsigned idx1 = 1; // dst |
| 6519 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 6520 | st->print_raw("subq "); |
| 6521 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 6522 | st->print_raw(", "); |
| 6523 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 6524 | st->print_raw("\t# long"); |
| 6525 | } |
| 6526 | #endif |
| 6527 | #ifndef PRODUCT |
| 6528 | void subL_rReg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 6529 | // Start at oper_input_base() and count operands |
| 6530 | unsigned idx0 = 1; |
| 6531 | unsigned idx1 = 1; // dst |
| 6532 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 6533 | st->print_raw("subq "); |
| 6534 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 6535 | st->print_raw(", "); |
| 6536 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 6537 | st->print_raw("\t# long"); |
| 6538 | } |
| 6539 | #endif |
| 6540 | #ifndef PRODUCT |
| 6541 | void subL_rReg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 6542 | // Start at oper_input_base() and count operands |
| 6543 | unsigned idx0 = 2; |
| 6544 | unsigned idx1 = 2; // dst |
| 6545 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 6546 | st->print_raw("subq "); |
| 6547 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 6548 | st->print_raw(", "); |
| 6549 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 6550 | st->print_raw("\t# long"); |
| 6551 | } |
| 6552 | #endif |
| 6553 | #ifndef PRODUCT |
| 6554 | void subL_mem_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 6555 | // Start at oper_input_base() and count operands |
| 6556 | unsigned idx0 = 2; |
| 6557 | unsigned idx1 = 2; // dst |
| 6558 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 6559 | st->print_raw("subq "); |
| 6560 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 6561 | st->print_raw(", "); |
| 6562 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 6563 | st->print_raw("\t# long"); |
| 6564 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 6565 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 6566 | st->print(" ! Field: "); |
| 6567 | if (f->is_volatile()) |
| 6568 | st->print("volatile "); |
| 6569 | f->holder()->name()->print_symbol_on(st); |
| 6570 | st->print("."); |
| 6571 | f->name()->print_symbol_on(st); |
| 6572 | if (f->is_constant()) |
| 6573 | st->print(" (constant)"); |
| 6574 | } else { |
| 6575 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 6576 | st->print(" volatile!"); |
| 6577 | } |
| 6578 | } |
| 6579 | #endif |
| 6580 | #ifndef PRODUCT |
| 6581 | void subL_mem_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 6582 | // Start at oper_input_base() and count operands |
| 6583 | unsigned idx0 = 2; |
| 6584 | unsigned idx1 = 2; // dst |
| 6585 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 6586 | st->print_raw("subq "); |
| 6587 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 6588 | st->print_raw(", "); |
| 6589 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 6590 | st->print_raw("\t# long"); |
| 6591 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 6592 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 6593 | st->print(" ! Field: "); |
| 6594 | if (f->is_volatile()) |
| 6595 | st->print("volatile "); |
| 6596 | f->holder()->name()->print_symbol_on(st); |
| 6597 | st->print("."); |
| 6598 | f->name()->print_symbol_on(st); |
| 6599 | if (f->is_constant()) |
| 6600 | st->print(" (constant)"); |
| 6601 | } else { |
| 6602 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 6603 | st->print(" volatile!"); |
| 6604 | } |
| 6605 | } |
| 6606 | #endif |
| 6607 | #ifndef PRODUCT |
| 6608 | void subP_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 6609 | // Start at oper_input_base() and count operands |
| 6610 | unsigned idx0 = 2; |
| 6611 | unsigned idx1 = 2; // dst |
| 6612 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero |
| 6613 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // src |
| 6614 | st->print_raw("subq "); |
| 6615 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 6616 | st->print_raw(", "); |
| 6617 | opnd_array(3)->ext_format(ra, this,idx3, st); // src |
| 6618 | st->print_raw("\t# ptr - int"); |
| 6619 | } |
| 6620 | #endif |
| 6621 | #ifndef PRODUCT |
| 6622 | void negI_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 6623 | // Start at oper_input_base() and count operands |
| 6624 | unsigned idx0 = 1; |
| 6625 | unsigned idx1 = 1; // zero |
| 6626 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst |
| 6627 | st->print_raw("negl "); |
| 6628 | opnd_array(2)->ext_format(ra, this,idx2, st); // dst |
| 6629 | st->print_raw("\t# int"); |
| 6630 | } |
| 6631 | #endif |
| 6632 | #ifndef PRODUCT |
| 6633 | void negI_rReg_2Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 6634 | // Start at oper_input_base() and count operands |
| 6635 | unsigned idx0 = 1; |
| 6636 | unsigned idx1 = 1; // dst |
| 6637 | st->print_raw("negl "); |
| 6638 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 6639 | st->print_raw("\t# int"); |
| 6640 | } |
| 6641 | #endif |
| 6642 | #ifndef PRODUCT |
| 6643 | void negI_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 6644 | // Start at oper_input_base() and count operands |
| 6645 | unsigned idx0 = 2; |
| 6646 | unsigned idx1 = 2; // dst |
| 6647 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero |
| 6648 | st->print_raw("negl "); |
| 6649 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 6650 | st->print_raw("\t# int"); |
| 6651 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 6652 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 6653 | st->print(" ! Field: "); |
| 6654 | if (f->is_volatile()) |
| 6655 | st->print("volatile "); |
| 6656 | f->holder()->name()->print_symbol_on(st); |
| 6657 | st->print("."); |
| 6658 | f->name()->print_symbol_on(st); |
| 6659 | if (f->is_constant()) |
| 6660 | st->print(" (constant)"); |
| 6661 | } else { |
| 6662 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 6663 | st->print(" volatile!"); |
| 6664 | } |
| 6665 | } |
| 6666 | #endif |
| 6667 | #ifndef PRODUCT |
| 6668 | void negL_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 6669 | // Start at oper_input_base() and count operands |
| 6670 | unsigned idx0 = 1; |
| 6671 | unsigned idx1 = 1; // zero |
| 6672 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst |
| 6673 | st->print_raw("negq "); |
| 6674 | opnd_array(2)->ext_format(ra, this,idx2, st); // dst |
| 6675 | st->print_raw("\t# long"); |
| 6676 | } |
| 6677 | #endif |
| 6678 | #ifndef PRODUCT |
| 6679 | void negL_rReg_2Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 6680 | // Start at oper_input_base() and count operands |
| 6681 | unsigned idx0 = 1; |
| 6682 | unsigned idx1 = 1; // dst |
| 6683 | st->print_raw("negq "); |
| 6684 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 6685 | st->print_raw("\t# int"); |
| 6686 | } |
| 6687 | #endif |
| 6688 | #ifndef PRODUCT |
| 6689 | void negL_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 6690 | // Start at oper_input_base() and count operands |
| 6691 | unsigned idx0 = 2; |
| 6692 | unsigned idx1 = 2; // dst |
| 6693 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero |
| 6694 | st->print_raw("negq "); |
| 6695 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 6696 | st->print_raw("\t# long"); |
| 6697 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 6698 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 6699 | st->print(" ! Field: "); |
| 6700 | if (f->is_volatile()) |
| 6701 | st->print("volatile "); |
| 6702 | f->holder()->name()->print_symbol_on(st); |
| 6703 | st->print("."); |
| 6704 | f->name()->print_symbol_on(st); |
| 6705 | if (f->is_constant()) |
| 6706 | st->print(" (constant)"); |
| 6707 | } else { |
| 6708 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 6709 | st->print(" volatile!"); |
| 6710 | } |
| 6711 | } |
| 6712 | #endif |
| 6713 | #ifndef PRODUCT |
| 6714 | void mulI_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 6715 | // Start at oper_input_base() and count operands |
| 6716 | unsigned idx0 = 1; |
| 6717 | unsigned idx1 = 1; // dst |
| 6718 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 6719 | st->print_raw("imull "); |
| 6720 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 6721 | st->print_raw(", "); |
| 6722 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 6723 | st->print_raw("\t# int"); |
| 6724 | } |
| 6725 | #endif |
| 6726 | #ifndef PRODUCT |
| 6727 | void mulI_rReg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 6728 | // Start at oper_input_base() and count operands |
| 6729 | unsigned idx0 = 1; |
| 6730 | unsigned idx1 = 1; // src |
| 6731 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // imm |
| 6732 | st->print_raw("imull "); |
| 6733 | opnd_array(0)->int_format(ra, this, st); // dst |
| 6734 | st->print_raw(", "); |
| 6735 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 6736 | st->print_raw(", "); |
| 6737 | opnd_array(2)->ext_format(ra, this,idx2, st); // imm |
| 6738 | st->print_raw("\t# int"); |
| 6739 | } |
| 6740 | #endif |
| 6741 | #ifndef PRODUCT |
| 6742 | void mulI_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 6743 | // Start at oper_input_base() and count operands |
| 6744 | unsigned idx0 = 2; |
| 6745 | unsigned idx1 = 2; // dst |
| 6746 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 6747 | st->print_raw("imull "); |
| 6748 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 6749 | st->print_raw(", "); |
| 6750 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 6751 | st->print_raw("\t# int"); |
| 6752 | } |
| 6753 | #endif |
| 6754 | #ifndef PRODUCT |
| 6755 | void mulI_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 6756 | // Start at oper_input_base() and count operands |
| 6757 | unsigned idx0 = 2; |
| 6758 | unsigned idx1 = 2; // src |
| 6759 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst |
| 6760 | st->print_raw("imull "); |
| 6761 | opnd_array(2)->ext_format(ra, this,idx2, st); // dst |
| 6762 | st->print_raw(", "); |
| 6763 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 6764 | st->print_raw("\t# int"); |
| 6765 | } |
| 6766 | #endif |
| 6767 | #ifndef PRODUCT |
| 6768 | void mulI_mem_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 6769 | // Start at oper_input_base() and count operands |
| 6770 | unsigned idx0 = 2; |
| 6771 | unsigned idx1 = 2; // src |
| 6772 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // imm |
| 6773 | st->print_raw("imull "); |
| 6774 | opnd_array(0)->int_format(ra, this, st); // dst |
| 6775 | st->print_raw(", "); |
| 6776 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 6777 | st->print_raw(", "); |
| 6778 | opnd_array(2)->ext_format(ra, this,idx2, st); // imm |
| 6779 | st->print_raw("\t# int"); |
| 6780 | } |
| 6781 | #endif |
| 6782 | #ifndef PRODUCT |
| 6783 | void mulAddS2I_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 6784 | } |
| 6785 | #endif |
| 6786 | #ifndef PRODUCT |
| 6787 | void mulL_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 6788 | // Start at oper_input_base() and count operands |
| 6789 | unsigned idx0 = 1; |
| 6790 | unsigned idx1 = 1; // dst |
| 6791 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 6792 | st->print_raw("imulq "); |
| 6793 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 6794 | st->print_raw(", "); |
| 6795 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 6796 | st->print_raw("\t# long"); |
| 6797 | } |
| 6798 | #endif |
| 6799 | #ifndef PRODUCT |
| 6800 | void mulL_rReg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 6801 | // Start at oper_input_base() and count operands |
| 6802 | unsigned idx0 = 1; |
| 6803 | unsigned idx1 = 1; // src |
| 6804 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // imm |
| 6805 | st->print_raw("imulq "); |
| 6806 | opnd_array(0)->int_format(ra, this, st); // dst |
| 6807 | st->print_raw(", "); |
| 6808 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 6809 | st->print_raw(", "); |
| 6810 | opnd_array(2)->ext_format(ra, this,idx2, st); // imm |
| 6811 | st->print_raw("\t# long"); |
| 6812 | } |
| 6813 | #endif |
| 6814 | #ifndef PRODUCT |
| 6815 | void mulL_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 6816 | // Start at oper_input_base() and count operands |
| 6817 | unsigned idx0 = 2; |
| 6818 | unsigned idx1 = 2; // dst |
| 6819 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 6820 | st->print_raw("imulq "); |
| 6821 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 6822 | st->print_raw(", "); |
| 6823 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 6824 | st->print_raw("\t# long"); |
| 6825 | } |
| 6826 | #endif |
| 6827 | #ifndef PRODUCT |
| 6828 | void mulL_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 6829 | // Start at oper_input_base() and count operands |
| 6830 | unsigned idx0 = 2; |
| 6831 | unsigned idx1 = 2; // src |
| 6832 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst |
| 6833 | st->print_raw("imulq "); |
| 6834 | opnd_array(2)->ext_format(ra, this,idx2, st); // dst |
| 6835 | st->print_raw(", "); |
| 6836 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 6837 | st->print_raw("\t# long"); |
| 6838 | } |
| 6839 | #endif |
| 6840 | #ifndef PRODUCT |
| 6841 | void mulL_mem_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 6842 | // Start at oper_input_base() and count operands |
| 6843 | unsigned idx0 = 2; |
| 6844 | unsigned idx1 = 2; // src |
| 6845 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // imm |
| 6846 | st->print_raw("imulq "); |
| 6847 | opnd_array(0)->int_format(ra, this, st); // dst |
| 6848 | st->print_raw(", "); |
| 6849 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 6850 | st->print_raw(", "); |
| 6851 | opnd_array(2)->ext_format(ra, this,idx2, st); // imm |
| 6852 | st->print_raw("\t# long"); |
| 6853 | } |
| 6854 | #endif |
| 6855 | #ifndef PRODUCT |
| 6856 | void mulHiL_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 6857 | // Start at oper_input_base() and count operands |
| 6858 | unsigned idx0 = 1; |
| 6859 | unsigned idx1 = 1; // src |
| 6860 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // rax |
| 6861 | st->print_raw("imulq RDX:RAX, RAX, "); |
| 6862 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 6863 | st->print_raw("\t# mulhi"); |
| 6864 | } |
| 6865 | #endif |
| 6866 | #ifndef PRODUCT |
| 6867 | void umulHiL_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 6868 | // Start at oper_input_base() and count operands |
| 6869 | unsigned idx0 = 1; |
| 6870 | unsigned idx1 = 1; // src |
| 6871 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // rax |
| 6872 | st->print_raw("mulq RDX:RAX, RAX, "); |
| 6873 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 6874 | st->print_raw("\t# umulhi"); |
| 6875 | } |
| 6876 | #endif |
| 6877 | #ifndef PRODUCT |
| 6878 | void divI_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 6879 | // Start at oper_input_base() and count operands |
| 6880 | unsigned idx0 = 1; |
| 6881 | unsigned idx1 = 1; // rax |
| 6882 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // div |
| 6883 | st->print_raw("cmpl rax, 0x80000000\t# idiv\n\t"); |
| 6884 | st->print_raw("jne,s normal\n\t"); |
| 6885 | st->print_raw("xorl rdx, rdx\n\t"); |
| 6886 | st->print_raw("cmpl "); |
| 6887 | opnd_array(2)->ext_format(ra, this,idx2, st); // div |
| 6888 | st->print_raw(", -1\n\t"); |
| 6889 | st->print_raw("je,s done\n"); |
| 6890 | st->print_raw("normal: cdql\n\t"); |
| 6891 | st->print_raw("idivl "); |
| 6892 | opnd_array(2)->ext_format(ra, this,idx2, st); // div |
| 6893 | st->print_raw("\n"); |
| 6894 | st->print_raw("done:"); |
| 6895 | } |
| 6896 | #endif |
| 6897 | #ifndef PRODUCT |
| 6898 | void divL_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 6899 | // Start at oper_input_base() and count operands |
| 6900 | unsigned idx0 = 1; |
| 6901 | unsigned idx1 = 1; // rax |
| 6902 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // div |
| 6903 | st->print_raw("movq rdx, 0x8000000000000000\t# ldiv\n\t"); |
| 6904 | st->print_raw("cmpq rax, rdx\n\t"); |
| 6905 | st->print_raw("jne,s normal\n\t"); |
| 6906 | st->print_raw("xorl rdx, rdx\n\t"); |
| 6907 | st->print_raw("cmpq "); |
| 6908 | opnd_array(2)->ext_format(ra, this,idx2, st); // div |
| 6909 | st->print_raw(", -1\n\t"); |
| 6910 | st->print_raw("je,s done\n"); |
| 6911 | st->print_raw("normal: cdqq\n\t"); |
| 6912 | st->print_raw("idivq "); |
| 6913 | opnd_array(2)->ext_format(ra, this,idx2, st); // div |
| 6914 | st->print_raw("\n"); |
| 6915 | st->print_raw("done:"); |
| 6916 | } |
| 6917 | #endif |
| 6918 | #ifndef PRODUCT |
| 6919 | void divModI_rReg_divmodNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 6920 | // Start at oper_input_base() and count operands |
| 6921 | unsigned idx0 = 1; |
| 6922 | unsigned idx1 = 1; // div |
| 6923 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // rdx |
| 6924 | st->print_raw("cmpl rax, 0x80000000\t# idiv\n\t"); |
| 6925 | st->print_raw("jne,s normal\n\t"); |
| 6926 | st->print_raw("xorl rdx, rdx\n\t"); |
| 6927 | st->print_raw("cmpl "); |
| 6928 | opnd_array(2)->ext_format(ra, this,idx2, st); // div |
| 6929 | st->print_raw(", -1\n\t"); |
| 6930 | st->print_raw("je,s done\n"); |
| 6931 | st->print_raw("normal: cdql\n\t"); |
| 6932 | st->print_raw("idivl "); |
| 6933 | opnd_array(2)->ext_format(ra, this,idx2, st); // div |
| 6934 | st->print_raw("\n"); |
| 6935 | st->print_raw("done:"); |
| 6936 | } |
| 6937 | #endif |
| 6938 | #ifndef PRODUCT |
| 6939 | void divModL_rReg_divmodNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 6940 | // Start at oper_input_base() and count operands |
| 6941 | unsigned idx0 = 1; |
| 6942 | unsigned idx1 = 1; // div |
| 6943 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // rdx |
| 6944 | st->print_raw("movq rdx, 0x8000000000000000\t# ldiv\n\t"); |
| 6945 | st->print_raw("cmpq rax, rdx\n\t"); |
| 6946 | st->print_raw("jne,s normal\n\t"); |
| 6947 | st->print_raw("xorl rdx, rdx\n\t"); |
| 6948 | st->print_raw("cmpq "); |
| 6949 | opnd_array(2)->ext_format(ra, this,idx2, st); // div |
| 6950 | st->print_raw(", -1\n\t"); |
| 6951 | st->print_raw("je,s done\n"); |
| 6952 | st->print_raw("normal: cdqq\n\t"); |
| 6953 | st->print_raw("idivq "); |
| 6954 | opnd_array(2)->ext_format(ra, this,idx2, st); // div |
| 6955 | st->print_raw("\n"); |
| 6956 | st->print_raw("done:"); |
| 6957 | } |
| 6958 | #endif |
| 6959 | #ifndef PRODUCT |
| 6960 | void loadConL_0x6666666666666667Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 6961 | // Start at oper_input_base() and count operands |
| 6962 | unsigned idx0 = 1; |
| 6963 | unsigned idx1 = 1; // |
| 6964 | st->print_raw("movq "); |
| 6965 | opnd_array(0)->int_format(ra, this, st); // dst |
| 6966 | st->print_raw(", #0x666666666666667\t# Used in div-by-10"); |
| 6967 | } |
| 6968 | #endif |
| 6969 | #ifndef PRODUCT |
| 6970 | void mul_hiNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 6971 | // Start at oper_input_base() and count operands |
| 6972 | unsigned idx0 = 1; |
| 6973 | unsigned idx1 = 1; // src |
| 6974 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // rax |
| 6975 | st->print_raw("imulq rdx:rax, rax, "); |
| 6976 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 6977 | st->print_raw("\t# Used in div-by-10"); |
| 6978 | } |
| 6979 | #endif |
| 6980 | #ifndef PRODUCT |
| 6981 | void sarL_rReg_63Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 6982 | // Start at oper_input_base() and count operands |
| 6983 | unsigned idx0 = 1; |
| 6984 | unsigned idx1 = 1; // cr |
| 6985 | st->print_raw("sarq "); |
| 6986 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 6987 | st->print_raw(", #63\t# Used in div-by-10"); |
| 6988 | } |
| 6989 | #endif |
| 6990 | #ifndef PRODUCT |
| 6991 | void sarL_rReg_2Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 6992 | // Start at oper_input_base() and count operands |
| 6993 | unsigned idx0 = 1; |
| 6994 | unsigned idx1 = 1; // cr |
| 6995 | st->print_raw("sarq "); |
| 6996 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 6997 | st->print_raw(", #2\t# Used in div-by-10"); |
| 6998 | } |
| 6999 | #endif |
| 7000 | #ifndef PRODUCT |
| 7001 | void divL_10Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 7002 | } |
| 7003 | #endif |
| 7004 | #ifndef PRODUCT |
| 7005 | void modI_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 7006 | // Start at oper_input_base() and count operands |
| 7007 | unsigned idx0 = 1; |
| 7008 | unsigned idx1 = 1; // rax |
| 7009 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // div |
| 7010 | st->print_raw("cmpl rax, 0x80000000\t# irem\n\t"); |
| 7011 | st->print_raw("jne,s normal\n\t"); |
| 7012 | st->print_raw("xorl rdx, rdx\n\t"); |
| 7013 | st->print_raw("cmpl "); |
| 7014 | opnd_array(2)->ext_format(ra, this,idx2, st); // div |
| 7015 | st->print_raw(", -1\n\t"); |
| 7016 | st->print_raw("je,s done\n"); |
| 7017 | st->print_raw("normal: cdql\n\t"); |
| 7018 | st->print_raw("idivl "); |
| 7019 | opnd_array(2)->ext_format(ra, this,idx2, st); // div |
| 7020 | st->print_raw("\n"); |
| 7021 | st->print_raw("done:"); |
| 7022 | } |
| 7023 | #endif |
| 7024 | #ifndef PRODUCT |
| 7025 | void modL_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 7026 | // Start at oper_input_base() and count operands |
| 7027 | unsigned idx0 = 1; |
| 7028 | unsigned idx1 = 1; // rax |
| 7029 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // div |
| 7030 | st->print_raw("movq rdx, 0x8000000000000000\t# lrem\n\t"); |
| 7031 | st->print_raw("cmpq rax, rdx\n\t"); |
| 7032 | st->print_raw("jne,s normal\n\t"); |
| 7033 | st->print_raw("xorl rdx, rdx\n\t"); |
| 7034 | st->print_raw("cmpq "); |
| 7035 | opnd_array(2)->ext_format(ra, this,idx2, st); // div |
| 7036 | st->print_raw(", -1\n\t"); |
| 7037 | st->print_raw("je,s done\n"); |
| 7038 | st->print_raw("normal: cdqq\n\t"); |
| 7039 | st->print_raw("idivq "); |
| 7040 | opnd_array(2)->ext_format(ra, this,idx2, st); // div |
| 7041 | st->print_raw("\n"); |
| 7042 | st->print_raw("done:"); |
| 7043 | } |
| 7044 | #endif |
| 7045 | #ifndef PRODUCT |
| 7046 | void salI_rReg_1Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 7047 | // Start at oper_input_base() and count operands |
| 7048 | unsigned idx0 = 1; |
| 7049 | unsigned idx1 = 1; // dst |
| 7050 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 7051 | st->print_raw("sall "); |
| 7052 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 7053 | st->print_raw(", "); |
| 7054 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 7055 | } |
| 7056 | #endif |
| 7057 | #ifndef PRODUCT |
| 7058 | void salI_mem_1Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 7059 | // Start at oper_input_base() and count operands |
| 7060 | unsigned idx0 = 2; |
| 7061 | unsigned idx1 = 2; // dst |
| 7062 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 7063 | st->print_raw("sall "); |
| 7064 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 7065 | st->print_raw(", "); |
| 7066 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 7067 | st->print_raw("\t"); |
| 7068 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 7069 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 7070 | st->print(" ! Field: "); |
| 7071 | if (f->is_volatile()) |
| 7072 | st->print("volatile "); |
| 7073 | f->holder()->name()->print_symbol_on(st); |
| 7074 | st->print("."); |
| 7075 | f->name()->print_symbol_on(st); |
| 7076 | if (f->is_constant()) |
| 7077 | st->print(" (constant)"); |
| 7078 | } else { |
| 7079 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 7080 | st->print(" volatile!"); |
| 7081 | } |
| 7082 | } |
| 7083 | #endif |
| 7084 | #ifndef PRODUCT |
| 7085 | void salI_rReg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 7086 | // Start at oper_input_base() and count operands |
| 7087 | unsigned idx0 = 1; |
| 7088 | unsigned idx1 = 1; // dst |
| 7089 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 7090 | st->print_raw("sall "); |
| 7091 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 7092 | st->print_raw(", "); |
| 7093 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 7094 | } |
| 7095 | #endif |
| 7096 | #ifndef PRODUCT |
| 7097 | void salI_mem_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 7098 | // Start at oper_input_base() and count operands |
| 7099 | unsigned idx0 = 2; |
| 7100 | unsigned idx1 = 2; // dst |
| 7101 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 7102 | st->print_raw("sall "); |
| 7103 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 7104 | st->print_raw(", "); |
| 7105 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 7106 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 7107 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 7108 | st->print(" ! Field: "); |
| 7109 | if (f->is_volatile()) |
| 7110 | st->print("volatile "); |
| 7111 | f->holder()->name()->print_symbol_on(st); |
| 7112 | st->print("."); |
| 7113 | f->name()->print_symbol_on(st); |
| 7114 | if (f->is_constant()) |
| 7115 | st->print(" (constant)"); |
| 7116 | } else { |
| 7117 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 7118 | st->print(" volatile!"); |
| 7119 | } |
| 7120 | } |
| 7121 | #endif |
| 7122 | #ifndef PRODUCT |
| 7123 | void salI_rReg_CLNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 7124 | // Start at oper_input_base() and count operands |
| 7125 | unsigned idx0 = 1; |
| 7126 | unsigned idx1 = 1; // dst |
| 7127 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 7128 | st->print_raw("sall "); |
| 7129 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 7130 | st->print_raw(", "); |
| 7131 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 7132 | } |
| 7133 | #endif |
| 7134 | #ifndef PRODUCT |
| 7135 | void salI_mem_CLNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 7136 | // Start at oper_input_base() and count operands |
| 7137 | unsigned idx0 = 2; |
| 7138 | unsigned idx1 = 2; // dst |
| 7139 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 7140 | st->print_raw("sall "); |
| 7141 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 7142 | st->print_raw(", "); |
| 7143 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 7144 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 7145 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 7146 | st->print(" ! Field: "); |
| 7147 | if (f->is_volatile()) |
| 7148 | st->print("volatile "); |
| 7149 | f->holder()->name()->print_symbol_on(st); |
| 7150 | st->print("."); |
| 7151 | f->name()->print_symbol_on(st); |
| 7152 | if (f->is_constant()) |
| 7153 | st->print(" (constant)"); |
| 7154 | } else { |
| 7155 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 7156 | st->print(" volatile!"); |
| 7157 | } |
| 7158 | } |
| 7159 | #endif |
| 7160 | #ifndef PRODUCT |
| 7161 | void sarI_rReg_1Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 7162 | // Start at oper_input_base() and count operands |
| 7163 | unsigned idx0 = 1; |
| 7164 | unsigned idx1 = 1; // dst |
| 7165 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 7166 | st->print_raw("sarl "); |
| 7167 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 7168 | st->print_raw(", "); |
| 7169 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 7170 | } |
| 7171 | #endif |
| 7172 | #ifndef PRODUCT |
| 7173 | void sarI_mem_1Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 7174 | // Start at oper_input_base() and count operands |
| 7175 | unsigned idx0 = 2; |
| 7176 | unsigned idx1 = 2; // dst |
| 7177 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 7178 | st->print_raw("sarl "); |
| 7179 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 7180 | st->print_raw(", "); |
| 7181 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 7182 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 7183 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 7184 | st->print(" ! Field: "); |
| 7185 | if (f->is_volatile()) |
| 7186 | st->print("volatile "); |
| 7187 | f->holder()->name()->print_symbol_on(st); |
| 7188 | st->print("."); |
| 7189 | f->name()->print_symbol_on(st); |
| 7190 | if (f->is_constant()) |
| 7191 | st->print(" (constant)"); |
| 7192 | } else { |
| 7193 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 7194 | st->print(" volatile!"); |
| 7195 | } |
| 7196 | } |
| 7197 | #endif |
| 7198 | #ifndef PRODUCT |
| 7199 | void sarI_rReg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 7200 | // Start at oper_input_base() and count operands |
| 7201 | unsigned idx0 = 1; |
| 7202 | unsigned idx1 = 1; // dst |
| 7203 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 7204 | st->print_raw("sarl "); |
| 7205 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 7206 | st->print_raw(", "); |
| 7207 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 7208 | } |
| 7209 | #endif |
| 7210 | #ifndef PRODUCT |
| 7211 | void sarI_mem_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 7212 | // Start at oper_input_base() and count operands |
| 7213 | unsigned idx0 = 2; |
| 7214 | unsigned idx1 = 2; // dst |
| 7215 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 7216 | st->print_raw("sarl "); |
| 7217 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 7218 | st->print_raw(", "); |
| 7219 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 7220 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 7221 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 7222 | st->print(" ! Field: "); |
| 7223 | if (f->is_volatile()) |
| 7224 | st->print("volatile "); |
| 7225 | f->holder()->name()->print_symbol_on(st); |
| 7226 | st->print("."); |
| 7227 | f->name()->print_symbol_on(st); |
| 7228 | if (f->is_constant()) |
| 7229 | st->print(" (constant)"); |
| 7230 | } else { |
| 7231 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 7232 | st->print(" volatile!"); |
| 7233 | } |
| 7234 | } |
| 7235 | #endif |
| 7236 | #ifndef PRODUCT |
| 7237 | void sarI_rReg_CLNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 7238 | // Start at oper_input_base() and count operands |
| 7239 | unsigned idx0 = 1; |
| 7240 | unsigned idx1 = 1; // dst |
| 7241 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 7242 | st->print_raw("sarl "); |
| 7243 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 7244 | st->print_raw(", "); |
| 7245 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 7246 | } |
| 7247 | #endif |
| 7248 | #ifndef PRODUCT |
| 7249 | void sarI_mem_CLNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 7250 | // Start at oper_input_base() and count operands |
| 7251 | unsigned idx0 = 2; |
| 7252 | unsigned idx1 = 2; // dst |
| 7253 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 7254 | st->print_raw("sarl "); |
| 7255 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 7256 | st->print_raw(", "); |
| 7257 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 7258 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 7259 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 7260 | st->print(" ! Field: "); |
| 7261 | if (f->is_volatile()) |
| 7262 | st->print("volatile "); |
| 7263 | f->holder()->name()->print_symbol_on(st); |
| 7264 | st->print("."); |
| 7265 | f->name()->print_symbol_on(st); |
| 7266 | if (f->is_constant()) |
| 7267 | st->print(" (constant)"); |
| 7268 | } else { |
| 7269 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 7270 | st->print(" volatile!"); |
| 7271 | } |
| 7272 | } |
| 7273 | #endif |
| 7274 | #ifndef PRODUCT |
| 7275 | void shrI_rReg_1Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 7276 | // Start at oper_input_base() and count operands |
| 7277 | unsigned idx0 = 1; |
| 7278 | unsigned idx1 = 1; // dst |
| 7279 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 7280 | st->print_raw("shrl "); |
| 7281 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 7282 | st->print_raw(", "); |
| 7283 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 7284 | } |
| 7285 | #endif |
| 7286 | #ifndef PRODUCT |
| 7287 | void shrI_mem_1Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 7288 | // Start at oper_input_base() and count operands |
| 7289 | unsigned idx0 = 2; |
| 7290 | unsigned idx1 = 2; // dst |
| 7291 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 7292 | st->print_raw("shrl "); |
| 7293 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 7294 | st->print_raw(", "); |
| 7295 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 7296 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 7297 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 7298 | st->print(" ! Field: "); |
| 7299 | if (f->is_volatile()) |
| 7300 | st->print("volatile "); |
| 7301 | f->holder()->name()->print_symbol_on(st); |
| 7302 | st->print("."); |
| 7303 | f->name()->print_symbol_on(st); |
| 7304 | if (f->is_constant()) |
| 7305 | st->print(" (constant)"); |
| 7306 | } else { |
| 7307 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 7308 | st->print(" volatile!"); |
| 7309 | } |
| 7310 | } |
| 7311 | #endif |
| 7312 | #ifndef PRODUCT |
| 7313 | void shrI_rReg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 7314 | // Start at oper_input_base() and count operands |
| 7315 | unsigned idx0 = 1; |
| 7316 | unsigned idx1 = 1; // dst |
| 7317 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 7318 | st->print_raw("shrl "); |
| 7319 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 7320 | st->print_raw(", "); |
| 7321 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 7322 | } |
| 7323 | #endif |
| 7324 | #ifndef PRODUCT |
| 7325 | void shrI_mem_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 7326 | // Start at oper_input_base() and count operands |
| 7327 | unsigned idx0 = 2; |
| 7328 | unsigned idx1 = 2; // dst |
| 7329 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 7330 | st->print_raw("shrl "); |
| 7331 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 7332 | st->print_raw(", "); |
| 7333 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 7334 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 7335 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 7336 | st->print(" ! Field: "); |
| 7337 | if (f->is_volatile()) |
| 7338 | st->print("volatile "); |
| 7339 | f->holder()->name()->print_symbol_on(st); |
| 7340 | st->print("."); |
| 7341 | f->name()->print_symbol_on(st); |
| 7342 | if (f->is_constant()) |
| 7343 | st->print(" (constant)"); |
| 7344 | } else { |
| 7345 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 7346 | st->print(" volatile!"); |
| 7347 | } |
| 7348 | } |
| 7349 | #endif |
| 7350 | #ifndef PRODUCT |
| 7351 | void shrI_rReg_CLNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 7352 | // Start at oper_input_base() and count operands |
| 7353 | unsigned idx0 = 1; |
| 7354 | unsigned idx1 = 1; // dst |
| 7355 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 7356 | st->print_raw("shrl "); |
| 7357 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 7358 | st->print_raw(", "); |
| 7359 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 7360 | } |
| 7361 | #endif |
| 7362 | #ifndef PRODUCT |
| 7363 | void shrI_mem_CLNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 7364 | // Start at oper_input_base() and count operands |
| 7365 | unsigned idx0 = 2; |
| 7366 | unsigned idx1 = 2; // dst |
| 7367 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 7368 | st->print_raw("shrl "); |
| 7369 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 7370 | st->print_raw(", "); |
| 7371 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 7372 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 7373 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 7374 | st->print(" ! Field: "); |
| 7375 | if (f->is_volatile()) |
| 7376 | st->print("volatile "); |
| 7377 | f->holder()->name()->print_symbol_on(st); |
| 7378 | st->print("."); |
| 7379 | f->name()->print_symbol_on(st); |
| 7380 | if (f->is_constant()) |
| 7381 | st->print(" (constant)"); |
| 7382 | } else { |
| 7383 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 7384 | st->print(" volatile!"); |
| 7385 | } |
| 7386 | } |
| 7387 | #endif |
| 7388 | #ifndef PRODUCT |
| 7389 | void salL_rReg_1Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 7390 | // Start at oper_input_base() and count operands |
| 7391 | unsigned idx0 = 1; |
| 7392 | unsigned idx1 = 1; // dst |
| 7393 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 7394 | st->print_raw("salq "); |
| 7395 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 7396 | st->print_raw(", "); |
| 7397 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 7398 | } |
| 7399 | #endif |
| 7400 | #ifndef PRODUCT |
| 7401 | void salL_mem_1Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 7402 | // Start at oper_input_base() and count operands |
| 7403 | unsigned idx0 = 2; |
| 7404 | unsigned idx1 = 2; // dst |
| 7405 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 7406 | st->print_raw("salq "); |
| 7407 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 7408 | st->print_raw(", "); |
| 7409 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 7410 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 7411 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 7412 | st->print(" ! Field: "); |
| 7413 | if (f->is_volatile()) |
| 7414 | st->print("volatile "); |
| 7415 | f->holder()->name()->print_symbol_on(st); |
| 7416 | st->print("."); |
| 7417 | f->name()->print_symbol_on(st); |
| 7418 | if (f->is_constant()) |
| 7419 | st->print(" (constant)"); |
| 7420 | } else { |
| 7421 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 7422 | st->print(" volatile!"); |
| 7423 | } |
| 7424 | } |
| 7425 | #endif |
| 7426 | #ifndef PRODUCT |
| 7427 | void salL_rReg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 7428 | // Start at oper_input_base() and count operands |
| 7429 | unsigned idx0 = 1; |
| 7430 | unsigned idx1 = 1; // dst |
| 7431 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 7432 | st->print_raw("salq "); |
| 7433 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 7434 | st->print_raw(", "); |
| 7435 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 7436 | } |
| 7437 | #endif |
| 7438 | #ifndef PRODUCT |
| 7439 | void salL_mem_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 7440 | // Start at oper_input_base() and count operands |
| 7441 | unsigned idx0 = 2; |
| 7442 | unsigned idx1 = 2; // dst |
| 7443 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 7444 | st->print_raw("salq "); |
| 7445 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 7446 | st->print_raw(", "); |
| 7447 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 7448 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 7449 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 7450 | st->print(" ! Field: "); |
| 7451 | if (f->is_volatile()) |
| 7452 | st->print("volatile "); |
| 7453 | f->holder()->name()->print_symbol_on(st); |
| 7454 | st->print("."); |
| 7455 | f->name()->print_symbol_on(st); |
| 7456 | if (f->is_constant()) |
| 7457 | st->print(" (constant)"); |
| 7458 | } else { |
| 7459 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 7460 | st->print(" volatile!"); |
| 7461 | } |
| 7462 | } |
| 7463 | #endif |
| 7464 | #ifndef PRODUCT |
| 7465 | void salL_rReg_CLNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 7466 | // Start at oper_input_base() and count operands |
| 7467 | unsigned idx0 = 1; |
| 7468 | unsigned idx1 = 1; // dst |
| 7469 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 7470 | st->print_raw("salq "); |
| 7471 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 7472 | st->print_raw(", "); |
| 7473 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 7474 | } |
| 7475 | #endif |
| 7476 | #ifndef PRODUCT |
| 7477 | void salL_mem_CLNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 7478 | // Start at oper_input_base() and count operands |
| 7479 | unsigned idx0 = 2; |
| 7480 | unsigned idx1 = 2; // dst |
| 7481 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 7482 | st->print_raw("salq "); |
| 7483 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 7484 | st->print_raw(", "); |
| 7485 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 7486 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 7487 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 7488 | st->print(" ! Field: "); |
| 7489 | if (f->is_volatile()) |
| 7490 | st->print("volatile "); |
| 7491 | f->holder()->name()->print_symbol_on(st); |
| 7492 | st->print("."); |
| 7493 | f->name()->print_symbol_on(st); |
| 7494 | if (f->is_constant()) |
| 7495 | st->print(" (constant)"); |
| 7496 | } else { |
| 7497 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 7498 | st->print(" volatile!"); |
| 7499 | } |
| 7500 | } |
| 7501 | #endif |
| 7502 | #ifndef PRODUCT |
| 7503 | void sarL_rReg_1Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 7504 | // Start at oper_input_base() and count operands |
| 7505 | unsigned idx0 = 1; |
| 7506 | unsigned idx1 = 1; // dst |
| 7507 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 7508 | st->print_raw("sarq "); |
| 7509 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 7510 | st->print_raw(", "); |
| 7511 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 7512 | } |
| 7513 | #endif |
| 7514 | #ifndef PRODUCT |
| 7515 | void sarL_mem_1Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 7516 | // Start at oper_input_base() and count operands |
| 7517 | unsigned idx0 = 2; |
| 7518 | unsigned idx1 = 2; // dst |
| 7519 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 7520 | st->print_raw("sarq "); |
| 7521 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 7522 | st->print_raw(", "); |
| 7523 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 7524 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 7525 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 7526 | st->print(" ! Field: "); |
| 7527 | if (f->is_volatile()) |
| 7528 | st->print("volatile "); |
| 7529 | f->holder()->name()->print_symbol_on(st); |
| 7530 | st->print("."); |
| 7531 | f->name()->print_symbol_on(st); |
| 7532 | if (f->is_constant()) |
| 7533 | st->print(" (constant)"); |
| 7534 | } else { |
| 7535 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 7536 | st->print(" volatile!"); |
| 7537 | } |
| 7538 | } |
| 7539 | #endif |
| 7540 | #ifndef PRODUCT |
| 7541 | void sarL_rReg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 7542 | // Start at oper_input_base() and count operands |
| 7543 | unsigned idx0 = 1; |
| 7544 | unsigned idx1 = 1; // dst |
| 7545 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 7546 | st->print_raw("sarq "); |
| 7547 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 7548 | st->print_raw(", "); |
| 7549 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 7550 | } |
| 7551 | #endif |
| 7552 | #ifndef PRODUCT |
| 7553 | void sarL_mem_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 7554 | // Start at oper_input_base() and count operands |
| 7555 | unsigned idx0 = 2; |
| 7556 | unsigned idx1 = 2; // dst |
| 7557 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 7558 | st->print_raw("sarq "); |
| 7559 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 7560 | st->print_raw(", "); |
| 7561 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 7562 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 7563 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 7564 | st->print(" ! Field: "); |
| 7565 | if (f->is_volatile()) |
| 7566 | st->print("volatile "); |
| 7567 | f->holder()->name()->print_symbol_on(st); |
| 7568 | st->print("."); |
| 7569 | f->name()->print_symbol_on(st); |
| 7570 | if (f->is_constant()) |
| 7571 | st->print(" (constant)"); |
| 7572 | } else { |
| 7573 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 7574 | st->print(" volatile!"); |
| 7575 | } |
| 7576 | } |
| 7577 | #endif |
| 7578 | #ifndef PRODUCT |
| 7579 | void sarL_rReg_CLNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 7580 | // Start at oper_input_base() and count operands |
| 7581 | unsigned idx0 = 1; |
| 7582 | unsigned idx1 = 1; // dst |
| 7583 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 7584 | st->print_raw("sarq "); |
| 7585 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 7586 | st->print_raw(", "); |
| 7587 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 7588 | } |
| 7589 | #endif |
| 7590 | #ifndef PRODUCT |
| 7591 | void sarL_mem_CLNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 7592 | // Start at oper_input_base() and count operands |
| 7593 | unsigned idx0 = 2; |
| 7594 | unsigned idx1 = 2; // dst |
| 7595 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 7596 | st->print_raw("sarq "); |
| 7597 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 7598 | st->print_raw(", "); |
| 7599 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 7600 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 7601 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 7602 | st->print(" ! Field: "); |
| 7603 | if (f->is_volatile()) |
| 7604 | st->print("volatile "); |
| 7605 | f->holder()->name()->print_symbol_on(st); |
| 7606 | st->print("."); |
| 7607 | f->name()->print_symbol_on(st); |
| 7608 | if (f->is_constant()) |
| 7609 | st->print(" (constant)"); |
| 7610 | } else { |
| 7611 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 7612 | st->print(" volatile!"); |
| 7613 | } |
| 7614 | } |
| 7615 | #endif |
| 7616 | #ifndef PRODUCT |
| 7617 | void shrL_rReg_1Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 7618 | // Start at oper_input_base() and count operands |
| 7619 | unsigned idx0 = 1; |
| 7620 | unsigned idx1 = 1; // dst |
| 7621 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 7622 | st->print_raw("shrq "); |
| 7623 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 7624 | st->print_raw(", "); |
| 7625 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 7626 | } |
| 7627 | #endif |
| 7628 | #ifndef PRODUCT |
| 7629 | void shrL_mem_1Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 7630 | // Start at oper_input_base() and count operands |
| 7631 | unsigned idx0 = 2; |
| 7632 | unsigned idx1 = 2; // dst |
| 7633 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 7634 | st->print_raw("shrq "); |
| 7635 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 7636 | st->print_raw(", "); |
| 7637 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 7638 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 7639 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 7640 | st->print(" ! Field: "); |
| 7641 | if (f->is_volatile()) |
| 7642 | st->print("volatile "); |
| 7643 | f->holder()->name()->print_symbol_on(st); |
| 7644 | st->print("."); |
| 7645 | f->name()->print_symbol_on(st); |
| 7646 | if (f->is_constant()) |
| 7647 | st->print(" (constant)"); |
| 7648 | } else { |
| 7649 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 7650 | st->print(" volatile!"); |
| 7651 | } |
| 7652 | } |
| 7653 | #endif |
| 7654 | #ifndef PRODUCT |
| 7655 | void shrL_rReg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 7656 | // Start at oper_input_base() and count operands |
| 7657 | unsigned idx0 = 1; |
| 7658 | unsigned idx1 = 1; // dst |
| 7659 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 7660 | st->print_raw("shrq "); |
| 7661 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 7662 | st->print_raw(", "); |
| 7663 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 7664 | } |
| 7665 | #endif |
| 7666 | #ifndef PRODUCT |
| 7667 | void shrL_mem_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 7668 | // Start at oper_input_base() and count operands |
| 7669 | unsigned idx0 = 2; |
| 7670 | unsigned idx1 = 2; // dst |
| 7671 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 7672 | st->print_raw("shrq "); |
| 7673 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 7674 | st->print_raw(", "); |
| 7675 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 7676 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 7677 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 7678 | st->print(" ! Field: "); |
| 7679 | if (f->is_volatile()) |
| 7680 | st->print("volatile "); |
| 7681 | f->holder()->name()->print_symbol_on(st); |
| 7682 | st->print("."); |
| 7683 | f->name()->print_symbol_on(st); |
| 7684 | if (f->is_constant()) |
| 7685 | st->print(" (constant)"); |
| 7686 | } else { |
| 7687 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 7688 | st->print(" volatile!"); |
| 7689 | } |
| 7690 | } |
| 7691 | #endif |
| 7692 | #ifndef PRODUCT |
| 7693 | void shrL_rReg_CLNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 7694 | // Start at oper_input_base() and count operands |
| 7695 | unsigned idx0 = 1; |
| 7696 | unsigned idx1 = 1; // dst |
| 7697 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 7698 | st->print_raw("shrq "); |
| 7699 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 7700 | st->print_raw(", "); |
| 7701 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 7702 | } |
| 7703 | #endif |
| 7704 | #ifndef PRODUCT |
| 7705 | void shrL_mem_CLNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 7706 | // Start at oper_input_base() and count operands |
| 7707 | unsigned idx0 = 2; |
| 7708 | unsigned idx1 = 2; // dst |
| 7709 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 7710 | st->print_raw("shrq "); |
| 7711 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 7712 | st->print_raw(", "); |
| 7713 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 7714 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 7715 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 7716 | st->print(" ! Field: "); |
| 7717 | if (f->is_volatile()) |
| 7718 | st->print("volatile "); |
| 7719 | f->holder()->name()->print_symbol_on(st); |
| 7720 | st->print("."); |
| 7721 | f->name()->print_symbol_on(st); |
| 7722 | if (f->is_constant()) |
| 7723 | st->print(" (constant)"); |
| 7724 | } else { |
| 7725 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 7726 | st->print(" volatile!"); |
| 7727 | } |
| 7728 | } |
| 7729 | #endif |
| 7730 | #ifndef PRODUCT |
| 7731 | void i2bNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 7732 | // Start at oper_input_base() and count operands |
| 7733 | unsigned idx0 = 1; |
| 7734 | unsigned idx1 = 1; // src |
| 7735 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // twentyfour |
| 7736 | st->print_raw("movsbl "); |
| 7737 | opnd_array(0)->int_format(ra, this, st); // dst |
| 7738 | st->print_raw(", "); |
| 7739 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 7740 | st->print_raw("\t# i2b"); |
| 7741 | } |
| 7742 | #endif |
| 7743 | #ifndef PRODUCT |
| 7744 | void i2sNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 7745 | // Start at oper_input_base() and count operands |
| 7746 | unsigned idx0 = 1; |
| 7747 | unsigned idx1 = 1; // src |
| 7748 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // sixteen |
| 7749 | st->print_raw("movswl "); |
| 7750 | opnd_array(0)->int_format(ra, this, st); // dst |
| 7751 | st->print_raw(", "); |
| 7752 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 7753 | st->print_raw("\t# i2s"); |
| 7754 | } |
| 7755 | #endif |
| 7756 | #ifndef PRODUCT |
| 7757 | void rolI_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 7758 | // Start at oper_input_base() and count operands |
| 7759 | unsigned idx0 = 1; |
| 7760 | unsigned idx1 = 1; // dst |
| 7761 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 7762 | st->print_raw("roll "); |
| 7763 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 7764 | st->print_raw(", "); |
| 7765 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 7766 | } |
| 7767 | #endif |
| 7768 | #ifndef PRODUCT |
| 7769 | void rolI_rReg_VarNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 7770 | // Start at oper_input_base() and count operands |
| 7771 | unsigned idx0 = 1; |
| 7772 | unsigned idx1 = 1; // dst |
| 7773 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 7774 | st->print_raw("roll "); |
| 7775 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 7776 | st->print_raw(", "); |
| 7777 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 7778 | } |
| 7779 | #endif |
| 7780 | #ifndef PRODUCT |
| 7781 | void rorI_immI8_legacyNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 7782 | // Start at oper_input_base() and count operands |
| 7783 | unsigned idx0 = 1; |
| 7784 | unsigned idx1 = 1; // dst |
| 7785 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 7786 | st->print_raw("rorl "); |
| 7787 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 7788 | st->print_raw(", "); |
| 7789 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 7790 | } |
| 7791 | #endif |
| 7792 | #ifndef PRODUCT |
| 7793 | void rorI_immI8Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 7794 | // Start at oper_input_base() and count operands |
| 7795 | unsigned idx0 = 1; |
| 7796 | unsigned idx1 = 1; // dst |
| 7797 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 7798 | st->print_raw("rorxd "); |
| 7799 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 7800 | st->print_raw(", "); |
| 7801 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 7802 | } |
| 7803 | #endif |
| 7804 | #ifndef PRODUCT |
| 7805 | void rorI_rReg_VarNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 7806 | // Start at oper_input_base() and count operands |
| 7807 | unsigned idx0 = 1; |
| 7808 | unsigned idx1 = 1; // dst |
| 7809 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 7810 | st->print_raw("rorl "); |
| 7811 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 7812 | st->print_raw(", "); |
| 7813 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 7814 | } |
| 7815 | #endif |
| 7816 | #ifndef PRODUCT |
| 7817 | void rolL_immI8Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 7818 | // Start at oper_input_base() and count operands |
| 7819 | unsigned idx0 = 1; |
| 7820 | unsigned idx1 = 1; // dst |
| 7821 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 7822 | st->print_raw("rolq "); |
| 7823 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 7824 | st->print_raw(", "); |
| 7825 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 7826 | } |
| 7827 | #endif |
| 7828 | #ifndef PRODUCT |
| 7829 | void rolL_rReg_VarNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 7830 | // Start at oper_input_base() and count operands |
| 7831 | unsigned idx0 = 1; |
| 7832 | unsigned idx1 = 1; // dst |
| 7833 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 7834 | st->print_raw("rolq "); |
| 7835 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 7836 | st->print_raw(", "); |
| 7837 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 7838 | } |
| 7839 | #endif |
| 7840 | #ifndef PRODUCT |
| 7841 | void rorL_immI8_legacyNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 7842 | // Start at oper_input_base() and count operands |
| 7843 | unsigned idx0 = 1; |
| 7844 | unsigned idx1 = 1; // dst |
| 7845 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 7846 | st->print_raw("rorq "); |
| 7847 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 7848 | st->print_raw(", "); |
| 7849 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 7850 | } |
| 7851 | #endif |
| 7852 | #ifndef PRODUCT |
| 7853 | void rorL_immI8Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 7854 | // Start at oper_input_base() and count operands |
| 7855 | unsigned idx0 = 1; |
| 7856 | unsigned idx1 = 1; // dst |
| 7857 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 7858 | st->print_raw("rorxq "); |
| 7859 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 7860 | st->print_raw(", "); |
| 7861 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 7862 | } |
| 7863 | #endif |
| 7864 | #ifndef PRODUCT |
| 7865 | void rorL_rReg_VarNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 7866 | // Start at oper_input_base() and count operands |
| 7867 | unsigned idx0 = 1; |
| 7868 | unsigned idx1 = 1; // dst |
| 7869 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 7870 | st->print_raw("rorq "); |
| 7871 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 7872 | st->print_raw(", "); |
| 7873 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 7874 | } |
| 7875 | #endif |
| 7876 | #ifndef PRODUCT |
| 7877 | void andI_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 7878 | // Start at oper_input_base() and count operands |
| 7879 | unsigned idx0 = 1; |
| 7880 | unsigned idx1 = 1; // dst |
| 7881 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 7882 | st->print_raw("andl "); |
| 7883 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 7884 | st->print_raw(", "); |
| 7885 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 7886 | st->print_raw("\t# int"); |
| 7887 | } |
| 7888 | #endif |
| 7889 | #ifndef PRODUCT |
| 7890 | void andI_rReg_imm255Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 7891 | // Start at oper_input_base() and count operands |
| 7892 | unsigned idx0 = 1; |
| 7893 | unsigned idx1 = 1; // dst |
| 7894 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 7895 | st->print_raw("movzbl "); |
| 7896 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 7897 | st->print_raw(", "); |
| 7898 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 7899 | st->print_raw("\t# int & 0xFF"); |
| 7900 | } |
| 7901 | #endif |
| 7902 | #ifndef PRODUCT |
| 7903 | void andI2L_rReg_imm255Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 7904 | // Start at oper_input_base() and count operands |
| 7905 | unsigned idx0 = 1; |
| 7906 | unsigned idx1 = 1; // src |
| 7907 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask |
| 7908 | st->print_raw("movzbl "); |
| 7909 | opnd_array(0)->int_format(ra, this, st); // dst |
| 7910 | st->print_raw(", "); |
| 7911 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 7912 | st->print_raw("\t# int & 0xFF -> long"); |
| 7913 | } |
| 7914 | #endif |
| 7915 | #ifndef PRODUCT |
| 7916 | void andI_rReg_imm65535Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 7917 | // Start at oper_input_base() and count operands |
| 7918 | unsigned idx0 = 1; |
| 7919 | unsigned idx1 = 1; // dst |
| 7920 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 7921 | st->print_raw("movzwl "); |
| 7922 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 7923 | st->print_raw(", "); |
| 7924 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 7925 | st->print_raw("\t# int & 0xFFFF"); |
| 7926 | } |
| 7927 | #endif |
| 7928 | #ifndef PRODUCT |
| 7929 | void andI2L_rReg_imm65535Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 7930 | // Start at oper_input_base() and count operands |
| 7931 | unsigned idx0 = 1; |
| 7932 | unsigned idx1 = 1; // src |
| 7933 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask |
| 7934 | st->print_raw("movzwl "); |
| 7935 | opnd_array(0)->int_format(ra, this, st); // dst |
| 7936 | st->print_raw(", "); |
| 7937 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 7938 | st->print_raw("\t# int & 0xFFFF -> long"); |
| 7939 | } |
| 7940 | #endif |
| 7941 | #ifndef PRODUCT |
| 7942 | void convI2LAndI_reg_immIbitmaskNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 7943 | // Start at oper_input_base() and count operands |
| 7944 | unsigned idx0 = 1; |
| 7945 | unsigned idx1 = 1; // src |
| 7946 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask |
| 7947 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp |
| 7948 | st->print_raw("bzhiq "); |
| 7949 | opnd_array(0)->int_format(ra, this, st); // dst |
| 7950 | st->print_raw(", "); |
| 7951 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 7952 | st->print_raw(", "); |
| 7953 | opnd_array(2)->ext_format(ra, this,idx2, st); // mask |
| 7954 | st->print_raw(" \t# using "); |
| 7955 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp |
| 7956 | st->print_raw(" as TEMP, int & immI_Pow2M1 -> long"); |
| 7957 | } |
| 7958 | #endif |
| 7959 | #ifndef PRODUCT |
| 7960 | void andI_rReg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 7961 | // Start at oper_input_base() and count operands |
| 7962 | unsigned idx0 = 1; |
| 7963 | unsigned idx1 = 1; // dst |
| 7964 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 7965 | st->print_raw("andl "); |
| 7966 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 7967 | st->print_raw(", "); |
| 7968 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 7969 | st->print_raw("\t# int"); |
| 7970 | } |
| 7971 | #endif |
| 7972 | #ifndef PRODUCT |
| 7973 | void andI_rReg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 7974 | // Start at oper_input_base() and count operands |
| 7975 | unsigned idx0 = 2; |
| 7976 | unsigned idx1 = 2; // dst |
| 7977 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 7978 | st->print_raw("andl "); |
| 7979 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 7980 | st->print_raw(", "); |
| 7981 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 7982 | st->print_raw("\t# int"); |
| 7983 | } |
| 7984 | #endif |
| 7985 | #ifndef PRODUCT |
| 7986 | void andI_rReg_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 7987 | // Start at oper_input_base() and count operands |
| 7988 | unsigned idx0 = 2; |
| 7989 | unsigned idx1 = 2; // src |
| 7990 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst |
| 7991 | st->print_raw("andl "); |
| 7992 | opnd_array(2)->ext_format(ra, this,idx2, st); // dst |
| 7993 | st->print_raw(", "); |
| 7994 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 7995 | st->print_raw("\t# int"); |
| 7996 | } |
| 7997 | #endif |
| 7998 | #ifndef PRODUCT |
| 7999 | void andB_mem_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 8000 | // Start at oper_input_base() and count operands |
| 8001 | unsigned idx0 = 2; |
| 8002 | unsigned idx1 = 2; // dst |
| 8003 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 8004 | st->print_raw("andb "); |
| 8005 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 8006 | st->print_raw(", "); |
| 8007 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 8008 | st->print_raw("\t# byte"); |
| 8009 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 8010 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 8011 | st->print(" ! Field: "); |
| 8012 | if (f->is_volatile()) |
| 8013 | st->print("volatile "); |
| 8014 | f->holder()->name()->print_symbol_on(st); |
| 8015 | st->print("."); |
| 8016 | f->name()->print_symbol_on(st); |
| 8017 | if (f->is_constant()) |
| 8018 | st->print(" (constant)"); |
| 8019 | } else { |
| 8020 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 8021 | st->print(" volatile!"); |
| 8022 | } |
| 8023 | } |
| 8024 | #endif |
| 8025 | #ifndef PRODUCT |
| 8026 | void andB_mem_rReg_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 8027 | // Start at oper_input_base() and count operands |
| 8028 | unsigned idx0 = 2; |
| 8029 | unsigned idx1 = 2; // dst |
| 8030 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 8031 | st->print_raw("andb "); |
| 8032 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 8033 | st->print_raw(", "); |
| 8034 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 8035 | st->print_raw("\t# byte"); |
| 8036 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 8037 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 8038 | st->print(" ! Field: "); |
| 8039 | if (f->is_volatile()) |
| 8040 | st->print("volatile "); |
| 8041 | f->holder()->name()->print_symbol_on(st); |
| 8042 | st->print("."); |
| 8043 | f->name()->print_symbol_on(st); |
| 8044 | if (f->is_constant()) |
| 8045 | st->print(" (constant)"); |
| 8046 | } else { |
| 8047 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 8048 | st->print(" volatile!"); |
| 8049 | } |
| 8050 | } |
| 8051 | #endif |
| 8052 | #ifndef PRODUCT |
| 8053 | void andI_mem_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 8054 | // Start at oper_input_base() and count operands |
| 8055 | unsigned idx0 = 2; |
| 8056 | unsigned idx1 = 2; // dst |
| 8057 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 8058 | st->print_raw("andl "); |
| 8059 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 8060 | st->print_raw(", "); |
| 8061 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 8062 | st->print_raw("\t# int"); |
| 8063 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 8064 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 8065 | st->print(" ! Field: "); |
| 8066 | if (f->is_volatile()) |
| 8067 | st->print("volatile "); |
| 8068 | f->holder()->name()->print_symbol_on(st); |
| 8069 | st->print("."); |
| 8070 | f->name()->print_symbol_on(st); |
| 8071 | if (f->is_constant()) |
| 8072 | st->print(" (constant)"); |
| 8073 | } else { |
| 8074 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 8075 | st->print(" volatile!"); |
| 8076 | } |
| 8077 | } |
| 8078 | #endif |
| 8079 | #ifndef PRODUCT |
| 8080 | void andI_mem_rReg_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 8081 | // Start at oper_input_base() and count operands |
| 8082 | unsigned idx0 = 2; |
| 8083 | unsigned idx1 = 2; // dst |
| 8084 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 8085 | st->print_raw("andl "); |
| 8086 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 8087 | st->print_raw(", "); |
| 8088 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 8089 | st->print_raw("\t# int"); |
| 8090 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 8091 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 8092 | st->print(" ! Field: "); |
| 8093 | if (f->is_volatile()) |
| 8094 | st->print("volatile "); |
| 8095 | f->holder()->name()->print_symbol_on(st); |
| 8096 | st->print("."); |
| 8097 | f->name()->print_symbol_on(st); |
| 8098 | if (f->is_constant()) |
| 8099 | st->print(" (constant)"); |
| 8100 | } else { |
| 8101 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 8102 | st->print(" volatile!"); |
| 8103 | } |
| 8104 | } |
| 8105 | #endif |
| 8106 | #ifndef PRODUCT |
| 8107 | void andI_mem_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 8108 | // Start at oper_input_base() and count operands |
| 8109 | unsigned idx0 = 2; |
| 8110 | unsigned idx1 = 2; // dst |
| 8111 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 8112 | st->print_raw("andl "); |
| 8113 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 8114 | st->print_raw(", "); |
| 8115 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 8116 | st->print_raw("\t# int"); |
| 8117 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 8118 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 8119 | st->print(" ! Field: "); |
| 8120 | if (f->is_volatile()) |
| 8121 | st->print("volatile "); |
| 8122 | f->holder()->name()->print_symbol_on(st); |
| 8123 | st->print("."); |
| 8124 | f->name()->print_symbol_on(st); |
| 8125 | if (f->is_constant()) |
| 8126 | st->print(" (constant)"); |
| 8127 | } else { |
| 8128 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 8129 | st->print(" volatile!"); |
| 8130 | } |
| 8131 | } |
| 8132 | #endif |
| 8133 | #ifndef PRODUCT |
| 8134 | void andnI_rReg_rReg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 8135 | // Start at oper_input_base() and count operands |
| 8136 | unsigned idx0 = 2; |
| 8137 | unsigned idx1 = 2; // src1 |
| 8138 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1 |
| 8139 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // src2 |
| 8140 | st->print_raw("andnl "); |
| 8141 | opnd_array(0)->int_format(ra, this, st); // dst |
| 8142 | st->print_raw(", "); |
| 8143 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 8144 | st->print_raw(", "); |
| 8145 | opnd_array(3)->ext_format(ra, this,idx3, st); // src2 |
| 8146 | } |
| 8147 | #endif |
| 8148 | #ifndef PRODUCT |
| 8149 | void andnI_rReg_rReg_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 8150 | // Start at oper_input_base() and count operands |
| 8151 | unsigned idx0 = 2; |
| 8152 | unsigned idx1 = 2; // src2 |
| 8153 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src1 |
| 8154 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // minus_1 |
| 8155 | st->print_raw("andnl "); |
| 8156 | opnd_array(0)->int_format(ra, this, st); // dst |
| 8157 | st->print_raw(", "); |
| 8158 | opnd_array(2)->ext_format(ra, this,idx2, st); // src1 |
| 8159 | st->print_raw(", "); |
| 8160 | opnd_array(1)->ext_format(ra, this,idx1, st); // src2 |
| 8161 | } |
| 8162 | #endif |
| 8163 | #ifndef PRODUCT |
| 8164 | void andnI_rReg_rReg_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 8165 | // Start at oper_input_base() and count operands |
| 8166 | unsigned idx0 = 1; |
| 8167 | unsigned idx1 = 1; // src1 |
| 8168 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1 |
| 8169 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // src2 |
| 8170 | st->print_raw("andnl "); |
| 8171 | opnd_array(0)->int_format(ra, this, st); // dst |
| 8172 | st->print_raw(", "); |
| 8173 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 8174 | st->print_raw(", "); |
| 8175 | opnd_array(3)->ext_format(ra, this,idx3, st); // src2 |
| 8176 | } |
| 8177 | #endif |
| 8178 | #ifndef PRODUCT |
| 8179 | void andnI_rReg_rReg_rReg_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 8180 | // Start at oper_input_base() and count operands |
| 8181 | unsigned idx0 = 1; |
| 8182 | unsigned idx1 = 1; // src2 |
| 8183 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src1 |
| 8184 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // minus_1 |
| 8185 | st->print_raw("andnl "); |
| 8186 | opnd_array(0)->int_format(ra, this, st); // dst |
| 8187 | st->print_raw(", "); |
| 8188 | opnd_array(2)->ext_format(ra, this,idx2, st); // src1 |
| 8189 | st->print_raw(", "); |
| 8190 | opnd_array(1)->ext_format(ra, this,idx1, st); // src2 |
| 8191 | } |
| 8192 | #endif |
| 8193 | #ifndef PRODUCT |
| 8194 | void blsiI_rReg_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 8195 | // Start at oper_input_base() and count operands |
| 8196 | unsigned idx0 = 1; |
| 8197 | unsigned idx1 = 1; // imm_zero |
| 8198 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 8199 | st->print_raw("blsil "); |
| 8200 | opnd_array(0)->int_format(ra, this, st); // dst |
| 8201 | st->print_raw(", "); |
| 8202 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 8203 | } |
| 8204 | #endif |
| 8205 | #ifndef PRODUCT |
| 8206 | void blsiI_rReg_rReg_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 8207 | // Start at oper_input_base() and count operands |
| 8208 | unsigned idx0 = 1; |
| 8209 | unsigned idx1 = 1; // src |
| 8210 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // imm_zero |
| 8211 | st->print_raw("blsil "); |
| 8212 | opnd_array(0)->int_format(ra, this, st); // dst |
| 8213 | st->print_raw(", "); |
| 8214 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 8215 | } |
| 8216 | #endif |
| 8217 | #ifndef PRODUCT |
| 8218 | void blsiI_rReg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 8219 | // Start at oper_input_base() and count operands |
| 8220 | unsigned idx0 = 2; |
| 8221 | unsigned idx1 = 2; // imm_zero |
| 8222 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 8223 | st->print_raw("blsil "); |
| 8224 | opnd_array(0)->int_format(ra, this, st); // dst |
| 8225 | st->print_raw(", "); |
| 8226 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 8227 | } |
| 8228 | #endif |
| 8229 | #ifndef PRODUCT |
| 8230 | void blsiI_rReg_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 8231 | // Start at oper_input_base() and count operands |
| 8232 | unsigned idx0 = 2; |
| 8233 | unsigned idx1 = 2; // src |
| 8234 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // imm_zero |
| 8235 | st->print_raw("blsil "); |
| 8236 | opnd_array(0)->int_format(ra, this, st); // dst |
| 8237 | st->print_raw(", "); |
| 8238 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 8239 | } |
| 8240 | #endif |
| 8241 | #ifndef PRODUCT |
| 8242 | void blsmskI_rReg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 8243 | // Start at oper_input_base() and count operands |
| 8244 | unsigned idx0 = 2; |
| 8245 | unsigned idx1 = 2; // src |
| 8246 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1 |
| 8247 | st->print_raw("blsmskl "); |
| 8248 | opnd_array(0)->int_format(ra, this, st); // dst |
| 8249 | st->print_raw(", "); |
| 8250 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 8251 | } |
| 8252 | #endif |
| 8253 | #ifndef PRODUCT |
| 8254 | void blsmskI_rReg_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 8255 | // Start at oper_input_base() and count operands |
| 8256 | unsigned idx0 = 2; |
| 8257 | unsigned idx1 = 2; // src |
| 8258 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1 |
| 8259 | st->print_raw("blsmskl "); |
| 8260 | opnd_array(0)->int_format(ra, this, st); // dst |
| 8261 | st->print_raw(", "); |
| 8262 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 8263 | } |
| 8264 | #endif |
| 8265 | #ifndef PRODUCT |
| 8266 | void blsmskI_rReg_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 8267 | // Start at oper_input_base() and count operands |
| 8268 | unsigned idx0 = 1; |
| 8269 | unsigned idx1 = 1; // src |
| 8270 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1 |
| 8271 | st->print_raw("blsmskl "); |
| 8272 | opnd_array(0)->int_format(ra, this, st); // dst |
| 8273 | st->print_raw(", "); |
| 8274 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 8275 | } |
| 8276 | #endif |
| 8277 | #ifndef PRODUCT |
| 8278 | void blsmskI_rReg_rReg_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 8279 | // Start at oper_input_base() and count operands |
| 8280 | unsigned idx0 = 1; |
| 8281 | unsigned idx1 = 1; // src |
| 8282 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1 |
| 8283 | st->print_raw("blsmskl "); |
| 8284 | opnd_array(0)->int_format(ra, this, st); // dst |
| 8285 | st->print_raw(", "); |
| 8286 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 8287 | } |
| 8288 | #endif |
| 8289 | #ifndef PRODUCT |
| 8290 | void blsrI_rReg_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 8291 | // Start at oper_input_base() and count operands |
| 8292 | unsigned idx0 = 1; |
| 8293 | unsigned idx1 = 1; // src |
| 8294 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1 |
| 8295 | st->print_raw("blsrl "); |
| 8296 | opnd_array(0)->int_format(ra, this, st); // dst |
| 8297 | st->print_raw(", "); |
| 8298 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 8299 | } |
| 8300 | #endif |
| 8301 | #ifndef PRODUCT |
| 8302 | void blsrI_rReg_rReg_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 8303 | // Start at oper_input_base() and count operands |
| 8304 | unsigned idx0 = 1; |
| 8305 | unsigned idx1 = 1; // src |
| 8306 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1 |
| 8307 | st->print_raw("blsrl "); |
| 8308 | opnd_array(0)->int_format(ra, this, st); // dst |
| 8309 | st->print_raw(", "); |
| 8310 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 8311 | } |
| 8312 | #endif |
| 8313 | #ifndef PRODUCT |
| 8314 | void blsrI_rReg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 8315 | // Start at oper_input_base() and count operands |
| 8316 | unsigned idx0 = 2; |
| 8317 | unsigned idx1 = 2; // src |
| 8318 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1 |
| 8319 | st->print_raw("blsrl "); |
| 8320 | opnd_array(0)->int_format(ra, this, st); // dst |
| 8321 | st->print_raw(", "); |
| 8322 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 8323 | } |
| 8324 | #endif |
| 8325 | #ifndef PRODUCT |
| 8326 | void blsrI_rReg_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 8327 | // Start at oper_input_base() and count operands |
| 8328 | unsigned idx0 = 2; |
| 8329 | unsigned idx1 = 2; // src |
| 8330 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1 |
| 8331 | st->print_raw("blsrl "); |
| 8332 | opnd_array(0)->int_format(ra, this, st); // dst |
| 8333 | st->print_raw(", "); |
| 8334 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 8335 | } |
| 8336 | #endif |
| 8337 | #ifndef PRODUCT |
| 8338 | void orI_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 8339 | // Start at oper_input_base() and count operands |
| 8340 | unsigned idx0 = 1; |
| 8341 | unsigned idx1 = 1; // dst |
| 8342 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 8343 | st->print_raw("orl "); |
| 8344 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 8345 | st->print_raw(", "); |
| 8346 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 8347 | st->print_raw("\t# int"); |
| 8348 | } |
| 8349 | #endif |
| 8350 | #ifndef PRODUCT |
| 8351 | void orI_rReg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 8352 | // Start at oper_input_base() and count operands |
| 8353 | unsigned idx0 = 1; |
| 8354 | unsigned idx1 = 1; // dst |
| 8355 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 8356 | st->print_raw("orl "); |
| 8357 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 8358 | st->print_raw(", "); |
| 8359 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 8360 | st->print_raw("\t# int"); |
| 8361 | } |
| 8362 | #endif |
| 8363 | #ifndef PRODUCT |
| 8364 | void orI_rReg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 8365 | // Start at oper_input_base() and count operands |
| 8366 | unsigned idx0 = 2; |
| 8367 | unsigned idx1 = 2; // dst |
| 8368 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 8369 | st->print_raw("orl "); |
| 8370 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 8371 | st->print_raw(", "); |
| 8372 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 8373 | st->print_raw("\t# int"); |
| 8374 | } |
| 8375 | #endif |
| 8376 | #ifndef PRODUCT |
| 8377 | void orI_rReg_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 8378 | // Start at oper_input_base() and count operands |
| 8379 | unsigned idx0 = 2; |
| 8380 | unsigned idx1 = 2; // src |
| 8381 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst |
| 8382 | st->print_raw("orl "); |
| 8383 | opnd_array(2)->ext_format(ra, this,idx2, st); // dst |
| 8384 | st->print_raw(", "); |
| 8385 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 8386 | st->print_raw("\t# int"); |
| 8387 | } |
| 8388 | #endif |
| 8389 | #ifndef PRODUCT |
| 8390 | void orB_mem_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 8391 | // Start at oper_input_base() and count operands |
| 8392 | unsigned idx0 = 2; |
| 8393 | unsigned idx1 = 2; // dst |
| 8394 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 8395 | st->print_raw("orb "); |
| 8396 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 8397 | st->print_raw(", "); |
| 8398 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 8399 | st->print_raw("\t# byte"); |
| 8400 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 8401 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 8402 | st->print(" ! Field: "); |
| 8403 | if (f->is_volatile()) |
| 8404 | st->print("volatile "); |
| 8405 | f->holder()->name()->print_symbol_on(st); |
| 8406 | st->print("."); |
| 8407 | f->name()->print_symbol_on(st); |
| 8408 | if (f->is_constant()) |
| 8409 | st->print(" (constant)"); |
| 8410 | } else { |
| 8411 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 8412 | st->print(" volatile!"); |
| 8413 | } |
| 8414 | } |
| 8415 | #endif |
| 8416 | #ifndef PRODUCT |
| 8417 | void orB_mem_rReg_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 8418 | // Start at oper_input_base() and count operands |
| 8419 | unsigned idx0 = 2; |
| 8420 | unsigned idx1 = 2; // dst |
| 8421 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 8422 | st->print_raw("orb "); |
| 8423 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 8424 | st->print_raw(", "); |
| 8425 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 8426 | st->print_raw("\t# byte"); |
| 8427 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 8428 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 8429 | st->print(" ! Field: "); |
| 8430 | if (f->is_volatile()) |
| 8431 | st->print("volatile "); |
| 8432 | f->holder()->name()->print_symbol_on(st); |
| 8433 | st->print("."); |
| 8434 | f->name()->print_symbol_on(st); |
| 8435 | if (f->is_constant()) |
| 8436 | st->print(" (constant)"); |
| 8437 | } else { |
| 8438 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 8439 | st->print(" volatile!"); |
| 8440 | } |
| 8441 | } |
| 8442 | #endif |
| 8443 | #ifndef PRODUCT |
| 8444 | void orI_mem_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 8445 | // Start at oper_input_base() and count operands |
| 8446 | unsigned idx0 = 2; |
| 8447 | unsigned idx1 = 2; // dst |
| 8448 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 8449 | st->print_raw("orl "); |
| 8450 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 8451 | st->print_raw(", "); |
| 8452 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 8453 | st->print_raw("\t# int"); |
| 8454 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 8455 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 8456 | st->print(" ! Field: "); |
| 8457 | if (f->is_volatile()) |
| 8458 | st->print("volatile "); |
| 8459 | f->holder()->name()->print_symbol_on(st); |
| 8460 | st->print("."); |
| 8461 | f->name()->print_symbol_on(st); |
| 8462 | if (f->is_constant()) |
| 8463 | st->print(" (constant)"); |
| 8464 | } else { |
| 8465 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 8466 | st->print(" volatile!"); |
| 8467 | } |
| 8468 | } |
| 8469 | #endif |
| 8470 | #ifndef PRODUCT |
| 8471 | void orI_mem_rReg_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 8472 | // Start at oper_input_base() and count operands |
| 8473 | unsigned idx0 = 2; |
| 8474 | unsigned idx1 = 2; // dst |
| 8475 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 8476 | st->print_raw("orl "); |
| 8477 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 8478 | st->print_raw(", "); |
| 8479 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 8480 | st->print_raw("\t# int"); |
| 8481 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 8482 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 8483 | st->print(" ! Field: "); |
| 8484 | if (f->is_volatile()) |
| 8485 | st->print("volatile "); |
| 8486 | f->holder()->name()->print_symbol_on(st); |
| 8487 | st->print("."); |
| 8488 | f->name()->print_symbol_on(st); |
| 8489 | if (f->is_constant()) |
| 8490 | st->print(" (constant)"); |
| 8491 | } else { |
| 8492 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 8493 | st->print(" volatile!"); |
| 8494 | } |
| 8495 | } |
| 8496 | #endif |
| 8497 | #ifndef PRODUCT |
| 8498 | void orI_mem_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 8499 | // Start at oper_input_base() and count operands |
| 8500 | unsigned idx0 = 2; |
| 8501 | unsigned idx1 = 2; // dst |
| 8502 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 8503 | st->print_raw("orl "); |
| 8504 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 8505 | st->print_raw(", "); |
| 8506 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 8507 | st->print_raw("\t# int"); |
| 8508 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 8509 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 8510 | st->print(" ! Field: "); |
| 8511 | if (f->is_volatile()) |
| 8512 | st->print("volatile "); |
| 8513 | f->holder()->name()->print_symbol_on(st); |
| 8514 | st->print("."); |
| 8515 | f->name()->print_symbol_on(st); |
| 8516 | if (f->is_constant()) |
| 8517 | st->print(" (constant)"); |
| 8518 | } else { |
| 8519 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 8520 | st->print(" volatile!"); |
| 8521 | } |
| 8522 | } |
| 8523 | #endif |
| 8524 | #ifndef PRODUCT |
| 8525 | void xorI_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 8526 | // Start at oper_input_base() and count operands |
| 8527 | unsigned idx0 = 1; |
| 8528 | unsigned idx1 = 1; // dst |
| 8529 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 8530 | st->print_raw("xorl "); |
| 8531 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 8532 | st->print_raw(", "); |
| 8533 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 8534 | st->print_raw("\t# int"); |
| 8535 | } |
| 8536 | #endif |
| 8537 | #ifndef PRODUCT |
| 8538 | void xorI_rReg_im1Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 8539 | // Start at oper_input_base() and count operands |
| 8540 | unsigned idx0 = 1; |
| 8541 | unsigned idx1 = 1; // dst |
| 8542 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // imm |
| 8543 | st->print_raw("not "); |
| 8544 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 8545 | } |
| 8546 | #endif |
| 8547 | #ifndef PRODUCT |
| 8548 | void xorI_rReg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 8549 | // Start at oper_input_base() and count operands |
| 8550 | unsigned idx0 = 1; |
| 8551 | unsigned idx1 = 1; // dst |
| 8552 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 8553 | st->print_raw("xorl "); |
| 8554 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 8555 | st->print_raw(", "); |
| 8556 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 8557 | st->print_raw("\t# int"); |
| 8558 | } |
| 8559 | #endif |
| 8560 | #ifndef PRODUCT |
| 8561 | void xorI_rReg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 8562 | // Start at oper_input_base() and count operands |
| 8563 | unsigned idx0 = 2; |
| 8564 | unsigned idx1 = 2; // dst |
| 8565 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 8566 | st->print_raw("xorl "); |
| 8567 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 8568 | st->print_raw(", "); |
| 8569 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 8570 | st->print_raw("\t# int"); |
| 8571 | } |
| 8572 | #endif |
| 8573 | #ifndef PRODUCT |
| 8574 | void xorI_rReg_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 8575 | // Start at oper_input_base() and count operands |
| 8576 | unsigned idx0 = 2; |
| 8577 | unsigned idx1 = 2; // src |
| 8578 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst |
| 8579 | st->print_raw("xorl "); |
| 8580 | opnd_array(2)->ext_format(ra, this,idx2, st); // dst |
| 8581 | st->print_raw(", "); |
| 8582 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 8583 | st->print_raw("\t# int"); |
| 8584 | } |
| 8585 | #endif |
| 8586 | #ifndef PRODUCT |
| 8587 | void xorB_mem_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 8588 | // Start at oper_input_base() and count operands |
| 8589 | unsigned idx0 = 2; |
| 8590 | unsigned idx1 = 2; // dst |
| 8591 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 8592 | st->print_raw("xorb "); |
| 8593 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 8594 | st->print_raw(", "); |
| 8595 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 8596 | st->print_raw("\t# byte"); |
| 8597 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 8598 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 8599 | st->print(" ! Field: "); |
| 8600 | if (f->is_volatile()) |
| 8601 | st->print("volatile "); |
| 8602 | f->holder()->name()->print_symbol_on(st); |
| 8603 | st->print("."); |
| 8604 | f->name()->print_symbol_on(st); |
| 8605 | if (f->is_constant()) |
| 8606 | st->print(" (constant)"); |
| 8607 | } else { |
| 8608 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 8609 | st->print(" volatile!"); |
| 8610 | } |
| 8611 | } |
| 8612 | #endif |
| 8613 | #ifndef PRODUCT |
| 8614 | void xorB_mem_rReg_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 8615 | // Start at oper_input_base() and count operands |
| 8616 | unsigned idx0 = 2; |
| 8617 | unsigned idx1 = 2; // dst |
| 8618 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 8619 | st->print_raw("xorb "); |
| 8620 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 8621 | st->print_raw(", "); |
| 8622 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 8623 | st->print_raw("\t# byte"); |
| 8624 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 8625 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 8626 | st->print(" ! Field: "); |
| 8627 | if (f->is_volatile()) |
| 8628 | st->print("volatile "); |
| 8629 | f->holder()->name()->print_symbol_on(st); |
| 8630 | st->print("."); |
| 8631 | f->name()->print_symbol_on(st); |
| 8632 | if (f->is_constant()) |
| 8633 | st->print(" (constant)"); |
| 8634 | } else { |
| 8635 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 8636 | st->print(" volatile!"); |
| 8637 | } |
| 8638 | } |
| 8639 | #endif |
| 8640 | #ifndef PRODUCT |
| 8641 | void xorI_mem_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 8642 | // Start at oper_input_base() and count operands |
| 8643 | unsigned idx0 = 2; |
| 8644 | unsigned idx1 = 2; // dst |
| 8645 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 8646 | st->print_raw("xorl "); |
| 8647 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 8648 | st->print_raw(", "); |
| 8649 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 8650 | st->print_raw("\t# int"); |
| 8651 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 8652 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 8653 | st->print(" ! Field: "); |
| 8654 | if (f->is_volatile()) |
| 8655 | st->print("volatile "); |
| 8656 | f->holder()->name()->print_symbol_on(st); |
| 8657 | st->print("."); |
| 8658 | f->name()->print_symbol_on(st); |
| 8659 | if (f->is_constant()) |
| 8660 | st->print(" (constant)"); |
| 8661 | } else { |
| 8662 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 8663 | st->print(" volatile!"); |
| 8664 | } |
| 8665 | } |
| 8666 | #endif |
| 8667 | #ifndef PRODUCT |
| 8668 | void xorI_mem_rReg_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 8669 | // Start at oper_input_base() and count operands |
| 8670 | unsigned idx0 = 2; |
| 8671 | unsigned idx1 = 2; // dst |
| 8672 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 8673 | st->print_raw("xorl "); |
| 8674 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 8675 | st->print_raw(", "); |
| 8676 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 8677 | st->print_raw("\t# int"); |
| 8678 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 8679 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 8680 | st->print(" ! Field: "); |
| 8681 | if (f->is_volatile()) |
| 8682 | st->print("volatile "); |
| 8683 | f->holder()->name()->print_symbol_on(st); |
| 8684 | st->print("."); |
| 8685 | f->name()->print_symbol_on(st); |
| 8686 | if (f->is_constant()) |
| 8687 | st->print(" (constant)"); |
| 8688 | } else { |
| 8689 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 8690 | st->print(" volatile!"); |
| 8691 | } |
| 8692 | } |
| 8693 | #endif |
| 8694 | #ifndef PRODUCT |
| 8695 | void xorI_mem_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 8696 | // Start at oper_input_base() and count operands |
| 8697 | unsigned idx0 = 2; |
| 8698 | unsigned idx1 = 2; // dst |
| 8699 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 8700 | st->print_raw("xorl "); |
| 8701 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 8702 | st->print_raw(", "); |
| 8703 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 8704 | st->print_raw("\t# int"); |
| 8705 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 8706 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 8707 | st->print(" ! Field: "); |
| 8708 | if (f->is_volatile()) |
| 8709 | st->print("volatile "); |
| 8710 | f->holder()->name()->print_symbol_on(st); |
| 8711 | st->print("."); |
| 8712 | f->name()->print_symbol_on(st); |
| 8713 | if (f->is_constant()) |
| 8714 | st->print(" (constant)"); |
| 8715 | } else { |
| 8716 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 8717 | st->print(" volatile!"); |
| 8718 | } |
| 8719 | } |
| 8720 | #endif |
| 8721 | #ifndef PRODUCT |
| 8722 | void andL_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 8723 | // Start at oper_input_base() and count operands |
| 8724 | unsigned idx0 = 1; |
| 8725 | unsigned idx1 = 1; // dst |
| 8726 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 8727 | st->print_raw("andq "); |
| 8728 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 8729 | st->print_raw(", "); |
| 8730 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 8731 | st->print_raw("\t# long"); |
| 8732 | } |
| 8733 | #endif |
| 8734 | #ifndef PRODUCT |
| 8735 | void andL_rReg_imm255Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 8736 | // Start at oper_input_base() and count operands |
| 8737 | unsigned idx0 = 1; |
| 8738 | unsigned idx1 = 1; // dst |
| 8739 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 8740 | st->print_raw("movzbq "); |
| 8741 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 8742 | st->print_raw(", "); |
| 8743 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 8744 | st->print_raw("\t# long & 0xFF"); |
| 8745 | } |
| 8746 | #endif |
| 8747 | #ifndef PRODUCT |
| 8748 | void andL_rReg_imm65535Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 8749 | // Start at oper_input_base() and count operands |
| 8750 | unsigned idx0 = 1; |
| 8751 | unsigned idx1 = 1; // dst |
| 8752 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 8753 | st->print_raw("movzwq "); |
| 8754 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 8755 | st->print_raw(", "); |
| 8756 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 8757 | st->print_raw("\t# long & 0xFFFF"); |
| 8758 | } |
| 8759 | #endif |
| 8760 | #ifndef PRODUCT |
| 8761 | void andL_rReg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 8762 | // Start at oper_input_base() and count operands |
| 8763 | unsigned idx0 = 1; |
| 8764 | unsigned idx1 = 1; // dst |
| 8765 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 8766 | st->print_raw("andq "); |
| 8767 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 8768 | st->print_raw(", "); |
| 8769 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 8770 | st->print_raw("\t# long"); |
| 8771 | } |
| 8772 | #endif |
| 8773 | #ifndef PRODUCT |
| 8774 | void andL_rReg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 8775 | // Start at oper_input_base() and count operands |
| 8776 | unsigned idx0 = 2; |
| 8777 | unsigned idx1 = 2; // dst |
| 8778 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 8779 | st->print_raw("andq "); |
| 8780 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 8781 | st->print_raw(", "); |
| 8782 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 8783 | st->print_raw("\t# long"); |
| 8784 | } |
| 8785 | #endif |
| 8786 | #ifndef PRODUCT |
| 8787 | void andL_rReg_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 8788 | // Start at oper_input_base() and count operands |
| 8789 | unsigned idx0 = 2; |
| 8790 | unsigned idx1 = 2; // src |
| 8791 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst |
| 8792 | st->print_raw("andq "); |
| 8793 | opnd_array(2)->ext_format(ra, this,idx2, st); // dst |
| 8794 | st->print_raw(", "); |
| 8795 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 8796 | st->print_raw("\t# long"); |
| 8797 | } |
| 8798 | #endif |
| 8799 | #ifndef PRODUCT |
| 8800 | void andL_mem_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 8801 | // Start at oper_input_base() and count operands |
| 8802 | unsigned idx0 = 2; |
| 8803 | unsigned idx1 = 2; // dst |
| 8804 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 8805 | st->print_raw("andq "); |
| 8806 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 8807 | st->print_raw(", "); |
| 8808 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 8809 | st->print_raw("\t# long"); |
| 8810 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 8811 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 8812 | st->print(" ! Field: "); |
| 8813 | if (f->is_volatile()) |
| 8814 | st->print("volatile "); |
| 8815 | f->holder()->name()->print_symbol_on(st); |
| 8816 | st->print("."); |
| 8817 | f->name()->print_symbol_on(st); |
| 8818 | if (f->is_constant()) |
| 8819 | st->print(" (constant)"); |
| 8820 | } else { |
| 8821 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 8822 | st->print(" volatile!"); |
| 8823 | } |
| 8824 | } |
| 8825 | #endif |
| 8826 | #ifndef PRODUCT |
| 8827 | void andL_mem_rReg_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 8828 | // Start at oper_input_base() and count operands |
| 8829 | unsigned idx0 = 2; |
| 8830 | unsigned idx1 = 2; // dst |
| 8831 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 8832 | st->print_raw("andq "); |
| 8833 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 8834 | st->print_raw(", "); |
| 8835 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 8836 | st->print_raw("\t# long"); |
| 8837 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 8838 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 8839 | st->print(" ! Field: "); |
| 8840 | if (f->is_volatile()) |
| 8841 | st->print("volatile "); |
| 8842 | f->holder()->name()->print_symbol_on(st); |
| 8843 | st->print("."); |
| 8844 | f->name()->print_symbol_on(st); |
| 8845 | if (f->is_constant()) |
| 8846 | st->print(" (constant)"); |
| 8847 | } else { |
| 8848 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 8849 | st->print(" volatile!"); |
| 8850 | } |
| 8851 | } |
| 8852 | #endif |
| 8853 | #ifndef PRODUCT |
| 8854 | void andL_mem_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 8855 | // Start at oper_input_base() and count operands |
| 8856 | unsigned idx0 = 2; |
| 8857 | unsigned idx1 = 2; // dst |
| 8858 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 8859 | st->print_raw("andq "); |
| 8860 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 8861 | st->print_raw(", "); |
| 8862 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 8863 | st->print_raw("\t# long"); |
| 8864 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 8865 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 8866 | st->print(" ! Field: "); |
| 8867 | if (f->is_volatile()) |
| 8868 | st->print("volatile "); |
| 8869 | f->holder()->name()->print_symbol_on(st); |
| 8870 | st->print("."); |
| 8871 | f->name()->print_symbol_on(st); |
| 8872 | if (f->is_constant()) |
| 8873 | st->print(" (constant)"); |
| 8874 | } else { |
| 8875 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 8876 | st->print(" volatile!"); |
| 8877 | } |
| 8878 | } |
| 8879 | #endif |
| 8880 | #ifndef PRODUCT |
| 8881 | void btrL_mem_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 8882 | // Start at oper_input_base() and count operands |
| 8883 | unsigned idx0 = 2; |
| 8884 | unsigned idx1 = 2; // dst |
| 8885 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con |
| 8886 | st->print_raw("btrq "); |
| 8887 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 8888 | st->print_raw(", log2(not("); |
| 8889 | opnd_array(2)->ext_format(ra, this,idx2, st); // con |
| 8890 | st->print_raw("))\t# long"); |
| 8891 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 8892 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 8893 | st->print(" ! Field: "); |
| 8894 | if (f->is_volatile()) |
| 8895 | st->print("volatile "); |
| 8896 | f->holder()->name()->print_symbol_on(st); |
| 8897 | st->print("."); |
| 8898 | f->name()->print_symbol_on(st); |
| 8899 | if (f->is_constant()) |
| 8900 | st->print(" (constant)"); |
| 8901 | } else { |
| 8902 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 8903 | st->print(" volatile!"); |
| 8904 | } |
| 8905 | } |
| 8906 | #endif |
| 8907 | #ifndef PRODUCT |
| 8908 | void andnL_rReg_rReg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 8909 | // Start at oper_input_base() and count operands |
| 8910 | unsigned idx0 = 2; |
| 8911 | unsigned idx1 = 2; // src1 |
| 8912 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1 |
| 8913 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // src2 |
| 8914 | st->print_raw("andnq "); |
| 8915 | opnd_array(0)->int_format(ra, this, st); // dst |
| 8916 | st->print_raw(", "); |
| 8917 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 8918 | st->print_raw(", "); |
| 8919 | opnd_array(3)->ext_format(ra, this,idx3, st); // src2 |
| 8920 | } |
| 8921 | #endif |
| 8922 | #ifndef PRODUCT |
| 8923 | void andnL_rReg_rReg_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 8924 | // Start at oper_input_base() and count operands |
| 8925 | unsigned idx0 = 2; |
| 8926 | unsigned idx1 = 2; // src2 |
| 8927 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src1 |
| 8928 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // minus_1 |
| 8929 | st->print_raw("andnq "); |
| 8930 | opnd_array(0)->int_format(ra, this, st); // dst |
| 8931 | st->print_raw(", "); |
| 8932 | opnd_array(2)->ext_format(ra, this,idx2, st); // src1 |
| 8933 | st->print_raw(", "); |
| 8934 | opnd_array(1)->ext_format(ra, this,idx1, st); // src2 |
| 8935 | } |
| 8936 | #endif |
| 8937 | #ifndef PRODUCT |
| 8938 | void andnL_rReg_rReg_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 8939 | // Start at oper_input_base() and count operands |
| 8940 | unsigned idx0 = 1; |
| 8941 | unsigned idx1 = 1; // src1 |
| 8942 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1 |
| 8943 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // src2 |
| 8944 | st->print_raw("andnq "); |
| 8945 | opnd_array(0)->int_format(ra, this, st); // dst |
| 8946 | st->print_raw(", "); |
| 8947 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 8948 | st->print_raw(", "); |
| 8949 | opnd_array(3)->ext_format(ra, this,idx3, st); // src2 |
| 8950 | } |
| 8951 | #endif |
| 8952 | #ifndef PRODUCT |
| 8953 | void andnL_rReg_rReg_rReg_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 8954 | // Start at oper_input_base() and count operands |
| 8955 | unsigned idx0 = 1; |
| 8956 | unsigned idx1 = 1; // src2 |
| 8957 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src1 |
| 8958 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // minus_1 |
| 8959 | st->print_raw("andnq "); |
| 8960 | opnd_array(0)->int_format(ra, this, st); // dst |
| 8961 | st->print_raw(", "); |
| 8962 | opnd_array(2)->ext_format(ra, this,idx2, st); // src1 |
| 8963 | st->print_raw(", "); |
| 8964 | opnd_array(1)->ext_format(ra, this,idx1, st); // src2 |
| 8965 | } |
| 8966 | #endif |
| 8967 | #ifndef PRODUCT |
| 8968 | void blsiL_rReg_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 8969 | // Start at oper_input_base() and count operands |
| 8970 | unsigned idx0 = 1; |
| 8971 | unsigned idx1 = 1; // imm_zero |
| 8972 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 8973 | st->print_raw("blsiq "); |
| 8974 | opnd_array(0)->int_format(ra, this, st); // dst |
| 8975 | st->print_raw(", "); |
| 8976 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 8977 | } |
| 8978 | #endif |
| 8979 | #ifndef PRODUCT |
| 8980 | void blsiL_rReg_rReg_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 8981 | // Start at oper_input_base() and count operands |
| 8982 | unsigned idx0 = 1; |
| 8983 | unsigned idx1 = 1; // src |
| 8984 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // imm_zero |
| 8985 | st->print_raw("blsiq "); |
| 8986 | opnd_array(0)->int_format(ra, this, st); // dst |
| 8987 | st->print_raw(", "); |
| 8988 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 8989 | } |
| 8990 | #endif |
| 8991 | #ifndef PRODUCT |
| 8992 | void blsiL_rReg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 8993 | // Start at oper_input_base() and count operands |
| 8994 | unsigned idx0 = 2; |
| 8995 | unsigned idx1 = 2; // imm_zero |
| 8996 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 8997 | st->print_raw("blsiq "); |
| 8998 | opnd_array(0)->int_format(ra, this, st); // dst |
| 8999 | st->print_raw(", "); |
| 9000 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 9001 | } |
| 9002 | #endif |
| 9003 | #ifndef PRODUCT |
| 9004 | void blsiL_rReg_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 9005 | // Start at oper_input_base() and count operands |
| 9006 | unsigned idx0 = 2; |
| 9007 | unsigned idx1 = 2; // src |
| 9008 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // imm_zero |
| 9009 | st->print_raw("blsiq "); |
| 9010 | opnd_array(0)->int_format(ra, this, st); // dst |
| 9011 | st->print_raw(", "); |
| 9012 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 9013 | } |
| 9014 | #endif |
| 9015 | #ifndef PRODUCT |
| 9016 | void blsmskL_rReg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 9017 | // Start at oper_input_base() and count operands |
| 9018 | unsigned idx0 = 2; |
| 9019 | unsigned idx1 = 2; // src |
| 9020 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1 |
| 9021 | st->print_raw("blsmskq "); |
| 9022 | opnd_array(0)->int_format(ra, this, st); // dst |
| 9023 | st->print_raw(", "); |
| 9024 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 9025 | } |
| 9026 | #endif |
| 9027 | #ifndef PRODUCT |
| 9028 | void blsmskL_rReg_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 9029 | // Start at oper_input_base() and count operands |
| 9030 | unsigned idx0 = 2; |
| 9031 | unsigned idx1 = 2; // src |
| 9032 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1 |
| 9033 | st->print_raw("blsmskq "); |
| 9034 | opnd_array(0)->int_format(ra, this, st); // dst |
| 9035 | st->print_raw(", "); |
| 9036 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 9037 | } |
| 9038 | #endif |
| 9039 | #ifndef PRODUCT |
| 9040 | void blsmskL_rReg_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 9041 | // Start at oper_input_base() and count operands |
| 9042 | unsigned idx0 = 1; |
| 9043 | unsigned idx1 = 1; // src |
| 9044 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1 |
| 9045 | st->print_raw("blsmskq "); |
| 9046 | opnd_array(0)->int_format(ra, this, st); // dst |
| 9047 | st->print_raw(", "); |
| 9048 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 9049 | } |
| 9050 | #endif |
| 9051 | #ifndef PRODUCT |
| 9052 | void blsmskL_rReg_rReg_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 9053 | // Start at oper_input_base() and count operands |
| 9054 | unsigned idx0 = 1; |
| 9055 | unsigned idx1 = 1; // src |
| 9056 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1 |
| 9057 | st->print_raw("blsmskq "); |
| 9058 | opnd_array(0)->int_format(ra, this, st); // dst |
| 9059 | st->print_raw(", "); |
| 9060 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 9061 | } |
| 9062 | #endif |
| 9063 | #ifndef PRODUCT |
| 9064 | void blsrL_rReg_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 9065 | // Start at oper_input_base() and count operands |
| 9066 | unsigned idx0 = 1; |
| 9067 | unsigned idx1 = 1; // src |
| 9068 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1 |
| 9069 | st->print_raw("blsrq "); |
| 9070 | opnd_array(0)->int_format(ra, this, st); // dst |
| 9071 | st->print_raw(", "); |
| 9072 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 9073 | } |
| 9074 | #endif |
| 9075 | #ifndef PRODUCT |
| 9076 | void blsrL_rReg_rReg_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 9077 | // Start at oper_input_base() and count operands |
| 9078 | unsigned idx0 = 1; |
| 9079 | unsigned idx1 = 1; // src |
| 9080 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1 |
| 9081 | st->print_raw("blsrq "); |
| 9082 | opnd_array(0)->int_format(ra, this, st); // dst |
| 9083 | st->print_raw(", "); |
| 9084 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 9085 | } |
| 9086 | #endif |
| 9087 | #ifndef PRODUCT |
| 9088 | void blsrL_rReg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 9089 | // Start at oper_input_base() and count operands |
| 9090 | unsigned idx0 = 2; |
| 9091 | unsigned idx1 = 2; // src |
| 9092 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1 |
| 9093 | st->print_raw("blsrq "); |
| 9094 | opnd_array(0)->int_format(ra, this, st); // dst |
| 9095 | st->print_raw(", "); |
| 9096 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 9097 | } |
| 9098 | #endif |
| 9099 | #ifndef PRODUCT |
| 9100 | void blsrL_rReg_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 9101 | // Start at oper_input_base() and count operands |
| 9102 | unsigned idx0 = 2; |
| 9103 | unsigned idx1 = 2; // src |
| 9104 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1 |
| 9105 | st->print_raw("blsrq "); |
| 9106 | opnd_array(0)->int_format(ra, this, st); // dst |
| 9107 | st->print_raw(", "); |
| 9108 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 9109 | } |
| 9110 | #endif |
| 9111 | #ifndef PRODUCT |
| 9112 | void orL_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 9113 | // Start at oper_input_base() and count operands |
| 9114 | unsigned idx0 = 1; |
| 9115 | unsigned idx1 = 1; // dst |
| 9116 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 9117 | st->print_raw("orq "); |
| 9118 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 9119 | st->print_raw(", "); |
| 9120 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 9121 | st->print_raw("\t# long"); |
| 9122 | } |
| 9123 | #endif |
| 9124 | #ifndef PRODUCT |
| 9125 | void orL_rReg_castP2XNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 9126 | // Start at oper_input_base() and count operands |
| 9127 | unsigned idx0 = 1; |
| 9128 | unsigned idx1 = 1; // dst |
| 9129 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 9130 | st->print_raw("orq "); |
| 9131 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 9132 | st->print_raw(", "); |
| 9133 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 9134 | st->print_raw("\t# long"); |
| 9135 | } |
| 9136 | #endif |
| 9137 | #ifndef PRODUCT |
| 9138 | void orL_rReg_castP2X_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 9139 | // Start at oper_input_base() and count operands |
| 9140 | unsigned idx0 = 1; |
| 9141 | unsigned idx1 = 1; // src |
| 9142 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst |
| 9143 | st->print_raw("orq "); |
| 9144 | opnd_array(2)->ext_format(ra, this,idx2, st); // dst |
| 9145 | st->print_raw(", "); |
| 9146 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 9147 | st->print_raw("\t# long"); |
| 9148 | } |
| 9149 | #endif |
| 9150 | #ifndef PRODUCT |
| 9151 | void orL_rReg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 9152 | // Start at oper_input_base() and count operands |
| 9153 | unsigned idx0 = 1; |
| 9154 | unsigned idx1 = 1; // dst |
| 9155 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 9156 | st->print_raw("orq "); |
| 9157 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 9158 | st->print_raw(", "); |
| 9159 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 9160 | st->print_raw("\t# long"); |
| 9161 | } |
| 9162 | #endif |
| 9163 | #ifndef PRODUCT |
| 9164 | void orL_rReg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 9165 | // Start at oper_input_base() and count operands |
| 9166 | unsigned idx0 = 2; |
| 9167 | unsigned idx1 = 2; // dst |
| 9168 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 9169 | st->print_raw("orq "); |
| 9170 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 9171 | st->print_raw(", "); |
| 9172 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 9173 | st->print_raw("\t# long"); |
| 9174 | } |
| 9175 | #endif |
| 9176 | #ifndef PRODUCT |
| 9177 | void orL_rReg_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 9178 | // Start at oper_input_base() and count operands |
| 9179 | unsigned idx0 = 2; |
| 9180 | unsigned idx1 = 2; // src |
| 9181 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst |
| 9182 | st->print_raw("orq "); |
| 9183 | opnd_array(2)->ext_format(ra, this,idx2, st); // dst |
| 9184 | st->print_raw(", "); |
| 9185 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 9186 | st->print_raw("\t# long"); |
| 9187 | } |
| 9188 | #endif |
| 9189 | #ifndef PRODUCT |
| 9190 | void orL_mem_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 9191 | // Start at oper_input_base() and count operands |
| 9192 | unsigned idx0 = 2; |
| 9193 | unsigned idx1 = 2; // dst |
| 9194 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 9195 | st->print_raw("orq "); |
| 9196 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 9197 | st->print_raw(", "); |
| 9198 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 9199 | st->print_raw("\t# long"); |
| 9200 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 9201 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 9202 | st->print(" ! Field: "); |
| 9203 | if (f->is_volatile()) |
| 9204 | st->print("volatile "); |
| 9205 | f->holder()->name()->print_symbol_on(st); |
| 9206 | st->print("."); |
| 9207 | f->name()->print_symbol_on(st); |
| 9208 | if (f->is_constant()) |
| 9209 | st->print(" (constant)"); |
| 9210 | } else { |
| 9211 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 9212 | st->print(" volatile!"); |
| 9213 | } |
| 9214 | } |
| 9215 | #endif |
| 9216 | #ifndef PRODUCT |
| 9217 | void orL_mem_rReg_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 9218 | // Start at oper_input_base() and count operands |
| 9219 | unsigned idx0 = 2; |
| 9220 | unsigned idx1 = 2; // dst |
| 9221 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 9222 | st->print_raw("orq "); |
| 9223 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 9224 | st->print_raw(", "); |
| 9225 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 9226 | st->print_raw("\t# long"); |
| 9227 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 9228 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 9229 | st->print(" ! Field: "); |
| 9230 | if (f->is_volatile()) |
| 9231 | st->print("volatile "); |
| 9232 | f->holder()->name()->print_symbol_on(st); |
| 9233 | st->print("."); |
| 9234 | f->name()->print_symbol_on(st); |
| 9235 | if (f->is_constant()) |
| 9236 | st->print(" (constant)"); |
| 9237 | } else { |
| 9238 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 9239 | st->print(" volatile!"); |
| 9240 | } |
| 9241 | } |
| 9242 | #endif |
| 9243 | #ifndef PRODUCT |
| 9244 | void orL_mem_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 9245 | // Start at oper_input_base() and count operands |
| 9246 | unsigned idx0 = 2; |
| 9247 | unsigned idx1 = 2; // dst |
| 9248 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 9249 | st->print_raw("orq "); |
| 9250 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 9251 | st->print_raw(", "); |
| 9252 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 9253 | st->print_raw("\t# long"); |
| 9254 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 9255 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 9256 | st->print(" ! Field: "); |
| 9257 | if (f->is_volatile()) |
| 9258 | st->print("volatile "); |
| 9259 | f->holder()->name()->print_symbol_on(st); |
| 9260 | st->print("."); |
| 9261 | f->name()->print_symbol_on(st); |
| 9262 | if (f->is_constant()) |
| 9263 | st->print(" (constant)"); |
| 9264 | } else { |
| 9265 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 9266 | st->print(" volatile!"); |
| 9267 | } |
| 9268 | } |
| 9269 | #endif |
| 9270 | #ifndef PRODUCT |
| 9271 | void btsL_mem_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 9272 | // Start at oper_input_base() and count operands |
| 9273 | unsigned idx0 = 2; |
| 9274 | unsigned idx1 = 2; // dst |
| 9275 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con |
| 9276 | st->print_raw("btsq "); |
| 9277 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 9278 | st->print_raw(", log2("); |
| 9279 | opnd_array(2)->ext_format(ra, this,idx2, st); // con |
| 9280 | st->print_raw(")\t# long"); |
| 9281 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 9282 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 9283 | st->print(" ! Field: "); |
| 9284 | if (f->is_volatile()) |
| 9285 | st->print("volatile "); |
| 9286 | f->holder()->name()->print_symbol_on(st); |
| 9287 | st->print("."); |
| 9288 | f->name()->print_symbol_on(st); |
| 9289 | if (f->is_constant()) |
| 9290 | st->print(" (constant)"); |
| 9291 | } else { |
| 9292 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 9293 | st->print(" volatile!"); |
| 9294 | } |
| 9295 | } |
| 9296 | #endif |
| 9297 | #ifndef PRODUCT |
| 9298 | void xorL_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 9299 | // Start at oper_input_base() and count operands |
| 9300 | unsigned idx0 = 1; |
| 9301 | unsigned idx1 = 1; // dst |
| 9302 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 9303 | st->print_raw("xorq "); |
| 9304 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 9305 | st->print_raw(", "); |
| 9306 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 9307 | st->print_raw("\t# long"); |
| 9308 | } |
| 9309 | #endif |
| 9310 | #ifndef PRODUCT |
| 9311 | void xorL_rReg_im1Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 9312 | // Start at oper_input_base() and count operands |
| 9313 | unsigned idx0 = 1; |
| 9314 | unsigned idx1 = 1; // dst |
| 9315 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // imm |
| 9316 | st->print_raw("notq "); |
| 9317 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 9318 | } |
| 9319 | #endif |
| 9320 | #ifndef PRODUCT |
| 9321 | void xorL_rReg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 9322 | // Start at oper_input_base() and count operands |
| 9323 | unsigned idx0 = 1; |
| 9324 | unsigned idx1 = 1; // dst |
| 9325 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 9326 | st->print_raw("xorq "); |
| 9327 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 9328 | st->print_raw(", "); |
| 9329 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 9330 | st->print_raw("\t# long"); |
| 9331 | } |
| 9332 | #endif |
| 9333 | #ifndef PRODUCT |
| 9334 | void xorL_rReg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 9335 | // Start at oper_input_base() and count operands |
| 9336 | unsigned idx0 = 2; |
| 9337 | unsigned idx1 = 2; // dst |
| 9338 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 9339 | st->print_raw("xorq "); |
| 9340 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 9341 | st->print_raw(", "); |
| 9342 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 9343 | st->print_raw("\t# long"); |
| 9344 | } |
| 9345 | #endif |
| 9346 | #ifndef PRODUCT |
| 9347 | void xorL_rReg_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 9348 | // Start at oper_input_base() and count operands |
| 9349 | unsigned idx0 = 2; |
| 9350 | unsigned idx1 = 2; // src |
| 9351 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst |
| 9352 | st->print_raw("xorq "); |
| 9353 | opnd_array(2)->ext_format(ra, this,idx2, st); // dst |
| 9354 | st->print_raw(", "); |
| 9355 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 9356 | st->print_raw("\t# long"); |
| 9357 | } |
| 9358 | #endif |
| 9359 | #ifndef PRODUCT |
| 9360 | void xorL_mem_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 9361 | // Start at oper_input_base() and count operands |
| 9362 | unsigned idx0 = 2; |
| 9363 | unsigned idx1 = 2; // dst |
| 9364 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 9365 | st->print_raw("xorq "); |
| 9366 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 9367 | st->print_raw(", "); |
| 9368 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 9369 | st->print_raw("\t# long"); |
| 9370 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 9371 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 9372 | st->print(" ! Field: "); |
| 9373 | if (f->is_volatile()) |
| 9374 | st->print("volatile "); |
| 9375 | f->holder()->name()->print_symbol_on(st); |
| 9376 | st->print("."); |
| 9377 | f->name()->print_symbol_on(st); |
| 9378 | if (f->is_constant()) |
| 9379 | st->print(" (constant)"); |
| 9380 | } else { |
| 9381 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 9382 | st->print(" volatile!"); |
| 9383 | } |
| 9384 | } |
| 9385 | #endif |
| 9386 | #ifndef PRODUCT |
| 9387 | void xorL_mem_rReg_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 9388 | // Start at oper_input_base() and count operands |
| 9389 | unsigned idx0 = 2; |
| 9390 | unsigned idx1 = 2; // dst |
| 9391 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 9392 | st->print_raw("xorq "); |
| 9393 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 9394 | st->print_raw(", "); |
| 9395 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 9396 | st->print_raw("\t# long"); |
| 9397 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 9398 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 9399 | st->print(" ! Field: "); |
| 9400 | if (f->is_volatile()) |
| 9401 | st->print("volatile "); |
| 9402 | f->holder()->name()->print_symbol_on(st); |
| 9403 | st->print("."); |
| 9404 | f->name()->print_symbol_on(st); |
| 9405 | if (f->is_constant()) |
| 9406 | st->print(" (constant)"); |
| 9407 | } else { |
| 9408 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 9409 | st->print(" volatile!"); |
| 9410 | } |
| 9411 | } |
| 9412 | #endif |
| 9413 | #ifndef PRODUCT |
| 9414 | void xorL_mem_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 9415 | // Start at oper_input_base() and count operands |
| 9416 | unsigned idx0 = 2; |
| 9417 | unsigned idx1 = 2; // dst |
| 9418 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 9419 | st->print_raw("xorq "); |
| 9420 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 9421 | st->print_raw(", "); |
| 9422 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 9423 | st->print_raw("\t# long"); |
| 9424 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 9425 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 9426 | st->print(" ! Field: "); |
| 9427 | if (f->is_volatile()) |
| 9428 | st->print("volatile "); |
| 9429 | f->holder()->name()->print_symbol_on(st); |
| 9430 | st->print("."); |
| 9431 | f->name()->print_symbol_on(st); |
| 9432 | if (f->is_constant()) |
| 9433 | st->print(" (constant)"); |
| 9434 | } else { |
| 9435 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 9436 | st->print(" volatile!"); |
| 9437 | } |
| 9438 | } |
| 9439 | #endif |
| 9440 | #ifndef PRODUCT |
| 9441 | void convI2BNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 9442 | // Start at oper_input_base() and count operands |
| 9443 | unsigned idx0 = 1; |
| 9444 | unsigned idx1 = 1; // src |
| 9445 | st->print_raw("testl "); |
| 9446 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 9447 | st->print_raw(", "); |
| 9448 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 9449 | st->print_raw("\t# ci2b\n\t"); |
| 9450 | st->print_raw("setnz "); |
| 9451 | opnd_array(0)->int_format(ra, this, st); // dst |
| 9452 | st->print_raw("\n\t"); |
| 9453 | st->print_raw("movzbl "); |
| 9454 | opnd_array(0)->int_format(ra, this, st); // dst |
| 9455 | st->print_raw(", "); |
| 9456 | opnd_array(0)->int_format(ra, this, st); // dst |
| 9457 | } |
| 9458 | #endif |
| 9459 | #ifndef PRODUCT |
| 9460 | void convP2BNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 9461 | // Start at oper_input_base() and count operands |
| 9462 | unsigned idx0 = 1; |
| 9463 | unsigned idx1 = 1; // src |
| 9464 | st->print_raw("testq "); |
| 9465 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 9466 | st->print_raw(", "); |
| 9467 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 9468 | st->print_raw("\t# cp2b\n\t"); |
| 9469 | st->print_raw("setnz "); |
| 9470 | opnd_array(0)->int_format(ra, this, st); // dst |
| 9471 | st->print_raw("\n\t"); |
| 9472 | st->print_raw("movzbl "); |
| 9473 | opnd_array(0)->int_format(ra, this, st); // dst |
| 9474 | st->print_raw(", "); |
| 9475 | opnd_array(0)->int_format(ra, this, st); // dst |
| 9476 | } |
| 9477 | #endif |
| 9478 | #ifndef PRODUCT |
| 9479 | void cmpLTMaskNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 9480 | // Start at oper_input_base() and count operands |
| 9481 | unsigned idx0 = 1; |
| 9482 | unsigned idx1 = 1; // p |
| 9483 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // q |
| 9484 | st->print_raw("cmpl "); |
| 9485 | opnd_array(1)->ext_format(ra, this,idx1, st); // p |
| 9486 | st->print_raw(", "); |
| 9487 | opnd_array(2)->ext_format(ra, this,idx2, st); // q |
| 9488 | st->print_raw("\t# cmpLTMask\n\t"); |
| 9489 | st->print_raw("setlt "); |
| 9490 | opnd_array(0)->int_format(ra, this, st); // dst |
| 9491 | st->print_raw("\n\t"); |
| 9492 | st->print_raw("movzbl "); |
| 9493 | opnd_array(0)->int_format(ra, this, st); // dst |
| 9494 | st->print_raw(", "); |
| 9495 | opnd_array(0)->int_format(ra, this, st); // dst |
| 9496 | st->print_raw("\n\t"); |
| 9497 | st->print_raw("negl "); |
| 9498 | opnd_array(0)->int_format(ra, this, st); // dst |
| 9499 | } |
| 9500 | #endif |
| 9501 | #ifndef PRODUCT |
| 9502 | void cmpLTMask0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 9503 | // Start at oper_input_base() and count operands |
| 9504 | unsigned idx0 = 1; |
| 9505 | unsigned idx1 = 1; // dst |
| 9506 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero |
| 9507 | st->print_raw("sarl "); |
| 9508 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 9509 | st->print_raw(", #31\t# cmpLTMask0"); |
| 9510 | } |
| 9511 | #endif |
| 9512 | #ifndef PRODUCT |
| 9513 | void cadd_cmpLTMaskNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 9514 | // Start at oper_input_base() and count operands |
| 9515 | unsigned idx0 = 1; |
| 9516 | unsigned idx1 = 1; // p |
| 9517 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // q |
| 9518 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // y |
| 9519 | st->print_raw("subl "); |
| 9520 | opnd_array(1)->ext_format(ra, this,idx1, st); // p |
| 9521 | st->print_raw(","); |
| 9522 | opnd_array(2)->ext_format(ra, this,idx2, st); // q |
| 9523 | st->print_raw("\t# cadd_cmpLTMask\n\t"); |
| 9524 | st->print_raw("jge done\n\t"); |
| 9525 | st->print_raw("addl "); |
| 9526 | opnd_array(1)->ext_format(ra, this,idx1, st); // p |
| 9527 | st->print_raw(","); |
| 9528 | opnd_array(3)->ext_format(ra, this,idx3, st); // y |
| 9529 | st->print_raw("\n"); |
| 9530 | st->print_raw("done: "); |
| 9531 | } |
| 9532 | #endif |
| 9533 | #ifndef PRODUCT |
| 9534 | void cadd_cmpLTMask_1Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 9535 | // Start at oper_input_base() and count operands |
| 9536 | unsigned idx0 = 1; |
| 9537 | unsigned idx1 = 1; // p |
| 9538 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // q |
| 9539 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // y |
| 9540 | st->print_raw("subl "); |
| 9541 | opnd_array(1)->ext_format(ra, this,idx1, st); // p |
| 9542 | st->print_raw(","); |
| 9543 | opnd_array(2)->ext_format(ra, this,idx2, st); // q |
| 9544 | st->print_raw("\t# cadd_cmpLTMask\n\t"); |
| 9545 | st->print_raw("jge done\n\t"); |
| 9546 | st->print_raw("addl "); |
| 9547 | opnd_array(1)->ext_format(ra, this,idx1, st); // p |
| 9548 | st->print_raw(","); |
| 9549 | opnd_array(3)->ext_format(ra, this,idx3, st); // y |
| 9550 | st->print_raw("\n"); |
| 9551 | st->print_raw("done: "); |
| 9552 | } |
| 9553 | #endif |
| 9554 | #ifndef PRODUCT |
| 9555 | void cadd_cmpLTMask_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 9556 | // Start at oper_input_base() and count operands |
| 9557 | unsigned idx0 = 1; |
| 9558 | unsigned idx1 = 1; // y |
| 9559 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // p |
| 9560 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // q |
| 9561 | st->print_raw("subl "); |
| 9562 | opnd_array(2)->ext_format(ra, this,idx2, st); // p |
| 9563 | st->print_raw(","); |
| 9564 | opnd_array(3)->ext_format(ra, this,idx3, st); // q |
| 9565 | st->print_raw("\t# cadd_cmpLTMask\n\t"); |
| 9566 | st->print_raw("jge done\n\t"); |
| 9567 | st->print_raw("addl "); |
| 9568 | opnd_array(2)->ext_format(ra, this,idx2, st); // p |
| 9569 | st->print_raw(","); |
| 9570 | opnd_array(1)->ext_format(ra, this,idx1, st); // y |
| 9571 | st->print_raw("\n"); |
| 9572 | st->print_raw("done: "); |
| 9573 | } |
| 9574 | #endif |
| 9575 | #ifndef PRODUCT |
| 9576 | void cadd_cmpLTMask_2Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 9577 | // Start at oper_input_base() and count operands |
| 9578 | unsigned idx0 = 1; |
| 9579 | unsigned idx1 = 1; // p |
| 9580 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // q |
| 9581 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // y |
| 9582 | st->print_raw("subl "); |
| 9583 | opnd_array(1)->ext_format(ra, this,idx1, st); // p |
| 9584 | st->print_raw(","); |
| 9585 | opnd_array(2)->ext_format(ra, this,idx2, st); // q |
| 9586 | st->print_raw("\t# cadd_cmpLTMask\n\t"); |
| 9587 | st->print_raw("jge done\n\t"); |
| 9588 | st->print_raw("addl "); |
| 9589 | opnd_array(1)->ext_format(ra, this,idx1, st); // p |
| 9590 | st->print_raw(","); |
| 9591 | opnd_array(3)->ext_format(ra, this,idx3, st); // y |
| 9592 | st->print_raw("\n"); |
| 9593 | st->print_raw("done: "); |
| 9594 | } |
| 9595 | #endif |
| 9596 | #ifndef PRODUCT |
| 9597 | void and_cmpLTMaskNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 9598 | // Start at oper_input_base() and count operands |
| 9599 | unsigned idx0 = 1; |
| 9600 | unsigned idx1 = 1; // p |
| 9601 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // q |
| 9602 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // y |
| 9603 | st->print_raw("cmpl "); |
| 9604 | opnd_array(1)->ext_format(ra, this,idx1, st); // p |
| 9605 | st->print_raw(", "); |
| 9606 | opnd_array(2)->ext_format(ra, this,idx2, st); // q |
| 9607 | st->print_raw("\t# and_cmpLTMask\n\t"); |
| 9608 | st->print_raw("jlt done\n\t"); |
| 9609 | st->print_raw("xorl "); |
| 9610 | opnd_array(3)->ext_format(ra, this,idx3, st); // y |
| 9611 | st->print_raw(", "); |
| 9612 | opnd_array(3)->ext_format(ra, this,idx3, st); // y |
| 9613 | st->print_raw("\n"); |
| 9614 | st->print_raw("done: "); |
| 9615 | } |
| 9616 | #endif |
| 9617 | #ifndef PRODUCT |
| 9618 | void and_cmpLTMask_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 9619 | // Start at oper_input_base() and count operands |
| 9620 | unsigned idx0 = 1; |
| 9621 | unsigned idx1 = 1; // y |
| 9622 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // p |
| 9623 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // q |
| 9624 | st->print_raw("cmpl "); |
| 9625 | opnd_array(2)->ext_format(ra, this,idx2, st); // p |
| 9626 | st->print_raw(", "); |
| 9627 | opnd_array(3)->ext_format(ra, this,idx3, st); // q |
| 9628 | st->print_raw("\t# and_cmpLTMask\n\t"); |
| 9629 | st->print_raw("jlt done\n\t"); |
| 9630 | st->print_raw("xorl "); |
| 9631 | opnd_array(1)->ext_format(ra, this,idx1, st); // y |
| 9632 | st->print_raw(", "); |
| 9633 | opnd_array(1)->ext_format(ra, this,idx1, st); // y |
| 9634 | st->print_raw("\n"); |
| 9635 | st->print_raw("done: "); |
| 9636 | } |
| 9637 | #endif |
| 9638 | #ifndef PRODUCT |
| 9639 | void cmpF_cc_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 9640 | // Start at oper_input_base() and count operands |
| 9641 | unsigned idx0 = 1; |
| 9642 | unsigned idx1 = 1; // src1 |
| 9643 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 9644 | st->print_raw("ucomiss "); |
| 9645 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 9646 | st->print_raw(", "); |
| 9647 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 9648 | st->print_raw("\n\t"); |
| 9649 | st->print_raw("jnp,s exit\n\t"); |
| 9650 | st->print_raw("pushfq\t# saw NaN, set CF\n\t"); |
| 9651 | st->print_raw("andq [rsp], #0xffffff2b\n\t"); |
| 9652 | st->print_raw("popfq\n"); |
| 9653 | st->print_raw("exit:"); |
| 9654 | } |
| 9655 | #endif |
| 9656 | #ifndef PRODUCT |
| 9657 | void cmpF_cc_reg_CFNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 9658 | // Start at oper_input_base() and count operands |
| 9659 | unsigned idx0 = 1; |
| 9660 | unsigned idx1 = 1; // src1 |
| 9661 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 9662 | st->print_raw("ucomiss "); |
| 9663 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 9664 | st->print_raw(", "); |
| 9665 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 9666 | } |
| 9667 | #endif |
| 9668 | #ifndef PRODUCT |
| 9669 | void cmpF_cc_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 9670 | // Start at oper_input_base() and count operands |
| 9671 | unsigned idx0 = 2; |
| 9672 | unsigned idx1 = 2; // src1 |
| 9673 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 9674 | st->print_raw("ucomiss "); |
| 9675 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 9676 | st->print_raw(", "); |
| 9677 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 9678 | st->print_raw("\n\t"); |
| 9679 | st->print_raw("jnp,s exit\n\t"); |
| 9680 | st->print_raw("pushfq\t# saw NaN, set CF\n\t"); |
| 9681 | st->print_raw("andq [rsp], #0xffffff2b\n\t"); |
| 9682 | st->print_raw("popfq\n"); |
| 9683 | st->print_raw("exit:"); |
| 9684 | } |
| 9685 | #endif |
| 9686 | #ifndef PRODUCT |
| 9687 | void cmpF_cc_memCFNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 9688 | // Start at oper_input_base() and count operands |
| 9689 | unsigned idx0 = 2; |
| 9690 | unsigned idx1 = 2; // src1 |
| 9691 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 9692 | st->print_raw("ucomiss "); |
| 9693 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 9694 | st->print_raw(", "); |
| 9695 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 9696 | } |
| 9697 | #endif |
| 9698 | #ifndef PRODUCT |
| 9699 | void cmpF_cc_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 9700 | // Start at oper_input_base() and count operands |
| 9701 | unsigned idx0 = 1; |
| 9702 | unsigned idx1 = 1; // src |
| 9703 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con |
| 9704 | st->print_raw("ucomiss "); |
| 9705 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 9706 | st->print_raw(", ["); |
| 9707 | st->print("constant table base + #%d", constant_offset_unchecked()); |
| 9708 | st->print_raw("]\t# load from constant table: float="); |
| 9709 | opnd_array(2)->ext_format(ra, this,idx2, st); // con |
| 9710 | st->print_raw("\n\t"); |
| 9711 | st->print_raw("jnp,s exit\n\t"); |
| 9712 | st->print_raw("pushfq\t# saw NaN, set CF\n\t"); |
| 9713 | st->print_raw("andq [rsp], #0xffffff2b\n\t"); |
| 9714 | st->print_raw("popfq\n"); |
| 9715 | st->print_raw("exit:"); |
| 9716 | } |
| 9717 | #endif |
| 9718 | #ifndef PRODUCT |
| 9719 | void cmpF_cc_immCFNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 9720 | // Start at oper_input_base() and count operands |
| 9721 | unsigned idx0 = 1; |
| 9722 | unsigned idx1 = 1; // src |
| 9723 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con |
| 9724 | st->print_raw("ucomiss "); |
| 9725 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 9726 | st->print_raw(", ["); |
| 9727 | st->print("constant table base + #%d", constant_offset_unchecked()); |
| 9728 | st->print_raw("]\t# load from constant table: float="); |
| 9729 | opnd_array(2)->ext_format(ra, this,idx2, st); // con |
| 9730 | } |
| 9731 | #endif |
| 9732 | #ifndef PRODUCT |
| 9733 | void cmpD_cc_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 9734 | // Start at oper_input_base() and count operands |
| 9735 | unsigned idx0 = 1; |
| 9736 | unsigned idx1 = 1; // src1 |
| 9737 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 9738 | st->print_raw("ucomisd "); |
| 9739 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 9740 | st->print_raw(", "); |
| 9741 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 9742 | st->print_raw("\n\t"); |
| 9743 | st->print_raw("jnp,s exit\n\t"); |
| 9744 | st->print_raw("pushfq\t# saw NaN, set CF\n\t"); |
| 9745 | st->print_raw("andq [rsp], #0xffffff2b\n\t"); |
| 9746 | st->print_raw("popfq\n"); |
| 9747 | st->print_raw("exit:"); |
| 9748 | } |
| 9749 | #endif |
| 9750 | #ifndef PRODUCT |
| 9751 | void cmpD_cc_reg_CFNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 9752 | // Start at oper_input_base() and count operands |
| 9753 | unsigned idx0 = 1; |
| 9754 | unsigned idx1 = 1; // src1 |
| 9755 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 9756 | st->print_raw("ucomisd "); |
| 9757 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 9758 | st->print_raw(", "); |
| 9759 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 9760 | st->print_raw(" test"); |
| 9761 | } |
| 9762 | #endif |
| 9763 | #ifndef PRODUCT |
| 9764 | void cmpD_cc_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 9765 | // Start at oper_input_base() and count operands |
| 9766 | unsigned idx0 = 2; |
| 9767 | unsigned idx1 = 2; // src1 |
| 9768 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 9769 | st->print_raw("ucomisd "); |
| 9770 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 9771 | st->print_raw(", "); |
| 9772 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 9773 | st->print_raw("\n\t"); |
| 9774 | st->print_raw("jnp,s exit\n\t"); |
| 9775 | st->print_raw("pushfq\t# saw NaN, set CF\n\t"); |
| 9776 | st->print_raw("andq [rsp], #0xffffff2b\n\t"); |
| 9777 | st->print_raw("popfq\n"); |
| 9778 | st->print_raw("exit:"); |
| 9779 | } |
| 9780 | #endif |
| 9781 | #ifndef PRODUCT |
| 9782 | void cmpD_cc_memCFNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 9783 | // Start at oper_input_base() and count operands |
| 9784 | unsigned idx0 = 2; |
| 9785 | unsigned idx1 = 2; // src1 |
| 9786 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 9787 | st->print_raw("ucomisd "); |
| 9788 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 9789 | st->print_raw(", "); |
| 9790 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 9791 | } |
| 9792 | #endif |
| 9793 | #ifndef PRODUCT |
| 9794 | void cmpD_cc_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 9795 | // Start at oper_input_base() and count operands |
| 9796 | unsigned idx0 = 1; |
| 9797 | unsigned idx1 = 1; // src |
| 9798 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con |
| 9799 | st->print_raw("ucomisd "); |
| 9800 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 9801 | st->print_raw(", ["); |
| 9802 | st->print("constant table base + #%d", constant_offset_unchecked()); |
| 9803 | st->print_raw("]\t# load from constant table: double="); |
| 9804 | opnd_array(2)->ext_format(ra, this,idx2, st); // con |
| 9805 | st->print_raw("\n\t"); |
| 9806 | st->print_raw("jnp,s exit\n\t"); |
| 9807 | st->print_raw("pushfq\t# saw NaN, set CF\n\t"); |
| 9808 | st->print_raw("andq [rsp], #0xffffff2b\n\t"); |
| 9809 | st->print_raw("popfq\n"); |
| 9810 | st->print_raw("exit:"); |
| 9811 | } |
| 9812 | #endif |
| 9813 | #ifndef PRODUCT |
| 9814 | void cmpD_cc_immCFNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 9815 | // Start at oper_input_base() and count operands |
| 9816 | unsigned idx0 = 1; |
| 9817 | unsigned idx1 = 1; // src |
| 9818 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con |
| 9819 | st->print_raw("ucomisd "); |
| 9820 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 9821 | st->print_raw(", ["); |
| 9822 | st->print("constant table base + #%d", constant_offset_unchecked()); |
| 9823 | st->print_raw("]\t# load from constant table: double="); |
| 9824 | opnd_array(2)->ext_format(ra, this,idx2, st); // con |
| 9825 | } |
| 9826 | #endif |
| 9827 | #ifndef PRODUCT |
| 9828 | void cmpF_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 9829 | // Start at oper_input_base() and count operands |
| 9830 | unsigned idx0 = 1; |
| 9831 | unsigned idx1 = 1; // src1 |
| 9832 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 9833 | st->print_raw("ucomiss "); |
| 9834 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 9835 | st->print_raw(", "); |
| 9836 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 9837 | st->print_raw("\n\t"); |
| 9838 | st->print_raw("movl "); |
| 9839 | opnd_array(0)->int_format(ra, this, st); // dst |
| 9840 | st->print_raw(", #-1\n\t"); |
| 9841 | st->print_raw("jp,s done\n\t"); |
| 9842 | st->print_raw("jb,s done\n\t"); |
| 9843 | st->print_raw("setne "); |
| 9844 | opnd_array(0)->int_format(ra, this, st); // dst |
| 9845 | st->print_raw("\n\t"); |
| 9846 | st->print_raw("movzbl "); |
| 9847 | opnd_array(0)->int_format(ra, this, st); // dst |
| 9848 | st->print_raw(", "); |
| 9849 | opnd_array(0)->int_format(ra, this, st); // dst |
| 9850 | st->print_raw("\n"); |
| 9851 | st->print_raw("done:"); |
| 9852 | } |
| 9853 | #endif |
| 9854 | #ifndef PRODUCT |
| 9855 | void cmpF_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 9856 | // Start at oper_input_base() and count operands |
| 9857 | unsigned idx0 = 2; |
| 9858 | unsigned idx1 = 2; // src1 |
| 9859 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 9860 | st->print_raw("ucomiss "); |
| 9861 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 9862 | st->print_raw(", "); |
| 9863 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 9864 | st->print_raw("\n\t"); |
| 9865 | st->print_raw("movl "); |
| 9866 | opnd_array(0)->int_format(ra, this, st); // dst |
| 9867 | st->print_raw(", #-1\n\t"); |
| 9868 | st->print_raw("jp,s done\n\t"); |
| 9869 | st->print_raw("jb,s done\n\t"); |
| 9870 | st->print_raw("setne "); |
| 9871 | opnd_array(0)->int_format(ra, this, st); // dst |
| 9872 | st->print_raw("\n\t"); |
| 9873 | st->print_raw("movzbl "); |
| 9874 | opnd_array(0)->int_format(ra, this, st); // dst |
| 9875 | st->print_raw(", "); |
| 9876 | opnd_array(0)->int_format(ra, this, st); // dst |
| 9877 | st->print_raw("\n"); |
| 9878 | st->print_raw("done:"); |
| 9879 | } |
| 9880 | #endif |
| 9881 | #ifndef PRODUCT |
| 9882 | void cmpF_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 9883 | // Start at oper_input_base() and count operands |
| 9884 | unsigned idx0 = 1; |
| 9885 | unsigned idx1 = 1; // src |
| 9886 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con |
| 9887 | st->print_raw("ucomiss "); |
| 9888 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 9889 | st->print_raw(", ["); |
| 9890 | st->print("constant table base + #%d", constant_offset_unchecked()); |
| 9891 | st->print_raw("]\t# load from constant table: float="); |
| 9892 | opnd_array(2)->ext_format(ra, this,idx2, st); // con |
| 9893 | st->print_raw("\n\t"); |
| 9894 | st->print_raw("movl "); |
| 9895 | opnd_array(0)->int_format(ra, this, st); // dst |
| 9896 | st->print_raw(", #-1\n\t"); |
| 9897 | st->print_raw("jp,s done\n\t"); |
| 9898 | st->print_raw("jb,s done\n\t"); |
| 9899 | st->print_raw("setne "); |
| 9900 | opnd_array(0)->int_format(ra, this, st); // dst |
| 9901 | st->print_raw("\n\t"); |
| 9902 | st->print_raw("movzbl "); |
| 9903 | opnd_array(0)->int_format(ra, this, st); // dst |
| 9904 | st->print_raw(", "); |
| 9905 | opnd_array(0)->int_format(ra, this, st); // dst |
| 9906 | st->print_raw("\n"); |
| 9907 | st->print_raw("done:"); |
| 9908 | } |
| 9909 | #endif |
| 9910 | #ifndef PRODUCT |
| 9911 | void cmpD_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 9912 | // Start at oper_input_base() and count operands |
| 9913 | unsigned idx0 = 1; |
| 9914 | unsigned idx1 = 1; // src1 |
| 9915 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 9916 | st->print_raw("ucomisd "); |
| 9917 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 9918 | st->print_raw(", "); |
| 9919 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 9920 | st->print_raw("\n\t"); |
| 9921 | st->print_raw("movl "); |
| 9922 | opnd_array(0)->int_format(ra, this, st); // dst |
| 9923 | st->print_raw(", #-1\n\t"); |
| 9924 | st->print_raw("jp,s done\n\t"); |
| 9925 | st->print_raw("jb,s done\n\t"); |
| 9926 | st->print_raw("setne "); |
| 9927 | opnd_array(0)->int_format(ra, this, st); // dst |
| 9928 | st->print_raw("\n\t"); |
| 9929 | st->print_raw("movzbl "); |
| 9930 | opnd_array(0)->int_format(ra, this, st); // dst |
| 9931 | st->print_raw(", "); |
| 9932 | opnd_array(0)->int_format(ra, this, st); // dst |
| 9933 | st->print_raw("\n"); |
| 9934 | st->print_raw("done:"); |
| 9935 | } |
| 9936 | #endif |
| 9937 | #ifndef PRODUCT |
| 9938 | void cmpD_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 9939 | // Start at oper_input_base() and count operands |
| 9940 | unsigned idx0 = 2; |
| 9941 | unsigned idx1 = 2; // src1 |
| 9942 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 9943 | st->print_raw("ucomisd "); |
| 9944 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 9945 | st->print_raw(", "); |
| 9946 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 9947 | st->print_raw("\n\t"); |
| 9948 | st->print_raw("movl "); |
| 9949 | opnd_array(0)->int_format(ra, this, st); // dst |
| 9950 | st->print_raw(", #-1\n\t"); |
| 9951 | st->print_raw("jp,s done\n\t"); |
| 9952 | st->print_raw("jb,s done\n\t"); |
| 9953 | st->print_raw("setne "); |
| 9954 | opnd_array(0)->int_format(ra, this, st); // dst |
| 9955 | st->print_raw("\n\t"); |
| 9956 | st->print_raw("movzbl "); |
| 9957 | opnd_array(0)->int_format(ra, this, st); // dst |
| 9958 | st->print_raw(", "); |
| 9959 | opnd_array(0)->int_format(ra, this, st); // dst |
| 9960 | st->print_raw("\n"); |
| 9961 | st->print_raw("done:"); |
| 9962 | } |
| 9963 | #endif |
| 9964 | #ifndef PRODUCT |
| 9965 | void cmpD_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 9966 | // Start at oper_input_base() and count operands |
| 9967 | unsigned idx0 = 1; |
| 9968 | unsigned idx1 = 1; // src |
| 9969 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con |
| 9970 | st->print_raw("ucomisd "); |
| 9971 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 9972 | st->print_raw(", ["); |
| 9973 | st->print("constant table base + #%d", constant_offset_unchecked()); |
| 9974 | st->print_raw("]\t# load from constant table: double="); |
| 9975 | opnd_array(2)->ext_format(ra, this,idx2, st); // con |
| 9976 | st->print_raw("\n\t"); |
| 9977 | st->print_raw("movl "); |
| 9978 | opnd_array(0)->int_format(ra, this, st); // dst |
| 9979 | st->print_raw(", #-1\n\t"); |
| 9980 | st->print_raw("jp,s done\n\t"); |
| 9981 | st->print_raw("jb,s done\n\t"); |
| 9982 | st->print_raw("setne "); |
| 9983 | opnd_array(0)->int_format(ra, this, st); // dst |
| 9984 | st->print_raw("\n\t"); |
| 9985 | st->print_raw("movzbl "); |
| 9986 | opnd_array(0)->int_format(ra, this, st); // dst |
| 9987 | st->print_raw(", "); |
| 9988 | opnd_array(0)->int_format(ra, this, st); // dst |
| 9989 | st->print_raw("\n"); |
| 9990 | st->print_raw("done:"); |
| 9991 | } |
| 9992 | #endif |
| 9993 | #ifndef PRODUCT |
| 9994 | void convF2D_reg_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 9995 | // Start at oper_input_base() and count operands |
| 9996 | unsigned idx0 = 1; |
| 9997 | unsigned idx1 = 1; // src |
| 9998 | st->print_raw("cvtss2sd "); |
| 9999 | opnd_array(0)->int_format(ra, this, st); // dst |
| 10000 | st->print_raw(", "); |
| 10001 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 10002 | } |
| 10003 | #endif |
| 10004 | #ifndef PRODUCT |
| 10005 | void convF2D_reg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 10006 | // Start at oper_input_base() and count operands |
| 10007 | unsigned idx0 = 2; |
| 10008 | unsigned idx1 = 2; // src |
| 10009 | st->print_raw("cvtss2sd "); |
| 10010 | opnd_array(0)->int_format(ra, this, st); // dst |
| 10011 | st->print_raw(", "); |
| 10012 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 10013 | } |
| 10014 | #endif |
| 10015 | #ifndef PRODUCT |
| 10016 | void convD2F_reg_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 10017 | // Start at oper_input_base() and count operands |
| 10018 | unsigned idx0 = 1; |
| 10019 | unsigned idx1 = 1; // src |
| 10020 | st->print_raw("cvtsd2ss "); |
| 10021 | opnd_array(0)->int_format(ra, this, st); // dst |
| 10022 | st->print_raw(", "); |
| 10023 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 10024 | } |
| 10025 | #endif |
| 10026 | #ifndef PRODUCT |
| 10027 | void convD2F_reg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 10028 | // Start at oper_input_base() and count operands |
| 10029 | unsigned idx0 = 2; |
| 10030 | unsigned idx1 = 2; // src |
| 10031 | st->print_raw("cvtsd2ss "); |
| 10032 | opnd_array(0)->int_format(ra, this, st); // dst |
| 10033 | st->print_raw(", "); |
| 10034 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 10035 | } |
| 10036 | #endif |
| 10037 | #ifndef PRODUCT |
| 10038 | void convF2I_reg_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 10039 | // Start at oper_input_base() and count operands |
| 10040 | unsigned idx0 = 1; |
| 10041 | unsigned idx1 = 1; // src |
| 10042 | st->print_raw("convert_f2i "); |
| 10043 | opnd_array(0)->int_format(ra, this, st); // dst |
| 10044 | st->print_raw(","); |
| 10045 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 10046 | } |
| 10047 | #endif |
| 10048 | #ifndef PRODUCT |
| 10049 | void convF2L_reg_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 10050 | // Start at oper_input_base() and count operands |
| 10051 | unsigned idx0 = 1; |
| 10052 | unsigned idx1 = 1; // src |
| 10053 | st->print_raw("convert_f2l "); |
| 10054 | opnd_array(0)->int_format(ra, this, st); // dst |
| 10055 | st->print_raw(","); |
| 10056 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 10057 | } |
| 10058 | #endif |
| 10059 | #ifndef PRODUCT |
| 10060 | void convD2I_reg_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 10061 | // Start at oper_input_base() and count operands |
| 10062 | unsigned idx0 = 1; |
| 10063 | unsigned idx1 = 1; // src |
| 10064 | st->print_raw("convert_d2i "); |
| 10065 | opnd_array(0)->int_format(ra, this, st); // dst |
| 10066 | st->print_raw(","); |
| 10067 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 10068 | } |
| 10069 | #endif |
| 10070 | #ifndef PRODUCT |
| 10071 | void convD2L_reg_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 10072 | // Start at oper_input_base() and count operands |
| 10073 | unsigned idx0 = 1; |
| 10074 | unsigned idx1 = 1; // src |
| 10075 | st->print_raw("convert_d2l "); |
| 10076 | opnd_array(0)->int_format(ra, this, st); // dst |
| 10077 | st->print_raw(","); |
| 10078 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 10079 | } |
| 10080 | #endif |
| 10081 | #ifndef PRODUCT |
| 10082 | void convI2F_reg_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 10083 | // Start at oper_input_base() and count operands |
| 10084 | unsigned idx0 = 1; |
| 10085 | unsigned idx1 = 1; // src |
| 10086 | st->print_raw("cvtsi2ssl "); |
| 10087 | opnd_array(0)->int_format(ra, this, st); // dst |
| 10088 | st->print_raw(", "); |
| 10089 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 10090 | st->print_raw("\t# i2f"); |
| 10091 | } |
| 10092 | #endif |
| 10093 | #ifndef PRODUCT |
| 10094 | void convI2F_reg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 10095 | // Start at oper_input_base() and count operands |
| 10096 | unsigned idx0 = 2; |
| 10097 | unsigned idx1 = 2; // src |
| 10098 | st->print_raw("cvtsi2ssl "); |
| 10099 | opnd_array(0)->int_format(ra, this, st); // dst |
| 10100 | st->print_raw(", "); |
| 10101 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 10102 | st->print_raw("\t# i2f"); |
| 10103 | } |
| 10104 | #endif |
| 10105 | #ifndef PRODUCT |
| 10106 | void convI2D_reg_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 10107 | // Start at oper_input_base() and count operands |
| 10108 | unsigned idx0 = 1; |
| 10109 | unsigned idx1 = 1; // src |
| 10110 | st->print_raw("cvtsi2sdl "); |
| 10111 | opnd_array(0)->int_format(ra, this, st); // dst |
| 10112 | st->print_raw(", "); |
| 10113 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 10114 | st->print_raw("\t# i2d"); |
| 10115 | } |
| 10116 | #endif |
| 10117 | #ifndef PRODUCT |
| 10118 | void convI2D_reg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 10119 | // Start at oper_input_base() and count operands |
| 10120 | unsigned idx0 = 2; |
| 10121 | unsigned idx1 = 2; // src |
| 10122 | st->print_raw("cvtsi2sdl "); |
| 10123 | opnd_array(0)->int_format(ra, this, st); // dst |
| 10124 | st->print_raw(", "); |
| 10125 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 10126 | st->print_raw("\t# i2d"); |
| 10127 | } |
| 10128 | #endif |
| 10129 | #ifndef PRODUCT |
| 10130 | void convXI2F_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 10131 | // Start at oper_input_base() and count operands |
| 10132 | unsigned idx0 = 1; |
| 10133 | unsigned idx1 = 1; // src |
| 10134 | st->print_raw("movdl "); |
| 10135 | opnd_array(0)->int_format(ra, this, st); // dst |
| 10136 | st->print_raw(", "); |
| 10137 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 10138 | st->print_raw("\n\t"); |
| 10139 | st->print_raw("cvtdq2psl "); |
| 10140 | opnd_array(0)->int_format(ra, this, st); // dst |
| 10141 | st->print_raw(", "); |
| 10142 | opnd_array(0)->int_format(ra, this, st); // dst |
| 10143 | st->print_raw("\t# i2f"); |
| 10144 | } |
| 10145 | #endif |
| 10146 | #ifndef PRODUCT |
| 10147 | void convXI2D_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 10148 | // Start at oper_input_base() and count operands |
| 10149 | unsigned idx0 = 1; |
| 10150 | unsigned idx1 = 1; // src |
| 10151 | st->print_raw("movdl "); |
| 10152 | opnd_array(0)->int_format(ra, this, st); // dst |
| 10153 | st->print_raw(", "); |
| 10154 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 10155 | st->print_raw("\n\t"); |
| 10156 | st->print_raw("cvtdq2pdl "); |
| 10157 | opnd_array(0)->int_format(ra, this, st); // dst |
| 10158 | st->print_raw(", "); |
| 10159 | opnd_array(0)->int_format(ra, this, st); // dst |
| 10160 | st->print_raw("\t# i2d"); |
| 10161 | } |
| 10162 | #endif |
| 10163 | #ifndef PRODUCT |
| 10164 | void convL2F_reg_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 10165 | // Start at oper_input_base() and count operands |
| 10166 | unsigned idx0 = 1; |
| 10167 | unsigned idx1 = 1; // src |
| 10168 | st->print_raw("cvtsi2ssq "); |
| 10169 | opnd_array(0)->int_format(ra, this, st); // dst |
| 10170 | st->print_raw(", "); |
| 10171 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 10172 | st->print_raw("\t# l2f"); |
| 10173 | } |
| 10174 | #endif |
| 10175 | #ifndef PRODUCT |
| 10176 | void convL2F_reg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 10177 | // Start at oper_input_base() and count operands |
| 10178 | unsigned idx0 = 2; |
| 10179 | unsigned idx1 = 2; // src |
| 10180 | st->print_raw("cvtsi2ssq "); |
| 10181 | opnd_array(0)->int_format(ra, this, st); // dst |
| 10182 | st->print_raw(", "); |
| 10183 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 10184 | st->print_raw("\t# l2f"); |
| 10185 | } |
| 10186 | #endif |
| 10187 | #ifndef PRODUCT |
| 10188 | void convL2D_reg_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 10189 | // Start at oper_input_base() and count operands |
| 10190 | unsigned idx0 = 1; |
| 10191 | unsigned idx1 = 1; // src |
| 10192 | st->print_raw("cvtsi2sdq "); |
| 10193 | opnd_array(0)->int_format(ra, this, st); // dst |
| 10194 | st->print_raw(", "); |
| 10195 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 10196 | st->print_raw("\t# l2d"); |
| 10197 | } |
| 10198 | #endif |
| 10199 | #ifndef PRODUCT |
| 10200 | void convL2D_reg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 10201 | // Start at oper_input_base() and count operands |
| 10202 | unsigned idx0 = 2; |
| 10203 | unsigned idx1 = 2; // src |
| 10204 | st->print_raw("cvtsi2sdq "); |
| 10205 | opnd_array(0)->int_format(ra, this, st); // dst |
| 10206 | st->print_raw(", "); |
| 10207 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 10208 | st->print_raw("\t# l2d"); |
| 10209 | } |
| 10210 | #endif |
| 10211 | #ifndef PRODUCT |
| 10212 | void convI2L_reg_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 10213 | // Start at oper_input_base() and count operands |
| 10214 | unsigned idx0 = 1; |
| 10215 | unsigned idx1 = 1; // src |
| 10216 | st->print_raw("movslq "); |
| 10217 | opnd_array(0)->int_format(ra, this, st); // dst |
| 10218 | st->print_raw(", "); |
| 10219 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 10220 | st->print_raw("\t# i2l"); |
| 10221 | } |
| 10222 | #endif |
| 10223 | #ifndef PRODUCT |
| 10224 | void convI2L_reg_reg_zexNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 10225 | // Start at oper_input_base() and count operands |
| 10226 | unsigned idx0 = 1; |
| 10227 | unsigned idx1 = 1; // src |
| 10228 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask |
| 10229 | st->print_raw("movl "); |
| 10230 | opnd_array(0)->int_format(ra, this, st); // dst |
| 10231 | st->print_raw(", "); |
| 10232 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 10233 | st->print_raw("\t# i2l zero-extend\n\t"); |
| 10234 | } |
| 10235 | #endif |
| 10236 | #ifndef PRODUCT |
| 10237 | void convI2L_reg_mem_zexNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 10238 | // Start at oper_input_base() and count operands |
| 10239 | unsigned idx0 = 2; |
| 10240 | unsigned idx1 = 2; // src |
| 10241 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask |
| 10242 | st->print_raw("movl "); |
| 10243 | opnd_array(0)->int_format(ra, this, st); // dst |
| 10244 | st->print_raw(", "); |
| 10245 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 10246 | st->print_raw("\t# i2l zero-extend\n\t"); |
| 10247 | } |
| 10248 | #endif |
| 10249 | #ifndef PRODUCT |
| 10250 | void zerox_long_reg_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 10251 | // Start at oper_input_base() and count operands |
| 10252 | unsigned idx0 = 1; |
| 10253 | unsigned idx1 = 1; // src |
| 10254 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask |
| 10255 | st->print_raw("movl "); |
| 10256 | opnd_array(0)->int_format(ra, this, st); // dst |
| 10257 | st->print_raw(", "); |
| 10258 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 10259 | st->print_raw("\t# zero-extend long"); |
| 10260 | } |
| 10261 | #endif |
| 10262 | #ifndef PRODUCT |
| 10263 | void convL2I_reg_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 10264 | // Start at oper_input_base() and count operands |
| 10265 | unsigned idx0 = 1; |
| 10266 | unsigned idx1 = 1; // src |
| 10267 | st->print_raw("movl "); |
| 10268 | opnd_array(0)->int_format(ra, this, st); // dst |
| 10269 | st->print_raw(", "); |
| 10270 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 10271 | st->print_raw("\t# l2i"); |
| 10272 | } |
| 10273 | #endif |
| 10274 | #ifndef PRODUCT |
| 10275 | void MoveF2I_stack_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 10276 | // Start at oper_input_base() and count operands |
| 10277 | unsigned idx0 = 1; |
| 10278 | unsigned idx1 = 1; // src |
| 10279 | st->print_raw("movl "); |
| 10280 | opnd_array(0)->int_format(ra, this, st); // dst |
| 10281 | st->print_raw(", "); |
| 10282 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 10283 | st->print_raw("\t# MoveF2I_stack_reg"); |
| 10284 | } |
| 10285 | #endif |
| 10286 | #ifndef PRODUCT |
| 10287 | void MoveI2F_stack_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 10288 | // Start at oper_input_base() and count operands |
| 10289 | unsigned idx0 = 1; |
| 10290 | unsigned idx1 = 1; // src |
| 10291 | st->print_raw("movss "); |
| 10292 | opnd_array(0)->int_format(ra, this, st); // dst |
| 10293 | st->print_raw(", "); |
| 10294 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 10295 | st->print_raw("\t# MoveI2F_stack_reg"); |
| 10296 | } |
| 10297 | #endif |
| 10298 | #ifndef PRODUCT |
| 10299 | void MoveD2L_stack_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 10300 | // Start at oper_input_base() and count operands |
| 10301 | unsigned idx0 = 1; |
| 10302 | unsigned idx1 = 1; // src |
| 10303 | st->print_raw("movq "); |
| 10304 | opnd_array(0)->int_format(ra, this, st); // dst |
| 10305 | st->print_raw(", "); |
| 10306 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 10307 | st->print_raw("\t# MoveD2L_stack_reg"); |
| 10308 | } |
| 10309 | #endif |
| 10310 | #ifndef PRODUCT |
| 10311 | void MoveL2D_stack_reg_partialNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 10312 | // Start at oper_input_base() and count operands |
| 10313 | unsigned idx0 = 1; |
| 10314 | unsigned idx1 = 1; // src |
| 10315 | st->print_raw("movlpd "); |
| 10316 | opnd_array(0)->int_format(ra, this, st); // dst |
| 10317 | st->print_raw(", "); |
| 10318 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 10319 | st->print_raw("\t# MoveL2D_stack_reg"); |
| 10320 | } |
| 10321 | #endif |
| 10322 | #ifndef PRODUCT |
| 10323 | void MoveL2D_stack_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 10324 | // Start at oper_input_base() and count operands |
| 10325 | unsigned idx0 = 1; |
| 10326 | unsigned idx1 = 1; // src |
| 10327 | st->print_raw("movsd "); |
| 10328 | opnd_array(0)->int_format(ra, this, st); // dst |
| 10329 | st->print_raw(", "); |
| 10330 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 10331 | st->print_raw("\t# MoveL2D_stack_reg"); |
| 10332 | } |
| 10333 | #endif |
| 10334 | #ifndef PRODUCT |
| 10335 | void MoveF2I_reg_stackNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 10336 | // Start at oper_input_base() and count operands |
| 10337 | unsigned idx0 = 1; |
| 10338 | unsigned idx1 = 1; // src |
| 10339 | st->print_raw("movss "); |
| 10340 | opnd_array(0)->int_format(ra, this, st); // dst |
| 10341 | st->print_raw(", "); |
| 10342 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 10343 | st->print_raw("\t# MoveF2I_reg_stack"); |
| 10344 | } |
| 10345 | #endif |
| 10346 | #ifndef PRODUCT |
| 10347 | void MoveI2F_reg_stackNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 10348 | // Start at oper_input_base() and count operands |
| 10349 | unsigned idx0 = 1; |
| 10350 | unsigned idx1 = 1; // src |
| 10351 | st->print_raw("movl "); |
| 10352 | opnd_array(0)->int_format(ra, this, st); // dst |
| 10353 | st->print_raw(", "); |
| 10354 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 10355 | st->print_raw("\t# MoveI2F_reg_stack"); |
| 10356 | } |
| 10357 | #endif |
| 10358 | #ifndef PRODUCT |
| 10359 | void MoveD2L_reg_stackNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 10360 | // Start at oper_input_base() and count operands |
| 10361 | unsigned idx0 = 1; |
| 10362 | unsigned idx1 = 1; // src |
| 10363 | st->print_raw("movsd "); |
| 10364 | opnd_array(0)->int_format(ra, this, st); // dst |
| 10365 | st->print_raw(", "); |
| 10366 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 10367 | st->print_raw("\t# MoveL2D_reg_stack"); |
| 10368 | } |
| 10369 | #endif |
| 10370 | #ifndef PRODUCT |
| 10371 | void MoveL2D_reg_stackNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 10372 | // Start at oper_input_base() and count operands |
| 10373 | unsigned idx0 = 1; |
| 10374 | unsigned idx1 = 1; // src |
| 10375 | st->print_raw("movq "); |
| 10376 | opnd_array(0)->int_format(ra, this, st); // dst |
| 10377 | st->print_raw(", "); |
| 10378 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 10379 | st->print_raw("\t# MoveL2D_reg_stack"); |
| 10380 | } |
| 10381 | #endif |
| 10382 | #ifndef PRODUCT |
| 10383 | void MoveF2I_reg_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 10384 | // Start at oper_input_base() and count operands |
| 10385 | unsigned idx0 = 1; |
| 10386 | unsigned idx1 = 1; // src |
| 10387 | st->print_raw("movd "); |
| 10388 | opnd_array(0)->int_format(ra, this, st); // dst |
| 10389 | st->print_raw(","); |
| 10390 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 10391 | st->print_raw("\t# MoveF2I"); |
| 10392 | } |
| 10393 | #endif |
| 10394 | #ifndef PRODUCT |
| 10395 | void MoveD2L_reg_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 10396 | // Start at oper_input_base() and count operands |
| 10397 | unsigned idx0 = 1; |
| 10398 | unsigned idx1 = 1; // src |
| 10399 | st->print_raw("movd "); |
| 10400 | opnd_array(0)->int_format(ra, this, st); // dst |
| 10401 | st->print_raw(","); |
| 10402 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 10403 | st->print_raw("\t# MoveD2L"); |
| 10404 | } |
| 10405 | #endif |
| 10406 | #ifndef PRODUCT |
| 10407 | void MoveI2F_reg_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 10408 | // Start at oper_input_base() and count operands |
| 10409 | unsigned idx0 = 1; |
| 10410 | unsigned idx1 = 1; // src |
| 10411 | st->print_raw("movd "); |
| 10412 | opnd_array(0)->int_format(ra, this, st); // dst |
| 10413 | st->print_raw(","); |
| 10414 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 10415 | st->print_raw("\t# MoveI2F"); |
| 10416 | } |
| 10417 | #endif |
| 10418 | #ifndef PRODUCT |
| 10419 | void MoveL2D_reg_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 10420 | // Start at oper_input_base() and count operands |
| 10421 | unsigned idx0 = 1; |
| 10422 | unsigned idx1 = 1; // src |
| 10423 | st->print_raw("movd "); |
| 10424 | opnd_array(0)->int_format(ra, this, st); // dst |
| 10425 | st->print_raw(","); |
| 10426 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 10427 | st->print_raw("\t# MoveL2D"); |
| 10428 | } |
| 10429 | #endif |
| 10430 | #ifndef PRODUCT |
| 10431 | void rep_stosNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 10432 | st->print_raw("xorq rax, rax\t# ClearArray:\n\t"); |
| 10433 | st->print_raw("cmp InitArrayShortSize,rcx\n\t"); |
| 10434 | st->print_raw("jg LARGE\n\t"); |
| 10435 | st->print_raw("dec rcx\n\t"); |
| 10436 | st->print_raw("js DONE\t# Zero length\n\t"); |
| 10437 | st->print_raw("mov rax,(rdi,rcx,8)\t# LOOP\n\t"); |
| 10438 | st->print_raw("dec rcx\n\t"); |
| 10439 | st->print_raw("jge LOOP\n\t"); |
| 10440 | st->print_raw("jmp DONE\n\t"); |
| 10441 | st->print_raw("# LARGE:\n\t"); |
| 10442 | if (UseFastStosb) { |
| 10443 | st->print_raw("shlq rcx,3\t# Convert doublewords to bytes\n\t"); |
| 10444 | st->print_raw("rep stosb\t# Store rax to *rdi++ while rcx--\n\t"); |
| 10445 | } else if (UseXMMForObjInit) { |
| 10446 | st->print_raw("mov rdi,rax\n\t"); |
| 10447 | st->print_raw("vpxor ymm0,ymm0,ymm0\n\t"); |
| 10448 | st->print_raw("jmpq L_zero_64_bytes\n\t"); |
| 10449 | st->print_raw("# L_loop:\t# 64-byte LOOP\n\t"); |
| 10450 | st->print_raw("vmovdqu ymm0,(rax)\n\t"); |
| 10451 | st->print_raw("vmovdqu ymm0,0x20(rax)\n\t"); |
| 10452 | st->print_raw("add 0x40,rax\n\t"); |
| 10453 | st->print_raw("# L_zero_64_bytes:\n\t"); |
| 10454 | st->print_raw("sub 0x8,rcx\n\t"); |
| 10455 | st->print_raw("jge L_loop\n\t"); |
| 10456 | st->print_raw("add 0x4,rcx\n\t"); |
| 10457 | st->print_raw("jl L_tail\n\t"); |
| 10458 | st->print_raw("vmovdqu ymm0,(rax)\n\t"); |
| 10459 | st->print_raw("add 0x20,rax\n\t"); |
| 10460 | st->print_raw("sub 0x4,rcx\n\t"); |
| 10461 | st->print_raw("# L_tail:\t# Clearing tail bytes\n\t"); |
| 10462 | st->print_raw("add 0x4,rcx\n\t"); |
| 10463 | st->print_raw("jle L_end\n\t"); |
| 10464 | st->print_raw("dec rcx\n\t"); |
| 10465 | st->print_raw("# L_sloop:\t# 8-byte short loop\n\t"); |
| 10466 | st->print_raw("vmovq xmm0,(rax)\n\t"); |
| 10467 | st->print_raw("add 0x8,rax\n\t"); |
| 10468 | st->print_raw("dec rcx\n\t"); |
| 10469 | st->print_raw("jge L_sloop\n\t"); |
| 10470 | st->print_raw("# L_end:\n\t"); |
| 10471 | } else { |
| 10472 | st->print_raw("rep stosq\t# Store rax to *rdi++ while rcx--\n\t"); |
| 10473 | } |
| 10474 | st->print_raw("# DONE"); |
| 10475 | } |
| 10476 | #endif |
| 10477 | #ifndef PRODUCT |
| 10478 | void rep_stos_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 10479 | st->print_raw("xorq rax, rax\t# ClearArray:\n\t"); |
| 10480 | st->print_raw("cmp InitArrayShortSize,rcx\n\t"); |
| 10481 | st->print_raw("jg LARGE\n\t"); |
| 10482 | st->print_raw("dec rcx\n\t"); |
| 10483 | st->print_raw("js DONE\t# Zero length\n\t"); |
| 10484 | st->print_raw("mov rax,(rdi,rcx,8)\t# LOOP\n\t"); |
| 10485 | st->print_raw("dec rcx\n\t"); |
| 10486 | st->print_raw("jge LOOP\n\t"); |
| 10487 | st->print_raw("jmp DONE\n\t"); |
| 10488 | st->print_raw("# LARGE:\n\t"); |
| 10489 | if (UseFastStosb) { |
| 10490 | st->print_raw("shlq rcx,3\t# Convert doublewords to bytes\n\t"); |
| 10491 | st->print_raw("rep stosb\t# Store rax to *rdi++ while rcx--\n\t"); |
| 10492 | } else if (UseXMMForObjInit) { |
| 10493 | st->print_raw("mov rdi,rax\n\t"); |
| 10494 | st->print_raw("vpxor ymm0,ymm0,ymm0\n\t"); |
| 10495 | st->print_raw("jmpq L_zero_64_bytes\n\t"); |
| 10496 | st->print_raw("# L_loop:\t# 64-byte LOOP\n\t"); |
| 10497 | st->print_raw("vmovdqu ymm0,(rax)\n\t"); |
| 10498 | st->print_raw("vmovdqu ymm0,0x20(rax)\n\t"); |
| 10499 | st->print_raw("add 0x40,rax\n\t"); |
| 10500 | st->print_raw("# L_zero_64_bytes:\n\t"); |
| 10501 | st->print_raw("sub 0x8,rcx\n\t"); |
| 10502 | st->print_raw("jge L_loop\n\t"); |
| 10503 | st->print_raw("add 0x4,rcx\n\t"); |
| 10504 | st->print_raw("jl L_tail\n\t"); |
| 10505 | st->print_raw("vmovdqu ymm0,(rax)\n\t"); |
| 10506 | st->print_raw("add 0x20,rax\n\t"); |
| 10507 | st->print_raw("sub 0x4,rcx\n\t"); |
| 10508 | st->print_raw("# L_tail:\t# Clearing tail bytes\n\t"); |
| 10509 | st->print_raw("add 0x4,rcx\n\t"); |
| 10510 | st->print_raw("jle L_end\n\t"); |
| 10511 | st->print_raw("dec rcx\n\t"); |
| 10512 | st->print_raw("# L_sloop:\t# 8-byte short loop\n\t"); |
| 10513 | st->print_raw("vmovq xmm0,(rax)\n\t"); |
| 10514 | st->print_raw("add 0x8,rax\n\t"); |
| 10515 | st->print_raw("dec rcx\n\t"); |
| 10516 | st->print_raw("jge L_sloop\n\t"); |
| 10517 | st->print_raw("# L_end:\n\t"); |
| 10518 | } else { |
| 10519 | st->print_raw("rep stosq\t# Store rax to *rdi++ while rcx--\n\t"); |
| 10520 | } |
| 10521 | st->print_raw("# DONE"); |
| 10522 | } |
| 10523 | #endif |
| 10524 | #ifndef PRODUCT |
| 10525 | void rep_stos_largeNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 10526 | if (UseFastStosb) { |
| 10527 | st->print_raw("xorq rax, rax\t# ClearArray:\n\t"); |
| 10528 | st->print_raw("shlq rcx,3\t# Convert doublewords to bytes\n\t"); |
| 10529 | st->print_raw("rep stosb\t# Store rax to *rdi++ while rcx--"); |
| 10530 | } else if (UseXMMForObjInit) { |
| 10531 | st->print_raw("mov rdi,rax\t# ClearArray:\n\t"); |
| 10532 | st->print_raw("vpxor ymm0,ymm0,ymm0\n\t"); |
| 10533 | st->print_raw("jmpq L_zero_64_bytes\n\t"); |
| 10534 | st->print_raw("# L_loop:\t# 64-byte LOOP\n\t"); |
| 10535 | st->print_raw("vmovdqu ymm0,(rax)\n\t"); |
| 10536 | st->print_raw("vmovdqu ymm0,0x20(rax)\n\t"); |
| 10537 | st->print_raw("add 0x40,rax\n\t"); |
| 10538 | st->print_raw("# L_zero_64_bytes:\n\t"); |
| 10539 | st->print_raw("sub 0x8,rcx\n\t"); |
| 10540 | st->print_raw("jge L_loop\n\t"); |
| 10541 | st->print_raw("add 0x4,rcx\n\t"); |
| 10542 | st->print_raw("jl L_tail\n\t"); |
| 10543 | st->print_raw("vmovdqu ymm0,(rax)\n\t"); |
| 10544 | st->print_raw("add 0x20,rax\n\t"); |
| 10545 | st->print_raw("sub 0x4,rcx\n\t"); |
| 10546 | st->print_raw("# L_tail:\t# Clearing tail bytes\n\t"); |
| 10547 | st->print_raw("add 0x4,rcx\n\t"); |
| 10548 | st->print_raw("jle L_end\n\t"); |
| 10549 | st->print_raw("dec rcx\n\t"); |
| 10550 | st->print_raw("# L_sloop:\t# 8-byte short loop\n\t"); |
| 10551 | st->print_raw("vmovq xmm0,(rax)\n\t"); |
| 10552 | st->print_raw("add 0x8,rax\n\t"); |
| 10553 | st->print_raw("dec rcx\n\t"); |
| 10554 | st->print_raw("jge L_sloop\n\t"); |
| 10555 | st->print_raw("# L_end:\n\t"); |
| 10556 | } else { |
| 10557 | st->print_raw("xorq rax, rax\t# ClearArray:\n\t"); |
| 10558 | st->print_raw("rep stosq\t# Store rax to *rdi++ while rcx--"); |
| 10559 | } |
| 10560 | } |
| 10561 | #endif |
| 10562 | #ifndef PRODUCT |
| 10563 | void rep_stos_large_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 10564 | if (UseFastStosb) { |
| 10565 | st->print_raw("xorq rax, rax\t# ClearArray:\n\t"); |
| 10566 | st->print_raw("shlq rcx,3\t# Convert doublewords to bytes\n\t"); |
| 10567 | st->print_raw("rep stosb\t# Store rax to *rdi++ while rcx--"); |
| 10568 | } else if (UseXMMForObjInit) { |
| 10569 | st->print_raw("mov rdi,rax\t# ClearArray:\n\t"); |
| 10570 | st->print_raw("vpxor ymm0,ymm0,ymm0\n\t"); |
| 10571 | st->print_raw("jmpq L_zero_64_bytes\n\t"); |
| 10572 | st->print_raw("# L_loop:\t# 64-byte LOOP\n\t"); |
| 10573 | st->print_raw("vmovdqu ymm0,(rax)\n\t"); |
| 10574 | st->print_raw("vmovdqu ymm0,0x20(rax)\n\t"); |
| 10575 | st->print_raw("add 0x40,rax\n\t"); |
| 10576 | st->print_raw("# L_zero_64_bytes:\n\t"); |
| 10577 | st->print_raw("sub 0x8,rcx\n\t"); |
| 10578 | st->print_raw("jge L_loop\n\t"); |
| 10579 | st->print_raw("add 0x4,rcx\n\t"); |
| 10580 | st->print_raw("jl L_tail\n\t"); |
| 10581 | st->print_raw("vmovdqu ymm0,(rax)\n\t"); |
| 10582 | st->print_raw("add 0x20,rax\n\t"); |
| 10583 | st->print_raw("sub 0x4,rcx\n\t"); |
| 10584 | st->print_raw("# L_tail:\t# Clearing tail bytes\n\t"); |
| 10585 | st->print_raw("add 0x4,rcx\n\t"); |
| 10586 | st->print_raw("jle L_end\n\t"); |
| 10587 | st->print_raw("dec rcx\n\t"); |
| 10588 | st->print_raw("# L_sloop:\t# 8-byte short loop\n\t"); |
| 10589 | st->print_raw("vmovq xmm0,(rax)\n\t"); |
| 10590 | st->print_raw("add 0x8,rax\n\t"); |
| 10591 | st->print_raw("dec rcx\n\t"); |
| 10592 | st->print_raw("jge L_sloop\n\t"); |
| 10593 | st->print_raw("# L_end:\n\t"); |
| 10594 | } else { |
| 10595 | st->print_raw("xorq rax, rax\t# ClearArray:\n\t"); |
| 10596 | st->print_raw("rep stosq\t# Store rax to *rdi++ while rcx--"); |
| 10597 | } |
| 10598 | } |
| 10599 | #endif |
| 10600 | #ifndef PRODUCT |
| 10601 | void rep_stos_imNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 10602 | // Start at oper_input_base() and count operands |
| 10603 | unsigned idx0 = 2; |
| 10604 | unsigned idx1 = 2; // cnt |
| 10605 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // base |
| 10606 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp |
| 10607 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // zero |
| 10608 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // ktmp |
| 10609 | st->print_raw("clear_mem_imm "); |
| 10610 | opnd_array(2)->ext_format(ra, this,idx2, st); // base |
| 10611 | st->print_raw(" , "); |
| 10612 | opnd_array(1)->ext_format(ra, this,idx1, st); // cnt |
| 10613 | st->print_raw(" \n\t"); |
| 10614 | } |
| 10615 | #endif |
| 10616 | #ifndef PRODUCT |
| 10617 | void string_compareLNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 10618 | // Start at oper_input_base() and count operands |
| 10619 | unsigned idx0 = 2; |
| 10620 | unsigned idx1 = 2; // str1 |
| 10621 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cnt1 |
| 10622 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // str2 |
| 10623 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // cnt2 |
| 10624 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp1 |
| 10625 | st->print_raw("String Compare byte[] "); |
| 10626 | opnd_array(1)->ext_format(ra, this,idx1, st); // str1 |
| 10627 | st->print_raw(","); |
| 10628 | opnd_array(2)->ext_format(ra, this,idx2, st); // cnt1 |
| 10629 | st->print_raw(","); |
| 10630 | opnd_array(3)->ext_format(ra, this,idx3, st); // str2 |
| 10631 | st->print_raw(","); |
| 10632 | opnd_array(4)->ext_format(ra, this,idx4, st); // cnt2 |
| 10633 | st->print_raw(" -> "); |
| 10634 | opnd_array(0)->int_format(ra, this, st); // result |
| 10635 | st->print_raw(" // KILL "); |
| 10636 | opnd_array(5)->ext_format(ra, this,idx5, st); // tmp1 |
| 10637 | } |
| 10638 | #endif |
| 10639 | #ifndef PRODUCT |
| 10640 | void string_compareL_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 10641 | // Start at oper_input_base() and count operands |
| 10642 | unsigned idx0 = 2; |
| 10643 | unsigned idx1 = 2; // str1 |
| 10644 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cnt1 |
| 10645 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // str2 |
| 10646 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // cnt2 |
| 10647 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp1 |
| 10648 | unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // ktmp |
| 10649 | st->print_raw("String Compare byte[] "); |
| 10650 | opnd_array(1)->ext_format(ra, this,idx1, st); // str1 |
| 10651 | st->print_raw(","); |
| 10652 | opnd_array(2)->ext_format(ra, this,idx2, st); // cnt1 |
| 10653 | st->print_raw(","); |
| 10654 | opnd_array(3)->ext_format(ra, this,idx3, st); // str2 |
| 10655 | st->print_raw(","); |
| 10656 | opnd_array(4)->ext_format(ra, this,idx4, st); // cnt2 |
| 10657 | st->print_raw(" -> "); |
| 10658 | opnd_array(0)->int_format(ra, this, st); // result |
| 10659 | st->print_raw(" // KILL "); |
| 10660 | opnd_array(5)->ext_format(ra, this,idx5, st); // tmp1 |
| 10661 | } |
| 10662 | #endif |
| 10663 | #ifndef PRODUCT |
| 10664 | void string_compareUNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 10665 | // Start at oper_input_base() and count operands |
| 10666 | unsigned idx0 = 2; |
| 10667 | unsigned idx1 = 2; // str1 |
| 10668 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cnt1 |
| 10669 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // str2 |
| 10670 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // cnt2 |
| 10671 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp1 |
| 10672 | st->print_raw("String Compare char[] "); |
| 10673 | opnd_array(1)->ext_format(ra, this,idx1, st); // str1 |
| 10674 | st->print_raw(","); |
| 10675 | opnd_array(2)->ext_format(ra, this,idx2, st); // cnt1 |
| 10676 | st->print_raw(","); |
| 10677 | opnd_array(3)->ext_format(ra, this,idx3, st); // str2 |
| 10678 | st->print_raw(","); |
| 10679 | opnd_array(4)->ext_format(ra, this,idx4, st); // cnt2 |
| 10680 | st->print_raw(" -> "); |
| 10681 | opnd_array(0)->int_format(ra, this, st); // result |
| 10682 | st->print_raw(" // KILL "); |
| 10683 | opnd_array(5)->ext_format(ra, this,idx5, st); // tmp1 |
| 10684 | } |
| 10685 | #endif |
| 10686 | #ifndef PRODUCT |
| 10687 | void string_compareU_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 10688 | // Start at oper_input_base() and count operands |
| 10689 | unsigned idx0 = 2; |
| 10690 | unsigned idx1 = 2; // str1 |
| 10691 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cnt1 |
| 10692 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // str2 |
| 10693 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // cnt2 |
| 10694 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp1 |
| 10695 | unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // ktmp |
| 10696 | st->print_raw("String Compare char[] "); |
| 10697 | opnd_array(1)->ext_format(ra, this,idx1, st); // str1 |
| 10698 | st->print_raw(","); |
| 10699 | opnd_array(2)->ext_format(ra, this,idx2, st); // cnt1 |
| 10700 | st->print_raw(","); |
| 10701 | opnd_array(3)->ext_format(ra, this,idx3, st); // str2 |
| 10702 | st->print_raw(","); |
| 10703 | opnd_array(4)->ext_format(ra, this,idx4, st); // cnt2 |
| 10704 | st->print_raw(" -> "); |
| 10705 | opnd_array(0)->int_format(ra, this, st); // result |
| 10706 | st->print_raw(" // KILL "); |
| 10707 | opnd_array(5)->ext_format(ra, this,idx5, st); // tmp1 |
| 10708 | } |
| 10709 | #endif |
| 10710 | #ifndef PRODUCT |
| 10711 | void string_compareLUNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 10712 | // Start at oper_input_base() and count operands |
| 10713 | unsigned idx0 = 2; |
| 10714 | unsigned idx1 = 2; // str1 |
| 10715 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cnt1 |
| 10716 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // str2 |
| 10717 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // cnt2 |
| 10718 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp1 |
| 10719 | st->print_raw("String Compare byte[] "); |
| 10720 | opnd_array(1)->ext_format(ra, this,idx1, st); // str1 |
| 10721 | st->print_raw(","); |
| 10722 | opnd_array(2)->ext_format(ra, this,idx2, st); // cnt1 |
| 10723 | st->print_raw(","); |
| 10724 | opnd_array(3)->ext_format(ra, this,idx3, st); // str2 |
| 10725 | st->print_raw(","); |
| 10726 | opnd_array(4)->ext_format(ra, this,idx4, st); // cnt2 |
| 10727 | st->print_raw(" -> "); |
| 10728 | opnd_array(0)->int_format(ra, this, st); // result |
| 10729 | st->print_raw(" // KILL "); |
| 10730 | opnd_array(5)->ext_format(ra, this,idx5, st); // tmp1 |
| 10731 | } |
| 10732 | #endif |
| 10733 | #ifndef PRODUCT |
| 10734 | void string_compareLU_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 10735 | // Start at oper_input_base() and count operands |
| 10736 | unsigned idx0 = 2; |
| 10737 | unsigned idx1 = 2; // str1 |
| 10738 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cnt1 |
| 10739 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // str2 |
| 10740 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // cnt2 |
| 10741 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp1 |
| 10742 | unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // ktmp |
| 10743 | st->print_raw("String Compare byte[] "); |
| 10744 | opnd_array(1)->ext_format(ra, this,idx1, st); // str1 |
| 10745 | st->print_raw(","); |
| 10746 | opnd_array(2)->ext_format(ra, this,idx2, st); // cnt1 |
| 10747 | st->print_raw(","); |
| 10748 | opnd_array(3)->ext_format(ra, this,idx3, st); // str2 |
| 10749 | st->print_raw(","); |
| 10750 | opnd_array(4)->ext_format(ra, this,idx4, st); // cnt2 |
| 10751 | st->print_raw(" -> "); |
| 10752 | opnd_array(0)->int_format(ra, this, st); // result |
| 10753 | st->print_raw(" // KILL "); |
| 10754 | opnd_array(5)->ext_format(ra, this,idx5, st); // tmp1 |
| 10755 | } |
| 10756 | #endif |
| 10757 | #ifndef PRODUCT |
| 10758 | void string_compareULNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 10759 | // Start at oper_input_base() and count operands |
| 10760 | unsigned idx0 = 2; |
| 10761 | unsigned idx1 = 2; // str1 |
| 10762 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cnt1 |
| 10763 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // str2 |
| 10764 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // cnt2 |
| 10765 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp1 |
| 10766 | st->print_raw("String Compare byte[] "); |
| 10767 | opnd_array(1)->ext_format(ra, this,idx1, st); // str1 |
| 10768 | st->print_raw(","); |
| 10769 | opnd_array(2)->ext_format(ra, this,idx2, st); // cnt1 |
| 10770 | st->print_raw(","); |
| 10771 | opnd_array(3)->ext_format(ra, this,idx3, st); // str2 |
| 10772 | st->print_raw(","); |
| 10773 | opnd_array(4)->ext_format(ra, this,idx4, st); // cnt2 |
| 10774 | st->print_raw(" -> "); |
| 10775 | opnd_array(0)->int_format(ra, this, st); // result |
| 10776 | st->print_raw(" // KILL "); |
| 10777 | opnd_array(5)->ext_format(ra, this,idx5, st); // tmp1 |
| 10778 | } |
| 10779 | #endif |
| 10780 | #ifndef PRODUCT |
| 10781 | void string_compareUL_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 10782 | // Start at oper_input_base() and count operands |
| 10783 | unsigned idx0 = 2; |
| 10784 | unsigned idx1 = 2; // str1 |
| 10785 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cnt1 |
| 10786 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // str2 |
| 10787 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // cnt2 |
| 10788 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp1 |
| 10789 | unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // ktmp |
| 10790 | st->print_raw("String Compare byte[] "); |
| 10791 | opnd_array(1)->ext_format(ra, this,idx1, st); // str1 |
| 10792 | st->print_raw(","); |
| 10793 | opnd_array(2)->ext_format(ra, this,idx2, st); // cnt1 |
| 10794 | st->print_raw(","); |
| 10795 | opnd_array(3)->ext_format(ra, this,idx3, st); // str2 |
| 10796 | st->print_raw(","); |
| 10797 | opnd_array(4)->ext_format(ra, this,idx4, st); // cnt2 |
| 10798 | st->print_raw(" -> "); |
| 10799 | opnd_array(0)->int_format(ra, this, st); // result |
| 10800 | st->print_raw(" // KILL "); |
| 10801 | opnd_array(5)->ext_format(ra, this,idx5, st); // tmp1 |
| 10802 | } |
| 10803 | #endif |
| 10804 | #ifndef PRODUCT |
| 10805 | void string_indexof_conLNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 10806 | // Start at oper_input_base() and count operands |
| 10807 | unsigned idx0 = 2; |
| 10808 | unsigned idx1 = 2; // str1 |
| 10809 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cnt1 |
| 10810 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // str2 |
| 10811 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // int_cnt2 |
| 10812 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp_vec |
| 10813 | st->print_raw("String IndexOf byte[] "); |
| 10814 | opnd_array(1)->ext_format(ra, this,idx1, st); // str1 |
| 10815 | st->print_raw(","); |
| 10816 | opnd_array(2)->ext_format(ra, this,idx2, st); // cnt1 |
| 10817 | st->print_raw(","); |
| 10818 | opnd_array(3)->ext_format(ra, this,idx3, st); // str2 |
| 10819 | st->print_raw(","); |
| 10820 | opnd_array(4)->ext_format(ra, this,idx4, st); // int_cnt2 |
| 10821 | st->print_raw(" -> "); |
| 10822 | opnd_array(0)->int_format(ra, this, st); // result |
| 10823 | st->print_raw(" // KILL "); |
| 10824 | opnd_array(5)->ext_format(ra, this,idx5, st); // tmp_vec |
| 10825 | st->print_raw(", "); |
| 10826 | opnd_array(2)->ext_format(ra, this,idx2, st); // cnt1 |
| 10827 | st->print_raw(", "); |
| 10828 | st->print_raw("RAX"); |
| 10829 | st->print_raw(", "); |
| 10830 | st->print_raw("RCX"); |
| 10831 | } |
| 10832 | #endif |
| 10833 | #ifndef PRODUCT |
| 10834 | void string_indexof_conUNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 10835 | // Start at oper_input_base() and count operands |
| 10836 | unsigned idx0 = 2; |
| 10837 | unsigned idx1 = 2; // str1 |
| 10838 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cnt1 |
| 10839 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // str2 |
| 10840 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // int_cnt2 |
| 10841 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp_vec |
| 10842 | st->print_raw("String IndexOf char[] "); |
| 10843 | opnd_array(1)->ext_format(ra, this,idx1, st); // str1 |
| 10844 | st->print_raw(","); |
| 10845 | opnd_array(2)->ext_format(ra, this,idx2, st); // cnt1 |
| 10846 | st->print_raw(","); |
| 10847 | opnd_array(3)->ext_format(ra, this,idx3, st); // str2 |
| 10848 | st->print_raw(","); |
| 10849 | opnd_array(4)->ext_format(ra, this,idx4, st); // int_cnt2 |
| 10850 | st->print_raw(" -> "); |
| 10851 | opnd_array(0)->int_format(ra, this, st); // result |
| 10852 | st->print_raw(" // KILL "); |
| 10853 | opnd_array(5)->ext_format(ra, this,idx5, st); // tmp_vec |
| 10854 | st->print_raw(", "); |
| 10855 | opnd_array(2)->ext_format(ra, this,idx2, st); // cnt1 |
| 10856 | st->print_raw(", "); |
| 10857 | st->print_raw("RAX"); |
| 10858 | st->print_raw(", "); |
| 10859 | st->print_raw("RCX"); |
| 10860 | } |
| 10861 | #endif |
| 10862 | #ifndef PRODUCT |
| 10863 | void string_indexof_conULNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 10864 | // Start at oper_input_base() and count operands |
| 10865 | unsigned idx0 = 2; |
| 10866 | unsigned idx1 = 2; // str1 |
| 10867 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cnt1 |
| 10868 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // str2 |
| 10869 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // int_cnt2 |
| 10870 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp_vec |
| 10871 | st->print_raw("String IndexOf char[] "); |
| 10872 | opnd_array(1)->ext_format(ra, this,idx1, st); // str1 |
| 10873 | st->print_raw(","); |
| 10874 | opnd_array(2)->ext_format(ra, this,idx2, st); // cnt1 |
| 10875 | st->print_raw(","); |
| 10876 | opnd_array(3)->ext_format(ra, this,idx3, st); // str2 |
| 10877 | st->print_raw(","); |
| 10878 | opnd_array(4)->ext_format(ra, this,idx4, st); // int_cnt2 |
| 10879 | st->print_raw(" -> "); |
| 10880 | opnd_array(0)->int_format(ra, this, st); // result |
| 10881 | st->print_raw(" // KILL "); |
| 10882 | opnd_array(5)->ext_format(ra, this,idx5, st); // tmp_vec |
| 10883 | st->print_raw(", "); |
| 10884 | opnd_array(2)->ext_format(ra, this,idx2, st); // cnt1 |
| 10885 | st->print_raw(", "); |
| 10886 | st->print_raw("RAX"); |
| 10887 | st->print_raw(", "); |
| 10888 | st->print_raw("RCX"); |
| 10889 | } |
| 10890 | #endif |
| 10891 | #ifndef PRODUCT |
| 10892 | void string_indexofLNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 10893 | // Start at oper_input_base() and count operands |
| 10894 | unsigned idx0 = 2; |
| 10895 | unsigned idx1 = 2; // str1 |
| 10896 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cnt1 |
| 10897 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // str2 |
| 10898 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // cnt2 |
| 10899 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp_vec |
| 10900 | st->print_raw("String IndexOf byte[] "); |
| 10901 | opnd_array(1)->ext_format(ra, this,idx1, st); // str1 |
| 10902 | st->print_raw(","); |
| 10903 | opnd_array(2)->ext_format(ra, this,idx2, st); // cnt1 |
| 10904 | st->print_raw(","); |
| 10905 | opnd_array(3)->ext_format(ra, this,idx3, st); // str2 |
| 10906 | st->print_raw(","); |
| 10907 | opnd_array(4)->ext_format(ra, this,idx4, st); // cnt2 |
| 10908 | st->print_raw(" -> "); |
| 10909 | opnd_array(0)->int_format(ra, this, st); // result |
| 10910 | st->print_raw(" // KILL all"); |
| 10911 | } |
| 10912 | #endif |
| 10913 | #ifndef PRODUCT |
| 10914 | void string_indexofUNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 10915 | // Start at oper_input_base() and count operands |
| 10916 | unsigned idx0 = 2; |
| 10917 | unsigned idx1 = 2; // str1 |
| 10918 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cnt1 |
| 10919 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // str2 |
| 10920 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // cnt2 |
| 10921 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp_vec |
Value stored to 'idx5' during its initialization is never read | |
| 10922 | st->print_raw("String IndexOf char[] "); |
| 10923 | opnd_array(1)->ext_format(ra, this,idx1, st); // str1 |
| 10924 | st->print_raw(","); |
| 10925 | opnd_array(2)->ext_format(ra, this,idx2, st); // cnt1 |
| 10926 | st->print_raw(","); |
| 10927 | opnd_array(3)->ext_format(ra, this,idx3, st); // str2 |
| 10928 | st->print_raw(","); |
| 10929 | opnd_array(4)->ext_format(ra, this,idx4, st); // cnt2 |
| 10930 | st->print_raw(" -> "); |
| 10931 | opnd_array(0)->int_format(ra, this, st); // result |
| 10932 | st->print_raw(" // KILL all"); |
| 10933 | } |
| 10934 | #endif |
| 10935 | #ifndef PRODUCT |
| 10936 | void string_indexofULNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 10937 | // Start at oper_input_base() and count operands |
| 10938 | unsigned idx0 = 2; |
| 10939 | unsigned idx1 = 2; // str1 |
| 10940 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cnt1 |
| 10941 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // str2 |
| 10942 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // cnt2 |
| 10943 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp_vec |
| 10944 | st->print_raw("String IndexOf char[] "); |
| 10945 | opnd_array(1)->ext_format(ra, this,idx1, st); // str1 |
| 10946 | st->print_raw(","); |
| 10947 | opnd_array(2)->ext_format(ra, this,idx2, st); // cnt1 |
| 10948 | st->print_raw(","); |
| 10949 | opnd_array(3)->ext_format(ra, this,idx3, st); // str2 |
| 10950 | st->print_raw(","); |
| 10951 | opnd_array(4)->ext_format(ra, this,idx4, st); // cnt2 |
| 10952 | st->print_raw(" -> "); |
| 10953 | opnd_array(0)->int_format(ra, this, st); // result |
| 10954 | st->print_raw(" // KILL all"); |
| 10955 | } |
| 10956 | #endif |
| 10957 | #ifndef PRODUCT |
| 10958 | void string_indexof_charNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 10959 | // Start at oper_input_base() and count operands |
| 10960 | unsigned idx0 = 2; |
| 10961 | unsigned idx1 = 2; // str1 |
| 10962 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cnt1 |
| 10963 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // ch |
| 10964 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp_vec1 |
| 10965 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp_vec2 |
| 10966 | unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // tmp_vec3 |
| 10967 | unsigned idx7 = idx6 + opnd_array(6)->num_edges(); // tmp |
| 10968 | st->print_raw("StringUTF16 IndexOf char[] "); |
| 10969 | opnd_array(1)->ext_format(ra, this,idx1, st); // str1 |
| 10970 | st->print_raw(","); |
| 10971 | opnd_array(2)->ext_format(ra, this,idx2, st); // cnt1 |
| 10972 | st->print_raw(","); |
| 10973 | opnd_array(3)->ext_format(ra, this,idx3, st); // ch |
| 10974 | st->print_raw(" -> "); |
| 10975 | opnd_array(0)->int_format(ra, this, st); // result |
| 10976 | st->print_raw(" // KILL all"); |
| 10977 | } |
| 10978 | #endif |
| 10979 | #ifndef PRODUCT |
| 10980 | void stringL_indexof_charNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 10981 | // Start at oper_input_base() and count operands |
| 10982 | unsigned idx0 = 2; |
| 10983 | unsigned idx1 = 2; // str1 |
| 10984 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cnt1 |
| 10985 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // ch |
| 10986 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp_vec1 |
| 10987 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp_vec2 |
| 10988 | unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // tmp_vec3 |
| 10989 | unsigned idx7 = idx6 + opnd_array(6)->num_edges(); // tmp |
| 10990 | st->print_raw("StringLatin1 IndexOf char[] "); |
| 10991 | opnd_array(1)->ext_format(ra, this,idx1, st); // str1 |
| 10992 | st->print_raw(","); |
| 10993 | opnd_array(2)->ext_format(ra, this,idx2, st); // cnt1 |
| 10994 | st->print_raw(","); |
| 10995 | opnd_array(3)->ext_format(ra, this,idx3, st); // ch |
| 10996 | st->print_raw(" -> "); |
| 10997 | opnd_array(0)->int_format(ra, this, st); // result |
| 10998 | st->print_raw(" // KILL all"); |
| 10999 | } |
| 11000 | #endif |
| 11001 | #ifndef PRODUCT |
| 11002 | void string_equalsNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11003 | // Start at oper_input_base() and count operands |
| 11004 | unsigned idx0 = 2; |
| 11005 | unsigned idx1 = 2; // str1 |
| 11006 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // str2 |
| 11007 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // cnt |
| 11008 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1 |
| 11009 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2 |
| 11010 | st->print_raw("String Equals "); |
| 11011 | opnd_array(1)->ext_format(ra, this,idx1, st); // str1 |
| 11012 | st->print_raw(","); |
| 11013 | opnd_array(2)->ext_format(ra, this,idx2, st); // str2 |
| 11014 | st->print_raw(","); |
| 11015 | opnd_array(3)->ext_format(ra, this,idx3, st); // cnt |
| 11016 | st->print_raw(" -> "); |
| 11017 | opnd_array(0)->int_format(ra, this, st); // result |
| 11018 | st->print_raw(" // KILL "); |
| 11019 | opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1 |
| 11020 | st->print_raw(", "); |
| 11021 | opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2 |
| 11022 | st->print_raw(", "); |
| 11023 | st->print_raw("RBX"); |
| 11024 | } |
| 11025 | #endif |
| 11026 | #ifndef PRODUCT |
| 11027 | void string_equals_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11028 | // Start at oper_input_base() and count operands |
| 11029 | unsigned idx0 = 2; |
| 11030 | unsigned idx1 = 2; // str1 |
| 11031 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // str2 |
| 11032 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // cnt |
| 11033 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1 |
| 11034 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2 |
| 11035 | unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // ktmp |
| 11036 | st->print_raw("String Equals "); |
| 11037 | opnd_array(1)->ext_format(ra, this,idx1, st); // str1 |
| 11038 | st->print_raw(","); |
| 11039 | opnd_array(2)->ext_format(ra, this,idx2, st); // str2 |
| 11040 | st->print_raw(","); |
| 11041 | opnd_array(3)->ext_format(ra, this,idx3, st); // cnt |
| 11042 | st->print_raw(" -> "); |
| 11043 | opnd_array(0)->int_format(ra, this, st); // result |
| 11044 | st->print_raw(" // KILL "); |
| 11045 | opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1 |
| 11046 | st->print_raw(", "); |
| 11047 | opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2 |
| 11048 | st->print_raw(", "); |
| 11049 | st->print_raw("RBX"); |
| 11050 | } |
| 11051 | #endif |
| 11052 | #ifndef PRODUCT |
| 11053 | void array_equalsBNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11054 | // Start at oper_input_base() and count operands |
| 11055 | unsigned idx0 = 2; |
| 11056 | unsigned idx1 = 2; // ary1 |
| 11057 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // ary2 |
| 11058 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp1 |
| 11059 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2 |
| 11060 | st->print_raw("Array Equals byte[] "); |
| 11061 | opnd_array(1)->ext_format(ra, this,idx1, st); // ary1 |
| 11062 | st->print_raw(","); |
| 11063 | opnd_array(2)->ext_format(ra, this,idx2, st); // ary2 |
| 11064 | st->print_raw(" -> "); |
| 11065 | opnd_array(0)->int_format(ra, this, st); // result |
| 11066 | st->print_raw(" // KILL "); |
| 11067 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp1 |
| 11068 | st->print_raw(", "); |
| 11069 | opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2 |
| 11070 | st->print_raw(", "); |
| 11071 | st->print_raw("RCX"); |
| 11072 | st->print_raw(", "); |
| 11073 | st->print_raw("RBX"); |
| 11074 | } |
| 11075 | #endif |
| 11076 | #ifndef PRODUCT |
| 11077 | void array_equalsB_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11078 | // Start at oper_input_base() and count operands |
| 11079 | unsigned idx0 = 2; |
| 11080 | unsigned idx1 = 2; // ary1 |
| 11081 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // ary2 |
| 11082 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp1 |
| 11083 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2 |
| 11084 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // ktmp |
| 11085 | st->print_raw("Array Equals byte[] "); |
| 11086 | opnd_array(1)->ext_format(ra, this,idx1, st); // ary1 |
| 11087 | st->print_raw(","); |
| 11088 | opnd_array(2)->ext_format(ra, this,idx2, st); // ary2 |
| 11089 | st->print_raw(" -> "); |
| 11090 | opnd_array(0)->int_format(ra, this, st); // result |
| 11091 | st->print_raw(" // KILL "); |
| 11092 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp1 |
| 11093 | st->print_raw(", "); |
| 11094 | opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2 |
| 11095 | st->print_raw(", "); |
| 11096 | st->print_raw("RCX"); |
| 11097 | st->print_raw(", "); |
| 11098 | st->print_raw("RBX"); |
| 11099 | } |
| 11100 | #endif |
| 11101 | #ifndef PRODUCT |
| 11102 | void array_equalsCNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11103 | // Start at oper_input_base() and count operands |
| 11104 | unsigned idx0 = 2; |
| 11105 | unsigned idx1 = 2; // ary1 |
| 11106 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // ary2 |
| 11107 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp1 |
| 11108 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2 |
| 11109 | st->print_raw("Array Equals char[] "); |
| 11110 | opnd_array(1)->ext_format(ra, this,idx1, st); // ary1 |
| 11111 | st->print_raw(","); |
| 11112 | opnd_array(2)->ext_format(ra, this,idx2, st); // ary2 |
| 11113 | st->print_raw(" -> "); |
| 11114 | opnd_array(0)->int_format(ra, this, st); // result |
| 11115 | st->print_raw(" // KILL "); |
| 11116 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp1 |
| 11117 | st->print_raw(", "); |
| 11118 | opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2 |
| 11119 | st->print_raw(", "); |
| 11120 | st->print_raw("RCX"); |
| 11121 | st->print_raw(", "); |
| 11122 | st->print_raw("RBX"); |
| 11123 | } |
| 11124 | #endif |
| 11125 | #ifndef PRODUCT |
| 11126 | void array_equalsC_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11127 | // Start at oper_input_base() and count operands |
| 11128 | unsigned idx0 = 2; |
| 11129 | unsigned idx1 = 2; // ary1 |
| 11130 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // ary2 |
| 11131 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp1 |
| 11132 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2 |
| 11133 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // ktmp |
| 11134 | st->print_raw("Array Equals char[] "); |
| 11135 | opnd_array(1)->ext_format(ra, this,idx1, st); // ary1 |
| 11136 | st->print_raw(","); |
| 11137 | opnd_array(2)->ext_format(ra, this,idx2, st); // ary2 |
| 11138 | st->print_raw(" -> "); |
| 11139 | opnd_array(0)->int_format(ra, this, st); // result |
| 11140 | st->print_raw(" // KILL "); |
| 11141 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp1 |
| 11142 | st->print_raw(", "); |
| 11143 | opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2 |
| 11144 | st->print_raw(", "); |
| 11145 | st->print_raw("RCX"); |
| 11146 | st->print_raw(", "); |
| 11147 | st->print_raw("RBX"); |
| 11148 | } |
| 11149 | #endif |
| 11150 | #ifndef PRODUCT |
| 11151 | void has_negativesNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11152 | // Start at oper_input_base() and count operands |
| 11153 | unsigned idx0 = 2; |
| 11154 | unsigned idx1 = 2; // ary1 |
| 11155 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // len |
| 11156 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp1 |
| 11157 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2 |
| 11158 | st->print_raw("has negatives byte[] "); |
| 11159 | opnd_array(1)->ext_format(ra, this,idx1, st); // ary1 |
| 11160 | st->print_raw(","); |
| 11161 | opnd_array(2)->ext_format(ra, this,idx2, st); // len |
| 11162 | st->print_raw(" -> "); |
| 11163 | opnd_array(0)->int_format(ra, this, st); // result |
| 11164 | st->print_raw(" // KILL "); |
| 11165 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp1 |
| 11166 | st->print_raw(", "); |
| 11167 | opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2 |
| 11168 | st->print_raw(", "); |
| 11169 | st->print_raw("RBX"); |
| 11170 | } |
| 11171 | #endif |
| 11172 | #ifndef PRODUCT |
| 11173 | void has_negatives_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11174 | // Start at oper_input_base() and count operands |
| 11175 | unsigned idx0 = 2; |
| 11176 | unsigned idx1 = 2; // ary1 |
| 11177 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // len |
| 11178 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp1 |
| 11179 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2 |
| 11180 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // ktmp1 |
| 11181 | unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // ktmp2 |
| 11182 | st->print_raw("has negatives byte[] "); |
| 11183 | opnd_array(1)->ext_format(ra, this,idx1, st); // ary1 |
| 11184 | st->print_raw(","); |
| 11185 | opnd_array(2)->ext_format(ra, this,idx2, st); // len |
| 11186 | st->print_raw(" -> "); |
| 11187 | opnd_array(0)->int_format(ra, this, st); // result |
| 11188 | st->print_raw(" // KILL "); |
| 11189 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp1 |
| 11190 | st->print_raw(", "); |
| 11191 | opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2 |
| 11192 | st->print_raw(", "); |
| 11193 | st->print_raw("RBX"); |
| 11194 | } |
| 11195 | #endif |
| 11196 | #ifndef PRODUCT |
| 11197 | void string_compressNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11198 | // Start at oper_input_base() and count operands |
| 11199 | unsigned idx0 = 2; |
| 11200 | unsigned idx1 = 2; // src |
| 11201 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst |
| 11202 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // len |
| 11203 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1 |
| 11204 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2 |
| 11205 | unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // tmp3 |
| 11206 | unsigned idx7 = idx6 + opnd_array(6)->num_edges(); // tmp4 |
| 11207 | st->print_raw("String Compress "); |
| 11208 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 11209 | st->print_raw(","); |
| 11210 | opnd_array(2)->ext_format(ra, this,idx2, st); // dst |
| 11211 | st->print_raw(" -> "); |
| 11212 | opnd_array(0)->int_format(ra, this, st); // result |
| 11213 | st->print_raw(" // KILL RAX, RCX, RDX"); |
| 11214 | } |
| 11215 | #endif |
| 11216 | #ifndef PRODUCT |
| 11217 | void string_compress_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11218 | // Start at oper_input_base() and count operands |
| 11219 | unsigned idx0 = 2; |
| 11220 | unsigned idx1 = 2; // src |
| 11221 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst |
| 11222 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // len |
| 11223 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1 |
| 11224 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2 |
| 11225 | unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // tmp3 |
| 11226 | unsigned idx7 = idx6 + opnd_array(6)->num_edges(); // tmp4 |
| 11227 | unsigned idx8 = idx7 + opnd_array(7)->num_edges(); // ktmp1 |
| 11228 | unsigned idx9 = idx8 + opnd_array(8)->num_edges(); // ktmp2 |
| 11229 | st->print_raw("String Compress "); |
| 11230 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 11231 | st->print_raw(","); |
| 11232 | opnd_array(2)->ext_format(ra, this,idx2, st); // dst |
| 11233 | st->print_raw(" -> "); |
| 11234 | opnd_array(0)->int_format(ra, this, st); // result |
| 11235 | st->print_raw(" // KILL RAX, RCX, RDX"); |
| 11236 | } |
| 11237 | #endif |
| 11238 | #ifndef PRODUCT |
| 11239 | void string_inflateNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11240 | // Start at oper_input_base() and count operands |
| 11241 | unsigned idx0 = 2; |
| 11242 | unsigned idx1 = 2; // src |
| 11243 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst |
| 11244 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // len |
| 11245 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1 |
| 11246 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2 |
| 11247 | st->print_raw("String Inflate "); |
| 11248 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 11249 | st->print_raw(","); |
| 11250 | opnd_array(2)->ext_format(ra, this,idx2, st); // dst |
| 11251 | st->print_raw(" // KILL "); |
| 11252 | opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1 |
| 11253 | st->print_raw(", "); |
| 11254 | opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2 |
| 11255 | } |
| 11256 | #endif |
| 11257 | #ifndef PRODUCT |
| 11258 | void string_inflate_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11259 | // Start at oper_input_base() and count operands |
| 11260 | unsigned idx0 = 2; |
| 11261 | unsigned idx1 = 2; // src |
| 11262 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst |
| 11263 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // len |
| 11264 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1 |
| 11265 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // ktmp |
| 11266 | unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // tmp2 |
| 11267 | st->print_raw("String Inflate "); |
| 11268 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 11269 | st->print_raw(","); |
| 11270 | opnd_array(2)->ext_format(ra, this,idx2, st); // dst |
| 11271 | st->print_raw(" // KILL "); |
| 11272 | opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1 |
| 11273 | st->print_raw(", "); |
| 11274 | opnd_array(6)->ext_format(ra, this,idx6, st); // tmp2 |
| 11275 | } |
| 11276 | #endif |
| 11277 | #ifndef PRODUCT |
| 11278 | void encode_iso_arrayNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11279 | // Start at oper_input_base() and count operands |
| 11280 | unsigned idx0 = 2; |
| 11281 | unsigned idx1 = 2; // src |
| 11282 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst |
| 11283 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // len |
| 11284 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1 |
| 11285 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2 |
| 11286 | unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // tmp3 |
| 11287 | unsigned idx7 = idx6 + opnd_array(6)->num_edges(); // tmp4 |
| 11288 | st->print_raw("Encode iso array "); |
| 11289 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 11290 | st->print_raw(","); |
| 11291 | opnd_array(2)->ext_format(ra, this,idx2, st); // dst |
| 11292 | st->print_raw(","); |
| 11293 | opnd_array(3)->ext_format(ra, this,idx3, st); // len |
| 11294 | st->print_raw(" -> "); |
| 11295 | opnd_array(0)->int_format(ra, this, st); // result |
| 11296 | st->print_raw(" // KILL RCX, RDX, "); |
| 11297 | opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1 |
| 11298 | st->print_raw(", "); |
| 11299 | opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2 |
| 11300 | st->print_raw(", "); |
| 11301 | opnd_array(6)->ext_format(ra, this,idx6, st); // tmp3 |
| 11302 | st->print_raw(", "); |
| 11303 | opnd_array(7)->ext_format(ra, this,idx7, st); // tmp4 |
| 11304 | st->print_raw(", RSI, RDI "); |
| 11305 | } |
| 11306 | #endif |
| 11307 | #ifndef PRODUCT |
| 11308 | void encode_ascii_arrayNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11309 | // Start at oper_input_base() and count operands |
| 11310 | unsigned idx0 = 2; |
| 11311 | unsigned idx1 = 2; // src |
| 11312 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst |
| 11313 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // len |
| 11314 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1 |
| 11315 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2 |
| 11316 | unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // tmp3 |
| 11317 | unsigned idx7 = idx6 + opnd_array(6)->num_edges(); // tmp4 |
| 11318 | st->print_raw("Encode ascii array "); |
| 11319 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 11320 | st->print_raw(","); |
| 11321 | opnd_array(2)->ext_format(ra, this,idx2, st); // dst |
| 11322 | st->print_raw(","); |
| 11323 | opnd_array(3)->ext_format(ra, this,idx3, st); // len |
| 11324 | st->print_raw(" -> "); |
| 11325 | opnd_array(0)->int_format(ra, this, st); // result |
| 11326 | st->print_raw(" // KILL RCX, RDX, "); |
| 11327 | opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1 |
| 11328 | st->print_raw(", "); |
| 11329 | opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2 |
| 11330 | st->print_raw(", "); |
| 11331 | opnd_array(6)->ext_format(ra, this,idx6, st); // tmp3 |
| 11332 | st->print_raw(", "); |
| 11333 | opnd_array(7)->ext_format(ra, this,idx7, st); // tmp4 |
| 11334 | st->print_raw(", RSI, RDI "); |
| 11335 | } |
| 11336 | #endif |
| 11337 | #ifndef PRODUCT |
| 11338 | void overflowAddI_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11339 | // Start at oper_input_base() and count operands |
| 11340 | unsigned idx0 = 1; |
| 11341 | unsigned idx1 = 1; // op1 |
| 11342 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2 |
| 11343 | st->print_raw("addl "); |
| 11344 | opnd_array(1)->ext_format(ra, this,idx1, st); // op1 |
| 11345 | st->print_raw(", "); |
| 11346 | opnd_array(2)->ext_format(ra, this,idx2, st); // op2 |
| 11347 | st->print_raw("\t# overflow check int"); |
| 11348 | } |
| 11349 | #endif |
| 11350 | #ifndef PRODUCT |
| 11351 | void overflowAddI_rReg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11352 | // Start at oper_input_base() and count operands |
| 11353 | unsigned idx0 = 1; |
| 11354 | unsigned idx1 = 1; // op1 |
| 11355 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2 |
| 11356 | st->print_raw("addl "); |
| 11357 | opnd_array(1)->ext_format(ra, this,idx1, st); // op1 |
| 11358 | st->print_raw(", "); |
| 11359 | opnd_array(2)->ext_format(ra, this,idx2, st); // op2 |
| 11360 | st->print_raw("\t# overflow check int"); |
| 11361 | } |
| 11362 | #endif |
| 11363 | #ifndef PRODUCT |
| 11364 | void overflowAddL_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11365 | // Start at oper_input_base() and count operands |
| 11366 | unsigned idx0 = 1; |
| 11367 | unsigned idx1 = 1; // op1 |
| 11368 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2 |
| 11369 | st->print_raw("addq "); |
| 11370 | opnd_array(1)->ext_format(ra, this,idx1, st); // op1 |
| 11371 | st->print_raw(", "); |
| 11372 | opnd_array(2)->ext_format(ra, this,idx2, st); // op2 |
| 11373 | st->print_raw("\t# overflow check long"); |
| 11374 | } |
| 11375 | #endif |
| 11376 | #ifndef PRODUCT |
| 11377 | void overflowAddL_rReg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11378 | // Start at oper_input_base() and count operands |
| 11379 | unsigned idx0 = 1; |
| 11380 | unsigned idx1 = 1; // op1 |
| 11381 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2 |
| 11382 | st->print_raw("addq "); |
| 11383 | opnd_array(1)->ext_format(ra, this,idx1, st); // op1 |
| 11384 | st->print_raw(", "); |
| 11385 | opnd_array(2)->ext_format(ra, this,idx2, st); // op2 |
| 11386 | st->print_raw("\t# overflow check long"); |
| 11387 | } |
| 11388 | #endif |
| 11389 | #ifndef PRODUCT |
| 11390 | void overflowSubI_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11391 | // Start at oper_input_base() and count operands |
| 11392 | unsigned idx0 = 1; |
| 11393 | unsigned idx1 = 1; // op1 |
| 11394 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2 |
| 11395 | st->print_raw("cmpl "); |
| 11396 | opnd_array(1)->ext_format(ra, this,idx1, st); // op1 |
| 11397 | st->print_raw(", "); |
| 11398 | opnd_array(2)->ext_format(ra, this,idx2, st); // op2 |
| 11399 | st->print_raw("\t# overflow check int"); |
| 11400 | } |
| 11401 | #endif |
| 11402 | #ifndef PRODUCT |
| 11403 | void overflowSubI_rReg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11404 | // Start at oper_input_base() and count operands |
| 11405 | unsigned idx0 = 1; |
| 11406 | unsigned idx1 = 1; // op1 |
| 11407 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2 |
| 11408 | st->print_raw("cmpl "); |
| 11409 | opnd_array(1)->ext_format(ra, this,idx1, st); // op1 |
| 11410 | st->print_raw(", "); |
| 11411 | opnd_array(2)->ext_format(ra, this,idx2, st); // op2 |
| 11412 | st->print_raw("\t# overflow check int"); |
| 11413 | } |
| 11414 | #endif |
| 11415 | #ifndef PRODUCT |
| 11416 | void overflowSubL_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11417 | // Start at oper_input_base() and count operands |
| 11418 | unsigned idx0 = 1; |
| 11419 | unsigned idx1 = 1; // op1 |
| 11420 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2 |
| 11421 | st->print_raw("cmpq "); |
| 11422 | opnd_array(1)->ext_format(ra, this,idx1, st); // op1 |
| 11423 | st->print_raw(", "); |
| 11424 | opnd_array(2)->ext_format(ra, this,idx2, st); // op2 |
| 11425 | st->print_raw("\t# overflow check long"); |
| 11426 | } |
| 11427 | #endif |
| 11428 | #ifndef PRODUCT |
| 11429 | void overflowSubL_rReg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11430 | // Start at oper_input_base() and count operands |
| 11431 | unsigned idx0 = 1; |
| 11432 | unsigned idx1 = 1; // op1 |
| 11433 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2 |
| 11434 | st->print_raw("cmpq "); |
| 11435 | opnd_array(1)->ext_format(ra, this,idx1, st); // op1 |
| 11436 | st->print_raw(", "); |
| 11437 | opnd_array(2)->ext_format(ra, this,idx2, st); // op2 |
| 11438 | st->print_raw("\t# overflow check long"); |
| 11439 | } |
| 11440 | #endif |
| 11441 | #ifndef PRODUCT |
| 11442 | void overflowNegI_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11443 | // Start at oper_input_base() and count operands |
| 11444 | unsigned idx0 = 1; |
| 11445 | unsigned idx1 = 1; // zero |
| 11446 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2 |
| 11447 | st->print_raw("negl "); |
| 11448 | opnd_array(2)->ext_format(ra, this,idx2, st); // op2 |
| 11449 | st->print_raw("\t# overflow check int"); |
| 11450 | } |
| 11451 | #endif |
| 11452 | #ifndef PRODUCT |
| 11453 | void overflowNegL_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11454 | // Start at oper_input_base() and count operands |
| 11455 | unsigned idx0 = 1; |
| 11456 | unsigned idx1 = 1; // zero |
| 11457 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2 |
| 11458 | st->print_raw("negq "); |
| 11459 | opnd_array(2)->ext_format(ra, this,idx2, st); // op2 |
| 11460 | st->print_raw("\t# overflow check long"); |
| 11461 | } |
| 11462 | #endif |
| 11463 | #ifndef PRODUCT |
| 11464 | void overflowMulI_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11465 | // Start at oper_input_base() and count operands |
| 11466 | unsigned idx0 = 1; |
| 11467 | unsigned idx1 = 1; // op1 |
| 11468 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2 |
| 11469 | st->print_raw("imull "); |
| 11470 | opnd_array(1)->ext_format(ra, this,idx1, st); // op1 |
| 11471 | st->print_raw(", "); |
| 11472 | opnd_array(2)->ext_format(ra, this,idx2, st); // op2 |
| 11473 | st->print_raw("\t# overflow check int"); |
| 11474 | } |
| 11475 | #endif |
| 11476 | #ifndef PRODUCT |
| 11477 | void overflowMulI_rReg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11478 | // Start at oper_input_base() and count operands |
| 11479 | unsigned idx0 = 1; |
| 11480 | unsigned idx1 = 1; // op1 |
| 11481 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2 |
| 11482 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp |
| 11483 | st->print_raw("imull "); |
| 11484 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp |
| 11485 | st->print_raw(", "); |
| 11486 | opnd_array(1)->ext_format(ra, this,idx1, st); // op1 |
| 11487 | st->print_raw(", "); |
| 11488 | opnd_array(2)->ext_format(ra, this,idx2, st); // op2 |
| 11489 | st->print_raw("\t# overflow check int"); |
| 11490 | } |
| 11491 | #endif |
| 11492 | #ifndef PRODUCT |
| 11493 | void overflowMulL_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11494 | // Start at oper_input_base() and count operands |
| 11495 | unsigned idx0 = 1; |
| 11496 | unsigned idx1 = 1; // op1 |
| 11497 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2 |
| 11498 | st->print_raw("imulq "); |
| 11499 | opnd_array(1)->ext_format(ra, this,idx1, st); // op1 |
| 11500 | st->print_raw(", "); |
| 11501 | opnd_array(2)->ext_format(ra, this,idx2, st); // op2 |
| 11502 | st->print_raw("\t# overflow check long"); |
| 11503 | } |
| 11504 | #endif |
| 11505 | #ifndef PRODUCT |
| 11506 | void overflowMulL_rReg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11507 | // Start at oper_input_base() and count operands |
| 11508 | unsigned idx0 = 1; |
| 11509 | unsigned idx1 = 1; // op1 |
| 11510 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2 |
| 11511 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp |
| 11512 | st->print_raw("imulq "); |
| 11513 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp |
| 11514 | st->print_raw(", "); |
| 11515 | opnd_array(1)->ext_format(ra, this,idx1, st); // op1 |
| 11516 | st->print_raw(", "); |
| 11517 | opnd_array(2)->ext_format(ra, this,idx2, st); // op2 |
| 11518 | st->print_raw("\t# overflow check long"); |
| 11519 | } |
| 11520 | #endif |
| 11521 | #ifndef PRODUCT |
| 11522 | void compI_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11523 | // Start at oper_input_base() and count operands |
| 11524 | unsigned idx0 = 1; |
| 11525 | unsigned idx1 = 1; // op1 |
| 11526 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2 |
| 11527 | st->print_raw("cmpl "); |
| 11528 | opnd_array(1)->ext_format(ra, this,idx1, st); // op1 |
| 11529 | st->print_raw(", "); |
| 11530 | opnd_array(2)->ext_format(ra, this,idx2, st); // op2 |
| 11531 | } |
| 11532 | #endif |
| 11533 | #ifndef PRODUCT |
| 11534 | void compI_rReg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11535 | // Start at oper_input_base() and count operands |
| 11536 | unsigned idx0 = 1; |
| 11537 | unsigned idx1 = 1; // op1 |
| 11538 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2 |
| 11539 | st->print_raw("cmpl "); |
| 11540 | opnd_array(1)->ext_format(ra, this,idx1, st); // op1 |
| 11541 | st->print_raw(", "); |
| 11542 | opnd_array(2)->ext_format(ra, this,idx2, st); // op2 |
| 11543 | } |
| 11544 | #endif |
| 11545 | #ifndef PRODUCT |
| 11546 | void compI_rReg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11547 | // Start at oper_input_base() and count operands |
| 11548 | unsigned idx0 = 2; |
| 11549 | unsigned idx1 = 2; // op1 |
| 11550 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2 |
| 11551 | st->print_raw("cmpl "); |
| 11552 | opnd_array(1)->ext_format(ra, this,idx1, st); // op1 |
| 11553 | st->print_raw(", "); |
| 11554 | opnd_array(2)->ext_format(ra, this,idx2, st); // op2 |
| 11555 | } |
| 11556 | #endif |
| 11557 | #ifndef PRODUCT |
| 11558 | void testI_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11559 | // Start at oper_input_base() and count operands |
| 11560 | unsigned idx0 = 1; |
| 11561 | unsigned idx1 = 1; // src |
| 11562 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero |
| 11563 | st->print_raw("testl "); |
| 11564 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 11565 | st->print_raw(", "); |
| 11566 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 11567 | } |
| 11568 | #endif |
| 11569 | #ifndef PRODUCT |
| 11570 | void testI_reg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11571 | // Start at oper_input_base() and count operands |
| 11572 | unsigned idx0 = 1; |
| 11573 | unsigned idx1 = 1; // src |
| 11574 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con |
| 11575 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // zero |
| 11576 | st->print_raw("testl "); |
| 11577 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 11578 | st->print_raw(", "); |
| 11579 | opnd_array(2)->ext_format(ra, this,idx2, st); // con |
| 11580 | } |
| 11581 | #endif |
| 11582 | #ifndef PRODUCT |
| 11583 | void testI_reg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11584 | // Start at oper_input_base() and count operands |
| 11585 | unsigned idx0 = 2; |
| 11586 | unsigned idx1 = 2; // src |
| 11587 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem |
| 11588 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // zero |
| 11589 | st->print_raw("testl "); |
| 11590 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 11591 | st->print_raw(", "); |
| 11592 | opnd_array(2)->ext_format(ra, this,idx2, st); // mem |
| 11593 | } |
| 11594 | #endif |
| 11595 | #ifndef PRODUCT |
| 11596 | void testI_reg_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11597 | // Start at oper_input_base() and count operands |
| 11598 | unsigned idx0 = 2; |
| 11599 | unsigned idx1 = 2; // mem |
| 11600 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 11601 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // zero |
| 11602 | st->print_raw("testl "); |
| 11603 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 11604 | st->print_raw(", "); |
| 11605 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 11606 | } |
| 11607 | #endif |
| 11608 | #ifndef PRODUCT |
| 11609 | void compU_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11610 | // Start at oper_input_base() and count operands |
| 11611 | unsigned idx0 = 1; |
| 11612 | unsigned idx1 = 1; // op1 |
| 11613 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2 |
| 11614 | st->print_raw("cmpl "); |
| 11615 | opnd_array(1)->ext_format(ra, this,idx1, st); // op1 |
| 11616 | st->print_raw(", "); |
| 11617 | opnd_array(2)->ext_format(ra, this,idx2, st); // op2 |
| 11618 | st->print_raw("\t# unsigned"); |
| 11619 | } |
| 11620 | #endif |
| 11621 | #ifndef PRODUCT |
| 11622 | void compU_rReg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11623 | // Start at oper_input_base() and count operands |
| 11624 | unsigned idx0 = 1; |
| 11625 | unsigned idx1 = 1; // op1 |
| 11626 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2 |
| 11627 | st->print_raw("cmpl "); |
| 11628 | opnd_array(1)->ext_format(ra, this,idx1, st); // op1 |
| 11629 | st->print_raw(", "); |
| 11630 | opnd_array(2)->ext_format(ra, this,idx2, st); // op2 |
| 11631 | st->print_raw("\t# unsigned"); |
| 11632 | } |
| 11633 | #endif |
| 11634 | #ifndef PRODUCT |
| 11635 | void compU_rReg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11636 | // Start at oper_input_base() and count operands |
| 11637 | unsigned idx0 = 2; |
| 11638 | unsigned idx1 = 2; // op1 |
| 11639 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2 |
| 11640 | st->print_raw("cmpl "); |
| 11641 | opnd_array(1)->ext_format(ra, this,idx1, st); // op1 |
| 11642 | st->print_raw(", "); |
| 11643 | opnd_array(2)->ext_format(ra, this,idx2, st); // op2 |
| 11644 | st->print_raw("\t# unsigned"); |
| 11645 | } |
| 11646 | #endif |
| 11647 | #ifndef PRODUCT |
| 11648 | void testU_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11649 | // Start at oper_input_base() and count operands |
| 11650 | unsigned idx0 = 1; |
| 11651 | unsigned idx1 = 1; // src |
| 11652 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero |
| 11653 | st->print_raw("testl "); |
| 11654 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 11655 | st->print_raw(", "); |
| 11656 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 11657 | st->print_raw("\t# unsigned"); |
| 11658 | } |
| 11659 | #endif |
| 11660 | #ifndef PRODUCT |
| 11661 | void compP_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11662 | // Start at oper_input_base() and count operands |
| 11663 | unsigned idx0 = 1; |
| 11664 | unsigned idx1 = 1; // op1 |
| 11665 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2 |
| 11666 | st->print_raw("cmpq "); |
| 11667 | opnd_array(1)->ext_format(ra, this,idx1, st); // op1 |
| 11668 | st->print_raw(", "); |
| 11669 | opnd_array(2)->ext_format(ra, this,idx2, st); // op2 |
| 11670 | st->print_raw("\t# ptr"); |
| 11671 | } |
| 11672 | #endif |
| 11673 | #ifndef PRODUCT |
| 11674 | void compP_rReg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11675 | // Start at oper_input_base() and count operands |
| 11676 | unsigned idx0 = 2; |
| 11677 | unsigned idx1 = 2; // op1 |
| 11678 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2 |
| 11679 | st->print_raw("cmpq "); |
| 11680 | opnd_array(1)->ext_format(ra, this,idx1, st); // op1 |
| 11681 | st->print_raw(", "); |
| 11682 | opnd_array(2)->ext_format(ra, this,idx2, st); // op2 |
| 11683 | st->print_raw("\t# ptr"); |
| 11684 | } |
| 11685 | #endif |
| 11686 | #ifndef PRODUCT |
| 11687 | void compP_mem_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11688 | // Start at oper_input_base() and count operands |
| 11689 | unsigned idx0 = 2; |
| 11690 | unsigned idx1 = 2; // op1 |
| 11691 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2 |
| 11692 | st->print_raw("cmpq "); |
| 11693 | opnd_array(1)->ext_format(ra, this,idx1, st); // op1 |
| 11694 | st->print_raw(", "); |
| 11695 | opnd_array(2)->ext_format(ra, this,idx2, st); // op2 |
| 11696 | st->print_raw("\t# raw ptr"); |
| 11697 | } |
| 11698 | #endif |
| 11699 | #ifndef PRODUCT |
| 11700 | void testP_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11701 | // Start at oper_input_base() and count operands |
| 11702 | unsigned idx0 = 1; |
| 11703 | unsigned idx1 = 1; // src |
| 11704 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero |
| 11705 | st->print_raw("testq "); |
| 11706 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 11707 | st->print_raw(", "); |
| 11708 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 11709 | st->print_raw("\t# ptr"); |
| 11710 | } |
| 11711 | #endif |
| 11712 | #ifndef PRODUCT |
| 11713 | void testP_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11714 | // Start at oper_input_base() and count operands |
| 11715 | unsigned idx0 = 2; |
| 11716 | unsigned idx1 = 2; // op |
| 11717 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero |
| 11718 | st->print_raw("testq "); |
| 11719 | opnd_array(1)->ext_format(ra, this,idx1, st); // op |
| 11720 | st->print_raw(", 0xffffffffffffffff\t# ptr"); |
| 11721 | } |
| 11722 | #endif |
| 11723 | #ifndef PRODUCT |
| 11724 | void testP_mem_reg0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11725 | // Start at oper_input_base() and count operands |
| 11726 | unsigned idx0 = 2; |
| 11727 | unsigned idx1 = 2; // mem |
| 11728 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero |
| 11729 | st->print_raw("cmpq R12, "); |
| 11730 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 11731 | st->print_raw("\t# ptr (R12_heapbase==0)"); |
| 11732 | } |
| 11733 | #endif |
| 11734 | #ifndef PRODUCT |
| 11735 | void compN_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11736 | // Start at oper_input_base() and count operands |
| 11737 | unsigned idx0 = 1; |
| 11738 | unsigned idx1 = 1; // op1 |
| 11739 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2 |
| 11740 | st->print_raw("cmpl "); |
| 11741 | opnd_array(1)->ext_format(ra, this,idx1, st); // op1 |
| 11742 | st->print_raw(", "); |
| 11743 | opnd_array(2)->ext_format(ra, this,idx2, st); // op2 |
| 11744 | st->print_raw("\t# compressed ptr"); |
| 11745 | } |
| 11746 | #endif |
| 11747 | #ifndef PRODUCT |
| 11748 | void compN_rReg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11749 | // Start at oper_input_base() and count operands |
| 11750 | unsigned idx0 = 2; |
| 11751 | unsigned idx1 = 2; // src |
| 11752 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem |
| 11753 | st->print_raw("cmpl "); |
| 11754 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 11755 | st->print_raw(", "); |
| 11756 | opnd_array(2)->ext_format(ra, this,idx2, st); // mem |
| 11757 | st->print_raw("\t# compressed ptr"); |
| 11758 | } |
| 11759 | #endif |
| 11760 | #ifndef PRODUCT |
| 11761 | void compN_rReg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11762 | // Start at oper_input_base() and count operands |
| 11763 | unsigned idx0 = 1; |
| 11764 | unsigned idx1 = 1; // op1 |
| 11765 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2 |
| 11766 | st->print_raw("cmpl "); |
| 11767 | opnd_array(1)->ext_format(ra, this,idx1, st); // op1 |
| 11768 | st->print_raw(", "); |
| 11769 | opnd_array(2)->ext_format(ra, this,idx2, st); // op2 |
| 11770 | st->print_raw("\t# compressed ptr"); |
| 11771 | } |
| 11772 | #endif |
| 11773 | #ifndef PRODUCT |
| 11774 | void compN_mem_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11775 | // Start at oper_input_base() and count operands |
| 11776 | unsigned idx0 = 2; |
| 11777 | unsigned idx1 = 2; // src |
| 11778 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem |
| 11779 | st->print_raw("cmpl "); |
| 11780 | opnd_array(2)->ext_format(ra, this,idx2, st); // mem |
| 11781 | st->print_raw(", "); |
| 11782 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 11783 | st->print_raw("\t# compressed ptr"); |
| 11784 | } |
| 11785 | #endif |
| 11786 | #ifndef PRODUCT |
| 11787 | void compN_rReg_imm_klassNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11788 | // Start at oper_input_base() and count operands |
| 11789 | unsigned idx0 = 1; |
| 11790 | unsigned idx1 = 1; // op1 |
| 11791 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2 |
| 11792 | st->print_raw("cmpl "); |
| 11793 | opnd_array(1)->ext_format(ra, this,idx1, st); // op1 |
| 11794 | st->print_raw(", "); |
| 11795 | opnd_array(2)->ext_format(ra, this,idx2, st); // op2 |
| 11796 | st->print_raw("\t# compressed klass ptr"); |
| 11797 | } |
| 11798 | #endif |
| 11799 | #ifndef PRODUCT |
| 11800 | void compN_mem_imm_klassNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11801 | // Start at oper_input_base() and count operands |
| 11802 | unsigned idx0 = 2; |
| 11803 | unsigned idx1 = 2; // src |
| 11804 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem |
| 11805 | st->print_raw("cmpl "); |
| 11806 | opnd_array(2)->ext_format(ra, this,idx2, st); // mem |
| 11807 | st->print_raw(", "); |
| 11808 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 11809 | st->print_raw("\t# compressed klass ptr"); |
| 11810 | } |
| 11811 | #endif |
| 11812 | #ifndef PRODUCT |
| 11813 | void testN_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11814 | // Start at oper_input_base() and count operands |
| 11815 | unsigned idx0 = 1; |
| 11816 | unsigned idx1 = 1; // src |
| 11817 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero |
| 11818 | st->print_raw("testl "); |
| 11819 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 11820 | st->print_raw(", "); |
| 11821 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 11822 | st->print_raw("\t# compressed ptr"); |
| 11823 | } |
| 11824 | #endif |
| 11825 | #ifndef PRODUCT |
| 11826 | void testN_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11827 | // Start at oper_input_base() and count operands |
| 11828 | unsigned idx0 = 2; |
| 11829 | unsigned idx1 = 2; // mem |
| 11830 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero |
| 11831 | st->print_raw("testl "); |
| 11832 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 11833 | st->print_raw(", 0xffffffff\t# compressed ptr"); |
| 11834 | } |
| 11835 | #endif |
| 11836 | #ifndef PRODUCT |
| 11837 | void testN_mem_reg0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11838 | // Start at oper_input_base() and count operands |
| 11839 | unsigned idx0 = 2; |
| 11840 | unsigned idx1 = 2; // mem |
| 11841 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero |
| 11842 | st->print_raw("cmpl R12, "); |
| 11843 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 11844 | st->print_raw("\t# compressed ptr (R12_heapbase==0)"); |
| 11845 | } |
| 11846 | #endif |
| 11847 | #ifndef PRODUCT |
| 11848 | void compL_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11849 | // Start at oper_input_base() and count operands |
| 11850 | unsigned idx0 = 1; |
| 11851 | unsigned idx1 = 1; // op1 |
| 11852 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2 |
| 11853 | st->print_raw("cmpq "); |
| 11854 | opnd_array(1)->ext_format(ra, this,idx1, st); // op1 |
| 11855 | st->print_raw(", "); |
| 11856 | opnd_array(2)->ext_format(ra, this,idx2, st); // op2 |
| 11857 | } |
| 11858 | #endif |
| 11859 | #ifndef PRODUCT |
| 11860 | void compL_rReg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11861 | // Start at oper_input_base() and count operands |
| 11862 | unsigned idx0 = 1; |
| 11863 | unsigned idx1 = 1; // op1 |
| 11864 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2 |
| 11865 | st->print_raw("cmpq "); |
| 11866 | opnd_array(1)->ext_format(ra, this,idx1, st); // op1 |
| 11867 | st->print_raw(", "); |
| 11868 | opnd_array(2)->ext_format(ra, this,idx2, st); // op2 |
| 11869 | } |
| 11870 | #endif |
| 11871 | #ifndef PRODUCT |
| 11872 | void compL_rReg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11873 | // Start at oper_input_base() and count operands |
| 11874 | unsigned idx0 = 2; |
| 11875 | unsigned idx1 = 2; // op1 |
| 11876 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2 |
| 11877 | st->print_raw("cmpq "); |
| 11878 | opnd_array(1)->ext_format(ra, this,idx1, st); // op1 |
| 11879 | st->print_raw(", "); |
| 11880 | opnd_array(2)->ext_format(ra, this,idx2, st); // op2 |
| 11881 | } |
| 11882 | #endif |
| 11883 | #ifndef PRODUCT |
| 11884 | void testL_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11885 | // Start at oper_input_base() and count operands |
| 11886 | unsigned idx0 = 1; |
| 11887 | unsigned idx1 = 1; // src |
| 11888 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero |
| 11889 | st->print_raw("testq "); |
| 11890 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 11891 | st->print_raw(", "); |
| 11892 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 11893 | } |
| 11894 | #endif |
| 11895 | #ifndef PRODUCT |
| 11896 | void testL_reg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11897 | // Start at oper_input_base() and count operands |
| 11898 | unsigned idx0 = 1; |
| 11899 | unsigned idx1 = 1; // src |
| 11900 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con |
| 11901 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // zero |
| 11902 | st->print_raw("testq "); |
| 11903 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 11904 | st->print_raw(", "); |
| 11905 | opnd_array(2)->ext_format(ra, this,idx2, st); // con |
| 11906 | st->print_raw("\t# long"); |
| 11907 | } |
| 11908 | #endif |
| 11909 | #ifndef PRODUCT |
| 11910 | void testL_reg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11911 | // Start at oper_input_base() and count operands |
| 11912 | unsigned idx0 = 2; |
| 11913 | unsigned idx1 = 2; // src |
| 11914 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem |
| 11915 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // zero |
| 11916 | st->print_raw("testq "); |
| 11917 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 11918 | st->print_raw(", "); |
| 11919 | opnd_array(2)->ext_format(ra, this,idx2, st); // mem |
| 11920 | } |
| 11921 | #endif |
| 11922 | #ifndef PRODUCT |
| 11923 | void testL_reg_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11924 | // Start at oper_input_base() and count operands |
| 11925 | unsigned idx0 = 2; |
| 11926 | unsigned idx1 = 2; // mem |
| 11927 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 11928 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // zero |
| 11929 | st->print_raw("testq "); |
| 11930 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 11931 | st->print_raw(", "); |
| 11932 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 11933 | } |
| 11934 | #endif |
| 11935 | #ifndef PRODUCT |
| 11936 | void testL_reg_mem2Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11937 | // Start at oper_input_base() and count operands |
| 11938 | unsigned idx0 = 2; |
| 11939 | unsigned idx1 = 2; // src |
| 11940 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem |
| 11941 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // zero |
| 11942 | st->print_raw("testq "); |
| 11943 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 11944 | st->print_raw(", "); |
| 11945 | opnd_array(2)->ext_format(ra, this,idx2, st); // mem |
| 11946 | } |
| 11947 | #endif |
| 11948 | #ifndef PRODUCT |
| 11949 | void testL_reg_mem2_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11950 | // Start at oper_input_base() and count operands |
| 11951 | unsigned idx0 = 2; |
| 11952 | unsigned idx1 = 2; // mem |
| 11953 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 11954 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // zero |
| 11955 | st->print_raw("testq "); |
| 11956 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 11957 | st->print_raw(", "); |
| 11958 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 11959 | } |
| 11960 | #endif |
| 11961 | #ifndef PRODUCT |
| 11962 | void cmpL3_reg_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11963 | // Start at oper_input_base() and count operands |
| 11964 | unsigned idx0 = 1; |
| 11965 | unsigned idx1 = 1; // src1 |
| 11966 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 11967 | st->print_raw("cmpq "); |
| 11968 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 11969 | st->print_raw(", "); |
| 11970 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 11971 | st->print_raw("\t# CmpL3\n\t"); |
| 11972 | st->print_raw("movl "); |
| 11973 | opnd_array(0)->int_format(ra, this, st); // dst |
| 11974 | st->print_raw(", -1\n\t"); |
| 11975 | st->print_raw("jl,s done\n\t"); |
| 11976 | st->print_raw("setne "); |
| 11977 | opnd_array(0)->int_format(ra, this, st); // dst |
| 11978 | st->print_raw("\n\t"); |
| 11979 | st->print_raw("movzbl "); |
| 11980 | opnd_array(0)->int_format(ra, this, st); // dst |
| 11981 | st->print_raw(", "); |
| 11982 | opnd_array(0)->int_format(ra, this, st); // dst |
| 11983 | st->print_raw("\n\t"); |
| 11984 | st->print_raw("done:"); |
| 11985 | } |
| 11986 | #endif |
| 11987 | #ifndef PRODUCT |
| 11988 | void compUL_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 11989 | // Start at oper_input_base() and count operands |
| 11990 | unsigned idx0 = 1; |
| 11991 | unsigned idx1 = 1; // op1 |
| 11992 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2 |
| 11993 | st->print_raw("cmpq "); |
| 11994 | opnd_array(1)->ext_format(ra, this,idx1, st); // op1 |
| 11995 | st->print_raw(", "); |
| 11996 | opnd_array(2)->ext_format(ra, this,idx2, st); // op2 |
| 11997 | st->print_raw("\t# unsigned"); |
| 11998 | } |
| 11999 | #endif |
| 12000 | #ifndef PRODUCT |
| 12001 | void compUL_rReg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12002 | // Start at oper_input_base() and count operands |
| 12003 | unsigned idx0 = 1; |
| 12004 | unsigned idx1 = 1; // op1 |
| 12005 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2 |
| 12006 | st->print_raw("cmpq "); |
| 12007 | opnd_array(1)->ext_format(ra, this,idx1, st); // op1 |
| 12008 | st->print_raw(", "); |
| 12009 | opnd_array(2)->ext_format(ra, this,idx2, st); // op2 |
| 12010 | st->print_raw("\t# unsigned"); |
| 12011 | } |
| 12012 | #endif |
| 12013 | #ifndef PRODUCT |
| 12014 | void compUL_rReg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12015 | // Start at oper_input_base() and count operands |
| 12016 | unsigned idx0 = 2; |
| 12017 | unsigned idx1 = 2; // op1 |
| 12018 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2 |
| 12019 | st->print_raw("cmpq "); |
| 12020 | opnd_array(1)->ext_format(ra, this,idx1, st); // op1 |
| 12021 | st->print_raw(", "); |
| 12022 | opnd_array(2)->ext_format(ra, this,idx2, st); // op2 |
| 12023 | st->print_raw("\t# unsigned"); |
| 12024 | } |
| 12025 | #endif |
| 12026 | #ifndef PRODUCT |
| 12027 | void testUL_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12028 | // Start at oper_input_base() and count operands |
| 12029 | unsigned idx0 = 1; |
| 12030 | unsigned idx1 = 1; // src |
| 12031 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero |
| 12032 | st->print_raw("testq "); |
| 12033 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 12034 | st->print_raw(", "); |
| 12035 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 12036 | st->print_raw("\t# unsigned"); |
| 12037 | } |
| 12038 | #endif |
| 12039 | #ifndef PRODUCT |
| 12040 | void compB_mem_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12041 | // Start at oper_input_base() and count operands |
| 12042 | unsigned idx0 = 2; |
| 12043 | unsigned idx1 = 2; // mem |
| 12044 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // imm |
| 12045 | st->print_raw("cmpb "); |
| 12046 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 12047 | st->print_raw(", "); |
| 12048 | opnd_array(2)->ext_format(ra, this,idx2, st); // imm |
| 12049 | } |
| 12050 | #endif |
| 12051 | #ifndef PRODUCT |
| 12052 | void testUB_mem_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12053 | // Start at oper_input_base() and count operands |
| 12054 | unsigned idx0 = 2; |
| 12055 | unsigned idx1 = 2; // mem |
| 12056 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // imm |
| 12057 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // zero |
| 12058 | st->print_raw("testb "); |
| 12059 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 12060 | st->print_raw(", "); |
| 12061 | opnd_array(2)->ext_format(ra, this,idx2, st); // imm |
| 12062 | st->print_raw("\t# ubyte"); |
| 12063 | } |
| 12064 | #endif |
| 12065 | #ifndef PRODUCT |
| 12066 | void testB_mem_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12067 | // Start at oper_input_base() and count operands |
| 12068 | unsigned idx0 = 2; |
| 12069 | unsigned idx1 = 2; // mem |
| 12070 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // imm |
| 12071 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // zero |
| 12072 | st->print_raw("testb "); |
| 12073 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 12074 | st->print_raw(", "); |
| 12075 | opnd_array(2)->ext_format(ra, this,idx2, st); // imm |
| 12076 | st->print_raw("\t# byte"); |
| 12077 | } |
| 12078 | #endif |
| 12079 | #ifndef PRODUCT |
| 12080 | void cmovI_reg_gNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12081 | // Start at oper_input_base() and count operands |
| 12082 | unsigned idx0 = 1; |
| 12083 | unsigned idx1 = 1; // src |
| 12084 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr |
| 12085 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // |
| 12086 | st->print_raw("cmovlgt "); |
| 12087 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 12088 | st->print_raw(", "); |
| 12089 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 12090 | st->print_raw("\t# min"); |
| 12091 | } |
| 12092 | #endif |
| 12093 | #ifndef PRODUCT |
| 12094 | void minI_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12095 | } |
| 12096 | #endif |
| 12097 | #ifndef PRODUCT |
| 12098 | void cmovI_reg_lNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12099 | // Start at oper_input_base() and count operands |
| 12100 | unsigned idx0 = 1; |
| 12101 | unsigned idx1 = 1; // src |
| 12102 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr |
| 12103 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // |
| 12104 | st->print_raw("cmovllt "); |
| 12105 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 12106 | st->print_raw(", "); |
| 12107 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 12108 | st->print_raw("\t# max"); |
| 12109 | } |
| 12110 | #endif |
| 12111 | #ifndef PRODUCT |
| 12112 | void maxI_rRegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12113 | } |
| 12114 | #endif |
| 12115 | #ifndef PRODUCT |
| 12116 | void jmpDirNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12117 | // Start at oper_input_base() and count operands |
| 12118 | unsigned idx0 = 1; |
| 12119 | unsigned idx1 = 1; // |
| 12120 | st->print_raw("jmp "); |
| 12121 | opnd_array(1)->ext_format(ra, this,idx1, st); // labl |
| 12122 | } |
| 12123 | #endif |
| 12124 | #ifndef PRODUCT |
| 12125 | void jmpConNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12126 | // Start at oper_input_base() and count operands |
| 12127 | unsigned idx0 = 1; |
| 12128 | unsigned idx1 = 1; // cr |
| 12129 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // labl |
| 12130 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // |
| 12131 | st->print_raw("j"); |
| 12132 | opnd_array(1)->ext_format(ra, this,idx1, st); // cop |
| 12133 | st->print_raw(" "); |
| 12134 | opnd_array(3)->ext_format(ra, this,idx3, st); // labl |
| 12135 | st->print(" P=%f C=%f",_prob,_fcnt); |
| 12136 | } |
| 12137 | #endif |
| 12138 | #ifndef PRODUCT |
| 12139 | void jmpLoopEndNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12140 | // Start at oper_input_base() and count operands |
| 12141 | unsigned idx0 = 1; |
| 12142 | unsigned idx1 = 1; // cr |
| 12143 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // labl |
| 12144 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // |
| 12145 | st->print_raw("j"); |
| 12146 | opnd_array(1)->ext_format(ra, this,idx1, st); // cop |
| 12147 | st->print_raw(" "); |
| 12148 | opnd_array(3)->ext_format(ra, this,idx3, st); // labl |
| 12149 | st->print_raw("\t# loop end"); |
| 12150 | st->print(" P=%f C=%f",_prob,_fcnt); |
| 12151 | } |
| 12152 | #endif |
| 12153 | #ifndef PRODUCT |
| 12154 | void jmpLoopEndUNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12155 | // Start at oper_input_base() and count operands |
| 12156 | unsigned idx0 = 1; |
| 12157 | unsigned idx1 = 1; // cmp |
| 12158 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // labl |
| 12159 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // |
| 12160 | st->print_raw("j"); |
| 12161 | opnd_array(1)->ext_format(ra, this,idx1, st); // cop |
| 12162 | st->print_raw(",u "); |
| 12163 | opnd_array(3)->ext_format(ra, this,idx3, st); // labl |
| 12164 | st->print_raw("\t# loop end"); |
| 12165 | st->print(" P=%f C=%f",_prob,_fcnt); |
| 12166 | } |
| 12167 | #endif |
| 12168 | #ifndef PRODUCT |
| 12169 | void jmpLoopEndUCFNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12170 | // Start at oper_input_base() and count operands |
| 12171 | unsigned idx0 = 1; |
| 12172 | unsigned idx1 = 1; // cmp |
| 12173 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // labl |
| 12174 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // |
| 12175 | st->print_raw("j"); |
| 12176 | opnd_array(1)->ext_format(ra, this,idx1, st); // cop |
| 12177 | st->print_raw(",u "); |
| 12178 | opnd_array(3)->ext_format(ra, this,idx3, st); // labl |
| 12179 | st->print_raw("\t# loop end"); |
| 12180 | st->print(" P=%f C=%f",_prob,_fcnt); |
| 12181 | } |
| 12182 | #endif |
| 12183 | #ifndef PRODUCT |
| 12184 | void jmpLoopEnd_and_restoreMaskNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12185 | // Start at oper_input_base() and count operands |
| 12186 | unsigned idx0 = 1; |
| 12187 | unsigned idx1 = 1; // cr |
| 12188 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // ktmp |
| 12189 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // labl |
| 12190 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // |
| 12191 | st->print_raw("j"); |
| 12192 | opnd_array(1)->ext_format(ra, this,idx1, st); // cop |
| 12193 | st->print_raw(" "); |
| 12194 | opnd_array(4)->ext_format(ra, this,idx4, st); // labl |
| 12195 | st->print_raw("\t# loop end\n\t"); |
| 12196 | st->print_raw("restorevectmask \t# vector mask restore for loops"); |
| 12197 | st->print(" P=%f C=%f",_prob,_fcnt); |
| 12198 | } |
| 12199 | #endif |
| 12200 | #ifndef PRODUCT |
| 12201 | void jmpLoopEndU_and_restoreMaskNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12202 | // Start at oper_input_base() and count operands |
| 12203 | unsigned idx0 = 1; |
| 12204 | unsigned idx1 = 1; // cmp |
| 12205 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // ktmp |
| 12206 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // labl |
| 12207 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // |
| 12208 | st->print_raw("j"); |
| 12209 | opnd_array(1)->ext_format(ra, this,idx1, st); // cop |
| 12210 | st->print_raw(",u "); |
| 12211 | opnd_array(4)->ext_format(ra, this,idx4, st); // labl |
| 12212 | st->print_raw("\t# loop end\n\t"); |
| 12213 | st->print_raw("restorevectmask \t# vector mask restore for loops"); |
| 12214 | st->print(" P=%f C=%f",_prob,_fcnt); |
| 12215 | } |
| 12216 | #endif |
| 12217 | #ifndef PRODUCT |
| 12218 | void jmpLoopEndUCF_and_restoreMaskNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12219 | // Start at oper_input_base() and count operands |
| 12220 | unsigned idx0 = 1; |
| 12221 | unsigned idx1 = 1; // cmp |
| 12222 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // ktmp |
| 12223 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // labl |
| 12224 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // |
| 12225 | st->print_raw("j"); |
| 12226 | opnd_array(1)->ext_format(ra, this,idx1, st); // cop |
| 12227 | st->print_raw(",u "); |
| 12228 | opnd_array(4)->ext_format(ra, this,idx4, st); // labl |
| 12229 | st->print_raw("\t# loop end\n\t"); |
| 12230 | st->print_raw("restorevectmask \t# vector mask restore for loops"); |
| 12231 | st->print(" P=%f C=%f",_prob,_fcnt); |
| 12232 | } |
| 12233 | #endif |
| 12234 | #ifndef PRODUCT |
| 12235 | void jmpConUNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12236 | // Start at oper_input_base() and count operands |
| 12237 | unsigned idx0 = 1; |
| 12238 | unsigned idx1 = 1; // cmp |
| 12239 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // labl |
| 12240 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // |
| 12241 | st->print_raw("j"); |
| 12242 | opnd_array(1)->ext_format(ra, this,idx1, st); // cop |
| 12243 | st->print_raw(",u "); |
| 12244 | opnd_array(3)->ext_format(ra, this,idx3, st); // labl |
| 12245 | st->print(" P=%f C=%f",_prob,_fcnt); |
| 12246 | } |
| 12247 | #endif |
| 12248 | #ifndef PRODUCT |
| 12249 | void jmpConUCFNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12250 | // Start at oper_input_base() and count operands |
| 12251 | unsigned idx0 = 1; |
| 12252 | unsigned idx1 = 1; // cmp |
| 12253 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // labl |
| 12254 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // |
| 12255 | st->print_raw("j"); |
| 12256 | opnd_array(1)->ext_format(ra, this,idx1, st); // cop |
| 12257 | st->print_raw(",u "); |
| 12258 | opnd_array(3)->ext_format(ra, this,idx3, st); // labl |
| 12259 | st->print(" P=%f C=%f",_prob,_fcnt); |
| 12260 | } |
| 12261 | #endif |
| 12262 | #ifndef PRODUCT |
| 12263 | void jmpConUCF2Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12264 | // Start at oper_input_base() and count operands |
| 12265 | unsigned idx0 = 1; |
| 12266 | unsigned idx1 = 1; // cmp |
| 12267 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // labl |
| 12268 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // |
| 12269 | if ( opnd_array(1)->ccode() == Assembler::notEqual) { |
| 12270 | st->print_raw("jp,u "); |
| 12271 | opnd_array(3)->ext_format(ra, this,idx3, st); // labl |
| 12272 | st->print_raw("\n\t"); |
| 12273 | st->print_raw("j"); |
| 12274 | opnd_array(1)->ext_format(ra, this,idx1, st); // cop |
| 12275 | st->print_raw(",u "); |
| 12276 | opnd_array(3)->ext_format(ra, this,idx3, st); // labl |
| 12277 | } else { |
| 12278 | st->print_raw("jp,u done\n\t"); |
| 12279 | st->print_raw("j"); |
| 12280 | opnd_array(1)->ext_format(ra, this,idx1, st); // cop |
| 12281 | st->print_raw(",u "); |
| 12282 | opnd_array(3)->ext_format(ra, this,idx3, st); // labl |
| 12283 | st->print_raw("\n\t"); |
| 12284 | st->print_raw("done:"); |
| 12285 | } |
| 12286 | st->print(" P=%f C=%f",_prob,_fcnt); |
| 12287 | } |
| 12288 | #endif |
| 12289 | #ifndef PRODUCT |
| 12290 | void partialSubtypeCheckNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12291 | // Start at oper_input_base() and count operands |
| 12292 | unsigned idx0 = 1; |
| 12293 | unsigned idx1 = 1; // sub |
| 12294 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // super |
| 12295 | st->print_raw("movq rdi, ["); |
| 12296 | opnd_array(1)->ext_format(ra, this,idx1, st); // sub |
| 12297 | st->print_raw(" + in_bytes(Klass::secondary_supers_offset())]\n\t"); |
| 12298 | st->print_raw("movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"); |
| 12299 | st->print_raw("addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"); |
| 12300 | st->print_raw("repne scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t"); |
| 12301 | st->print_raw("jne,s miss\t\t# Missed: rdi not-zero\n\t"); |
| 12302 | st->print_raw("movq ["); |
| 12303 | opnd_array(1)->ext_format(ra, this,idx1, st); // sub |
| 12304 | st->print_raw(" + in_bytes(Klass::secondary_super_cache_offset())], "); |
| 12305 | opnd_array(2)->ext_format(ra, this,idx2, st); // super |
| 12306 | st->print_raw("\t# Hit: update cache\n\t"); |
| 12307 | st->print_raw("xorq "); |
| 12308 | opnd_array(0)->int_format(ra, this, st); // result |
| 12309 | st->print_raw(", "); |
| 12310 | opnd_array(0)->int_format(ra, this, st); // result |
| 12311 | st->print_raw("\t\t Hit: rdi zero\n\t"); |
| 12312 | st->print_raw("miss:\t"); |
| 12313 | } |
| 12314 | #endif |
| 12315 | #ifndef PRODUCT |
| 12316 | void partialSubtypeCheck_vs_ZeroNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12317 | // Start at oper_input_base() and count operands |
| 12318 | unsigned idx0 = 1; |
| 12319 | unsigned idx1 = 1; // sub |
| 12320 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // super |
| 12321 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // zero |
| 12322 | st->print_raw("movq rdi, ["); |
| 12323 | opnd_array(1)->ext_format(ra, this,idx1, st); // sub |
| 12324 | st->print_raw(" + in_bytes(Klass::secondary_supers_offset())]\n\t"); |
| 12325 | st->print_raw("movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"); |
| 12326 | st->print_raw("addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"); |
| 12327 | st->print_raw("repne scasq\t# Scan *rdi++ for a match with rax while cx-- != 0\n\t"); |
| 12328 | st->print_raw("jne,s miss\t\t# Missed: flags nz\n\t"); |
| 12329 | st->print_raw("movq ["); |
| 12330 | opnd_array(1)->ext_format(ra, this,idx1, st); // sub |
| 12331 | st->print_raw(" + in_bytes(Klass::secondary_super_cache_offset())], "); |
| 12332 | opnd_array(2)->ext_format(ra, this,idx2, st); // super |
| 12333 | st->print_raw("\t# Hit: update cache\n\t"); |
| 12334 | st->print_raw("miss:\t"); |
| 12335 | } |
| 12336 | #endif |
| 12337 | #ifndef PRODUCT |
| 12338 | void jmpDir_shortNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12339 | // Start at oper_input_base() and count operands |
| 12340 | unsigned idx0 = 1; |
| 12341 | unsigned idx1 = 1; // |
| 12342 | st->print_raw("jmp,s "); |
| 12343 | opnd_array(1)->ext_format(ra, this,idx1, st); // labl |
| 12344 | } |
| 12345 | #endif |
| 12346 | #ifndef PRODUCT |
| 12347 | void jmpCon_shortNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12348 | // Start at oper_input_base() and count operands |
| 12349 | unsigned idx0 = 1; |
| 12350 | unsigned idx1 = 1; // cr |
| 12351 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // labl |
| 12352 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // |
| 12353 | st->print_raw("j"); |
| 12354 | opnd_array(1)->ext_format(ra, this,idx1, st); // cop |
| 12355 | st->print_raw(",s "); |
| 12356 | opnd_array(3)->ext_format(ra, this,idx3, st); // labl |
| 12357 | st->print(" P=%f C=%f",_prob,_fcnt); |
| 12358 | } |
| 12359 | #endif |
| 12360 | #ifndef PRODUCT |
| 12361 | void jmpLoopEnd_shortNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12362 | // Start at oper_input_base() and count operands |
| 12363 | unsigned idx0 = 1; |
| 12364 | unsigned idx1 = 1; // cr |
| 12365 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // labl |
| 12366 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // |
| 12367 | st->print_raw("j"); |
| 12368 | opnd_array(1)->ext_format(ra, this,idx1, st); // cop |
| 12369 | st->print_raw(",s "); |
| 12370 | opnd_array(3)->ext_format(ra, this,idx3, st); // labl |
| 12371 | st->print_raw("\t# loop end"); |
| 12372 | st->print(" P=%f C=%f",_prob,_fcnt); |
| 12373 | } |
| 12374 | #endif |
| 12375 | #ifndef PRODUCT |
| 12376 | void jmpLoopEndU_shortNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12377 | // Start at oper_input_base() and count operands |
| 12378 | unsigned idx0 = 1; |
| 12379 | unsigned idx1 = 1; // cmp |
| 12380 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // labl |
| 12381 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // |
| 12382 | st->print_raw("j"); |
| 12383 | opnd_array(1)->ext_format(ra, this,idx1, st); // cop |
| 12384 | st->print_raw(",us "); |
| 12385 | opnd_array(3)->ext_format(ra, this,idx3, st); // labl |
| 12386 | st->print_raw("\t# loop end"); |
| 12387 | st->print(" P=%f C=%f",_prob,_fcnt); |
| 12388 | } |
| 12389 | #endif |
| 12390 | #ifndef PRODUCT |
| 12391 | void jmpLoopEndUCF_shortNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12392 | // Start at oper_input_base() and count operands |
| 12393 | unsigned idx0 = 1; |
| 12394 | unsigned idx1 = 1; // cmp |
| 12395 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // labl |
| 12396 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // |
| 12397 | st->print_raw("j"); |
| 12398 | opnd_array(1)->ext_format(ra, this,idx1, st); // cop |
| 12399 | st->print_raw(",us "); |
| 12400 | opnd_array(3)->ext_format(ra, this,idx3, st); // labl |
| 12401 | st->print_raw("\t# loop end"); |
| 12402 | st->print(" P=%f C=%f",_prob,_fcnt); |
| 12403 | } |
| 12404 | #endif |
| 12405 | #ifndef PRODUCT |
| 12406 | void jmpConU_shortNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12407 | // Start at oper_input_base() and count operands |
| 12408 | unsigned idx0 = 1; |
| 12409 | unsigned idx1 = 1; // cmp |
| 12410 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // labl |
| 12411 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // |
| 12412 | st->print_raw("j"); |
| 12413 | opnd_array(1)->ext_format(ra, this,idx1, st); // cop |
| 12414 | st->print_raw(",us "); |
| 12415 | opnd_array(3)->ext_format(ra, this,idx3, st); // labl |
| 12416 | st->print(" P=%f C=%f",_prob,_fcnt); |
| 12417 | } |
| 12418 | #endif |
| 12419 | #ifndef PRODUCT |
| 12420 | void jmpConUCF_shortNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12421 | // Start at oper_input_base() and count operands |
| 12422 | unsigned idx0 = 1; |
| 12423 | unsigned idx1 = 1; // cmp |
| 12424 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // labl |
| 12425 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // |
| 12426 | st->print_raw("j"); |
| 12427 | opnd_array(1)->ext_format(ra, this,idx1, st); // cop |
| 12428 | st->print_raw(",us "); |
| 12429 | opnd_array(3)->ext_format(ra, this,idx3, st); // labl |
| 12430 | st->print(" P=%f C=%f",_prob,_fcnt); |
| 12431 | } |
| 12432 | #endif |
| 12433 | #ifndef PRODUCT |
| 12434 | void jmpConUCF2_shortNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12435 | // Start at oper_input_base() and count operands |
| 12436 | unsigned idx0 = 1; |
| 12437 | unsigned idx1 = 1; // cmp |
| 12438 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // labl |
| 12439 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // |
| 12440 | if ( opnd_array(1)->ccode() == Assembler::notEqual) { |
| 12441 | st->print_raw("jp,u,s "); |
| 12442 | opnd_array(3)->ext_format(ra, this,idx3, st); // labl |
| 12443 | st->print_raw("\n\t"); |
| 12444 | st->print_raw("j"); |
| 12445 | opnd_array(1)->ext_format(ra, this,idx1, st); // cop |
| 12446 | st->print_raw(",u,s "); |
| 12447 | opnd_array(3)->ext_format(ra, this,idx3, st); // labl |
| 12448 | } else { |
| 12449 | st->print_raw("jp,u,s done\n\t"); |
| 12450 | st->print_raw("j"); |
| 12451 | opnd_array(1)->ext_format(ra, this,idx1, st); // cop |
| 12452 | st->print_raw(",u,s "); |
| 12453 | opnd_array(3)->ext_format(ra, this,idx3, st); // labl |
| 12454 | st->print_raw("\n\t"); |
| 12455 | st->print_raw("done:"); |
| 12456 | } |
| 12457 | st->print(" P=%f C=%f",_prob,_fcnt); |
| 12458 | } |
| 12459 | #endif |
| 12460 | #ifndef PRODUCT |
| 12461 | void cmpFastLockRTMNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12462 | // Start at oper_input_base() and count operands |
| 12463 | unsigned idx0 = 1; |
| 12464 | unsigned idx1 = 1; // object |
| 12465 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // box |
| 12466 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp |
| 12467 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // scr |
| 12468 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // cx1 |
| 12469 | unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // cx2 |
| 12470 | st->print_raw("fastlock "); |
| 12471 | opnd_array(1)->ext_format(ra, this,idx1, st); // object |
| 12472 | st->print_raw(","); |
| 12473 | opnd_array(2)->ext_format(ra, this,idx2, st); // box |
| 12474 | st->print_raw("\t! kills "); |
| 12475 | opnd_array(2)->ext_format(ra, this,idx2, st); // box |
| 12476 | st->print_raw(","); |
| 12477 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp |
| 12478 | st->print_raw(","); |
| 12479 | opnd_array(4)->ext_format(ra, this,idx4, st); // scr |
| 12480 | st->print_raw(","); |
| 12481 | opnd_array(5)->ext_format(ra, this,idx5, st); // cx1 |
| 12482 | st->print_raw(","); |
| 12483 | opnd_array(6)->ext_format(ra, this,idx6, st); // cx2 |
| 12484 | } |
| 12485 | #endif |
| 12486 | #ifndef PRODUCT |
| 12487 | void cmpFastLockNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12488 | // Start at oper_input_base() and count operands |
| 12489 | unsigned idx0 = 1; |
| 12490 | unsigned idx1 = 1; // object |
| 12491 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // box |
| 12492 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp |
| 12493 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // scr |
| 12494 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // cx1 |
| 12495 | st->print_raw("fastlock "); |
| 12496 | opnd_array(1)->ext_format(ra, this,idx1, st); // object |
| 12497 | st->print_raw(","); |
| 12498 | opnd_array(2)->ext_format(ra, this,idx2, st); // box |
| 12499 | st->print_raw("\t! kills "); |
| 12500 | opnd_array(2)->ext_format(ra, this,idx2, st); // box |
| 12501 | st->print_raw(","); |
| 12502 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp |
| 12503 | st->print_raw(","); |
| 12504 | opnd_array(4)->ext_format(ra, this,idx4, st); // scr |
| 12505 | } |
| 12506 | #endif |
| 12507 | #ifndef PRODUCT |
| 12508 | void cmpFastUnlockNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12509 | // Start at oper_input_base() and count operands |
| 12510 | unsigned idx0 = 1; |
| 12511 | unsigned idx1 = 1; // object |
| 12512 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // box |
| 12513 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp |
| 12514 | st->print_raw("fastunlock "); |
| 12515 | opnd_array(1)->ext_format(ra, this,idx1, st); // object |
| 12516 | st->print_raw(","); |
| 12517 | opnd_array(2)->ext_format(ra, this,idx2, st); // box |
| 12518 | st->print_raw("\t! kills "); |
| 12519 | opnd_array(2)->ext_format(ra, this,idx2, st); // box |
| 12520 | st->print_raw(","); |
| 12521 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp |
| 12522 | } |
| 12523 | #endif |
| 12524 | #ifndef PRODUCT |
| 12525 | void safePoint_poll_tlsNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12526 | // Start at oper_input_base() and count operands |
| 12527 | unsigned idx0 = 5; |
| 12528 | unsigned idx1 = 5; // cr |
| 12529 | st->print_raw("testl rax, ["); |
| 12530 | opnd_array(1)->ext_format(ra, this,idx1, st); // poll |
| 12531 | st->print_raw("]\t"); |
| 12532 | st->print_raw("# Safepoint: poll for GC"); |
| 12533 | st->print_raw(""); |
| 12534 | if (_jvms) _jvms->format(ra, this, st); else st->print_cr(" No JVM State Info"); |
| 12535 | st->print(" # "); |
| 12536 | if( _jvms && _oop_map ) _oop_map->print_on(st); |
| 12537 | } |
| 12538 | #endif |
| 12539 | #ifndef PRODUCT |
| 12540 | void CallStaticJavaDirectNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12541 | st->print_raw("call,static "); |
| 12542 | if( _method ) _method->print_short_name(st); |
| 12543 | else st->print(" wrapper for: %s", _name); |
| 12544 | if( !_method ) dump_trap_args(st); |
| 12545 | st->cr(); |
| 12546 | if (_jvms) _jvms->format(ra, this, st); else st->print_cr(" No JVM State Info"); |
| 12547 | st->print(" # "); |
| 12548 | if( _jvms && _oop_map ) _oop_map->print_on(st); |
| 12549 | } |
| 12550 | #endif |
| 12551 | #ifndef PRODUCT |
| 12552 | void CallDynamicJavaDirectNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12553 | st->print_raw("movq rax, #Universe::non_oop_word()\n\t"); |
| 12554 | st->print_raw("call,dynamic "); |
| 12555 | _method->print_short_name(st); |
| 12556 | st->cr(); |
| 12557 | if (_jvms) _jvms->format(ra, this, st); else st->print_cr(" No JVM State Info"); |
| 12558 | st->print(" # "); |
| 12559 | if( _jvms && _oop_map ) _oop_map->print_on(st); |
| 12560 | } |
| 12561 | #endif |
| 12562 | #ifndef PRODUCT |
| 12563 | void CallRuntimeDirectNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12564 | st->print_raw("call,runtime "); |
| 12565 | st->print(" %s", _name); st->cr(); |
| 12566 | if (_jvms) _jvms->format(ra, this, st); else st->print_cr(" No JVM State Info"); |
| 12567 | st->print(" # "); |
| 12568 | if( _jvms && _oop_map ) _oop_map->print_on(st); |
| 12569 | } |
| 12570 | #endif |
| 12571 | #ifndef PRODUCT |
| 12572 | void CallLeafDirectNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12573 | st->print_raw("call_leaf,runtime "); |
| 12574 | st->print(" %s", _name); st->cr(); |
| 12575 | if (_jvms) _jvms->format(ra, this, st); else st->print_cr(" No JVM State Info"); |
| 12576 | st->print(" # "); |
| 12577 | if( _jvms && _oop_map ) _oop_map->print_on(st); |
| 12578 | } |
| 12579 | #endif |
| 12580 | #ifndef PRODUCT |
| 12581 | void CallLeafDirectVectorNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12582 | st->print_raw("call_leaf,vector "); |
| 12583 | st->print(" %s", _name); st->cr(); |
| 12584 | if (_jvms) _jvms->format(ra, this, st); else st->print_cr(" No JVM State Info"); |
| 12585 | st->print(" # "); |
| 12586 | if( _jvms && _oop_map ) _oop_map->print_on(st); |
| 12587 | } |
| 12588 | #endif |
| 12589 | #ifndef PRODUCT |
| 12590 | void CallNativeDirectNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12591 | st->print_raw("call_native "); |
| 12592 | st->print(" %s", _name); st->cr(); |
| 12593 | if (_jvms) _jvms->format(ra, this, st); else st->print_cr(" No JVM State Info"); |
| 12594 | st->print(" # "); |
| 12595 | if( _jvms && _oop_map ) _oop_map->print_on(st); |
| 12596 | } |
| 12597 | #endif |
| 12598 | #ifndef PRODUCT |
| 12599 | void CallLeafNoFPDirectNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12600 | st->print_raw("call_leaf_nofp,runtime "); |
| 12601 | st->print(" %s", _name); st->cr(); |
| 12602 | if (_jvms) _jvms->format(ra, this, st); else st->print_cr(" No JVM State Info"); |
| 12603 | st->print(" # "); |
| 12604 | if( _jvms && _oop_map ) _oop_map->print_on(st); |
| 12605 | } |
| 12606 | #endif |
| 12607 | #ifndef PRODUCT |
| 12608 | void RetNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12609 | st->print_raw("ret"); |
| 12610 | } |
| 12611 | #endif |
| 12612 | #ifndef PRODUCT |
| 12613 | void TailCalljmpIndNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12614 | // Start at oper_input_base() and count operands |
| 12615 | unsigned idx0 = 5; |
| 12616 | unsigned idx1 = 5; // method_ptr |
| 12617 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // |
| 12618 | st->print_raw("jmp "); |
| 12619 | opnd_array(1)->ext_format(ra, this,idx1, st); // jump_target |
| 12620 | st->print_raw("\t# rbx holds method"); |
| 12621 | } |
| 12622 | #endif |
| 12623 | #ifndef PRODUCT |
| 12624 | void tailjmpIndNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12625 | // Start at oper_input_base() and count operands |
| 12626 | unsigned idx0 = 5; |
| 12627 | unsigned idx1 = 5; // ex_oop |
| 12628 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // |
| 12629 | st->print_raw("popq rdx\t# pop return address\n\t"); |
| 12630 | st->print_raw("jmp "); |
| 12631 | opnd_array(1)->ext_format(ra, this,idx1, st); // jump_target |
| 12632 | } |
| 12633 | #endif |
| 12634 | #ifndef PRODUCT |
| 12635 | void CreateExceptionNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12636 | st->print_raw("# exception oop is in rax; no code emitted"); |
| 12637 | } |
| 12638 | #endif |
| 12639 | #ifndef PRODUCT |
| 12640 | void RethrowExceptionNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12641 | st->print_raw("jmp rethrow_stub"); |
| 12642 | } |
| 12643 | #endif |
| 12644 | #ifndef PRODUCT |
| 12645 | void tlsLoadPNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12646 | st->print_raw("# TLS is in R15"); |
| 12647 | } |
| 12648 | #endif |
| 12649 | #ifndef PRODUCT |
| 12650 | void ShouldNotReachHereNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12651 | st->print_raw("stop\t# ShouldNotReachHere"); |
| 12652 | } |
| 12653 | #endif |
| 12654 | #ifndef PRODUCT |
| 12655 | void setMaskNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12656 | // Start at oper_input_base() and count operands |
| 12657 | unsigned idx0 = 1; |
| 12658 | unsigned idx1 = 1; // src |
| 12659 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst |
| 12660 | st->print_raw("setvectmask "); |
| 12661 | opnd_array(2)->ext_format(ra, this,idx2, st); // dst |
| 12662 | st->print_raw(", "); |
| 12663 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 12664 | } |
| 12665 | #endif |
| 12666 | #ifndef PRODUCT |
| 12667 | void addF_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12668 | // Start at oper_input_base() and count operands |
| 12669 | unsigned idx0 = 1; |
| 12670 | unsigned idx1 = 1; // dst |
| 12671 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 12672 | st->print_raw("addss "); |
| 12673 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 12674 | st->print_raw(", "); |
| 12675 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 12676 | } |
| 12677 | #endif |
| 12678 | #ifndef PRODUCT |
| 12679 | void addF_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12680 | // Start at oper_input_base() and count operands |
| 12681 | unsigned idx0 = 2; |
| 12682 | unsigned idx1 = 2; // dst |
| 12683 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 12684 | st->print_raw("addss "); |
| 12685 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 12686 | st->print_raw(", "); |
| 12687 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 12688 | } |
| 12689 | #endif |
| 12690 | #ifndef PRODUCT |
| 12691 | void addF_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12692 | // Start at oper_input_base() and count operands |
| 12693 | unsigned idx0 = 2; |
| 12694 | unsigned idx1 = 2; // src |
| 12695 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst |
| 12696 | st->print_raw("addss "); |
| 12697 | opnd_array(2)->ext_format(ra, this,idx2, st); // dst |
| 12698 | st->print_raw(", "); |
| 12699 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 12700 | } |
| 12701 | #endif |
| 12702 | #ifndef PRODUCT |
| 12703 | void addF_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12704 | // Start at oper_input_base() and count operands |
| 12705 | unsigned idx0 = 1; |
| 12706 | unsigned idx1 = 1; // dst |
| 12707 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con |
| 12708 | st->print_raw("addss "); |
| 12709 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 12710 | st->print_raw(", ["); |
| 12711 | st->print("constant table base + #%d", constant_offset_unchecked()); |
| 12712 | st->print_raw("]\t# load from constant table: float="); |
| 12713 | opnd_array(2)->ext_format(ra, this,idx2, st); // con |
| 12714 | } |
| 12715 | #endif |
| 12716 | #ifndef PRODUCT |
| 12717 | void addF_reg_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12718 | // Start at oper_input_base() and count operands |
| 12719 | unsigned idx0 = 1; |
| 12720 | unsigned idx1 = 1; // src1 |
| 12721 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 12722 | st->print_raw("vaddss "); |
| 12723 | opnd_array(0)->int_format(ra, this, st); // dst |
| 12724 | st->print_raw(", "); |
| 12725 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 12726 | st->print_raw(", "); |
| 12727 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 12728 | } |
| 12729 | #endif |
| 12730 | #ifndef PRODUCT |
| 12731 | void addF_reg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12732 | // Start at oper_input_base() and count operands |
| 12733 | unsigned idx0 = 2; |
| 12734 | unsigned idx1 = 2; // src1 |
| 12735 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 12736 | st->print_raw("vaddss "); |
| 12737 | opnd_array(0)->int_format(ra, this, st); // dst |
| 12738 | st->print_raw(", "); |
| 12739 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 12740 | st->print_raw(", "); |
| 12741 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 12742 | } |
| 12743 | #endif |
| 12744 | #ifndef PRODUCT |
| 12745 | void addF_reg_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12746 | // Start at oper_input_base() and count operands |
| 12747 | unsigned idx0 = 2; |
| 12748 | unsigned idx1 = 2; // src2 |
| 12749 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src1 |
| 12750 | st->print_raw("vaddss "); |
| 12751 | opnd_array(0)->int_format(ra, this, st); // dst |
| 12752 | st->print_raw(", "); |
| 12753 | opnd_array(2)->ext_format(ra, this,idx2, st); // src1 |
| 12754 | st->print_raw(", "); |
| 12755 | opnd_array(1)->ext_format(ra, this,idx1, st); // src2 |
| 12756 | } |
| 12757 | #endif |
| 12758 | #ifndef PRODUCT |
| 12759 | void addF_reg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12760 | // Start at oper_input_base() and count operands |
| 12761 | unsigned idx0 = 1; |
| 12762 | unsigned idx1 = 1; // src |
| 12763 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con |
| 12764 | st->print_raw("vaddss "); |
| 12765 | opnd_array(0)->int_format(ra, this, st); // dst |
| 12766 | st->print_raw(", "); |
| 12767 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 12768 | st->print_raw(", ["); |
| 12769 | st->print("constant table base + #%d", constant_offset_unchecked()); |
| 12770 | st->print_raw("]\t# load from constant table: float="); |
| 12771 | opnd_array(2)->ext_format(ra, this,idx2, st); // con |
| 12772 | } |
| 12773 | #endif |
| 12774 | #ifndef PRODUCT |
| 12775 | void addD_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12776 | // Start at oper_input_base() and count operands |
| 12777 | unsigned idx0 = 1; |
| 12778 | unsigned idx1 = 1; // dst |
| 12779 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 12780 | st->print_raw("addsd "); |
| 12781 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 12782 | st->print_raw(", "); |
| 12783 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 12784 | } |
| 12785 | #endif |
| 12786 | #ifndef PRODUCT |
| 12787 | void addD_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12788 | // Start at oper_input_base() and count operands |
| 12789 | unsigned idx0 = 2; |
| 12790 | unsigned idx1 = 2; // dst |
| 12791 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 12792 | st->print_raw("addsd "); |
| 12793 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 12794 | st->print_raw(", "); |
| 12795 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 12796 | } |
| 12797 | #endif |
| 12798 | #ifndef PRODUCT |
| 12799 | void addD_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12800 | // Start at oper_input_base() and count operands |
| 12801 | unsigned idx0 = 2; |
| 12802 | unsigned idx1 = 2; // src |
| 12803 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst |
| 12804 | st->print_raw("addsd "); |
| 12805 | opnd_array(2)->ext_format(ra, this,idx2, st); // dst |
| 12806 | st->print_raw(", "); |
| 12807 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 12808 | } |
| 12809 | #endif |
| 12810 | #ifndef PRODUCT |
| 12811 | void addD_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12812 | // Start at oper_input_base() and count operands |
| 12813 | unsigned idx0 = 1; |
| 12814 | unsigned idx1 = 1; // dst |
| 12815 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con |
| 12816 | st->print_raw("addsd "); |
| 12817 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 12818 | st->print_raw(", ["); |
| 12819 | st->print("constant table base + #%d", constant_offset_unchecked()); |
| 12820 | st->print_raw("]\t# load from constant table: double="); |
| 12821 | opnd_array(2)->ext_format(ra, this,idx2, st); // con |
| 12822 | } |
| 12823 | #endif |
| 12824 | #ifndef PRODUCT |
| 12825 | void addD_reg_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12826 | // Start at oper_input_base() and count operands |
| 12827 | unsigned idx0 = 1; |
| 12828 | unsigned idx1 = 1; // src1 |
| 12829 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 12830 | st->print_raw("vaddsd "); |
| 12831 | opnd_array(0)->int_format(ra, this, st); // dst |
| 12832 | st->print_raw(", "); |
| 12833 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 12834 | st->print_raw(", "); |
| 12835 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 12836 | } |
| 12837 | #endif |
| 12838 | #ifndef PRODUCT |
| 12839 | void addD_reg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12840 | // Start at oper_input_base() and count operands |
| 12841 | unsigned idx0 = 2; |
| 12842 | unsigned idx1 = 2; // src1 |
| 12843 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 12844 | st->print_raw("vaddsd "); |
| 12845 | opnd_array(0)->int_format(ra, this, st); // dst |
| 12846 | st->print_raw(", "); |
| 12847 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 12848 | st->print_raw(", "); |
| 12849 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 12850 | } |
| 12851 | #endif |
| 12852 | #ifndef PRODUCT |
| 12853 | void addD_reg_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12854 | // Start at oper_input_base() and count operands |
| 12855 | unsigned idx0 = 2; |
| 12856 | unsigned idx1 = 2; // src2 |
| 12857 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src1 |
| 12858 | st->print_raw("vaddsd "); |
| 12859 | opnd_array(0)->int_format(ra, this, st); // dst |
| 12860 | st->print_raw(", "); |
| 12861 | opnd_array(2)->ext_format(ra, this,idx2, st); // src1 |
| 12862 | st->print_raw(", "); |
| 12863 | opnd_array(1)->ext_format(ra, this,idx1, st); // src2 |
| 12864 | } |
| 12865 | #endif |
| 12866 | #ifndef PRODUCT |
| 12867 | void addD_reg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12868 | // Start at oper_input_base() and count operands |
| 12869 | unsigned idx0 = 1; |
| 12870 | unsigned idx1 = 1; // src |
| 12871 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con |
| 12872 | st->print_raw("vaddsd "); |
| 12873 | opnd_array(0)->int_format(ra, this, st); // dst |
| 12874 | st->print_raw(", "); |
| 12875 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 12876 | st->print_raw(", ["); |
| 12877 | st->print("constant table base + #%d", constant_offset_unchecked()); |
| 12878 | st->print_raw("]\t# load from constant table: double="); |
| 12879 | opnd_array(2)->ext_format(ra, this,idx2, st); // con |
| 12880 | } |
| 12881 | #endif |
| 12882 | #ifndef PRODUCT |
| 12883 | void subF_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12884 | // Start at oper_input_base() and count operands |
| 12885 | unsigned idx0 = 1; |
| 12886 | unsigned idx1 = 1; // dst |
| 12887 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 12888 | st->print_raw("subss "); |
| 12889 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 12890 | st->print_raw(", "); |
| 12891 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 12892 | } |
| 12893 | #endif |
| 12894 | #ifndef PRODUCT |
| 12895 | void subF_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12896 | // Start at oper_input_base() and count operands |
| 12897 | unsigned idx0 = 2; |
| 12898 | unsigned idx1 = 2; // dst |
| 12899 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 12900 | st->print_raw("subss "); |
| 12901 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 12902 | st->print_raw(", "); |
| 12903 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 12904 | } |
| 12905 | #endif |
| 12906 | #ifndef PRODUCT |
| 12907 | void subF_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12908 | // Start at oper_input_base() and count operands |
| 12909 | unsigned idx0 = 1; |
| 12910 | unsigned idx1 = 1; // dst |
| 12911 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con |
| 12912 | st->print_raw("subss "); |
| 12913 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 12914 | st->print_raw(", ["); |
| 12915 | st->print("constant table base + #%d", constant_offset_unchecked()); |
| 12916 | st->print_raw("]\t# load from constant table: float="); |
| 12917 | opnd_array(2)->ext_format(ra, this,idx2, st); // con |
| 12918 | } |
| 12919 | #endif |
| 12920 | #ifndef PRODUCT |
| 12921 | void subF_reg_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12922 | // Start at oper_input_base() and count operands |
| 12923 | unsigned idx0 = 1; |
| 12924 | unsigned idx1 = 1; // src1 |
| 12925 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 12926 | st->print_raw("vsubss "); |
| 12927 | opnd_array(0)->int_format(ra, this, st); // dst |
| 12928 | st->print_raw(", "); |
| 12929 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 12930 | st->print_raw(", "); |
| 12931 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 12932 | } |
| 12933 | #endif |
| 12934 | #ifndef PRODUCT |
| 12935 | void subF_reg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12936 | // Start at oper_input_base() and count operands |
| 12937 | unsigned idx0 = 2; |
| 12938 | unsigned idx1 = 2; // src1 |
| 12939 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 12940 | st->print_raw("vsubss "); |
| 12941 | opnd_array(0)->int_format(ra, this, st); // dst |
| 12942 | st->print_raw(", "); |
| 12943 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 12944 | st->print_raw(", "); |
| 12945 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 12946 | } |
| 12947 | #endif |
| 12948 | #ifndef PRODUCT |
| 12949 | void subF_reg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12950 | // Start at oper_input_base() and count operands |
| 12951 | unsigned idx0 = 1; |
| 12952 | unsigned idx1 = 1; // src |
| 12953 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con |
| 12954 | st->print_raw("vsubss "); |
| 12955 | opnd_array(0)->int_format(ra, this, st); // dst |
| 12956 | st->print_raw(", "); |
| 12957 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 12958 | st->print_raw(", ["); |
| 12959 | st->print("constant table base + #%d", constant_offset_unchecked()); |
| 12960 | st->print_raw("]\t# load from constant table: float="); |
| 12961 | opnd_array(2)->ext_format(ra, this,idx2, st); // con |
| 12962 | } |
| 12963 | #endif |
| 12964 | #ifndef PRODUCT |
| 12965 | void subD_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12966 | // Start at oper_input_base() and count operands |
| 12967 | unsigned idx0 = 1; |
| 12968 | unsigned idx1 = 1; // dst |
| 12969 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 12970 | st->print_raw("subsd "); |
| 12971 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 12972 | st->print_raw(", "); |
| 12973 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 12974 | } |
| 12975 | #endif |
| 12976 | #ifndef PRODUCT |
| 12977 | void subD_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12978 | // Start at oper_input_base() and count operands |
| 12979 | unsigned idx0 = 2; |
| 12980 | unsigned idx1 = 2; // dst |
| 12981 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 12982 | st->print_raw("subsd "); |
| 12983 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 12984 | st->print_raw(", "); |
| 12985 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 12986 | } |
| 12987 | #endif |
| 12988 | #ifndef PRODUCT |
| 12989 | void subD_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 12990 | // Start at oper_input_base() and count operands |
| 12991 | unsigned idx0 = 1; |
| 12992 | unsigned idx1 = 1; // dst |
| 12993 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con |
| 12994 | st->print_raw("subsd "); |
| 12995 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 12996 | st->print_raw(", ["); |
| 12997 | st->print("constant table base + #%d", constant_offset_unchecked()); |
| 12998 | st->print_raw("]\t# load from constant table: double="); |
| 12999 | opnd_array(2)->ext_format(ra, this,idx2, st); // con |
| 13000 | } |
| 13001 | #endif |
| 13002 | #ifndef PRODUCT |
| 13003 | void subD_reg_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13004 | // Start at oper_input_base() and count operands |
| 13005 | unsigned idx0 = 1; |
| 13006 | unsigned idx1 = 1; // src1 |
| 13007 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 13008 | st->print_raw("vsubsd "); |
| 13009 | opnd_array(0)->int_format(ra, this, st); // dst |
| 13010 | st->print_raw(", "); |
| 13011 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 13012 | st->print_raw(", "); |
| 13013 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 13014 | } |
| 13015 | #endif |
| 13016 | #ifndef PRODUCT |
| 13017 | void subD_reg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13018 | // Start at oper_input_base() and count operands |
| 13019 | unsigned idx0 = 2; |
| 13020 | unsigned idx1 = 2; // src1 |
| 13021 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 13022 | st->print_raw("vsubsd "); |
| 13023 | opnd_array(0)->int_format(ra, this, st); // dst |
| 13024 | st->print_raw(", "); |
| 13025 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 13026 | st->print_raw(", "); |
| 13027 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 13028 | } |
| 13029 | #endif |
| 13030 | #ifndef PRODUCT |
| 13031 | void subD_reg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13032 | // Start at oper_input_base() and count operands |
| 13033 | unsigned idx0 = 1; |
| 13034 | unsigned idx1 = 1; // src |
| 13035 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con |
| 13036 | st->print_raw("vsubsd "); |
| 13037 | opnd_array(0)->int_format(ra, this, st); // dst |
| 13038 | st->print_raw(", "); |
| 13039 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 13040 | st->print_raw(", ["); |
| 13041 | st->print("constant table base + #%d", constant_offset_unchecked()); |
| 13042 | st->print_raw("]\t# load from constant table: double="); |
| 13043 | opnd_array(2)->ext_format(ra, this,idx2, st); // con |
| 13044 | } |
| 13045 | #endif |
| 13046 | #ifndef PRODUCT |
| 13047 | void mulF_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13048 | // Start at oper_input_base() and count operands |
| 13049 | unsigned idx0 = 1; |
| 13050 | unsigned idx1 = 1; // dst |
| 13051 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 13052 | st->print_raw("mulss "); |
| 13053 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 13054 | st->print_raw(", "); |
| 13055 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 13056 | } |
| 13057 | #endif |
| 13058 | #ifndef PRODUCT |
| 13059 | void mulF_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13060 | // Start at oper_input_base() and count operands |
| 13061 | unsigned idx0 = 2; |
| 13062 | unsigned idx1 = 2; // dst |
| 13063 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 13064 | st->print_raw("mulss "); |
| 13065 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 13066 | st->print_raw(", "); |
| 13067 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 13068 | } |
| 13069 | #endif |
| 13070 | #ifndef PRODUCT |
| 13071 | void mulF_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13072 | // Start at oper_input_base() and count operands |
| 13073 | unsigned idx0 = 2; |
| 13074 | unsigned idx1 = 2; // src |
| 13075 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst |
| 13076 | st->print_raw("mulss "); |
| 13077 | opnd_array(2)->ext_format(ra, this,idx2, st); // dst |
| 13078 | st->print_raw(", "); |
| 13079 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 13080 | } |
| 13081 | #endif |
| 13082 | #ifndef PRODUCT |
| 13083 | void mulF_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13084 | // Start at oper_input_base() and count operands |
| 13085 | unsigned idx0 = 1; |
| 13086 | unsigned idx1 = 1; // dst |
| 13087 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con |
| 13088 | st->print_raw("mulss "); |
| 13089 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 13090 | st->print_raw(", ["); |
| 13091 | st->print("constant table base + #%d", constant_offset_unchecked()); |
| 13092 | st->print_raw("]\t# load from constant table: float="); |
| 13093 | opnd_array(2)->ext_format(ra, this,idx2, st); // con |
| 13094 | } |
| 13095 | #endif |
| 13096 | #ifndef PRODUCT |
| 13097 | void mulF_reg_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13098 | // Start at oper_input_base() and count operands |
| 13099 | unsigned idx0 = 1; |
| 13100 | unsigned idx1 = 1; // src1 |
| 13101 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 13102 | st->print_raw("vmulss "); |
| 13103 | opnd_array(0)->int_format(ra, this, st); // dst |
| 13104 | st->print_raw(", "); |
| 13105 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 13106 | st->print_raw(", "); |
| 13107 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 13108 | } |
| 13109 | #endif |
| 13110 | #ifndef PRODUCT |
| 13111 | void mulF_reg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13112 | // Start at oper_input_base() and count operands |
| 13113 | unsigned idx0 = 2; |
| 13114 | unsigned idx1 = 2; // src1 |
| 13115 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 13116 | st->print_raw("vmulss "); |
| 13117 | opnd_array(0)->int_format(ra, this, st); // dst |
| 13118 | st->print_raw(", "); |
| 13119 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 13120 | st->print_raw(", "); |
| 13121 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 13122 | } |
| 13123 | #endif |
| 13124 | #ifndef PRODUCT |
| 13125 | void mulF_reg_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13126 | // Start at oper_input_base() and count operands |
| 13127 | unsigned idx0 = 2; |
| 13128 | unsigned idx1 = 2; // src2 |
| 13129 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src1 |
| 13130 | st->print_raw("vmulss "); |
| 13131 | opnd_array(0)->int_format(ra, this, st); // dst |
| 13132 | st->print_raw(", "); |
| 13133 | opnd_array(2)->ext_format(ra, this,idx2, st); // src1 |
| 13134 | st->print_raw(", "); |
| 13135 | opnd_array(1)->ext_format(ra, this,idx1, st); // src2 |
| 13136 | } |
| 13137 | #endif |
| 13138 | #ifndef PRODUCT |
| 13139 | void mulF_reg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13140 | // Start at oper_input_base() and count operands |
| 13141 | unsigned idx0 = 1; |
| 13142 | unsigned idx1 = 1; // src |
| 13143 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con |
| 13144 | st->print_raw("vmulss "); |
| 13145 | opnd_array(0)->int_format(ra, this, st); // dst |
| 13146 | st->print_raw(", "); |
| 13147 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 13148 | st->print_raw(", ["); |
| 13149 | st->print("constant table base + #%d", constant_offset_unchecked()); |
| 13150 | st->print_raw("]\t# load from constant table: float="); |
| 13151 | opnd_array(2)->ext_format(ra, this,idx2, st); // con |
| 13152 | } |
| 13153 | #endif |
| 13154 | #ifndef PRODUCT |
| 13155 | void mulD_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13156 | // Start at oper_input_base() and count operands |
| 13157 | unsigned idx0 = 1; |
| 13158 | unsigned idx1 = 1; // dst |
| 13159 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 13160 | st->print_raw("mulsd "); |
| 13161 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 13162 | st->print_raw(", "); |
| 13163 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 13164 | } |
| 13165 | #endif |
| 13166 | #ifndef PRODUCT |
| 13167 | void mulD_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13168 | // Start at oper_input_base() and count operands |
| 13169 | unsigned idx0 = 2; |
| 13170 | unsigned idx1 = 2; // dst |
| 13171 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 13172 | st->print_raw("mulsd "); |
| 13173 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 13174 | st->print_raw(", "); |
| 13175 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 13176 | } |
| 13177 | #endif |
| 13178 | #ifndef PRODUCT |
| 13179 | void mulD_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13180 | // Start at oper_input_base() and count operands |
| 13181 | unsigned idx0 = 2; |
| 13182 | unsigned idx1 = 2; // src |
| 13183 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst |
| 13184 | st->print_raw("mulsd "); |
| 13185 | opnd_array(2)->ext_format(ra, this,idx2, st); // dst |
| 13186 | st->print_raw(", "); |
| 13187 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 13188 | } |
| 13189 | #endif |
| 13190 | #ifndef PRODUCT |
| 13191 | void mulD_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13192 | // Start at oper_input_base() and count operands |
| 13193 | unsigned idx0 = 1; |
| 13194 | unsigned idx1 = 1; // dst |
| 13195 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con |
| 13196 | st->print_raw("mulsd "); |
| 13197 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 13198 | st->print_raw(", ["); |
| 13199 | st->print("constant table base + #%d", constant_offset_unchecked()); |
| 13200 | st->print_raw("]\t# load from constant table: double="); |
| 13201 | opnd_array(2)->ext_format(ra, this,idx2, st); // con |
| 13202 | } |
| 13203 | #endif |
| 13204 | #ifndef PRODUCT |
| 13205 | void mulD_reg_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13206 | // Start at oper_input_base() and count operands |
| 13207 | unsigned idx0 = 1; |
| 13208 | unsigned idx1 = 1; // src1 |
| 13209 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 13210 | st->print_raw("vmulsd "); |
| 13211 | opnd_array(0)->int_format(ra, this, st); // dst |
| 13212 | st->print_raw(", "); |
| 13213 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 13214 | st->print_raw(", "); |
| 13215 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 13216 | } |
| 13217 | #endif |
| 13218 | #ifndef PRODUCT |
| 13219 | void mulD_reg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13220 | // Start at oper_input_base() and count operands |
| 13221 | unsigned idx0 = 2; |
| 13222 | unsigned idx1 = 2; // src1 |
| 13223 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 13224 | st->print_raw("vmulsd "); |
| 13225 | opnd_array(0)->int_format(ra, this, st); // dst |
| 13226 | st->print_raw(", "); |
| 13227 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 13228 | st->print_raw(", "); |
| 13229 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 13230 | } |
| 13231 | #endif |
| 13232 | #ifndef PRODUCT |
| 13233 | void mulD_reg_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13234 | // Start at oper_input_base() and count operands |
| 13235 | unsigned idx0 = 2; |
| 13236 | unsigned idx1 = 2; // src2 |
| 13237 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src1 |
| 13238 | st->print_raw("vmulsd "); |
| 13239 | opnd_array(0)->int_format(ra, this, st); // dst |
| 13240 | st->print_raw(", "); |
| 13241 | opnd_array(2)->ext_format(ra, this,idx2, st); // src1 |
| 13242 | st->print_raw(", "); |
| 13243 | opnd_array(1)->ext_format(ra, this,idx1, st); // src2 |
| 13244 | } |
| 13245 | #endif |
| 13246 | #ifndef PRODUCT |
| 13247 | void mulD_reg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13248 | // Start at oper_input_base() and count operands |
| 13249 | unsigned idx0 = 1; |
| 13250 | unsigned idx1 = 1; // src |
| 13251 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con |
| 13252 | st->print_raw("vmulsd "); |
| 13253 | opnd_array(0)->int_format(ra, this, st); // dst |
| 13254 | st->print_raw(", "); |
| 13255 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 13256 | st->print_raw(", ["); |
| 13257 | st->print("constant table base + #%d", constant_offset_unchecked()); |
| 13258 | st->print_raw("]\t# load from constant table: double="); |
| 13259 | opnd_array(2)->ext_format(ra, this,idx2, st); // con |
| 13260 | } |
| 13261 | #endif |
| 13262 | #ifndef PRODUCT |
| 13263 | void divF_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13264 | // Start at oper_input_base() and count operands |
| 13265 | unsigned idx0 = 1; |
| 13266 | unsigned idx1 = 1; // dst |
| 13267 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 13268 | st->print_raw("divss "); |
| 13269 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 13270 | st->print_raw(", "); |
| 13271 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 13272 | } |
| 13273 | #endif |
| 13274 | #ifndef PRODUCT |
| 13275 | void divF_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13276 | // Start at oper_input_base() and count operands |
| 13277 | unsigned idx0 = 2; |
| 13278 | unsigned idx1 = 2; // dst |
| 13279 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 13280 | st->print_raw("divss "); |
| 13281 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 13282 | st->print_raw(", "); |
| 13283 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 13284 | } |
| 13285 | #endif |
| 13286 | #ifndef PRODUCT |
| 13287 | void divF_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13288 | // Start at oper_input_base() and count operands |
| 13289 | unsigned idx0 = 1; |
| 13290 | unsigned idx1 = 1; // dst |
| 13291 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con |
| 13292 | st->print_raw("divss "); |
| 13293 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 13294 | st->print_raw(", ["); |
| 13295 | st->print("constant table base + #%d", constant_offset_unchecked()); |
| 13296 | st->print_raw("]\t# load from constant table: float="); |
| 13297 | opnd_array(2)->ext_format(ra, this,idx2, st); // con |
| 13298 | } |
| 13299 | #endif |
| 13300 | #ifndef PRODUCT |
| 13301 | void divF_reg_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13302 | // Start at oper_input_base() and count operands |
| 13303 | unsigned idx0 = 1; |
| 13304 | unsigned idx1 = 1; // src1 |
| 13305 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 13306 | st->print_raw("vdivss "); |
| 13307 | opnd_array(0)->int_format(ra, this, st); // dst |
| 13308 | st->print_raw(", "); |
| 13309 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 13310 | st->print_raw(", "); |
| 13311 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 13312 | } |
| 13313 | #endif |
| 13314 | #ifndef PRODUCT |
| 13315 | void divF_reg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13316 | // Start at oper_input_base() and count operands |
| 13317 | unsigned idx0 = 2; |
| 13318 | unsigned idx1 = 2; // src1 |
| 13319 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 13320 | st->print_raw("vdivss "); |
| 13321 | opnd_array(0)->int_format(ra, this, st); // dst |
| 13322 | st->print_raw(", "); |
| 13323 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 13324 | st->print_raw(", "); |
| 13325 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 13326 | } |
| 13327 | #endif |
| 13328 | #ifndef PRODUCT |
| 13329 | void divF_reg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13330 | // Start at oper_input_base() and count operands |
| 13331 | unsigned idx0 = 1; |
| 13332 | unsigned idx1 = 1; // src |
| 13333 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con |
| 13334 | st->print_raw("vdivss "); |
| 13335 | opnd_array(0)->int_format(ra, this, st); // dst |
| 13336 | st->print_raw(", "); |
| 13337 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 13338 | st->print_raw(", ["); |
| 13339 | st->print("constant table base + #%d", constant_offset_unchecked()); |
| 13340 | st->print_raw("]\t# load from constant table: float="); |
| 13341 | opnd_array(2)->ext_format(ra, this,idx2, st); // con |
| 13342 | } |
| 13343 | #endif |
| 13344 | #ifndef PRODUCT |
| 13345 | void divD_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13346 | // Start at oper_input_base() and count operands |
| 13347 | unsigned idx0 = 1; |
| 13348 | unsigned idx1 = 1; // dst |
| 13349 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 13350 | st->print_raw("divsd "); |
| 13351 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 13352 | st->print_raw(", "); |
| 13353 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 13354 | } |
| 13355 | #endif |
| 13356 | #ifndef PRODUCT |
| 13357 | void divD_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13358 | // Start at oper_input_base() and count operands |
| 13359 | unsigned idx0 = 2; |
| 13360 | unsigned idx1 = 2; // dst |
| 13361 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 13362 | st->print_raw("divsd "); |
| 13363 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 13364 | st->print_raw(", "); |
| 13365 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 13366 | } |
| 13367 | #endif |
| 13368 | #ifndef PRODUCT |
| 13369 | void divD_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13370 | // Start at oper_input_base() and count operands |
| 13371 | unsigned idx0 = 1; |
| 13372 | unsigned idx1 = 1; // dst |
| 13373 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con |
| 13374 | st->print_raw("divsd "); |
| 13375 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 13376 | st->print_raw(", ["); |
| 13377 | st->print("constant table base + #%d", constant_offset_unchecked()); |
| 13378 | st->print_raw("]\t# load from constant table: double="); |
| 13379 | opnd_array(2)->ext_format(ra, this,idx2, st); // con |
| 13380 | } |
| 13381 | #endif |
| 13382 | #ifndef PRODUCT |
| 13383 | void divD_reg_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13384 | // Start at oper_input_base() and count operands |
| 13385 | unsigned idx0 = 1; |
| 13386 | unsigned idx1 = 1; // src1 |
| 13387 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 13388 | st->print_raw("vdivsd "); |
| 13389 | opnd_array(0)->int_format(ra, this, st); // dst |
| 13390 | st->print_raw(", "); |
| 13391 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 13392 | st->print_raw(", "); |
| 13393 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 13394 | } |
| 13395 | #endif |
| 13396 | #ifndef PRODUCT |
| 13397 | void divD_reg_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13398 | // Start at oper_input_base() and count operands |
| 13399 | unsigned idx0 = 2; |
| 13400 | unsigned idx1 = 2; // src1 |
| 13401 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 13402 | st->print_raw("vdivsd "); |
| 13403 | opnd_array(0)->int_format(ra, this, st); // dst |
| 13404 | st->print_raw(", "); |
| 13405 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 13406 | st->print_raw(", "); |
| 13407 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 13408 | } |
| 13409 | #endif |
| 13410 | #ifndef PRODUCT |
| 13411 | void divD_reg_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13412 | // Start at oper_input_base() and count operands |
| 13413 | unsigned idx0 = 1; |
| 13414 | unsigned idx1 = 1; // src |
| 13415 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con |
| 13416 | st->print_raw("vdivsd "); |
| 13417 | opnd_array(0)->int_format(ra, this, st); // dst |
| 13418 | st->print_raw(", "); |
| 13419 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 13420 | st->print_raw(", ["); |
| 13421 | st->print("constant table base + #%d", constant_offset_unchecked()); |
| 13422 | st->print_raw("]\t# load from constant table: double="); |
| 13423 | opnd_array(2)->ext_format(ra, this,idx2, st); // con |
| 13424 | } |
| 13425 | #endif |
| 13426 | #ifndef PRODUCT |
| 13427 | void absF_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13428 | // Start at oper_input_base() and count operands |
| 13429 | unsigned idx0 = 1; |
| 13430 | unsigned idx1 = 1; // dst |
| 13431 | st->print_raw("andps "); |
| 13432 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 13433 | st->print_raw(", [0x7fffffff]\t# abs float by sign masking"); |
| 13434 | } |
| 13435 | #endif |
| 13436 | #ifndef PRODUCT |
| 13437 | void absF_reg_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13438 | // Start at oper_input_base() and count operands |
| 13439 | unsigned idx0 = 1; |
| 13440 | unsigned idx1 = 1; // src |
| 13441 | st->print_raw("vandps "); |
| 13442 | opnd_array(0)->int_format(ra, this, st); // dst |
| 13443 | st->print_raw(", "); |
| 13444 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 13445 | st->print_raw(", [0x7fffffff]\t# abs float by sign masking"); |
| 13446 | } |
| 13447 | #endif |
| 13448 | #ifndef PRODUCT |
| 13449 | void absD_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13450 | // Start at oper_input_base() and count operands |
| 13451 | unsigned idx0 = 1; |
| 13452 | unsigned idx1 = 1; // dst |
| 13453 | st->print_raw("andpd "); |
| 13454 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 13455 | st->print_raw(", [0x7fffffffffffffff]\t"); |
| 13456 | st->print_raw("# abs double by sign masking"); |
| 13457 | } |
| 13458 | #endif |
| 13459 | #ifndef PRODUCT |
| 13460 | void absD_reg_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13461 | // Start at oper_input_base() and count operands |
| 13462 | unsigned idx0 = 1; |
| 13463 | unsigned idx1 = 1; // src |
| 13464 | st->print_raw("vandpd "); |
| 13465 | opnd_array(0)->int_format(ra, this, st); // dst |
| 13466 | st->print_raw(", "); |
| 13467 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 13468 | st->print_raw(", [0x7fffffffffffffff]\t"); |
| 13469 | st->print_raw("# abs double by sign masking"); |
| 13470 | } |
| 13471 | #endif |
| 13472 | #ifndef PRODUCT |
| 13473 | void negF_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13474 | // Start at oper_input_base() and count operands |
| 13475 | unsigned idx0 = 1; |
| 13476 | unsigned idx1 = 1; // dst |
| 13477 | st->print_raw("xorps "); |
| 13478 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 13479 | st->print_raw(", [0x80000000]\t# neg float by sign flipping"); |
| 13480 | } |
| 13481 | #endif |
| 13482 | #ifndef PRODUCT |
| 13483 | void negF_reg_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13484 | // Start at oper_input_base() and count operands |
| 13485 | unsigned idx0 = 1; |
| 13486 | unsigned idx1 = 1; // src |
| 13487 | st->print_raw("vnegatess "); |
| 13488 | opnd_array(0)->int_format(ra, this, st); // dst |
| 13489 | st->print_raw(", "); |
| 13490 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 13491 | st->print_raw(", [0x80000000]\t# neg float by sign flipping"); |
| 13492 | } |
| 13493 | #endif |
| 13494 | #ifndef PRODUCT |
| 13495 | void negD_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13496 | // Start at oper_input_base() and count operands |
| 13497 | unsigned idx0 = 1; |
| 13498 | unsigned idx1 = 1; // dst |
| 13499 | st->print_raw("xorpd "); |
| 13500 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 13501 | st->print_raw(", [0x8000000000000000]\t"); |
| 13502 | st->print_raw("# neg double by sign flipping"); |
| 13503 | } |
| 13504 | #endif |
| 13505 | #ifndef PRODUCT |
| 13506 | void negD_reg_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13507 | // Start at oper_input_base() and count operands |
| 13508 | unsigned idx0 = 1; |
| 13509 | unsigned idx1 = 1; // src |
| 13510 | st->print_raw("vnegatesd "); |
| 13511 | opnd_array(0)->int_format(ra, this, st); // dst |
| 13512 | st->print_raw(", "); |
| 13513 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 13514 | st->print_raw(", [0x8000000000000000]\t"); |
| 13515 | st->print_raw("# neg double by sign flipping"); |
| 13516 | } |
| 13517 | #endif |
| 13518 | #ifndef PRODUCT |
| 13519 | void sqrtF_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13520 | // Start at oper_input_base() and count operands |
| 13521 | unsigned idx0 = 1; |
| 13522 | unsigned idx1 = 1; // dst |
| 13523 | st->print_raw("sqrtss "); |
| 13524 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 13525 | st->print_raw(", "); |
| 13526 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 13527 | } |
| 13528 | #endif |
| 13529 | #ifndef PRODUCT |
| 13530 | void sqrtD_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13531 | // Start at oper_input_base() and count operands |
| 13532 | unsigned idx0 = 1; |
| 13533 | unsigned idx1 = 1; // dst |
| 13534 | st->print_raw("sqrtsd "); |
| 13535 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 13536 | st->print_raw(", "); |
| 13537 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 13538 | } |
| 13539 | #endif |
| 13540 | #ifndef PRODUCT |
| 13541 | void reinterpret_maskNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13542 | // Start at oper_input_base() and count operands |
| 13543 | unsigned idx0 = 1; |
| 13544 | unsigned idx1 = 1; // dst |
| 13545 | st->print_raw("vector_reinterpret "); |
| 13546 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 13547 | st->print_raw("\t!"); |
| 13548 | } |
| 13549 | #endif |
| 13550 | #ifndef PRODUCT |
| 13551 | void reinterpret_mask_W2BNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13552 | // Start at oper_input_base() and count operands |
| 13553 | unsigned idx0 = 1; |
| 13554 | unsigned idx1 = 1; // src |
| 13555 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // xtmp |
| 13556 | st->print_raw("vector_mask_reinterpret_W2B "); |
| 13557 | opnd_array(0)->int_format(ra, this, st); // dst |
| 13558 | st->print_raw(" "); |
| 13559 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 13560 | st->print_raw("\t!"); |
| 13561 | } |
| 13562 | #endif |
| 13563 | #ifndef PRODUCT |
| 13564 | void reinterpret_mask_D2BNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13565 | // Start at oper_input_base() and count operands |
| 13566 | unsigned idx0 = 1; |
| 13567 | unsigned idx1 = 1; // src |
| 13568 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // xtmp |
| 13569 | st->print_raw("vector_mask_reinterpret_D2B "); |
| 13570 | opnd_array(0)->int_format(ra, this, st); // dst |
| 13571 | st->print_raw(" "); |
| 13572 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 13573 | st->print_raw("\t!"); |
| 13574 | } |
| 13575 | #endif |
| 13576 | #ifndef PRODUCT |
| 13577 | void reinterpret_mask_Q2BNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13578 | // Start at oper_input_base() and count operands |
| 13579 | unsigned idx0 = 1; |
| 13580 | unsigned idx1 = 1; // src |
| 13581 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // xtmp |
| 13582 | st->print_raw("vector_mask_reinterpret_Q2B "); |
| 13583 | opnd_array(0)->int_format(ra, this, st); // dst |
| 13584 | st->print_raw(" "); |
| 13585 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 13586 | st->print_raw("\t!"); |
| 13587 | } |
| 13588 | #endif |
| 13589 | #ifndef PRODUCT |
| 13590 | void reinterpretNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13591 | // Start at oper_input_base() and count operands |
| 13592 | unsigned idx0 = 1; |
| 13593 | unsigned idx1 = 1; // dst |
| 13594 | st->print_raw("vector_reinterpret "); |
| 13595 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 13596 | st->print_raw("\t!"); |
| 13597 | } |
| 13598 | #endif |
| 13599 | #ifndef PRODUCT |
| 13600 | void reinterpret_expandNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13601 | // Start at oper_input_base() and count operands |
| 13602 | unsigned idx0 = 1; |
| 13603 | unsigned idx1 = 1; // src |
| 13604 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst |
| 13605 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // scratch |
| 13606 | st->print_raw("vector_reinterpret_expand "); |
| 13607 | opnd_array(2)->ext_format(ra, this,idx2, st); // dst |
| 13608 | st->print_raw(","); |
| 13609 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 13610 | st->print_raw("\t! using "); |
| 13611 | opnd_array(3)->ext_format(ra, this,idx3, st); // scratch |
| 13612 | st->print_raw(" as TEMP"); |
| 13613 | } |
| 13614 | #endif |
| 13615 | #ifndef PRODUCT |
| 13616 | void vreinterpret_expand4Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13617 | // Start at oper_input_base() and count operands |
| 13618 | unsigned idx0 = 1; |
| 13619 | unsigned idx1 = 1; // src |
| 13620 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // scratch |
| 13621 | st->print_raw("vector_reinterpret_expand "); |
| 13622 | opnd_array(0)->int_format(ra, this, st); // dst |
| 13623 | st->print_raw(","); |
| 13624 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 13625 | st->print_raw("\t! using "); |
| 13626 | opnd_array(2)->ext_format(ra, this,idx2, st); // scratch |
| 13627 | st->print_raw(" as TEMP"); |
| 13628 | } |
| 13629 | #endif |
| 13630 | #ifndef PRODUCT |
| 13631 | void vreinterpret_expandNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13632 | // Start at oper_input_base() and count operands |
| 13633 | unsigned idx0 = 1; |
| 13634 | unsigned idx1 = 1; // src |
| 13635 | st->print_raw("vector_reinterpret_expand "); |
| 13636 | opnd_array(0)->int_format(ra, this, st); // dst |
| 13637 | st->print_raw(","); |
| 13638 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 13639 | st->print_raw("\t!"); |
| 13640 | } |
| 13641 | #endif |
| 13642 | #ifndef PRODUCT |
| 13643 | void reinterpret_shrinkNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13644 | // Start at oper_input_base() and count operands |
| 13645 | unsigned idx0 = 1; |
| 13646 | unsigned idx1 = 1; // src |
| 13647 | st->print_raw("vector_reinterpret_shrink "); |
| 13648 | opnd_array(0)->int_format(ra, this, st); // dst |
| 13649 | st->print_raw(","); |
| 13650 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 13651 | st->print_raw("\t!"); |
| 13652 | } |
| 13653 | #endif |
| 13654 | #ifndef PRODUCT |
| 13655 | void roundD_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13656 | // Start at oper_input_base() and count operands |
| 13657 | unsigned idx0 = 1; |
| 13658 | unsigned idx1 = 1; // src |
| 13659 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // rmode |
| 13660 | st->print_raw("roundsd "); |
| 13661 | opnd_array(0)->int_format(ra, this, st); // dst |
| 13662 | st->print_raw(","); |
| 13663 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 13664 | } |
| 13665 | #endif |
| 13666 | #ifndef PRODUCT |
| 13667 | void roundD_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13668 | // Start at oper_input_base() and count operands |
| 13669 | unsigned idx0 = 2; |
| 13670 | unsigned idx1 = 2; // src |
| 13671 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // rmode |
| 13672 | st->print_raw("roundsd "); |
| 13673 | opnd_array(0)->int_format(ra, this, st); // dst |
| 13674 | st->print_raw(","); |
| 13675 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 13676 | } |
| 13677 | #endif |
| 13678 | #ifndef PRODUCT |
| 13679 | void roundD_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13680 | // Start at oper_input_base() and count operands |
| 13681 | unsigned idx0 = 1; |
| 13682 | unsigned idx1 = 1; // con |
| 13683 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // rmode |
| 13684 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // scratch_reg |
| 13685 | st->print_raw("roundsd "); |
| 13686 | opnd_array(0)->int_format(ra, this, st); // dst |
| 13687 | st->print_raw(",["); |
| 13688 | st->print("constant table base + #%d", constant_offset_unchecked()); |
| 13689 | st->print_raw("]\t# load from constant table: double="); |
| 13690 | opnd_array(1)->ext_format(ra, this,idx1, st); // con |
| 13691 | } |
| 13692 | #endif |
| 13693 | #ifndef PRODUCT |
| 13694 | void vroundD_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13695 | // Start at oper_input_base() and count operands |
| 13696 | unsigned idx0 = 1; |
| 13697 | unsigned idx1 = 1; // src |
| 13698 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // rmode |
| 13699 | st->print_raw("vroundpd "); |
| 13700 | opnd_array(0)->int_format(ra, this, st); // dst |
| 13701 | st->print_raw(","); |
| 13702 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 13703 | st->print_raw(","); |
| 13704 | opnd_array(2)->ext_format(ra, this,idx2, st); // rmode |
| 13705 | st->print_raw("\t! round packedD"); |
| 13706 | } |
| 13707 | #endif |
| 13708 | #ifndef PRODUCT |
| 13709 | void vround8D_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13710 | // Start at oper_input_base() and count operands |
| 13711 | unsigned idx0 = 1; |
| 13712 | unsigned idx1 = 1; // src |
| 13713 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // rmode |
| 13714 | st->print_raw("vrndscalepd "); |
| 13715 | opnd_array(0)->int_format(ra, this, st); // dst |
| 13716 | st->print_raw(","); |
| 13717 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 13718 | st->print_raw(","); |
| 13719 | opnd_array(2)->ext_format(ra, this,idx2, st); // rmode |
| 13720 | st->print_raw("\t! round packed8D"); |
| 13721 | } |
| 13722 | #endif |
| 13723 | #ifndef PRODUCT |
| 13724 | void vroundD_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13725 | // Start at oper_input_base() and count operands |
| 13726 | unsigned idx0 = 2; |
| 13727 | unsigned idx1 = 2; // mem |
| 13728 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // rmode |
| 13729 | st->print_raw("vroundpd "); |
| 13730 | opnd_array(0)->int_format(ra, this, st); // dst |
| 13731 | st->print_raw(", "); |
| 13732 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 13733 | st->print_raw(", "); |
| 13734 | opnd_array(2)->ext_format(ra, this,idx2, st); // rmode |
| 13735 | st->print_raw("\t! round packedD"); |
| 13736 | } |
| 13737 | #endif |
| 13738 | #ifndef PRODUCT |
| 13739 | void vround8D_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13740 | // Start at oper_input_base() and count operands |
| 13741 | unsigned idx0 = 2; |
| 13742 | unsigned idx1 = 2; // mem |
| 13743 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // rmode |
| 13744 | st->print_raw("vrndscalepd "); |
| 13745 | opnd_array(0)->int_format(ra, this, st); // dst |
| 13746 | st->print_raw(","); |
| 13747 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 13748 | st->print_raw(","); |
| 13749 | opnd_array(2)->ext_format(ra, this,idx2, st); // rmode |
| 13750 | st->print_raw("\t! round packed8D"); |
| 13751 | } |
| 13752 | #endif |
| 13753 | #ifndef PRODUCT |
| 13754 | void onspinwaitNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13755 | st->print_raw("pause\t! membar_onspinwait"); |
| 13756 | } |
| 13757 | #endif |
| 13758 | #ifndef PRODUCT |
| 13759 | void fmaD_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13760 | // Start at oper_input_base() and count operands |
| 13761 | unsigned idx0 = 1; |
| 13762 | unsigned idx1 = 1; // c |
| 13763 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // a |
| 13764 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // b |
| 13765 | st->print_raw("fmasd "); |
| 13766 | opnd_array(2)->ext_format(ra, this,idx2, st); // a |
| 13767 | st->print_raw(","); |
| 13768 | opnd_array(3)->ext_format(ra, this,idx3, st); // b |
| 13769 | st->print_raw(","); |
| 13770 | opnd_array(1)->ext_format(ra, this,idx1, st); // c |
| 13771 | st->print_raw("\t# "); |
| 13772 | opnd_array(1)->ext_format(ra, this,idx1, st); // c |
| 13773 | st->print_raw(" = "); |
| 13774 | opnd_array(2)->ext_format(ra, this,idx2, st); // a |
| 13775 | st->print_raw(" * "); |
| 13776 | opnd_array(3)->ext_format(ra, this,idx3, st); // b |
| 13777 | st->print_raw(" + "); |
| 13778 | opnd_array(1)->ext_format(ra, this,idx1, st); // c |
| 13779 | } |
| 13780 | #endif |
| 13781 | #ifndef PRODUCT |
| 13782 | void fmaF_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13783 | // Start at oper_input_base() and count operands |
| 13784 | unsigned idx0 = 1; |
| 13785 | unsigned idx1 = 1; // c |
| 13786 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // a |
| 13787 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // b |
| 13788 | st->print_raw("fmass "); |
| 13789 | opnd_array(2)->ext_format(ra, this,idx2, st); // a |
| 13790 | st->print_raw(","); |
| 13791 | opnd_array(3)->ext_format(ra, this,idx3, st); // b |
| 13792 | st->print_raw(","); |
| 13793 | opnd_array(1)->ext_format(ra, this,idx1, st); // c |
| 13794 | st->print_raw("\t# "); |
| 13795 | opnd_array(1)->ext_format(ra, this,idx1, st); // c |
| 13796 | st->print_raw(" = "); |
| 13797 | opnd_array(2)->ext_format(ra, this,idx2, st); // a |
| 13798 | st->print_raw(" * "); |
| 13799 | opnd_array(3)->ext_format(ra, this,idx3, st); // b |
| 13800 | st->print_raw(" + "); |
| 13801 | opnd_array(1)->ext_format(ra, this,idx1, st); // c |
| 13802 | } |
| 13803 | #endif |
| 13804 | #ifndef PRODUCT |
| 13805 | void MoveVec2LegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13806 | st->print_raw(""); |
| 13807 | } |
| 13808 | #endif |
| 13809 | #ifndef PRODUCT |
| 13810 | void MoveLeg2VecNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13811 | st->print_raw(""); |
| 13812 | } |
| 13813 | #endif |
| 13814 | #ifndef PRODUCT |
| 13815 | void loadVNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13816 | // Start at oper_input_base() and count operands |
| 13817 | unsigned idx0 = 2; |
| 13818 | unsigned idx1 = 2; // mem |
| 13819 | st->print_raw("load_vector "); |
| 13820 | opnd_array(0)->int_format(ra, this, st); // dst |
| 13821 | st->print_raw(","); |
| 13822 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 13823 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 13824 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 13825 | st->print(" ! Field: "); |
| 13826 | if (f->is_volatile()) |
| 13827 | st->print("volatile "); |
| 13828 | f->holder()->name()->print_symbol_on(st); |
| 13829 | st->print("."); |
| 13830 | f->name()->print_symbol_on(st); |
| 13831 | if (f->is_constant()) |
| 13832 | st->print(" (constant)"); |
| 13833 | } else { |
| 13834 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 13835 | st->print(" volatile!"); |
| 13836 | } |
| 13837 | } |
| 13838 | #endif |
| 13839 | #ifndef PRODUCT |
| 13840 | void storeVNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13841 | // Start at oper_input_base() and count operands |
| 13842 | unsigned idx0 = 2; |
| 13843 | unsigned idx1 = 2; // mem |
| 13844 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 13845 | st->print_raw("store_vector "); |
| 13846 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 13847 | st->print_raw(","); |
| 13848 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 13849 | st->print_raw("\n\t"); |
| 13850 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 13851 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 13852 | st->print(" ! Field: "); |
| 13853 | if (f->is_volatile()) |
| 13854 | st->print("volatile "); |
| 13855 | f->holder()->name()->print_symbol_on(st); |
| 13856 | st->print("."); |
| 13857 | f->name()->print_symbol_on(st); |
| 13858 | if (f->is_constant()) |
| 13859 | st->print(" (constant)"); |
| 13860 | } else { |
| 13861 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 13862 | st->print(" volatile!"); |
| 13863 | } |
| 13864 | } |
| 13865 | #endif |
| 13866 | #ifndef PRODUCT |
| 13867 | void gatherNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13868 | // Start at oper_input_base() and count operands |
| 13869 | unsigned idx0 = 2; |
| 13870 | unsigned idx1 = 2; // mem |
| 13871 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // idx |
| 13872 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 13873 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp |
| 13874 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // mask |
| 13875 | st->print_raw("load_vector_gather "); |
| 13876 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 13877 | st->print_raw(", "); |
| 13878 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 13879 | st->print_raw(", "); |
| 13880 | opnd_array(2)->ext_format(ra, this,idx2, st); // idx |
| 13881 | st->print_raw("\t! using "); |
| 13882 | opnd_array(4)->ext_format(ra, this,idx4, st); // tmp |
| 13883 | st->print_raw(" and "); |
| 13884 | opnd_array(5)->ext_format(ra, this,idx5, st); // mask |
| 13885 | st->print_raw(" as TEMP"); |
| 13886 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 13887 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 13888 | st->print(" ! Field: "); |
| 13889 | if (f->is_volatile()) |
| 13890 | st->print("volatile "); |
| 13891 | f->holder()->name()->print_symbol_on(st); |
| 13892 | st->print("."); |
| 13893 | f->name()->print_symbol_on(st); |
| 13894 | if (f->is_constant()) |
| 13895 | st->print(" (constant)"); |
| 13896 | } else { |
| 13897 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 13898 | st->print(" volatile!"); |
| 13899 | } |
| 13900 | } |
| 13901 | #endif |
| 13902 | #ifndef PRODUCT |
| 13903 | void evgatherNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13904 | // Start at oper_input_base() and count operands |
| 13905 | unsigned idx0 = 2; |
| 13906 | unsigned idx1 = 2; // mem |
| 13907 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // idx |
| 13908 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 13909 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp |
| 13910 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // ktmp |
| 13911 | st->print_raw("load_vector_gather "); |
| 13912 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 13913 | st->print_raw(", "); |
| 13914 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 13915 | st->print_raw(", "); |
| 13916 | opnd_array(2)->ext_format(ra, this,idx2, st); // idx |
| 13917 | st->print_raw("\t! using "); |
| 13918 | opnd_array(4)->ext_format(ra, this,idx4, st); // tmp |
| 13919 | st->print_raw(" and ktmp as TEMP"); |
| 13920 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 13921 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 13922 | st->print(" ! Field: "); |
| 13923 | if (f->is_volatile()) |
| 13924 | st->print("volatile "); |
| 13925 | f->holder()->name()->print_symbol_on(st); |
| 13926 | st->print("."); |
| 13927 | f->name()->print_symbol_on(st); |
| 13928 | if (f->is_constant()) |
| 13929 | st->print(" (constant)"); |
| 13930 | } else { |
| 13931 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 13932 | st->print(" volatile!"); |
| 13933 | } |
| 13934 | } |
| 13935 | #endif |
| 13936 | #ifndef PRODUCT |
| 13937 | void evgather_maskedNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13938 | // Start at oper_input_base() and count operands |
| 13939 | unsigned idx0 = 2; |
| 13940 | unsigned idx1 = 2; // mem |
| 13941 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // idx |
| 13942 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 13943 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // dst |
| 13944 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // ktmp |
| 13945 | unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // tmp |
| 13946 | st->print_raw("load_vector_gather_masked "); |
| 13947 | opnd_array(4)->ext_format(ra, this,idx4, st); // dst |
| 13948 | st->print_raw(", "); |
| 13949 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 13950 | st->print_raw(", "); |
| 13951 | opnd_array(2)->ext_format(ra, this,idx2, st); // idx |
| 13952 | st->print_raw(", "); |
| 13953 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 13954 | st->print_raw("\t! using "); |
| 13955 | opnd_array(6)->ext_format(ra, this,idx6, st); // tmp |
| 13956 | st->print_raw(" and ktmp as TEMP"); |
| 13957 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 13958 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 13959 | st->print(" ! Field: "); |
| 13960 | if (f->is_volatile()) |
| 13961 | st->print("volatile "); |
| 13962 | f->holder()->name()->print_symbol_on(st); |
| 13963 | st->print("."); |
| 13964 | f->name()->print_symbol_on(st); |
| 13965 | if (f->is_constant()) |
| 13966 | st->print(" (constant)"); |
| 13967 | } else { |
| 13968 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 13969 | st->print(" volatile!"); |
| 13970 | } |
| 13971 | } |
| 13972 | #endif |
| 13973 | #ifndef PRODUCT |
| 13974 | void scatterNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 13975 | // Start at oper_input_base() and count operands |
| 13976 | unsigned idx0 = 2; |
| 13977 | unsigned idx1 = 2; // mem |
| 13978 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 13979 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // idx |
| 13980 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp |
| 13981 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // ktmp |
| 13982 | st->print_raw("store_vector_scatter "); |
| 13983 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 13984 | st->print_raw(", "); |
| 13985 | opnd_array(3)->ext_format(ra, this,idx3, st); // idx |
| 13986 | st->print_raw(", "); |
| 13987 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 13988 | st->print_raw("\t! using k2 and "); |
| 13989 | opnd_array(4)->ext_format(ra, this,idx4, st); // tmp |
| 13990 | st->print_raw(" as TEMP"); |
| 13991 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 13992 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 13993 | st->print(" ! Field: "); |
| 13994 | if (f->is_volatile()) |
| 13995 | st->print("volatile "); |
| 13996 | f->holder()->name()->print_symbol_on(st); |
| 13997 | st->print("."); |
| 13998 | f->name()->print_symbol_on(st); |
| 13999 | if (f->is_constant()) |
| 14000 | st->print(" (constant)"); |
| 14001 | } else { |
| 14002 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 14003 | st->print(" volatile!"); |
| 14004 | } |
| 14005 | } |
| 14006 | #endif |
| 14007 | #ifndef PRODUCT |
| 14008 | void scatter_maskedNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 14009 | // Start at oper_input_base() and count operands |
| 14010 | unsigned idx0 = 2; |
| 14011 | unsigned idx1 = 2; // mem |
| 14012 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 14013 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // idx |
| 14014 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // mask |
| 14015 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // ktmp |
| 14016 | unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // tmp |
| 14017 | st->print_raw("store_vector_scatter_masked "); |
| 14018 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 14019 | st->print_raw(", "); |
| 14020 | opnd_array(3)->ext_format(ra, this,idx3, st); // idx |
| 14021 | st->print_raw(", "); |
| 14022 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 14023 | st->print_raw(", "); |
| 14024 | opnd_array(4)->ext_format(ra, this,idx4, st); // mask |
| 14025 | st->print_raw("\t!"); |
| 14026 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 14027 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 14028 | st->print(" ! Field: "); |
| 14029 | if (f->is_volatile()) |
| 14030 | st->print("volatile "); |
| 14031 | f->holder()->name()->print_symbol_on(st); |
| 14032 | st->print("."); |
| 14033 | f->name()->print_symbol_on(st); |
| 14034 | if (f->is_constant()) |
| 14035 | st->print(" (constant)"); |
| 14036 | } else { |
| 14037 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 14038 | st->print(" volatile!"); |
| 14039 | } |
| 14040 | } |
| 14041 | #endif |
| 14042 | #ifndef PRODUCT |
| 14043 | void ReplB_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 14044 | // Start at oper_input_base() and count operands |
| 14045 | unsigned idx0 = 1; |
| 14046 | unsigned idx1 = 1; // src |
| 14047 | st->print_raw("replicateB "); |
| 14048 | opnd_array(0)->int_format(ra, this, st); // dst |
| 14049 | st->print_raw(","); |
| 14050 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 14051 | } |
| 14052 | #endif |
| 14053 | #ifndef PRODUCT |
| 14054 | void ReplB_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 14055 | // Start at oper_input_base() and count operands |
| 14056 | unsigned idx0 = 2; |
| 14057 | unsigned idx1 = 2; // mem |
| 14058 | st->print_raw("replicateB "); |
| 14059 | opnd_array(0)->int_format(ra, this, st); // dst |
| 14060 | st->print_raw(","); |
| 14061 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 14062 | } |
| 14063 | #endif |
| 14064 | #ifndef PRODUCT |
| 14065 | void ReplB_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 14066 | // Start at oper_input_base() and count operands |
| 14067 | unsigned idx0 = 1; |
| 14068 | unsigned idx1 = 1; // con |
| 14069 | st->print_raw("replicateB "); |
| 14070 | opnd_array(0)->int_format(ra, this, st); // dst |
| 14071 | st->print_raw(","); |
| 14072 | opnd_array(1)->ext_format(ra, this,idx1, st); // con |
| 14073 | } |
| 14074 | #endif |
| 14075 | #ifndef PRODUCT |
| 14076 | void ReplB_zeroNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 14077 | // Start at oper_input_base() and count operands |
| 14078 | unsigned idx0 = 1; |
| 14079 | unsigned idx1 = 1; // zero |
| 14080 | st->print_raw("replicateB "); |
| 14081 | opnd_array(0)->int_format(ra, this, st); // dst |
| 14082 | st->print_raw(","); |
| 14083 | opnd_array(1)->ext_format(ra, this,idx1, st); // zero |
| 14084 | } |
| 14085 | #endif |
| 14086 | #ifndef PRODUCT |
| 14087 | void ReplS_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 14088 | // Start at oper_input_base() and count operands |
| 14089 | unsigned idx0 = 1; |
| 14090 | unsigned idx1 = 1; // src |
| 14091 | st->print_raw("replicateS "); |
| 14092 | opnd_array(0)->int_format(ra, this, st); // dst |
| 14093 | st->print_raw(","); |
| 14094 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 14095 | } |
| 14096 | #endif |
| 14097 | #ifndef PRODUCT |
| 14098 | void ReplS_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 14099 | // Start at oper_input_base() and count operands |
| 14100 | unsigned idx0 = 2; |
| 14101 | unsigned idx1 = 2; // mem |
| 14102 | st->print_raw("replicateS "); |
| 14103 | opnd_array(0)->int_format(ra, this, st); // dst |
| 14104 | st->print_raw(","); |
| 14105 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 14106 | } |
| 14107 | #endif |
| 14108 | #ifndef PRODUCT |
| 14109 | void ReplS_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 14110 | // Start at oper_input_base() and count operands |
| 14111 | unsigned idx0 = 1; |
| 14112 | unsigned idx1 = 1; // con |
| 14113 | st->print_raw("replicateS "); |
| 14114 | opnd_array(0)->int_format(ra, this, st); // dst |
| 14115 | st->print_raw(","); |
| 14116 | opnd_array(1)->ext_format(ra, this,idx1, st); // con |
| 14117 | } |
| 14118 | #endif |
| 14119 | #ifndef PRODUCT |
| 14120 | void ReplS_zeroNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 14121 | // Start at oper_input_base() and count operands |
| 14122 | unsigned idx0 = 1; |
| 14123 | unsigned idx1 = 1; // zero |
| 14124 | st->print_raw("replicateS "); |
| 14125 | opnd_array(0)->int_format(ra, this, st); // dst |
| 14126 | st->print_raw(","); |
| 14127 | opnd_array(1)->ext_format(ra, this,idx1, st); // zero |
| 14128 | } |
| 14129 | #endif |
| 14130 | #ifndef PRODUCT |
| 14131 | void ReplI_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 14132 | // Start at oper_input_base() and count operands |
| 14133 | unsigned idx0 = 1; |
| 14134 | unsigned idx1 = 1; // src |
| 14135 | st->print_raw("replicateI "); |
| 14136 | opnd_array(0)->int_format(ra, this, st); // dst |
| 14137 | st->print_raw(","); |
| 14138 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 14139 | } |
| 14140 | #endif |
| 14141 | #ifndef PRODUCT |
| 14142 | void ReplI_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 14143 | // Start at oper_input_base() and count operands |
| 14144 | unsigned idx0 = 2; |
| 14145 | unsigned idx1 = 2; // mem |
| 14146 | st->print_raw("replicateI "); |
| 14147 | opnd_array(0)->int_format(ra, this, st); // dst |
| 14148 | st->print_raw(","); |
| 14149 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 14150 | } |
| 14151 | #endif |
| 14152 | #ifndef PRODUCT |
| 14153 | void ReplI_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 14154 | // Start at oper_input_base() and count operands |
| 14155 | unsigned idx0 = 1; |
| 14156 | unsigned idx1 = 1; // con |
| 14157 | st->print_raw("replicateI "); |
| 14158 | opnd_array(0)->int_format(ra, this, st); // dst |
| 14159 | st->print_raw(","); |
| 14160 | opnd_array(1)->ext_format(ra, this,idx1, st); // con |
| 14161 | } |
| 14162 | #endif |
| 14163 | #ifndef PRODUCT |
| 14164 | void ReplI_zeroNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 14165 | // Start at oper_input_base() and count operands |
| 14166 | unsigned idx0 = 1; |
| 14167 | unsigned idx1 = 1; // zero |
| 14168 | st->print_raw("replicateI "); |
| 14169 | opnd_array(0)->int_format(ra, this, st); // dst |
| 14170 | st->print_raw(","); |
| 14171 | opnd_array(1)->ext_format(ra, this,idx1, st); // zero |
| 14172 | } |
| 14173 | #endif |
| 14174 | #ifndef PRODUCT |
| 14175 | void ReplI_M1Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 14176 | // Start at oper_input_base() and count operands |
| 14177 | unsigned idx0 = 1; |
| 14178 | unsigned idx1 = 1; // con |
| 14179 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst |
| 14180 | st->print_raw("vallones "); |
| 14181 | opnd_array(2)->ext_format(ra, this,idx2, st); // dst |
| 14182 | } |
| 14183 | #endif |
| 14184 | #ifndef PRODUCT |
| 14185 | void ReplI_M1_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 14186 | // Start at oper_input_base() and count operands |
| 14187 | unsigned idx0 = 1; |
| 14188 | unsigned idx1 = 1; // con |
| 14189 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst |
| 14190 | st->print_raw("vallones "); |
| 14191 | opnd_array(2)->ext_format(ra, this,idx2, st); // dst |
| 14192 | } |
| 14193 | #endif |
| 14194 | #ifndef PRODUCT |
| 14195 | void ReplI_M1_1Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 14196 | // Start at oper_input_base() and count operands |
| 14197 | unsigned idx0 = 1; |
| 14198 | unsigned idx1 = 1; // con |
| 14199 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst |
| 14200 | st->print_raw("vallones "); |
| 14201 | opnd_array(2)->ext_format(ra, this,idx2, st); // dst |
| 14202 | } |
| 14203 | #endif |
| 14204 | #ifndef PRODUCT |
| 14205 | void ReplL_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 14206 | // Start at oper_input_base() and count operands |
| 14207 | unsigned idx0 = 1; |
| 14208 | unsigned idx1 = 1; // src |
| 14209 | st->print_raw("replicateL "); |
| 14210 | opnd_array(0)->int_format(ra, this, st); // dst |
| 14211 | st->print_raw(","); |
| 14212 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 14213 | } |
| 14214 | #endif |
| 14215 | #ifndef PRODUCT |
| 14216 | void ReplL_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 14217 | // Start at oper_input_base() and count operands |
| 14218 | unsigned idx0 = 2; |
| 14219 | unsigned idx1 = 2; // mem |
| 14220 | st->print_raw("replicateL "); |
| 14221 | opnd_array(0)->int_format(ra, this, st); // dst |
| 14222 | st->print_raw(","); |
| 14223 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 14224 | } |
| 14225 | #endif |
| 14226 | #ifndef PRODUCT |
| 14227 | void ReplL_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 14228 | // Start at oper_input_base() and count operands |
| 14229 | unsigned idx0 = 1; |
| 14230 | unsigned idx1 = 1; // con |
| 14231 | st->print_raw("replicateL "); |
| 14232 | opnd_array(0)->int_format(ra, this, st); // dst |
| 14233 | st->print_raw(","); |
| 14234 | opnd_array(1)->ext_format(ra, this,idx1, st); // con |
| 14235 | } |
| 14236 | #endif |
| 14237 | #ifndef PRODUCT |
| 14238 | void ReplL_zeroNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 14239 | // Start at oper_input_base() and count operands |
| 14240 | unsigned idx0 = 1; |
| 14241 | unsigned idx1 = 1; // zero |
| 14242 | st->print_raw("replicateL "); |
| 14243 | opnd_array(0)->int_format(ra, this, st); // dst |
| 14244 | st->print_raw(","); |
| 14245 | opnd_array(1)->ext_format(ra, this,idx1, st); // zero |
| 14246 | } |
| 14247 | #endif |
| 14248 | #ifndef PRODUCT |
| 14249 | void ReplL_M1Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 14250 | // Start at oper_input_base() and count operands |
| 14251 | unsigned idx0 = 1; |
| 14252 | unsigned idx1 = 1; // con |
| 14253 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst |
| 14254 | st->print_raw("vallones "); |
| 14255 | opnd_array(2)->ext_format(ra, this,idx2, st); // dst |
| 14256 | } |
| 14257 | #endif |
| 14258 | #ifndef PRODUCT |
| 14259 | void ReplF_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 14260 | // Start at oper_input_base() and count operands |
| 14261 | unsigned idx0 = 1; |
| 14262 | unsigned idx1 = 1; // src |
| 14263 | st->print_raw("replicateF "); |
| 14264 | opnd_array(0)->int_format(ra, this, st); // dst |
| 14265 | st->print_raw(","); |
| 14266 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 14267 | } |
| 14268 | #endif |
| 14269 | #ifndef PRODUCT |
| 14270 | void ReplF_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 14271 | // Start at oper_input_base() and count operands |
| 14272 | unsigned idx0 = 2; |
| 14273 | unsigned idx1 = 2; // mem |
| 14274 | st->print_raw("replicateF "); |
| 14275 | opnd_array(0)->int_format(ra, this, st); // dst |
| 14276 | st->print_raw(","); |
| 14277 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 14278 | } |
| 14279 | #endif |
| 14280 | #ifndef PRODUCT |
| 14281 | void ReplF_zeroNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 14282 | // Start at oper_input_base() and count operands |
| 14283 | unsigned idx0 = 1; |
| 14284 | unsigned idx1 = 1; // zero |
| 14285 | st->print_raw("replicateF "); |
| 14286 | opnd_array(0)->int_format(ra, this, st); // dst |
| 14287 | st->print_raw(","); |
| 14288 | opnd_array(1)->ext_format(ra, this,idx1, st); // zero |
| 14289 | } |
| 14290 | #endif |
| 14291 | #ifndef PRODUCT |
| 14292 | void ReplD_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 14293 | // Start at oper_input_base() and count operands |
| 14294 | unsigned idx0 = 1; |
| 14295 | unsigned idx1 = 1; // src |
| 14296 | st->print_raw("replicateD "); |
| 14297 | opnd_array(0)->int_format(ra, this, st); // dst |
| 14298 | st->print_raw(","); |
| 14299 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 14300 | } |
| 14301 | #endif |
| 14302 | #ifndef PRODUCT |
| 14303 | void ReplD_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 14304 | // Start at oper_input_base() and count operands |
| 14305 | unsigned idx0 = 2; |
| 14306 | unsigned idx1 = 2; // mem |
| 14307 | st->print_raw("replicateD "); |
| 14308 | opnd_array(0)->int_format(ra, this, st); // dst |
| 14309 | st->print_raw(","); |
| 14310 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 14311 | } |
| 14312 | #endif |
| 14313 | #ifndef PRODUCT |
| 14314 | void ReplD_zeroNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 14315 | // Start at oper_input_base() and count operands |
| 14316 | unsigned idx0 = 1; |
| 14317 | unsigned idx1 = 1; // zero |
| 14318 | st->print_raw("replicateD "); |
| 14319 | opnd_array(0)->int_format(ra, this, st); // dst |
| 14320 | st->print_raw(","); |
| 14321 | opnd_array(1)->ext_format(ra, this,idx1, st); // zero |
| 14322 | } |
| 14323 | #endif |
| 14324 | #ifndef PRODUCT |
| 14325 | void insertNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 14326 | // Start at oper_input_base() and count operands |
| 14327 | unsigned idx0 = 1; |
| 14328 | unsigned idx1 = 1; // dst |
| 14329 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // val |
| 14330 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // idx |
| 14331 | st->print_raw("vector_insert "); |
| 14332 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 14333 | st->print_raw(","); |
| 14334 | opnd_array(2)->ext_format(ra, this,idx2, st); // val |
| 14335 | st->print_raw(","); |
| 14336 | opnd_array(3)->ext_format(ra, this,idx3, st); // idx |
| 14337 | } |
| 14338 | #endif |
| 14339 | #ifndef PRODUCT |
| 14340 | void insert32Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 14341 | // Start at oper_input_base() and count operands |
| 14342 | unsigned idx0 = 1; |
| 14343 | unsigned idx1 = 1; // src |
| 14344 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // val |
| 14345 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // idx |
| 14346 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp |
| 14347 | st->print_raw("vector_insert "); |
| 14348 | opnd_array(0)->int_format(ra, this, st); // dst |
| 14349 | st->print_raw(","); |
| 14350 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 14351 | st->print_raw(","); |
| 14352 | opnd_array(2)->ext_format(ra, this,idx2, st); // val |
| 14353 | st->print_raw(","); |
| 14354 | opnd_array(3)->ext_format(ra, this,idx3, st); // idx |
| 14355 | st->print_raw("\t!using "); |
| 14356 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp |
| 14357 | st->print_raw(" as TEMP"); |
| 14358 | } |
| 14359 | #endif |
| 14360 | #ifndef PRODUCT |
| 14361 | void insert64Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 14362 | // Start at oper_input_base() and count operands |
| 14363 | unsigned idx0 = 1; |
| 14364 | unsigned idx1 = 1; // src |
| 14365 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // val |
| 14366 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // idx |
| 14367 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp |
| 14368 | st->print_raw("vector_insert "); |
| 14369 | opnd_array(0)->int_format(ra, this, st); // dst |
| 14370 | st->print_raw(","); |
| 14371 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 14372 | st->print_raw(","); |
| 14373 | opnd_array(2)->ext_format(ra, this,idx2, st); // val |
| 14374 | st->print_raw(","); |
| 14375 | opnd_array(3)->ext_format(ra, this,idx3, st); // idx |
| 14376 | st->print_raw("\t!using "); |
| 14377 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp |
| 14378 | st->print_raw(" as TEMP"); |
| 14379 | } |
| 14380 | #endif |
| 14381 | #ifndef PRODUCT |
| 14382 | void insert2LNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 14383 | // Start at oper_input_base() and count operands |
| 14384 | unsigned idx0 = 1; |
| 14385 | unsigned idx1 = 1; // dst |
| 14386 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // val |
| 14387 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // idx |
| 14388 | st->print_raw("vector_insert "); |
| 14389 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 14390 | st->print_raw(","); |
| 14391 | opnd_array(2)->ext_format(ra, this,idx2, st); // val |
| 14392 | st->print_raw(","); |
| 14393 | opnd_array(3)->ext_format(ra, this,idx3, st); // idx |
| 14394 | } |
| 14395 | #endif |
| 14396 | #ifndef PRODUCT |
| 14397 | void insert4LNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 14398 | // Start at oper_input_base() and count operands |
| 14399 | unsigned idx0 = 1; |
| 14400 | unsigned idx1 = 1; // src |
| 14401 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // val |
| 14402 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // idx |
| 14403 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp |
| 14404 | st->print_raw("vector_insert "); |
| 14405 | opnd_array(0)->int_format(ra, this, st); // dst |
| 14406 | st->print_raw(","); |
| 14407 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 14408 | st->print_raw(","); |
| 14409 | opnd_array(2)->ext_format(ra, this,idx2, st); // val |
| 14410 | st->print_raw(","); |
| 14411 | opnd_array(3)->ext_format(ra, this,idx3, st); // idx |
| 14412 | st->print_raw("\t!using "); |
| 14413 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp |
| 14414 | st->print_raw(" as TEMP"); |
| 14415 | } |
| 14416 | #endif |
| 14417 | #ifndef PRODUCT |
| 14418 | void insert8LNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 14419 | // Start at oper_input_base() and count operands |
| 14420 | unsigned idx0 = 1; |
| 14421 | unsigned idx1 = 1; // src |
| 14422 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // val |
| 14423 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // idx |
| 14424 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp |
| 14425 | st->print_raw("vector_insert "); |
| 14426 | opnd_array(0)->int_format(ra, this, st); // dst |
| 14427 | st->print_raw(","); |
| 14428 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 14429 | st->print_raw(","); |
| 14430 | opnd_array(2)->ext_format(ra, this,idx2, st); // val |
| 14431 | st->print_raw(","); |
| 14432 | opnd_array(3)->ext_format(ra, this,idx3, st); // idx |
| 14433 | st->print_raw("\t!using "); |
| 14434 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp |
| 14435 | st->print_raw(" as TEMP"); |
| 14436 | } |
| 14437 | #endif |
| 14438 | #ifndef PRODUCT |
| 14439 | void insertFNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 14440 | // Start at oper_input_base() and count operands |
| 14441 | unsigned idx0 = 1; |
| 14442 | unsigned idx1 = 1; // dst |
| 14443 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // val |
| 14444 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // idx |
| 14445 | st->print_raw("vector_insert "); |
| 14446 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 14447 | st->print_raw(","); |
| 14448 | opnd_array(2)->ext_format(ra, this,idx2, st); // val |
| 14449 | st->print_raw(","); |
| 14450 | opnd_array(3)->ext_format(ra, this,idx3, st); // idx |
| 14451 | } |
| 14452 | #endif |
| 14453 | #ifndef PRODUCT |
| 14454 | void vinsertFNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 14455 | // Start at oper_input_base() and count operands |
| 14456 | unsigned idx0 = 1; |
| 14457 | unsigned idx1 = 1; // src |
| 14458 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // val |
| 14459 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // idx |
| 14460 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp |
| 14461 | st->print_raw("vector_insert "); |
| 14462 | opnd_array(0)->int_format(ra, this, st); // dst |
| 14463 | st->print_raw(","); |
| 14464 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 14465 | st->print_raw(","); |
| 14466 | opnd_array(2)->ext_format(ra, this,idx2, st); // val |
| 14467 | st->print_raw(","); |
| 14468 | opnd_array(3)->ext_format(ra, this,idx3, st); // idx |
| 14469 | st->print_raw("\t!using "); |
| 14470 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp |
| 14471 | st->print_raw(" as TEMP"); |
| 14472 | } |
| 14473 | #endif |
| 14474 | #ifndef PRODUCT |
| 14475 | void insert2DNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 14476 | // Start at oper_input_base() and count operands |
| 14477 | unsigned idx0 = 1; |
| 14478 | unsigned idx1 = 1; // dst |
| 14479 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // val |
| 14480 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // idx |
| 14481 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp |
| 14482 | st->print_raw("vector_insert "); |
| 14483 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 14484 | st->print_raw(","); |
| 14485 | opnd_array(2)->ext_format(ra, this,idx2, st); // val |
| 14486 | st->print_raw(","); |
| 14487 | opnd_array(3)->ext_format(ra, this,idx3, st); // idx |
| 14488 | st->print_raw("\t!using "); |
| 14489 | opnd_array(4)->ext_format(ra, this,idx4, st); // tmp |
| 14490 | st->print_raw(" as TEMP"); |
| 14491 | } |
| 14492 | #endif |
| 14493 | #ifndef PRODUCT |
| 14494 | void insert4DNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 14495 | // Start at oper_input_base() and count operands |
| 14496 | unsigned idx0 = 1; |
| 14497 | unsigned idx1 = 1; // src |
| 14498 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // val |
| 14499 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // idx |
| 14500 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp |
| 14501 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // vtmp |
| 14502 | st->print_raw("vector_insert "); |
| 14503 | opnd_array(0)->int_format(ra, this, st); // dst |
| 14504 | st->print_raw(","); |
| 14505 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 14506 | st->print_raw(","); |
| 14507 | opnd_array(2)->ext_format(ra, this,idx2, st); // val |
| 14508 | st->print_raw(","); |
| 14509 | opnd_array(3)->ext_format(ra, this,idx3, st); // idx |
| 14510 | st->print_raw("\t!using "); |
| 14511 | opnd_array(4)->ext_format(ra, this,idx4, st); // tmp |
| 14512 | st->print_raw(", "); |
| 14513 | opnd_array(5)->ext_format(ra, this,idx5, st); // vtmp |
| 14514 | st->print_raw(" as TEMP"); |
| 14515 | } |
| 14516 | #endif |
| 14517 | #ifndef PRODUCT |
| 14518 | void insert8DNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 14519 | // Start at oper_input_base() and count operands |
| 14520 | unsigned idx0 = 1; |
| 14521 | unsigned idx1 = 1; // src |
| 14522 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // val |
| 14523 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // idx |
| 14524 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp |
| 14525 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // vtmp |
| 14526 | st->print_raw("vector_insert "); |
| 14527 | opnd_array(0)->int_format(ra, this, st); // dst |
| 14528 | st->print_raw(","); |
| 14529 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 14530 | st->print_raw(","); |
| 14531 | opnd_array(2)->ext_format(ra, this,idx2, st); // val |
| 14532 | st->print_raw(","); |
| 14533 | opnd_array(3)->ext_format(ra, this,idx3, st); // idx |
| 14534 | st->print_raw("\t!using "); |
| 14535 | opnd_array(5)->ext_format(ra, this,idx5, st); // vtmp |
| 14536 | st->print_raw(" as TEMP"); |
| 14537 | } |
| 14538 | #endif |
| 14539 | #ifndef PRODUCT |
| 14540 | void reductionINode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 14541 | // Start at oper_input_base() and count operands |
| 14542 | unsigned idx0 = 1; |
| 14543 | unsigned idx1 = 1; // src1 |
| 14544 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 14545 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1 |
| 14546 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2 |
| 14547 | st->print_raw("vector_reduction_int "); |
| 14548 | opnd_array(0)->int_format(ra, this, st); // dst |
| 14549 | st->print_raw(","); |
| 14550 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 14551 | st->print_raw(","); |
| 14552 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 14553 | st->print_raw(" ; using "); |
| 14554 | opnd_array(3)->ext_format(ra, this,idx3, st); // vtmp1 |
| 14555 | st->print_raw(", "); |
| 14556 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp2 |
| 14557 | st->print_raw(" as TEMP"); |
| 14558 | } |
| 14559 | #endif |
| 14560 | #ifndef PRODUCT |
| 14561 | void reductionI_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 14562 | // Start at oper_input_base() and count operands |
| 14563 | unsigned idx0 = 1; |
| 14564 | unsigned idx1 = 1; // src1 |
| 14565 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 14566 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1 |
| 14567 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2 |
| 14568 | st->print_raw("vector_reduction_int "); |
| 14569 | opnd_array(0)->int_format(ra, this, st); // dst |
| 14570 | st->print_raw(","); |
| 14571 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 14572 | st->print_raw(","); |
| 14573 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 14574 | st->print_raw(" ; using "); |
| 14575 | opnd_array(3)->ext_format(ra, this,idx3, st); // vtmp1 |
| 14576 | st->print_raw(", "); |
| 14577 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp2 |
| 14578 | st->print_raw(" as TEMP"); |
| 14579 | } |
| 14580 | #endif |
| 14581 | #ifndef PRODUCT |
| 14582 | void reductionI_1Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 14583 | // Start at oper_input_base() and count operands |
| 14584 | unsigned idx0 = 1; |
| 14585 | unsigned idx1 = 1; // src1 |
| 14586 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 14587 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1 |
| 14588 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2 |
| 14589 | st->print_raw("vector_reduction_int "); |
| 14590 | opnd_array(0)->int_format(ra, this, st); // dst |
| 14591 | st->print_raw(","); |
| 14592 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 14593 | st->print_raw(","); |
| 14594 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 14595 | st->print_raw(" ; using "); |
| 14596 | opnd_array(3)->ext_format(ra, this,idx3, st); // vtmp1 |
| 14597 | st->print_raw(", "); |
| 14598 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp2 |
| 14599 | st->print_raw(" as TEMP"); |
| 14600 | } |
| 14601 | #endif |
| 14602 | #ifndef PRODUCT |
| 14603 | void reductionI_2Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 14604 | // Start at oper_input_base() and count operands |
| 14605 | unsigned idx0 = 1; |
| 14606 | unsigned idx1 = 1; // src1 |
| 14607 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 14608 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1 |
| 14609 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2 |
| 14610 | st->print_raw("vector_reduction_int "); |
| 14611 | opnd_array(0)->int_format(ra, this, st); // dst |
| 14612 | st->print_raw(","); |
| 14613 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 14614 | st->print_raw(","); |
| 14615 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 14616 | st->print_raw(" ; using "); |
| 14617 | opnd_array(3)->ext_format(ra, this,idx3, st); // vtmp1 |
| 14618 | st->print_raw(", "); |
| 14619 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp2 |
| 14620 | st->print_raw(" as TEMP"); |
| 14621 | } |
| 14622 | #endif |
| 14623 | #ifndef PRODUCT |
| 14624 | void reductionI_3Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 14625 | // Start at oper_input_base() and count operands |
| 14626 | unsigned idx0 = 1; |
| 14627 | unsigned idx1 = 1; // src1 |
| 14628 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 14629 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1 |
| 14630 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2 |
| 14631 | st->print_raw("vector_reduction_int "); |
| 14632 | opnd_array(0)->int_format(ra, this, st); // dst |
| 14633 | st->print_raw(","); |
| 14634 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 14635 | st->print_raw(","); |
| 14636 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 14637 | st->print_raw(" ; using "); |
| 14638 | opnd_array(3)->ext_format(ra, this,idx3, st); // vtmp1 |
| 14639 | st->print_raw(", "); |
| 14640 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp2 |
| 14641 | st->print_raw(" as TEMP"); |
| 14642 | } |
| 14643 | #endif |
| 14644 | #ifndef PRODUCT |
| 14645 | void reductionI_4Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 14646 | // Start at oper_input_base() and count operands |
| 14647 | unsigned idx0 = 1; |
| 14648 | unsigned idx1 = 1; // src1 |
| 14649 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 14650 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1 |
| 14651 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2 |
| 14652 | st->print_raw("vector_reduction_int "); |
| 14653 | opnd_array(0)->int_format(ra, this, st); // dst |
| 14654 | st->print_raw(","); |
| 14655 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 14656 | st->print_raw(","); |
| 14657 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 14658 | st->print_raw(" ; using "); |
| 14659 | opnd_array(3)->ext_format(ra, this,idx3, st); // vtmp1 |
| 14660 | st->print_raw(", "); |
| 14661 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp2 |
| 14662 | st->print_raw(" as TEMP"); |
| 14663 | } |
| 14664 | #endif |
| 14665 | #ifndef PRODUCT |
| 14666 | void reductionI_5Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 14667 | // Start at oper_input_base() and count operands |
| 14668 | unsigned idx0 = 1; |
| 14669 | unsigned idx1 = 1; // src1 |
| 14670 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 14671 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1 |
| 14672 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2 |
| 14673 | st->print_raw("vector_reduction_int "); |
| 14674 | opnd_array(0)->int_format(ra, this, st); // dst |
| 14675 | st->print_raw(","); |
| 14676 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 14677 | st->print_raw(","); |
| 14678 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 14679 | st->print_raw(" ; using "); |
| 14680 | opnd_array(3)->ext_format(ra, this,idx3, st); // vtmp1 |
| 14681 | st->print_raw(", "); |
| 14682 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp2 |
| 14683 | st->print_raw(" as TEMP"); |
| 14684 | } |
| 14685 | #endif |
| 14686 | #ifndef PRODUCT |
| 14687 | void reductionLNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 14688 | // Start at oper_input_base() and count operands |
| 14689 | unsigned idx0 = 1; |
| 14690 | unsigned idx1 = 1; // src1 |
| 14691 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 14692 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1 |
| 14693 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2 |
| 14694 | st->print_raw("vector_reduction_long "); |
| 14695 | opnd_array(0)->int_format(ra, this, st); // dst |
| 14696 | st->print_raw(","); |
| 14697 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 14698 | st->print_raw(","); |
| 14699 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 14700 | st->print_raw(" ; using "); |
| 14701 | opnd_array(3)->ext_format(ra, this,idx3, st); // vtmp1 |
| 14702 | st->print_raw(", "); |
| 14703 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp2 |
| 14704 | st->print_raw(" as TEMP"); |
| 14705 | } |
| 14706 | #endif |
| 14707 | #ifndef PRODUCT |
| 14708 | void reductionL_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 14709 | // Start at oper_input_base() and count operands |
| 14710 | unsigned idx0 = 1; |
| 14711 | unsigned idx1 = 1; // src1 |
| 14712 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 14713 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1 |
| 14714 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2 |
| 14715 | st->print_raw("vector_reduction_long "); |
| 14716 | opnd_array(0)->int_format(ra, this, st); // dst |
| 14717 | st->print_raw(","); |
| 14718 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 14719 | st->print_raw(","); |
| 14720 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 14721 | st->print_raw(" ; using "); |
| 14722 | opnd_array(3)->ext_format(ra, this,idx3, st); // vtmp1 |
| 14723 | st->print_raw(", "); |
| 14724 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp2 |
| 14725 | st->print_raw(" as TEMP"); |
| 14726 | } |
| 14727 | #endif |
| 14728 | #ifndef PRODUCT |
| 14729 | void reductionL_1Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 14730 | // Start at oper_input_base() and count operands |
| 14731 | unsigned idx0 = 1; |
| 14732 | unsigned idx1 = 1; // src1 |
| 14733 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 14734 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1 |
| 14735 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2 |
| 14736 | st->print_raw("vector_reduction_long "); |
| 14737 | opnd_array(0)->int_format(ra, this, st); // dst |
| 14738 | st->print_raw(","); |
| 14739 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 14740 | st->print_raw(","); |
| 14741 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 14742 | st->print_raw(" ; using "); |
| 14743 | opnd_array(3)->ext_format(ra, this,idx3, st); // vtmp1 |
| 14744 | st->print_raw(", "); |
| 14745 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp2 |
| 14746 | st->print_raw(" as TEMP"); |
| 14747 | } |
| 14748 | #endif |
| 14749 | #ifndef PRODUCT |
| 14750 | void reductionL_2Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 14751 | // Start at oper_input_base() and count operands |
| 14752 | unsigned idx0 = 1; |
| 14753 | unsigned idx1 = 1; // src1 |
| 14754 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 14755 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1 |
| 14756 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2 |
| 14757 | st->print_raw("vector_reduction_long "); |
| 14758 | opnd_array(0)->int_format(ra, this, st); // dst |
| 14759 | st->print_raw(","); |
| 14760 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 14761 | st->print_raw(","); |
| 14762 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 14763 | st->print_raw(" ; using "); |
| 14764 | opnd_array(3)->ext_format(ra, this,idx3, st); // vtmp1 |
| 14765 | st->print_raw(", "); |
| 14766 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp2 |
| 14767 | st->print_raw(" as TEMP"); |
| 14768 | } |
| 14769 | #endif |
| 14770 | #ifndef PRODUCT |
| 14771 | void reductionL_3Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 14772 | // Start at oper_input_base() and count operands |
| 14773 | unsigned idx0 = 1; |
| 14774 | unsigned idx1 = 1; // src1 |
| 14775 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 14776 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1 |
| 14777 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2 |
| 14778 | st->print_raw("vector_reduction_long "); |
| 14779 | opnd_array(0)->int_format(ra, this, st); // dst |
| 14780 | st->print_raw(","); |
| 14781 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 14782 | st->print_raw(","); |
| 14783 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 14784 | st->print_raw(" ; using "); |
| 14785 | opnd_array(3)->ext_format(ra, this,idx3, st); // vtmp1 |
| 14786 | st->print_raw(", "); |
| 14787 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp2 |
| 14788 | st->print_raw(" as TEMP"); |
| 14789 | } |
| 14790 | #endif |
| 14791 | #ifndef PRODUCT |
| 14792 | void reductionL_4Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 14793 | // Start at oper_input_base() and count operands |
| 14794 | unsigned idx0 = 1; |
| 14795 | unsigned idx1 = 1; // src1 |
| 14796 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 14797 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1 |
| 14798 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2 |
| 14799 | st->print_raw("vector_reduction_long "); |
| 14800 | opnd_array(0)->int_format(ra, this, st); // dst |
| 14801 | st->print_raw(","); |
| 14802 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 14803 | st->print_raw(","); |
| 14804 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 14805 | st->print_raw(" ; using "); |
| 14806 | opnd_array(3)->ext_format(ra, this,idx3, st); // vtmp1 |
| 14807 | st->print_raw(", "); |
| 14808 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp2 |
| 14809 | st->print_raw(" as TEMP"); |
| 14810 | } |
| 14811 | #endif |
| 14812 | #ifndef PRODUCT |
| 14813 | void reductionL_5Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 14814 | // Start at oper_input_base() and count operands |
| 14815 | unsigned idx0 = 1; |
| 14816 | unsigned idx1 = 1; // src1 |
| 14817 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 14818 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1 |
| 14819 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2 |
| 14820 | st->print_raw("vector_reduction_long "); |
| 14821 | opnd_array(0)->int_format(ra, this, st); // dst |
| 14822 | st->print_raw(","); |
| 14823 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 14824 | st->print_raw(","); |
| 14825 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 14826 | st->print_raw(" ; using "); |
| 14827 | opnd_array(3)->ext_format(ra, this,idx3, st); // vtmp1 |
| 14828 | st->print_raw(", "); |
| 14829 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp2 |
| 14830 | st->print_raw(" as TEMP"); |
| 14831 | } |
| 14832 | #endif |
| 14833 | #ifndef PRODUCT |
| 14834 | void reductionL_avx512dqNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 14835 | // Start at oper_input_base() and count operands |
| 14836 | unsigned idx0 = 1; |
| 14837 | unsigned idx1 = 1; // src1 |
| 14838 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 14839 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1 |
| 14840 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2 |
| 14841 | st->print_raw("vector_reduction_long "); |
| 14842 | opnd_array(0)->int_format(ra, this, st); // dst |
| 14843 | st->print_raw(","); |
| 14844 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 14845 | st->print_raw(","); |
| 14846 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 14847 | st->print_raw(" ; using "); |
| 14848 | opnd_array(3)->ext_format(ra, this,idx3, st); // vtmp1 |
| 14849 | st->print_raw(", "); |
| 14850 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp2 |
| 14851 | st->print_raw(" as TEMP"); |
| 14852 | } |
| 14853 | #endif |
| 14854 | #ifndef PRODUCT |
| 14855 | void reductionL_avx512dq_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 14856 | // Start at oper_input_base() and count operands |
| 14857 | unsigned idx0 = 1; |
| 14858 | unsigned idx1 = 1; // src1 |
| 14859 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 14860 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1 |
| 14861 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2 |
| 14862 | st->print_raw("vector_reduction_long "); |
| 14863 | opnd_array(0)->int_format(ra, this, st); // dst |
| 14864 | st->print_raw(","); |
| 14865 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 14866 | st->print_raw(","); |
| 14867 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 14868 | st->print_raw(" ; using "); |
| 14869 | opnd_array(3)->ext_format(ra, this,idx3, st); // vtmp1 |
| 14870 | st->print_raw(", "); |
| 14871 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp2 |
| 14872 | st->print_raw(" as TEMP"); |
| 14873 | } |
| 14874 | #endif |
| 14875 | #ifndef PRODUCT |
| 14876 | void reductionL_avx512dq_1Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 14877 | // Start at oper_input_base() and count operands |
| 14878 | unsigned idx0 = 1; |
| 14879 | unsigned idx1 = 1; // src1 |
| 14880 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 14881 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1 |
| 14882 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2 |
| 14883 | st->print_raw("vector_reduction_long "); |
| 14884 | opnd_array(0)->int_format(ra, this, st); // dst |
| 14885 | st->print_raw(","); |
| 14886 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 14887 | st->print_raw(","); |
| 14888 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 14889 | st->print_raw(" ; using "); |
| 14890 | opnd_array(3)->ext_format(ra, this,idx3, st); // vtmp1 |
| 14891 | st->print_raw(", "); |
| 14892 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp2 |
| 14893 | st->print_raw(" as TEMP"); |
| 14894 | } |
| 14895 | #endif |
| 14896 | #ifndef PRODUCT |
| 14897 | void reductionL_avx512dq_2Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 14898 | // Start at oper_input_base() and count operands |
| 14899 | unsigned idx0 = 1; |
| 14900 | unsigned idx1 = 1; // src1 |
| 14901 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 14902 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1 |
| 14903 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2 |
| 14904 | st->print_raw("vector_reduction_long "); |
| 14905 | opnd_array(0)->int_format(ra, this, st); // dst |
| 14906 | st->print_raw(","); |
| 14907 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 14908 | st->print_raw(","); |
| 14909 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 14910 | st->print_raw(" ; using "); |
| 14911 | opnd_array(3)->ext_format(ra, this,idx3, st); // vtmp1 |
| 14912 | st->print_raw(", "); |
| 14913 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp2 |
| 14914 | st->print_raw(" as TEMP"); |
| 14915 | } |
| 14916 | #endif |
| 14917 | #ifndef PRODUCT |
| 14918 | void reductionL_avx512dq_3Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 14919 | // Start at oper_input_base() and count operands |
| 14920 | unsigned idx0 = 1; |
| 14921 | unsigned idx1 = 1; // src1 |
| 14922 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 14923 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1 |
| 14924 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2 |
| 14925 | st->print_raw("vector_reduction_long "); |
| 14926 | opnd_array(0)->int_format(ra, this, st); // dst |
| 14927 | st->print_raw(","); |
| 14928 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 14929 | st->print_raw(","); |
| 14930 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 14931 | st->print_raw(" ; using "); |
| 14932 | opnd_array(3)->ext_format(ra, this,idx3, st); // vtmp1 |
| 14933 | st->print_raw(", "); |
| 14934 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp2 |
| 14935 | st->print_raw(" as TEMP"); |
| 14936 | } |
| 14937 | #endif |
| 14938 | #ifndef PRODUCT |
| 14939 | void reductionL_avx512dq_4Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 14940 | // Start at oper_input_base() and count operands |
| 14941 | unsigned idx0 = 1; |
| 14942 | unsigned idx1 = 1; // src1 |
| 14943 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 14944 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1 |
| 14945 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2 |
| 14946 | st->print_raw("vector_reduction_long "); |
| 14947 | opnd_array(0)->int_format(ra, this, st); // dst |
| 14948 | st->print_raw(","); |
| 14949 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 14950 | st->print_raw(","); |
| 14951 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 14952 | st->print_raw(" ; using "); |
| 14953 | opnd_array(3)->ext_format(ra, this,idx3, st); // vtmp1 |
| 14954 | st->print_raw(", "); |
| 14955 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp2 |
| 14956 | st->print_raw(" as TEMP"); |
| 14957 | } |
| 14958 | #endif |
| 14959 | #ifndef PRODUCT |
| 14960 | void reductionL_avx512dq_5Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 14961 | // Start at oper_input_base() and count operands |
| 14962 | unsigned idx0 = 1; |
| 14963 | unsigned idx1 = 1; // src1 |
| 14964 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 14965 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1 |
| 14966 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2 |
| 14967 | st->print_raw("vector_reduction_long "); |
| 14968 | opnd_array(0)->int_format(ra, this, st); // dst |
| 14969 | st->print_raw(","); |
| 14970 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 14971 | st->print_raw(","); |
| 14972 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 14973 | st->print_raw(" ; using "); |
| 14974 | opnd_array(3)->ext_format(ra, this,idx3, st); // vtmp1 |
| 14975 | st->print_raw(", "); |
| 14976 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp2 |
| 14977 | st->print_raw(" as TEMP"); |
| 14978 | } |
| 14979 | #endif |
| 14980 | #ifndef PRODUCT |
| 14981 | void reductionF128Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 14982 | // Start at oper_input_base() and count operands |
| 14983 | unsigned idx0 = 1; |
| 14984 | unsigned idx1 = 1; // dst |
| 14985 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 14986 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp |
| 14987 | st->print_raw("vector_reduction_float "); |
| 14988 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 14989 | st->print_raw(","); |
| 14990 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 14991 | st->print_raw(" ; using "); |
| 14992 | opnd_array(3)->ext_format(ra, this,idx3, st); // vtmp |
| 14993 | st->print_raw(" as TEMP"); |
| 14994 | } |
| 14995 | #endif |
| 14996 | #ifndef PRODUCT |
| 14997 | void reductionF128_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 14998 | // Start at oper_input_base() and count operands |
| 14999 | unsigned idx0 = 1; |
| 15000 | unsigned idx1 = 1; // dst |
| 15001 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 15002 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp |
| 15003 | st->print_raw("vector_reduction_float "); |
| 15004 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 15005 | st->print_raw(","); |
| 15006 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 15007 | st->print_raw(" ; using "); |
| 15008 | opnd_array(3)->ext_format(ra, this,idx3, st); // vtmp |
| 15009 | st->print_raw(" as TEMP"); |
| 15010 | } |
| 15011 | #endif |
| 15012 | #ifndef PRODUCT |
| 15013 | void reduction8FNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 15014 | // Start at oper_input_base() and count operands |
| 15015 | unsigned idx0 = 1; |
| 15016 | unsigned idx1 = 1; // dst |
| 15017 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 15018 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1 |
| 15019 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2 |
| 15020 | st->print_raw("vector_reduction_float "); |
| 15021 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 15022 | st->print_raw(","); |
| 15023 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 15024 | st->print_raw(" ; using "); |
| 15025 | opnd_array(3)->ext_format(ra, this,idx3, st); // vtmp1 |
| 15026 | st->print_raw(", "); |
| 15027 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp2 |
| 15028 | st->print_raw(" as TEMP"); |
| 15029 | } |
| 15030 | #endif |
| 15031 | #ifndef PRODUCT |
| 15032 | void reduction8F_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 15033 | // Start at oper_input_base() and count operands |
| 15034 | unsigned idx0 = 1; |
| 15035 | unsigned idx1 = 1; // dst |
| 15036 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 15037 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1 |
| 15038 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2 |
| 15039 | st->print_raw("vector_reduction_float "); |
| 15040 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 15041 | st->print_raw(","); |
| 15042 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 15043 | st->print_raw(" ; using "); |
| 15044 | opnd_array(3)->ext_format(ra, this,idx3, st); // vtmp1 |
| 15045 | st->print_raw(", "); |
| 15046 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp2 |
| 15047 | st->print_raw(" as TEMP"); |
| 15048 | } |
| 15049 | #endif |
| 15050 | #ifndef PRODUCT |
| 15051 | void reduction16FNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 15052 | // Start at oper_input_base() and count operands |
| 15053 | unsigned idx0 = 1; |
| 15054 | unsigned idx1 = 1; // dst |
| 15055 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 15056 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1 |
| 15057 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2 |
| 15058 | st->print_raw("vector_reduction_float "); |
| 15059 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 15060 | st->print_raw(","); |
| 15061 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 15062 | st->print_raw(" ; using "); |
| 15063 | opnd_array(3)->ext_format(ra, this,idx3, st); // vtmp1 |
| 15064 | st->print_raw(", "); |
| 15065 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp2 |
| 15066 | st->print_raw(" as TEMP"); |
| 15067 | } |
| 15068 | #endif |
| 15069 | #ifndef PRODUCT |
| 15070 | void reduction16F_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 15071 | // Start at oper_input_base() and count operands |
| 15072 | unsigned idx0 = 1; |
| 15073 | unsigned idx1 = 1; // dst |
| 15074 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 15075 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1 |
| 15076 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2 |
| 15077 | st->print_raw("vector_reduction_float "); |
| 15078 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 15079 | st->print_raw(","); |
| 15080 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 15081 | st->print_raw(" ; using "); |
| 15082 | opnd_array(3)->ext_format(ra, this,idx3, st); // vtmp1 |
| 15083 | st->print_raw(", "); |
| 15084 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp2 |
| 15085 | st->print_raw(" as TEMP"); |
| 15086 | } |
| 15087 | #endif |
| 15088 | #ifndef PRODUCT |
| 15089 | void reduction2DNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 15090 | // Start at oper_input_base() and count operands |
| 15091 | unsigned idx0 = 1; |
| 15092 | unsigned idx1 = 1; // dst |
| 15093 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 15094 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp |
| 15095 | st->print_raw("vector_reduction_double "); |
| 15096 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 15097 | st->print_raw(","); |
| 15098 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 15099 | st->print_raw(" ; using "); |
| 15100 | opnd_array(3)->ext_format(ra, this,idx3, st); // vtmp |
| 15101 | st->print_raw(" as TEMP"); |
| 15102 | } |
| 15103 | #endif |
| 15104 | #ifndef PRODUCT |
| 15105 | void reduction2D_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 15106 | // Start at oper_input_base() and count operands |
| 15107 | unsigned idx0 = 1; |
| 15108 | unsigned idx1 = 1; // dst |
| 15109 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 15110 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp |
| 15111 | st->print_raw("vector_reduction_double "); |
| 15112 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 15113 | st->print_raw(","); |
| 15114 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 15115 | st->print_raw(" ; using "); |
| 15116 | opnd_array(3)->ext_format(ra, this,idx3, st); // vtmp |
| 15117 | st->print_raw(" as TEMP"); |
| 15118 | } |
| 15119 | #endif |
| 15120 | #ifndef PRODUCT |
| 15121 | void reduction4DNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 15122 | // Start at oper_input_base() and count operands |
| 15123 | unsigned idx0 = 1; |
| 15124 | unsigned idx1 = 1; // dst |
| 15125 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 15126 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1 |
| 15127 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2 |
| 15128 | st->print_raw("vector_reduction_double "); |
| 15129 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 15130 | st->print_raw(","); |
| 15131 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 15132 | st->print_raw(" ; using "); |
| 15133 | opnd_array(3)->ext_format(ra, this,idx3, st); // vtmp1 |
| 15134 | st->print_raw(", "); |
| 15135 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp2 |
| 15136 | st->print_raw(" as TEMP"); |
| 15137 | } |
| 15138 | #endif |
| 15139 | #ifndef PRODUCT |
| 15140 | void reduction4D_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 15141 | // Start at oper_input_base() and count operands |
| 15142 | unsigned idx0 = 1; |
| 15143 | unsigned idx1 = 1; // dst |
| 15144 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 15145 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1 |
| 15146 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2 |
| 15147 | st->print_raw("vector_reduction_double "); |
| 15148 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 15149 | st->print_raw(","); |
| 15150 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 15151 | st->print_raw(" ; using "); |
| 15152 | opnd_array(3)->ext_format(ra, this,idx3, st); // vtmp1 |
| 15153 | st->print_raw(", "); |
| 15154 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp2 |
| 15155 | st->print_raw(" as TEMP"); |
| 15156 | } |
| 15157 | #endif |
| 15158 | #ifndef PRODUCT |
| 15159 | void reduction8DNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 15160 | // Start at oper_input_base() and count operands |
| 15161 | unsigned idx0 = 1; |
| 15162 | unsigned idx1 = 1; // dst |
| 15163 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 15164 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1 |
| 15165 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2 |
| 15166 | st->print_raw("vector_reduction_double "); |
| 15167 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 15168 | st->print_raw(","); |
| 15169 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 15170 | st->print_raw(" ; using "); |
| 15171 | opnd_array(3)->ext_format(ra, this,idx3, st); // vtmp1 |
| 15172 | st->print_raw(", "); |
| 15173 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp2 |
| 15174 | st->print_raw(" as TEMP"); |
| 15175 | } |
| 15176 | #endif |
| 15177 | #ifndef PRODUCT |
| 15178 | void reduction8D_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 15179 | // Start at oper_input_base() and count operands |
| 15180 | unsigned idx0 = 1; |
| 15181 | unsigned idx1 = 1; // dst |
| 15182 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 15183 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1 |
| 15184 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2 |
| 15185 | st->print_raw("vector_reduction_double "); |
| 15186 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 15187 | st->print_raw(","); |
| 15188 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 15189 | st->print_raw(" ; using "); |
| 15190 | opnd_array(3)->ext_format(ra, this,idx3, st); // vtmp1 |
| 15191 | st->print_raw(", "); |
| 15192 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp2 |
| 15193 | st->print_raw(" as TEMP"); |
| 15194 | } |
| 15195 | #endif |
| 15196 | #ifndef PRODUCT |
| 15197 | void reductionBNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 15198 | // Start at oper_input_base() and count operands |
| 15199 | unsigned idx0 = 1; |
| 15200 | unsigned idx1 = 1; // src1 |
| 15201 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 15202 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1 |
| 15203 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2 |
| 15204 | st->print_raw("vector_reduction_byte "); |
| 15205 | opnd_array(0)->int_format(ra, this, st); // dst |
| 15206 | st->print_raw(","); |
| 15207 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 15208 | st->print_raw(","); |
| 15209 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 15210 | st->print_raw(" ; using "); |
| 15211 | opnd_array(3)->ext_format(ra, this,idx3, st); // vtmp1 |
| 15212 | st->print_raw(", "); |
| 15213 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp2 |
| 15214 | st->print_raw(" as TEMP"); |
| 15215 | } |
| 15216 | #endif |
| 15217 | #ifndef PRODUCT |
| 15218 | void reductionB_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 15219 | // Start at oper_input_base() and count operands |
| 15220 | unsigned idx0 = 1; |
| 15221 | unsigned idx1 = 1; // src1 |
| 15222 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 15223 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1 |
| 15224 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2 |
| 15225 | st->print_raw("vector_reduction_byte "); |
| 15226 | opnd_array(0)->int_format(ra, this, st); // dst |
| 15227 | st->print_raw(","); |
| 15228 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 15229 | st->print_raw(","); |
| 15230 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 15231 | st->print_raw(" ; using "); |
| 15232 | opnd_array(3)->ext_format(ra, this,idx3, st); // vtmp1 |
| 15233 | st->print_raw(", "); |
| 15234 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp2 |
| 15235 | st->print_raw(" as TEMP"); |
| 15236 | } |
| 15237 | #endif |
| 15238 | #ifndef PRODUCT |
| 15239 | void reductionB_1Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 15240 | // Start at oper_input_base() and count operands |
| 15241 | unsigned idx0 = 1; |
| 15242 | unsigned idx1 = 1; // src1 |
| 15243 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 15244 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1 |
| 15245 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2 |
| 15246 | st->print_raw("vector_reduction_byte "); |
| 15247 | opnd_array(0)->int_format(ra, this, st); // dst |
| 15248 | st->print_raw(","); |
| 15249 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 15250 | st->print_raw(","); |
| 15251 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 15252 | st->print_raw(" ; using "); |
| 15253 | opnd_array(3)->ext_format(ra, this,idx3, st); // vtmp1 |
| 15254 | st->print_raw(", "); |
| 15255 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp2 |
| 15256 | st->print_raw(" as TEMP"); |
| 15257 | } |
| 15258 | #endif |
| 15259 | #ifndef PRODUCT |
| 15260 | void reductionB_2Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 15261 | // Start at oper_input_base() and count operands |
| 15262 | unsigned idx0 = 1; |
| 15263 | unsigned idx1 = 1; // src1 |
| 15264 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 15265 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1 |
| 15266 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2 |
| 15267 | st->print_raw("vector_reduction_byte "); |
| 15268 | opnd_array(0)->int_format(ra, this, st); // dst |
| 15269 | st->print_raw(","); |
| 15270 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 15271 | st->print_raw(","); |
| 15272 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 15273 | st->print_raw(" ; using "); |
| 15274 | opnd_array(3)->ext_format(ra, this,idx3, st); // vtmp1 |
| 15275 | st->print_raw(", "); |
| 15276 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp2 |
| 15277 | st->print_raw(" as TEMP"); |
| 15278 | } |
| 15279 | #endif |
| 15280 | #ifndef PRODUCT |
| 15281 | void reductionB_3Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 15282 | // Start at oper_input_base() and count operands |
| 15283 | unsigned idx0 = 1; |
| 15284 | unsigned idx1 = 1; // src1 |
| 15285 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 15286 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1 |
| 15287 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2 |
| 15288 | st->print_raw("vector_reduction_byte "); |
| 15289 | opnd_array(0)->int_format(ra, this, st); // dst |
| 15290 | st->print_raw(","); |
| 15291 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 15292 | st->print_raw(","); |
| 15293 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 15294 | st->print_raw(" ; using "); |
| 15295 | opnd_array(3)->ext_format(ra, this,idx3, st); // vtmp1 |
| 15296 | st->print_raw(", "); |
| 15297 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp2 |
| 15298 | st->print_raw(" as TEMP"); |
| 15299 | } |
| 15300 | #endif |
| 15301 | #ifndef PRODUCT |
| 15302 | void reductionB_4Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 15303 | // Start at oper_input_base() and count operands |
| 15304 | unsigned idx0 = 1; |
| 15305 | unsigned idx1 = 1; // src1 |
| 15306 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 15307 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1 |
| 15308 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2 |
| 15309 | st->print_raw("vector_reduction_byte "); |
| 15310 | opnd_array(0)->int_format(ra, this, st); // dst |
| 15311 | st->print_raw(","); |
| 15312 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 15313 | st->print_raw(","); |
| 15314 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 15315 | st->print_raw(" ; using "); |
| 15316 | opnd_array(3)->ext_format(ra, this,idx3, st); // vtmp1 |
| 15317 | st->print_raw(", "); |
| 15318 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp2 |
| 15319 | st->print_raw(" as TEMP"); |
| 15320 | } |
| 15321 | #endif |
| 15322 | #ifndef PRODUCT |
| 15323 | void reductionB_avx512bwNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 15324 | // Start at oper_input_base() and count operands |
| 15325 | unsigned idx0 = 1; |
| 15326 | unsigned idx1 = 1; // src1 |
| 15327 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 15328 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1 |
| 15329 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2 |
| 15330 | st->print_raw("vector_reduction_byte "); |
| 15331 | opnd_array(0)->int_format(ra, this, st); // dst |
| 15332 | st->print_raw(","); |
| 15333 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 15334 | st->print_raw(","); |
| 15335 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 15336 | st->print_raw(" ; using "); |
| 15337 | opnd_array(3)->ext_format(ra, this,idx3, st); // vtmp1 |
| 15338 | st->print_raw(", "); |
| 15339 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp2 |
| 15340 | st->print_raw(" as TEMP"); |
| 15341 | } |
| 15342 | #endif |
| 15343 | #ifndef PRODUCT |
| 15344 | void reductionB_avx512bw_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 15345 | // Start at oper_input_base() and count operands |
| 15346 | unsigned idx0 = 1; |
| 15347 | unsigned idx1 = 1; // src1 |
| 15348 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 15349 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1 |
| 15350 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2 |
| 15351 | st->print_raw("vector_reduction_byte "); |
| 15352 | opnd_array(0)->int_format(ra, this, st); // dst |
| 15353 | st->print_raw(","); |
| 15354 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 15355 | st->print_raw(","); |
| 15356 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 15357 | st->print_raw(" ; using "); |
| 15358 | opnd_array(3)->ext_format(ra, this,idx3, st); // vtmp1 |
| 15359 | st->print_raw(", "); |
| 15360 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp2 |
| 15361 | st->print_raw(" as TEMP"); |
| 15362 | } |
| 15363 | #endif |
| 15364 | #ifndef PRODUCT |
| 15365 | void reductionB_avx512bw_1Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 15366 | // Start at oper_input_base() and count operands |
| 15367 | unsigned idx0 = 1; |
| 15368 | unsigned idx1 = 1; // src1 |
| 15369 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 15370 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1 |
| 15371 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2 |
| 15372 | st->print_raw("vector_reduction_byte "); |
| 15373 | opnd_array(0)->int_format(ra, this, st); // dst |
| 15374 | st->print_raw(","); |
| 15375 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 15376 | st->print_raw(","); |
| 15377 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 15378 | st->print_raw(" ; using "); |
| 15379 | opnd_array(3)->ext_format(ra, this,idx3, st); // vtmp1 |
| 15380 | st->print_raw(", "); |
| 15381 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp2 |
| 15382 | st->print_raw(" as TEMP"); |
| 15383 | } |
| 15384 | #endif |
| 15385 | #ifndef PRODUCT |
| 15386 | void reductionB_avx512bw_2Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 15387 | // Start at oper_input_base() and count operands |
| 15388 | unsigned idx0 = 1; |
| 15389 | unsigned idx1 = 1; // src1 |
| 15390 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 15391 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1 |
| 15392 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2 |
| 15393 | st->print_raw("vector_reduction_byte "); |
| 15394 | opnd_array(0)->int_format(ra, this, st); // dst |
| 15395 | st->print_raw(","); |
| 15396 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 15397 | st->print_raw(","); |
| 15398 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 15399 | st->print_raw(" ; using "); |
| 15400 | opnd_array(3)->ext_format(ra, this,idx3, st); // vtmp1 |
| 15401 | st->print_raw(", "); |
| 15402 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp2 |
| 15403 | st->print_raw(" as TEMP"); |
| 15404 | } |
| 15405 | #endif |
| 15406 | #ifndef PRODUCT |
| 15407 | void reductionB_avx512bw_3Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 15408 | // Start at oper_input_base() and count operands |
| 15409 | unsigned idx0 = 1; |
| 15410 | unsigned idx1 = 1; // src1 |
| 15411 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 15412 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1 |
| 15413 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2 |
| 15414 | st->print_raw("vector_reduction_byte "); |
| 15415 | opnd_array(0)->int_format(ra, this, st); // dst |
| 15416 | st->print_raw(","); |
| 15417 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 15418 | st->print_raw(","); |
| 15419 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 15420 | st->print_raw(" ; using "); |
| 15421 | opnd_array(3)->ext_format(ra, this,idx3, st); // vtmp1 |
| 15422 | st->print_raw(", "); |
| 15423 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp2 |
| 15424 | st->print_raw(" as TEMP"); |
| 15425 | } |
| 15426 | #endif |
| 15427 | #ifndef PRODUCT |
| 15428 | void reductionB_avx512bw_4Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 15429 | // Start at oper_input_base() and count operands |
| 15430 | unsigned idx0 = 1; |
| 15431 | unsigned idx1 = 1; // src1 |
| 15432 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 15433 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1 |
| 15434 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2 |
| 15435 | st->print_raw("vector_reduction_byte "); |
| 15436 | opnd_array(0)->int_format(ra, this, st); // dst |
| 15437 | st->print_raw(","); |
| 15438 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 15439 | st->print_raw(","); |
| 15440 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 15441 | st->print_raw(" ; using "); |
| 15442 | opnd_array(3)->ext_format(ra, this,idx3, st); // vtmp1 |
| 15443 | st->print_raw(", "); |
| 15444 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp2 |
| 15445 | st->print_raw(" as TEMP"); |
| 15446 | } |
| 15447 | #endif |
| 15448 | #ifndef PRODUCT |
| 15449 | void reductionSNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 15450 | // Start at oper_input_base() and count operands |
| 15451 | unsigned idx0 = 1; |
| 15452 | unsigned idx1 = 1; // src1 |
| 15453 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 15454 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1 |
| 15455 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2 |
| 15456 | st->print_raw("vector_reduction_short "); |
| 15457 | opnd_array(0)->int_format(ra, this, st); // dst |
| 15458 | st->print_raw(","); |
| 15459 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 15460 | st->print_raw(","); |
| 15461 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 15462 | st->print_raw(" ; using "); |
| 15463 | opnd_array(3)->ext_format(ra, this,idx3, st); // vtmp1 |
| 15464 | st->print_raw(", "); |
| 15465 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp2 |
| 15466 | st->print_raw(" as TEMP"); |
| 15467 | } |
| 15468 | #endif |
| 15469 | #ifndef PRODUCT |
| 15470 | void reductionS_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 15471 | // Start at oper_input_base() and count operands |
| 15472 | unsigned idx0 = 1; |
| 15473 | unsigned idx1 = 1; // src1 |
| 15474 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 15475 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1 |
| 15476 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2 |
| 15477 | st->print_raw("vector_reduction_short "); |
| 15478 | opnd_array(0)->int_format(ra, this, st); // dst |
| 15479 | st->print_raw(","); |
| 15480 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 15481 | st->print_raw(","); |
| 15482 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 15483 | st->print_raw(" ; using "); |
| 15484 | opnd_array(3)->ext_format(ra, this,idx3, st); // vtmp1 |
| 15485 | st->print_raw(", "); |
| 15486 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp2 |
| 15487 | st->print_raw(" as TEMP"); |
| 15488 | } |
| 15489 | #endif |
| 15490 | #ifndef PRODUCT |
| 15491 | void reductionS_1Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 15492 | // Start at oper_input_base() and count operands |
| 15493 | unsigned idx0 = 1; |
| 15494 | unsigned idx1 = 1; // src1 |
| 15495 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 15496 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1 |
| 15497 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2 |
| 15498 | st->print_raw("vector_reduction_short "); |
| 15499 | opnd_array(0)->int_format(ra, this, st); // dst |
| 15500 | st->print_raw(","); |
| 15501 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 15502 | st->print_raw(","); |
| 15503 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 15504 | st->print_raw(" ; using "); |
| 15505 | opnd_array(3)->ext_format(ra, this,idx3, st); // vtmp1 |
| 15506 | st->print_raw(", "); |
| 15507 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp2 |
| 15508 | st->print_raw(" as TEMP"); |
| 15509 | } |
| 15510 | #endif |
| 15511 | #ifndef PRODUCT |
| 15512 | void reductionS_2Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 15513 | // Start at oper_input_base() and count operands |
| 15514 | unsigned idx0 = 1; |
| 15515 | unsigned idx1 = 1; // src1 |
| 15516 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 15517 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1 |
| 15518 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2 |
| 15519 | st->print_raw("vector_reduction_short "); |
| 15520 | opnd_array(0)->int_format(ra, this, st); // dst |
| 15521 | st->print_raw(","); |
| 15522 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 15523 | st->print_raw(","); |
| 15524 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 15525 | st->print_raw(" ; using "); |
| 15526 | opnd_array(3)->ext_format(ra, this,idx3, st); // vtmp1 |
| 15527 | st->print_raw(", "); |
| 15528 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp2 |
| 15529 | st->print_raw(" as TEMP"); |
| 15530 | } |
| 15531 | #endif |
| 15532 | #ifndef PRODUCT |
| 15533 | void reductionS_3Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 15534 | // Start at oper_input_base() and count operands |
| 15535 | unsigned idx0 = 1; |
| 15536 | unsigned idx1 = 1; // src1 |
| 15537 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 15538 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1 |
| 15539 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2 |
| 15540 | st->print_raw("vector_reduction_short "); |
| 15541 | opnd_array(0)->int_format(ra, this, st); // dst |
| 15542 | st->print_raw(","); |
| 15543 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 15544 | st->print_raw(","); |
| 15545 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 15546 | st->print_raw(" ; using "); |
| 15547 | opnd_array(3)->ext_format(ra, this,idx3, st); // vtmp1 |
| 15548 | st->print_raw(", "); |
| 15549 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp2 |
| 15550 | st->print_raw(" as TEMP"); |
| 15551 | } |
| 15552 | #endif |
| 15553 | #ifndef PRODUCT |
| 15554 | void reductionS_4Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 15555 | // Start at oper_input_base() and count operands |
| 15556 | unsigned idx0 = 1; |
| 15557 | unsigned idx1 = 1; // src1 |
| 15558 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 15559 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1 |
| 15560 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2 |
| 15561 | st->print_raw("vector_reduction_short "); |
| 15562 | opnd_array(0)->int_format(ra, this, st); // dst |
| 15563 | st->print_raw(","); |
| 15564 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 15565 | st->print_raw(","); |
| 15566 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 15567 | st->print_raw(" ; using "); |
| 15568 | opnd_array(3)->ext_format(ra, this,idx3, st); // vtmp1 |
| 15569 | st->print_raw(", "); |
| 15570 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp2 |
| 15571 | st->print_raw(" as TEMP"); |
| 15572 | } |
| 15573 | #endif |
| 15574 | #ifndef PRODUCT |
| 15575 | void reductionS_5Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 15576 | // Start at oper_input_base() and count operands |
| 15577 | unsigned idx0 = 1; |
| 15578 | unsigned idx1 = 1; // src1 |
| 15579 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 15580 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1 |
| 15581 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2 |
| 15582 | st->print_raw("vector_reduction_short "); |
| 15583 | opnd_array(0)->int_format(ra, this, st); // dst |
| 15584 | st->print_raw(","); |
| 15585 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 15586 | st->print_raw(","); |
| 15587 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 15588 | st->print_raw(" ; using "); |
| 15589 | opnd_array(3)->ext_format(ra, this,idx3, st); // vtmp1 |
| 15590 | st->print_raw(", "); |
| 15591 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp2 |
| 15592 | st->print_raw(" as TEMP"); |
| 15593 | } |
| 15594 | #endif |
| 15595 | #ifndef PRODUCT |
| 15596 | void mul_reductionBNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 15597 | // Start at oper_input_base() and count operands |
| 15598 | unsigned idx0 = 1; |
| 15599 | unsigned idx1 = 1; // src1 |
| 15600 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 15601 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 15602 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp1 |
| 15603 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // vtmp2 |
| 15604 | st->print_raw("vector_mul_reduction_byte "); |
| 15605 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 15606 | st->print_raw(","); |
| 15607 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 15608 | st->print_raw(","); |
| 15609 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 15610 | st->print_raw("; using "); |
| 15611 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp1 |
| 15612 | st->print_raw(", "); |
| 15613 | opnd_array(5)->ext_format(ra, this,idx5, st); // vtmp2 |
| 15614 | st->print_raw(" as TEMP"); |
| 15615 | } |
| 15616 | #endif |
| 15617 | #ifndef PRODUCT |
| 15618 | void mul_reduction64BNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 15619 | // Start at oper_input_base() and count operands |
| 15620 | unsigned idx0 = 1; |
| 15621 | unsigned idx1 = 1; // src1 |
| 15622 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 15623 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 15624 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp1 |
| 15625 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // vtmp2 |
| 15626 | st->print_raw("vector_mul_reduction_byte "); |
| 15627 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 15628 | st->print_raw(","); |
| 15629 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 15630 | st->print_raw(","); |
| 15631 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 15632 | st->print_raw("; using "); |
| 15633 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp1 |
| 15634 | st->print_raw(", "); |
| 15635 | opnd_array(5)->ext_format(ra, this,idx5, st); // vtmp2 |
| 15636 | st->print_raw(" as TEMP"); |
| 15637 | } |
| 15638 | #endif |
| 15639 | #ifndef PRODUCT |
| 15640 | void minmax_reduction2FNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 15641 | // Start at oper_input_base() and count operands |
| 15642 | unsigned idx0 = 1; |
| 15643 | unsigned idx1 = 1; // src1 |
| 15644 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 15645 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 15646 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp |
| 15647 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // atmp |
| 15648 | unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // btmp |
| 15649 | unsigned idx7 = idx6 + opnd_array(6)->num_edges(); // xmm_1 |
| 15650 | st->print_raw("vector_minmax2F_reduction "); |
| 15651 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 15652 | st->print_raw(","); |
| 15653 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 15654 | st->print_raw(","); |
| 15655 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 15656 | st->print_raw(" ; using "); |
| 15657 | opnd_array(4)->ext_format(ra, this,idx4, st); // tmp |
| 15658 | st->print_raw(", "); |
| 15659 | opnd_array(5)->ext_format(ra, this,idx5, st); // atmp |
| 15660 | st->print_raw(", "); |
| 15661 | opnd_array(6)->ext_format(ra, this,idx6, st); // btmp |
| 15662 | st->print_raw(", "); |
| 15663 | opnd_array(7)->ext_format(ra, this,idx7, st); // xmm_1 |
| 15664 | st->print_raw(" as TEMP"); |
| 15665 | } |
| 15666 | #endif |
| 15667 | #ifndef PRODUCT |
| 15668 | void minmax_reduction2F_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 15669 | // Start at oper_input_base() and count operands |
| 15670 | unsigned idx0 = 1; |
| 15671 | unsigned idx1 = 1; // src1 |
| 15672 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 15673 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 15674 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp |
| 15675 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // atmp |
| 15676 | unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // btmp |
| 15677 | unsigned idx7 = idx6 + opnd_array(6)->num_edges(); // xmm_1 |
| 15678 | st->print_raw("vector_minmax2F_reduction "); |
| 15679 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 15680 | st->print_raw(","); |
| 15681 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 15682 | st->print_raw(","); |
| 15683 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 15684 | st->print_raw(" ; using "); |
| 15685 | opnd_array(4)->ext_format(ra, this,idx4, st); // tmp |
| 15686 | st->print_raw(", "); |
| 15687 | opnd_array(5)->ext_format(ra, this,idx5, st); // atmp |
| 15688 | st->print_raw(", "); |
| 15689 | opnd_array(6)->ext_format(ra, this,idx6, st); // btmp |
| 15690 | st->print_raw(", "); |
| 15691 | opnd_array(7)->ext_format(ra, this,idx7, st); // xmm_1 |
| 15692 | st->print_raw(" as TEMP"); |
| 15693 | } |
| 15694 | #endif |
| 15695 | #ifndef PRODUCT |
| 15696 | void minmax_reductionFNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 15697 | // Start at oper_input_base() and count operands |
| 15698 | unsigned idx0 = 1; |
| 15699 | unsigned idx1 = 1; // src1 |
| 15700 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 15701 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 15702 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp |
| 15703 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // atmp |
| 15704 | unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // btmp |
| 15705 | unsigned idx7 = idx6 + opnd_array(6)->num_edges(); // xmm_0 |
| 15706 | unsigned idx8 = idx7 + opnd_array(7)->num_edges(); // xmm_1 |
| 15707 | st->print_raw("vector_minmaxF_reduction "); |
| 15708 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 15709 | st->print_raw(","); |
| 15710 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 15711 | st->print_raw(","); |
| 15712 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 15713 | st->print_raw(" ; using "); |
| 15714 | opnd_array(4)->ext_format(ra, this,idx4, st); // tmp |
| 15715 | st->print_raw(", "); |
| 15716 | opnd_array(5)->ext_format(ra, this,idx5, st); // atmp |
| 15717 | st->print_raw(", "); |
| 15718 | opnd_array(6)->ext_format(ra, this,idx6, st); // btmp |
| 15719 | st->print_raw(", "); |
| 15720 | opnd_array(7)->ext_format(ra, this,idx7, st); // xmm_0 |
| 15721 | st->print_raw(", "); |
| 15722 | opnd_array(8)->ext_format(ra, this,idx8, st); // xmm_1 |
| 15723 | st->print_raw(" as TEMP"); |
| 15724 | } |
| 15725 | #endif |
| 15726 | #ifndef PRODUCT |
| 15727 | void minmax_reductionF_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 15728 | // Start at oper_input_base() and count operands |
| 15729 | unsigned idx0 = 1; |
| 15730 | unsigned idx1 = 1; // src1 |
| 15731 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 15732 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 15733 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp |
| 15734 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // atmp |
| 15735 | unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // btmp |
| 15736 | unsigned idx7 = idx6 + opnd_array(6)->num_edges(); // xmm_0 |
| 15737 | unsigned idx8 = idx7 + opnd_array(7)->num_edges(); // xmm_1 |
| 15738 | st->print_raw("vector_minmaxF_reduction "); |
| 15739 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 15740 | st->print_raw(","); |
| 15741 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 15742 | st->print_raw(","); |
| 15743 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 15744 | st->print_raw(" ; using "); |
| 15745 | opnd_array(4)->ext_format(ra, this,idx4, st); // tmp |
| 15746 | st->print_raw(", "); |
| 15747 | opnd_array(5)->ext_format(ra, this,idx5, st); // atmp |
| 15748 | st->print_raw(", "); |
| 15749 | opnd_array(6)->ext_format(ra, this,idx6, st); // btmp |
| 15750 | st->print_raw(", "); |
| 15751 | opnd_array(7)->ext_format(ra, this,idx7, st); // xmm_0 |
| 15752 | st->print_raw(", "); |
| 15753 | opnd_array(8)->ext_format(ra, this,idx8, st); // xmm_1 |
| 15754 | st->print_raw(" as TEMP"); |
| 15755 | } |
| 15756 | #endif |
| 15757 | #ifndef PRODUCT |
| 15758 | void minmax_reduction2F_avNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 15759 | // Start at oper_input_base() and count operands |
| 15760 | unsigned idx0 = 1; |
| 15761 | unsigned idx1 = 1; // dst |
| 15762 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 15763 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp |
| 15764 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // atmp |
| 15765 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // btmp |
| 15766 | unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // xmm_1 |
| 15767 | st->print_raw("vector_minmax2F_reduction "); |
| 15768 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 15769 | st->print_raw(","); |
| 15770 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 15771 | st->print_raw(" ; using "); |
| 15772 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp |
| 15773 | st->print_raw(", "); |
| 15774 | opnd_array(4)->ext_format(ra, this,idx4, st); // atmp |
| 15775 | st->print_raw(", "); |
| 15776 | opnd_array(5)->ext_format(ra, this,idx5, st); // btmp |
| 15777 | st->print_raw(", "); |
| 15778 | opnd_array(6)->ext_format(ra, this,idx6, st); // xmm_1 |
| 15779 | st->print_raw(" as TEMP"); |
| 15780 | } |
| 15781 | #endif |
| 15782 | #ifndef PRODUCT |
| 15783 | void minmax_reduction2F_av_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 15784 | // Start at oper_input_base() and count operands |
| 15785 | unsigned idx0 = 1; |
| 15786 | unsigned idx1 = 1; // dst |
| 15787 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 15788 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp |
| 15789 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // atmp |
| 15790 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // btmp |
| 15791 | unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // xmm_1 |
| 15792 | st->print_raw("vector_minmax2F_reduction "); |
| 15793 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 15794 | st->print_raw(","); |
| 15795 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 15796 | st->print_raw(" ; using "); |
| 15797 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp |
| 15798 | st->print_raw(", "); |
| 15799 | opnd_array(4)->ext_format(ra, this,idx4, st); // atmp |
| 15800 | st->print_raw(", "); |
| 15801 | opnd_array(5)->ext_format(ra, this,idx5, st); // btmp |
| 15802 | st->print_raw(", "); |
| 15803 | opnd_array(6)->ext_format(ra, this,idx6, st); // xmm_1 |
| 15804 | st->print_raw(" as TEMP"); |
| 15805 | } |
| 15806 | #endif |
| 15807 | #ifndef PRODUCT |
| 15808 | void minmax_reductionF_avNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 15809 | // Start at oper_input_base() and count operands |
| 15810 | unsigned idx0 = 1; |
| 15811 | unsigned idx1 = 1; // dst |
| 15812 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 15813 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp |
| 15814 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // atmp |
| 15815 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // btmp |
| 15816 | unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // xmm_0 |
| 15817 | unsigned idx7 = idx6 + opnd_array(6)->num_edges(); // xmm_1 |
| 15818 | st->print_raw("vector_minmaxF_reduction "); |
| 15819 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 15820 | st->print_raw(","); |
| 15821 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 15822 | st->print_raw(" ; using "); |
| 15823 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp |
| 15824 | st->print_raw(", "); |
| 15825 | opnd_array(4)->ext_format(ra, this,idx4, st); // atmp |
| 15826 | st->print_raw(", "); |
| 15827 | opnd_array(5)->ext_format(ra, this,idx5, st); // btmp |
| 15828 | st->print_raw(", "); |
| 15829 | opnd_array(6)->ext_format(ra, this,idx6, st); // xmm_0 |
| 15830 | st->print_raw(", "); |
| 15831 | opnd_array(7)->ext_format(ra, this,idx7, st); // xmm_1 |
| 15832 | st->print_raw(" as TEMP"); |
| 15833 | } |
| 15834 | #endif |
| 15835 | #ifndef PRODUCT |
| 15836 | void minmax_reductionF_av_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 15837 | // Start at oper_input_base() and count operands |
| 15838 | unsigned idx0 = 1; |
| 15839 | unsigned idx1 = 1; // dst |
| 15840 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 15841 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp |
| 15842 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // atmp |
| 15843 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // btmp |
| 15844 | unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // xmm_0 |
| 15845 | unsigned idx7 = idx6 + opnd_array(6)->num_edges(); // xmm_1 |
| 15846 | st->print_raw("vector_minmaxF_reduction "); |
| 15847 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 15848 | st->print_raw(","); |
| 15849 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 15850 | st->print_raw(" ; using "); |
| 15851 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp |
| 15852 | st->print_raw(", "); |
| 15853 | opnd_array(4)->ext_format(ra, this,idx4, st); // atmp |
| 15854 | st->print_raw(", "); |
| 15855 | opnd_array(5)->ext_format(ra, this,idx5, st); // btmp |
| 15856 | st->print_raw(", "); |
| 15857 | opnd_array(6)->ext_format(ra, this,idx6, st); // xmm_0 |
| 15858 | st->print_raw(", "); |
| 15859 | opnd_array(7)->ext_format(ra, this,idx7, st); // xmm_1 |
| 15860 | st->print_raw(" as TEMP"); |
| 15861 | } |
| 15862 | #endif |
| 15863 | #ifndef PRODUCT |
| 15864 | void minmax_reduction2DNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 15865 | // Start at oper_input_base() and count operands |
| 15866 | unsigned idx0 = 1; |
| 15867 | unsigned idx1 = 1; // src1 |
| 15868 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 15869 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 15870 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1 |
| 15871 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2 |
| 15872 | unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // tmp3 |
| 15873 | unsigned idx7 = idx6 + opnd_array(6)->num_edges(); // tmp4 |
| 15874 | st->print_raw("vector_minmax2D_reduction "); |
| 15875 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 15876 | st->print_raw(","); |
| 15877 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 15878 | st->print_raw(","); |
| 15879 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 15880 | st->print_raw(" ; using "); |
| 15881 | opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1 |
| 15882 | st->print_raw(", "); |
| 15883 | opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2 |
| 15884 | st->print_raw(", "); |
| 15885 | opnd_array(6)->ext_format(ra, this,idx6, st); // tmp3 |
| 15886 | st->print_raw(", "); |
| 15887 | opnd_array(7)->ext_format(ra, this,idx7, st); // tmp4 |
| 15888 | st->print_raw(" as TEMP"); |
| 15889 | } |
| 15890 | #endif |
| 15891 | #ifndef PRODUCT |
| 15892 | void minmax_reduction2D_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 15893 | // Start at oper_input_base() and count operands |
| 15894 | unsigned idx0 = 1; |
| 15895 | unsigned idx1 = 1; // src1 |
| 15896 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 15897 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 15898 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1 |
| 15899 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2 |
| 15900 | unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // tmp3 |
| 15901 | unsigned idx7 = idx6 + opnd_array(6)->num_edges(); // tmp4 |
| 15902 | st->print_raw("vector_minmax2D_reduction "); |
| 15903 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 15904 | st->print_raw(","); |
| 15905 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 15906 | st->print_raw(","); |
| 15907 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 15908 | st->print_raw(" ; using "); |
| 15909 | opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1 |
| 15910 | st->print_raw(", "); |
| 15911 | opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2 |
| 15912 | st->print_raw(", "); |
| 15913 | opnd_array(6)->ext_format(ra, this,idx6, st); // tmp3 |
| 15914 | st->print_raw(", "); |
| 15915 | opnd_array(7)->ext_format(ra, this,idx7, st); // tmp4 |
| 15916 | st->print_raw(" as TEMP"); |
| 15917 | } |
| 15918 | #endif |
| 15919 | #ifndef PRODUCT |
| 15920 | void minmax_reductionDNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 15921 | // Start at oper_input_base() and count operands |
| 15922 | unsigned idx0 = 1; |
| 15923 | unsigned idx1 = 1; // src1 |
| 15924 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 15925 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 15926 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1 |
| 15927 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2 |
| 15928 | unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // tmp3 |
| 15929 | unsigned idx7 = idx6 + opnd_array(6)->num_edges(); // tmp4 |
| 15930 | unsigned idx8 = idx7 + opnd_array(7)->num_edges(); // tmp5 |
| 15931 | st->print_raw("vector_minmaxD_reduction "); |
| 15932 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 15933 | st->print_raw(","); |
| 15934 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 15935 | st->print_raw(","); |
| 15936 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 15937 | st->print_raw(" ; using "); |
| 15938 | opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1 |
| 15939 | st->print_raw(", "); |
| 15940 | opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2 |
| 15941 | st->print_raw(", "); |
| 15942 | opnd_array(6)->ext_format(ra, this,idx6, st); // tmp3 |
| 15943 | st->print_raw(", "); |
| 15944 | opnd_array(7)->ext_format(ra, this,idx7, st); // tmp4 |
| 15945 | st->print_raw(", "); |
| 15946 | opnd_array(8)->ext_format(ra, this,idx8, st); // tmp5 |
| 15947 | st->print_raw(" as TEMP"); |
| 15948 | } |
| 15949 | #endif |
| 15950 | #ifndef PRODUCT |
| 15951 | void minmax_reductionD_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 15952 | // Start at oper_input_base() and count operands |
| 15953 | unsigned idx0 = 1; |
| 15954 | unsigned idx1 = 1; // src1 |
| 15955 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 15956 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 15957 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1 |
| 15958 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2 |
| 15959 | unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // tmp3 |
| 15960 | unsigned idx7 = idx6 + opnd_array(6)->num_edges(); // tmp4 |
| 15961 | unsigned idx8 = idx7 + opnd_array(7)->num_edges(); // tmp5 |
| 15962 | st->print_raw("vector_minmaxD_reduction "); |
| 15963 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 15964 | st->print_raw(","); |
| 15965 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 15966 | st->print_raw(","); |
| 15967 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 15968 | st->print_raw(" ; using "); |
| 15969 | opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1 |
| 15970 | st->print_raw(", "); |
| 15971 | opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2 |
| 15972 | st->print_raw(", "); |
| 15973 | opnd_array(6)->ext_format(ra, this,idx6, st); // tmp3 |
| 15974 | st->print_raw(", "); |
| 15975 | opnd_array(7)->ext_format(ra, this,idx7, st); // tmp4 |
| 15976 | st->print_raw(", "); |
| 15977 | opnd_array(8)->ext_format(ra, this,idx8, st); // tmp5 |
| 15978 | st->print_raw(" as TEMP"); |
| 15979 | } |
| 15980 | #endif |
| 15981 | #ifndef PRODUCT |
| 15982 | void minmax_reduction2D_avNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 15983 | // Start at oper_input_base() and count operands |
| 15984 | unsigned idx0 = 1; |
| 15985 | unsigned idx1 = 1; // dst |
| 15986 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 15987 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp1 |
| 15988 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2 |
| 15989 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp3 |
| 15990 | unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // tmp4 |
| 15991 | st->print_raw("vector_minmax2D_reduction "); |
| 15992 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 15993 | st->print_raw(","); |
| 15994 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 15995 | st->print_raw(" ; using "); |
| 15996 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp1 |
| 15997 | st->print_raw(", "); |
| 15998 | opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2 |
| 15999 | st->print_raw(", "); |
| 16000 | opnd_array(5)->ext_format(ra, this,idx5, st); // tmp3 |
| 16001 | st->print_raw(", "); |
| 16002 | opnd_array(6)->ext_format(ra, this,idx6, st); // tmp4 |
| 16003 | st->print_raw(" as TEMP"); |
| 16004 | } |
| 16005 | #endif |
| 16006 | #ifndef PRODUCT |
| 16007 | void minmax_reduction2D_av_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 16008 | // Start at oper_input_base() and count operands |
| 16009 | unsigned idx0 = 1; |
| 16010 | unsigned idx1 = 1; // dst |
| 16011 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 16012 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp1 |
| 16013 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2 |
| 16014 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp3 |
| 16015 | unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // tmp4 |
| 16016 | st->print_raw("vector_minmax2D_reduction "); |
| 16017 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 16018 | st->print_raw(","); |
| 16019 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 16020 | st->print_raw(" ; using "); |
| 16021 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp1 |
| 16022 | st->print_raw(", "); |
| 16023 | opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2 |
| 16024 | st->print_raw(", "); |
| 16025 | opnd_array(5)->ext_format(ra, this,idx5, st); // tmp3 |
| 16026 | st->print_raw(", "); |
| 16027 | opnd_array(6)->ext_format(ra, this,idx6, st); // tmp4 |
| 16028 | st->print_raw(" as TEMP"); |
| 16029 | } |
| 16030 | #endif |
| 16031 | #ifndef PRODUCT |
| 16032 | void minmax_reductionD_avNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 16033 | // Start at oper_input_base() and count operands |
| 16034 | unsigned idx0 = 1; |
| 16035 | unsigned idx1 = 1; // dst |
| 16036 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 16037 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp1 |
| 16038 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2 |
| 16039 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp3 |
| 16040 | unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // tmp4 |
| 16041 | unsigned idx7 = idx6 + opnd_array(6)->num_edges(); // tmp5 |
| 16042 | st->print_raw("vector_minmaxD_reduction "); |
| 16043 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 16044 | st->print_raw(","); |
| 16045 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 16046 | st->print_raw(" ; using "); |
| 16047 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp1 |
| 16048 | st->print_raw(", "); |
| 16049 | opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2 |
| 16050 | st->print_raw(", "); |
| 16051 | opnd_array(5)->ext_format(ra, this,idx5, st); // tmp3 |
| 16052 | st->print_raw(", "); |
| 16053 | opnd_array(6)->ext_format(ra, this,idx6, st); // tmp4 |
| 16054 | st->print_raw(", "); |
| 16055 | opnd_array(7)->ext_format(ra, this,idx7, st); // tmp5 |
| 16056 | st->print_raw(" as TEMP"); |
| 16057 | } |
| 16058 | #endif |
| 16059 | #ifndef PRODUCT |
| 16060 | void minmax_reductionD_av_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 16061 | // Start at oper_input_base() and count operands |
| 16062 | unsigned idx0 = 1; |
| 16063 | unsigned idx1 = 1; // dst |
| 16064 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 16065 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp1 |
| 16066 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2 |
| 16067 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp3 |
| 16068 | unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // tmp4 |
| 16069 | unsigned idx7 = idx6 + opnd_array(6)->num_edges(); // tmp5 |
| 16070 | st->print_raw("vector_minmaxD_reduction "); |
| 16071 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 16072 | st->print_raw(","); |
| 16073 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 16074 | st->print_raw(" ; using "); |
| 16075 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp1 |
| 16076 | st->print_raw(", "); |
| 16077 | opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2 |
| 16078 | st->print_raw(", "); |
| 16079 | opnd_array(5)->ext_format(ra, this,idx5, st); // tmp3 |
| 16080 | st->print_raw(", "); |
| 16081 | opnd_array(6)->ext_format(ra, this,idx6, st); // tmp4 |
| 16082 | st->print_raw(", "); |
| 16083 | opnd_array(7)->ext_format(ra, this,idx7, st); // tmp5 |
| 16084 | st->print_raw(" as TEMP"); |
| 16085 | } |
| 16086 | #endif |
| 16087 | #ifndef PRODUCT |
| 16088 | void vaddBNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 16089 | // Start at oper_input_base() and count operands |
| 16090 | unsigned idx0 = 1; |
| 16091 | unsigned idx1 = 1; // dst |
| 16092 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 16093 | st->print_raw("paddb "); |
| 16094 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 16095 | st->print_raw(","); |
| 16096 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 16097 | st->print_raw("\t! add packedB"); |
| 16098 | } |
| 16099 | #endif |
| 16100 | #ifndef PRODUCT |
| 16101 | void vaddB_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 16102 | // Start at oper_input_base() and count operands |
| 16103 | unsigned idx0 = 1; |
| 16104 | unsigned idx1 = 1; // src1 |
| 16105 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 16106 | st->print_raw("vpaddb "); |
| 16107 | opnd_array(0)->int_format(ra, this, st); // dst |
| 16108 | st->print_raw(","); |
| 16109 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 16110 | st->print_raw(","); |
| 16111 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 16112 | st->print_raw("\t! add packedB"); |
| 16113 | } |
| 16114 | #endif |
| 16115 | #ifndef PRODUCT |
| 16116 | void vaddB_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 16117 | // Start at oper_input_base() and count operands |
| 16118 | unsigned idx0 = 2; |
| 16119 | unsigned idx1 = 2; // src |
| 16120 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem |
| 16121 | st->print_raw("vpaddb "); |
| 16122 | opnd_array(0)->int_format(ra, this, st); // dst |
| 16123 | st->print_raw(","); |
| 16124 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 16125 | st->print_raw(","); |
| 16126 | opnd_array(2)->ext_format(ra, this,idx2, st); // mem |
| 16127 | st->print_raw("\t! add packedB"); |
| 16128 | } |
| 16129 | #endif |
| 16130 | #ifndef PRODUCT |
| 16131 | void vaddB_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 16132 | // Start at oper_input_base() and count operands |
| 16133 | unsigned idx0 = 2; |
| 16134 | unsigned idx1 = 2; // mem |
| 16135 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 16136 | st->print_raw("vpaddb "); |
| 16137 | opnd_array(0)->int_format(ra, this, st); // dst |
| 16138 | st->print_raw(","); |
| 16139 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 16140 | st->print_raw(","); |
| 16141 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 16142 | st->print_raw("\t! add packedB"); |
| 16143 | } |
| 16144 | #endif |
| 16145 | #ifndef PRODUCT |
| 16146 | void vaddSNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 16147 | // Start at oper_input_base() and count operands |
| 16148 | unsigned idx0 = 1; |
| 16149 | unsigned idx1 = 1; // dst |
| 16150 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 16151 | st->print_raw("paddw "); |
| 16152 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 16153 | st->print_raw(","); |
| 16154 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 16155 | st->print_raw("\t! add packedS"); |
| 16156 | } |
| 16157 | #endif |
| 16158 | #ifndef PRODUCT |
| 16159 | void vaddS_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 16160 | // Start at oper_input_base() and count operands |
| 16161 | unsigned idx0 = 1; |
| 16162 | unsigned idx1 = 1; // src1 |
| 16163 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 16164 | st->print_raw("vpaddw "); |
| 16165 | opnd_array(0)->int_format(ra, this, st); // dst |
| 16166 | st->print_raw(","); |
| 16167 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 16168 | st->print_raw(","); |
| 16169 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 16170 | st->print_raw("\t! add packedS"); |
| 16171 | } |
| 16172 | #endif |
| 16173 | #ifndef PRODUCT |
| 16174 | void vaddS_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 16175 | // Start at oper_input_base() and count operands |
| 16176 | unsigned idx0 = 2; |
| 16177 | unsigned idx1 = 2; // src |
| 16178 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem |
| 16179 | st->print_raw("vpaddw "); |
| 16180 | opnd_array(0)->int_format(ra, this, st); // dst |
| 16181 | st->print_raw(","); |
| 16182 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 16183 | st->print_raw(","); |
| 16184 | opnd_array(2)->ext_format(ra, this,idx2, st); // mem |
| 16185 | st->print_raw("\t! add packedS"); |
| 16186 | } |
| 16187 | #endif |
| 16188 | #ifndef PRODUCT |
| 16189 | void vaddS_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 16190 | // Start at oper_input_base() and count operands |
| 16191 | unsigned idx0 = 2; |
| 16192 | unsigned idx1 = 2; // mem |
| 16193 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 16194 | st->print_raw("vpaddw "); |
| 16195 | opnd_array(0)->int_format(ra, this, st); // dst |
| 16196 | st->print_raw(","); |
| 16197 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 16198 | st->print_raw(","); |
| 16199 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 16200 | st->print_raw("\t! add packedS"); |
| 16201 | } |
| 16202 | #endif |
| 16203 | #ifndef PRODUCT |
| 16204 | void vaddINode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 16205 | // Start at oper_input_base() and count operands |
| 16206 | unsigned idx0 = 1; |
| 16207 | unsigned idx1 = 1; // dst |
| 16208 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 16209 | st->print_raw("paddd "); |
| 16210 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 16211 | st->print_raw(","); |
| 16212 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 16213 | st->print_raw("\t! add packedI"); |
| 16214 | } |
| 16215 | #endif |
| 16216 | #ifndef PRODUCT |
| 16217 | void vaddI_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 16218 | // Start at oper_input_base() and count operands |
| 16219 | unsigned idx0 = 1; |
| 16220 | unsigned idx1 = 1; // src1 |
| 16221 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 16222 | st->print_raw("vpaddd "); |
| 16223 | opnd_array(0)->int_format(ra, this, st); // dst |
| 16224 | st->print_raw(","); |
| 16225 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 16226 | st->print_raw(","); |
| 16227 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 16228 | st->print_raw("\t! add packedI"); |
| 16229 | } |
| 16230 | #endif |
| 16231 | #ifndef PRODUCT |
| 16232 | void vaddI_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 16233 | // Start at oper_input_base() and count operands |
| 16234 | unsigned idx0 = 2; |
| 16235 | unsigned idx1 = 2; // src |
| 16236 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem |
| 16237 | st->print_raw("vpaddd "); |
| 16238 | opnd_array(0)->int_format(ra, this, st); // dst |
| 16239 | st->print_raw(","); |
| 16240 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 16241 | st->print_raw(","); |
| 16242 | opnd_array(2)->ext_format(ra, this,idx2, st); // mem |
| 16243 | st->print_raw("\t! add packedI"); |
| 16244 | } |
| 16245 | #endif |
| 16246 | #ifndef PRODUCT |
| 16247 | void vaddI_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 16248 | // Start at oper_input_base() and count operands |
| 16249 | unsigned idx0 = 2; |
| 16250 | unsigned idx1 = 2; // mem |
| 16251 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 16252 | st->print_raw("vpaddd "); |
| 16253 | opnd_array(0)->int_format(ra, this, st); // dst |
| 16254 | st->print_raw(","); |
| 16255 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 16256 | st->print_raw(","); |
| 16257 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 16258 | st->print_raw("\t! add packedI"); |
| 16259 | } |
| 16260 | #endif |
| 16261 | #ifndef PRODUCT |
| 16262 | void vaddLNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 16263 | // Start at oper_input_base() and count operands |
| 16264 | unsigned idx0 = 1; |
| 16265 | unsigned idx1 = 1; // dst |
| 16266 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 16267 | st->print_raw("paddq "); |
| 16268 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 16269 | st->print_raw(","); |
| 16270 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 16271 | st->print_raw("\t! add packedL"); |
| 16272 | } |
| 16273 | #endif |
| 16274 | #ifndef PRODUCT |
| 16275 | void vaddL_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 16276 | // Start at oper_input_base() and count operands |
| 16277 | unsigned idx0 = 1; |
| 16278 | unsigned idx1 = 1; // src1 |
| 16279 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 16280 | st->print_raw("vpaddq "); |
| 16281 | opnd_array(0)->int_format(ra, this, st); // dst |
| 16282 | st->print_raw(","); |
| 16283 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 16284 | st->print_raw(","); |
| 16285 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 16286 | st->print_raw("\t! add packedL"); |
| 16287 | } |
| 16288 | #endif |
| 16289 | #ifndef PRODUCT |
| 16290 | void vaddL_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 16291 | // Start at oper_input_base() and count operands |
| 16292 | unsigned idx0 = 2; |
| 16293 | unsigned idx1 = 2; // src |
| 16294 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem |
| 16295 | st->print_raw("vpaddq "); |
| 16296 | opnd_array(0)->int_format(ra, this, st); // dst |
| 16297 | st->print_raw(","); |
| 16298 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 16299 | st->print_raw(","); |
| 16300 | opnd_array(2)->ext_format(ra, this,idx2, st); // mem |
| 16301 | st->print_raw("\t! add packedL"); |
| 16302 | } |
| 16303 | #endif |
| 16304 | #ifndef PRODUCT |
| 16305 | void vaddL_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 16306 | // Start at oper_input_base() and count operands |
| 16307 | unsigned idx0 = 2; |
| 16308 | unsigned idx1 = 2; // mem |
| 16309 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 16310 | st->print_raw("vpaddq "); |
| 16311 | opnd_array(0)->int_format(ra, this, st); // dst |
| 16312 | st->print_raw(","); |
| 16313 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 16314 | st->print_raw(","); |
| 16315 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 16316 | st->print_raw("\t! add packedL"); |
| 16317 | } |
| 16318 | #endif |
| 16319 | #ifndef PRODUCT |
| 16320 | void vaddFNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 16321 | // Start at oper_input_base() and count operands |
| 16322 | unsigned idx0 = 1; |
| 16323 | unsigned idx1 = 1; // dst |
| 16324 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 16325 | st->print_raw("addps "); |
| 16326 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 16327 | st->print_raw(","); |
| 16328 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 16329 | st->print_raw("\t! add packedF"); |
| 16330 | } |
| 16331 | #endif |
| 16332 | #ifndef PRODUCT |
| 16333 | void vaddF_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 16334 | // Start at oper_input_base() and count operands |
| 16335 | unsigned idx0 = 1; |
| 16336 | unsigned idx1 = 1; // src1 |
| 16337 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 16338 | st->print_raw("vaddps "); |
| 16339 | opnd_array(0)->int_format(ra, this, st); // dst |
| 16340 | st->print_raw(","); |
| 16341 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 16342 | st->print_raw(","); |
| 16343 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 16344 | st->print_raw("\t! add packedF"); |
| 16345 | } |
| 16346 | #endif |
| 16347 | #ifndef PRODUCT |
| 16348 | void vaddF_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 16349 | // Start at oper_input_base() and count operands |
| 16350 | unsigned idx0 = 2; |
| 16351 | unsigned idx1 = 2; // src |
| 16352 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem |
| 16353 | st->print_raw("vaddps "); |
| 16354 | opnd_array(0)->int_format(ra, this, st); // dst |
| 16355 | st->print_raw(","); |
| 16356 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 16357 | st->print_raw(","); |
| 16358 | opnd_array(2)->ext_format(ra, this,idx2, st); // mem |
| 16359 | st->print_raw("\t! add packedF"); |
| 16360 | } |
| 16361 | #endif |
| 16362 | #ifndef PRODUCT |
| 16363 | void vaddF_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 16364 | // Start at oper_input_base() and count operands |
| 16365 | unsigned idx0 = 2; |
| 16366 | unsigned idx1 = 2; // mem |
| 16367 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 16368 | st->print_raw("vaddps "); |
| 16369 | opnd_array(0)->int_format(ra, this, st); // dst |
| 16370 | st->print_raw(","); |
| 16371 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 16372 | st->print_raw(","); |
| 16373 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 16374 | st->print_raw("\t! add packedF"); |
| 16375 | } |
| 16376 | #endif |
| 16377 | #ifndef PRODUCT |
| 16378 | void vaddDNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 16379 | // Start at oper_input_base() and count operands |
| 16380 | unsigned idx0 = 1; |
| 16381 | unsigned idx1 = 1; // dst |
| 16382 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 16383 | st->print_raw("addpd "); |
| 16384 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 16385 | st->print_raw(","); |
| 16386 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 16387 | st->print_raw("\t! add packedD"); |
| 16388 | } |
| 16389 | #endif |
| 16390 | #ifndef PRODUCT |
| 16391 | void vaddD_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 16392 | // Start at oper_input_base() and count operands |
| 16393 | unsigned idx0 = 1; |
| 16394 | unsigned idx1 = 1; // src1 |
| 16395 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 16396 | st->print_raw("vaddpd "); |
| 16397 | opnd_array(0)->int_format(ra, this, st); // dst |
| 16398 | st->print_raw(","); |
| 16399 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 16400 | st->print_raw(","); |
| 16401 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 16402 | st->print_raw("\t! add packedD"); |
| 16403 | } |
| 16404 | #endif |
| 16405 | #ifndef PRODUCT |
| 16406 | void vaddD_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 16407 | // Start at oper_input_base() and count operands |
| 16408 | unsigned idx0 = 2; |
| 16409 | unsigned idx1 = 2; // src |
| 16410 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem |
| 16411 | st->print_raw("vaddpd "); |
| 16412 | opnd_array(0)->int_format(ra, this, st); // dst |
| 16413 | st->print_raw(","); |
| 16414 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 16415 | st->print_raw(","); |
| 16416 | opnd_array(2)->ext_format(ra, this,idx2, st); // mem |
| 16417 | st->print_raw("\t! add packedD"); |
| 16418 | } |
| 16419 | #endif |
| 16420 | #ifndef PRODUCT |
| 16421 | void vaddD_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 16422 | // Start at oper_input_base() and count operands |
| 16423 | unsigned idx0 = 2; |
| 16424 | unsigned idx1 = 2; // mem |
| 16425 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 16426 | st->print_raw("vaddpd "); |
| 16427 | opnd_array(0)->int_format(ra, this, st); // dst |
| 16428 | st->print_raw(","); |
| 16429 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 16430 | st->print_raw(","); |
| 16431 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 16432 | st->print_raw("\t! add packedD"); |
| 16433 | } |
| 16434 | #endif |
| 16435 | #ifndef PRODUCT |
| 16436 | void vsubBNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 16437 | // Start at oper_input_base() and count operands |
| 16438 | unsigned idx0 = 1; |
| 16439 | unsigned idx1 = 1; // dst |
| 16440 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 16441 | st->print_raw("psubb "); |
| 16442 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 16443 | st->print_raw(","); |
| 16444 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 16445 | st->print_raw("\t! sub packedB"); |
| 16446 | } |
| 16447 | #endif |
| 16448 | #ifndef PRODUCT |
| 16449 | void vsubB_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 16450 | // Start at oper_input_base() and count operands |
| 16451 | unsigned idx0 = 1; |
| 16452 | unsigned idx1 = 1; // src1 |
| 16453 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 16454 | st->print_raw("vpsubb "); |
| 16455 | opnd_array(0)->int_format(ra, this, st); // dst |
| 16456 | st->print_raw(","); |
| 16457 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 16458 | st->print_raw(","); |
| 16459 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 16460 | st->print_raw("\t! sub packedB"); |
| 16461 | } |
| 16462 | #endif |
| 16463 | #ifndef PRODUCT |
| 16464 | void vsubB_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 16465 | // Start at oper_input_base() and count operands |
| 16466 | unsigned idx0 = 2; |
| 16467 | unsigned idx1 = 2; // src |
| 16468 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem |
| 16469 | st->print_raw("vpsubb "); |
| 16470 | opnd_array(0)->int_format(ra, this, st); // dst |
| 16471 | st->print_raw(","); |
| 16472 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 16473 | st->print_raw(","); |
| 16474 | opnd_array(2)->ext_format(ra, this,idx2, st); // mem |
| 16475 | st->print_raw("\t! sub packedB"); |
| 16476 | } |
| 16477 | #endif |
| 16478 | #ifndef PRODUCT |
| 16479 | void vsubSNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 16480 | // Start at oper_input_base() and count operands |
| 16481 | unsigned idx0 = 1; |
| 16482 | unsigned idx1 = 1; // dst |
| 16483 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 16484 | st->print_raw("psubw "); |
| 16485 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 16486 | st->print_raw(","); |
| 16487 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 16488 | st->print_raw("\t! sub packedS"); |
| 16489 | } |
| 16490 | #endif |
| 16491 | #ifndef PRODUCT |
| 16492 | void vsubS_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 16493 | // Start at oper_input_base() and count operands |
| 16494 | unsigned idx0 = 1; |
| 16495 | unsigned idx1 = 1; // src1 |
| 16496 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 16497 | st->print_raw("vpsubw "); |
| 16498 | opnd_array(0)->int_format(ra, this, st); // dst |
| 16499 | st->print_raw(","); |
| 16500 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 16501 | st->print_raw(","); |
| 16502 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 16503 | st->print_raw("\t! sub packedS"); |
| 16504 | } |
| 16505 | #endif |
| 16506 | #ifndef PRODUCT |
| 16507 | void vsubS_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 16508 | // Start at oper_input_base() and count operands |
| 16509 | unsigned idx0 = 2; |
| 16510 | unsigned idx1 = 2; // src |
| 16511 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem |
| 16512 | st->print_raw("vpsubw "); |
| 16513 | opnd_array(0)->int_format(ra, this, st); // dst |
| 16514 | st->print_raw(","); |
| 16515 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 16516 | st->print_raw(","); |
| 16517 | opnd_array(2)->ext_format(ra, this,idx2, st); // mem |
| 16518 | st->print_raw("\t! sub packedS"); |
| 16519 | } |
| 16520 | #endif |
| 16521 | #ifndef PRODUCT |
| 16522 | void vsubINode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 16523 | // Start at oper_input_base() and count operands |
| 16524 | unsigned idx0 = 1; |
| 16525 | unsigned idx1 = 1; // dst |
| 16526 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 16527 | st->print_raw("psubd "); |
| 16528 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 16529 | st->print_raw(","); |
| 16530 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 16531 | st->print_raw("\t! sub packedI"); |
| 16532 | } |
| 16533 | #endif |
| 16534 | #ifndef PRODUCT |
| 16535 | void vsubI_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 16536 | // Start at oper_input_base() and count operands |
| 16537 | unsigned idx0 = 1; |
| 16538 | unsigned idx1 = 1; // src1 |
| 16539 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 16540 | st->print_raw("vpsubd "); |
| 16541 | opnd_array(0)->int_format(ra, this, st); // dst |
| 16542 | st->print_raw(","); |
| 16543 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 16544 | st->print_raw(","); |
| 16545 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 16546 | st->print_raw("\t! sub packedI"); |
| 16547 | } |
| 16548 | #endif |
| 16549 | #ifndef PRODUCT |
| 16550 | void vsubI_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 16551 | // Start at oper_input_base() and count operands |
| 16552 | unsigned idx0 = 2; |
| 16553 | unsigned idx1 = 2; // src |
| 16554 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem |
| 16555 | st->print_raw("vpsubd "); |
| 16556 | opnd_array(0)->int_format(ra, this, st); // dst |
| 16557 | st->print_raw(","); |
| 16558 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 16559 | st->print_raw(","); |
| 16560 | opnd_array(2)->ext_format(ra, this,idx2, st); // mem |
| 16561 | st->print_raw("\t! sub packedI"); |
| 16562 | } |
| 16563 | #endif |
| 16564 | #ifndef PRODUCT |
| 16565 | void vsubLNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 16566 | // Start at oper_input_base() and count operands |
| 16567 | unsigned idx0 = 1; |
| 16568 | unsigned idx1 = 1; // dst |
| 16569 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 16570 | st->print_raw("psubq "); |
| 16571 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 16572 | st->print_raw(","); |
| 16573 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 16574 | st->print_raw("\t! sub packedL"); |
| 16575 | } |
| 16576 | #endif |
| 16577 | #ifndef PRODUCT |
| 16578 | void vsubL_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 16579 | // Start at oper_input_base() and count operands |
| 16580 | unsigned idx0 = 1; |
| 16581 | unsigned idx1 = 1; // src1 |
| 16582 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 16583 | st->print_raw("vpsubq "); |
| 16584 | opnd_array(0)->int_format(ra, this, st); // dst |
| 16585 | st->print_raw(","); |
| 16586 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 16587 | st->print_raw(","); |
| 16588 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 16589 | st->print_raw("\t! sub packedL"); |
| 16590 | } |
| 16591 | #endif |
| 16592 | #ifndef PRODUCT |
| 16593 | void vsubL_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 16594 | // Start at oper_input_base() and count operands |
| 16595 | unsigned idx0 = 2; |
| 16596 | unsigned idx1 = 2; // src |
| 16597 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem |
| 16598 | st->print_raw("vpsubq "); |
| 16599 | opnd_array(0)->int_format(ra, this, st); // dst |
| 16600 | st->print_raw(","); |
| 16601 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 16602 | st->print_raw(","); |
| 16603 | opnd_array(2)->ext_format(ra, this,idx2, st); // mem |
| 16604 | st->print_raw("\t! sub packedL"); |
| 16605 | } |
| 16606 | #endif |
| 16607 | #ifndef PRODUCT |
| 16608 | void vsubFNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 16609 | // Start at oper_input_base() and count operands |
| 16610 | unsigned idx0 = 1; |
| 16611 | unsigned idx1 = 1; // dst |
| 16612 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 16613 | st->print_raw("subps "); |
| 16614 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 16615 | st->print_raw(","); |
| 16616 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 16617 | st->print_raw("\t! sub packedF"); |
| 16618 | } |
| 16619 | #endif |
| 16620 | #ifndef PRODUCT |
| 16621 | void vsubF_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 16622 | // Start at oper_input_base() and count operands |
| 16623 | unsigned idx0 = 1; |
| 16624 | unsigned idx1 = 1; // src1 |
| 16625 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 16626 | st->print_raw("vsubps "); |
| 16627 | opnd_array(0)->int_format(ra, this, st); // dst |
| 16628 | st->print_raw(","); |
| 16629 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 16630 | st->print_raw(","); |
| 16631 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 16632 | st->print_raw("\t! sub packedF"); |
| 16633 | } |
| 16634 | #endif |
| 16635 | #ifndef PRODUCT |
| 16636 | void vsubF_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 16637 | // Start at oper_input_base() and count operands |
| 16638 | unsigned idx0 = 2; |
| 16639 | unsigned idx1 = 2; // src |
| 16640 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem |
| 16641 | st->print_raw("vsubps "); |
| 16642 | opnd_array(0)->int_format(ra, this, st); // dst |
| 16643 | st->print_raw(","); |
| 16644 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 16645 | st->print_raw(","); |
| 16646 | opnd_array(2)->ext_format(ra, this,idx2, st); // mem |
| 16647 | st->print_raw("\t! sub packedF"); |
| 16648 | } |
| 16649 | #endif |
| 16650 | #ifndef PRODUCT |
| 16651 | void vsubDNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 16652 | // Start at oper_input_base() and count operands |
| 16653 | unsigned idx0 = 1; |
| 16654 | unsigned idx1 = 1; // dst |
| 16655 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 16656 | st->print_raw("subpd "); |
| 16657 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 16658 | st->print_raw(","); |
| 16659 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 16660 | st->print_raw("\t! sub packedD"); |
| 16661 | } |
| 16662 | #endif |
| 16663 | #ifndef PRODUCT |
| 16664 | void vsubD_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 16665 | // Start at oper_input_base() and count operands |
| 16666 | unsigned idx0 = 1; |
| 16667 | unsigned idx1 = 1; // src1 |
| 16668 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 16669 | st->print_raw("vsubpd "); |
| 16670 | opnd_array(0)->int_format(ra, this, st); // dst |
| 16671 | st->print_raw(","); |
| 16672 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 16673 | st->print_raw(","); |
| 16674 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 16675 | st->print_raw("\t! sub packedD"); |
| 16676 | } |
| 16677 | #endif |
| 16678 | #ifndef PRODUCT |
| 16679 | void vsubD_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 16680 | // Start at oper_input_base() and count operands |
| 16681 | unsigned idx0 = 2; |
| 16682 | unsigned idx1 = 2; // src |
| 16683 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem |
| 16684 | st->print_raw("vsubpd "); |
| 16685 | opnd_array(0)->int_format(ra, this, st); // dst |
| 16686 | st->print_raw(","); |
| 16687 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 16688 | st->print_raw(","); |
| 16689 | opnd_array(2)->ext_format(ra, this,idx2, st); // mem |
| 16690 | st->print_raw("\t! sub packedD"); |
| 16691 | } |
| 16692 | #endif |
| 16693 | #ifndef PRODUCT |
| 16694 | void mulB_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 16695 | // Start at oper_input_base() and count operands |
| 16696 | unsigned idx0 = 1; |
| 16697 | unsigned idx1 = 1; // src1 |
| 16698 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 16699 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 16700 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp |
| 16701 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch |
| 16702 | st->print_raw("vector_mulB "); |
| 16703 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 16704 | st->print_raw(","); |
| 16705 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 16706 | st->print_raw(","); |
| 16707 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 16708 | } |
| 16709 | #endif |
| 16710 | #ifndef PRODUCT |
| 16711 | void mul16B_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 16712 | // Start at oper_input_base() and count operands |
| 16713 | unsigned idx0 = 1; |
| 16714 | unsigned idx1 = 1; // src1 |
| 16715 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 16716 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 16717 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1 |
| 16718 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2 |
| 16719 | unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // scratch |
| 16720 | st->print_raw("vector_mulB "); |
| 16721 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 16722 | st->print_raw(","); |
| 16723 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 16724 | st->print_raw(","); |
| 16725 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 16726 | } |
| 16727 | #endif |
| 16728 | #ifndef PRODUCT |
| 16729 | void vmul16B_reg_avxNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 16730 | // Start at oper_input_base() and count operands |
| 16731 | unsigned idx0 = 1; |
| 16732 | unsigned idx1 = 1; // src1 |
| 16733 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 16734 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 16735 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp |
| 16736 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch |
| 16737 | st->print_raw("vector_mulB "); |
| 16738 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 16739 | st->print_raw(","); |
| 16740 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 16741 | st->print_raw(","); |
| 16742 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 16743 | } |
| 16744 | #endif |
| 16745 | #ifndef PRODUCT |
| 16746 | void vmul32B_reg_avxNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 16747 | // Start at oper_input_base() and count operands |
| 16748 | unsigned idx0 = 1; |
| 16749 | unsigned idx1 = 1; // src1 |
| 16750 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 16751 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 16752 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1 |
| 16753 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2 |
| 16754 | unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // scratch |
| 16755 | st->print_raw("vector_mulB "); |
| 16756 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 16757 | st->print_raw(","); |
| 16758 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 16759 | st->print_raw(","); |
| 16760 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 16761 | } |
| 16762 | #endif |
| 16763 | #ifndef PRODUCT |
| 16764 | void vmul64B_reg_avxNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 16765 | // Start at oper_input_base() and count operands |
| 16766 | unsigned idx0 = 1; |
| 16767 | unsigned idx1 = 1; // src1 |
| 16768 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 16769 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 16770 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1 |
| 16771 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2 |
| 16772 | unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // scratch |
| 16773 | st->print_raw("vector_mulB "); |
| 16774 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 16775 | st->print_raw(","); |
| 16776 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 16777 | st->print_raw(","); |
| 16778 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 16779 | st->print_raw("\n\t"); |
| 16780 | } |
| 16781 | #endif |
| 16782 | #ifndef PRODUCT |
| 16783 | void vmulSNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 16784 | // Start at oper_input_base() and count operands |
| 16785 | unsigned idx0 = 1; |
| 16786 | unsigned idx1 = 1; // dst |
| 16787 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 16788 | st->print_raw("pmullw "); |
| 16789 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 16790 | st->print_raw(","); |
| 16791 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 16792 | st->print_raw("\t! mul packedS"); |
| 16793 | } |
| 16794 | #endif |
| 16795 | #ifndef PRODUCT |
| 16796 | void vmulS_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 16797 | // Start at oper_input_base() and count operands |
| 16798 | unsigned idx0 = 1; |
| 16799 | unsigned idx1 = 1; // src1 |
| 16800 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 16801 | st->print_raw("vpmullw "); |
| 16802 | opnd_array(0)->int_format(ra, this, st); // dst |
| 16803 | st->print_raw(","); |
| 16804 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 16805 | st->print_raw(","); |
| 16806 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 16807 | st->print_raw("\t! mul packedS"); |
| 16808 | } |
| 16809 | #endif |
| 16810 | #ifndef PRODUCT |
| 16811 | void vmulS_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 16812 | // Start at oper_input_base() and count operands |
| 16813 | unsigned idx0 = 2; |
| 16814 | unsigned idx1 = 2; // src |
| 16815 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem |
| 16816 | st->print_raw("vpmullw "); |
| 16817 | opnd_array(0)->int_format(ra, this, st); // dst |
| 16818 | st->print_raw(","); |
| 16819 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 16820 | st->print_raw(","); |
| 16821 | opnd_array(2)->ext_format(ra, this,idx2, st); // mem |
| 16822 | st->print_raw("\t! mul packedS"); |
| 16823 | } |
| 16824 | #endif |
| 16825 | #ifndef PRODUCT |
| 16826 | void vmulS_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 16827 | // Start at oper_input_base() and count operands |
| 16828 | unsigned idx0 = 2; |
| 16829 | unsigned idx1 = 2; // mem |
| 16830 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 16831 | st->print_raw("vpmullw "); |
| 16832 | opnd_array(0)->int_format(ra, this, st); // dst |
| 16833 | st->print_raw(","); |
| 16834 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 16835 | st->print_raw(","); |
| 16836 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 16837 | st->print_raw("\t! mul packedS"); |
| 16838 | } |
| 16839 | #endif |
| 16840 | #ifndef PRODUCT |
| 16841 | void vmulINode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 16842 | // Start at oper_input_base() and count operands |
| 16843 | unsigned idx0 = 1; |
| 16844 | unsigned idx1 = 1; // dst |
| 16845 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 16846 | st->print_raw("pmulld "); |
| 16847 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 16848 | st->print_raw(","); |
| 16849 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 16850 | st->print_raw("\t! mul packedI"); |
| 16851 | } |
| 16852 | #endif |
| 16853 | #ifndef PRODUCT |
| 16854 | void vmulI_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 16855 | // Start at oper_input_base() and count operands |
| 16856 | unsigned idx0 = 1; |
| 16857 | unsigned idx1 = 1; // src1 |
| 16858 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 16859 | st->print_raw("vpmulld "); |
| 16860 | opnd_array(0)->int_format(ra, this, st); // dst |
| 16861 | st->print_raw(","); |
| 16862 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 16863 | st->print_raw(","); |
| 16864 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 16865 | st->print_raw("\t! mul packedI"); |
| 16866 | } |
| 16867 | #endif |
| 16868 | #ifndef PRODUCT |
| 16869 | void vmulI_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 16870 | // Start at oper_input_base() and count operands |
| 16871 | unsigned idx0 = 2; |
| 16872 | unsigned idx1 = 2; // src |
| 16873 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem |
| 16874 | st->print_raw("vpmulld "); |
| 16875 | opnd_array(0)->int_format(ra, this, st); // dst |
| 16876 | st->print_raw(","); |
| 16877 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 16878 | st->print_raw(","); |
| 16879 | opnd_array(2)->ext_format(ra, this,idx2, st); // mem |
| 16880 | st->print_raw("\t! mul packedI"); |
| 16881 | } |
| 16882 | #endif |
| 16883 | #ifndef PRODUCT |
| 16884 | void vmulI_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 16885 | // Start at oper_input_base() and count operands |
| 16886 | unsigned idx0 = 2; |
| 16887 | unsigned idx1 = 2; // mem |
| 16888 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 16889 | st->print_raw("vpmulld "); |
| 16890 | opnd_array(0)->int_format(ra, this, st); // dst |
| 16891 | st->print_raw(","); |
| 16892 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 16893 | st->print_raw(","); |
| 16894 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 16895 | st->print_raw("\t! mul packedI"); |
| 16896 | } |
| 16897 | #endif |
| 16898 | #ifndef PRODUCT |
| 16899 | void vmulL_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 16900 | // Start at oper_input_base() and count operands |
| 16901 | unsigned idx0 = 1; |
| 16902 | unsigned idx1 = 1; // src1 |
| 16903 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 16904 | st->print_raw("vpmullq "); |
| 16905 | opnd_array(0)->int_format(ra, this, st); // dst |
| 16906 | st->print_raw(","); |
| 16907 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 16908 | st->print_raw(","); |
| 16909 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 16910 | st->print_raw("\t! mul packedL"); |
| 16911 | } |
| 16912 | #endif |
| 16913 | #ifndef PRODUCT |
| 16914 | void vmulL_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 16915 | // Start at oper_input_base() and count operands |
| 16916 | unsigned idx0 = 2; |
| 16917 | unsigned idx1 = 2; // src |
| 16918 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem |
| 16919 | st->print_raw("vpmullq "); |
| 16920 | opnd_array(0)->int_format(ra, this, st); // dst |
| 16921 | st->print_raw(","); |
| 16922 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 16923 | st->print_raw(","); |
| 16924 | opnd_array(2)->ext_format(ra, this,idx2, st); // mem |
| 16925 | st->print_raw("\t! mul packedL"); |
| 16926 | } |
| 16927 | #endif |
| 16928 | #ifndef PRODUCT |
| 16929 | void vmulL_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 16930 | // Start at oper_input_base() and count operands |
| 16931 | unsigned idx0 = 2; |
| 16932 | unsigned idx1 = 2; // mem |
| 16933 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 16934 | st->print_raw("vpmullq "); |
| 16935 | opnd_array(0)->int_format(ra, this, st); // dst |
| 16936 | st->print_raw(","); |
| 16937 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 16938 | st->print_raw(","); |
| 16939 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 16940 | st->print_raw("\t! mul packedL"); |
| 16941 | } |
| 16942 | #endif |
| 16943 | #ifndef PRODUCT |
| 16944 | void mul2L_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 16945 | // Start at oper_input_base() and count operands |
| 16946 | unsigned idx0 = 1; |
| 16947 | unsigned idx1 = 1; // dst |
| 16948 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 16949 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp |
| 16950 | st->print_raw("pshufd "); |
| 16951 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp |
| 16952 | st->print_raw(","); |
| 16953 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 16954 | st->print_raw(", 177\n\t"); |
| 16955 | st->print_raw("pmulld "); |
| 16956 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp |
| 16957 | st->print_raw(","); |
| 16958 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 16959 | st->print_raw("\n\t"); |
| 16960 | st->print_raw("phaddd "); |
| 16961 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp |
| 16962 | st->print_raw(","); |
| 16963 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp |
| 16964 | st->print_raw("\n\t"); |
| 16965 | st->print_raw("pmovzxdq "); |
| 16966 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp |
| 16967 | st->print_raw(","); |
| 16968 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp |
| 16969 | st->print_raw("\n\t"); |
| 16970 | st->print_raw("psllq "); |
| 16971 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp |
| 16972 | st->print_raw(", 32\n\t"); |
| 16973 | st->print_raw("pmuludq "); |
| 16974 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 16975 | st->print_raw(","); |
| 16976 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 16977 | st->print_raw("\n\t"); |
| 16978 | st->print_raw("paddq "); |
| 16979 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 16980 | st->print_raw(","); |
| 16981 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp |
| 16982 | st->print_raw("\n\t! mul packed2L"); |
| 16983 | } |
| 16984 | #endif |
| 16985 | #ifndef PRODUCT |
| 16986 | void vmul4L_reg_avxNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 16987 | // Start at oper_input_base() and count operands |
| 16988 | unsigned idx0 = 1; |
| 16989 | unsigned idx1 = 1; // src1 |
| 16990 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 16991 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp |
| 16992 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1 |
| 16993 | st->print_raw("vpshufd "); |
| 16994 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp |
| 16995 | st->print_raw(","); |
| 16996 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 16997 | st->print_raw("\n\t"); |
| 16998 | st->print_raw("vpmulld "); |
| 16999 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp |
| 17000 | st->print_raw(","); |
| 17001 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 17002 | st->print_raw(","); |
| 17003 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp |
| 17004 | st->print_raw("\n\t"); |
| 17005 | st->print_raw("vphaddd "); |
| 17006 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp |
| 17007 | st->print_raw(","); |
| 17008 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp |
| 17009 | st->print_raw(","); |
| 17010 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp |
| 17011 | st->print_raw("\n\t"); |
| 17012 | st->print_raw("vpmovzxdq "); |
| 17013 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp |
| 17014 | st->print_raw(","); |
| 17015 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp |
| 17016 | st->print_raw("\n\t"); |
| 17017 | st->print_raw("vpsllq "); |
| 17018 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp |
| 17019 | st->print_raw(","); |
| 17020 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp |
| 17021 | st->print_raw("\n\t"); |
| 17022 | st->print_raw("vpmuludq "); |
| 17023 | opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1 |
| 17024 | st->print_raw(","); |
| 17025 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 17026 | st->print_raw(","); |
| 17027 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 17028 | st->print_raw("\n\t"); |
| 17029 | st->print_raw("vpaddq "); |
| 17030 | opnd_array(0)->int_format(ra, this, st); // dst |
| 17031 | st->print_raw(","); |
| 17032 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp |
| 17033 | st->print_raw(","); |
| 17034 | opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1 |
| 17035 | st->print_raw("\t! mul packed4L"); |
| 17036 | } |
| 17037 | #endif |
| 17038 | #ifndef PRODUCT |
| 17039 | void vmulFNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 17040 | // Start at oper_input_base() and count operands |
| 17041 | unsigned idx0 = 1; |
| 17042 | unsigned idx1 = 1; // dst |
| 17043 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 17044 | st->print_raw("mulps "); |
| 17045 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 17046 | st->print_raw(","); |
| 17047 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 17048 | st->print_raw("\t! mul packedF"); |
| 17049 | } |
| 17050 | #endif |
| 17051 | #ifndef PRODUCT |
| 17052 | void vmulF_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 17053 | // Start at oper_input_base() and count operands |
| 17054 | unsigned idx0 = 1; |
| 17055 | unsigned idx1 = 1; // src1 |
| 17056 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 17057 | st->print_raw("vmulps "); |
| 17058 | opnd_array(0)->int_format(ra, this, st); // dst |
| 17059 | st->print_raw(","); |
| 17060 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 17061 | st->print_raw(","); |
| 17062 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 17063 | st->print_raw("\t! mul packedF"); |
| 17064 | } |
| 17065 | #endif |
| 17066 | #ifndef PRODUCT |
| 17067 | void vmulF_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 17068 | // Start at oper_input_base() and count operands |
| 17069 | unsigned idx0 = 2; |
| 17070 | unsigned idx1 = 2; // src |
| 17071 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem |
| 17072 | st->print_raw("vmulps "); |
| 17073 | opnd_array(0)->int_format(ra, this, st); // dst |
| 17074 | st->print_raw(","); |
| 17075 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 17076 | st->print_raw(","); |
| 17077 | opnd_array(2)->ext_format(ra, this,idx2, st); // mem |
| 17078 | st->print_raw("\t! mul packedF"); |
| 17079 | } |
| 17080 | #endif |
| 17081 | #ifndef PRODUCT |
| 17082 | void vmulF_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 17083 | // Start at oper_input_base() and count operands |
| 17084 | unsigned idx0 = 2; |
| 17085 | unsigned idx1 = 2; // mem |
| 17086 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 17087 | st->print_raw("vmulps "); |
| 17088 | opnd_array(0)->int_format(ra, this, st); // dst |
| 17089 | st->print_raw(","); |
| 17090 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 17091 | st->print_raw(","); |
| 17092 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 17093 | st->print_raw("\t! mul packedF"); |
| 17094 | } |
| 17095 | #endif |
| 17096 | #ifndef PRODUCT |
| 17097 | void vmulDNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 17098 | // Start at oper_input_base() and count operands |
| 17099 | unsigned idx0 = 1; |
| 17100 | unsigned idx1 = 1; // dst |
| 17101 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 17102 | st->print_raw("mulpd "); |
| 17103 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 17104 | st->print_raw(","); |
| 17105 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 17106 | st->print_raw("\t! mul packedD"); |
| 17107 | } |
| 17108 | #endif |
| 17109 | #ifndef PRODUCT |
| 17110 | void vmulD_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 17111 | // Start at oper_input_base() and count operands |
| 17112 | unsigned idx0 = 1; |
| 17113 | unsigned idx1 = 1; // src1 |
| 17114 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 17115 | st->print_raw("vmulpd "); |
| 17116 | opnd_array(0)->int_format(ra, this, st); // dst |
| 17117 | st->print_raw(","); |
| 17118 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 17119 | st->print_raw(","); |
| 17120 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 17121 | st->print_raw("\t! mul packedD"); |
| 17122 | } |
| 17123 | #endif |
| 17124 | #ifndef PRODUCT |
| 17125 | void vmulD_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 17126 | // Start at oper_input_base() and count operands |
| 17127 | unsigned idx0 = 2; |
| 17128 | unsigned idx1 = 2; // src |
| 17129 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem |
| 17130 | st->print_raw("vmulpd "); |
| 17131 | opnd_array(0)->int_format(ra, this, st); // dst |
| 17132 | st->print_raw(","); |
| 17133 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 17134 | st->print_raw(","); |
| 17135 | opnd_array(2)->ext_format(ra, this,idx2, st); // mem |
| 17136 | st->print_raw("\t! mul packedD"); |
| 17137 | } |
| 17138 | #endif |
| 17139 | #ifndef PRODUCT |
| 17140 | void vmulD_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 17141 | // Start at oper_input_base() and count operands |
| 17142 | unsigned idx0 = 2; |
| 17143 | unsigned idx1 = 2; // mem |
| 17144 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 17145 | st->print_raw("vmulpd "); |
| 17146 | opnd_array(0)->int_format(ra, this, st); // dst |
| 17147 | st->print_raw(","); |
| 17148 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 17149 | st->print_raw(","); |
| 17150 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 17151 | st->print_raw("\t! mul packedD"); |
| 17152 | } |
| 17153 | #endif |
| 17154 | #ifndef PRODUCT |
| 17155 | void vcmov8F_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 17156 | // Start at oper_input_base() and count operands |
| 17157 | unsigned idx0 = 1; |
| 17158 | unsigned idx1 = 1; // copnd |
| 17159 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cop |
| 17160 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // src1 |
| 17161 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src2 |
| 17162 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // dst |
| 17163 | st->print_raw("cmpps."); |
| 17164 | opnd_array(1)->ext_format(ra, this,idx1, st); // copnd |
| 17165 | st->print_raw(" "); |
| 17166 | opnd_array(5)->ext_format(ra, this,idx5, st); // dst |
| 17167 | st->print_raw(", "); |
| 17168 | opnd_array(3)->ext_format(ra, this,idx3, st); // src1 |
| 17169 | st->print_raw(", "); |
| 17170 | opnd_array(4)->ext_format(ra, this,idx4, st); // src2 |
| 17171 | st->print_raw(" ! vcmovevf, cond="); |
| 17172 | opnd_array(2)->ext_format(ra, this,idx2, st); // cop |
| 17173 | st->print_raw("\n\t"); |
| 17174 | st->print_raw("blendvps "); |
| 17175 | opnd_array(5)->ext_format(ra, this,idx5, st); // dst |
| 17176 | st->print_raw(","); |
| 17177 | opnd_array(3)->ext_format(ra, this,idx3, st); // src1 |
| 17178 | st->print_raw(","); |
| 17179 | opnd_array(4)->ext_format(ra, this,idx4, st); // src2 |
| 17180 | st->print_raw(","); |
| 17181 | opnd_array(5)->ext_format(ra, this,idx5, st); // dst |
| 17182 | st->print_raw(" ! vcmovevf\n\t"); |
| 17183 | } |
| 17184 | #endif |
| 17185 | #ifndef PRODUCT |
| 17186 | void vcmov4D_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 17187 | // Start at oper_input_base() and count operands |
| 17188 | unsigned idx0 = 1; |
| 17189 | unsigned idx1 = 1; // copnd |
| 17190 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cop |
| 17191 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // src1 |
| 17192 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src2 |
| 17193 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // dst |
| 17194 | st->print_raw("cmppd."); |
| 17195 | opnd_array(1)->ext_format(ra, this,idx1, st); // copnd |
| 17196 | st->print_raw(" "); |
| 17197 | opnd_array(5)->ext_format(ra, this,idx5, st); // dst |
| 17198 | st->print_raw(", "); |
| 17199 | opnd_array(3)->ext_format(ra, this,idx3, st); // src1 |
| 17200 | st->print_raw(", "); |
| 17201 | opnd_array(4)->ext_format(ra, this,idx4, st); // src2 |
| 17202 | st->print_raw(" ! vcmovevd, cond="); |
| 17203 | opnd_array(2)->ext_format(ra, this,idx2, st); // cop |
| 17204 | st->print_raw("\n\t"); |
| 17205 | st->print_raw("vblendvpd "); |
| 17206 | opnd_array(5)->ext_format(ra, this,idx5, st); // dst |
| 17207 | st->print_raw(","); |
| 17208 | opnd_array(3)->ext_format(ra, this,idx3, st); // src1 |
| 17209 | st->print_raw(","); |
| 17210 | opnd_array(4)->ext_format(ra, this,idx4, st); // src2 |
| 17211 | st->print_raw(","); |
| 17212 | opnd_array(5)->ext_format(ra, this,idx5, st); // dst |
| 17213 | st->print_raw(" ! vcmovevd\n\t"); |
| 17214 | } |
| 17215 | #endif |
| 17216 | #ifndef PRODUCT |
| 17217 | void vdivFNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 17218 | // Start at oper_input_base() and count operands |
| 17219 | unsigned idx0 = 1; |
| 17220 | unsigned idx1 = 1; // dst |
| 17221 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 17222 | st->print_raw("divps "); |
| 17223 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 17224 | st->print_raw(","); |
| 17225 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 17226 | st->print_raw("\t! div packedF"); |
| 17227 | } |
| 17228 | #endif |
| 17229 | #ifndef PRODUCT |
| 17230 | void vdivF_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 17231 | // Start at oper_input_base() and count operands |
| 17232 | unsigned idx0 = 1; |
| 17233 | unsigned idx1 = 1; // src1 |
| 17234 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 17235 | st->print_raw("vdivps "); |
| 17236 | opnd_array(0)->int_format(ra, this, st); // dst |
| 17237 | st->print_raw(","); |
| 17238 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 17239 | st->print_raw(","); |
| 17240 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 17241 | st->print_raw("\t! div packedF"); |
| 17242 | } |
| 17243 | #endif |
| 17244 | #ifndef PRODUCT |
| 17245 | void vdivF_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 17246 | // Start at oper_input_base() and count operands |
| 17247 | unsigned idx0 = 2; |
| 17248 | unsigned idx1 = 2; // src |
| 17249 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem |
| 17250 | st->print_raw("vdivps "); |
| 17251 | opnd_array(0)->int_format(ra, this, st); // dst |
| 17252 | st->print_raw(","); |
| 17253 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 17254 | st->print_raw(","); |
| 17255 | opnd_array(2)->ext_format(ra, this,idx2, st); // mem |
| 17256 | st->print_raw("\t! div packedF"); |
| 17257 | } |
| 17258 | #endif |
| 17259 | #ifndef PRODUCT |
| 17260 | void vdivDNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 17261 | // Start at oper_input_base() and count operands |
| 17262 | unsigned idx0 = 1; |
| 17263 | unsigned idx1 = 1; // dst |
| 17264 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 17265 | st->print_raw("divpd "); |
| 17266 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 17267 | st->print_raw(","); |
| 17268 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 17269 | st->print_raw("\t! div packedD"); |
| 17270 | } |
| 17271 | #endif |
| 17272 | #ifndef PRODUCT |
| 17273 | void vdivD_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 17274 | // Start at oper_input_base() and count operands |
| 17275 | unsigned idx0 = 1; |
| 17276 | unsigned idx1 = 1; // src1 |
| 17277 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 17278 | st->print_raw("vdivpd "); |
| 17279 | opnd_array(0)->int_format(ra, this, st); // dst |
| 17280 | st->print_raw(","); |
| 17281 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 17282 | st->print_raw(","); |
| 17283 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 17284 | st->print_raw("\t! div packedD"); |
| 17285 | } |
| 17286 | #endif |
| 17287 | #ifndef PRODUCT |
| 17288 | void vdivD_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 17289 | // Start at oper_input_base() and count operands |
| 17290 | unsigned idx0 = 2; |
| 17291 | unsigned idx1 = 2; // src |
| 17292 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem |
| 17293 | st->print_raw("vdivpd "); |
| 17294 | opnd_array(0)->int_format(ra, this, st); // dst |
| 17295 | st->print_raw(","); |
| 17296 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 17297 | st->print_raw(","); |
| 17298 | opnd_array(2)->ext_format(ra, this,idx2, st); // mem |
| 17299 | st->print_raw("\t! div packedD"); |
| 17300 | } |
| 17301 | #endif |
| 17302 | #ifndef PRODUCT |
| 17303 | void minmax_reg_sseNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 17304 | // Start at oper_input_base() and count operands |
| 17305 | unsigned idx0 = 1; |
| 17306 | unsigned idx1 = 1; // dst |
| 17307 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 17308 | st->print_raw("vector_minmax "); |
| 17309 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 17310 | st->print_raw(","); |
| 17311 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 17312 | st->print_raw("\t! "); |
| 17313 | } |
| 17314 | #endif |
| 17315 | #ifndef PRODUCT |
| 17316 | void minmax_reg_sse_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 17317 | // Start at oper_input_base() and count operands |
| 17318 | unsigned idx0 = 1; |
| 17319 | unsigned idx1 = 1; // dst |
| 17320 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 17321 | st->print_raw("vector_minmax "); |
| 17322 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 17323 | st->print_raw(","); |
| 17324 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 17325 | st->print_raw("\t! "); |
| 17326 | } |
| 17327 | #endif |
| 17328 | #ifndef PRODUCT |
| 17329 | void vminmax_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 17330 | // Start at oper_input_base() and count operands |
| 17331 | unsigned idx0 = 1; |
| 17332 | unsigned idx1 = 1; // src1 |
| 17333 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 17334 | st->print_raw("vector_minmax "); |
| 17335 | opnd_array(0)->int_format(ra, this, st); // dst |
| 17336 | st->print_raw(","); |
| 17337 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 17338 | st->print_raw(","); |
| 17339 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 17340 | st->print_raw("\t! "); |
| 17341 | } |
| 17342 | #endif |
| 17343 | #ifndef PRODUCT |
| 17344 | void vminmax_reg_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 17345 | // Start at oper_input_base() and count operands |
| 17346 | unsigned idx0 = 1; |
| 17347 | unsigned idx1 = 1; // src1 |
| 17348 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 17349 | st->print_raw("vector_minmax "); |
| 17350 | opnd_array(0)->int_format(ra, this, st); // dst |
| 17351 | st->print_raw(","); |
| 17352 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 17353 | st->print_raw(","); |
| 17354 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 17355 | st->print_raw("\t! "); |
| 17356 | } |
| 17357 | #endif |
| 17358 | #ifndef PRODUCT |
| 17359 | void minmaxL_reg_sseNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 17360 | // Start at oper_input_base() and count operands |
| 17361 | unsigned idx0 = 1; |
| 17362 | unsigned idx1 = 1; // dst |
| 17363 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 17364 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp |
| 17365 | st->print_raw("vector_minmaxL "); |
| 17366 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 17367 | st->print_raw(","); |
| 17368 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 17369 | st->print_raw("\t!using "); |
| 17370 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp |
| 17371 | st->print_raw(" as TEMP"); |
| 17372 | } |
| 17373 | #endif |
| 17374 | #ifndef PRODUCT |
| 17375 | void minmaxL_reg_sse_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 17376 | // Start at oper_input_base() and count operands |
| 17377 | unsigned idx0 = 1; |
| 17378 | unsigned idx1 = 1; // src |
| 17379 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst |
| 17380 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp |
| 17381 | st->print_raw("vector_minmaxL "); |
| 17382 | opnd_array(2)->ext_format(ra, this,idx2, st); // dst |
| 17383 | st->print_raw(","); |
| 17384 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 17385 | st->print_raw("\t!using "); |
| 17386 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp |
| 17387 | st->print_raw(" as TEMP"); |
| 17388 | } |
| 17389 | #endif |
| 17390 | #ifndef PRODUCT |
| 17391 | void vminmaxL_reg_avxNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 17392 | // Start at oper_input_base() and count operands |
| 17393 | unsigned idx0 = 1; |
| 17394 | unsigned idx1 = 1; // src1 |
| 17395 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 17396 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 17397 | st->print_raw("vector_minmaxL "); |
| 17398 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 17399 | st->print_raw(","); |
| 17400 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 17401 | st->print_raw(","); |
| 17402 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 17403 | st->print_raw("\t! "); |
| 17404 | } |
| 17405 | #endif |
| 17406 | #ifndef PRODUCT |
| 17407 | void vminmaxL_reg_avx_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 17408 | // Start at oper_input_base() and count operands |
| 17409 | unsigned idx0 = 1; |
| 17410 | unsigned idx1 = 1; // src1 |
| 17411 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 17412 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 17413 | st->print_raw("vector_minmaxL "); |
| 17414 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 17415 | st->print_raw(","); |
| 17416 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 17417 | st->print_raw(","); |
| 17418 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 17419 | st->print_raw("\t! "); |
| 17420 | } |
| 17421 | #endif |
| 17422 | #ifndef PRODUCT |
| 17423 | void vminmaxL_reg_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 17424 | // Start at oper_input_base() and count operands |
| 17425 | unsigned idx0 = 1; |
| 17426 | unsigned idx1 = 1; // src1 |
| 17427 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 17428 | st->print_raw("vector_minmaxL "); |
| 17429 | opnd_array(0)->int_format(ra, this, st); // dst |
| 17430 | st->print_raw(","); |
| 17431 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 17432 | st->print_raw(",src2\t! "); |
| 17433 | } |
| 17434 | #endif |
| 17435 | #ifndef PRODUCT |
| 17436 | void vminmaxL_reg_evex_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 17437 | // Start at oper_input_base() and count operands |
| 17438 | unsigned idx0 = 1; |
| 17439 | unsigned idx1 = 1; // src1 |
| 17440 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 17441 | st->print_raw("vector_minmaxL "); |
| 17442 | opnd_array(0)->int_format(ra, this, st); // dst |
| 17443 | st->print_raw(","); |
| 17444 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 17445 | st->print_raw(",src2\t! "); |
| 17446 | } |
| 17447 | #endif |
| 17448 | #ifndef PRODUCT |
| 17449 | void minmaxFP_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 17450 | // Start at oper_input_base() and count operands |
| 17451 | unsigned idx0 = 1; |
| 17452 | unsigned idx1 = 1; // a |
| 17453 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // b |
| 17454 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp |
| 17455 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // atmp |
| 17456 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // btmp |
| 17457 | st->print_raw("vector_minmaxFP "); |
| 17458 | opnd_array(0)->int_format(ra, this, st); // dst |
| 17459 | st->print_raw(","); |
| 17460 | opnd_array(1)->ext_format(ra, this,idx1, st); // a |
| 17461 | st->print_raw(","); |
| 17462 | opnd_array(2)->ext_format(ra, this,idx2, st); // b |
| 17463 | st->print_raw("\t!using "); |
| 17464 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp |
| 17465 | st->print_raw(", "); |
| 17466 | opnd_array(4)->ext_format(ra, this,idx4, st); // atmp |
| 17467 | st->print_raw(", "); |
| 17468 | opnd_array(5)->ext_format(ra, this,idx5, st); // btmp |
| 17469 | st->print_raw(" as TEMP"); |
| 17470 | } |
| 17471 | #endif |
| 17472 | #ifndef PRODUCT |
| 17473 | void minmaxFP_reg_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 17474 | // Start at oper_input_base() and count operands |
| 17475 | unsigned idx0 = 1; |
| 17476 | unsigned idx1 = 1; // a |
| 17477 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // b |
| 17478 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp |
| 17479 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // atmp |
| 17480 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // btmp |
| 17481 | st->print_raw("vector_minmaxFP "); |
| 17482 | opnd_array(0)->int_format(ra, this, st); // dst |
| 17483 | st->print_raw(","); |
| 17484 | opnd_array(1)->ext_format(ra, this,idx1, st); // a |
| 17485 | st->print_raw(","); |
| 17486 | opnd_array(2)->ext_format(ra, this,idx2, st); // b |
| 17487 | st->print_raw("\t!using "); |
| 17488 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp |
| 17489 | st->print_raw(", "); |
| 17490 | opnd_array(4)->ext_format(ra, this,idx4, st); // atmp |
| 17491 | st->print_raw(", "); |
| 17492 | opnd_array(5)->ext_format(ra, this,idx5, st); // btmp |
| 17493 | st->print_raw(" as TEMP"); |
| 17494 | } |
| 17495 | #endif |
| 17496 | #ifndef PRODUCT |
| 17497 | void evminmaxFP_reg_eavxNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 17498 | // Start at oper_input_base() and count operands |
| 17499 | unsigned idx0 = 1; |
| 17500 | unsigned idx1 = 1; // a |
| 17501 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // b |
| 17502 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 17503 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // atmp |
| 17504 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // btmp |
| 17505 | unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // ktmp |
| 17506 | st->print_raw("vector_minmaxFP "); |
| 17507 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 17508 | st->print_raw(","); |
| 17509 | opnd_array(1)->ext_format(ra, this,idx1, st); // a |
| 17510 | st->print_raw(","); |
| 17511 | opnd_array(2)->ext_format(ra, this,idx2, st); // b |
| 17512 | st->print_raw("\t!using "); |
| 17513 | opnd_array(4)->ext_format(ra, this,idx4, st); // atmp |
| 17514 | st->print_raw(", "); |
| 17515 | opnd_array(5)->ext_format(ra, this,idx5, st); // btmp |
| 17516 | st->print_raw(" as TEMP"); |
| 17517 | } |
| 17518 | #endif |
| 17519 | #ifndef PRODUCT |
| 17520 | void evminmaxFP_reg_eavx_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 17521 | // Start at oper_input_base() and count operands |
| 17522 | unsigned idx0 = 1; |
| 17523 | unsigned idx1 = 1; // a |
| 17524 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // b |
| 17525 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 17526 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // atmp |
| 17527 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // btmp |
| 17528 | unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // ktmp |
| 17529 | st->print_raw("vector_minmaxFP "); |
| 17530 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 17531 | st->print_raw(","); |
| 17532 | opnd_array(1)->ext_format(ra, this,idx1, st); // a |
| 17533 | st->print_raw(","); |
| 17534 | opnd_array(2)->ext_format(ra, this,idx2, st); // b |
| 17535 | st->print_raw("\t!using "); |
| 17536 | opnd_array(4)->ext_format(ra, this,idx4, st); // atmp |
| 17537 | st->print_raw(", "); |
| 17538 | opnd_array(5)->ext_format(ra, this,idx5, st); // btmp |
| 17539 | st->print_raw(" as TEMP"); |
| 17540 | } |
| 17541 | #endif |
| 17542 | #ifndef PRODUCT |
| 17543 | void signumF_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 17544 | // Start at oper_input_base() and count operands |
| 17545 | unsigned idx0 = 1; |
| 17546 | unsigned idx1 = 1; // dst |
| 17547 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero |
| 17548 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // one |
| 17549 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // scratch |
| 17550 | st->print_raw("signumF "); |
| 17551 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 17552 | st->print_raw(", "); |
| 17553 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 17554 | st->print_raw("\t! using "); |
| 17555 | opnd_array(4)->ext_format(ra, this,idx4, st); // scratch |
| 17556 | st->print_raw(" as TEMP"); |
| 17557 | } |
| 17558 | #endif |
| 17559 | #ifndef PRODUCT |
| 17560 | void signumD_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 17561 | // Start at oper_input_base() and count operands |
| 17562 | unsigned idx0 = 1; |
| 17563 | unsigned idx1 = 1; // dst |
| 17564 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero |
| 17565 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // one |
| 17566 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // scratch |
| 17567 | st->print_raw("signumD "); |
| 17568 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 17569 | st->print_raw(", "); |
| 17570 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 17571 | st->print_raw("\t! using "); |
| 17572 | opnd_array(4)->ext_format(ra, this,idx4, st); // scratch |
| 17573 | st->print_raw(" as TEMP"); |
| 17574 | } |
| 17575 | #endif |
| 17576 | #ifndef PRODUCT |
| 17577 | void copySignF_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 17578 | // Start at oper_input_base() and count operands |
| 17579 | unsigned idx0 = 1; |
| 17580 | unsigned idx1 = 1; // dst |
| 17581 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 17582 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp1 |
| 17583 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2 |
| 17584 | st->print_raw("CopySignF "); |
| 17585 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 17586 | st->print_raw(", "); |
| 17587 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 17588 | st->print_raw("\t! using "); |
| 17589 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp1 |
| 17590 | st->print_raw(" and "); |
| 17591 | opnd_array(4)->ext_format(ra, this,idx4, st); // tmp2 |
| 17592 | st->print_raw(" as TEMP"); |
| 17593 | } |
| 17594 | #endif |
| 17595 | #ifndef PRODUCT |
| 17596 | void copySignD_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 17597 | // Start at oper_input_base() and count operands |
| 17598 | unsigned idx0 = 1; |
| 17599 | unsigned idx1 = 1; // dst |
| 17600 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 17601 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // zero |
| 17602 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1 |
| 17603 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2 |
| 17604 | st->print_raw("CopySignD "); |
| 17605 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 17606 | st->print_raw(", "); |
| 17607 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 17608 | st->print_raw("\t! using "); |
| 17609 | opnd_array(4)->ext_format(ra, this,idx4, st); // tmp1 |
| 17610 | st->print_raw(" and "); |
| 17611 | opnd_array(5)->ext_format(ra, this,idx5, st); // tmp2 |
| 17612 | st->print_raw(" as TEMP"); |
| 17613 | } |
| 17614 | #endif |
| 17615 | #ifndef PRODUCT |
| 17616 | void vsqrtF_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 17617 | // Start at oper_input_base() and count operands |
| 17618 | unsigned idx0 = 1; |
| 17619 | unsigned idx1 = 1; // src |
| 17620 | st->print_raw("vsqrtps "); |
| 17621 | opnd_array(0)->int_format(ra, this, st); // dst |
| 17622 | st->print_raw(","); |
| 17623 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 17624 | st->print_raw("\t! sqrt packedF"); |
| 17625 | } |
| 17626 | #endif |
| 17627 | #ifndef PRODUCT |
| 17628 | void vsqrtF_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 17629 | // Start at oper_input_base() and count operands |
| 17630 | unsigned idx0 = 2; |
| 17631 | unsigned idx1 = 2; // mem |
| 17632 | st->print_raw("vsqrtps "); |
| 17633 | opnd_array(0)->int_format(ra, this, st); // dst |
| 17634 | st->print_raw(","); |
| 17635 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 17636 | st->print_raw("\t! sqrt packedF"); |
| 17637 | } |
| 17638 | #endif |
| 17639 | #ifndef PRODUCT |
| 17640 | void vsqrtD_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 17641 | // Start at oper_input_base() and count operands |
| 17642 | unsigned idx0 = 1; |
| 17643 | unsigned idx1 = 1; // src |
| 17644 | st->print_raw("vsqrtpd "); |
| 17645 | opnd_array(0)->int_format(ra, this, st); // dst |
| 17646 | st->print_raw(","); |
| 17647 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 17648 | st->print_raw("\t! sqrt packedD"); |
| 17649 | } |
| 17650 | #endif |
| 17651 | #ifndef PRODUCT |
| 17652 | void vsqrtD_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 17653 | // Start at oper_input_base() and count operands |
| 17654 | unsigned idx0 = 2; |
| 17655 | unsigned idx1 = 2; // mem |
| 17656 | st->print_raw("vsqrtpd "); |
| 17657 | opnd_array(0)->int_format(ra, this, st); // dst |
| 17658 | st->print_raw(","); |
| 17659 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 17660 | st->print_raw("\t! sqrt packedD"); |
| 17661 | } |
| 17662 | #endif |
| 17663 | #ifndef PRODUCT |
| 17664 | void vshiftcntNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 17665 | // Start at oper_input_base() and count operands |
| 17666 | unsigned idx0 = 1; |
| 17667 | unsigned idx1 = 1; // cnt |
| 17668 | st->print_raw("movdl "); |
| 17669 | opnd_array(0)->int_format(ra, this, st); // dst |
| 17670 | st->print_raw(","); |
| 17671 | opnd_array(1)->ext_format(ra, this,idx1, st); // cnt |
| 17672 | st->print_raw("\t! load shift count"); |
| 17673 | } |
| 17674 | #endif |
| 17675 | #ifndef PRODUCT |
| 17676 | void vshiftcnt_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 17677 | // Start at oper_input_base() and count operands |
| 17678 | unsigned idx0 = 1; |
| 17679 | unsigned idx1 = 1; // cnt |
| 17680 | st->print_raw("movdl "); |
| 17681 | opnd_array(0)->int_format(ra, this, st); // dst |
| 17682 | st->print_raw(","); |
| 17683 | opnd_array(1)->ext_format(ra, this,idx1, st); // cnt |
| 17684 | st->print_raw("\t! load shift count"); |
| 17685 | } |
| 17686 | #endif |
| 17687 | #ifndef PRODUCT |
| 17688 | void vshiftBNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 17689 | // Start at oper_input_base() and count operands |
| 17690 | unsigned idx0 = 1; |
| 17691 | unsigned idx1 = 1; // src |
| 17692 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 17693 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 17694 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp |
| 17695 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch |
| 17696 | st->print_raw("vector_byte_shift "); |
| 17697 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 17698 | st->print_raw(","); |
| 17699 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 17700 | st->print_raw(","); |
| 17701 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 17702 | } |
| 17703 | #endif |
| 17704 | #ifndef PRODUCT |
| 17705 | void vshiftB_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 17706 | // Start at oper_input_base() and count operands |
| 17707 | unsigned idx0 = 1; |
| 17708 | unsigned idx1 = 1; // src |
| 17709 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 17710 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 17711 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp |
| 17712 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch |
| 17713 | st->print_raw("vector_byte_shift "); |
| 17714 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 17715 | st->print_raw(","); |
| 17716 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 17717 | st->print_raw(","); |
| 17718 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 17719 | } |
| 17720 | #endif |
| 17721 | #ifndef PRODUCT |
| 17722 | void vshiftB_1Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 17723 | // Start at oper_input_base() and count operands |
| 17724 | unsigned idx0 = 1; |
| 17725 | unsigned idx1 = 1; // src |
| 17726 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 17727 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 17728 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp |
| 17729 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch |
| 17730 | st->print_raw("vector_byte_shift "); |
| 17731 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 17732 | st->print_raw(","); |
| 17733 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 17734 | st->print_raw(","); |
| 17735 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 17736 | } |
| 17737 | #endif |
| 17738 | #ifndef PRODUCT |
| 17739 | void vshift16BNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 17740 | // Start at oper_input_base() and count operands |
| 17741 | unsigned idx0 = 1; |
| 17742 | unsigned idx1 = 1; // src |
| 17743 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 17744 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 17745 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1 |
| 17746 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2 |
| 17747 | unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // scratch |
| 17748 | st->print_raw("vector_byte_shift "); |
| 17749 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 17750 | st->print_raw(","); |
| 17751 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 17752 | st->print_raw(","); |
| 17753 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 17754 | } |
| 17755 | #endif |
| 17756 | #ifndef PRODUCT |
| 17757 | void vshift16B_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 17758 | // Start at oper_input_base() and count operands |
| 17759 | unsigned idx0 = 1; |
| 17760 | unsigned idx1 = 1; // src |
| 17761 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 17762 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 17763 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1 |
| 17764 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2 |
| 17765 | unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // scratch |
| 17766 | st->print_raw("vector_byte_shift "); |
| 17767 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 17768 | st->print_raw(","); |
| 17769 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 17770 | st->print_raw(","); |
| 17771 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 17772 | } |
| 17773 | #endif |
| 17774 | #ifndef PRODUCT |
| 17775 | void vshift16B_1Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 17776 | // Start at oper_input_base() and count operands |
| 17777 | unsigned idx0 = 1; |
| 17778 | unsigned idx1 = 1; // src |
| 17779 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 17780 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 17781 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1 |
| 17782 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2 |
| 17783 | unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // scratch |
| 17784 | st->print_raw("vector_byte_shift "); |
| 17785 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 17786 | st->print_raw(","); |
| 17787 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 17788 | st->print_raw(","); |
| 17789 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 17790 | } |
| 17791 | #endif |
| 17792 | #ifndef PRODUCT |
| 17793 | void vshift16B_avxNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 17794 | // Start at oper_input_base() and count operands |
| 17795 | unsigned idx0 = 1; |
| 17796 | unsigned idx1 = 1; // src |
| 17797 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 17798 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 17799 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp |
| 17800 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch |
| 17801 | st->print_raw("vector_byte_shift "); |
| 17802 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 17803 | st->print_raw(","); |
| 17804 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 17805 | st->print_raw(","); |
| 17806 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 17807 | } |
| 17808 | #endif |
| 17809 | #ifndef PRODUCT |
| 17810 | void vshift16B_avx_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 17811 | // Start at oper_input_base() and count operands |
| 17812 | unsigned idx0 = 1; |
| 17813 | unsigned idx1 = 1; // src |
| 17814 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 17815 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 17816 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp |
| 17817 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch |
| 17818 | st->print_raw("vector_byte_shift "); |
| 17819 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 17820 | st->print_raw(","); |
| 17821 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 17822 | st->print_raw(","); |
| 17823 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 17824 | } |
| 17825 | #endif |
| 17826 | #ifndef PRODUCT |
| 17827 | void vshift16B_avx_1Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 17828 | // Start at oper_input_base() and count operands |
| 17829 | unsigned idx0 = 1; |
| 17830 | unsigned idx1 = 1; // src |
| 17831 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 17832 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 17833 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp |
| 17834 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch |
| 17835 | st->print_raw("vector_byte_shift "); |
| 17836 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 17837 | st->print_raw(","); |
| 17838 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 17839 | st->print_raw(","); |
| 17840 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 17841 | } |
| 17842 | #endif |
| 17843 | #ifndef PRODUCT |
| 17844 | void vshift32B_avxNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 17845 | // Start at oper_input_base() and count operands |
| 17846 | unsigned idx0 = 1; |
| 17847 | unsigned idx1 = 1; // src |
| 17848 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 17849 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 17850 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp |
| 17851 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch |
| 17852 | st->print_raw("vector_byte_shift "); |
| 17853 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 17854 | st->print_raw(","); |
| 17855 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 17856 | st->print_raw(","); |
| 17857 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 17858 | } |
| 17859 | #endif |
| 17860 | #ifndef PRODUCT |
| 17861 | void vshift32B_avx_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 17862 | // Start at oper_input_base() and count operands |
| 17863 | unsigned idx0 = 1; |
| 17864 | unsigned idx1 = 1; // src |
| 17865 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 17866 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 17867 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp |
| 17868 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch |
| 17869 | st->print_raw("vector_byte_shift "); |
| 17870 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 17871 | st->print_raw(","); |
| 17872 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 17873 | st->print_raw(","); |
| 17874 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 17875 | } |
| 17876 | #endif |
| 17877 | #ifndef PRODUCT |
| 17878 | void vshift32B_avx_1Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 17879 | // Start at oper_input_base() and count operands |
| 17880 | unsigned idx0 = 1; |
| 17881 | unsigned idx1 = 1; // src |
| 17882 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 17883 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 17884 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp |
| 17885 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch |
| 17886 | st->print_raw("vector_byte_shift "); |
| 17887 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 17888 | st->print_raw(","); |
| 17889 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 17890 | st->print_raw(","); |
| 17891 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 17892 | } |
| 17893 | #endif |
| 17894 | #ifndef PRODUCT |
| 17895 | void vshift64B_avxNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 17896 | // Start at oper_input_base() and count operands |
| 17897 | unsigned idx0 = 1; |
| 17898 | unsigned idx1 = 1; // src |
| 17899 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 17900 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 17901 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1 |
| 17902 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2 |
| 17903 | unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // scratch |
| 17904 | st->print_raw("vector_byte_shift "); |
| 17905 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 17906 | st->print_raw(","); |
| 17907 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 17908 | st->print_raw(","); |
| 17909 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 17910 | } |
| 17911 | #endif |
| 17912 | #ifndef PRODUCT |
| 17913 | void vshift64B_avx_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 17914 | // Start at oper_input_base() and count operands |
| 17915 | unsigned idx0 = 1; |
| 17916 | unsigned idx1 = 1; // src |
| 17917 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 17918 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 17919 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1 |
| 17920 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2 |
| 17921 | unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // scratch |
| 17922 | st->print_raw("vector_byte_shift "); |
| 17923 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 17924 | st->print_raw(","); |
| 17925 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 17926 | st->print_raw(","); |
| 17927 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 17928 | } |
| 17929 | #endif |
| 17930 | #ifndef PRODUCT |
| 17931 | void vshift64B_avx_1Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 17932 | // Start at oper_input_base() and count operands |
| 17933 | unsigned idx0 = 1; |
| 17934 | unsigned idx1 = 1; // src |
| 17935 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 17936 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 17937 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1 |
| 17938 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2 |
| 17939 | unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // scratch |
| 17940 | st->print_raw("vector_byte_shift "); |
| 17941 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 17942 | st->print_raw(","); |
| 17943 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 17944 | st->print_raw(","); |
| 17945 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 17946 | } |
| 17947 | #endif |
| 17948 | #ifndef PRODUCT |
| 17949 | void vshiftSNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 17950 | // Start at oper_input_base() and count operands |
| 17951 | unsigned idx0 = 1; |
| 17952 | unsigned idx1 = 1; // src |
| 17953 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 17954 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 17955 | st->print_raw("vshiftw "); |
| 17956 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 17957 | st->print_raw(","); |
| 17958 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 17959 | st->print_raw(","); |
| 17960 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 17961 | st->print_raw("\t! shift packedS"); |
| 17962 | } |
| 17963 | #endif |
| 17964 | #ifndef PRODUCT |
| 17965 | void vshiftS_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 17966 | // Start at oper_input_base() and count operands |
| 17967 | unsigned idx0 = 1; |
| 17968 | unsigned idx1 = 1; // src |
| 17969 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 17970 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 17971 | st->print_raw("vshiftw "); |
| 17972 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 17973 | st->print_raw(","); |
| 17974 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 17975 | st->print_raw(","); |
| 17976 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 17977 | st->print_raw("\t! shift packedS"); |
| 17978 | } |
| 17979 | #endif |
| 17980 | #ifndef PRODUCT |
| 17981 | void vshiftS_1Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 17982 | // Start at oper_input_base() and count operands |
| 17983 | unsigned idx0 = 1; |
| 17984 | unsigned idx1 = 1; // src |
| 17985 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 17986 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 17987 | st->print_raw("vshiftw "); |
| 17988 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 17989 | st->print_raw(","); |
| 17990 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 17991 | st->print_raw(","); |
| 17992 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 17993 | st->print_raw("\t! shift packedS"); |
| 17994 | } |
| 17995 | #endif |
| 17996 | #ifndef PRODUCT |
| 17997 | void vshiftINode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 17998 | // Start at oper_input_base() and count operands |
| 17999 | unsigned idx0 = 1; |
| 18000 | unsigned idx1 = 1; // src |
| 18001 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 18002 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 18003 | st->print_raw("vshiftd "); |
| 18004 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 18005 | st->print_raw(","); |
| 18006 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 18007 | st->print_raw(","); |
| 18008 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 18009 | st->print_raw("\t! shift packedI"); |
| 18010 | } |
| 18011 | #endif |
| 18012 | #ifndef PRODUCT |
| 18013 | void vshiftI_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 18014 | // Start at oper_input_base() and count operands |
| 18015 | unsigned idx0 = 1; |
| 18016 | unsigned idx1 = 1; // src |
| 18017 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 18018 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 18019 | st->print_raw("vshiftd "); |
| 18020 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 18021 | st->print_raw(","); |
| 18022 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 18023 | st->print_raw(","); |
| 18024 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 18025 | st->print_raw("\t! shift packedI"); |
| 18026 | } |
| 18027 | #endif |
| 18028 | #ifndef PRODUCT |
| 18029 | void vshiftI_1Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 18030 | // Start at oper_input_base() and count operands |
| 18031 | unsigned idx0 = 1; |
| 18032 | unsigned idx1 = 1; // src |
| 18033 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 18034 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 18035 | st->print_raw("vshiftd "); |
| 18036 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 18037 | st->print_raw(","); |
| 18038 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 18039 | st->print_raw(","); |
| 18040 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 18041 | st->print_raw("\t! shift packedI"); |
| 18042 | } |
| 18043 | #endif |
| 18044 | #ifndef PRODUCT |
| 18045 | void vshiftI_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 18046 | // Start at oper_input_base() and count operands |
| 18047 | unsigned idx0 = 1; |
| 18048 | unsigned idx1 = 1; // src |
| 18049 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 18050 | st->print_raw("vshiftd_imm "); |
| 18051 | opnd_array(0)->int_format(ra, this, st); // dst |
| 18052 | st->print_raw(","); |
| 18053 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 18054 | st->print_raw(","); |
| 18055 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 18056 | st->print_raw("\t! shift packedI"); |
| 18057 | } |
| 18058 | #endif |
| 18059 | #ifndef PRODUCT |
| 18060 | void vshiftI_imm_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 18061 | // Start at oper_input_base() and count operands |
| 18062 | unsigned idx0 = 1; |
| 18063 | unsigned idx1 = 1; // src |
| 18064 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 18065 | st->print_raw("vshiftd_imm "); |
| 18066 | opnd_array(0)->int_format(ra, this, st); // dst |
| 18067 | st->print_raw(","); |
| 18068 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 18069 | st->print_raw(","); |
| 18070 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 18071 | st->print_raw("\t! shift packedI"); |
| 18072 | } |
| 18073 | #endif |
| 18074 | #ifndef PRODUCT |
| 18075 | void vshiftI_imm_1Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 18076 | // Start at oper_input_base() and count operands |
| 18077 | unsigned idx0 = 1; |
| 18078 | unsigned idx1 = 1; // src |
| 18079 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 18080 | st->print_raw("vshiftd_imm "); |
| 18081 | opnd_array(0)->int_format(ra, this, st); // dst |
| 18082 | st->print_raw(","); |
| 18083 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 18084 | st->print_raw(","); |
| 18085 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 18086 | st->print_raw("\t! shift packedI"); |
| 18087 | } |
| 18088 | #endif |
| 18089 | #ifndef PRODUCT |
| 18090 | void vshiftLNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 18091 | // Start at oper_input_base() and count operands |
| 18092 | unsigned idx0 = 1; |
| 18093 | unsigned idx1 = 1; // src |
| 18094 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 18095 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 18096 | st->print_raw("vshiftq "); |
| 18097 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 18098 | st->print_raw(","); |
| 18099 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 18100 | st->print_raw(","); |
| 18101 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 18102 | st->print_raw("\t! shift packedL"); |
| 18103 | } |
| 18104 | #endif |
| 18105 | #ifndef PRODUCT |
| 18106 | void vshiftL_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 18107 | // Start at oper_input_base() and count operands |
| 18108 | unsigned idx0 = 1; |
| 18109 | unsigned idx1 = 1; // src |
| 18110 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 18111 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 18112 | st->print_raw("vshiftq "); |
| 18113 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 18114 | st->print_raw(","); |
| 18115 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 18116 | st->print_raw(","); |
| 18117 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 18118 | st->print_raw("\t! shift packedL"); |
| 18119 | } |
| 18120 | #endif |
| 18121 | #ifndef PRODUCT |
| 18122 | void vshiftL_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 18123 | // Start at oper_input_base() and count operands |
| 18124 | unsigned idx0 = 1; |
| 18125 | unsigned idx1 = 1; // src |
| 18126 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 18127 | st->print_raw("vshiftq_imm "); |
| 18128 | opnd_array(0)->int_format(ra, this, st); // dst |
| 18129 | st->print_raw(","); |
| 18130 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 18131 | st->print_raw(","); |
| 18132 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 18133 | st->print_raw("\t! shift packedL"); |
| 18134 | } |
| 18135 | #endif |
| 18136 | #ifndef PRODUCT |
| 18137 | void vshiftL_imm_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 18138 | // Start at oper_input_base() and count operands |
| 18139 | unsigned idx0 = 1; |
| 18140 | unsigned idx1 = 1; // src |
| 18141 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 18142 | st->print_raw("vshiftq_imm "); |
| 18143 | opnd_array(0)->int_format(ra, this, st); // dst |
| 18144 | st->print_raw(","); |
| 18145 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 18146 | st->print_raw(","); |
| 18147 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 18148 | st->print_raw("\t! shift packedL"); |
| 18149 | } |
| 18150 | #endif |
| 18151 | #ifndef PRODUCT |
| 18152 | void vshiftL_arith_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 18153 | // Start at oper_input_base() and count operands |
| 18154 | unsigned idx0 = 1; |
| 18155 | unsigned idx1 = 1; // src |
| 18156 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 18157 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 18158 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp |
| 18159 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch |
| 18160 | st->print_raw("vshiftq "); |
| 18161 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 18162 | st->print_raw(","); |
| 18163 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 18164 | st->print_raw(","); |
| 18165 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 18166 | } |
| 18167 | #endif |
| 18168 | #ifndef PRODUCT |
| 18169 | void vshiftL_arith_reg_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 18170 | // Start at oper_input_base() and count operands |
| 18171 | unsigned idx0 = 1; |
| 18172 | unsigned idx1 = 1; // src |
| 18173 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 18174 | st->print_raw("vshiftq "); |
| 18175 | opnd_array(0)->int_format(ra, this, st); // dst |
| 18176 | st->print_raw(","); |
| 18177 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 18178 | st->print_raw(","); |
| 18179 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 18180 | } |
| 18181 | #endif |
| 18182 | #ifndef PRODUCT |
| 18183 | void vshift8B_var_nobwNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 18184 | // Start at oper_input_base() and count operands |
| 18185 | unsigned idx0 = 1; |
| 18186 | unsigned idx1 = 1; // src |
| 18187 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 18188 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 18189 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp |
| 18190 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch |
| 18191 | st->print_raw("vector_varshift_byte "); |
| 18192 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 18193 | st->print_raw(", "); |
| 18194 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 18195 | st->print_raw(", "); |
| 18196 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 18197 | st->print_raw("\n\t! using "); |
| 18198 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp |
| 18199 | st->print_raw(", "); |
| 18200 | opnd_array(5)->ext_format(ra, this,idx5, st); // scratch |
| 18201 | st->print_raw(" as TEMP"); |
| 18202 | } |
| 18203 | #endif |
| 18204 | #ifndef PRODUCT |
| 18205 | void vshift8B_var_nobw_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 18206 | // Start at oper_input_base() and count operands |
| 18207 | unsigned idx0 = 1; |
| 18208 | unsigned idx1 = 1; // src |
| 18209 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 18210 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 18211 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp |
| 18212 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch |
| 18213 | st->print_raw("vector_varshift_byte "); |
| 18214 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 18215 | st->print_raw(", "); |
| 18216 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 18217 | st->print_raw(", "); |
| 18218 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 18219 | st->print_raw("\n\t! using "); |
| 18220 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp |
| 18221 | st->print_raw(", "); |
| 18222 | opnd_array(5)->ext_format(ra, this,idx5, st); // scratch |
| 18223 | st->print_raw(" as TEMP"); |
| 18224 | } |
| 18225 | #endif |
| 18226 | #ifndef PRODUCT |
| 18227 | void vshift8B_var_nobw_1Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 18228 | // Start at oper_input_base() and count operands |
| 18229 | unsigned idx0 = 1; |
| 18230 | unsigned idx1 = 1; // src |
| 18231 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 18232 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 18233 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp |
| 18234 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch |
| 18235 | st->print_raw("vector_varshift_byte "); |
| 18236 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 18237 | st->print_raw(", "); |
| 18238 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 18239 | st->print_raw(", "); |
| 18240 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 18241 | st->print_raw("\n\t! using "); |
| 18242 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp |
| 18243 | st->print_raw(", "); |
| 18244 | opnd_array(5)->ext_format(ra, this,idx5, st); // scratch |
| 18245 | st->print_raw(" as TEMP"); |
| 18246 | } |
| 18247 | #endif |
| 18248 | #ifndef PRODUCT |
| 18249 | void vshift16B_var_nobwNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 18250 | // Start at oper_input_base() and count operands |
| 18251 | unsigned idx0 = 1; |
| 18252 | unsigned idx1 = 1; // src |
| 18253 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 18254 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 18255 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp1 |
| 18256 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // vtmp2 |
| 18257 | unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // scratch |
| 18258 | st->print_raw("vector_varshift_byte "); |
| 18259 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 18260 | st->print_raw(", "); |
| 18261 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 18262 | st->print_raw(", "); |
| 18263 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 18264 | st->print_raw("\n\t! using "); |
| 18265 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp1 |
| 18266 | st->print_raw(", "); |
| 18267 | opnd_array(5)->ext_format(ra, this,idx5, st); // vtmp2 |
| 18268 | st->print_raw(" and "); |
| 18269 | opnd_array(6)->ext_format(ra, this,idx6, st); // scratch |
| 18270 | st->print_raw(" as TEMP"); |
| 18271 | } |
| 18272 | #endif |
| 18273 | #ifndef PRODUCT |
| 18274 | void vshift16B_var_nobw_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 18275 | // Start at oper_input_base() and count operands |
| 18276 | unsigned idx0 = 1; |
| 18277 | unsigned idx1 = 1; // src |
| 18278 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 18279 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 18280 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp1 |
| 18281 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // vtmp2 |
| 18282 | unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // scratch |
| 18283 | st->print_raw("vector_varshift_byte "); |
| 18284 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 18285 | st->print_raw(", "); |
| 18286 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 18287 | st->print_raw(", "); |
| 18288 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 18289 | st->print_raw("\n\t! using "); |
| 18290 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp1 |
| 18291 | st->print_raw(", "); |
| 18292 | opnd_array(5)->ext_format(ra, this,idx5, st); // vtmp2 |
| 18293 | st->print_raw(" and "); |
| 18294 | opnd_array(6)->ext_format(ra, this,idx6, st); // scratch |
| 18295 | st->print_raw(" as TEMP"); |
| 18296 | } |
| 18297 | #endif |
| 18298 | #ifndef PRODUCT |
| 18299 | void vshift16B_var_nobw_1Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 18300 | // Start at oper_input_base() and count operands |
| 18301 | unsigned idx0 = 1; |
| 18302 | unsigned idx1 = 1; // src |
| 18303 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 18304 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 18305 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp1 |
| 18306 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // vtmp2 |
| 18307 | unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // scratch |
| 18308 | st->print_raw("vector_varshift_byte "); |
| 18309 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 18310 | st->print_raw(", "); |
| 18311 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 18312 | st->print_raw(", "); |
| 18313 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 18314 | st->print_raw("\n\t! using "); |
| 18315 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp1 |
| 18316 | st->print_raw(", "); |
| 18317 | opnd_array(5)->ext_format(ra, this,idx5, st); // vtmp2 |
| 18318 | st->print_raw(" and "); |
| 18319 | opnd_array(6)->ext_format(ra, this,idx6, st); // scratch |
| 18320 | st->print_raw(" as TEMP"); |
| 18321 | } |
| 18322 | #endif |
| 18323 | #ifndef PRODUCT |
| 18324 | void vshift32B_var_nobwNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 18325 | // Start at oper_input_base() and count operands |
| 18326 | unsigned idx0 = 1; |
| 18327 | unsigned idx1 = 1; // src |
| 18328 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 18329 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 18330 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp1 |
| 18331 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // vtmp2 |
| 18332 | unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // vtmp3 |
| 18333 | unsigned idx7 = idx6 + opnd_array(6)->num_edges(); // vtmp4 |
| 18334 | unsigned idx8 = idx7 + opnd_array(7)->num_edges(); // scratch |
| 18335 | st->print_raw("vector_varshift_byte "); |
| 18336 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 18337 | st->print_raw(", "); |
| 18338 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 18339 | st->print_raw(", "); |
| 18340 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 18341 | st->print_raw("\n\t using "); |
| 18342 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp1 |
| 18343 | st->print_raw(", "); |
| 18344 | opnd_array(5)->ext_format(ra, this,idx5, st); // vtmp2 |
| 18345 | st->print_raw(", "); |
| 18346 | opnd_array(6)->ext_format(ra, this,idx6, st); // vtmp3 |
| 18347 | st->print_raw(", "); |
| 18348 | opnd_array(7)->ext_format(ra, this,idx7, st); // vtmp4 |
| 18349 | st->print_raw(" and "); |
| 18350 | opnd_array(8)->ext_format(ra, this,idx8, st); // scratch |
| 18351 | st->print_raw(" as TEMP"); |
| 18352 | } |
| 18353 | #endif |
| 18354 | #ifndef PRODUCT |
| 18355 | void vshift32B_var_nobw_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 18356 | // Start at oper_input_base() and count operands |
| 18357 | unsigned idx0 = 1; |
| 18358 | unsigned idx1 = 1; // src |
| 18359 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 18360 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 18361 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp1 |
| 18362 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // vtmp2 |
| 18363 | unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // vtmp3 |
| 18364 | unsigned idx7 = idx6 + opnd_array(6)->num_edges(); // vtmp4 |
| 18365 | unsigned idx8 = idx7 + opnd_array(7)->num_edges(); // scratch |
| 18366 | st->print_raw("vector_varshift_byte "); |
| 18367 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 18368 | st->print_raw(", "); |
| 18369 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 18370 | st->print_raw(", "); |
| 18371 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 18372 | st->print_raw("\n\t using "); |
| 18373 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp1 |
| 18374 | st->print_raw(", "); |
| 18375 | opnd_array(5)->ext_format(ra, this,idx5, st); // vtmp2 |
| 18376 | st->print_raw(", "); |
| 18377 | opnd_array(6)->ext_format(ra, this,idx6, st); // vtmp3 |
| 18378 | st->print_raw(", "); |
| 18379 | opnd_array(7)->ext_format(ra, this,idx7, st); // vtmp4 |
| 18380 | st->print_raw(" and "); |
| 18381 | opnd_array(8)->ext_format(ra, this,idx8, st); // scratch |
| 18382 | st->print_raw(" as TEMP"); |
| 18383 | } |
| 18384 | #endif |
| 18385 | #ifndef PRODUCT |
| 18386 | void vshift32B_var_nobw_1Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 18387 | // Start at oper_input_base() and count operands |
| 18388 | unsigned idx0 = 1; |
| 18389 | unsigned idx1 = 1; // src |
| 18390 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 18391 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 18392 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp1 |
| 18393 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // vtmp2 |
| 18394 | unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // vtmp3 |
| 18395 | unsigned idx7 = idx6 + opnd_array(6)->num_edges(); // vtmp4 |
| 18396 | unsigned idx8 = idx7 + opnd_array(7)->num_edges(); // scratch |
| 18397 | st->print_raw("vector_varshift_byte "); |
| 18398 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 18399 | st->print_raw(", "); |
| 18400 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 18401 | st->print_raw(", "); |
| 18402 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 18403 | st->print_raw("\n\t using "); |
| 18404 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp1 |
| 18405 | st->print_raw(", "); |
| 18406 | opnd_array(5)->ext_format(ra, this,idx5, st); // vtmp2 |
| 18407 | st->print_raw(", "); |
| 18408 | opnd_array(6)->ext_format(ra, this,idx6, st); // vtmp3 |
| 18409 | st->print_raw(", "); |
| 18410 | opnd_array(7)->ext_format(ra, this,idx7, st); // vtmp4 |
| 18411 | st->print_raw(" and "); |
| 18412 | opnd_array(8)->ext_format(ra, this,idx8, st); // scratch |
| 18413 | st->print_raw(" as TEMP"); |
| 18414 | } |
| 18415 | #endif |
| 18416 | #ifndef PRODUCT |
| 18417 | void vshiftB_var_evex_bwNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 18418 | // Start at oper_input_base() and count operands |
| 18419 | unsigned idx0 = 1; |
| 18420 | unsigned idx1 = 1; // src |
| 18421 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 18422 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 18423 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp |
| 18424 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch |
| 18425 | st->print_raw("vector_varshift_byte "); |
| 18426 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 18427 | st->print_raw(", "); |
| 18428 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 18429 | st->print_raw(", "); |
| 18430 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 18431 | st->print_raw("\n\t! using "); |
| 18432 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp |
| 18433 | st->print_raw(", "); |
| 18434 | opnd_array(5)->ext_format(ra, this,idx5, st); // scratch |
| 18435 | st->print_raw(" as TEMP"); |
| 18436 | } |
| 18437 | #endif |
| 18438 | #ifndef PRODUCT |
| 18439 | void vshiftB_var_evex_bw_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 18440 | // Start at oper_input_base() and count operands |
| 18441 | unsigned idx0 = 1; |
| 18442 | unsigned idx1 = 1; // src |
| 18443 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 18444 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 18445 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp |
| 18446 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch |
| 18447 | st->print_raw("vector_varshift_byte "); |
| 18448 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 18449 | st->print_raw(", "); |
| 18450 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 18451 | st->print_raw(", "); |
| 18452 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 18453 | st->print_raw("\n\t! using "); |
| 18454 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp |
| 18455 | st->print_raw(", "); |
| 18456 | opnd_array(5)->ext_format(ra, this,idx5, st); // scratch |
| 18457 | st->print_raw(" as TEMP"); |
| 18458 | } |
| 18459 | #endif |
| 18460 | #ifndef PRODUCT |
| 18461 | void vshiftB_var_evex_bw_1Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 18462 | // Start at oper_input_base() and count operands |
| 18463 | unsigned idx0 = 1; |
| 18464 | unsigned idx1 = 1; // src |
| 18465 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 18466 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 18467 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp |
| 18468 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch |
| 18469 | st->print_raw("vector_varshift_byte "); |
| 18470 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 18471 | st->print_raw(", "); |
| 18472 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 18473 | st->print_raw(", "); |
| 18474 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 18475 | st->print_raw("\n\t! using "); |
| 18476 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp |
| 18477 | st->print_raw(", "); |
| 18478 | opnd_array(5)->ext_format(ra, this,idx5, st); // scratch |
| 18479 | st->print_raw(" as TEMP"); |
| 18480 | } |
| 18481 | #endif |
| 18482 | #ifndef PRODUCT |
| 18483 | void vshift64B_var_evex_bwNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 18484 | // Start at oper_input_base() and count operands |
| 18485 | unsigned idx0 = 1; |
| 18486 | unsigned idx1 = 1; // src |
| 18487 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 18488 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 18489 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp1 |
| 18490 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // vtmp2 |
| 18491 | unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // scratch |
| 18492 | st->print_raw("vector_varshift_byte "); |
| 18493 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 18494 | st->print_raw(", "); |
| 18495 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 18496 | st->print_raw(", "); |
| 18497 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 18498 | st->print_raw("\n\t! using "); |
| 18499 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp1 |
| 18500 | st->print_raw(", "); |
| 18501 | opnd_array(5)->ext_format(ra, this,idx5, st); // vtmp2 |
| 18502 | st->print_raw(" and "); |
| 18503 | opnd_array(6)->ext_format(ra, this,idx6, st); // scratch |
| 18504 | st->print_raw(" as TEMP"); |
| 18505 | } |
| 18506 | #endif |
| 18507 | #ifndef PRODUCT |
| 18508 | void vshift64B_var_evex_bw_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 18509 | // Start at oper_input_base() and count operands |
| 18510 | unsigned idx0 = 1; |
| 18511 | unsigned idx1 = 1; // src |
| 18512 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 18513 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 18514 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp1 |
| 18515 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // vtmp2 |
| 18516 | unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // scratch |
| 18517 | st->print_raw("vector_varshift_byte "); |
| 18518 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 18519 | st->print_raw(", "); |
| 18520 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 18521 | st->print_raw(", "); |
| 18522 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 18523 | st->print_raw("\n\t! using "); |
| 18524 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp1 |
| 18525 | st->print_raw(", "); |
| 18526 | opnd_array(5)->ext_format(ra, this,idx5, st); // vtmp2 |
| 18527 | st->print_raw(" and "); |
| 18528 | opnd_array(6)->ext_format(ra, this,idx6, st); // scratch |
| 18529 | st->print_raw(" as TEMP"); |
| 18530 | } |
| 18531 | #endif |
| 18532 | #ifndef PRODUCT |
| 18533 | void vshift64B_var_evex_bw_1Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 18534 | // Start at oper_input_base() and count operands |
| 18535 | unsigned idx0 = 1; |
| 18536 | unsigned idx1 = 1; // src |
| 18537 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 18538 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 18539 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp1 |
| 18540 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // vtmp2 |
| 18541 | unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // scratch |
| 18542 | st->print_raw("vector_varshift_byte "); |
| 18543 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 18544 | st->print_raw(", "); |
| 18545 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 18546 | st->print_raw(", "); |
| 18547 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 18548 | st->print_raw("\n\t! using "); |
| 18549 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp1 |
| 18550 | st->print_raw(", "); |
| 18551 | opnd_array(5)->ext_format(ra, this,idx5, st); // vtmp2 |
| 18552 | st->print_raw(" and "); |
| 18553 | opnd_array(6)->ext_format(ra, this,idx6, st); // scratch |
| 18554 | st->print_raw(" as TEMP"); |
| 18555 | } |
| 18556 | #endif |
| 18557 | #ifndef PRODUCT |
| 18558 | void vshift8S_var_nobwNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 18559 | // Start at oper_input_base() and count operands |
| 18560 | unsigned idx0 = 1; |
| 18561 | unsigned idx1 = 1; // src |
| 18562 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 18563 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 18564 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp |
| 18565 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch |
| 18566 | st->print_raw("vector_var_shift_left_short "); |
| 18567 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 18568 | st->print_raw(", "); |
| 18569 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 18570 | st->print_raw(", "); |
| 18571 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 18572 | st->print_raw("\n\t"); |
| 18573 | } |
| 18574 | #endif |
| 18575 | #ifndef PRODUCT |
| 18576 | void vshift8S_var_nobw_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 18577 | // Start at oper_input_base() and count operands |
| 18578 | unsigned idx0 = 1; |
| 18579 | unsigned idx1 = 1; // src |
| 18580 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 18581 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 18582 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp |
| 18583 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch |
| 18584 | st->print_raw("vector_var_shift_left_short "); |
| 18585 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 18586 | st->print_raw(", "); |
| 18587 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 18588 | st->print_raw(", "); |
| 18589 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 18590 | st->print_raw("\n\t"); |
| 18591 | } |
| 18592 | #endif |
| 18593 | #ifndef PRODUCT |
| 18594 | void vshift8S_var_nobw_1Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 18595 | // Start at oper_input_base() and count operands |
| 18596 | unsigned idx0 = 1; |
| 18597 | unsigned idx1 = 1; // src |
| 18598 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 18599 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 18600 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp |
| 18601 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch |
| 18602 | st->print_raw("vector_var_shift_left_short "); |
| 18603 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 18604 | st->print_raw(", "); |
| 18605 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 18606 | st->print_raw(", "); |
| 18607 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 18608 | st->print_raw("\n\t"); |
| 18609 | } |
| 18610 | #endif |
| 18611 | #ifndef PRODUCT |
| 18612 | void vshift16S_var_nobwNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 18613 | // Start at oper_input_base() and count operands |
| 18614 | unsigned idx0 = 1; |
| 18615 | unsigned idx1 = 1; // src |
| 18616 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 18617 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 18618 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp1 |
| 18619 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // vtmp2 |
| 18620 | unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // scratch |
| 18621 | st->print_raw("vector_var_shift_left_short "); |
| 18622 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 18623 | st->print_raw(", "); |
| 18624 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 18625 | st->print_raw(", "); |
| 18626 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 18627 | st->print_raw("\n\t"); |
| 18628 | } |
| 18629 | #endif |
| 18630 | #ifndef PRODUCT |
| 18631 | void vshift16S_var_nobw_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 18632 | // Start at oper_input_base() and count operands |
| 18633 | unsigned idx0 = 1; |
| 18634 | unsigned idx1 = 1; // src |
| 18635 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 18636 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 18637 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp1 |
| 18638 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // vtmp2 |
| 18639 | unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // scratch |
| 18640 | st->print_raw("vector_var_shift_left_short "); |
| 18641 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 18642 | st->print_raw(", "); |
| 18643 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 18644 | st->print_raw(", "); |
| 18645 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 18646 | st->print_raw("\n\t"); |
| 18647 | } |
| 18648 | #endif |
| 18649 | #ifndef PRODUCT |
| 18650 | void vshift16S_var_nobw_1Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 18651 | // Start at oper_input_base() and count operands |
| 18652 | unsigned idx0 = 1; |
| 18653 | unsigned idx1 = 1; // src |
| 18654 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 18655 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 18656 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp1 |
| 18657 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // vtmp2 |
| 18658 | unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // scratch |
| 18659 | st->print_raw("vector_var_shift_left_short "); |
| 18660 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 18661 | st->print_raw(", "); |
| 18662 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 18663 | st->print_raw(", "); |
| 18664 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 18665 | st->print_raw("\n\t"); |
| 18666 | } |
| 18667 | #endif |
| 18668 | #ifndef PRODUCT |
| 18669 | void vshift16S_var_evex_bwNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 18670 | // Start at oper_input_base() and count operands |
| 18671 | unsigned idx0 = 1; |
| 18672 | unsigned idx1 = 1; // src |
| 18673 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 18674 | st->print_raw("vector_varshift_short "); |
| 18675 | opnd_array(0)->int_format(ra, this, st); // dst |
| 18676 | st->print_raw(","); |
| 18677 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 18678 | st->print_raw(","); |
| 18679 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 18680 | st->print_raw("\t!"); |
| 18681 | } |
| 18682 | #endif |
| 18683 | #ifndef PRODUCT |
| 18684 | void vshift16S_var_evex_bw_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 18685 | // Start at oper_input_base() and count operands |
| 18686 | unsigned idx0 = 1; |
| 18687 | unsigned idx1 = 1; // src |
| 18688 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 18689 | st->print_raw("vector_varshift_short "); |
| 18690 | opnd_array(0)->int_format(ra, this, st); // dst |
| 18691 | st->print_raw(","); |
| 18692 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 18693 | st->print_raw(","); |
| 18694 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 18695 | st->print_raw("\t!"); |
| 18696 | } |
| 18697 | #endif |
| 18698 | #ifndef PRODUCT |
| 18699 | void vshift16S_var_evex_bw_1Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 18700 | // Start at oper_input_base() and count operands |
| 18701 | unsigned idx0 = 1; |
| 18702 | unsigned idx1 = 1; // src |
| 18703 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 18704 | st->print_raw("vector_varshift_short "); |
| 18705 | opnd_array(0)->int_format(ra, this, st); // dst |
| 18706 | st->print_raw(","); |
| 18707 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 18708 | st->print_raw(","); |
| 18709 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 18710 | st->print_raw("\t!"); |
| 18711 | } |
| 18712 | #endif |
| 18713 | #ifndef PRODUCT |
| 18714 | void vshiftI_varNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 18715 | // Start at oper_input_base() and count operands |
| 18716 | unsigned idx0 = 1; |
| 18717 | unsigned idx1 = 1; // src |
| 18718 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 18719 | st->print_raw("vector_varshift_int "); |
| 18720 | opnd_array(0)->int_format(ra, this, st); // dst |
| 18721 | st->print_raw(","); |
| 18722 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 18723 | st->print_raw(","); |
| 18724 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 18725 | st->print_raw("\t!"); |
| 18726 | } |
| 18727 | #endif |
| 18728 | #ifndef PRODUCT |
| 18729 | void vshiftI_var_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 18730 | // Start at oper_input_base() and count operands |
| 18731 | unsigned idx0 = 1; |
| 18732 | unsigned idx1 = 1; // src |
| 18733 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 18734 | st->print_raw("vector_varshift_int "); |
| 18735 | opnd_array(0)->int_format(ra, this, st); // dst |
| 18736 | st->print_raw(","); |
| 18737 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 18738 | st->print_raw(","); |
| 18739 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 18740 | st->print_raw("\t!"); |
| 18741 | } |
| 18742 | #endif |
| 18743 | #ifndef PRODUCT |
| 18744 | void vshiftI_var_1Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 18745 | // Start at oper_input_base() and count operands |
| 18746 | unsigned idx0 = 1; |
| 18747 | unsigned idx1 = 1; // src |
| 18748 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 18749 | st->print_raw("vector_varshift_int "); |
| 18750 | opnd_array(0)->int_format(ra, this, st); // dst |
| 18751 | st->print_raw(","); |
| 18752 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 18753 | st->print_raw(","); |
| 18754 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 18755 | st->print_raw("\t!"); |
| 18756 | } |
| 18757 | #endif |
| 18758 | #ifndef PRODUCT |
| 18759 | void vshiftL_varNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 18760 | // Start at oper_input_base() and count operands |
| 18761 | unsigned idx0 = 1; |
| 18762 | unsigned idx1 = 1; // src |
| 18763 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 18764 | st->print_raw("vector_varshift_long "); |
| 18765 | opnd_array(0)->int_format(ra, this, st); // dst |
| 18766 | st->print_raw(","); |
| 18767 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 18768 | st->print_raw(","); |
| 18769 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 18770 | st->print_raw("\t!"); |
| 18771 | } |
| 18772 | #endif |
| 18773 | #ifndef PRODUCT |
| 18774 | void vshiftL_var_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 18775 | // Start at oper_input_base() and count operands |
| 18776 | unsigned idx0 = 1; |
| 18777 | unsigned idx1 = 1; // src |
| 18778 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 18779 | st->print_raw("vector_varshift_long "); |
| 18780 | opnd_array(0)->int_format(ra, this, st); // dst |
| 18781 | st->print_raw(","); |
| 18782 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 18783 | st->print_raw(","); |
| 18784 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 18785 | st->print_raw("\t!"); |
| 18786 | } |
| 18787 | #endif |
| 18788 | #ifndef PRODUCT |
| 18789 | void vshiftL_arith_varNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 18790 | // Start at oper_input_base() and count operands |
| 18791 | unsigned idx0 = 1; |
| 18792 | unsigned idx1 = 1; // src |
| 18793 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 18794 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 18795 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp |
| 18796 | st->print_raw("vector_varshift_long "); |
| 18797 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 18798 | st->print_raw(","); |
| 18799 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 18800 | st->print_raw(","); |
| 18801 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 18802 | st->print_raw("\n\t! using "); |
| 18803 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp |
| 18804 | st->print_raw(" as TEMP"); |
| 18805 | } |
| 18806 | #endif |
| 18807 | #ifndef PRODUCT |
| 18808 | void vshiftL_arith_var_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 18809 | // Start at oper_input_base() and count operands |
| 18810 | unsigned idx0 = 1; |
| 18811 | unsigned idx1 = 1; // src |
| 18812 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 18813 | st->print_raw("vector_varfshift_long "); |
| 18814 | opnd_array(0)->int_format(ra, this, st); // dst |
| 18815 | st->print_raw(","); |
| 18816 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 18817 | st->print_raw(","); |
| 18818 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 18819 | st->print_raw("\t!"); |
| 18820 | } |
| 18821 | #endif |
| 18822 | #ifndef PRODUCT |
| 18823 | void vandNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 18824 | // Start at oper_input_base() and count operands |
| 18825 | unsigned idx0 = 1; |
| 18826 | unsigned idx1 = 1; // dst |
| 18827 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 18828 | st->print_raw("pand "); |
| 18829 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 18830 | st->print_raw(","); |
| 18831 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 18832 | st->print_raw("\t! and vectors"); |
| 18833 | } |
| 18834 | #endif |
| 18835 | #ifndef PRODUCT |
| 18836 | void vand_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 18837 | // Start at oper_input_base() and count operands |
| 18838 | unsigned idx0 = 1; |
| 18839 | unsigned idx1 = 1; // src1 |
| 18840 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 18841 | st->print_raw("vpand "); |
| 18842 | opnd_array(0)->int_format(ra, this, st); // dst |
| 18843 | st->print_raw(","); |
| 18844 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 18845 | st->print_raw(","); |
| 18846 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 18847 | st->print_raw("\t! and vectors"); |
| 18848 | } |
| 18849 | #endif |
| 18850 | #ifndef PRODUCT |
| 18851 | void vand_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 18852 | // Start at oper_input_base() and count operands |
| 18853 | unsigned idx0 = 2; |
| 18854 | unsigned idx1 = 2; // src |
| 18855 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem |
| 18856 | st->print_raw("vpand "); |
| 18857 | opnd_array(0)->int_format(ra, this, st); // dst |
| 18858 | st->print_raw(","); |
| 18859 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 18860 | st->print_raw(","); |
| 18861 | opnd_array(2)->ext_format(ra, this,idx2, st); // mem |
| 18862 | st->print_raw("\t! and vectors"); |
| 18863 | } |
| 18864 | #endif |
| 18865 | #ifndef PRODUCT |
| 18866 | void vand_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 18867 | // Start at oper_input_base() and count operands |
| 18868 | unsigned idx0 = 2; |
| 18869 | unsigned idx1 = 2; // mem |
| 18870 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 18871 | st->print_raw("vpand "); |
| 18872 | opnd_array(0)->int_format(ra, this, st); // dst |
| 18873 | st->print_raw(","); |
| 18874 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 18875 | st->print_raw(","); |
| 18876 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 18877 | st->print_raw("\t! and vectors"); |
| 18878 | } |
| 18879 | #endif |
| 18880 | #ifndef PRODUCT |
| 18881 | void vorNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 18882 | // Start at oper_input_base() and count operands |
| 18883 | unsigned idx0 = 1; |
| 18884 | unsigned idx1 = 1; // dst |
| 18885 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 18886 | st->print_raw("por "); |
| 18887 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 18888 | st->print_raw(","); |
| 18889 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 18890 | st->print_raw("\t! or vectors"); |
| 18891 | } |
| 18892 | #endif |
| 18893 | #ifndef PRODUCT |
| 18894 | void vor_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 18895 | // Start at oper_input_base() and count operands |
| 18896 | unsigned idx0 = 1; |
| 18897 | unsigned idx1 = 1; // src1 |
| 18898 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 18899 | st->print_raw("vpor "); |
| 18900 | opnd_array(0)->int_format(ra, this, st); // dst |
| 18901 | st->print_raw(","); |
| 18902 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 18903 | st->print_raw(","); |
| 18904 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 18905 | st->print_raw("\t! or vectors"); |
| 18906 | } |
| 18907 | #endif |
| 18908 | #ifndef PRODUCT |
| 18909 | void vor_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 18910 | // Start at oper_input_base() and count operands |
| 18911 | unsigned idx0 = 2; |
| 18912 | unsigned idx1 = 2; // src |
| 18913 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem |
| 18914 | st->print_raw("vpor "); |
| 18915 | opnd_array(0)->int_format(ra, this, st); // dst |
| 18916 | st->print_raw(","); |
| 18917 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 18918 | st->print_raw(","); |
| 18919 | opnd_array(2)->ext_format(ra, this,idx2, st); // mem |
| 18920 | st->print_raw("\t! or vectors"); |
| 18921 | } |
| 18922 | #endif |
| 18923 | #ifndef PRODUCT |
| 18924 | void vor_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 18925 | // Start at oper_input_base() and count operands |
| 18926 | unsigned idx0 = 2; |
| 18927 | unsigned idx1 = 2; // mem |
| 18928 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 18929 | st->print_raw("vpor "); |
| 18930 | opnd_array(0)->int_format(ra, this, st); // dst |
| 18931 | st->print_raw(","); |
| 18932 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 18933 | st->print_raw(","); |
| 18934 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 18935 | st->print_raw("\t! or vectors"); |
| 18936 | } |
| 18937 | #endif |
| 18938 | #ifndef PRODUCT |
| 18939 | void vxorNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 18940 | // Start at oper_input_base() and count operands |
| 18941 | unsigned idx0 = 1; |
| 18942 | unsigned idx1 = 1; // dst |
| 18943 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 18944 | st->print_raw("pxor "); |
| 18945 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 18946 | st->print_raw(","); |
| 18947 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 18948 | st->print_raw("\t! xor vectors"); |
| 18949 | } |
| 18950 | #endif |
| 18951 | #ifndef PRODUCT |
| 18952 | void vxor_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 18953 | // Start at oper_input_base() and count operands |
| 18954 | unsigned idx0 = 1; |
| 18955 | unsigned idx1 = 1; // src1 |
| 18956 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 18957 | st->print_raw("vpxor "); |
| 18958 | opnd_array(0)->int_format(ra, this, st); // dst |
| 18959 | st->print_raw(","); |
| 18960 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 18961 | st->print_raw(","); |
| 18962 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 18963 | st->print_raw("\t! xor vectors"); |
| 18964 | } |
| 18965 | #endif |
| 18966 | #ifndef PRODUCT |
| 18967 | void vxor_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 18968 | // Start at oper_input_base() and count operands |
| 18969 | unsigned idx0 = 2; |
| 18970 | unsigned idx1 = 2; // src |
| 18971 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem |
| 18972 | st->print_raw("vpxor "); |
| 18973 | opnd_array(0)->int_format(ra, this, st); // dst |
| 18974 | st->print_raw(","); |
| 18975 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 18976 | st->print_raw(","); |
| 18977 | opnd_array(2)->ext_format(ra, this,idx2, st); // mem |
| 18978 | st->print_raw("\t! xor vectors"); |
| 18979 | } |
| 18980 | #endif |
| 18981 | #ifndef PRODUCT |
| 18982 | void vxor_mem_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 18983 | // Start at oper_input_base() and count operands |
| 18984 | unsigned idx0 = 2; |
| 18985 | unsigned idx1 = 2; // mem |
| 18986 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 18987 | st->print_raw("vpxor "); |
| 18988 | opnd_array(0)->int_format(ra, this, st); // dst |
| 18989 | st->print_raw(","); |
| 18990 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 18991 | st->print_raw(","); |
| 18992 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 18993 | st->print_raw("\t! xor vectors"); |
| 18994 | } |
| 18995 | #endif |
| 18996 | #ifndef PRODUCT |
| 18997 | void vcastBtoXNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 18998 | // Start at oper_input_base() and count operands |
| 18999 | unsigned idx0 = 1; |
| 19000 | unsigned idx1 = 1; // src |
| 19001 | st->print_raw("vector_cast_b2x "); |
| 19002 | opnd_array(0)->int_format(ra, this, st); // dst |
| 19003 | st->print_raw(","); |
| 19004 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 19005 | st->print_raw("\t!"); |
| 19006 | } |
| 19007 | #endif |
| 19008 | #ifndef PRODUCT |
| 19009 | void castStoXNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 19010 | // Start at oper_input_base() and count operands |
| 19011 | unsigned idx0 = 1; |
| 19012 | unsigned idx1 = 1; // src |
| 19013 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // scratch |
| 19014 | st->print_raw("vector_cast_s2x "); |
| 19015 | opnd_array(0)->int_format(ra, this, st); // dst |
| 19016 | st->print_raw(","); |
| 19017 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 19018 | st->print_raw("\t! using "); |
| 19019 | opnd_array(2)->ext_format(ra, this,idx2, st); // scratch |
| 19020 | st->print_raw(" as TEMP"); |
| 19021 | } |
| 19022 | #endif |
| 19023 | #ifndef PRODUCT |
| 19024 | void vcastStoXNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 19025 | // Start at oper_input_base() and count operands |
| 19026 | unsigned idx0 = 1; |
| 19027 | unsigned idx1 = 1; // src |
| 19028 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst |
| 19029 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp |
| 19030 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // scratch |
| 19031 | st->print_raw("vector_cast_s2x "); |
| 19032 | opnd_array(2)->ext_format(ra, this,idx2, st); // dst |
| 19033 | st->print_raw(","); |
| 19034 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 19035 | st->print_raw("\t! using "); |
| 19036 | opnd_array(3)->ext_format(ra, this,idx3, st); // vtmp |
| 19037 | st->print_raw(", "); |
| 19038 | opnd_array(4)->ext_format(ra, this,idx4, st); // scratch |
| 19039 | st->print_raw(" as TEMP"); |
| 19040 | } |
| 19041 | #endif |
| 19042 | #ifndef PRODUCT |
| 19043 | void vcastStoX_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 19044 | // Start at oper_input_base() and count operands |
| 19045 | unsigned idx0 = 1; |
| 19046 | unsigned idx1 = 1; // src |
| 19047 | st->print_raw("vector_cast_s2x "); |
| 19048 | opnd_array(0)->int_format(ra, this, st); // dst |
| 19049 | st->print_raw(","); |
| 19050 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 19051 | st->print_raw("\t!"); |
| 19052 | } |
| 19053 | #endif |
| 19054 | #ifndef PRODUCT |
| 19055 | void castItoXNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 19056 | // Start at oper_input_base() and count operands |
| 19057 | unsigned idx0 = 1; |
| 19058 | unsigned idx1 = 1; // src |
| 19059 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // scratch |
| 19060 | st->print_raw("vector_cast_i2x "); |
| 19061 | opnd_array(0)->int_format(ra, this, st); // dst |
| 19062 | st->print_raw(","); |
| 19063 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 19064 | st->print_raw("\t! using "); |
| 19065 | opnd_array(2)->ext_format(ra, this,idx2, st); // scratch |
| 19066 | st->print_raw(" as TEMP"); |
| 19067 | } |
| 19068 | #endif |
| 19069 | #ifndef PRODUCT |
| 19070 | void vcastItoXNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 19071 | // Start at oper_input_base() and count operands |
| 19072 | unsigned idx0 = 1; |
| 19073 | unsigned idx1 = 1; // src |
| 19074 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst |
| 19075 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp |
| 19076 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // scratch |
| 19077 | st->print_raw("vector_cast_i2x "); |
| 19078 | opnd_array(2)->ext_format(ra, this,idx2, st); // dst |
| 19079 | st->print_raw(","); |
| 19080 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 19081 | st->print_raw("\t! using "); |
| 19082 | opnd_array(3)->ext_format(ra, this,idx3, st); // vtmp |
| 19083 | st->print_raw(" and "); |
| 19084 | opnd_array(4)->ext_format(ra, this,idx4, st); // scratch |
| 19085 | st->print_raw(" as TEMP"); |
| 19086 | } |
| 19087 | #endif |
| 19088 | #ifndef PRODUCT |
| 19089 | void vcastItoX_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 19090 | // Start at oper_input_base() and count operands |
| 19091 | unsigned idx0 = 1; |
| 19092 | unsigned idx1 = 1; // src |
| 19093 | st->print_raw("vector_cast_i2x "); |
| 19094 | opnd_array(0)->int_format(ra, this, st); // dst |
| 19095 | st->print_raw(","); |
| 19096 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 19097 | st->print_raw("\t!"); |
| 19098 | } |
| 19099 | #endif |
| 19100 | #ifndef PRODUCT |
| 19101 | void vcastLtoBSNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 19102 | // Start at oper_input_base() and count operands |
| 19103 | unsigned idx0 = 1; |
| 19104 | unsigned idx1 = 1; // src |
| 19105 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // scratch |
| 19106 | st->print_raw("vector_cast_l2x "); |
| 19107 | opnd_array(0)->int_format(ra, this, st); // dst |
| 19108 | st->print_raw(","); |
| 19109 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 19110 | st->print_raw("\t! using "); |
| 19111 | opnd_array(2)->ext_format(ra, this,idx2, st); // scratch |
| 19112 | st->print_raw(" as TEMP"); |
| 19113 | } |
| 19114 | #endif |
| 19115 | #ifndef PRODUCT |
| 19116 | void vcastLtoX_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 19117 | // Start at oper_input_base() and count operands |
| 19118 | unsigned idx0 = 1; |
| 19119 | unsigned idx1 = 1; // src |
| 19120 | st->print_raw("vector_cast_l2x "); |
| 19121 | opnd_array(0)->int_format(ra, this, st); // dst |
| 19122 | st->print_raw(","); |
| 19123 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 19124 | st->print_raw("\t!"); |
| 19125 | } |
| 19126 | #endif |
| 19127 | #ifndef PRODUCT |
| 19128 | void vcastFtoD_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 19129 | // Start at oper_input_base() and count operands |
| 19130 | unsigned idx0 = 1; |
| 19131 | unsigned idx1 = 1; // src |
| 19132 | st->print_raw("vector_cast_f2d "); |
| 19133 | opnd_array(0)->int_format(ra, this, st); // dst |
| 19134 | st->print_raw(","); |
| 19135 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 19136 | st->print_raw("\t!"); |
| 19137 | } |
| 19138 | #endif |
| 19139 | #ifndef PRODUCT |
| 19140 | void vcastFtoI_reg_avxNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 19141 | // Start at oper_input_base() and count operands |
| 19142 | unsigned idx0 = 1; |
| 19143 | unsigned idx1 = 1; // src |
| 19144 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst |
| 19145 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // xtmp1 |
| 19146 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // xtmp2 |
| 19147 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // xtmp3 |
| 19148 | unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // xtmp4 |
| 19149 | unsigned idx7 = idx6 + opnd_array(6)->num_edges(); // scratch |
| 19150 | st->print_raw("vector_cast_f2i "); |
| 19151 | opnd_array(2)->ext_format(ra, this,idx2, st); // dst |
| 19152 | st->print_raw(","); |
| 19153 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 19154 | st->print_raw("\t! using "); |
| 19155 | opnd_array(3)->ext_format(ra, this,idx3, st); // xtmp1 |
| 19156 | st->print_raw(", "); |
| 19157 | opnd_array(4)->ext_format(ra, this,idx4, st); // xtmp2 |
| 19158 | st->print_raw(", "); |
| 19159 | opnd_array(5)->ext_format(ra, this,idx5, st); // xtmp3 |
| 19160 | st->print_raw(" and "); |
| 19161 | opnd_array(6)->ext_format(ra, this,idx6, st); // xtmp4 |
| 19162 | st->print_raw(" as TEMP"); |
| 19163 | } |
| 19164 | #endif |
| 19165 | #ifndef PRODUCT |
| 19166 | void vcastFtoI_reg_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 19167 | // Start at oper_input_base() and count operands |
| 19168 | unsigned idx0 = 1; |
| 19169 | unsigned idx1 = 1; // src |
| 19170 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst |
| 19171 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // xtmp1 |
| 19172 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // xtmp2 |
| 19173 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // ktmp1 |
| 19174 | unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // ktmp2 |
| 19175 | unsigned idx7 = idx6 + opnd_array(6)->num_edges(); // scratch |
| 19176 | st->print_raw("vector_cast_f2i "); |
| 19177 | opnd_array(2)->ext_format(ra, this,idx2, st); // dst |
| 19178 | st->print_raw(","); |
| 19179 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 19180 | st->print_raw("\t! using "); |
| 19181 | opnd_array(3)->ext_format(ra, this,idx3, st); // xtmp1 |
| 19182 | st->print_raw(", "); |
| 19183 | opnd_array(4)->ext_format(ra, this,idx4, st); // xtmp2 |
| 19184 | st->print_raw(", "); |
| 19185 | opnd_array(5)->ext_format(ra, this,idx5, st); // ktmp1 |
| 19186 | st->print_raw(" and "); |
| 19187 | opnd_array(6)->ext_format(ra, this,idx6, st); // ktmp2 |
| 19188 | st->print_raw(" as TEMP"); |
| 19189 | } |
| 19190 | #endif |
| 19191 | #ifndef PRODUCT |
| 19192 | void vcastDtoF_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 19193 | // Start at oper_input_base() and count operands |
| 19194 | unsigned idx0 = 1; |
| 19195 | unsigned idx1 = 1; // src |
| 19196 | st->print_raw("vector_cast_d2x "); |
| 19197 | opnd_array(0)->int_format(ra, this, st); // dst |
| 19198 | st->print_raw(","); |
| 19199 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 19200 | st->print_raw("\t!"); |
| 19201 | } |
| 19202 | #endif |
| 19203 | #ifndef PRODUCT |
| 19204 | void vcastDtoL_reg_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 19205 | // Start at oper_input_base() and count operands |
| 19206 | unsigned idx0 = 1; |
| 19207 | unsigned idx1 = 1; // src |
| 19208 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst |
| 19209 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // xtmp1 |
| 19210 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // xtmp2 |
| 19211 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // ktmp1 |
| 19212 | unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // ktmp2 |
| 19213 | unsigned idx7 = idx6 + opnd_array(6)->num_edges(); // scratch |
| 19214 | st->print_raw("vector_cast_d2l "); |
| 19215 | opnd_array(2)->ext_format(ra, this,idx2, st); // dst |
| 19216 | st->print_raw(","); |
| 19217 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 19218 | st->print_raw("\t! using "); |
| 19219 | opnd_array(3)->ext_format(ra, this,idx3, st); // xtmp1 |
| 19220 | st->print_raw(", "); |
| 19221 | opnd_array(4)->ext_format(ra, this,idx4, st); // xtmp2 |
| 19222 | st->print_raw(", "); |
| 19223 | opnd_array(5)->ext_format(ra, this,idx5, st); // ktmp1 |
| 19224 | st->print_raw(" and "); |
| 19225 | opnd_array(6)->ext_format(ra, this,idx6, st); // ktmp2 |
| 19226 | st->print_raw(" as TEMP"); |
| 19227 | } |
| 19228 | #endif |
| 19229 | #ifndef PRODUCT |
| 19230 | void vcmpFDNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 19231 | // Start at oper_input_base() and count operands |
| 19232 | unsigned idx0 = 1; |
| 19233 | unsigned idx1 = 1; // src1 |
| 19234 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 19235 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // cond |
| 19236 | st->print_raw("vector_compare "); |
| 19237 | opnd_array(0)->int_format(ra, this, st); // dst |
| 19238 | st->print_raw(","); |
| 19239 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 19240 | st->print_raw(","); |
| 19241 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 19242 | st->print_raw(","); |
| 19243 | opnd_array(3)->ext_format(ra, this,idx3, st); // cond |
| 19244 | st->print_raw("\t!"); |
| 19245 | } |
| 19246 | #endif |
| 19247 | #ifndef PRODUCT |
| 19248 | void evcmpFD64Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 19249 | // Start at oper_input_base() and count operands |
| 19250 | unsigned idx0 = 1; |
| 19251 | unsigned idx1 = 1; // src1 |
| 19252 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 19253 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // cond |
| 19254 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // scratch |
| 19255 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // ktmp |
| 19256 | st->print_raw("vector_compare "); |
| 19257 | opnd_array(0)->int_format(ra, this, st); // dst |
| 19258 | st->print_raw(","); |
| 19259 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 19260 | st->print_raw(","); |
| 19261 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 19262 | st->print_raw(","); |
| 19263 | opnd_array(3)->ext_format(ra, this,idx3, st); // cond |
| 19264 | st->print_raw("\t! using "); |
| 19265 | opnd_array(4)->ext_format(ra, this,idx4, st); // scratch |
| 19266 | st->print_raw(" as TEMP"); |
| 19267 | } |
| 19268 | #endif |
| 19269 | #ifndef PRODUCT |
| 19270 | void evcmpFDNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 19271 | // Start at oper_input_base() and count operands |
| 19272 | unsigned idx0 = 1; |
| 19273 | unsigned idx1 = 1; // src1 |
| 19274 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 19275 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // cond |
| 19276 | st->print_raw("vector_compare_evex "); |
| 19277 | opnd_array(0)->int_format(ra, this, st); // dst |
| 19278 | st->print_raw(","); |
| 19279 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 19280 | st->print_raw(","); |
| 19281 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 19282 | st->print_raw(","); |
| 19283 | opnd_array(3)->ext_format(ra, this,idx3, st); // cond |
| 19284 | st->print_raw("\t!"); |
| 19285 | } |
| 19286 | #endif |
| 19287 | #ifndef PRODUCT |
| 19288 | void vcmpNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 19289 | // Start at oper_input_base() and count operands |
| 19290 | unsigned idx0 = 1; |
| 19291 | unsigned idx1 = 1; // src1 |
| 19292 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 19293 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // cond |
| 19294 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // scratch |
| 19295 | st->print_raw("vector_compare "); |
| 19296 | opnd_array(0)->int_format(ra, this, st); // dst |
| 19297 | st->print_raw(","); |
| 19298 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 19299 | st->print_raw(","); |
| 19300 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 19301 | st->print_raw(","); |
| 19302 | opnd_array(3)->ext_format(ra, this,idx3, st); // cond |
| 19303 | st->print_raw("\t! using "); |
| 19304 | opnd_array(4)->ext_format(ra, this,idx4, st); // scratch |
| 19305 | st->print_raw(" as TEMP"); |
| 19306 | } |
| 19307 | #endif |
| 19308 | #ifndef PRODUCT |
| 19309 | void vcmpuNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 19310 | // Start at oper_input_base() and count operands |
| 19311 | unsigned idx0 = 1; |
| 19312 | unsigned idx1 = 1; // src1 |
| 19313 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 19314 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // cond |
| 19315 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp1 |
| 19316 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // vtmp2 |
| 19317 | unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // scratch |
| 19318 | st->print_raw("vector_compareu "); |
| 19319 | opnd_array(0)->int_format(ra, this, st); // dst |
| 19320 | st->print_raw(","); |
| 19321 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 19322 | st->print_raw(","); |
| 19323 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 19324 | st->print_raw(","); |
| 19325 | opnd_array(3)->ext_format(ra, this,idx3, st); // cond |
| 19326 | st->print_raw("\t! using "); |
| 19327 | opnd_array(6)->ext_format(ra, this,idx6, st); // scratch |
| 19328 | st->print_raw(" as TEMP"); |
| 19329 | } |
| 19330 | #endif |
| 19331 | #ifndef PRODUCT |
| 19332 | void vcmpu32Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 19333 | // Start at oper_input_base() and count operands |
| 19334 | unsigned idx0 = 1; |
| 19335 | unsigned idx1 = 1; // src1 |
| 19336 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 19337 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // cond |
| 19338 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // dst |
| 19339 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // vtmp1 |
| 19340 | unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // vtmp2 |
| 19341 | unsigned idx7 = idx6 + opnd_array(6)->num_edges(); // vtmp3 |
| 19342 | unsigned idx8 = idx7 + opnd_array(7)->num_edges(); // scratch |
| 19343 | st->print_raw("vector_compareu "); |
| 19344 | opnd_array(4)->ext_format(ra, this,idx4, st); // dst |
| 19345 | st->print_raw(","); |
| 19346 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 19347 | st->print_raw(","); |
| 19348 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 19349 | st->print_raw(","); |
| 19350 | opnd_array(3)->ext_format(ra, this,idx3, st); // cond |
| 19351 | st->print_raw("\t! using "); |
| 19352 | opnd_array(8)->ext_format(ra, this,idx8, st); // scratch |
| 19353 | st->print_raw(" as TEMP"); |
| 19354 | } |
| 19355 | #endif |
| 19356 | #ifndef PRODUCT |
| 19357 | void vcmpu64Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 19358 | // Start at oper_input_base() and count operands |
| 19359 | unsigned idx0 = 1; |
| 19360 | unsigned idx1 = 1; // src1 |
| 19361 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 19362 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // cond |
| 19363 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // scratch |
| 19364 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // ktmp |
| 19365 | st->print_raw("vector_compare "); |
| 19366 | opnd_array(0)->int_format(ra, this, st); // dst |
| 19367 | st->print_raw(","); |
| 19368 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 19369 | st->print_raw(","); |
| 19370 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 19371 | st->print_raw(","); |
| 19372 | opnd_array(3)->ext_format(ra, this,idx3, st); // cond |
| 19373 | st->print_raw("\t! using "); |
| 19374 | opnd_array(4)->ext_format(ra, this,idx4, st); // scratch |
| 19375 | st->print_raw(" as TEMP"); |
| 19376 | } |
| 19377 | #endif |
| 19378 | #ifndef PRODUCT |
| 19379 | void evcmpNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 19380 | // Start at oper_input_base() and count operands |
| 19381 | unsigned idx0 = 1; |
| 19382 | unsigned idx1 = 1; // src1 |
| 19383 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 19384 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // cond |
| 19385 | st->print_raw("vector_compared_evex "); |
| 19386 | opnd_array(0)->int_format(ra, this, st); // dst |
| 19387 | st->print_raw(","); |
| 19388 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 19389 | st->print_raw(","); |
| 19390 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 19391 | st->print_raw(","); |
| 19392 | opnd_array(3)->ext_format(ra, this,idx3, st); // cond |
| 19393 | st->print_raw("\t!"); |
| 19394 | } |
| 19395 | #endif |
| 19396 | #ifndef PRODUCT |
| 19397 | void extractINode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 19398 | // Start at oper_input_base() and count operands |
| 19399 | unsigned idx0 = 1; |
| 19400 | unsigned idx1 = 1; // src |
| 19401 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // idx |
| 19402 | st->print_raw("extractI "); |
| 19403 | opnd_array(0)->int_format(ra, this, st); // dst |
| 19404 | st->print_raw(","); |
| 19405 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 19406 | st->print_raw(","); |
| 19407 | opnd_array(2)->ext_format(ra, this,idx2, st); // idx |
| 19408 | st->print_raw("\t!"); |
| 19409 | } |
| 19410 | #endif |
| 19411 | #ifndef PRODUCT |
| 19412 | void extractI_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 19413 | // Start at oper_input_base() and count operands |
| 19414 | unsigned idx0 = 1; |
| 19415 | unsigned idx1 = 1; // src |
| 19416 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // idx |
| 19417 | st->print_raw("extractI "); |
| 19418 | opnd_array(0)->int_format(ra, this, st); // dst |
| 19419 | st->print_raw(","); |
| 19420 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 19421 | st->print_raw(","); |
| 19422 | opnd_array(2)->ext_format(ra, this,idx2, st); // idx |
| 19423 | st->print_raw("\t!"); |
| 19424 | } |
| 19425 | #endif |
| 19426 | #ifndef PRODUCT |
| 19427 | void extractI_1Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 19428 | // Start at oper_input_base() and count operands |
| 19429 | unsigned idx0 = 1; |
| 19430 | unsigned idx1 = 1; // src |
| 19431 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // idx |
| 19432 | st->print_raw("extractI "); |
| 19433 | opnd_array(0)->int_format(ra, this, st); // dst |
| 19434 | st->print_raw(","); |
| 19435 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 19436 | st->print_raw(","); |
| 19437 | opnd_array(2)->ext_format(ra, this,idx2, st); // idx |
| 19438 | st->print_raw("\t!"); |
| 19439 | } |
| 19440 | #endif |
| 19441 | #ifndef PRODUCT |
| 19442 | void vextractINode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 19443 | // Start at oper_input_base() and count operands |
| 19444 | unsigned idx0 = 1; |
| 19445 | unsigned idx1 = 1; // src |
| 19446 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // idx |
| 19447 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp |
| 19448 | st->print_raw("vextractI "); |
| 19449 | opnd_array(0)->int_format(ra, this, st); // dst |
| 19450 | st->print_raw(","); |
| 19451 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 19452 | st->print_raw(","); |
| 19453 | opnd_array(2)->ext_format(ra, this,idx2, st); // idx |
| 19454 | st->print_raw("\t! using "); |
| 19455 | opnd_array(3)->ext_format(ra, this,idx3, st); // vtmp |
| 19456 | st->print_raw(" as TEMP"); |
| 19457 | } |
| 19458 | #endif |
| 19459 | #ifndef PRODUCT |
| 19460 | void vextractI_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 19461 | // Start at oper_input_base() and count operands |
| 19462 | unsigned idx0 = 1; |
| 19463 | unsigned idx1 = 1; // src |
| 19464 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // idx |
| 19465 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp |
| 19466 | st->print_raw("vextractI "); |
| 19467 | opnd_array(0)->int_format(ra, this, st); // dst |
| 19468 | st->print_raw(","); |
| 19469 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 19470 | st->print_raw(","); |
| 19471 | opnd_array(2)->ext_format(ra, this,idx2, st); // idx |
| 19472 | st->print_raw("\t! using "); |
| 19473 | opnd_array(3)->ext_format(ra, this,idx3, st); // vtmp |
| 19474 | st->print_raw(" as TEMP"); |
| 19475 | } |
| 19476 | #endif |
| 19477 | #ifndef PRODUCT |
| 19478 | void vextractI_1Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 19479 | // Start at oper_input_base() and count operands |
| 19480 | unsigned idx0 = 1; |
| 19481 | unsigned idx1 = 1; // src |
| 19482 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // idx |
| 19483 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp |
| 19484 | st->print_raw("vextractI "); |
| 19485 | opnd_array(0)->int_format(ra, this, st); // dst |
| 19486 | st->print_raw(","); |
| 19487 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 19488 | st->print_raw(","); |
| 19489 | opnd_array(2)->ext_format(ra, this,idx2, st); // idx |
| 19490 | st->print_raw("\t! using "); |
| 19491 | opnd_array(3)->ext_format(ra, this,idx3, st); // vtmp |
| 19492 | st->print_raw(" as TEMP"); |
| 19493 | } |
| 19494 | #endif |
| 19495 | #ifndef PRODUCT |
| 19496 | void extractLNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 19497 | // Start at oper_input_base() and count operands |
| 19498 | unsigned idx0 = 1; |
| 19499 | unsigned idx1 = 1; // src |
| 19500 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // idx |
| 19501 | st->print_raw("extractL "); |
| 19502 | opnd_array(0)->int_format(ra, this, st); // dst |
| 19503 | st->print_raw(","); |
| 19504 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 19505 | st->print_raw(","); |
| 19506 | opnd_array(2)->ext_format(ra, this,idx2, st); // idx |
| 19507 | st->print_raw("\t!"); |
| 19508 | } |
| 19509 | #endif |
| 19510 | #ifndef PRODUCT |
| 19511 | void vextractLNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 19512 | // Start at oper_input_base() and count operands |
| 19513 | unsigned idx0 = 1; |
| 19514 | unsigned idx1 = 1; // src |
| 19515 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // idx |
| 19516 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp |
| 19517 | st->print_raw("vextractL "); |
| 19518 | opnd_array(0)->int_format(ra, this, st); // dst |
| 19519 | st->print_raw(","); |
| 19520 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 19521 | st->print_raw(","); |
| 19522 | opnd_array(2)->ext_format(ra, this,idx2, st); // idx |
| 19523 | st->print_raw("\t! using "); |
| 19524 | opnd_array(3)->ext_format(ra, this,idx3, st); // vtmp |
| 19525 | st->print_raw(" as TEMP"); |
| 19526 | } |
| 19527 | #endif |
| 19528 | #ifndef PRODUCT |
| 19529 | void extractFNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 19530 | // Start at oper_input_base() and count operands |
| 19531 | unsigned idx0 = 1; |
| 19532 | unsigned idx1 = 1; // src |
| 19533 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // idx |
| 19534 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 19535 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp |
| 19536 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // vtmp |
| 19537 | st->print_raw("extractF "); |
| 19538 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 19539 | st->print_raw(","); |
| 19540 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 19541 | st->print_raw(","); |
| 19542 | opnd_array(2)->ext_format(ra, this,idx2, st); // idx |
| 19543 | st->print_raw("\t! using "); |
| 19544 | opnd_array(4)->ext_format(ra, this,idx4, st); // tmp |
| 19545 | st->print_raw(", "); |
| 19546 | opnd_array(5)->ext_format(ra, this,idx5, st); // vtmp |
| 19547 | st->print_raw(" as TEMP"); |
| 19548 | } |
| 19549 | #endif |
| 19550 | #ifndef PRODUCT |
| 19551 | void vextractFNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 19552 | // Start at oper_input_base() and count operands |
| 19553 | unsigned idx0 = 1; |
| 19554 | unsigned idx1 = 1; // src |
| 19555 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // idx |
| 19556 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp |
| 19557 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp |
| 19558 | st->print_raw("vextractF "); |
| 19559 | opnd_array(0)->int_format(ra, this, st); // dst |
| 19560 | st->print_raw(","); |
| 19561 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 19562 | st->print_raw(","); |
| 19563 | opnd_array(2)->ext_format(ra, this,idx2, st); // idx |
| 19564 | st->print_raw("\t! using "); |
| 19565 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp |
| 19566 | st->print_raw(", "); |
| 19567 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp |
| 19568 | st->print_raw(" as TEMP"); |
| 19569 | } |
| 19570 | #endif |
| 19571 | #ifndef PRODUCT |
| 19572 | void extractDNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 19573 | // Start at oper_input_base() and count operands |
| 19574 | unsigned idx0 = 1; |
| 19575 | unsigned idx1 = 1; // src |
| 19576 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // idx |
| 19577 | st->print_raw("extractD "); |
| 19578 | opnd_array(0)->int_format(ra, this, st); // dst |
| 19579 | st->print_raw(","); |
| 19580 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 19581 | st->print_raw(","); |
| 19582 | opnd_array(2)->ext_format(ra, this,idx2, st); // idx |
| 19583 | st->print_raw("\t!"); |
| 19584 | } |
| 19585 | #endif |
| 19586 | #ifndef PRODUCT |
| 19587 | void vextractDNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 19588 | // Start at oper_input_base() and count operands |
| 19589 | unsigned idx0 = 1; |
| 19590 | unsigned idx1 = 1; // src |
| 19591 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // idx |
| 19592 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp |
| 19593 | st->print_raw("vextractD "); |
| 19594 | opnd_array(0)->int_format(ra, this, st); // dst |
| 19595 | st->print_raw(","); |
| 19596 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 19597 | st->print_raw(","); |
| 19598 | opnd_array(2)->ext_format(ra, this,idx2, st); // idx |
| 19599 | st->print_raw("\t! using "); |
| 19600 | opnd_array(3)->ext_format(ra, this,idx3, st); // vtmp |
| 19601 | st->print_raw(" as TEMP"); |
| 19602 | } |
| 19603 | #endif |
| 19604 | #ifndef PRODUCT |
| 19605 | void blendvpNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 19606 | // Start at oper_input_base() and count operands |
| 19607 | unsigned idx0 = 1; |
| 19608 | unsigned idx1 = 1; // dst |
| 19609 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 19610 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 19611 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp |
| 19612 | st->print_raw("vector_blend "); |
| 19613 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 19614 | st->print_raw(","); |
| 19615 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 19616 | st->print_raw(","); |
| 19617 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 19618 | st->print_raw("\t! using "); |
| 19619 | opnd_array(4)->ext_format(ra, this,idx4, st); // tmp |
| 19620 | st->print_raw(" as TEMP"); |
| 19621 | } |
| 19622 | #endif |
| 19623 | #ifndef PRODUCT |
| 19624 | void vblendvpINode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 19625 | // Start at oper_input_base() and count operands |
| 19626 | unsigned idx0 = 1; |
| 19627 | unsigned idx1 = 1; // src1 |
| 19628 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 19629 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 19630 | st->print_raw("vector_blend "); |
| 19631 | opnd_array(0)->int_format(ra, this, st); // dst |
| 19632 | st->print_raw(","); |
| 19633 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 19634 | st->print_raw(","); |
| 19635 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 19636 | st->print_raw(","); |
| 19637 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 19638 | st->print_raw("\t!"); |
| 19639 | } |
| 19640 | #endif |
| 19641 | #ifndef PRODUCT |
| 19642 | void vblendvpFDNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 19643 | // Start at oper_input_base() and count operands |
| 19644 | unsigned idx0 = 1; |
| 19645 | unsigned idx1 = 1; // src1 |
| 19646 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 19647 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 19648 | st->print_raw("vector_blend "); |
| 19649 | opnd_array(0)->int_format(ra, this, st); // dst |
| 19650 | st->print_raw(","); |
| 19651 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 19652 | st->print_raw(","); |
| 19653 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 19654 | st->print_raw(","); |
| 19655 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 19656 | st->print_raw("\t!"); |
| 19657 | } |
| 19658 | #endif |
| 19659 | #ifndef PRODUCT |
| 19660 | void evblendvp64Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 19661 | // Start at oper_input_base() and count operands |
| 19662 | unsigned idx0 = 1; |
| 19663 | unsigned idx1 = 1; // src1 |
| 19664 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 19665 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 19666 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // scratch |
| 19667 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // ktmp |
| 19668 | st->print_raw("vector_blend "); |
| 19669 | opnd_array(0)->int_format(ra, this, st); // dst |
| 19670 | st->print_raw(","); |
| 19671 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 19672 | st->print_raw(","); |
| 19673 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 19674 | st->print_raw(","); |
| 19675 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 19676 | st->print_raw("\t! using "); |
| 19677 | opnd_array(4)->ext_format(ra, this,idx4, st); // scratch |
| 19678 | st->print_raw(" and k2 as TEMP"); |
| 19679 | } |
| 19680 | #endif |
| 19681 | #ifndef PRODUCT |
| 19682 | void evblendvp64_maskedNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 19683 | // Start at oper_input_base() and count operands |
| 19684 | unsigned idx0 = 1; |
| 19685 | unsigned idx1 = 1; // src1 |
| 19686 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 19687 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 19688 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // scratch |
| 19689 | st->print_raw("vector_blend "); |
| 19690 | opnd_array(0)->int_format(ra, this, st); // dst |
| 19691 | st->print_raw(","); |
| 19692 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 19693 | st->print_raw(","); |
| 19694 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 19695 | st->print_raw(","); |
| 19696 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 19697 | st->print_raw("\t! using "); |
| 19698 | opnd_array(4)->ext_format(ra, this,idx4, st); // scratch |
| 19699 | st->print_raw(" and k2 as TEMP"); |
| 19700 | } |
| 19701 | #endif |
| 19702 | #ifndef PRODUCT |
| 19703 | void vabsB_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 19704 | // Start at oper_input_base() and count operands |
| 19705 | unsigned idx0 = 1; |
| 19706 | unsigned idx1 = 1; // src |
| 19707 | st->print_raw("vabsb "); |
| 19708 | opnd_array(0)->int_format(ra, this, st); // dst |
| 19709 | st->print_raw(","); |
| 19710 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 19711 | st->print_raw("\t# "); |
| 19712 | opnd_array(0)->int_format(ra, this, st); // dst |
| 19713 | st->print_raw(" = |"); |
| 19714 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 19715 | st->print_raw("| abs packedB"); |
| 19716 | } |
| 19717 | #endif |
| 19718 | #ifndef PRODUCT |
| 19719 | void vabsS_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 19720 | // Start at oper_input_base() and count operands |
| 19721 | unsigned idx0 = 1; |
| 19722 | unsigned idx1 = 1; // src |
| 19723 | st->print_raw("vabsw "); |
| 19724 | opnd_array(0)->int_format(ra, this, st); // dst |
| 19725 | st->print_raw(","); |
| 19726 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 19727 | st->print_raw("\t# "); |
| 19728 | opnd_array(0)->int_format(ra, this, st); // dst |
| 19729 | st->print_raw(" = |"); |
| 19730 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 19731 | st->print_raw("| abs packedS"); |
| 19732 | } |
| 19733 | #endif |
| 19734 | #ifndef PRODUCT |
| 19735 | void vabsI_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 19736 | // Start at oper_input_base() and count operands |
| 19737 | unsigned idx0 = 1; |
| 19738 | unsigned idx1 = 1; // src |
| 19739 | st->print_raw("pabsd "); |
| 19740 | opnd_array(0)->int_format(ra, this, st); // dst |
| 19741 | st->print_raw(","); |
| 19742 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 19743 | st->print_raw("\t# "); |
| 19744 | opnd_array(0)->int_format(ra, this, st); // dst |
| 19745 | st->print_raw(" = |"); |
| 19746 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 19747 | st->print_raw("| abs packedI"); |
| 19748 | } |
| 19749 | #endif |
| 19750 | #ifndef PRODUCT |
| 19751 | void vabsL_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 19752 | // Start at oper_input_base() and count operands |
| 19753 | unsigned idx0 = 1; |
| 19754 | unsigned idx1 = 1; // src |
| 19755 | st->print_raw("evpabsq "); |
| 19756 | opnd_array(0)->int_format(ra, this, st); // dst |
| 19757 | st->print_raw(","); |
| 19758 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 19759 | st->print_raw("\t# "); |
| 19760 | opnd_array(0)->int_format(ra, this, st); // dst |
| 19761 | st->print_raw(" = |"); |
| 19762 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 19763 | st->print_raw("| abs packedL"); |
| 19764 | } |
| 19765 | #endif |
| 19766 | #ifndef PRODUCT |
| 19767 | void vabsnegFNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 19768 | // Start at oper_input_base() and count operands |
| 19769 | unsigned idx0 = 1; |
| 19770 | unsigned idx1 = 1; // src |
| 19771 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // scratch |
| 19772 | st->print_raw("vabsnegf "); |
| 19773 | opnd_array(0)->int_format(ra, this, st); // dst |
| 19774 | st->print_raw(","); |
| 19775 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 19776 | st->print_raw(",[mask]\t# absneg packedF"); |
| 19777 | } |
| 19778 | #endif |
| 19779 | #ifndef PRODUCT |
| 19780 | void vabsnegF_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 19781 | // Start at oper_input_base() and count operands |
| 19782 | unsigned idx0 = 1; |
| 19783 | unsigned idx1 = 1; // src |
| 19784 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // scratch |
| 19785 | st->print_raw("vabsnegf "); |
| 19786 | opnd_array(0)->int_format(ra, this, st); // dst |
| 19787 | st->print_raw(","); |
| 19788 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 19789 | st->print_raw(",[mask]\t# absneg packedF"); |
| 19790 | } |
| 19791 | #endif |
| 19792 | #ifndef PRODUCT |
| 19793 | void vabsneg4FNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 19794 | // Start at oper_input_base() and count operands |
| 19795 | unsigned idx0 = 1; |
| 19796 | unsigned idx1 = 1; // dst |
| 19797 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // scratch |
| 19798 | st->print_raw("vabsnegf "); |
| 19799 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 19800 | st->print_raw(",[mask]\t# absneg packed4F"); |
| 19801 | } |
| 19802 | #endif |
| 19803 | #ifndef PRODUCT |
| 19804 | void vabsneg4F_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 19805 | // Start at oper_input_base() and count operands |
| 19806 | unsigned idx0 = 1; |
| 19807 | unsigned idx1 = 1; // dst |
| 19808 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // scratch |
| 19809 | st->print_raw("vabsnegf "); |
| 19810 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 19811 | st->print_raw(",[mask]\t# absneg packed4F"); |
| 19812 | } |
| 19813 | #endif |
| 19814 | #ifndef PRODUCT |
| 19815 | void vabsnegDNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 19816 | // Start at oper_input_base() and count operands |
| 19817 | unsigned idx0 = 1; |
| 19818 | unsigned idx1 = 1; // src |
| 19819 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // scratch |
| 19820 | st->print_raw("vabsnegd "); |
| 19821 | opnd_array(0)->int_format(ra, this, st); // dst |
| 19822 | st->print_raw(","); |
| 19823 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 19824 | st->print_raw(",[mask]\t# absneg packedD"); |
| 19825 | } |
| 19826 | #endif |
| 19827 | #ifndef PRODUCT |
| 19828 | void vabsnegD_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 19829 | // Start at oper_input_base() and count operands |
| 19830 | unsigned idx0 = 1; |
| 19831 | unsigned idx1 = 1; // src |
| 19832 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // scratch |
| 19833 | st->print_raw("vabsnegd "); |
| 19834 | opnd_array(0)->int_format(ra, this, st); // dst |
| 19835 | st->print_raw(","); |
| 19836 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 19837 | st->print_raw(",[mask]\t# absneg packedD"); |
| 19838 | } |
| 19839 | #endif |
| 19840 | #ifndef PRODUCT |
| 19841 | void vptest_alltrue_lt16Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 19842 | // Start at oper_input_base() and count operands |
| 19843 | unsigned idx0 = 1; |
| 19844 | unsigned idx1 = 1; // src1 |
| 19845 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 19846 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1 |
| 19847 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2 |
| 19848 | st->print_raw("vptest_alltrue_lt16 "); |
| 19849 | opnd_array(0)->int_format(ra, this, st); // dst |
| 19850 | st->print_raw(","); |
| 19851 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 19852 | st->print_raw(", "); |
| 19853 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 19854 | st->print_raw("\t! using "); |
| 19855 | opnd_array(3)->ext_format(ra, this,idx3, st); // vtmp1 |
| 19856 | st->print_raw(", "); |
| 19857 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp2 |
| 19858 | st->print_raw(" and "); |
| 19859 | st->print_raw("RFLAGS"); |
| 19860 | st->print_raw(" as TEMP"); |
| 19861 | } |
| 19862 | #endif |
| 19863 | #ifndef PRODUCT |
| 19864 | void vptest_alltrue_ge16Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 19865 | // Start at oper_input_base() and count operands |
| 19866 | unsigned idx0 = 1; |
| 19867 | unsigned idx1 = 1; // src1 |
| 19868 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 19869 | st->print_raw("vptest_alltrue_ge16 "); |
| 19870 | opnd_array(0)->int_format(ra, this, st); // dst |
| 19871 | st->print_raw(","); |
| 19872 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 19873 | st->print_raw(", "); |
| 19874 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 19875 | st->print_raw("\t! using "); |
| 19876 | st->print_raw("RFLAGS"); |
| 19877 | st->print_raw(" as TEMP"); |
| 19878 | } |
| 19879 | #endif |
| 19880 | #ifndef PRODUCT |
| 19881 | void vptest_alltrue_lt8_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 19882 | // Start at oper_input_base() and count operands |
| 19883 | unsigned idx0 = 1; |
| 19884 | unsigned idx1 = 1; // src1 |
| 19885 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 19886 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // kscratch |
| 19887 | st->print_raw("vptest_alltrue_lt8_evex "); |
| 19888 | opnd_array(0)->int_format(ra, this, st); // dst |
| 19889 | st->print_raw(","); |
| 19890 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 19891 | st->print_raw(","); |
| 19892 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 19893 | st->print_raw("\t! using "); |
| 19894 | st->print_raw("RFLAGS"); |
| 19895 | st->print_raw(" as TEMP"); |
| 19896 | } |
| 19897 | #endif |
| 19898 | #ifndef PRODUCT |
| 19899 | void vptest_alltrue_ge8_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 19900 | // Start at oper_input_base() and count operands |
| 19901 | unsigned idx0 = 1; |
| 19902 | unsigned idx1 = 1; // src1 |
| 19903 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 19904 | st->print_raw("vptest_alltrue_ge8_evex "); |
| 19905 | opnd_array(0)->int_format(ra, this, st); // dst |
| 19906 | st->print_raw(","); |
| 19907 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 19908 | st->print_raw(","); |
| 19909 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 19910 | st->print_raw("\t! using "); |
| 19911 | st->print_raw("RFLAGS"); |
| 19912 | st->print_raw(" as TEMP"); |
| 19913 | } |
| 19914 | #endif |
| 19915 | #ifndef PRODUCT |
| 19916 | void vptest_anytrue_lt16Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 19917 | // Start at oper_input_base() and count operands |
| 19918 | unsigned idx0 = 1; |
| 19919 | unsigned idx1 = 1; // src1 |
| 19920 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 19921 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp |
| 19922 | st->print_raw("vptest_anytrue_lt16 "); |
| 19923 | opnd_array(0)->int_format(ra, this, st); // dst |
| 19924 | st->print_raw(","); |
| 19925 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 19926 | st->print_raw(","); |
| 19927 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 19928 | st->print_raw("\t! using "); |
| 19929 | opnd_array(3)->ext_format(ra, this,idx3, st); // vtmp |
| 19930 | st->print_raw(", "); |
| 19931 | st->print_raw("RFLAGS"); |
| 19932 | st->print_raw(" as TEMP"); |
| 19933 | } |
| 19934 | #endif |
| 19935 | #ifndef PRODUCT |
| 19936 | void vptest_anytrue_ge16Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 19937 | // Start at oper_input_base() and count operands |
| 19938 | unsigned idx0 = 1; |
| 19939 | unsigned idx1 = 1; // src1 |
| 19940 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 19941 | st->print_raw("vptest_anytrue_ge16 "); |
| 19942 | opnd_array(0)->int_format(ra, this, st); // dst |
| 19943 | st->print_raw(","); |
| 19944 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 19945 | st->print_raw(","); |
| 19946 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 19947 | st->print_raw("\t! using "); |
| 19948 | st->print_raw("RFLAGS"); |
| 19949 | st->print_raw(" as TEMP"); |
| 19950 | } |
| 19951 | #endif |
| 19952 | #ifndef PRODUCT |
| 19953 | void vptest_anytrue_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 19954 | // Start at oper_input_base() and count operands |
| 19955 | unsigned idx0 = 1; |
| 19956 | unsigned idx1 = 1; // src1 |
| 19957 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 19958 | st->print_raw("vptest_anytrue_lt8_evex "); |
| 19959 | opnd_array(0)->int_format(ra, this, st); // dst |
| 19960 | st->print_raw(","); |
| 19961 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 19962 | st->print_raw(","); |
| 19963 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 19964 | st->print_raw("\t! using "); |
| 19965 | st->print_raw("RFLAGS"); |
| 19966 | st->print_raw(" as TEMP"); |
| 19967 | } |
| 19968 | #endif |
| 19969 | #ifndef PRODUCT |
| 19970 | void cmpvptest_anytrue_lt16Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 19971 | // Start at oper_input_base() and count operands |
| 19972 | unsigned idx0 = 1; |
| 19973 | unsigned idx1 = 1; // src1 |
| 19974 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 19975 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // zero |
| 19976 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp |
| 19977 | st->print_raw("cmpvptest_anytrue_lt16 "); |
| 19978 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 19979 | st->print_raw(","); |
| 19980 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 19981 | st->print_raw("\t! using "); |
| 19982 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp |
| 19983 | st->print_raw(" as TEMP"); |
| 19984 | } |
| 19985 | #endif |
| 19986 | #ifndef PRODUCT |
| 19987 | void cmpvptest_anytrue_ge16Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 19988 | // Start at oper_input_base() and count operands |
| 19989 | unsigned idx0 = 1; |
| 19990 | unsigned idx1 = 1; // src1 |
| 19991 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 19992 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // zero |
| 19993 | st->print_raw("cmpvptest_anytrue_ge16 "); |
| 19994 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 19995 | st->print_raw(","); |
| 19996 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 19997 | st->print_raw("\t!"); |
| 19998 | } |
| 19999 | #endif |
| 20000 | #ifndef PRODUCT |
| 20001 | void cmpvptest_anytrue_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 20002 | // Start at oper_input_base() and count operands |
| 20003 | unsigned idx0 = 1; |
| 20004 | unsigned idx1 = 1; // src1 |
| 20005 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 20006 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // zero |
| 20007 | st->print_raw("cmpvptest_anytrue_evex "); |
| 20008 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 20009 | st->print_raw(","); |
| 20010 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 20011 | st->print_raw("\t!"); |
| 20012 | } |
| 20013 | #endif |
| 20014 | #ifndef PRODUCT |
| 20015 | void loadMaskNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 20016 | // Start at oper_input_base() and count operands |
| 20017 | unsigned idx0 = 1; |
| 20018 | unsigned idx1 = 1; // src |
| 20019 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst |
| 20020 | st->print_raw("vector_loadmask_byte "); |
| 20021 | opnd_array(2)->ext_format(ra, this,idx2, st); // dst |
| 20022 | st->print_raw(", "); |
| 20023 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 20024 | st->print_raw("\n\t"); |
| 20025 | } |
| 20026 | #endif |
| 20027 | #ifndef PRODUCT |
| 20028 | void loadMask64Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 20029 | // Start at oper_input_base() and count operands |
| 20030 | unsigned idx0 = 1; |
| 20031 | unsigned idx1 = 1; // src |
| 20032 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // xtmp |
| 20033 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp |
| 20034 | st->print_raw("vector_loadmask_64byte "); |
| 20035 | opnd_array(0)->int_format(ra, this, st); // dst |
| 20036 | st->print_raw(", "); |
| 20037 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 20038 | st->print_raw("\t! using "); |
| 20039 | opnd_array(2)->ext_format(ra, this,idx2, st); // xtmp |
| 20040 | st->print_raw(" and "); |
| 20041 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp |
| 20042 | st->print_raw(" as TEMP"); |
| 20043 | } |
| 20044 | #endif |
| 20045 | #ifndef PRODUCT |
| 20046 | void loadMask_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 20047 | // Start at oper_input_base() and count operands |
| 20048 | unsigned idx0 = 1; |
| 20049 | unsigned idx1 = 1; // src |
| 20050 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // xtmp |
| 20051 | st->print_raw("vector_loadmask_byte "); |
| 20052 | opnd_array(0)->int_format(ra, this, st); // dst |
| 20053 | st->print_raw(", "); |
| 20054 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 20055 | st->print_raw("\t! using "); |
| 20056 | opnd_array(2)->ext_format(ra, this,idx2, st); // xtmp |
| 20057 | st->print_raw(" as TEMP"); |
| 20058 | } |
| 20059 | #endif |
| 20060 | #ifndef PRODUCT |
| 20061 | void vstoreMask1BNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 20062 | // Start at oper_input_base() and count operands |
| 20063 | unsigned idx0 = 1; |
| 20064 | unsigned idx1 = 1; // src |
| 20065 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // size |
| 20066 | st->print_raw("vector_store_mask "); |
| 20067 | opnd_array(0)->int_format(ra, this, st); // dst |
| 20068 | st->print_raw(", "); |
| 20069 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 20070 | st->print_raw(" \t! elem size is "); |
| 20071 | opnd_array(2)->ext_format(ra, this,idx2, st); // size |
| 20072 | st->print_raw(" byte[s]"); |
| 20073 | } |
| 20074 | #endif |
| 20075 | #ifndef PRODUCT |
| 20076 | void vstoreMask2BNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 20077 | // Start at oper_input_base() and count operands |
| 20078 | unsigned idx0 = 1; |
| 20079 | unsigned idx1 = 1; // src |
| 20080 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // size |
| 20081 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 20082 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // xtmp |
| 20083 | st->print_raw("vector_store_mask "); |
| 20084 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 20085 | st->print_raw(", "); |
| 20086 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 20087 | st->print_raw(" \t! elem size is "); |
| 20088 | opnd_array(2)->ext_format(ra, this,idx2, st); // size |
| 20089 | st->print_raw(" byte[s]"); |
| 20090 | } |
| 20091 | #endif |
| 20092 | #ifndef PRODUCT |
| 20093 | void vstoreMask4BNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 20094 | // Start at oper_input_base() and count operands |
| 20095 | unsigned idx0 = 1; |
| 20096 | unsigned idx1 = 1; // src |
| 20097 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // size |
| 20098 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 20099 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // xtmp |
| 20100 | st->print_raw("vector_store_mask "); |
| 20101 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 20102 | st->print_raw(", "); |
| 20103 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 20104 | st->print_raw(" \t! elem size is "); |
| 20105 | opnd_array(2)->ext_format(ra, this,idx2, st); // size |
| 20106 | st->print_raw(" byte[s]"); |
| 20107 | } |
| 20108 | #endif |
| 20109 | #ifndef PRODUCT |
| 20110 | void storeMask8BNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 20111 | // Start at oper_input_base() and count operands |
| 20112 | unsigned idx0 = 1; |
| 20113 | unsigned idx1 = 1; // src |
| 20114 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // size |
| 20115 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 20116 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // xtmp |
| 20117 | st->print_raw("vector_store_mask "); |
| 20118 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 20119 | st->print_raw(", "); |
| 20120 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 20121 | st->print_raw(" \t! elem size is "); |
| 20122 | opnd_array(2)->ext_format(ra, this,idx2, st); // size |
| 20123 | st->print_raw(" byte[s]"); |
| 20124 | } |
| 20125 | #endif |
| 20126 | #ifndef PRODUCT |
| 20127 | void storeMask8B_avxNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 20128 | // Start at oper_input_base() and count operands |
| 20129 | unsigned idx0 = 1; |
| 20130 | unsigned idx1 = 1; // src |
| 20131 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // size |
| 20132 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 20133 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp |
| 20134 | st->print_raw("vector_store_mask "); |
| 20135 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 20136 | st->print_raw(", "); |
| 20137 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 20138 | st->print_raw(" \t! elem size is "); |
| 20139 | opnd_array(2)->ext_format(ra, this,idx2, st); // size |
| 20140 | st->print_raw(" byte[s], using "); |
| 20141 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp |
| 20142 | st->print_raw(" as TEMP"); |
| 20143 | } |
| 20144 | #endif |
| 20145 | #ifndef PRODUCT |
| 20146 | void vstoreMask4B_evex_novectmaskNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 20147 | // Start at oper_input_base() and count operands |
| 20148 | unsigned idx0 = 1; |
| 20149 | unsigned idx1 = 1; // src |
| 20150 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // size |
| 20151 | st->print_raw("vector_store_mask "); |
| 20152 | opnd_array(0)->int_format(ra, this, st); // dst |
| 20153 | st->print_raw(", "); |
| 20154 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 20155 | st->print_raw(" \t! elem size is "); |
| 20156 | opnd_array(2)->ext_format(ra, this,idx2, st); // size |
| 20157 | st->print_raw(" byte[s]"); |
| 20158 | } |
| 20159 | #endif |
| 20160 | #ifndef PRODUCT |
| 20161 | void vstoreMask8B_evex_novectmaskNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 20162 | // Start at oper_input_base() and count operands |
| 20163 | unsigned idx0 = 1; |
| 20164 | unsigned idx1 = 1; // src |
| 20165 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // size |
| 20166 | st->print_raw("vector_store_mask "); |
| 20167 | opnd_array(0)->int_format(ra, this, st); // dst |
| 20168 | st->print_raw(", "); |
| 20169 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 20170 | st->print_raw(" \t! elem size is "); |
| 20171 | opnd_array(2)->ext_format(ra, this,idx2, st); // size |
| 20172 | st->print_raw(" byte[s]"); |
| 20173 | } |
| 20174 | #endif |
| 20175 | #ifndef PRODUCT |
| 20176 | void vstoreMask_evex_vectmaskNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 20177 | // Start at oper_input_base() and count operands |
| 20178 | unsigned idx0 = 1; |
| 20179 | unsigned idx1 = 1; // mask |
| 20180 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // size |
| 20181 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 20182 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp |
| 20183 | st->print_raw("vector_store_mask "); |
| 20184 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 20185 | st->print_raw(", "); |
| 20186 | opnd_array(1)->ext_format(ra, this,idx1, st); // mask |
| 20187 | st->print_raw(" \t! elem size is "); |
| 20188 | opnd_array(2)->ext_format(ra, this,idx2, st); // size |
| 20189 | st->print_raw(" byte[s]"); |
| 20190 | } |
| 20191 | #endif |
| 20192 | #ifndef PRODUCT |
| 20193 | void vstoreMask_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 20194 | // Start at oper_input_base() and count operands |
| 20195 | unsigned idx0 = 1; |
| 20196 | unsigned idx1 = 1; // mask |
| 20197 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // size |
| 20198 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 20199 | st->print_raw("vector_store_mask "); |
| 20200 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 20201 | st->print_raw(", "); |
| 20202 | opnd_array(1)->ext_format(ra, this,idx1, st); // mask |
| 20203 | st->print_raw(" \t! elem size is "); |
| 20204 | opnd_array(2)->ext_format(ra, this,idx2, st); // size |
| 20205 | st->print_raw(" byte[s]"); |
| 20206 | } |
| 20207 | #endif |
| 20208 | #ifndef PRODUCT |
| 20209 | void vmaskcast_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 20210 | // Start at oper_input_base() and count operands |
| 20211 | unsigned idx0 = 1; |
| 20212 | unsigned idx1 = 1; // dst |
| 20213 | st->print_raw("vector_mask_cast "); |
| 20214 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 20215 | } |
| 20216 | #endif |
| 20217 | #ifndef PRODUCT |
| 20218 | void vmaskcastNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 20219 | // Start at oper_input_base() and count operands |
| 20220 | unsigned idx0 = 1; |
| 20221 | unsigned idx1 = 1; // dst |
| 20222 | st->print_raw("vector_mask_cast "); |
| 20223 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 20224 | } |
| 20225 | #endif |
| 20226 | #ifndef PRODUCT |
| 20227 | void loadIotaIndicesNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 20228 | // Start at oper_input_base() and count operands |
| 20229 | unsigned idx0 = 1; |
| 20230 | unsigned idx1 = 1; // src |
| 20231 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // scratch |
| 20232 | st->print_raw("vector_load_iota "); |
| 20233 | opnd_array(0)->int_format(ra, this, st); // dst |
| 20234 | st->print_raw(" CONSTANT_MEMORY\t! load iota indices"); |
| 20235 | } |
| 20236 | #endif |
| 20237 | #ifndef PRODUCT |
| 20238 | void loadShuffleBNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 20239 | // Start at oper_input_base() and count operands |
| 20240 | unsigned idx0 = 1; |
| 20241 | unsigned idx1 = 1; // dst |
| 20242 | st->print_raw("vector_load_shuffle "); |
| 20243 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 20244 | st->print_raw(", "); |
| 20245 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 20246 | } |
| 20247 | #endif |
| 20248 | #ifndef PRODUCT |
| 20249 | void rearrangeBNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 20250 | // Start at oper_input_base() and count operands |
| 20251 | unsigned idx0 = 1; |
| 20252 | unsigned idx1 = 1; // dst |
| 20253 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shuffle |
| 20254 | st->print_raw("vector_rearrange "); |
| 20255 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 20256 | st->print_raw(", "); |
| 20257 | opnd_array(2)->ext_format(ra, this,idx2, st); // shuffle |
| 20258 | st->print_raw(", "); |
| 20259 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 20260 | } |
| 20261 | #endif |
| 20262 | #ifndef PRODUCT |
| 20263 | void rearrangeB_avxNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 20264 | // Start at oper_input_base() and count operands |
| 20265 | unsigned idx0 = 1; |
| 20266 | unsigned idx1 = 1; // src |
| 20267 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shuffle |
| 20268 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 20269 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp1 |
| 20270 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // vtmp2 |
| 20271 | unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // scratch |
| 20272 | st->print_raw("vector_rearrange "); |
| 20273 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 20274 | st->print_raw(", "); |
| 20275 | opnd_array(2)->ext_format(ra, this,idx2, st); // shuffle |
| 20276 | st->print_raw(", "); |
| 20277 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 20278 | st->print_raw("\t! using "); |
| 20279 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp1 |
| 20280 | st->print_raw(", "); |
| 20281 | opnd_array(5)->ext_format(ra, this,idx5, st); // vtmp2 |
| 20282 | st->print_raw(", "); |
| 20283 | opnd_array(6)->ext_format(ra, this,idx6, st); // scratch |
| 20284 | st->print_raw(" as TEMP"); |
| 20285 | } |
| 20286 | #endif |
| 20287 | #ifndef PRODUCT |
| 20288 | void rearrangeB_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 20289 | // Start at oper_input_base() and count operands |
| 20290 | unsigned idx0 = 1; |
| 20291 | unsigned idx1 = 1; // src |
| 20292 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shuffle |
| 20293 | st->print_raw("vector_rearrange "); |
| 20294 | opnd_array(0)->int_format(ra, this, st); // dst |
| 20295 | st->print_raw(", "); |
| 20296 | opnd_array(2)->ext_format(ra, this,idx2, st); // shuffle |
| 20297 | st->print_raw(", "); |
| 20298 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 20299 | } |
| 20300 | #endif |
| 20301 | #ifndef PRODUCT |
| 20302 | void loadShuffleSNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 20303 | // Start at oper_input_base() and count operands |
| 20304 | unsigned idx0 = 1; |
| 20305 | unsigned idx1 = 1; // src |
| 20306 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst |
| 20307 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp |
| 20308 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // scratch |
| 20309 | st->print_raw("vector_load_shuffle "); |
| 20310 | opnd_array(2)->ext_format(ra, this,idx2, st); // dst |
| 20311 | st->print_raw(", "); |
| 20312 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 20313 | st->print_raw("\t! using "); |
| 20314 | opnd_array(3)->ext_format(ra, this,idx3, st); // vtmp |
| 20315 | st->print_raw(" and "); |
| 20316 | opnd_array(4)->ext_format(ra, this,idx4, st); // scratch |
| 20317 | st->print_raw(" as TEMP"); |
| 20318 | } |
| 20319 | #endif |
| 20320 | #ifndef PRODUCT |
| 20321 | void rearrangeSNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 20322 | // Start at oper_input_base() and count operands |
| 20323 | unsigned idx0 = 1; |
| 20324 | unsigned idx1 = 1; // dst |
| 20325 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shuffle |
| 20326 | st->print_raw("vector_rearrange "); |
| 20327 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 20328 | st->print_raw(", "); |
| 20329 | opnd_array(2)->ext_format(ra, this,idx2, st); // shuffle |
| 20330 | st->print_raw(", "); |
| 20331 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 20332 | } |
| 20333 | #endif |
| 20334 | #ifndef PRODUCT |
| 20335 | void rearrangeS_avxNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 20336 | // Start at oper_input_base() and count operands |
| 20337 | unsigned idx0 = 1; |
| 20338 | unsigned idx1 = 1; // src |
| 20339 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shuffle |
| 20340 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 20341 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp1 |
| 20342 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // vtmp2 |
| 20343 | unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // scratch |
| 20344 | st->print_raw("vector_rearrange "); |
| 20345 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 20346 | st->print_raw(", "); |
| 20347 | opnd_array(2)->ext_format(ra, this,idx2, st); // shuffle |
| 20348 | st->print_raw(", "); |
| 20349 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 20350 | st->print_raw("\t! using "); |
| 20351 | opnd_array(4)->ext_format(ra, this,idx4, st); // vtmp1 |
| 20352 | st->print_raw(", "); |
| 20353 | opnd_array(5)->ext_format(ra, this,idx5, st); // vtmp2 |
| 20354 | st->print_raw(", "); |
| 20355 | opnd_array(6)->ext_format(ra, this,idx6, st); // scratch |
| 20356 | st->print_raw(" as TEMP"); |
| 20357 | } |
| 20358 | #endif |
| 20359 | #ifndef PRODUCT |
| 20360 | void loadShuffleS_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 20361 | // Start at oper_input_base() and count operands |
| 20362 | unsigned idx0 = 1; |
| 20363 | unsigned idx1 = 1; // src |
| 20364 | st->print_raw("vector_load_shuffle "); |
| 20365 | opnd_array(0)->int_format(ra, this, st); // dst |
| 20366 | st->print_raw(", "); |
| 20367 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 20368 | } |
| 20369 | #endif |
| 20370 | #ifndef PRODUCT |
| 20371 | void rearrangeS_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 20372 | // Start at oper_input_base() and count operands |
| 20373 | unsigned idx0 = 1; |
| 20374 | unsigned idx1 = 1; // src |
| 20375 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shuffle |
| 20376 | st->print_raw("vector_rearrange "); |
| 20377 | opnd_array(0)->int_format(ra, this, st); // dst |
| 20378 | st->print_raw(", "); |
| 20379 | opnd_array(2)->ext_format(ra, this,idx2, st); // shuffle |
| 20380 | st->print_raw(", "); |
| 20381 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 20382 | } |
| 20383 | #endif |
| 20384 | #ifndef PRODUCT |
| 20385 | void loadShuffleINode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 20386 | // Start at oper_input_base() and count operands |
| 20387 | unsigned idx0 = 1; |
| 20388 | unsigned idx1 = 1; // src |
| 20389 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst |
| 20390 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp |
| 20391 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // scratch |
| 20392 | st->print_raw("vector_load_shuffle "); |
| 20393 | opnd_array(2)->ext_format(ra, this,idx2, st); // dst |
| 20394 | st->print_raw(", "); |
| 20395 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 20396 | st->print_raw("\t! using "); |
| 20397 | opnd_array(3)->ext_format(ra, this,idx3, st); // vtmp |
| 20398 | st->print_raw(" and "); |
| 20399 | opnd_array(4)->ext_format(ra, this,idx4, st); // scratch |
| 20400 | st->print_raw(" as TEMP"); |
| 20401 | } |
| 20402 | #endif |
| 20403 | #ifndef PRODUCT |
| 20404 | void rearrangeINode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 20405 | // Start at oper_input_base() and count operands |
| 20406 | unsigned idx0 = 1; |
| 20407 | unsigned idx1 = 1; // dst |
| 20408 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shuffle |
| 20409 | st->print_raw("vector_rearrange "); |
| 20410 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 20411 | st->print_raw(", "); |
| 20412 | opnd_array(2)->ext_format(ra, this,idx2, st); // shuffle |
| 20413 | st->print_raw(", "); |
| 20414 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 20415 | } |
| 20416 | #endif |
| 20417 | #ifndef PRODUCT |
| 20418 | void loadShuffleI_avxNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 20419 | // Start at oper_input_base() and count operands |
| 20420 | unsigned idx0 = 1; |
| 20421 | unsigned idx1 = 1; // src |
| 20422 | st->print_raw("vector_load_shuffle "); |
| 20423 | opnd_array(0)->int_format(ra, this, st); // dst |
| 20424 | st->print_raw(", "); |
| 20425 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 20426 | } |
| 20427 | #endif |
| 20428 | #ifndef PRODUCT |
| 20429 | void rearrangeI_avxNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 20430 | // Start at oper_input_base() and count operands |
| 20431 | unsigned idx0 = 1; |
| 20432 | unsigned idx1 = 1; // src |
| 20433 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shuffle |
| 20434 | st->print_raw("vector_rearrange "); |
| 20435 | opnd_array(0)->int_format(ra, this, st); // dst |
| 20436 | st->print_raw(", "); |
| 20437 | opnd_array(2)->ext_format(ra, this,idx2, st); // shuffle |
| 20438 | st->print_raw(", "); |
| 20439 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 20440 | } |
| 20441 | #endif |
| 20442 | #ifndef PRODUCT |
| 20443 | void loadShuffleLNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 20444 | // Start at oper_input_base() and count operands |
| 20445 | unsigned idx0 = 1; |
| 20446 | unsigned idx1 = 1; // src |
| 20447 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst |
| 20448 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp |
| 20449 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // scratch |
| 20450 | st->print_raw("vector_load_shuffle "); |
| 20451 | opnd_array(2)->ext_format(ra, this,idx2, st); // dst |
| 20452 | st->print_raw(", "); |
| 20453 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 20454 | st->print_raw("\t! using "); |
| 20455 | opnd_array(3)->ext_format(ra, this,idx3, st); // vtmp |
| 20456 | st->print_raw(" and "); |
| 20457 | opnd_array(4)->ext_format(ra, this,idx4, st); // scratch |
| 20458 | st->print_raw(" as TEMP"); |
| 20459 | } |
| 20460 | #endif |
| 20461 | #ifndef PRODUCT |
| 20462 | void rearrangeLNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 20463 | // Start at oper_input_base() and count operands |
| 20464 | unsigned idx0 = 1; |
| 20465 | unsigned idx1 = 1; // src |
| 20466 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shuffle |
| 20467 | st->print_raw("vector_rearrange "); |
| 20468 | opnd_array(0)->int_format(ra, this, st); // dst |
| 20469 | st->print_raw(", "); |
| 20470 | opnd_array(2)->ext_format(ra, this,idx2, st); // shuffle |
| 20471 | st->print_raw(", "); |
| 20472 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 20473 | } |
| 20474 | #endif |
| 20475 | #ifndef PRODUCT |
| 20476 | void loadShuffleL_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 20477 | // Start at oper_input_base() and count operands |
| 20478 | unsigned idx0 = 1; |
| 20479 | unsigned idx1 = 1; // src |
| 20480 | st->print_raw("vector_load_shuffle "); |
| 20481 | opnd_array(0)->int_format(ra, this, st); // dst |
| 20482 | st->print_raw(", "); |
| 20483 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 20484 | } |
| 20485 | #endif |
| 20486 | #ifndef PRODUCT |
| 20487 | void rearrangeL_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 20488 | // Start at oper_input_base() and count operands |
| 20489 | unsigned idx0 = 1; |
| 20490 | unsigned idx1 = 1; // src |
| 20491 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shuffle |
| 20492 | st->print_raw("vector_rearrange "); |
| 20493 | opnd_array(0)->int_format(ra, this, st); // dst |
| 20494 | st->print_raw(", "); |
| 20495 | opnd_array(2)->ext_format(ra, this,idx2, st); // shuffle |
| 20496 | st->print_raw(", "); |
| 20497 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 20498 | } |
| 20499 | #endif |
| 20500 | #ifndef PRODUCT |
| 20501 | void vfmaF_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 20502 | // Start at oper_input_base() and count operands |
| 20503 | unsigned idx0 = 1; |
| 20504 | unsigned idx1 = 1; // c |
| 20505 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // a |
| 20506 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // b |
| 20507 | st->print_raw("fmaps "); |
| 20508 | opnd_array(2)->ext_format(ra, this,idx2, st); // a |
| 20509 | st->print_raw(","); |
| 20510 | opnd_array(3)->ext_format(ra, this,idx3, st); // b |
| 20511 | st->print_raw(","); |
| 20512 | opnd_array(1)->ext_format(ra, this,idx1, st); // c |
| 20513 | st->print_raw("\t# "); |
| 20514 | opnd_array(1)->ext_format(ra, this,idx1, st); // c |
| 20515 | st->print_raw(" = "); |
| 20516 | opnd_array(2)->ext_format(ra, this,idx2, st); // a |
| 20517 | st->print_raw(" * "); |
| 20518 | opnd_array(3)->ext_format(ra, this,idx3, st); // b |
| 20519 | st->print_raw(" + "); |
| 20520 | opnd_array(1)->ext_format(ra, this,idx1, st); // c |
| 20521 | st->print_raw(" fma packedF"); |
| 20522 | } |
| 20523 | #endif |
| 20524 | #ifndef PRODUCT |
| 20525 | void vfmaF_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 20526 | // Start at oper_input_base() and count operands |
| 20527 | unsigned idx0 = 2; |
| 20528 | unsigned idx1 = 2; // c |
| 20529 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // a |
| 20530 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // b |
| 20531 | st->print_raw("fmaps "); |
| 20532 | opnd_array(2)->ext_format(ra, this,idx2, st); // a |
| 20533 | st->print_raw(","); |
| 20534 | opnd_array(3)->ext_format(ra, this,idx3, st); // b |
| 20535 | st->print_raw(","); |
| 20536 | opnd_array(1)->ext_format(ra, this,idx1, st); // c |
| 20537 | st->print_raw("\t# "); |
| 20538 | opnd_array(1)->ext_format(ra, this,idx1, st); // c |
| 20539 | st->print_raw(" = "); |
| 20540 | opnd_array(2)->ext_format(ra, this,idx2, st); // a |
| 20541 | st->print_raw(" * "); |
| 20542 | opnd_array(3)->ext_format(ra, this,idx3, st); // b |
| 20543 | st->print_raw(" + "); |
| 20544 | opnd_array(1)->ext_format(ra, this,idx1, st); // c |
| 20545 | st->print_raw(" fma packedF"); |
| 20546 | } |
| 20547 | #endif |
| 20548 | #ifndef PRODUCT |
| 20549 | void vfmaD_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 20550 | // Start at oper_input_base() and count operands |
| 20551 | unsigned idx0 = 1; |
| 20552 | unsigned idx1 = 1; // c |
| 20553 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // a |
| 20554 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // b |
| 20555 | st->print_raw("fmapd "); |
| 20556 | opnd_array(2)->ext_format(ra, this,idx2, st); // a |
| 20557 | st->print_raw(","); |
| 20558 | opnd_array(3)->ext_format(ra, this,idx3, st); // b |
| 20559 | st->print_raw(","); |
| 20560 | opnd_array(1)->ext_format(ra, this,idx1, st); // c |
| 20561 | st->print_raw("\t# "); |
| 20562 | opnd_array(1)->ext_format(ra, this,idx1, st); // c |
| 20563 | st->print_raw(" = "); |
| 20564 | opnd_array(2)->ext_format(ra, this,idx2, st); // a |
| 20565 | st->print_raw(" * "); |
| 20566 | opnd_array(3)->ext_format(ra, this,idx3, st); // b |
| 20567 | st->print_raw(" + "); |
| 20568 | opnd_array(1)->ext_format(ra, this,idx1, st); // c |
| 20569 | st->print_raw(" fma packedD"); |
| 20570 | } |
| 20571 | #endif |
| 20572 | #ifndef PRODUCT |
| 20573 | void vfmaD_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 20574 | // Start at oper_input_base() and count operands |
| 20575 | unsigned idx0 = 2; |
| 20576 | unsigned idx1 = 2; // c |
| 20577 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // a |
| 20578 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // b |
| 20579 | st->print_raw("fmapd "); |
| 20580 | opnd_array(2)->ext_format(ra, this,idx2, st); // a |
| 20581 | st->print_raw(","); |
| 20582 | opnd_array(3)->ext_format(ra, this,idx3, st); // b |
| 20583 | st->print_raw(","); |
| 20584 | opnd_array(1)->ext_format(ra, this,idx1, st); // c |
| 20585 | st->print_raw("\t# "); |
| 20586 | opnd_array(1)->ext_format(ra, this,idx1, st); // c |
| 20587 | st->print_raw(" = "); |
| 20588 | opnd_array(2)->ext_format(ra, this,idx2, st); // a |
| 20589 | st->print_raw(" * "); |
| 20590 | opnd_array(3)->ext_format(ra, this,idx3, st); // b |
| 20591 | st->print_raw(" + "); |
| 20592 | opnd_array(1)->ext_format(ra, this,idx1, st); // c |
| 20593 | st->print_raw(" fma packedD"); |
| 20594 | } |
| 20595 | #endif |
| 20596 | #ifndef PRODUCT |
| 20597 | void vmuladdS2I_reg_sseNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 20598 | // Start at oper_input_base() and count operands |
| 20599 | unsigned idx0 = 1; |
| 20600 | unsigned idx1 = 1; // dst |
| 20601 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src1 |
| 20602 | st->print_raw("pmaddwd "); |
| 20603 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 20604 | st->print_raw(","); |
| 20605 | opnd_array(2)->ext_format(ra, this,idx2, st); // src1 |
| 20606 | st->print_raw("\t! muladd packedStoI"); |
| 20607 | } |
| 20608 | #endif |
| 20609 | #ifndef PRODUCT |
| 20610 | void vmuladdS2I_reg_avxNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 20611 | // Start at oper_input_base() and count operands |
| 20612 | unsigned idx0 = 1; |
| 20613 | unsigned idx1 = 1; // src1 |
| 20614 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 20615 | st->print_raw("vpmaddwd "); |
| 20616 | opnd_array(0)->int_format(ra, this, st); // dst |
| 20617 | st->print_raw(","); |
| 20618 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 20619 | st->print_raw(","); |
| 20620 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 20621 | st->print_raw("\t! muladd packedStoI"); |
| 20622 | } |
| 20623 | #endif |
| 20624 | #ifndef PRODUCT |
| 20625 | void vmuladdaddS2I_regNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 20626 | // Start at oper_input_base() and count operands |
| 20627 | unsigned idx0 = 1; |
| 20628 | unsigned idx1 = 1; // src1 |
| 20629 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 20630 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 20631 | st->print_raw("evpdpwssd "); |
| 20632 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 20633 | st->print_raw(","); |
| 20634 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 20635 | st->print_raw(","); |
| 20636 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 20637 | st->print_raw("\t! muladdadd packedStoI"); |
| 20638 | } |
| 20639 | #endif |
| 20640 | #ifndef PRODUCT |
| 20641 | void vmuladdaddS2I_reg_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 20642 | // Start at oper_input_base() and count operands |
| 20643 | unsigned idx0 = 1; |
| 20644 | unsigned idx1 = 1; // dst |
| 20645 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src1 |
| 20646 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // src2 |
| 20647 | st->print_raw("evpdpwssd "); |
| 20648 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 20649 | st->print_raw(","); |
| 20650 | opnd_array(2)->ext_format(ra, this,idx2, st); // src1 |
| 20651 | st->print_raw(","); |
| 20652 | opnd_array(3)->ext_format(ra, this,idx3, st); // src2 |
| 20653 | st->print_raw("\t! muladdadd packedStoI"); |
| 20654 | } |
| 20655 | #endif |
| 20656 | #ifndef PRODUCT |
| 20657 | void vpopcountINode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 20658 | // Start at oper_input_base() and count operands |
| 20659 | unsigned idx0 = 1; |
| 20660 | unsigned idx1 = 1; // src |
| 20661 | st->print_raw("vpopcntd "); |
| 20662 | opnd_array(0)->int_format(ra, this, st); // dst |
| 20663 | st->print_raw(","); |
| 20664 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 20665 | st->print_raw("\t! vector popcount packedI"); |
| 20666 | } |
| 20667 | #endif |
| 20668 | #ifndef PRODUCT |
| 20669 | void vpternlogNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 20670 | // Start at oper_input_base() and count operands |
| 20671 | unsigned idx0 = 1; |
| 20672 | unsigned idx1 = 1; // dst |
| 20673 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 20674 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // src3 |
| 20675 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // func |
| 20676 | st->print_raw("vpternlogd "); |
| 20677 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 20678 | st->print_raw(","); |
| 20679 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 20680 | st->print_raw(","); |
| 20681 | opnd_array(3)->ext_format(ra, this,idx3, st); // src3 |
| 20682 | st->print_raw(","); |
| 20683 | opnd_array(4)->ext_format(ra, this,idx4, st); // func |
| 20684 | st->print_raw("\t! vector ternary logic"); |
| 20685 | } |
| 20686 | #endif |
| 20687 | #ifndef PRODUCT |
| 20688 | void vpternlog_memNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 20689 | // Start at oper_input_base() and count operands |
| 20690 | unsigned idx0 = 2; |
| 20691 | unsigned idx1 = 2; // dst |
| 20692 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 20693 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // src3 |
| 20694 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // func |
| 20695 | st->print_raw("vpternlogd "); |
| 20696 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 20697 | st->print_raw(","); |
| 20698 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 20699 | st->print_raw(","); |
| 20700 | opnd_array(3)->ext_format(ra, this,idx3, st); // src3 |
| 20701 | st->print_raw(","); |
| 20702 | opnd_array(4)->ext_format(ra, this,idx4, st); // func |
| 20703 | st->print_raw("\t! vector ternary logic"); |
| 20704 | } |
| 20705 | #endif |
| 20706 | #ifndef PRODUCT |
| 20707 | void vprotate_immI8Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 20708 | // Start at oper_input_base() and count operands |
| 20709 | unsigned idx0 = 1; |
| 20710 | unsigned idx1 = 1; // src |
| 20711 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 20712 | st->print_raw("vprotate_imm8 "); |
| 20713 | opnd_array(0)->int_format(ra, this, st); // dst |
| 20714 | st->print_raw(","); |
| 20715 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 20716 | st->print_raw(","); |
| 20717 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 20718 | st->print_raw("\t! vector rotate"); |
| 20719 | } |
| 20720 | #endif |
| 20721 | #ifndef PRODUCT |
| 20722 | void vprotate_immI8_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 20723 | // Start at oper_input_base() and count operands |
| 20724 | unsigned idx0 = 1; |
| 20725 | unsigned idx1 = 1; // src |
| 20726 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 20727 | st->print_raw("vprotate_imm8 "); |
| 20728 | opnd_array(0)->int_format(ra, this, st); // dst |
| 20729 | st->print_raw(","); |
| 20730 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 20731 | st->print_raw(","); |
| 20732 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 20733 | st->print_raw("\t! vector rotate"); |
| 20734 | } |
| 20735 | #endif |
| 20736 | #ifndef PRODUCT |
| 20737 | void vprorateNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 20738 | // Start at oper_input_base() and count operands |
| 20739 | unsigned idx0 = 1; |
| 20740 | unsigned idx1 = 1; // src |
| 20741 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 20742 | st->print_raw("vprotate "); |
| 20743 | opnd_array(0)->int_format(ra, this, st); // dst |
| 20744 | st->print_raw(","); |
| 20745 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 20746 | st->print_raw(","); |
| 20747 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 20748 | st->print_raw("\t! vector rotate"); |
| 20749 | } |
| 20750 | #endif |
| 20751 | #ifndef PRODUCT |
| 20752 | void vprorate_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 20753 | // Start at oper_input_base() and count operands |
| 20754 | unsigned idx0 = 1; |
| 20755 | unsigned idx1 = 1; // src |
| 20756 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 20757 | st->print_raw("vprotate "); |
| 20758 | opnd_array(0)->int_format(ra, this, st); // dst |
| 20759 | st->print_raw(","); |
| 20760 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 20761 | st->print_raw(","); |
| 20762 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 20763 | st->print_raw("\t! vector rotate"); |
| 20764 | } |
| 20765 | #endif |
| 20766 | #ifndef PRODUCT |
| 20767 | void vmask_cmp_nodeNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 20768 | // Start at oper_input_base() and count operands |
| 20769 | unsigned idx0 = 1; |
| 20770 | unsigned idx1 = 1; // src1 |
| 20771 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 20772 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 20773 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // dst |
| 20774 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // ktmp1 |
| 20775 | unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // ktmp2 |
| 20776 | st->print_raw("vector_mask_cmp "); |
| 20777 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 20778 | st->print_raw(", "); |
| 20779 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 20780 | st->print_raw(", "); |
| 20781 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 20782 | st->print_raw(" \t! vector mask comparison"); |
| 20783 | } |
| 20784 | #endif |
| 20785 | #ifndef PRODUCT |
| 20786 | void vmasked_load64Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 20787 | // Start at oper_input_base() and count operands |
| 20788 | unsigned idx0 = 2; |
| 20789 | unsigned idx1 = 2; // mem |
| 20790 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask |
| 20791 | st->print_raw("vector_masked_load "); |
| 20792 | opnd_array(0)->int_format(ra, this, st); // dst |
| 20793 | st->print_raw(", "); |
| 20794 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 20795 | st->print_raw(", "); |
| 20796 | opnd_array(2)->ext_format(ra, this,idx2, st); // mask |
| 20797 | st->print_raw(" \t! vector masked copy"); |
| 20798 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 20799 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 20800 | st->print(" ! Field: "); |
| 20801 | if (f->is_volatile()) |
| 20802 | st->print("volatile "); |
| 20803 | f->holder()->name()->print_symbol_on(st); |
| 20804 | st->print("."); |
| 20805 | f->name()->print_symbol_on(st); |
| 20806 | if (f->is_constant()) |
| 20807 | st->print(" (constant)"); |
| 20808 | } else { |
| 20809 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 20810 | st->print(" volatile!"); |
| 20811 | } |
| 20812 | } |
| 20813 | #endif |
| 20814 | #ifndef PRODUCT |
| 20815 | void vmask_genNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 20816 | // Start at oper_input_base() and count operands |
| 20817 | unsigned idx0 = 1; |
| 20818 | unsigned idx1 = 1; // len |
| 20819 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // temp |
| 20820 | st->print_raw("vector_mask_gen32 "); |
| 20821 | opnd_array(0)->int_format(ra, this, st); // dst |
| 20822 | st->print_raw(", "); |
| 20823 | opnd_array(1)->ext_format(ra, this,idx1, st); // len |
| 20824 | st->print_raw(" \t! vector mask generator"); |
| 20825 | } |
| 20826 | #endif |
| 20827 | #ifndef PRODUCT |
| 20828 | void vmask_gen_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 20829 | // Start at oper_input_base() and count operands |
| 20830 | unsigned idx0 = 1; |
| 20831 | unsigned idx1 = 1; // len |
| 20832 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // temp |
| 20833 | st->print_raw("vector_mask_gen "); |
| 20834 | opnd_array(1)->ext_format(ra, this,idx1, st); // len |
| 20835 | st->print_raw(" \t! vector mask generator"); |
| 20836 | } |
| 20837 | #endif |
| 20838 | #ifndef PRODUCT |
| 20839 | void vmasked_store64Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 20840 | // Start at oper_input_base() and count operands |
| 20841 | unsigned idx0 = 2; |
| 20842 | unsigned idx1 = 2; // mem |
| 20843 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src |
| 20844 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 20845 | st->print_raw("vector_masked_store "); |
| 20846 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 20847 | st->print_raw(", "); |
| 20848 | opnd_array(2)->ext_format(ra, this,idx2, st); // src |
| 20849 | st->print_raw(", "); |
| 20850 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 20851 | st->print_raw(" \t! vector masked store"); |
| 20852 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 20853 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 20854 | st->print(" ! Field: "); |
| 20855 | if (f->is_volatile()) |
| 20856 | st->print("volatile "); |
| 20857 | f->holder()->name()->print_symbol_on(st); |
| 20858 | st->print("."); |
| 20859 | f->name()->print_symbol_on(st); |
| 20860 | if (f->is_constant()) |
| 20861 | st->print(" (constant)"); |
| 20862 | } else { |
| 20863 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 20864 | st->print(" volatile!"); |
| 20865 | } |
| 20866 | } |
| 20867 | #endif |
| 20868 | #ifndef PRODUCT |
| 20869 | void vmask_tolong_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 20870 | // Start at oper_input_base() and count operands |
| 20871 | unsigned idx0 = 1; |
| 20872 | unsigned idx1 = 1; // mask |
| 20873 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst |
| 20874 | st->print_raw("vector_tolong_evex "); |
| 20875 | opnd_array(2)->ext_format(ra, this,idx2, st); // dst |
| 20876 | st->print_raw(", "); |
| 20877 | opnd_array(1)->ext_format(ra, this,idx1, st); // mask |
| 20878 | st->print_raw(" \t! vector mask tolong"); |
| 20879 | } |
| 20880 | #endif |
| 20881 | #ifndef PRODUCT |
| 20882 | void vmask_tolong_boolNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 20883 | // Start at oper_input_base() and count operands |
| 20884 | unsigned idx0 = 1; |
| 20885 | unsigned idx1 = 1; // mask |
| 20886 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst |
| 20887 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // xtmp |
| 20888 | st->print_raw("vector_tolong_bool "); |
| 20889 | opnd_array(2)->ext_format(ra, this,idx2, st); // dst |
| 20890 | st->print_raw(", "); |
| 20891 | opnd_array(1)->ext_format(ra, this,idx1, st); // mask |
| 20892 | st->print_raw(" \t! using "); |
| 20893 | opnd_array(3)->ext_format(ra, this,idx3, st); // xtmp |
| 20894 | st->print_raw(" as TEMP"); |
| 20895 | } |
| 20896 | #endif |
| 20897 | #ifndef PRODUCT |
| 20898 | void vmask_tolong_avxNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 20899 | // Start at oper_input_base() and count operands |
| 20900 | unsigned idx0 = 1; |
| 20901 | unsigned idx1 = 1; // mask |
| 20902 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // size |
| 20903 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 20904 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // xtmp |
| 20905 | st->print_raw("vector_tolong_avx "); |
| 20906 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 20907 | st->print_raw(", "); |
| 20908 | opnd_array(1)->ext_format(ra, this,idx1, st); // mask |
| 20909 | st->print_raw(" \t! using "); |
| 20910 | opnd_array(4)->ext_format(ra, this,idx4, st); // xtmp |
| 20911 | st->print_raw(" as TEMP"); |
| 20912 | } |
| 20913 | #endif |
| 20914 | #ifndef PRODUCT |
| 20915 | void vmask_truecount_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 20916 | // Start at oper_input_base() and count operands |
| 20917 | unsigned idx0 = 1; |
| 20918 | unsigned idx1 = 1; // mask |
| 20919 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst |
| 20920 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp |
| 20921 | st->print_raw("vector_truecount_evex "); |
| 20922 | opnd_array(2)->ext_format(ra, this,idx2, st); // dst |
| 20923 | st->print_raw(", "); |
| 20924 | opnd_array(1)->ext_format(ra, this,idx1, st); // mask |
| 20925 | st->print_raw(" \t! using "); |
| 20926 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp |
| 20927 | st->print_raw(" as TEMP"); |
| 20928 | } |
| 20929 | #endif |
| 20930 | #ifndef PRODUCT |
| 20931 | void vmask_truecount_boolNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 20932 | // Start at oper_input_base() and count operands |
| 20933 | unsigned idx0 = 1; |
| 20934 | unsigned idx1 = 1; // mask |
| 20935 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst |
| 20936 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp |
| 20937 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // xtmp |
| 20938 | st->print_raw("vector_truecount_bool "); |
| 20939 | opnd_array(2)->ext_format(ra, this,idx2, st); // dst |
| 20940 | st->print_raw(", "); |
| 20941 | opnd_array(1)->ext_format(ra, this,idx1, st); // mask |
| 20942 | st->print_raw(" \t! using "); |
| 20943 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp |
| 20944 | st->print_raw(", "); |
| 20945 | opnd_array(4)->ext_format(ra, this,idx4, st); // xtmp |
| 20946 | st->print_raw(" as TEMP"); |
| 20947 | } |
| 20948 | #endif |
| 20949 | #ifndef PRODUCT |
| 20950 | void vmask_truecount_avxNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 20951 | // Start at oper_input_base() and count operands |
| 20952 | unsigned idx0 = 1; |
| 20953 | unsigned idx1 = 1; // mask |
| 20954 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // size |
| 20955 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 20956 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp |
| 20957 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // xtmp |
| 20958 | st->print_raw("vector_truecount_avx "); |
| 20959 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 20960 | st->print_raw(", "); |
| 20961 | opnd_array(1)->ext_format(ra, this,idx1, st); // mask |
| 20962 | st->print_raw(" \t! using "); |
| 20963 | opnd_array(4)->ext_format(ra, this,idx4, st); // tmp |
| 20964 | st->print_raw(", "); |
| 20965 | opnd_array(5)->ext_format(ra, this,idx5, st); // xtmp |
| 20966 | st->print_raw(" as TEMP"); |
| 20967 | } |
| 20968 | #endif |
| 20969 | #ifndef PRODUCT |
| 20970 | void vmask_first_or_last_true_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 20971 | // Start at oper_input_base() and count operands |
| 20972 | unsigned idx0 = 1; |
| 20973 | unsigned idx1 = 1; // mask |
| 20974 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst |
| 20975 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp |
| 20976 | st->print_raw("vector_mask_first_or_last_true_evex "); |
| 20977 | opnd_array(2)->ext_format(ra, this,idx2, st); // dst |
| 20978 | st->print_raw(", "); |
| 20979 | opnd_array(1)->ext_format(ra, this,idx1, st); // mask |
| 20980 | st->print_raw(" \t! using "); |
| 20981 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp |
| 20982 | st->print_raw(" as TEMP"); |
| 20983 | } |
| 20984 | #endif |
| 20985 | #ifndef PRODUCT |
| 20986 | void vmask_first_or_last_true_evex_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 20987 | // Start at oper_input_base() and count operands |
| 20988 | unsigned idx0 = 1; |
| 20989 | unsigned idx1 = 1; // mask |
| 20990 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst |
| 20991 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp |
| 20992 | st->print_raw("vector_mask_first_or_last_true_evex "); |
| 20993 | opnd_array(2)->ext_format(ra, this,idx2, st); // dst |
| 20994 | st->print_raw(", "); |
| 20995 | opnd_array(1)->ext_format(ra, this,idx1, st); // mask |
| 20996 | st->print_raw(" \t! using "); |
| 20997 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp |
| 20998 | st->print_raw(" as TEMP"); |
| 20999 | } |
| 21000 | #endif |
| 21001 | #ifndef PRODUCT |
| 21002 | void vmask_first_or_last_true_boolNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 21003 | // Start at oper_input_base() and count operands |
| 21004 | unsigned idx0 = 1; |
| 21005 | unsigned idx1 = 1; // mask |
| 21006 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst |
| 21007 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp |
| 21008 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // xtmp |
| 21009 | st->print_raw("vector_mask_first_or_last_true_bool "); |
| 21010 | opnd_array(2)->ext_format(ra, this,idx2, st); // dst |
| 21011 | st->print_raw(", "); |
| 21012 | opnd_array(1)->ext_format(ra, this,idx1, st); // mask |
| 21013 | st->print_raw(" \t! using "); |
| 21014 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp |
| 21015 | st->print_raw(", "); |
| 21016 | opnd_array(4)->ext_format(ra, this,idx4, st); // xtmp |
| 21017 | st->print_raw(" as TEMP"); |
| 21018 | } |
| 21019 | #endif |
| 21020 | #ifndef PRODUCT |
| 21021 | void vmask_first_or_last_true_bool_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 21022 | // Start at oper_input_base() and count operands |
| 21023 | unsigned idx0 = 1; |
| 21024 | unsigned idx1 = 1; // mask |
| 21025 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst |
| 21026 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp |
| 21027 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // xtmp |
| 21028 | st->print_raw("vector_mask_first_or_last_true_bool "); |
| 21029 | opnd_array(2)->ext_format(ra, this,idx2, st); // dst |
| 21030 | st->print_raw(", "); |
| 21031 | opnd_array(1)->ext_format(ra, this,idx1, st); // mask |
| 21032 | st->print_raw(" \t! using "); |
| 21033 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp |
| 21034 | st->print_raw(", "); |
| 21035 | opnd_array(4)->ext_format(ra, this,idx4, st); // xtmp |
| 21036 | st->print_raw(" as TEMP"); |
| 21037 | } |
| 21038 | #endif |
| 21039 | #ifndef PRODUCT |
| 21040 | void vmask_first_or_last_true_avxNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 21041 | // Start at oper_input_base() and count operands |
| 21042 | unsigned idx0 = 1; |
| 21043 | unsigned idx1 = 1; // mask |
| 21044 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // size |
| 21045 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 21046 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp |
| 21047 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // xtmp |
| 21048 | st->print_raw("vector_mask_first_or_last_true_avx "); |
| 21049 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 21050 | st->print_raw(", "); |
| 21051 | opnd_array(1)->ext_format(ra, this,idx1, st); // mask |
| 21052 | st->print_raw(" \t! using "); |
| 21053 | opnd_array(4)->ext_format(ra, this,idx4, st); // tmp |
| 21054 | st->print_raw(", "); |
| 21055 | opnd_array(5)->ext_format(ra, this,idx5, st); // xtmp |
| 21056 | st->print_raw(" as TEMP"); |
| 21057 | } |
| 21058 | #endif |
| 21059 | #ifndef PRODUCT |
| 21060 | void vmask_first_or_last_true_avx_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 21061 | // Start at oper_input_base() and count operands |
| 21062 | unsigned idx0 = 1; |
| 21063 | unsigned idx1 = 1; // mask |
| 21064 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // size |
| 21065 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 21066 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp |
| 21067 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // xtmp |
| 21068 | st->print_raw("vector_mask_first_or_last_true_avx "); |
| 21069 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 21070 | st->print_raw(", "); |
| 21071 | opnd_array(1)->ext_format(ra, this,idx1, st); // mask |
| 21072 | st->print_raw(" \t! using "); |
| 21073 | opnd_array(4)->ext_format(ra, this,idx4, st); // tmp |
| 21074 | st->print_raw(", "); |
| 21075 | opnd_array(5)->ext_format(ra, this,idx5, st); // xtmp |
| 21076 | st->print_raw(" as TEMP"); |
| 21077 | } |
| 21078 | #endif |
| 21079 | #ifndef PRODUCT |
| 21080 | void vadd_reg_maskedNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 21081 | // Start at oper_input_base() and count operands |
| 21082 | unsigned idx0 = 1; |
| 21083 | unsigned idx1 = 1; // dst |
| 21084 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 21085 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 21086 | st->print_raw("vpadd_masked "); |
| 21087 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21088 | st->print_raw(", "); |
| 21089 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21090 | st->print_raw(", "); |
| 21091 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 21092 | st->print_raw(", "); |
| 21093 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 21094 | st->print_raw("\t! add masked operation"); |
| 21095 | } |
| 21096 | #endif |
| 21097 | #ifndef PRODUCT |
| 21098 | void vadd_reg_masked_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 21099 | // Start at oper_input_base() and count operands |
| 21100 | unsigned idx0 = 1; |
| 21101 | unsigned idx1 = 1; // dst |
| 21102 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 21103 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 21104 | st->print_raw("vpadd_masked "); |
| 21105 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21106 | st->print_raw(", "); |
| 21107 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21108 | st->print_raw(", "); |
| 21109 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 21110 | st->print_raw(", "); |
| 21111 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 21112 | st->print_raw("\t! add masked operation"); |
| 21113 | } |
| 21114 | #endif |
| 21115 | #ifndef PRODUCT |
| 21116 | void vadd_reg_masked_1Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 21117 | // Start at oper_input_base() and count operands |
| 21118 | unsigned idx0 = 1; |
| 21119 | unsigned idx1 = 1; // dst |
| 21120 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 21121 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 21122 | st->print_raw("vpadd_masked "); |
| 21123 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21124 | st->print_raw(", "); |
| 21125 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21126 | st->print_raw(", "); |
| 21127 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 21128 | st->print_raw(", "); |
| 21129 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 21130 | st->print_raw("\t! add masked operation"); |
| 21131 | } |
| 21132 | #endif |
| 21133 | #ifndef PRODUCT |
| 21134 | void vadd_reg_masked_2Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 21135 | // Start at oper_input_base() and count operands |
| 21136 | unsigned idx0 = 1; |
| 21137 | unsigned idx1 = 1; // dst |
| 21138 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 21139 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 21140 | st->print_raw("vpadd_masked "); |
| 21141 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21142 | st->print_raw(", "); |
| 21143 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21144 | st->print_raw(", "); |
| 21145 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 21146 | st->print_raw(", "); |
| 21147 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 21148 | st->print_raw("\t! add masked operation"); |
| 21149 | } |
| 21150 | #endif |
| 21151 | #ifndef PRODUCT |
| 21152 | void vadd_reg_masked_3Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 21153 | // Start at oper_input_base() and count operands |
| 21154 | unsigned idx0 = 1; |
| 21155 | unsigned idx1 = 1; // dst |
| 21156 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 21157 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 21158 | st->print_raw("vpadd_masked "); |
| 21159 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21160 | st->print_raw(", "); |
| 21161 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21162 | st->print_raw(", "); |
| 21163 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 21164 | st->print_raw(", "); |
| 21165 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 21166 | st->print_raw("\t! add masked operation"); |
| 21167 | } |
| 21168 | #endif |
| 21169 | #ifndef PRODUCT |
| 21170 | void vadd_reg_masked_4Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 21171 | // Start at oper_input_base() and count operands |
| 21172 | unsigned idx0 = 1; |
| 21173 | unsigned idx1 = 1; // dst |
| 21174 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 21175 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 21176 | st->print_raw("vpadd_masked "); |
| 21177 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21178 | st->print_raw(", "); |
| 21179 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21180 | st->print_raw(", "); |
| 21181 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 21182 | st->print_raw(", "); |
| 21183 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 21184 | st->print_raw("\t! add masked operation"); |
| 21185 | } |
| 21186 | #endif |
| 21187 | #ifndef PRODUCT |
| 21188 | void vadd_mem_maskedNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 21189 | // Start at oper_input_base() and count operands |
| 21190 | unsigned idx0 = 2; |
| 21191 | unsigned idx1 = 2; // dst |
| 21192 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 21193 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 21194 | st->print_raw("vpadd_masked "); |
| 21195 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21196 | st->print_raw(", "); |
| 21197 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21198 | st->print_raw(", "); |
| 21199 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 21200 | st->print_raw(", "); |
| 21201 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 21202 | st->print_raw("\t! add masked operation"); |
| 21203 | } |
| 21204 | #endif |
| 21205 | #ifndef PRODUCT |
| 21206 | void vadd_mem_masked_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 21207 | // Start at oper_input_base() and count operands |
| 21208 | unsigned idx0 = 2; |
| 21209 | unsigned idx1 = 2; // dst |
| 21210 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 21211 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 21212 | st->print_raw("vpadd_masked "); |
| 21213 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21214 | st->print_raw(", "); |
| 21215 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21216 | st->print_raw(", "); |
| 21217 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 21218 | st->print_raw(", "); |
| 21219 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 21220 | st->print_raw("\t! add masked operation"); |
| 21221 | } |
| 21222 | #endif |
| 21223 | #ifndef PRODUCT |
| 21224 | void vadd_mem_masked_1Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 21225 | // Start at oper_input_base() and count operands |
| 21226 | unsigned idx0 = 2; |
| 21227 | unsigned idx1 = 2; // dst |
| 21228 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 21229 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 21230 | st->print_raw("vpadd_masked "); |
| 21231 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21232 | st->print_raw(", "); |
| 21233 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21234 | st->print_raw(", "); |
| 21235 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 21236 | st->print_raw(", "); |
| 21237 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 21238 | st->print_raw("\t! add masked operation"); |
| 21239 | } |
| 21240 | #endif |
| 21241 | #ifndef PRODUCT |
| 21242 | void vadd_mem_masked_2Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 21243 | // Start at oper_input_base() and count operands |
| 21244 | unsigned idx0 = 2; |
| 21245 | unsigned idx1 = 2; // dst |
| 21246 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 21247 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 21248 | st->print_raw("vpadd_masked "); |
| 21249 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21250 | st->print_raw(", "); |
| 21251 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21252 | st->print_raw(", "); |
| 21253 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 21254 | st->print_raw(", "); |
| 21255 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 21256 | st->print_raw("\t! add masked operation"); |
| 21257 | } |
| 21258 | #endif |
| 21259 | #ifndef PRODUCT |
| 21260 | void vadd_mem_masked_3Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 21261 | // Start at oper_input_base() and count operands |
| 21262 | unsigned idx0 = 2; |
| 21263 | unsigned idx1 = 2; // dst |
| 21264 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 21265 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 21266 | st->print_raw("vpadd_masked "); |
| 21267 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21268 | st->print_raw(", "); |
| 21269 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21270 | st->print_raw(", "); |
| 21271 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 21272 | st->print_raw(", "); |
| 21273 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 21274 | st->print_raw("\t! add masked operation"); |
| 21275 | } |
| 21276 | #endif |
| 21277 | #ifndef PRODUCT |
| 21278 | void vadd_mem_masked_4Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 21279 | // Start at oper_input_base() and count operands |
| 21280 | unsigned idx0 = 2; |
| 21281 | unsigned idx1 = 2; // dst |
| 21282 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 21283 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 21284 | st->print_raw("vpadd_masked "); |
| 21285 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21286 | st->print_raw(", "); |
| 21287 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21288 | st->print_raw(", "); |
| 21289 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 21290 | st->print_raw(", "); |
| 21291 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 21292 | st->print_raw("\t! add masked operation"); |
| 21293 | } |
| 21294 | #endif |
| 21295 | #ifndef PRODUCT |
| 21296 | void vxor_reg_maskedNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 21297 | // Start at oper_input_base() and count operands |
| 21298 | unsigned idx0 = 1; |
| 21299 | unsigned idx1 = 1; // dst |
| 21300 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 21301 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 21302 | st->print_raw("vxor_masked "); |
| 21303 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21304 | st->print_raw(", "); |
| 21305 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21306 | st->print_raw(", "); |
| 21307 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 21308 | st->print_raw(", "); |
| 21309 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 21310 | st->print_raw("\t! xor masked operation"); |
| 21311 | } |
| 21312 | #endif |
| 21313 | #ifndef PRODUCT |
| 21314 | void vxor_mem_maskedNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 21315 | // Start at oper_input_base() and count operands |
| 21316 | unsigned idx0 = 2; |
| 21317 | unsigned idx1 = 2; // dst |
| 21318 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 21319 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 21320 | st->print_raw("vxor_masked "); |
| 21321 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21322 | st->print_raw(", "); |
| 21323 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21324 | st->print_raw(", "); |
| 21325 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 21326 | st->print_raw(", "); |
| 21327 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 21328 | st->print_raw("\t! xor masked operation"); |
| 21329 | } |
| 21330 | #endif |
| 21331 | #ifndef PRODUCT |
| 21332 | void vor_reg_maskedNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 21333 | // Start at oper_input_base() and count operands |
| 21334 | unsigned idx0 = 1; |
| 21335 | unsigned idx1 = 1; // dst |
| 21336 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 21337 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 21338 | st->print_raw("vor_masked "); |
| 21339 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21340 | st->print_raw(", "); |
| 21341 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21342 | st->print_raw(", "); |
| 21343 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 21344 | st->print_raw(", "); |
| 21345 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 21346 | st->print_raw("\t! or masked operation"); |
| 21347 | } |
| 21348 | #endif |
| 21349 | #ifndef PRODUCT |
| 21350 | void vor_mem_maskedNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 21351 | // Start at oper_input_base() and count operands |
| 21352 | unsigned idx0 = 2; |
| 21353 | unsigned idx1 = 2; // dst |
| 21354 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 21355 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 21356 | st->print_raw("vor_masked "); |
| 21357 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21358 | st->print_raw(", "); |
| 21359 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21360 | st->print_raw(", "); |
| 21361 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 21362 | st->print_raw(", "); |
| 21363 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 21364 | st->print_raw("\t! or masked operation"); |
| 21365 | } |
| 21366 | #endif |
| 21367 | #ifndef PRODUCT |
| 21368 | void vand_reg_maskedNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 21369 | // Start at oper_input_base() and count operands |
| 21370 | unsigned idx0 = 1; |
| 21371 | unsigned idx1 = 1; // dst |
| 21372 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 21373 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 21374 | st->print_raw("vand_masked "); |
| 21375 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21376 | st->print_raw(", "); |
| 21377 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21378 | st->print_raw(", "); |
| 21379 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 21380 | st->print_raw(", "); |
| 21381 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 21382 | st->print_raw("\t! and masked operation"); |
| 21383 | } |
| 21384 | #endif |
| 21385 | #ifndef PRODUCT |
| 21386 | void vand_mem_maskedNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 21387 | // Start at oper_input_base() and count operands |
| 21388 | unsigned idx0 = 2; |
| 21389 | unsigned idx1 = 2; // dst |
| 21390 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 21391 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 21392 | st->print_raw("vand_masked "); |
| 21393 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21394 | st->print_raw(", "); |
| 21395 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21396 | st->print_raw(", "); |
| 21397 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 21398 | st->print_raw(", "); |
| 21399 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 21400 | st->print_raw("\t! and masked operation"); |
| 21401 | } |
| 21402 | #endif |
| 21403 | #ifndef PRODUCT |
| 21404 | void vsub_reg_maskedNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 21405 | // Start at oper_input_base() and count operands |
| 21406 | unsigned idx0 = 1; |
| 21407 | unsigned idx1 = 1; // dst |
| 21408 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 21409 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 21410 | st->print_raw("vpsub_masked "); |
| 21411 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21412 | st->print_raw(", "); |
| 21413 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21414 | st->print_raw(", "); |
| 21415 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 21416 | st->print_raw(", "); |
| 21417 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 21418 | st->print_raw("\t! sub masked operation"); |
| 21419 | } |
| 21420 | #endif |
| 21421 | #ifndef PRODUCT |
| 21422 | void vsub_reg_masked_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 21423 | // Start at oper_input_base() and count operands |
| 21424 | unsigned idx0 = 1; |
| 21425 | unsigned idx1 = 1; // dst |
| 21426 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 21427 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 21428 | st->print_raw("vpsub_masked "); |
| 21429 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21430 | st->print_raw(", "); |
| 21431 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21432 | st->print_raw(", "); |
| 21433 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 21434 | st->print_raw(", "); |
| 21435 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 21436 | st->print_raw("\t! sub masked operation"); |
| 21437 | } |
| 21438 | #endif |
| 21439 | #ifndef PRODUCT |
| 21440 | void vsub_reg_masked_1Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 21441 | // Start at oper_input_base() and count operands |
| 21442 | unsigned idx0 = 1; |
| 21443 | unsigned idx1 = 1; // dst |
| 21444 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 21445 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 21446 | st->print_raw("vpsub_masked "); |
| 21447 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21448 | st->print_raw(", "); |
| 21449 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21450 | st->print_raw(", "); |
| 21451 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 21452 | st->print_raw(", "); |
| 21453 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 21454 | st->print_raw("\t! sub masked operation"); |
| 21455 | } |
| 21456 | #endif |
| 21457 | #ifndef PRODUCT |
| 21458 | void vsub_reg_masked_2Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 21459 | // Start at oper_input_base() and count operands |
| 21460 | unsigned idx0 = 1; |
| 21461 | unsigned idx1 = 1; // dst |
| 21462 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 21463 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 21464 | st->print_raw("vpsub_masked "); |
| 21465 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21466 | st->print_raw(", "); |
| 21467 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21468 | st->print_raw(", "); |
| 21469 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 21470 | st->print_raw(", "); |
| 21471 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 21472 | st->print_raw("\t! sub masked operation"); |
| 21473 | } |
| 21474 | #endif |
| 21475 | #ifndef PRODUCT |
| 21476 | void vsub_reg_masked_3Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 21477 | // Start at oper_input_base() and count operands |
| 21478 | unsigned idx0 = 1; |
| 21479 | unsigned idx1 = 1; // dst |
| 21480 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 21481 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 21482 | st->print_raw("vpsub_masked "); |
| 21483 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21484 | st->print_raw(", "); |
| 21485 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21486 | st->print_raw(", "); |
| 21487 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 21488 | st->print_raw(", "); |
| 21489 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 21490 | st->print_raw("\t! sub masked operation"); |
| 21491 | } |
| 21492 | #endif |
| 21493 | #ifndef PRODUCT |
| 21494 | void vsub_reg_masked_4Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 21495 | // Start at oper_input_base() and count operands |
| 21496 | unsigned idx0 = 1; |
| 21497 | unsigned idx1 = 1; // dst |
| 21498 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 21499 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 21500 | st->print_raw("vpsub_masked "); |
| 21501 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21502 | st->print_raw(", "); |
| 21503 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21504 | st->print_raw(", "); |
| 21505 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 21506 | st->print_raw(", "); |
| 21507 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 21508 | st->print_raw("\t! sub masked operation"); |
| 21509 | } |
| 21510 | #endif |
| 21511 | #ifndef PRODUCT |
| 21512 | void vsub_mem_maskedNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 21513 | // Start at oper_input_base() and count operands |
| 21514 | unsigned idx0 = 2; |
| 21515 | unsigned idx1 = 2; // dst |
| 21516 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 21517 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 21518 | st->print_raw("vpsub_masked "); |
| 21519 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21520 | st->print_raw(", "); |
| 21521 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21522 | st->print_raw(", "); |
| 21523 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 21524 | st->print_raw(", "); |
| 21525 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 21526 | st->print_raw("\t! sub masked operation"); |
| 21527 | } |
| 21528 | #endif |
| 21529 | #ifndef PRODUCT |
| 21530 | void vsub_mem_masked_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 21531 | // Start at oper_input_base() and count operands |
| 21532 | unsigned idx0 = 2; |
| 21533 | unsigned idx1 = 2; // dst |
| 21534 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 21535 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 21536 | st->print_raw("vpsub_masked "); |
| 21537 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21538 | st->print_raw(", "); |
| 21539 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21540 | st->print_raw(", "); |
| 21541 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 21542 | st->print_raw(", "); |
| 21543 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 21544 | st->print_raw("\t! sub masked operation"); |
| 21545 | } |
| 21546 | #endif |
| 21547 | #ifndef PRODUCT |
| 21548 | void vsub_mem_masked_1Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 21549 | // Start at oper_input_base() and count operands |
| 21550 | unsigned idx0 = 2; |
| 21551 | unsigned idx1 = 2; // dst |
| 21552 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 21553 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 21554 | st->print_raw("vpsub_masked "); |
| 21555 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21556 | st->print_raw(", "); |
| 21557 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21558 | st->print_raw(", "); |
| 21559 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 21560 | st->print_raw(", "); |
| 21561 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 21562 | st->print_raw("\t! sub masked operation"); |
| 21563 | } |
| 21564 | #endif |
| 21565 | #ifndef PRODUCT |
| 21566 | void vsub_mem_masked_2Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 21567 | // Start at oper_input_base() and count operands |
| 21568 | unsigned idx0 = 2; |
| 21569 | unsigned idx1 = 2; // dst |
| 21570 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 21571 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 21572 | st->print_raw("vpsub_masked "); |
| 21573 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21574 | st->print_raw(", "); |
| 21575 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21576 | st->print_raw(", "); |
| 21577 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 21578 | st->print_raw(", "); |
| 21579 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 21580 | st->print_raw("\t! sub masked operation"); |
| 21581 | } |
| 21582 | #endif |
| 21583 | #ifndef PRODUCT |
| 21584 | void vsub_mem_masked_3Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 21585 | // Start at oper_input_base() and count operands |
| 21586 | unsigned idx0 = 2; |
| 21587 | unsigned idx1 = 2; // dst |
| 21588 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 21589 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 21590 | st->print_raw("vpsub_masked "); |
| 21591 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21592 | st->print_raw(", "); |
| 21593 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21594 | st->print_raw(", "); |
| 21595 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 21596 | st->print_raw(", "); |
| 21597 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 21598 | st->print_raw("\t! sub masked operation"); |
| 21599 | } |
| 21600 | #endif |
| 21601 | #ifndef PRODUCT |
| 21602 | void vsub_mem_masked_4Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 21603 | // Start at oper_input_base() and count operands |
| 21604 | unsigned idx0 = 2; |
| 21605 | unsigned idx1 = 2; // dst |
| 21606 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 21607 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 21608 | st->print_raw("vpsub_masked "); |
| 21609 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21610 | st->print_raw(", "); |
| 21611 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21612 | st->print_raw(", "); |
| 21613 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 21614 | st->print_raw(", "); |
| 21615 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 21616 | st->print_raw("\t! sub masked operation"); |
| 21617 | } |
| 21618 | #endif |
| 21619 | #ifndef PRODUCT |
| 21620 | void vmul_reg_maskedNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 21621 | // Start at oper_input_base() and count operands |
| 21622 | unsigned idx0 = 1; |
| 21623 | unsigned idx1 = 1; // dst |
| 21624 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 21625 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 21626 | st->print_raw("vpmul_masked "); |
| 21627 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21628 | st->print_raw(", "); |
| 21629 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21630 | st->print_raw(", "); |
| 21631 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 21632 | st->print_raw(", "); |
| 21633 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 21634 | st->print_raw("\t! mul masked operation"); |
| 21635 | } |
| 21636 | #endif |
| 21637 | #ifndef PRODUCT |
| 21638 | void vmul_reg_masked_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 21639 | // Start at oper_input_base() and count operands |
| 21640 | unsigned idx0 = 1; |
| 21641 | unsigned idx1 = 1; // dst |
| 21642 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 21643 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 21644 | st->print_raw("vpmul_masked "); |
| 21645 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21646 | st->print_raw(", "); |
| 21647 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21648 | st->print_raw(", "); |
| 21649 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 21650 | st->print_raw(", "); |
| 21651 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 21652 | st->print_raw("\t! mul masked operation"); |
| 21653 | } |
| 21654 | #endif |
| 21655 | #ifndef PRODUCT |
| 21656 | void vmul_reg_masked_1Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 21657 | // Start at oper_input_base() and count operands |
| 21658 | unsigned idx0 = 1; |
| 21659 | unsigned idx1 = 1; // dst |
| 21660 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 21661 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 21662 | st->print_raw("vpmul_masked "); |
| 21663 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21664 | st->print_raw(", "); |
| 21665 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21666 | st->print_raw(", "); |
| 21667 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 21668 | st->print_raw(", "); |
| 21669 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 21670 | st->print_raw("\t! mul masked operation"); |
| 21671 | } |
| 21672 | #endif |
| 21673 | #ifndef PRODUCT |
| 21674 | void vmul_reg_masked_2Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 21675 | // Start at oper_input_base() and count operands |
| 21676 | unsigned idx0 = 1; |
| 21677 | unsigned idx1 = 1; // dst |
| 21678 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 21679 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 21680 | st->print_raw("vpmul_masked "); |
| 21681 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21682 | st->print_raw(", "); |
| 21683 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21684 | st->print_raw(", "); |
| 21685 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 21686 | st->print_raw(", "); |
| 21687 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 21688 | st->print_raw("\t! mul masked operation"); |
| 21689 | } |
| 21690 | #endif |
| 21691 | #ifndef PRODUCT |
| 21692 | void vmul_reg_masked_3Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 21693 | // Start at oper_input_base() and count operands |
| 21694 | unsigned idx0 = 1; |
| 21695 | unsigned idx1 = 1; // dst |
| 21696 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 21697 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 21698 | st->print_raw("vpmul_masked "); |
| 21699 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21700 | st->print_raw(", "); |
| 21701 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21702 | st->print_raw(", "); |
| 21703 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 21704 | st->print_raw(", "); |
| 21705 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 21706 | st->print_raw("\t! mul masked operation"); |
| 21707 | } |
| 21708 | #endif |
| 21709 | #ifndef PRODUCT |
| 21710 | void vmul_mem_maskedNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 21711 | // Start at oper_input_base() and count operands |
| 21712 | unsigned idx0 = 2; |
| 21713 | unsigned idx1 = 2; // dst |
| 21714 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 21715 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 21716 | st->print_raw("vpmul_masked "); |
| 21717 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21718 | st->print_raw(", "); |
| 21719 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21720 | st->print_raw(", "); |
| 21721 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 21722 | st->print_raw(", "); |
| 21723 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 21724 | st->print_raw("\t! mul masked operation"); |
| 21725 | } |
| 21726 | #endif |
| 21727 | #ifndef PRODUCT |
| 21728 | void vmul_mem_masked_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 21729 | // Start at oper_input_base() and count operands |
| 21730 | unsigned idx0 = 2; |
| 21731 | unsigned idx1 = 2; // dst |
| 21732 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 21733 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 21734 | st->print_raw("vpmul_masked "); |
| 21735 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21736 | st->print_raw(", "); |
| 21737 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21738 | st->print_raw(", "); |
| 21739 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 21740 | st->print_raw(", "); |
| 21741 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 21742 | st->print_raw("\t! mul masked operation"); |
| 21743 | } |
| 21744 | #endif |
| 21745 | #ifndef PRODUCT |
| 21746 | void vmul_mem_masked_1Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 21747 | // Start at oper_input_base() and count operands |
| 21748 | unsigned idx0 = 2; |
| 21749 | unsigned idx1 = 2; // dst |
| 21750 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 21751 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 21752 | st->print_raw("vpmul_masked "); |
| 21753 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21754 | st->print_raw(", "); |
| 21755 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21756 | st->print_raw(", "); |
| 21757 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 21758 | st->print_raw(", "); |
| 21759 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 21760 | st->print_raw("\t! mul masked operation"); |
| 21761 | } |
| 21762 | #endif |
| 21763 | #ifndef PRODUCT |
| 21764 | void vmul_mem_masked_2Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 21765 | // Start at oper_input_base() and count operands |
| 21766 | unsigned idx0 = 2; |
| 21767 | unsigned idx1 = 2; // dst |
| 21768 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 21769 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 21770 | st->print_raw("vpmul_masked "); |
| 21771 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21772 | st->print_raw(", "); |
| 21773 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21774 | st->print_raw(", "); |
| 21775 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 21776 | st->print_raw(", "); |
| 21777 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 21778 | st->print_raw("\t! mul masked operation"); |
| 21779 | } |
| 21780 | #endif |
| 21781 | #ifndef PRODUCT |
| 21782 | void vmul_mem_masked_3Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 21783 | // Start at oper_input_base() and count operands |
| 21784 | unsigned idx0 = 2; |
| 21785 | unsigned idx1 = 2; // dst |
| 21786 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 21787 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 21788 | st->print_raw("vpmul_masked "); |
| 21789 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21790 | st->print_raw(", "); |
| 21791 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21792 | st->print_raw(", "); |
| 21793 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 21794 | st->print_raw(", "); |
| 21795 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 21796 | st->print_raw("\t! mul masked operation"); |
| 21797 | } |
| 21798 | #endif |
| 21799 | #ifndef PRODUCT |
| 21800 | void vsqrt_reg_maskedNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 21801 | // Start at oper_input_base() and count operands |
| 21802 | unsigned idx0 = 1; |
| 21803 | unsigned idx1 = 1; // dst |
| 21804 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask |
| 21805 | st->print_raw("vpsqrt_masked "); |
| 21806 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21807 | st->print_raw(", "); |
| 21808 | opnd_array(2)->ext_format(ra, this,idx2, st); // mask |
| 21809 | st->print_raw("\t! sqrt masked operation"); |
| 21810 | } |
| 21811 | #endif |
| 21812 | #ifndef PRODUCT |
| 21813 | void vsqrt_reg_masked_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 21814 | // Start at oper_input_base() and count operands |
| 21815 | unsigned idx0 = 1; |
| 21816 | unsigned idx1 = 1; // dst |
| 21817 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask |
| 21818 | st->print_raw("vpsqrt_masked "); |
| 21819 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21820 | st->print_raw(", "); |
| 21821 | opnd_array(2)->ext_format(ra, this,idx2, st); // mask |
| 21822 | st->print_raw("\t! sqrt masked operation"); |
| 21823 | } |
| 21824 | #endif |
| 21825 | #ifndef PRODUCT |
| 21826 | void vdiv_reg_maskedNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 21827 | // Start at oper_input_base() and count operands |
| 21828 | unsigned idx0 = 1; |
| 21829 | unsigned idx1 = 1; // dst |
| 21830 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 21831 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 21832 | st->print_raw("vpdiv_masked "); |
| 21833 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21834 | st->print_raw(", "); |
| 21835 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21836 | st->print_raw(", "); |
| 21837 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 21838 | st->print_raw(", "); |
| 21839 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 21840 | st->print_raw("\t! div masked operation"); |
| 21841 | } |
| 21842 | #endif |
| 21843 | #ifndef PRODUCT |
| 21844 | void vdiv_reg_masked_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 21845 | // Start at oper_input_base() and count operands |
| 21846 | unsigned idx0 = 1; |
| 21847 | unsigned idx1 = 1; // dst |
| 21848 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 21849 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 21850 | st->print_raw("vpdiv_masked "); |
| 21851 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21852 | st->print_raw(", "); |
| 21853 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21854 | st->print_raw(", "); |
| 21855 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 21856 | st->print_raw(", "); |
| 21857 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 21858 | st->print_raw("\t! div masked operation"); |
| 21859 | } |
| 21860 | #endif |
| 21861 | #ifndef PRODUCT |
| 21862 | void vdiv_mem_maskedNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 21863 | // Start at oper_input_base() and count operands |
| 21864 | unsigned idx0 = 2; |
| 21865 | unsigned idx1 = 2; // dst |
| 21866 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 21867 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 21868 | st->print_raw("vpdiv_masked "); |
| 21869 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21870 | st->print_raw(", "); |
| 21871 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21872 | st->print_raw(", "); |
| 21873 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 21874 | st->print_raw(", "); |
| 21875 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 21876 | st->print_raw("\t! div masked operation"); |
| 21877 | } |
| 21878 | #endif |
| 21879 | #ifndef PRODUCT |
| 21880 | void vdiv_mem_masked_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 21881 | // Start at oper_input_base() and count operands |
| 21882 | unsigned idx0 = 2; |
| 21883 | unsigned idx1 = 2; // dst |
| 21884 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 21885 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 21886 | st->print_raw("vpdiv_masked "); |
| 21887 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21888 | st->print_raw(", "); |
| 21889 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21890 | st->print_raw(", "); |
| 21891 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 21892 | st->print_raw(", "); |
| 21893 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 21894 | st->print_raw("\t! div masked operation"); |
| 21895 | } |
| 21896 | #endif |
| 21897 | #ifndef PRODUCT |
| 21898 | void vrol_imm_maskedNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 21899 | // Start at oper_input_base() and count operands |
| 21900 | unsigned idx0 = 1; |
| 21901 | unsigned idx1 = 1; // dst |
| 21902 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 21903 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 21904 | st->print_raw("vprotate_imm_masked "); |
| 21905 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21906 | st->print_raw(", "); |
| 21907 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21908 | st->print_raw(", "); |
| 21909 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 21910 | st->print_raw(", "); |
| 21911 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 21912 | st->print_raw("\t! rotate masked operation"); |
| 21913 | } |
| 21914 | #endif |
| 21915 | #ifndef PRODUCT |
| 21916 | void vrol_imm_masked_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 21917 | // Start at oper_input_base() and count operands |
| 21918 | unsigned idx0 = 1; |
| 21919 | unsigned idx1 = 1; // dst |
| 21920 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 21921 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 21922 | st->print_raw("vprotate_imm_masked "); |
| 21923 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21924 | st->print_raw(", "); |
| 21925 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21926 | st->print_raw(", "); |
| 21927 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 21928 | st->print_raw(", "); |
| 21929 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 21930 | st->print_raw("\t! rotate masked operation"); |
| 21931 | } |
| 21932 | #endif |
| 21933 | #ifndef PRODUCT |
| 21934 | void vrol_reg_maskedNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 21935 | // Start at oper_input_base() and count operands |
| 21936 | unsigned idx0 = 1; |
| 21937 | unsigned idx1 = 1; // dst |
| 21938 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 21939 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 21940 | st->print_raw("vrotate_masked "); |
| 21941 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21942 | st->print_raw(", "); |
| 21943 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21944 | st->print_raw(", "); |
| 21945 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 21946 | st->print_raw(", "); |
| 21947 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 21948 | st->print_raw("\t! rotate masked operation"); |
| 21949 | } |
| 21950 | #endif |
| 21951 | #ifndef PRODUCT |
| 21952 | void vrol_reg_masked_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 21953 | // Start at oper_input_base() and count operands |
| 21954 | unsigned idx0 = 1; |
| 21955 | unsigned idx1 = 1; // dst |
| 21956 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 21957 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 21958 | st->print_raw("vrotate_masked "); |
| 21959 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21960 | st->print_raw(", "); |
| 21961 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21962 | st->print_raw(", "); |
| 21963 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 21964 | st->print_raw(", "); |
| 21965 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 21966 | st->print_raw("\t! rotate masked operation"); |
| 21967 | } |
| 21968 | #endif |
| 21969 | #ifndef PRODUCT |
| 21970 | void vlshift_imm_maskedNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 21971 | // Start at oper_input_base() and count operands |
| 21972 | unsigned idx0 = 1; |
| 21973 | unsigned idx1 = 1; // dst |
| 21974 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 21975 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 21976 | st->print_raw("vplshift_imm_masked "); |
| 21977 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21978 | st->print_raw(", "); |
| 21979 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21980 | st->print_raw(", "); |
| 21981 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 21982 | st->print_raw(", "); |
| 21983 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 21984 | st->print_raw("\t! lshift masked operation"); |
| 21985 | } |
| 21986 | #endif |
| 21987 | #ifndef PRODUCT |
| 21988 | void vlshift_imm_masked_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 21989 | // Start at oper_input_base() and count operands |
| 21990 | unsigned idx0 = 1; |
| 21991 | unsigned idx1 = 1; // dst |
| 21992 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 21993 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 21994 | st->print_raw("vplshift_imm_masked "); |
| 21995 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21996 | st->print_raw(", "); |
| 21997 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 21998 | st->print_raw(", "); |
| 21999 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 22000 | st->print_raw(", "); |
| 22001 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 22002 | st->print_raw("\t! lshift masked operation"); |
| 22003 | } |
| 22004 | #endif |
| 22005 | #ifndef PRODUCT |
| 22006 | void vlshift_imm_masked_1Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 22007 | // Start at oper_input_base() and count operands |
| 22008 | unsigned idx0 = 1; |
| 22009 | unsigned idx1 = 1; // dst |
| 22010 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 22011 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 22012 | st->print_raw("vplshift_imm_masked "); |
| 22013 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22014 | st->print_raw(", "); |
| 22015 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22016 | st->print_raw(", "); |
| 22017 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 22018 | st->print_raw(", "); |
| 22019 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 22020 | st->print_raw("\t! lshift masked operation"); |
| 22021 | } |
| 22022 | #endif |
| 22023 | #ifndef PRODUCT |
| 22024 | void vlshift_reg_maskedNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 22025 | // Start at oper_input_base() and count operands |
| 22026 | unsigned idx0 = 1; |
| 22027 | unsigned idx1 = 1; // dst |
| 22028 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 22029 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 22030 | st->print_raw("vplshift_masked "); |
| 22031 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22032 | st->print_raw(", "); |
| 22033 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22034 | st->print_raw(", "); |
| 22035 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 22036 | st->print_raw(", "); |
| 22037 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 22038 | st->print_raw("\t! lshift masked operation"); |
| 22039 | } |
| 22040 | #endif |
| 22041 | #ifndef PRODUCT |
| 22042 | void vlshift_reg_masked_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 22043 | // Start at oper_input_base() and count operands |
| 22044 | unsigned idx0 = 1; |
| 22045 | unsigned idx1 = 1; // dst |
| 22046 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 22047 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 22048 | st->print_raw("vplshift_masked "); |
| 22049 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22050 | st->print_raw(", "); |
| 22051 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22052 | st->print_raw(", "); |
| 22053 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 22054 | st->print_raw(", "); |
| 22055 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 22056 | st->print_raw("\t! lshift masked operation"); |
| 22057 | } |
| 22058 | #endif |
| 22059 | #ifndef PRODUCT |
| 22060 | void vlshift_reg_masked_1Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 22061 | // Start at oper_input_base() and count operands |
| 22062 | unsigned idx0 = 1; |
| 22063 | unsigned idx1 = 1; // dst |
| 22064 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 22065 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 22066 | st->print_raw("vplshift_masked "); |
| 22067 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22068 | st->print_raw(", "); |
| 22069 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22070 | st->print_raw(", "); |
| 22071 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 22072 | st->print_raw(", "); |
| 22073 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 22074 | st->print_raw("\t! lshift masked operation"); |
| 22075 | } |
| 22076 | #endif |
| 22077 | #ifndef PRODUCT |
| 22078 | void vlshiftv_reg_maskedNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 22079 | // Start at oper_input_base() and count operands |
| 22080 | unsigned idx0 = 1; |
| 22081 | unsigned idx1 = 1; // dst |
| 22082 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 22083 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 22084 | st->print_raw("vplshiftv_masked "); |
| 22085 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22086 | st->print_raw(", "); |
| 22087 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22088 | st->print_raw(", "); |
| 22089 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 22090 | st->print_raw(", "); |
| 22091 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 22092 | st->print_raw("\t! lshift masked operation"); |
| 22093 | } |
| 22094 | #endif |
| 22095 | #ifndef PRODUCT |
| 22096 | void vlshiftv_reg_masked_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 22097 | // Start at oper_input_base() and count operands |
| 22098 | unsigned idx0 = 1; |
| 22099 | unsigned idx1 = 1; // dst |
| 22100 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 22101 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 22102 | st->print_raw("vplshiftv_masked "); |
| 22103 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22104 | st->print_raw(", "); |
| 22105 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22106 | st->print_raw(", "); |
| 22107 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 22108 | st->print_raw(", "); |
| 22109 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 22110 | st->print_raw("\t! lshift masked operation"); |
| 22111 | } |
| 22112 | #endif |
| 22113 | #ifndef PRODUCT |
| 22114 | void vlshiftv_reg_masked_1Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 22115 | // Start at oper_input_base() and count operands |
| 22116 | unsigned idx0 = 1; |
| 22117 | unsigned idx1 = 1; // dst |
| 22118 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 22119 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 22120 | st->print_raw("vplshiftv_masked "); |
| 22121 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22122 | st->print_raw(", "); |
| 22123 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22124 | st->print_raw(", "); |
| 22125 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 22126 | st->print_raw(", "); |
| 22127 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 22128 | st->print_raw("\t! lshift masked operation"); |
| 22129 | } |
| 22130 | #endif |
| 22131 | #ifndef PRODUCT |
| 22132 | void vlshift_mem_maskedNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 22133 | // Start at oper_input_base() and count operands |
| 22134 | unsigned idx0 = 2; |
| 22135 | unsigned idx1 = 2; // dst |
| 22136 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 22137 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 22138 | st->print_raw("vplshift_masked "); |
| 22139 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22140 | st->print_raw(", "); |
| 22141 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22142 | st->print_raw(", "); |
| 22143 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 22144 | st->print_raw(", "); |
| 22145 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 22146 | st->print_raw("\t! lshift masked operation"); |
| 22147 | } |
| 22148 | #endif |
| 22149 | #ifndef PRODUCT |
| 22150 | void vlshift_mem_masked_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 22151 | // Start at oper_input_base() and count operands |
| 22152 | unsigned idx0 = 2; |
| 22153 | unsigned idx1 = 2; // dst |
| 22154 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 22155 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 22156 | st->print_raw("vplshift_masked "); |
| 22157 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22158 | st->print_raw(", "); |
| 22159 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22160 | st->print_raw(", "); |
| 22161 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 22162 | st->print_raw(", "); |
| 22163 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 22164 | st->print_raw("\t! lshift masked operation"); |
| 22165 | } |
| 22166 | #endif |
| 22167 | #ifndef PRODUCT |
| 22168 | void vlshift_mem_masked_1Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 22169 | // Start at oper_input_base() and count operands |
| 22170 | unsigned idx0 = 2; |
| 22171 | unsigned idx1 = 2; // dst |
| 22172 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 22173 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 22174 | st->print_raw("vplshift_masked "); |
| 22175 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22176 | st->print_raw(", "); |
| 22177 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22178 | st->print_raw(", "); |
| 22179 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 22180 | st->print_raw(", "); |
| 22181 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 22182 | st->print_raw("\t! lshift masked operation"); |
| 22183 | } |
| 22184 | #endif |
| 22185 | #ifndef PRODUCT |
| 22186 | void vrshift_imm_maskedNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 22187 | // Start at oper_input_base() and count operands |
| 22188 | unsigned idx0 = 1; |
| 22189 | unsigned idx1 = 1; // dst |
| 22190 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 22191 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 22192 | st->print_raw("vprshift_imm_masked "); |
| 22193 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22194 | st->print_raw(", "); |
| 22195 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22196 | st->print_raw(", "); |
| 22197 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 22198 | st->print_raw(", "); |
| 22199 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 22200 | st->print_raw("\t! rshift masked operation"); |
| 22201 | } |
| 22202 | #endif |
| 22203 | #ifndef PRODUCT |
| 22204 | void vrshift_imm_masked_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 22205 | // Start at oper_input_base() and count operands |
| 22206 | unsigned idx0 = 1; |
| 22207 | unsigned idx1 = 1; // dst |
| 22208 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 22209 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 22210 | st->print_raw("vprshift_imm_masked "); |
| 22211 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22212 | st->print_raw(", "); |
| 22213 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22214 | st->print_raw(", "); |
| 22215 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 22216 | st->print_raw(", "); |
| 22217 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 22218 | st->print_raw("\t! rshift masked operation"); |
| 22219 | } |
| 22220 | #endif |
| 22221 | #ifndef PRODUCT |
| 22222 | void vrshift_imm_masked_1Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 22223 | // Start at oper_input_base() and count operands |
| 22224 | unsigned idx0 = 1; |
| 22225 | unsigned idx1 = 1; // dst |
| 22226 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 22227 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 22228 | st->print_raw("vprshift_imm_masked "); |
| 22229 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22230 | st->print_raw(", "); |
| 22231 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22232 | st->print_raw(", "); |
| 22233 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 22234 | st->print_raw(", "); |
| 22235 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 22236 | st->print_raw("\t! rshift masked operation"); |
| 22237 | } |
| 22238 | #endif |
| 22239 | #ifndef PRODUCT |
| 22240 | void vrshift_reg_maskedNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 22241 | // Start at oper_input_base() and count operands |
| 22242 | unsigned idx0 = 1; |
| 22243 | unsigned idx1 = 1; // dst |
| 22244 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 22245 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 22246 | st->print_raw("vprshift_masked "); |
| 22247 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22248 | st->print_raw(", "); |
| 22249 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22250 | st->print_raw(", "); |
| 22251 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 22252 | st->print_raw(", "); |
| 22253 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 22254 | st->print_raw("\t! rshift masked operation"); |
| 22255 | } |
| 22256 | #endif |
| 22257 | #ifndef PRODUCT |
| 22258 | void vrshift_reg_masked_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 22259 | // Start at oper_input_base() and count operands |
| 22260 | unsigned idx0 = 1; |
| 22261 | unsigned idx1 = 1; // dst |
| 22262 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 22263 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 22264 | st->print_raw("vprshift_masked "); |
| 22265 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22266 | st->print_raw(", "); |
| 22267 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22268 | st->print_raw(", "); |
| 22269 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 22270 | st->print_raw(", "); |
| 22271 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 22272 | st->print_raw("\t! rshift masked operation"); |
| 22273 | } |
| 22274 | #endif |
| 22275 | #ifndef PRODUCT |
| 22276 | void vrshift_reg_masked_1Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 22277 | // Start at oper_input_base() and count operands |
| 22278 | unsigned idx0 = 1; |
| 22279 | unsigned idx1 = 1; // dst |
| 22280 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 22281 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 22282 | st->print_raw("vprshift_masked "); |
| 22283 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22284 | st->print_raw(", "); |
| 22285 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22286 | st->print_raw(", "); |
| 22287 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 22288 | st->print_raw(", "); |
| 22289 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 22290 | st->print_raw("\t! rshift masked operation"); |
| 22291 | } |
| 22292 | #endif |
| 22293 | #ifndef PRODUCT |
| 22294 | void vrshiftv_reg_maskedNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 22295 | // Start at oper_input_base() and count operands |
| 22296 | unsigned idx0 = 1; |
| 22297 | unsigned idx1 = 1; // dst |
| 22298 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 22299 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 22300 | st->print_raw("vprshiftv_masked "); |
| 22301 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22302 | st->print_raw(", "); |
| 22303 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22304 | st->print_raw(", "); |
| 22305 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 22306 | st->print_raw(", "); |
| 22307 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 22308 | st->print_raw("\t! rshift masked operation"); |
| 22309 | } |
| 22310 | #endif |
| 22311 | #ifndef PRODUCT |
| 22312 | void vrshiftv_reg_masked_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 22313 | // Start at oper_input_base() and count operands |
| 22314 | unsigned idx0 = 1; |
| 22315 | unsigned idx1 = 1; // dst |
| 22316 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 22317 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 22318 | st->print_raw("vprshiftv_masked "); |
| 22319 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22320 | st->print_raw(", "); |
| 22321 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22322 | st->print_raw(", "); |
| 22323 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 22324 | st->print_raw(", "); |
| 22325 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 22326 | st->print_raw("\t! rshift masked operation"); |
| 22327 | } |
| 22328 | #endif |
| 22329 | #ifndef PRODUCT |
| 22330 | void vrshiftv_reg_masked_1Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 22331 | // Start at oper_input_base() and count operands |
| 22332 | unsigned idx0 = 1; |
| 22333 | unsigned idx1 = 1; // dst |
| 22334 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 22335 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 22336 | st->print_raw("vprshiftv_masked "); |
| 22337 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22338 | st->print_raw(", "); |
| 22339 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22340 | st->print_raw(", "); |
| 22341 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 22342 | st->print_raw(", "); |
| 22343 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 22344 | st->print_raw("\t! rshift masked operation"); |
| 22345 | } |
| 22346 | #endif |
| 22347 | #ifndef PRODUCT |
| 22348 | void vrshift_mem_maskedNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 22349 | // Start at oper_input_base() and count operands |
| 22350 | unsigned idx0 = 2; |
| 22351 | unsigned idx1 = 2; // dst |
| 22352 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 22353 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 22354 | st->print_raw("vprshift_masked "); |
| 22355 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22356 | st->print_raw(", "); |
| 22357 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22358 | st->print_raw(", "); |
| 22359 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 22360 | st->print_raw(", "); |
| 22361 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 22362 | st->print_raw("\t! rshift masked operation"); |
| 22363 | } |
| 22364 | #endif |
| 22365 | #ifndef PRODUCT |
| 22366 | void vrshift_mem_masked_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 22367 | // Start at oper_input_base() and count operands |
| 22368 | unsigned idx0 = 2; |
| 22369 | unsigned idx1 = 2; // dst |
| 22370 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 22371 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 22372 | st->print_raw("vprshift_masked "); |
| 22373 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22374 | st->print_raw(", "); |
| 22375 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22376 | st->print_raw(", "); |
| 22377 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 22378 | st->print_raw(", "); |
| 22379 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 22380 | st->print_raw("\t! rshift masked operation"); |
| 22381 | } |
| 22382 | #endif |
| 22383 | #ifndef PRODUCT |
| 22384 | void vrshift_mem_masked_1Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 22385 | // Start at oper_input_base() and count operands |
| 22386 | unsigned idx0 = 2; |
| 22387 | unsigned idx1 = 2; // dst |
| 22388 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 22389 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 22390 | st->print_raw("vprshift_masked "); |
| 22391 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22392 | st->print_raw(", "); |
| 22393 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22394 | st->print_raw(", "); |
| 22395 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 22396 | st->print_raw(", "); |
| 22397 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 22398 | st->print_raw("\t! rshift masked operation"); |
| 22399 | } |
| 22400 | #endif |
| 22401 | #ifndef PRODUCT |
| 22402 | void vurshift_imm_maskedNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 22403 | // Start at oper_input_base() and count operands |
| 22404 | unsigned idx0 = 1; |
| 22405 | unsigned idx1 = 1; // dst |
| 22406 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 22407 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 22408 | st->print_raw("vpurshift_imm_masked "); |
| 22409 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22410 | st->print_raw(", "); |
| 22411 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22412 | st->print_raw(", "); |
| 22413 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 22414 | st->print_raw(", "); |
| 22415 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 22416 | st->print_raw("\t! urshift masked operation"); |
| 22417 | } |
| 22418 | #endif |
| 22419 | #ifndef PRODUCT |
| 22420 | void vurshift_imm_masked_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 22421 | // Start at oper_input_base() and count operands |
| 22422 | unsigned idx0 = 1; |
| 22423 | unsigned idx1 = 1; // dst |
| 22424 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 22425 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 22426 | st->print_raw("vpurshift_imm_masked "); |
| 22427 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22428 | st->print_raw(", "); |
| 22429 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22430 | st->print_raw(", "); |
| 22431 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 22432 | st->print_raw(", "); |
| 22433 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 22434 | st->print_raw("\t! urshift masked operation"); |
| 22435 | } |
| 22436 | #endif |
| 22437 | #ifndef PRODUCT |
| 22438 | void vurshift_imm_masked_1Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 22439 | // Start at oper_input_base() and count operands |
| 22440 | unsigned idx0 = 1; |
| 22441 | unsigned idx1 = 1; // dst |
| 22442 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift |
| 22443 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 22444 | st->print_raw("vpurshift_imm_masked "); |
| 22445 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22446 | st->print_raw(", "); |
| 22447 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22448 | st->print_raw(", "); |
| 22449 | opnd_array(2)->ext_format(ra, this,idx2, st); // shift |
| 22450 | st->print_raw(", "); |
| 22451 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 22452 | st->print_raw("\t! urshift masked operation"); |
| 22453 | } |
| 22454 | #endif |
| 22455 | #ifndef PRODUCT |
| 22456 | void vurshift_reg_maskedNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 22457 | // Start at oper_input_base() and count operands |
| 22458 | unsigned idx0 = 1; |
| 22459 | unsigned idx1 = 1; // dst |
| 22460 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 22461 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 22462 | st->print_raw("vpurshift_masked "); |
| 22463 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22464 | st->print_raw(", "); |
| 22465 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22466 | st->print_raw(", "); |
| 22467 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 22468 | st->print_raw(", "); |
| 22469 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 22470 | st->print_raw("\t! urshift masked operation"); |
| 22471 | } |
| 22472 | #endif |
| 22473 | #ifndef PRODUCT |
| 22474 | void vurshift_reg_masked_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 22475 | // Start at oper_input_base() and count operands |
| 22476 | unsigned idx0 = 1; |
| 22477 | unsigned idx1 = 1; // dst |
| 22478 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 22479 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 22480 | st->print_raw("vpurshift_masked "); |
| 22481 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22482 | st->print_raw(", "); |
| 22483 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22484 | st->print_raw(", "); |
| 22485 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 22486 | st->print_raw(", "); |
| 22487 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 22488 | st->print_raw("\t! urshift masked operation"); |
| 22489 | } |
| 22490 | #endif |
| 22491 | #ifndef PRODUCT |
| 22492 | void vurshift_reg_masked_1Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 22493 | // Start at oper_input_base() and count operands |
| 22494 | unsigned idx0 = 1; |
| 22495 | unsigned idx1 = 1; // dst |
| 22496 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 22497 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 22498 | st->print_raw("vpurshift_masked "); |
| 22499 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22500 | st->print_raw(", "); |
| 22501 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22502 | st->print_raw(", "); |
| 22503 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 22504 | st->print_raw(", "); |
| 22505 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 22506 | st->print_raw("\t! urshift masked operation"); |
| 22507 | } |
| 22508 | #endif |
| 22509 | #ifndef PRODUCT |
| 22510 | void vurshiftv_reg_maskedNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 22511 | // Start at oper_input_base() and count operands |
| 22512 | unsigned idx0 = 1; |
| 22513 | unsigned idx1 = 1; // dst |
| 22514 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 22515 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 22516 | st->print_raw("vpurshiftv_masked "); |
| 22517 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22518 | st->print_raw(", "); |
| 22519 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22520 | st->print_raw(", "); |
| 22521 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 22522 | st->print_raw(", "); |
| 22523 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 22524 | st->print_raw("\t! urshift masked operation"); |
| 22525 | } |
| 22526 | #endif |
| 22527 | #ifndef PRODUCT |
| 22528 | void vurshiftv_reg_masked_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 22529 | // Start at oper_input_base() and count operands |
| 22530 | unsigned idx0 = 1; |
| 22531 | unsigned idx1 = 1; // dst |
| 22532 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 22533 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 22534 | st->print_raw("vpurshiftv_masked "); |
| 22535 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22536 | st->print_raw(", "); |
| 22537 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22538 | st->print_raw(", "); |
| 22539 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 22540 | st->print_raw(", "); |
| 22541 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 22542 | st->print_raw("\t! urshift masked operation"); |
| 22543 | } |
| 22544 | #endif |
| 22545 | #ifndef PRODUCT |
| 22546 | void vurshiftv_reg_masked_1Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 22547 | // Start at oper_input_base() and count operands |
| 22548 | unsigned idx0 = 1; |
| 22549 | unsigned idx1 = 1; // dst |
| 22550 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 22551 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 22552 | st->print_raw("vpurshiftv_masked "); |
| 22553 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22554 | st->print_raw(", "); |
| 22555 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22556 | st->print_raw(", "); |
| 22557 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 22558 | st->print_raw(", "); |
| 22559 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 22560 | st->print_raw("\t! urshift masked operation"); |
| 22561 | } |
| 22562 | #endif |
| 22563 | #ifndef PRODUCT |
| 22564 | void vurshift_mem_maskedNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 22565 | // Start at oper_input_base() and count operands |
| 22566 | unsigned idx0 = 2; |
| 22567 | unsigned idx1 = 2; // dst |
| 22568 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 22569 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 22570 | st->print_raw("vpurshift_masked "); |
| 22571 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22572 | st->print_raw(", "); |
| 22573 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22574 | st->print_raw(", "); |
| 22575 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 22576 | st->print_raw(", "); |
| 22577 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 22578 | st->print_raw("\t! urshift masked operation"); |
| 22579 | } |
| 22580 | #endif |
| 22581 | #ifndef PRODUCT |
| 22582 | void vurshift_mem_masked_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 22583 | // Start at oper_input_base() and count operands |
| 22584 | unsigned idx0 = 2; |
| 22585 | unsigned idx1 = 2; // dst |
| 22586 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 22587 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 22588 | st->print_raw("vpurshift_masked "); |
| 22589 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22590 | st->print_raw(", "); |
| 22591 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22592 | st->print_raw(", "); |
| 22593 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 22594 | st->print_raw(", "); |
| 22595 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 22596 | st->print_raw("\t! urshift masked operation"); |
| 22597 | } |
| 22598 | #endif |
| 22599 | #ifndef PRODUCT |
| 22600 | void vurshift_mem_masked_1Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 22601 | // Start at oper_input_base() and count operands |
| 22602 | unsigned idx0 = 2; |
| 22603 | unsigned idx1 = 2; // dst |
| 22604 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 22605 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 22606 | st->print_raw("vpurshift_masked "); |
| 22607 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22608 | st->print_raw(", "); |
| 22609 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22610 | st->print_raw(", "); |
| 22611 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 22612 | st->print_raw(", "); |
| 22613 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 22614 | st->print_raw("\t! urshift masked operation"); |
| 22615 | } |
| 22616 | #endif |
| 22617 | #ifndef PRODUCT |
| 22618 | void vmaxv_reg_maskedNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 22619 | // Start at oper_input_base() and count operands |
| 22620 | unsigned idx0 = 1; |
| 22621 | unsigned idx1 = 1; // dst |
| 22622 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 22623 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 22624 | st->print_raw("vpmax_masked "); |
| 22625 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22626 | st->print_raw(", "); |
| 22627 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22628 | st->print_raw(", "); |
| 22629 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 22630 | st->print_raw(", "); |
| 22631 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 22632 | st->print_raw("\t! max masked operation"); |
| 22633 | } |
| 22634 | #endif |
| 22635 | #ifndef PRODUCT |
| 22636 | void vmaxv_mem_maskedNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 22637 | // Start at oper_input_base() and count operands |
| 22638 | unsigned idx0 = 2; |
| 22639 | unsigned idx1 = 2; // dst |
| 22640 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 22641 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 22642 | st->print_raw("vpmax_masked "); |
| 22643 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22644 | st->print_raw(", "); |
| 22645 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22646 | st->print_raw(", "); |
| 22647 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 22648 | st->print_raw(", "); |
| 22649 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 22650 | st->print_raw("\t! max masked operation"); |
| 22651 | } |
| 22652 | #endif |
| 22653 | #ifndef PRODUCT |
| 22654 | void vminv_reg_maskedNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 22655 | // Start at oper_input_base() and count operands |
| 22656 | unsigned idx0 = 1; |
| 22657 | unsigned idx1 = 1; // dst |
| 22658 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 22659 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 22660 | st->print_raw("vpmin_masked "); |
| 22661 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22662 | st->print_raw(", "); |
| 22663 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22664 | st->print_raw(", "); |
| 22665 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 22666 | st->print_raw(", "); |
| 22667 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 22668 | st->print_raw("\t! min masked operation"); |
| 22669 | } |
| 22670 | #endif |
| 22671 | #ifndef PRODUCT |
| 22672 | void vminv_mem_maskedNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 22673 | // Start at oper_input_base() and count operands |
| 22674 | unsigned idx0 = 2; |
| 22675 | unsigned idx1 = 2; // dst |
| 22676 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 22677 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 22678 | st->print_raw("vpmin_masked "); |
| 22679 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22680 | st->print_raw(", "); |
| 22681 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22682 | st->print_raw(", "); |
| 22683 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 22684 | st->print_raw(", "); |
| 22685 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 22686 | st->print_raw("\t! min masked operation"); |
| 22687 | } |
| 22688 | #endif |
| 22689 | #ifndef PRODUCT |
| 22690 | void vrearrangev_reg_maskedNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 22691 | // Start at oper_input_base() and count operands |
| 22692 | unsigned idx0 = 1; |
| 22693 | unsigned idx1 = 1; // dst |
| 22694 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 22695 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask |
| 22696 | st->print_raw("vprearrange_masked "); |
| 22697 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22698 | st->print_raw(", "); |
| 22699 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22700 | st->print_raw(", "); |
| 22701 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 22702 | st->print_raw(", "); |
| 22703 | opnd_array(3)->ext_format(ra, this,idx3, st); // mask |
| 22704 | st->print_raw("\t! rearrange masked operation"); |
| 22705 | } |
| 22706 | #endif |
| 22707 | #ifndef PRODUCT |
| 22708 | void vabs_maskedNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 22709 | // Start at oper_input_base() and count operands |
| 22710 | unsigned idx0 = 1; |
| 22711 | unsigned idx1 = 1; // dst |
| 22712 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask |
| 22713 | st->print_raw("vabs_masked "); |
| 22714 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22715 | st->print_raw(", "); |
| 22716 | opnd_array(2)->ext_format(ra, this,idx2, st); // mask |
| 22717 | st->print_raw(" \t! vabs masked operation"); |
| 22718 | } |
| 22719 | #endif |
| 22720 | #ifndef PRODUCT |
| 22721 | void vabs_masked_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 22722 | // Start at oper_input_base() and count operands |
| 22723 | unsigned idx0 = 1; |
| 22724 | unsigned idx1 = 1; // dst |
| 22725 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask |
| 22726 | st->print_raw("vabs_masked "); |
| 22727 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22728 | st->print_raw(", "); |
| 22729 | opnd_array(2)->ext_format(ra, this,idx2, st); // mask |
| 22730 | st->print_raw(" \t! vabs masked operation"); |
| 22731 | } |
| 22732 | #endif |
| 22733 | #ifndef PRODUCT |
| 22734 | void vabs_masked_1Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 22735 | // Start at oper_input_base() and count operands |
| 22736 | unsigned idx0 = 1; |
| 22737 | unsigned idx1 = 1; // dst |
| 22738 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask |
| 22739 | st->print_raw("vabs_masked "); |
| 22740 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22741 | st->print_raw(", "); |
| 22742 | opnd_array(2)->ext_format(ra, this,idx2, st); // mask |
| 22743 | st->print_raw(" \t! vabs masked operation"); |
| 22744 | } |
| 22745 | #endif |
| 22746 | #ifndef PRODUCT |
| 22747 | void vabs_masked_2Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 22748 | // Start at oper_input_base() and count operands |
| 22749 | unsigned idx0 = 1; |
| 22750 | unsigned idx1 = 1; // dst |
| 22751 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask |
| 22752 | st->print_raw("vabs_masked "); |
| 22753 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22754 | st->print_raw(", "); |
| 22755 | opnd_array(2)->ext_format(ra, this,idx2, st); // mask |
| 22756 | st->print_raw(" \t! vabs masked operation"); |
| 22757 | } |
| 22758 | #endif |
| 22759 | #ifndef PRODUCT |
| 22760 | void vfma_reg_maskedNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 22761 | // Start at oper_input_base() and count operands |
| 22762 | unsigned idx0 = 1; |
| 22763 | unsigned idx1 = 1; // dst |
| 22764 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 22765 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // src3 |
| 22766 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // mask |
| 22767 | st->print_raw("vfma_masked "); |
| 22768 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22769 | st->print_raw(", "); |
| 22770 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 22771 | st->print_raw(", "); |
| 22772 | opnd_array(3)->ext_format(ra, this,idx3, st); // src3 |
| 22773 | st->print_raw(", "); |
| 22774 | opnd_array(4)->ext_format(ra, this,idx4, st); // mask |
| 22775 | st->print_raw(" \t! vfma masked operation"); |
| 22776 | } |
| 22777 | #endif |
| 22778 | #ifndef PRODUCT |
| 22779 | void vfma_reg_masked_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 22780 | // Start at oper_input_base() and count operands |
| 22781 | unsigned idx0 = 1; |
| 22782 | unsigned idx1 = 1; // dst |
| 22783 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 22784 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // src3 |
| 22785 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // mask |
| 22786 | st->print_raw("vfma_masked "); |
| 22787 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22788 | st->print_raw(", "); |
| 22789 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 22790 | st->print_raw(", "); |
| 22791 | opnd_array(3)->ext_format(ra, this,idx3, st); // src3 |
| 22792 | st->print_raw(", "); |
| 22793 | opnd_array(4)->ext_format(ra, this,idx4, st); // mask |
| 22794 | st->print_raw(" \t! vfma masked operation"); |
| 22795 | } |
| 22796 | #endif |
| 22797 | #ifndef PRODUCT |
| 22798 | void vfma_mem_maskedNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 22799 | // Start at oper_input_base() and count operands |
| 22800 | unsigned idx0 = 2; |
| 22801 | unsigned idx1 = 2; // dst |
| 22802 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 22803 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // src3 |
| 22804 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // mask |
| 22805 | st->print_raw("vfma_masked "); |
| 22806 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22807 | st->print_raw(", "); |
| 22808 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 22809 | st->print_raw(", "); |
| 22810 | opnd_array(3)->ext_format(ra, this,idx3, st); // src3 |
| 22811 | st->print_raw(", "); |
| 22812 | opnd_array(4)->ext_format(ra, this,idx4, st); // mask |
| 22813 | st->print_raw(" \t! vfma masked operation"); |
| 22814 | } |
| 22815 | #endif |
| 22816 | #ifndef PRODUCT |
| 22817 | void vfma_mem_masked_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 22818 | // Start at oper_input_base() and count operands |
| 22819 | unsigned idx0 = 2; |
| 22820 | unsigned idx1 = 2; // dst |
| 22821 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 22822 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // src3 |
| 22823 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // mask |
| 22824 | st->print_raw("vfma_masked "); |
| 22825 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 22826 | st->print_raw(", "); |
| 22827 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 22828 | st->print_raw(", "); |
| 22829 | opnd_array(3)->ext_format(ra, this,idx3, st); // src3 |
| 22830 | st->print_raw(", "); |
| 22831 | opnd_array(4)->ext_format(ra, this,idx4, st); // mask |
| 22832 | st->print_raw(" \t! vfma masked operation"); |
| 22833 | } |
| 22834 | #endif |
| 22835 | #ifndef PRODUCT |
| 22836 | void evcmp_maskedNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 22837 | // Start at oper_input_base() and count operands |
| 22838 | unsigned idx0 = 1; |
| 22839 | unsigned idx1 = 1; // src1 |
| 22840 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 22841 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // cond |
| 22842 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // mask |
| 22843 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch |
| 22844 | st->print_raw("vcmp_masked "); |
| 22845 | opnd_array(0)->int_format(ra, this, st); // dst |
| 22846 | st->print_raw(", "); |
| 22847 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 22848 | st->print_raw(", "); |
| 22849 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 22850 | st->print_raw(", "); |
| 22851 | opnd_array(3)->ext_format(ra, this,idx3, st); // cond |
| 22852 | st->print_raw(", "); |
| 22853 | opnd_array(4)->ext_format(ra, this,idx4, st); // mask |
| 22854 | st->print_raw("\t! using "); |
| 22855 | opnd_array(5)->ext_format(ra, this,idx5, st); // scratch |
| 22856 | st->print_raw(" as TEMP"); |
| 22857 | } |
| 22858 | #endif |
| 22859 | #ifndef PRODUCT |
| 22860 | void mask_all_evexI_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 22861 | // Start at oper_input_base() and count operands |
| 22862 | unsigned idx0 = 1; |
| 22863 | unsigned idx1 = 1; // cnt |
| 22864 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst |
| 22865 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp |
| 22866 | st->print_raw("mask_all_evexI "); |
| 22867 | opnd_array(2)->ext_format(ra, this,idx2, st); // dst |
| 22868 | st->print_raw(", "); |
| 22869 | opnd_array(1)->ext_format(ra, this,idx1, st); // cnt |
| 22870 | st->print_raw(" \t! using "); |
| 22871 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp |
| 22872 | st->print_raw(" as TEMP"); |
| 22873 | } |
| 22874 | #endif |
| 22875 | #ifndef PRODUCT |
| 22876 | void mask_all_evexINode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 22877 | // Start at oper_input_base() and count operands |
| 22878 | unsigned idx0 = 1; |
| 22879 | unsigned idx1 = 1; // src |
| 22880 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst |
| 22881 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp |
| 22882 | st->print_raw("mask_all_evexI "); |
| 22883 | opnd_array(2)->ext_format(ra, this,idx2, st); // dst |
| 22884 | st->print_raw(", "); |
| 22885 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 22886 | st->print_raw(" \t! using "); |
| 22887 | opnd_array(3)->ext_format(ra, this,idx3, st); // tmp |
| 22888 | st->print_raw(" as TEMP"); |
| 22889 | } |
| 22890 | #endif |
| 22891 | #ifndef PRODUCT |
| 22892 | void mask_all_evexLNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 22893 | // Start at oper_input_base() and count operands |
| 22894 | unsigned idx0 = 1; |
| 22895 | unsigned idx1 = 1; // src |
| 22896 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst |
| 22897 | st->print_raw("mask_all_evexL "); |
| 22898 | opnd_array(2)->ext_format(ra, this,idx2, st); // dst |
| 22899 | st->print_raw(", "); |
| 22900 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 22901 | st->print_raw(" \t! mask all operation"); |
| 22902 | } |
| 22903 | #endif |
| 22904 | #ifndef PRODUCT |
| 22905 | void mask_not_immLT8Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 22906 | // Start at oper_input_base() and count operands |
| 22907 | unsigned idx0 = 1; |
| 22908 | unsigned idx1 = 1; // src |
| 22909 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cnt |
| 22910 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst |
| 22911 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // rtmp |
| 22912 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // ktmp |
| 22913 | st->print_raw("mask_not_LT8 "); |
| 22914 | opnd_array(3)->ext_format(ra, this,idx3, st); // dst |
| 22915 | st->print_raw(", "); |
| 22916 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 22917 | st->print_raw(", "); |
| 22918 | opnd_array(2)->ext_format(ra, this,idx2, st); // cnt |
| 22919 | st->print_raw(" \t!using "); |
| 22920 | opnd_array(5)->ext_format(ra, this,idx5, st); // ktmp |
| 22921 | st->print_raw(" and "); |
| 22922 | opnd_array(4)->ext_format(ra, this,idx4, st); // rtmp |
| 22923 | st->print_raw(" as TEMP"); |
| 22924 | } |
| 22925 | #endif |
| 22926 | #ifndef PRODUCT |
| 22927 | void mask_not_immNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 22928 | // Start at oper_input_base() and count operands |
| 22929 | unsigned idx0 = 1; |
| 22930 | unsigned idx1 = 1; // src |
| 22931 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cnt |
| 22932 | st->print_raw("mask_not "); |
| 22933 | opnd_array(0)->int_format(ra, this, st); // dst |
| 22934 | st->print_raw(", "); |
| 22935 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 22936 | st->print_raw(", "); |
| 22937 | opnd_array(2)->ext_format(ra, this,idx2, st); // cnt |
| 22938 | st->print_raw(" \t! mask not operation"); |
| 22939 | } |
| 22940 | #endif |
| 22941 | #ifndef PRODUCT |
| 22942 | void long_to_maskLE8_avxNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 22943 | // Start at oper_input_base() and count operands |
| 22944 | unsigned idx0 = 1; |
| 22945 | unsigned idx1 = 1; // src |
| 22946 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst |
| 22947 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // rtmp1 |
| 22948 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // rtmp2 |
| 22949 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // xtmp |
| 22950 | st->print_raw("long_to_mask_avx "); |
| 22951 | opnd_array(2)->ext_format(ra, this,idx2, st); // dst |
| 22952 | st->print_raw(", "); |
| 22953 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 22954 | st->print_raw("\t! using "); |
| 22955 | opnd_array(3)->ext_format(ra, this,idx3, st); // rtmp1 |
| 22956 | st->print_raw(", "); |
| 22957 | opnd_array(4)->ext_format(ra, this,idx4, st); // rtmp2 |
| 22958 | st->print_raw(", "); |
| 22959 | opnd_array(5)->ext_format(ra, this,idx5, st); // xtmp |
| 22960 | st->print_raw(" as TEMP"); |
| 22961 | } |
| 22962 | #endif |
| 22963 | #ifndef PRODUCT |
| 22964 | void long_to_maskGT8_avxNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 22965 | // Start at oper_input_base() and count operands |
| 22966 | unsigned idx0 = 1; |
| 22967 | unsigned idx1 = 1; // src |
| 22968 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst |
| 22969 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // rtmp1 |
| 22970 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // rtmp2 |
| 22971 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // xtmp1 |
| 22972 | st->print_raw("long_to_mask_avx "); |
| 22973 | opnd_array(2)->ext_format(ra, this,idx2, st); // dst |
| 22974 | st->print_raw(", "); |
| 22975 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 22976 | st->print_raw("\t! using "); |
| 22977 | opnd_array(3)->ext_format(ra, this,idx3, st); // rtmp1 |
| 22978 | st->print_raw(", "); |
| 22979 | opnd_array(4)->ext_format(ra, this,idx4, st); // rtmp2 |
| 22980 | st->print_raw(", "); |
| 22981 | opnd_array(5)->ext_format(ra, this,idx5, st); // xtmp1 |
| 22982 | st->print_raw(", as TEMP"); |
| 22983 | } |
| 22984 | #endif |
| 22985 | #ifndef PRODUCT |
| 22986 | void long_to_mask_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 22987 | // Start at oper_input_base() and count operands |
| 22988 | unsigned idx0 = 1; |
| 22989 | unsigned idx1 = 1; // src |
| 22990 | st->print_raw("long_to_mask_evex "); |
| 22991 | opnd_array(0)->int_format(ra, this, st); // dst |
| 22992 | st->print_raw(", "); |
| 22993 | opnd_array(1)->ext_format(ra, this,idx1, st); // src |
| 22994 | st->print_raw("\t!"); |
| 22995 | } |
| 22996 | #endif |
| 22997 | #ifndef PRODUCT |
| 22998 | void mask_opers_evexNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 22999 | // Start at oper_input_base() and count operands |
| 23000 | unsigned idx0 = 1; |
| 23001 | unsigned idx1 = 1; // src1 |
| 23002 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 23003 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // kscratch |
| 23004 | st->print_raw("mask_opers_evex "); |
| 23005 | opnd_array(0)->int_format(ra, this, st); // dst |
| 23006 | st->print_raw(", "); |
| 23007 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 23008 | st->print_raw(", "); |
| 23009 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 23010 | st->print_raw("\t! using "); |
| 23011 | opnd_array(3)->ext_format(ra, this,idx3, st); // kscratch |
| 23012 | st->print_raw(" as TEMP"); |
| 23013 | } |
| 23014 | #endif |
| 23015 | #ifndef PRODUCT |
| 23016 | void mask_opers_evex_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 23017 | // Start at oper_input_base() and count operands |
| 23018 | unsigned idx0 = 1; |
| 23019 | unsigned idx1 = 1; // src1 |
| 23020 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 23021 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // kscratch |
| 23022 | st->print_raw("mask_opers_evex "); |
| 23023 | opnd_array(0)->int_format(ra, this, st); // dst |
| 23024 | st->print_raw(", "); |
| 23025 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 23026 | st->print_raw(", "); |
| 23027 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 23028 | st->print_raw("\t! using "); |
| 23029 | opnd_array(3)->ext_format(ra, this,idx3, st); // kscratch |
| 23030 | st->print_raw(" as TEMP"); |
| 23031 | } |
| 23032 | #endif |
| 23033 | #ifndef PRODUCT |
| 23034 | void mask_opers_evex_1Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 23035 | // Start at oper_input_base() and count operands |
| 23036 | unsigned idx0 = 1; |
| 23037 | unsigned idx1 = 1; // src1 |
| 23038 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2 |
| 23039 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // kscratch |
| 23040 | st->print_raw("mask_opers_evex "); |
| 23041 | opnd_array(0)->int_format(ra, this, st); // dst |
| 23042 | st->print_raw(", "); |
| 23043 | opnd_array(1)->ext_format(ra, this,idx1, st); // src1 |
| 23044 | st->print_raw(", "); |
| 23045 | opnd_array(2)->ext_format(ra, this,idx2, st); // src2 |
| 23046 | st->print_raw("\t! using "); |
| 23047 | opnd_array(3)->ext_format(ra, this,idx3, st); // kscratch |
| 23048 | st->print_raw(" as TEMP"); |
| 23049 | } |
| 23050 | #endif |
| 23051 | #ifndef PRODUCT |
| 23052 | void castMMNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 23053 | // Start at oper_input_base() and count operands |
| 23054 | unsigned idx0 = 1; |
| 23055 | unsigned idx1 = 1; // dst |
| 23056 | st->print_raw("# castVV of "); |
| 23057 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 23058 | } |
| 23059 | #endif |
| 23060 | #ifndef PRODUCT |
| 23061 | void castVVNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 23062 | // Start at oper_input_base() and count operands |
| 23063 | unsigned idx0 = 1; |
| 23064 | unsigned idx1 = 1; // dst |
| 23065 | st->print_raw("# castVV of "); |
| 23066 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 23067 | } |
| 23068 | #endif |
| 23069 | #ifndef PRODUCT |
| 23070 | void castVVLegNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 23071 | // Start at oper_input_base() and count operands |
| 23072 | unsigned idx0 = 1; |
| 23073 | unsigned idx1 = 1; // dst |
| 23074 | st->print_raw("# castVV of "); |
| 23075 | opnd_array(1)->ext_format(ra, this,idx1, st); // dst |
| 23076 | } |
| 23077 | #endif |
| 23078 | #ifndef PRODUCT |
| 23079 | void compareAndSwapP_shenandoahNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 23080 | // Start at oper_input_base() and count operands |
| 23081 | unsigned idx0 = 2; |
| 23082 | unsigned idx1 = 2; // mem_ptr |
| 23083 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval |
| 23084 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval |
| 23085 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1 |
| 23086 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2 |
| 23087 | st->print_raw("shenandoah_cas_oop "); |
| 23088 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr |
| 23089 | st->print_raw(","); |
| 23090 | opnd_array(3)->ext_format(ra, this,idx3, st); // newval |
| 23091 | } |
| 23092 | #endif |
| 23093 | #ifndef PRODUCT |
| 23094 | void compareAndSwapP_shenandoah_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 23095 | // Start at oper_input_base() and count operands |
| 23096 | unsigned idx0 = 2; |
| 23097 | unsigned idx1 = 2; // mem_ptr |
| 23098 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval |
| 23099 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval |
| 23100 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1 |
| 23101 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2 |
| 23102 | st->print_raw("shenandoah_cas_oop "); |
| 23103 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr |
| 23104 | st->print_raw(","); |
| 23105 | opnd_array(3)->ext_format(ra, this,idx3, st); // newval |
| 23106 | } |
| 23107 | #endif |
| 23108 | #ifndef PRODUCT |
| 23109 | void compareAndSwapN_shenandoahNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 23110 | // Start at oper_input_base() and count operands |
| 23111 | unsigned idx0 = 2; |
| 23112 | unsigned idx1 = 2; // mem_ptr |
| 23113 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval |
| 23114 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval |
| 23115 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1 |
| 23116 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2 |
| 23117 | st->print_raw("shenandoah_cas_oop "); |
| 23118 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr |
| 23119 | st->print_raw(","); |
| 23120 | opnd_array(3)->ext_format(ra, this,idx3, st); // newval |
| 23121 | } |
| 23122 | #endif |
| 23123 | #ifndef PRODUCT |
| 23124 | void compareAndSwapN_shenandoah_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 23125 | // Start at oper_input_base() and count operands |
| 23126 | unsigned idx0 = 2; |
| 23127 | unsigned idx1 = 2; // mem_ptr |
| 23128 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval |
| 23129 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval |
| 23130 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1 |
| 23131 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2 |
| 23132 | st->print_raw("shenandoah_cas_oop "); |
| 23133 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr |
| 23134 | st->print_raw(","); |
| 23135 | opnd_array(3)->ext_format(ra, this,idx3, st); // newval |
| 23136 | } |
| 23137 | #endif |
| 23138 | #ifndef PRODUCT |
| 23139 | void compareAndExchangeN_shenandoahNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 23140 | // Start at oper_input_base() and count operands |
| 23141 | unsigned idx0 = 2; |
| 23142 | unsigned idx1 = 2; // mem_ptr |
| 23143 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval |
| 23144 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval |
| 23145 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1 |
| 23146 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2 |
| 23147 | st->print_raw("shenandoah_cas_oop "); |
| 23148 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr |
| 23149 | st->print_raw(","); |
| 23150 | opnd_array(3)->ext_format(ra, this,idx3, st); // newval |
| 23151 | } |
| 23152 | #endif |
| 23153 | #ifndef PRODUCT |
| 23154 | void compareAndExchangeP_shenandoahNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 23155 | // Start at oper_input_base() and count operands |
| 23156 | unsigned idx0 = 2; |
| 23157 | unsigned idx1 = 2; // mem_ptr |
| 23158 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval |
| 23159 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval |
| 23160 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1 |
| 23161 | unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2 |
| 23162 | st->print_raw("shenandoah_cas_oop "); |
| 23163 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem_ptr |
| 23164 | st->print_raw(","); |
| 23165 | opnd_array(3)->ext_format(ra, this,idx3, st); // newval |
| 23166 | } |
| 23167 | #endif |
| 23168 | #ifndef PRODUCT |
| 23169 | void zLoadPNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 23170 | // Start at oper_input_base() and count operands |
| 23171 | unsigned idx0 = 2; |
| 23172 | unsigned idx1 = 2; // mem |
| 23173 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst |
| 23174 | st->print_raw("movq "); |
| 23175 | opnd_array(2)->ext_format(ra, this,idx2, st); // dst |
| 23176 | st->print_raw(", "); |
| 23177 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 23178 | if (ra->C->alias_type(adr_type())->field() != NULL__null) { |
| 23179 | ciField* f = ra->C->alias_type(adr_type())->field(); |
| 23180 | st->print(" ! Field: "); |
| 23181 | if (f->is_volatile()) |
| 23182 | st->print("volatile "); |
| 23183 | f->holder()->name()->print_symbol_on(st); |
| 23184 | st->print("."); |
| 23185 | f->name()->print_symbol_on(st); |
| 23186 | if (f->is_constant()) |
| 23187 | st->print(" (constant)"); |
| 23188 | } else { |
| 23189 | if (ra->C->alias_type(adr_type())->is_volatile()) |
| 23190 | st->print(" volatile!"); |
| 23191 | } |
| 23192 | } |
| 23193 | #endif |
| 23194 | #ifndef PRODUCT |
| 23195 | void zCompareAndExchangePNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 23196 | // Start at oper_input_base() and count operands |
| 23197 | unsigned idx0 = 2; |
| 23198 | unsigned idx1 = 2; // mem |
| 23199 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval |
| 23200 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval |
| 23201 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp |
| 23202 | st->print_raw("lock\n\t"); |
| 23203 | st->print_raw("cmpxchgq "); |
| 23204 | opnd_array(3)->ext_format(ra, this,idx3, st); // newval |
| 23205 | st->print_raw(", "); |
| 23206 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 23207 | } |
| 23208 | #endif |
| 23209 | #ifndef PRODUCT |
| 23210 | void zCompareAndSwapPNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 23211 | // Start at oper_input_base() and count operands |
| 23212 | unsigned idx0 = 2; |
| 23213 | unsigned idx1 = 2; // mem |
| 23214 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval |
| 23215 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval |
| 23216 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp |
| 23217 | st->print_raw("lock\n\t"); |
| 23218 | st->print_raw("cmpxchgq "); |
| 23219 | opnd_array(3)->ext_format(ra, this,idx3, st); // newval |
| 23220 | st->print_raw(", "); |
| 23221 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 23222 | st->print_raw("\n\t"); |
| 23223 | st->print_raw("sete "); |
| 23224 | opnd_array(0)->int_format(ra, this, st); // res |
| 23225 | st->print_raw("\n\t"); |
| 23226 | st->print_raw("movzbl "); |
| 23227 | opnd_array(0)->int_format(ra, this, st); // res |
| 23228 | st->print_raw(", "); |
| 23229 | opnd_array(0)->int_format(ra, this, st); // res |
| 23230 | } |
| 23231 | #endif |
| 23232 | #ifndef PRODUCT |
| 23233 | void zCompareAndSwapP_0Node::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 23234 | // Start at oper_input_base() and count operands |
| 23235 | unsigned idx0 = 2; |
| 23236 | unsigned idx1 = 2; // mem |
| 23237 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval |
| 23238 | unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval |
| 23239 | unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp |
| 23240 | st->print_raw("lock\n\t"); |
| 23241 | st->print_raw("cmpxchgq "); |
| 23242 | opnd_array(3)->ext_format(ra, this,idx3, st); // newval |
| 23243 | st->print_raw(", "); |
| 23244 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 23245 | st->print_raw("\n\t"); |
| 23246 | st->print_raw("sete "); |
| 23247 | opnd_array(0)->int_format(ra, this, st); // res |
| 23248 | st->print_raw("\n\t"); |
| 23249 | st->print_raw("movzbl "); |
| 23250 | opnd_array(0)->int_format(ra, this, st); // res |
| 23251 | st->print_raw(", "); |
| 23252 | opnd_array(0)->int_format(ra, this, st); // res |
| 23253 | } |
| 23254 | #endif |
| 23255 | #ifndef PRODUCT |
| 23256 | void zXChgPNode::format(PhaseRegAlloc *ra, outputStream *st) const { |
| 23257 | // Start at oper_input_base() and count operands |
| 23258 | unsigned idx0 = 2; |
| 23259 | unsigned idx1 = 2; // mem |
| 23260 | unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // newval |
| 23261 | st->print_raw("xchgq "); |
| 23262 | opnd_array(2)->ext_format(ra, this,idx2, st); // newval |
| 23263 | st->print_raw(", "); |
| 23264 | opnd_array(1)->ext_format(ra, this,idx1, st); // mem |
| 23265 | } |
| 23266 | #endif |
| 23267 | // Check consistency of C++ compilation with ADLC options: |
| 23268 | // Check adlc -DLINUX=1 |
| 23269 | #ifndef LINUX1 |
| 23270 | # error "LINUX must be defined" |
| 23271 | #endif // LINUX |
| 23272 | // Check adlc -D_GNU_SOURCE=1 |
| 23273 | #ifndef _GNU_SOURCE1 |
| 23274 | # error "_GNU_SOURCE must be defined" |
| 23275 | #endif // _GNU_SOURCE |
| 23276 | // Check adlc -DAMD64=1 |
| 23277 | #ifndef AMD641 |
| 23278 | # error "AMD64 must be defined" |
| 23279 | #endif // AMD64 |
| 23280 | // Check adlc -D_LP64=1 |
| 23281 | #ifndef _LP641 |
| 23282 | # error "_LP64 must be defined" |
| 23283 | #endif // _LP64 |