Bug Summary

File:jdk/build/linux-x86_64-server-fastdebug/hotspot/variant-server/gensrc/adfiles/ad_x86.cpp
Warning:line 27133, column 12
Value stored to 'idx2' during its initialization is never read

Annotated Source Code

Press '?' to see keyboard shortcuts

clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name ad_x86.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model pic -pic-level 2 -mthread-model posix -fno-delete-null-pointer-checks -mframe-pointer=all -relaxed-aliasing -fmath-errno -fno-rounding-math -masm-verbose -mconstructor-aliases -munwind-tables -target-cpu x86-64 -dwarf-column-info -fno-split-dwarf-inlining -debugger-tuning=gdb -resource-dir /usr/lib/llvm-10/lib/clang/10.0.0 -I /home/daniel/Projects/java/jdk/build/linux-x86_64-server-fastdebug/hotspot/variant-server/libjvm/objs/precompiled -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -D __STDC_CONSTANT_MACROS -D _GNU_SOURCE -D _REENTRANT -D LIBC=gnu -D LINUX -D VM_LITTLE_ENDIAN -D _LP64=1 -D ASSERT -D CHECK_UNHANDLED_OOPS -D TARGET_ARCH_x86 -D INCLUDE_SUFFIX_OS=_linux -D INCLUDE_SUFFIX_CPU=_x86 -D INCLUDE_SUFFIX_COMPILER=_gcc -D TARGET_COMPILER_gcc -D AMD64 -D HOTSPOT_LIB_ARCH="amd64" -D COMPILER1 -D COMPILER2 -I /home/daniel/Projects/java/jdk/build/linux-x86_64-server-fastdebug/hotspot/variant-server/gensrc/adfiles -I /home/daniel/Projects/java/jdk/src/hotspot/share -I /home/daniel/Projects/java/jdk/src/hotspot/os/linux -I /home/daniel/Projects/java/jdk/src/hotspot/os/posix -I /home/daniel/Projects/java/jdk/src/hotspot/cpu/x86 -I /home/daniel/Projects/java/jdk/src/hotspot/os_cpu/linux_x86 -I /home/daniel/Projects/java/jdk/build/linux-x86_64-server-fastdebug/hotspot/variant-server/gensrc -I /home/daniel/Projects/java/jdk/src/hotspot/share/precompiled -I /home/daniel/Projects/java/jdk/src/hotspot/share/include -I /home/daniel/Projects/java/jdk/src/hotspot/os/posix/include -I /home/daniel/Projects/java/jdk/build/linux-x86_64-server-fastdebug/support/modules_include/java.base -I /home/daniel/Projects/java/jdk/build/linux-x86_64-server-fastdebug/support/modules_include/java.base/linux -I /home/daniel/Projects/java/jdk/src/java.base/share/native/libjimage -I /home/daniel/Projects/java/jdk/build/linux-x86_64-server-fastdebug/hotspot/variant-server/gensrc/adfiles -I /home/daniel/Projects/java/jdk/src/hotspot/share -I /home/daniel/Projects/java/jdk/src/hotspot/os/linux -I /home/daniel/Projects/java/jdk/src/hotspot/os/posix -I /home/daniel/Projects/java/jdk/src/hotspot/cpu/x86 -I /home/daniel/Projects/java/jdk/src/hotspot/os_cpu/linux_x86 -I /home/daniel/Projects/java/jdk/build/linux-x86_64-server-fastdebug/hotspot/variant-server/gensrc -D _FORTIFY_SOURCE=2 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.5.0/../../../../include/c++/7.5.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.5.0/../../../../include/x86_64-linux-gnu/c++/7.5.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.5.0/../../../../include/x86_64-linux-gnu/c++/7.5.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.5.0/../../../../include/c++/7.5.0/backward -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-10/lib/clang/10.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O3 -Wno-format-zero-length -Wno-unused-parameter -Wno-unused -Wno-parentheses -Wno-comment -Wno-unknown-pragmas -Wno-address -Wno-delete-non-virtual-dtor -Wno-char-subscripts -Wno-array-bounds -Wno-int-in-bool-context -Wno-ignored-qualifiers -Wno-missing-field-initializers -Wno-implicit-fallthrough -Wno-empty-body -Wno-strict-overflow -Wno-sequence-point -Wno-maybe-uninitialized -Wno-misleading-indentation -Wno-cast-function-type -Wno-shift-negative-value -Wno-nonnull -std=c++14 -fdeprecated-macro -fdebug-compilation-dir /home/daniel/Projects/java/jdk/make/hotspot -ferror-limit 19 -fmessage-length 0 -fvisibility hidden -stack-protector 1 -fno-rtti -fgnuc-version=4.2.1 -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -faddrsig -o /home/daniel/Projects/java/scan/2021-12-21-193737-8510-1 -x c++ /home/daniel/Projects/java/jdk/build/linux-x86_64-server-fastdebug/hotspot/variant-server/gensrc/adfiles/ad_x86.cpp
1#line 1 "ad_x86.cpp"
2//
3// Copyright (c) 2003, 2021, Oracle and/or its affiliates. All rights reserved.
4// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5//
6// This code is free software; you can redistribute it and/or modify it
7// under the terms of the GNU General Public License version 2 only, as
8// published by the Free Software Foundation.
9//
10// This code is distributed in the hope that it will be useful, but WITHOUT
11// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13// version 2 for more details (a copy is included in the LICENSE file that
14// accompanied this code).
15//
16// You should have received a copy of the GNU General Public License version
17// 2 along with this work; if not, write to the Free Software Foundation,
18// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19//
20// Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21// or visit www.oracle.com if you need additional information or have any
22// questions.
23//
24//
25
26// Machine Generated File. Do Not Edit!
27
28#include "precompiled.hpp"
29#include "adfiles/adGlobals_x86.hpp"
30#include "adfiles/ad_x86.hpp"
31#include "memory/allocation.inline.hpp"
32#include "code/codeCache.hpp"
33#include "code/compiledIC.hpp"
34#include "code/nativeInst.hpp"
35#include "code/vmreg.inline.hpp"
36#include "gc/shared/collectedHeap.inline.hpp"
37#include "oops/compiledICHolder.hpp"
38#include "oops/compressedOops.hpp"
39#include "oops/markWord.hpp"
40#include "oops/method.hpp"
41#include "oops/oop.inline.hpp"
42#include "opto/c2_MacroAssembler.hpp"
43#include "opto/cfgnode.hpp"
44#include "opto/intrinsicnode.hpp"
45#include "opto/locknode.hpp"
46#include "opto/opcodes.hpp"
47#include "opto/regalloc.hpp"
48#include "opto/regmask.hpp"
49#include "opto/runtime.hpp"
50#include "runtime/safepointMechanism.hpp"
51#include "runtime/sharedRuntime.hpp"
52#include "runtime/stubRoutines.hpp"
53#include "utilities/growableArray.hpp"
54#include "utilities/powerOfTwo.hpp"
55
56//SourceForm
57
58#line 337 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
59
60#define RELOC_IMM64Assembler::imm_operand Assembler::imm_operand
61#define RELOC_DISP32Assembler::disp32_operand Assembler::disp32_operand
62
63#define ___masm. _masm.
64
65RegMask _ANY_REG_mask;
66RegMask _PTR_REG_mask;
67RegMask _PTR_REG_NO_RBP_mask;
68RegMask _PTR_NO_RAX_REG_mask;
69RegMask _PTR_NO_RAX_RBX_REG_mask;
70RegMask _LONG_REG_mask;
71RegMask _LONG_NO_RAX_RDX_REG_mask;
72RegMask _LONG_NO_RCX_REG_mask;
73RegMask _INT_REG_mask;
74RegMask _INT_NO_RAX_RDX_REG_mask;
75RegMask _INT_NO_RCX_REG_mask;
76RegMask _FLOAT_REG_mask;
77RegMask _STACK_OR_PTR_REG_mask;
78RegMask _STACK_OR_LONG_REG_mask;
79RegMask _STACK_OR_INT_REG_mask;
80
81static bool need_r12_heapbase() {
82 return UseCompressedOops;
83}
84
85void reg_mask_init() {
86 // _ALL_REG_mask is generated by adlc from the all_reg register class below.
87 // We derive a number of subsets from it.
88 _ANY_REG_mask = _ALL_REG_mask;
89
90 if (PreserveFramePointer) {
91 _ANY_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
92 _ANY_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()->next()));
93 }
94 if (need_r12_heapbase()) {
95 _ANY_REG_mask.Remove(OptoReg::as_OptoReg(r12->as_VMReg()));
96 _ANY_REG_mask.Remove(OptoReg::as_OptoReg(r12->as_VMReg()->next()));
97 }
98
99 _PTR_REG_mask = _ANY_REG_mask;
100 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(rsp->as_VMReg()));
101 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(rsp->as_VMReg()->next()));
102 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(r15->as_VMReg()));
103 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(r15->as_VMReg()->next()));
104
105 _STACK_OR_PTR_REG_mask = _PTR_REG_mask;
106 _STACK_OR_PTR_REG_mask.OR(STACK_OR_STACK_SLOTS_mask());
107
108 _PTR_REG_NO_RBP_mask = _PTR_REG_mask;
109 _PTR_REG_NO_RBP_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
110 _PTR_REG_NO_RBP_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()->next()));
111
112 _PTR_NO_RAX_REG_mask = _PTR_REG_mask;
113 _PTR_NO_RAX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()));
114 _PTR_NO_RAX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()->next()));
115
116 _PTR_NO_RAX_RBX_REG_mask = _PTR_NO_RAX_REG_mask;
117 _PTR_NO_RAX_RBX_REG_mask.Remove(OptoReg::as_OptoReg(rbx->as_VMReg()));
118 _PTR_NO_RAX_RBX_REG_mask.Remove(OptoReg::as_OptoReg(rbx->as_VMReg()->next()));
119
120 _LONG_REG_mask = _PTR_REG_mask;
121 _STACK_OR_LONG_REG_mask = _LONG_REG_mask;
122 _STACK_OR_LONG_REG_mask.OR(STACK_OR_STACK_SLOTS_mask());
123
124 _LONG_NO_RAX_RDX_REG_mask = _LONG_REG_mask;
125 _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()));
126 _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()->next()));
127 _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rdx->as_VMReg()));
128 _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rdx->as_VMReg()->next()));
129
130 _LONG_NO_RCX_REG_mask = _LONG_REG_mask;
131 _LONG_NO_RCX_REG_mask.Remove(OptoReg::as_OptoReg(rcx->as_VMReg()));
132 _LONG_NO_RCX_REG_mask.Remove(OptoReg::as_OptoReg(rcx->as_VMReg()->next()));
133
134 _INT_REG_mask = _ALL_INT_REG_mask;
135 if (PreserveFramePointer) {
136 _INT_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
137 }
138 if (need_r12_heapbase()) {
139 _INT_REG_mask.Remove(OptoReg::as_OptoReg(r12->as_VMReg()));
140 }
141
142 _STACK_OR_INT_REG_mask = _INT_REG_mask;
143 _STACK_OR_INT_REG_mask.OR(STACK_OR_STACK_SLOTS_mask());
144
145 _INT_NO_RAX_RDX_REG_mask = _INT_REG_mask;
146 _INT_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()));
147 _INT_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rdx->as_VMReg()));
148
149 _INT_NO_RCX_REG_mask = _INT_REG_mask;
150 _INT_NO_RCX_REG_mask.Remove(OptoReg::as_OptoReg(rcx->as_VMReg()));
151
152 // _FLOAT_REG_LEGACY_mask/_FLOAT_REG_EVEX_mask is generated by adlc
153 // from the float_reg_legacy/float_reg_evex register class.
154 _FLOAT_REG_mask = VM_Version::supports_evex() ? _FLOAT_REG_EVEX_mask : _FLOAT_REG_LEGACY_mask;
155
156 if (Matcher::has_predicated_vectors()) {
157 // Post-loop multi-versioning expects mask to be present in K1 register, till the time
158 // its fixed, RA should not be allocting K1 register, this shall prevent any accidental
159 // curruption of value held in K1 register.
160 if (PostLoopMultiversioning) {
161 const_cast<RegMask*>(&_VECTMASK_REG_mask)->Remove(OptoReg::as_OptoReg(k1->as_VMReg()));
162 const_cast<RegMask*>(&_VECTMASK_REG_mask)->Remove(OptoReg::as_OptoReg(k1->as_VMReg()->next()));
163 }
164 }
165}
166
167static bool generate_vzeroupper(Compile* C) {
168 return (VM_Version::supports_vzeroupper() && (C->max_vector_size() > 16 || C->clear_upper_avx() == true)) ? true: false; // Generate vzeroupper
169}
170
171static int clear_avx_size() {
172 return generate_vzeroupper(Compile::current()) ? 3: 0; // vzeroupper
173}
174
175// !!!!! Special hack to get all types of calls to specify the byte offset
176// from the start of the call to the point where the return address
177// will point.
178int MachCallStaticJavaNode::ret_addr_offset()
179{
180 int offset = 5; // 5 bytes from start of call to where return address points
181 offset += clear_avx_size();
182 return offset;
183}
184
185int MachCallDynamicJavaNode::ret_addr_offset()
186{
187 int offset = 15; // 15 bytes from start of call to where return address points
188 offset += clear_avx_size();
189 return offset;
190}
191
192int MachCallRuntimeNode::ret_addr_offset() {
193 int offset = 13; // movq r10,#addr; callq (r10)
194 if (this->ideal_Opcode() != Op_CallLeafVector) {
195 offset += clear_avx_size();
196 }
197 return offset;
198}
199
200int MachCallNativeNode::ret_addr_offset() {
201 int offset = 13; // movq r10,#addr; callq (r10)
202 offset += clear_avx_size();
203 return offset;
204}
205//
206// Compute padding required for nodes which need alignment
207//
208
209// The address of the call instruction needs to be 4-byte aligned to
210// ensure that it does not span a cache line so that it can be patched.
211int CallStaticJavaDirectNode::compute_padding(int current_offset) const
212{
213 current_offset += clear_avx_size(); // skip vzeroupper
214 current_offset += 1; // skip call opcode byte
215 return align_up(current_offset, alignment_required()) - current_offset;
216}
217
218// The address of the call instruction needs to be 4-byte aligned to
219// ensure that it does not span a cache line so that it can be patched.
220int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
221{
222 current_offset += clear_avx_size(); // skip vzeroupper
223 current_offset += 11; // skip movq instruction + call opcode byte
224 return align_up(current_offset, alignment_required()) - current_offset;
225}
226
227// EMIT_RM()
228void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
229 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3);
230 cbuf.insts()->emit_int8(c);
231}
232
233// EMIT_CC()
234void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
235 unsigned char c = (unsigned char) (f1 | f2);
236 cbuf.insts()->emit_int8(c);
237}
238
239// EMIT_OPCODE()
240void emit_opcode(CodeBuffer &cbuf, int code) {
241 cbuf.insts()->emit_int8((unsigned char) code);
242}
243
244// EMIT_OPCODE() w/ relocation information
245void emit_opcode(CodeBuffer &cbuf,
246 int code, relocInfo::relocType reloc, int offset, int format)
247{
248 cbuf.relocate(cbuf.insts_mark() + offset, reloc, format);
249 emit_opcode(cbuf, code);
250}
251
252// EMIT_D8()
253void emit_d8(CodeBuffer &cbuf, int d8) {
254 cbuf.insts()->emit_int8((unsigned char) d8);
255}
256
257// EMIT_D16()
258void emit_d16(CodeBuffer &cbuf, int d16) {
259 cbuf.insts()->emit_int16(d16);
260}
261
262// EMIT_D32()
263void emit_d32(CodeBuffer &cbuf, int d32) {
264 cbuf.insts()->emit_int32(d32);
265}
266
267// EMIT_D64()
268void emit_d64(CodeBuffer &cbuf, int64_t d64) {
269 cbuf.insts()->emit_int64(d64);
270}
271
272// emit 32 bit value and construct relocation entry from relocInfo::relocType
273void emit_d32_reloc(CodeBuffer& cbuf,
274 int d32,
275 relocInfo::relocType reloc,
276 int format)
277{
278 assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc")do { if (!(reloc != relocInfo::external_word_type)) { (*g_assert_poison
) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 556, "assert(" "reloc != relocInfo::external_word_type" ") failed"
, "use 2-arg emit_d32_reloc"); ::breakpoint(); } } while (0);
279 cbuf.relocate(cbuf.insts_mark(), reloc, format);
280 cbuf.insts()->emit_int32(d32);
281}
282
283// emit 32 bit value and construct relocation entry from RelocationHolder
284void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) {
285#ifdef ASSERT1
286 if (rspec.reloc()->type() == relocInfo::oop_type &&
287 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) {
288 assert(Universe::heap()->is_in((address)(intptr_t)d32), "should be real oop")do { if (!(Universe::heap()->is_in((address)(intptr_t)d32)
)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 566, "assert(" "Universe::heap()->is_in((address)(intptr_t)d32)"
") failed", "should be real oop"); ::breakpoint(); } } while
(0);
289 assert(oopDesc::is_oop(cast_to_oop((intptr_t)d32)), "cannot embed broken oops in code")do { if (!(oopDesc::is_oop(cast_to_oop((intptr_t)d32)))) { (*
g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 567, "assert(" "oopDesc::is_oop(cast_to_oop((intptr_t)d32))"
") failed", "cannot embed broken oops in code"); ::breakpoint
(); } } while (0);
290 }
291#endif
292 cbuf.relocate(cbuf.insts_mark(), rspec, format);
293 cbuf.insts()->emit_int32(d32);
294}
295
296void emit_d32_reloc(CodeBuffer& cbuf, address addr) {
297 address next_ip = cbuf.insts_end() + 4;
298 emit_d32_reloc(cbuf, (int) (addr - next_ip),
299 external_word_Relocation::spec(addr),
300 RELOC_DISP32Assembler::disp32_operand);
301}
302
303
304// emit 64 bit value and construct relocation entry from relocInfo::relocType
305void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, relocInfo::relocType reloc, int format) {
306 cbuf.relocate(cbuf.insts_mark(), reloc, format);
307 cbuf.insts()->emit_int64(d64);
308}
309
310// emit 64 bit value and construct relocation entry from RelocationHolder
311void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) {
312#ifdef ASSERT1
313 if (rspec.reloc()->type() == relocInfo::oop_type &&
314 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) {
315 assert(Universe::heap()->is_in((address)d64), "should be real oop")do { if (!(Universe::heap()->is_in((address)d64))) { (*g_assert_poison
) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 593, "assert(" "Universe::heap()->is_in((address)d64)" ") failed"
, "should be real oop"); ::breakpoint(); } } while (0);
316 assert(oopDesc::is_oop(cast_to_oop(d64)), "cannot embed broken oops in code")do { if (!(oopDesc::is_oop(cast_to_oop(d64)))) { (*g_assert_poison
) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 594, "assert(" "oopDesc::is_oop(cast_to_oop(d64))" ") failed"
, "cannot embed broken oops in code"); ::breakpoint(); } } while
(0);
317 }
318#endif
319 cbuf.relocate(cbuf.insts_mark(), rspec, format);
320 cbuf.insts()->emit_int64(d64);
321}
322
323// Access stack slot for load or store
324void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp)
325{
326 emit_opcode(cbuf, opcode); // (e.g., FILD [RSP+src])
327 if (-0x80 <= disp && disp < 0x80) {
328 emit_rm(cbuf, 0x01, rm_field, RSP_enc); // R/M byte
329 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
330 emit_d8(cbuf, disp); // Displacement // R/M byte
331 } else {
332 emit_rm(cbuf, 0x02, rm_field, RSP_enc); // R/M byte
333 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
334 emit_d32(cbuf, disp); // Displacement // R/M byte
335 }
336}
337
338 // rRegI ereg, memory mem) %{ // emit_reg_mem
339void encode_RegMem(CodeBuffer &cbuf,
340 int reg,
341 int base, int index, int scale, int disp, relocInfo::relocType disp_reloc)
342{
343 assert(disp_reloc == relocInfo::none, "cannot have disp")do { if (!(disp_reloc == relocInfo::none)) { (*g_assert_poison
) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 621, "assert(" "disp_reloc == relocInfo::none" ") failed", "cannot have disp"
); ::breakpoint(); } } while (0);
344 int regenc = reg & 7;
345 int baseenc = base & 7;
346 int indexenc = index & 7;
347
348 // There is no index & no scale, use form without SIB byte
349 if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) {
350 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
351 if (disp == 0 && base != RBP_enc && base != R13_enc) {
352 emit_rm(cbuf, 0x0, regenc, baseenc); // *
353 } else if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
354 // If 8-bit displacement, mode 0x1
355 emit_rm(cbuf, 0x1, regenc, baseenc); // *
356 emit_d8(cbuf, disp);
357 } else {
358 // If 32-bit displacement
359 if (base == -1) { // Special flag for absolute address
360 emit_rm(cbuf, 0x0, regenc, 0x5); // *
361 if (disp_reloc != relocInfo::none) {
362 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32Assembler::disp32_operand);
363 } else {
364 emit_d32(cbuf, disp);
365 }
366 } else {
367 // Normal base + offset
368 emit_rm(cbuf, 0x2, regenc, baseenc); // *
369 if (disp_reloc != relocInfo::none) {
370 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32Assembler::disp32_operand);
371 } else {
372 emit_d32(cbuf, disp);
373 }
374 }
375 }
376 } else {
377 // Else, encode with the SIB byte
378 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
379 if (disp == 0 && base != RBP_enc && base != R13_enc) {
380 // If no displacement
381 emit_rm(cbuf, 0x0, regenc, 0x4); // *
382 emit_rm(cbuf, scale, indexenc, baseenc);
383 } else {
384 if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
385 // If 8-bit displacement, mode 0x1
386 emit_rm(cbuf, 0x1, regenc, 0x4); // *
387 emit_rm(cbuf, scale, indexenc, baseenc);
388 emit_d8(cbuf, disp);
389 } else {
390 // If 32-bit displacement
391 if (base == 0x04 ) {
392 emit_rm(cbuf, 0x2, regenc, 0x4);
393 emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid???
394 } else {
395 emit_rm(cbuf, 0x2, regenc, 0x4);
396 emit_rm(cbuf, scale, indexenc, baseenc); // *
397 }
398 if (disp_reloc != relocInfo::none) {
399 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32Assembler::disp32_operand);
400 } else {
401 emit_d32(cbuf, disp);
402 }
403 }
404 }
405 }
406}
407
408// This could be in MacroAssembler but it's fairly C2 specific
409void emit_cmpfp_fixup(MacroAssembler& _masm) {
410 Label exit;
411 ___masm. jccb(Assembler::noParity, exit)jccb_0(Assembler::noParity, exit, "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 689);
412 ___masm. pushf();
413 //
414 // comiss/ucomiss instructions set ZF,PF,CF flags and
415 // zero OF,AF,SF for NaN values.
416 // Fixup flags by zeroing ZF,PF so that compare of NaN
417 // values returns 'less than' result (CF is set).
418 // Leave the rest of flags unchanged.
419 //
420 // 7 6 5 4 3 2 1 0
421 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
422 // 0 0 1 0 1 0 1 1 (0x2B)
423 //
424 ___masm. andq(Address(rsp, 0), 0xffffff2b);
425 ___masm. popf();
426 ___masm. bind(exit);
427}
428
429void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
430 Label done;
431 ___masm. movl(dst, -1);
432 ___masm. jcc(Assembler::parity, done);
433 ___masm. jcc(Assembler::below, done);
434 ___masm. setb(Assembler::notEqual, dst);
435 ___masm. movzbl(dst, dst);
436 ___masm. bind(done);
437}
438
439// Math.min() # Math.max()
440// --------------------------
441// ucomis[s/d] #
442// ja -> b # a
443// jp -> NaN # NaN
444// jb -> a # b
445// je #
446// |-jz -> a | b # a & b
447// | -> a #
448void emit_fp_min_max(MacroAssembler& _masm, XMMRegister dst,
449 XMMRegister a, XMMRegister b,
450 XMMRegister xmmt, Register rt,
451 bool min, bool single) {
452
453 Label nan, zero, below, above, done;
454
455 if (single)
456 ___masm. ucomiss(a, b);
457 else
458 ___masm. ucomisd(a, b);
459
460 if (dst->encoding() != (min ? b : a)->encoding())
461 ___masm. jccb(Assembler::above, above)jccb_0(Assembler::above, above, "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 739); // CF=0 & ZF=0
462 else
463 ___masm. jccb(Assembler::above, done)jccb_0(Assembler::above, done, "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 741);
464
465 ___masm. jccb(Assembler::parity, nan)jccb_0(Assembler::parity, nan, "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 743); // PF=1
466 ___masm. jccb(Assembler::below, below)jccb_0(Assembler::below, below, "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 744); // CF=1
467
468 // equal
469 ___masm. vpxor(xmmt, xmmt, xmmt, Assembler::AVX_128bit);
470 if (single) {
471 ___masm. ucomiss(a, xmmt);
472 ___masm. jccb(Assembler::equal, zero)jccb_0(Assembler::equal, zero, "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 750);
473
474 ___masm. movflt(dst, a);
475 ___masm. jmp(done);
476 }
477 else {
478 ___masm. ucomisd(a, xmmt);
479 ___masm. jccb(Assembler::equal, zero)jccb_0(Assembler::equal, zero, "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 757);
480
481 ___masm. movdbl(dst, a);
482 ___masm. jmp(done);
483 }
484
485 ___masm. bind(zero);
486 if (min)
487 ___masm. vpor(dst, a, b, Assembler::AVX_128bit);
488 else
489 ___masm. vpand(dst, a, b, Assembler::AVX_128bit);
490
491 ___masm. jmp(done);
492
493 ___masm. bind(above);
494 if (single)
495 ___masm. movflt(dst, min ? b : a);
496 else
497 ___masm. movdbl(dst, min ? b : a);
498
499 ___masm. jmp(done);
500
501 ___masm. bind(nan);
502 if (single) {
503 ___masm. movl(rt, 0x7fc00000); // Float.NaN
504 ___masm. movdl(dst, rt);
505 }
506 else {
507 ___masm. mov64(rt, 0x7ff8000000000000L); // Double.NaN
508 ___masm. movdq(dst, rt);
509 }
510 ___masm. jmp(done);
511
512 ___masm. bind(below);
513 if (single)
514 ___masm. movflt(dst, min ? a : b);
515 else
516 ___masm. movdbl(dst, min ? a : b);
517
518 ___masm. bind(done);
519}
520
521//=============================================================================
522const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
523
524int ConstantTable::calculate_table_base_offset() const {
525 return 0; // absolute addressing, no offset
526}
527
528bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
529void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
530 ShouldNotReachHere()do { (*g_assert_poison) = 'X';; report_should_not_reach_here(
"/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 808); ::breakpoint(); } while (0);
531}
532
533void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
534 // Empty encoding
535}
536
537uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
538 return 0;
539}
540
541#ifndef PRODUCT
542void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
543 st->print("# MachConstantBaseNode (empty encoding)");
544}
545#endif
546
547
548//=============================================================================
549#ifndef PRODUCT
550void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
551 Compile* C = ra_->C;
552
553 int framesize = C->output()->frame_size_in_bytes();
554 int bangsize = C->output()->bang_size_in_bytes();
555 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned")do { if (!((framesize & (StackAlignmentInBytes-1)) == 0))
{ (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 833, "assert(" "(framesize & (StackAlignmentInBytes-1)) == 0"
") failed", "frame size not aligned"); ::breakpoint(); } } while
(0);
556 // Remove wordSize for return addr which is already pushed.
557 framesize -= wordSize;
558
559 if (C->output()->need_stack_bang(bangsize)) {
560 framesize -= wordSize;
561 st->print("# stack bang (%d bytes)", bangsize);
562 st->print("\n\t");
563 st->print("pushq rbp\t# Save rbp");
564 if (PreserveFramePointer) {
565 st->print("\n\t");
566 st->print("movq rbp, rsp\t# Save the caller's SP into rbp");
567 }
568 if (framesize) {
569 st->print("\n\t");
570 st->print("subq rsp, #%d\t# Create frame",framesize);
571 }
572 } else {
573 st->print("subq rsp, #%d\t# Create frame",framesize);
574 st->print("\n\t");
575 framesize -= wordSize;
576 st->print("movq [rsp + #%d], rbp\t# Save rbp",framesize);
577 if (PreserveFramePointer) {
578 st->print("\n\t");
579 st->print("movq rbp, rsp\t# Save the caller's SP into rbp");
580 if (framesize > 0) {
581 st->print("\n\t");
582 st->print("addq rbp, #%d", framesize);
583 }
584 }
585 }
586
587 if (VerifyStackAtCalls) {
588 st->print("\n\t");
589 framesize -= wordSize;
590 st->print("movq [rsp + #%d], 0xbadb100d\t# Majik cookie for stack depth check",framesize);
591#ifdef ASSERT1
592 st->print("\n\t");
593 st->print("# stack alignment check");
594#endif
595 }
596 if (C->stub_function() != NULL__null && BarrierSet::barrier_set()->barrier_set_nmethod() != NULL__null) {
597 st->print("\n\t");
598 st->print("cmpl [r15_thread + #disarmed_offset], #disarmed_value\t");
599 st->print("\n\t");
600 st->print("je fast_entry\t");
601 st->print("\n\t");
602 st->print("call #nmethod_entry_barrier_stub\t");
603 st->print("\n\tfast_entry:");
604 }
605 st->cr();
606}
607#endif
608
609void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
610 Compile* C = ra_->C;
611 MacroAssembler _masm(&cbuf);
612
613 int framesize = C->output()->frame_size_in_bytes();
614 int bangsize = C->output()->bang_size_in_bytes();
615
616 if (C->clinit_barrier_on_entry()) {
617 assert(VM_Version::supports_fast_class_init_checks(), "sanity")do { if (!(VM_Version::supports_fast_class_init_checks())) { (
*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 895, "assert(" "VM_Version::supports_fast_class_init_checks()"
") failed", "sanity"); ::breakpoint(); } } while (0);
618 assert(!C->method()->holder()->is_not_initialized(), "initialization should have been started")do { if (!(!C->method()->holder()->is_not_initialized
())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 896, "assert(" "!C->method()->holder()->is_not_initialized()"
") failed", "initialization should have been started"); ::breakpoint
(); } } while (0);
619
620 Label L_skip_barrier;
621 Register klass = rscratch1;
622
623 ___masm. mov_metadata(klass, C->method()->holder()->constant_encoding());
624 ___masm. clinit_barrier(klass, r15_thread, &L_skip_barrier /*L_fast_path*/);
625
626 ___masm. jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub())); // slow path
627
628 ___masm. bind(L_skip_barrier);
629 }
630
631 ___masm. verified_entry(framesize, C->output()->need_stack_bang(bangsize)?bangsize:0, false, C->stub_function() != NULL__null);
632
633 C->output()->set_frame_complete(cbuf.insts_size());
634
635 if (C->has_mach_constant_base_node()) {
636 // NOTE: We set the table base offset here because users might be
637 // emitted before MachConstantBaseNode.
638 ConstantTable& constant_table = C->output()->constant_table();
639 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
640 }
641}
642
643uint MachPrologNode::size(PhaseRegAlloc* ra_) const
644{
645 return MachNode::size(ra_); // too many variables; just compute it
646 // the hard way
647}
648
649int MachPrologNode::reloc() const
650{
651 return 0; // a large enough number
652}
653
654//=============================================================================
655#ifndef PRODUCT
656void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const
657{
658 Compile* C = ra_->C;
659 if (generate_vzeroupper(C)) {
660 st->print("vzeroupper");
661 st->cr(); st->print("\t");
662 }
663
664 int framesize = C->output()->frame_size_in_bytes();
665 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned")do { if (!((framesize & (StackAlignmentInBytes-1)) == 0))
{ (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 943, "assert(" "(framesize & (StackAlignmentInBytes-1)) == 0"
") failed", "frame size not aligned"); ::breakpoint(); } } while
(0);
666 // Remove word for return adr already pushed
667 // and RBP
668 framesize -= 2*wordSize;
669
670 if (framesize) {
671 st->print_cr("addq rsp, %d\t# Destroy frame", framesize);
672 st->print("\t");
673 }
674
675 st->print_cr("popq rbp");
676 if (do_polling() && C->is_method_compilation()) {
677 st->print("\t");
678 st->print_cr("cmpq rsp, poll_offset[r15_thread] \n\t"
679 "ja #safepoint_stub\t"
680 "# Safepoint: poll for GC");
681 }
682}
683#endif
684
685void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
686{
687 Compile* C = ra_->C;
688 MacroAssembler _masm(&cbuf);
689
690 if (generate_vzeroupper(C)) {
691 // Clear upper bits of YMM registers when current compiled code uses
692 // wide vectors to avoid AVX <-> SSE transition penalty during call.
693 ___masm. vzeroupper();
694 }
695
696 int framesize = C->output()->frame_size_in_bytes();
697 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned")do { if (!((framesize & (StackAlignmentInBytes-1)) == 0))
{ (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 975, "assert(" "(framesize & (StackAlignmentInBytes-1)) == 0"
") failed", "frame size not aligned"); ::breakpoint(); } } while
(0);
698 // Remove word for return adr already pushed
699 // and RBP
700 framesize -= 2*wordSize;
701
702 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
703
704 if (framesize) {
705 emit_opcode(cbuf, Assembler::REX_W);
706 if (framesize < 0x80) {
707 emit_opcode(cbuf, 0x83); // addq rsp, #framesize
708 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
709 emit_d8(cbuf, framesize);
710 } else {
711 emit_opcode(cbuf, 0x81); // addq rsp, #framesize
712 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
713 emit_d32(cbuf, framesize);
714 }
715 }
716
717 // popq rbp
718 emit_opcode(cbuf, 0x58 | RBP_enc);
719
720 if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
721 ___masm. reserved_stack_check();
722 }
723
724 if (do_polling() && C->is_method_compilation()) {
725 MacroAssembler _masm(&cbuf);
726 Label dummy_label;
727 Label* code_stub = &dummy_label;
728 if (!C->output()->in_scratch_emit_size()) {
729 code_stub = &C->output()->safepoint_poll_table()->add_safepoint(___masm. offset());
730 }
731 ___masm. relocate(relocInfo::poll_return_type);
732 ___masm. safepoint_poll(*code_stub, r15_thread, true /* at_return */, true /* in_nmethod */);
733 }
734}
735
736uint MachEpilogNode::size(PhaseRegAlloc* ra_) const
737{
738 return MachNode::size(ra_); // too many variables; just compute it
739 // the hard way
740}
741
742int MachEpilogNode::reloc() const
743{
744 return 2; // a large enough number
745}
746
747const Pipeline* MachEpilogNode::pipeline() const
748{
749 return MachNode::pipeline_class();
750}
751
752//=============================================================================
753
754enum RC {
755 rc_bad,
756 rc_int,
757 rc_kreg,
758 rc_float,
759 rc_stack
760};
761
762static enum RC rc_class(OptoReg::Name reg)
763{
764 if( !OptoReg::is_valid(reg) ) return rc_bad;
765
766 if (OptoReg::is_stack(reg)) return rc_stack;
767
768 VMReg r = OptoReg::as_VMReg(reg);
769
770 if (r->is_Register()) return rc_int;
771
772 if (r->is_KRegister()) return rc_kreg;
773
774 assert(r->is_XMMRegister(), "must be")do { if (!(r->is_XMMRegister())) { (*g_assert_poison) = 'X'
;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 1052, "assert(" "r->is_XMMRegister()" ") failed", "must be"
); ::breakpoint(); } } while (0);
775 return rc_float;
776}
777
778// Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
779static void vec_mov_helper(CodeBuffer *cbuf, int src_lo, int dst_lo,
780 int src_hi, int dst_hi, uint ireg, outputStream* st);
781
782void vec_spill_helper(CodeBuffer *cbuf, bool is_load,
783 int stack_offset, int reg, uint ireg, outputStream* st);
784
785static void vec_stack_to_stack_helper(CodeBuffer *cbuf, int src_offset,
786 int dst_offset, uint ireg, outputStream* st) {
787 if (cbuf) {
788 MacroAssembler _masm(cbuf);
789 switch (ireg) {
790 case Op_VecS:
791 ___masm. movq(Address(rsp, -8), rax);
792 ___masm. movl(rax, Address(rsp, src_offset));
793 ___masm. movl(Address(rsp, dst_offset), rax);
794 ___masm. movq(rax, Address(rsp, -8));
795 break;
796 case Op_VecD:
797 ___masm. pushq(Address(rsp, src_offset));
798 ___masm. popq (Address(rsp, dst_offset));
799 break;
800 case Op_VecX:
801 ___masm. pushq(Address(rsp, src_offset));
802 ___masm. popq (Address(rsp, dst_offset));
803 ___masm. pushq(Address(rsp, src_offset+8));
804 ___masm. popq (Address(rsp, dst_offset+8));
805 break;
806 case Op_VecY:
807 ___masm. vmovdqu(Address(rsp, -32), xmm0);
808 ___masm. vmovdqu(xmm0, Address(rsp, src_offset));
809 ___masm. vmovdqu(Address(rsp, dst_offset), xmm0);
810 ___masm. vmovdqu(xmm0, Address(rsp, -32));
811 break;
812 case Op_VecZ:
813 ___masm. evmovdquq(Address(rsp, -64), xmm0, 2);
814 ___masm. evmovdquq(xmm0, Address(rsp, src_offset), 2);
815 ___masm. evmovdquq(Address(rsp, dst_offset), xmm0, 2);
816 ___masm. evmovdquq(xmm0, Address(rsp, -64), 2);
817 break;
818 default:
819 ShouldNotReachHere()do { (*g_assert_poison) = 'X';; report_should_not_reach_here(
"/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 1097); ::breakpoint(); } while (0);
820 }
821#ifndef PRODUCT
822 } else {
823 switch (ireg) {
824 case Op_VecS:
825 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
826 "movl rax, [rsp + #%d]\n\t"
827 "movl [rsp + #%d], rax\n\t"
828 "movq rax, [rsp - #8]",
829 src_offset, dst_offset);
830 break;
831 case Op_VecD:
832 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
833 "popq [rsp + #%d]",
834 src_offset, dst_offset);
835 break;
836 case Op_VecX:
837 st->print("pushq [rsp + #%d]\t# 128-bit mem-mem spill\n\t"
838 "popq [rsp + #%d]\n\t"
839 "pushq [rsp + #%d]\n\t"
840 "popq [rsp + #%d]",
841 src_offset, dst_offset, src_offset+8, dst_offset+8);
842 break;
843 case Op_VecY:
844 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
845 "vmovdqu xmm0, [rsp + #%d]\n\t"
846 "vmovdqu [rsp + #%d], xmm0\n\t"
847 "vmovdqu xmm0, [rsp - #32]",
848 src_offset, dst_offset);
849 break;
850 case Op_VecZ:
851 st->print("vmovdqu [rsp - #64], xmm0\t# 512-bit mem-mem spill\n\t"
852 "vmovdqu xmm0, [rsp + #%d]\n\t"
853 "vmovdqu [rsp + #%d], xmm0\n\t"
854 "vmovdqu xmm0, [rsp - #64]",
855 src_offset, dst_offset);
856 break;
857 default:
858 ShouldNotReachHere()do { (*g_assert_poison) = 'X';; report_should_not_reach_here(
"/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 1136); ::breakpoint(); } while (0);
859 }
860#endif
861 }
862}
863
864uint MachSpillCopyNode::implementation(CodeBuffer* cbuf,
865 PhaseRegAlloc* ra_,
866 bool do_size,
867 outputStream* st) const {
868 assert(cbuf != NULL || st != NULL, "sanity")do { if (!(cbuf != __null || st != __null)) { (*g_assert_poison
) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 1146, "assert(" "cbuf != __null || st != __null" ") failed"
, "sanity"); ::breakpoint(); } } while (0);
869 // Get registers to move
870 OptoReg::Name src_second = ra_->get_reg_second(in(1));
871 OptoReg::Name src_first = ra_->get_reg_first(in(1));
872 OptoReg::Name dst_second = ra_->get_reg_second(this);
873 OptoReg::Name dst_first = ra_->get_reg_first(this);
874
875 enum RC src_second_rc = rc_class(src_second);
876 enum RC src_first_rc = rc_class(src_first);
877 enum RC dst_second_rc = rc_class(dst_second);
878 enum RC dst_first_rc = rc_class(dst_first);
879
880 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first),do { if (!(OptoReg::is_valid(src_first) && OptoReg::is_valid
(dst_first))) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 1159, "assert(" "OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first)"
") failed", "must move at least 1 register"); ::breakpoint()
; } } while (0)
881 "must move at least 1 register" )do { if (!(OptoReg::is_valid(src_first) && OptoReg::is_valid
(dst_first))) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 1159, "assert(" "OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first)"
") failed", "must move at least 1 register"); ::breakpoint()
; } } while (0);
882
883 if (src_first == dst_first && src_second == dst_second) {
884 // Self copy, no move
885 return 0;
886 }
887 if (bottom_type()->isa_vect() != NULL__null && bottom_type()->isa_vectmask() == NULL__null) {
888 uint ireg = ideal_reg();
889 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity")do { if (!((src_first_rc != rc_int && dst_first_rc !=
rc_int))) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 1167, "assert(" "(src_first_rc != rc_int && dst_first_rc != rc_int)"
") failed", "sanity"); ::breakpoint(); } } while (0);
890 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY || ireg == Op_VecZ ), "sanity")do { if (!((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX
|| ireg == Op_VecY || ireg == Op_VecZ ))) { (*g_assert_poison
) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 1168, "assert(" "(ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY || ireg == Op_VecZ )"
") failed", "sanity"); ::breakpoint(); } } while (0);
891 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
892 // mem -> mem
893 int src_offset = ra_->reg2offset(src_first);
894 int dst_offset = ra_->reg2offset(dst_first);
895 vec_stack_to_stack_helper(cbuf, src_offset, dst_offset, ireg, st);
896 } else if (src_first_rc == rc_float && dst_first_rc == rc_float ) {
897 vec_mov_helper(cbuf, src_first, dst_first, src_second, dst_second, ireg, st);
898 } else if (src_first_rc == rc_float && dst_first_rc == rc_stack ) {
899 int stack_offset = ra_->reg2offset(dst_first);
900 vec_spill_helper(cbuf, false, stack_offset, src_first, ireg, st);
901 } else if (src_first_rc == rc_stack && dst_first_rc == rc_float ) {
902 int stack_offset = ra_->reg2offset(src_first);
903 vec_spill_helper(cbuf, true, stack_offset, dst_first, ireg, st);
904 } else {
905 ShouldNotReachHere()do { (*g_assert_poison) = 'X';; report_should_not_reach_here(
"/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 1183); ::breakpoint(); } while (0);
906 }
907 return 0;
908 }
909 if (src_first_rc == rc_stack) {
910 // mem ->
911 if (dst_first_rc == rc_stack) {
912 // mem -> mem
913 assert(src_second != dst_first, "overlap")do { if (!(src_second != dst_first)) { (*g_assert_poison) = 'X'
;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 1191, "assert(" "src_second != dst_first" ") failed", "overlap"
); ::breakpoint(); } } while (0);
914 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
915 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
916 // 64-bit
917 int src_offset = ra_->reg2offset(src_first);
918 int dst_offset = ra_->reg2offset(dst_first);
919 if (cbuf) {
920 MacroAssembler _masm(cbuf);
921 ___masm. pushq(Address(rsp, src_offset));
922 ___masm. popq (Address(rsp, dst_offset));
923#ifndef PRODUCT
924 } else {
925 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
926 "popq [rsp + #%d]",
927 src_offset, dst_offset);
928#endif
929 }
930 } else {
931 // 32-bit
932 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform")do { if (!(!((src_first & 1) == 0 && src_first + 1
== src_second))) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 1210, "assert(" "!((src_first & 1) == 0 && src_first + 1 == src_second)"
") failed", "no transform"); ::breakpoint(); } } while (0);
933 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform")do { if (!(!((dst_first & 1) == 0 && dst_first + 1
== dst_second))) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 1211, "assert(" "!((dst_first & 1) == 0 && dst_first + 1 == dst_second)"
") failed", "no transform"); ::breakpoint(); } } while (0);
934 // No pushl/popl, so:
935 int src_offset = ra_->reg2offset(src_first);
936 int dst_offset = ra_->reg2offset(dst_first);
937 if (cbuf) {
938 MacroAssembler _masm(cbuf);
939 ___masm. movq(Address(rsp, -8), rax);
940 ___masm. movl(rax, Address(rsp, src_offset));
941 ___masm. movl(Address(rsp, dst_offset), rax);
942 ___masm. movq(rax, Address(rsp, -8));
943#ifndef PRODUCT
944 } else {
945 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
946 "movl rax, [rsp + #%d]\n\t"
947 "movl [rsp + #%d], rax\n\t"
948 "movq rax, [rsp - #8]",
949 src_offset, dst_offset);
950#endif
951 }
952 }
953 return 0;
954 } else if (dst_first_rc == rc_int) {
955 // mem -> gpr
956 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
957 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
958 // 64-bit
959 int offset = ra_->reg2offset(src_first);
960 if (cbuf) {
961 MacroAssembler _masm(cbuf);
962 ___masm. movq(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
963#ifndef PRODUCT
964 } else {
965 st->print("movq %s, [rsp + #%d]\t# spill",
966 Matcher::regName[dst_first],
967 offset);
968#endif
969 }
970 } else {
971 // 32-bit
972 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform")do { if (!(!((src_first & 1) == 0 && src_first + 1
== src_second))) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 1250, "assert(" "!((src_first & 1) == 0 && src_first + 1 == src_second)"
") failed", "no transform"); ::breakpoint(); } } while (0);
973 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform")do { if (!(!((dst_first & 1) == 0 && dst_first + 1
== dst_second))) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 1251, "assert(" "!((dst_first & 1) == 0 && dst_first + 1 == dst_second)"
") failed", "no transform"); ::breakpoint(); } } while (0);
974 int offset = ra_->reg2offset(src_first);
975 if (cbuf) {
976 MacroAssembler _masm(cbuf);
977 ___masm. movl(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
978#ifndef PRODUCT
979 } else {
980 st->print("movl %s, [rsp + #%d]\t# spill",
981 Matcher::regName[dst_first],
982 offset);
983#endif
984 }
985 }
986 return 0;
987 } else if (dst_first_rc == rc_float) {
988 // mem-> xmm
989 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
990 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
991 // 64-bit
992 int offset = ra_->reg2offset(src_first);
993 if (cbuf) {
994 MacroAssembler _masm(cbuf);
995 ___masm. movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
996#ifndef PRODUCT
997 } else {
998 st->print("%s %s, [rsp + #%d]\t# spill",
999 UseXmmLoadAndClearUpper ? "movsd " : "movlpd",
1000 Matcher::regName[dst_first],
1001 offset);
1002#endif
1003 }
1004 } else {
1005 // 32-bit
1006 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform")do { if (!(!((src_first & 1) == 0 && src_first + 1
== src_second))) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 1284, "assert(" "!((src_first & 1) == 0 && src_first + 1 == src_second)"
") failed", "no transform"); ::breakpoint(); } } while (0);
1007 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform")do { if (!(!((dst_first & 1) == 0 && dst_first + 1
== dst_second))) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 1285, "assert(" "!((dst_first & 1) == 0 && dst_first + 1 == dst_second)"
") failed", "no transform"); ::breakpoint(); } } while (0);
1008 int offset = ra_->reg2offset(src_first);
1009 if (cbuf) {
1010 MacroAssembler _masm(cbuf);
1011 ___masm. movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1012#ifndef PRODUCT
1013 } else {
1014 st->print("movss %s, [rsp + #%d]\t# spill",
1015 Matcher::regName[dst_first],
1016 offset);
1017#endif
1018 }
1019 }
1020 return 0;
1021 } else if (dst_first_rc == rc_kreg) {
1022 // mem -> kreg
1023 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1024 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1025 // 64-bit
1026 int offset = ra_->reg2offset(src_first);
1027 if (cbuf) {
1028 MacroAssembler _masm(cbuf);
1029 ___masm. kmov(as_KRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1030#ifndef PRODUCT
1031 } else {
1032 st->print("kmovq %s, [rsp + #%d]\t# spill",
1033 Matcher::regName[dst_first],
1034 offset);
1035#endif
1036 }
1037 }
1038 return 0;
1039 }
1040 } else if (src_first_rc == rc_int) {
1041 // gpr ->
1042 if (dst_first_rc == rc_stack) {
1043 // gpr -> mem
1044 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1045 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1046 // 64-bit
1047 int offset = ra_->reg2offset(dst_first);
1048 if (cbuf) {
1049 MacroAssembler _masm(cbuf);
1050 ___masm. movq(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1051#ifndef PRODUCT
1052 } else {
1053 st->print("movq [rsp + #%d], %s\t# spill",
1054 offset,
1055 Matcher::regName[src_first]);
1056#endif
1057 }
1058 } else {
1059 // 32-bit
1060 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform")do { if (!(!((src_first & 1) == 0 && src_first + 1
== src_second))) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 1338, "assert(" "!((src_first & 1) == 0 && src_first + 1 == src_second)"
") failed", "no transform"); ::breakpoint(); } } while (0);
1061 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform")do { if (!(!((dst_first & 1) == 0 && dst_first + 1
== dst_second))) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 1339, "assert(" "!((dst_first & 1) == 0 && dst_first + 1 == dst_second)"
") failed", "no transform"); ::breakpoint(); } } while (0);
1062 int offset = ra_->reg2offset(dst_first);
1063 if (cbuf) {
1064 MacroAssembler _masm(cbuf);
1065 ___masm. movl(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1066#ifndef PRODUCT
1067 } else {
1068 st->print("movl [rsp + #%d], %s\t# spill",
1069 offset,
1070 Matcher::regName[src_first]);
1071#endif
1072 }
1073 }
1074 return 0;
1075 } else if (dst_first_rc == rc_int) {
1076 // gpr -> gpr
1077 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1078 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1079 // 64-bit
1080 if (cbuf) {
1081 MacroAssembler _masm(cbuf);
1082 ___masm. movq(as_Register(Matcher::_regEncode[dst_first]),
1083 as_Register(Matcher::_regEncode[src_first]));
1084#ifndef PRODUCT
1085 } else {
1086 st->print("movq %s, %s\t# spill",
1087 Matcher::regName[dst_first],
1088 Matcher::regName[src_first]);
1089#endif
1090 }
1091 return 0;
1092 } else {
1093 // 32-bit
1094 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform")do { if (!(!((src_first & 1) == 0 && src_first + 1
== src_second))) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 1372, "assert(" "!((src_first & 1) == 0 && src_first + 1 == src_second)"
") failed", "no transform"); ::breakpoint(); } } while (0);
1095 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform")do { if (!(!((dst_first & 1) == 0 && dst_first + 1
== dst_second))) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 1373, "assert(" "!((dst_first & 1) == 0 && dst_first + 1 == dst_second)"
") failed", "no transform"); ::breakpoint(); } } while (0);
1096 if (cbuf) {
1097 MacroAssembler _masm(cbuf);
1098 ___masm. movl(as_Register(Matcher::_regEncode[dst_first]),
1099 as_Register(Matcher::_regEncode[src_first]));
1100#ifndef PRODUCT
1101 } else {
1102 st->print("movl %s, %s\t# spill",
1103 Matcher::regName[dst_first],
1104 Matcher::regName[src_first]);
1105#endif
1106 }
1107 return 0;
1108 }
1109 } else if (dst_first_rc == rc_float) {
1110 // gpr -> xmm
1111 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1112 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1113 // 64-bit
1114 if (cbuf) {
1115 MacroAssembler _masm(cbuf);
1116 ___masm. movdq( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1117#ifndef PRODUCT
1118 } else {
1119 st->print("movdq %s, %s\t# spill",
1120 Matcher::regName[dst_first],
1121 Matcher::regName[src_first]);
1122#endif
1123 }
1124 } else {
1125 // 32-bit
1126 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform")do { if (!(!((src_first & 1) == 0 && src_first + 1
== src_second))) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 1404, "assert(" "!((src_first & 1) == 0 && src_first + 1 == src_second)"
") failed", "no transform"); ::breakpoint(); } } while (0);
1127 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform")do { if (!(!((dst_first & 1) == 0 && dst_first + 1
== dst_second))) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 1405, "assert(" "!((dst_first & 1) == 0 && dst_first + 1 == dst_second)"
") failed", "no transform"); ::breakpoint(); } } while (0);
1128 if (cbuf) {
1129 MacroAssembler _masm(cbuf);
1130 ___masm. movdl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1131#ifndef PRODUCT
1132 } else {
1133 st->print("movdl %s, %s\t# spill",
1134 Matcher::regName[dst_first],
1135 Matcher::regName[src_first]);
1136#endif
1137 }
1138 }
1139 return 0;
1140 } else if (dst_first_rc == rc_kreg) {
1141 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1142 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1143 // 64-bit
1144 if (cbuf) {
1145 MacroAssembler _masm(cbuf);
1146 ___masm. kmov(as_KRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1147 #ifndef PRODUCT
1148 } else {
1149 st->print("kmovq %s, %s\t# spill",
1150 Matcher::regName[dst_first],
1151 Matcher::regName[src_first]);
1152 #endif
1153 }
1154 }
1155 Unimplemented()do { (*g_assert_poison) = 'X';; report_unimplemented("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 1433); ::breakpoint(); } while (0);
1156 return 0;
1157 }
1158 } else if (src_first_rc == rc_float) {
1159 // xmm ->
1160 if (dst_first_rc == rc_stack) {
1161 // xmm -> mem
1162 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1163 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1164 // 64-bit
1165 int offset = ra_->reg2offset(dst_first);
1166 if (cbuf) {
1167 MacroAssembler _masm(cbuf);
1168 ___masm. movdbl( Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1169#ifndef PRODUCT
1170 } else {
1171 st->print("movsd [rsp + #%d], %s\t# spill",
1172 offset,
1173 Matcher::regName[src_first]);
1174#endif
1175 }
1176 } else {
1177 // 32-bit
1178 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform")do { if (!(!((src_first & 1) == 0 && src_first + 1
== src_second))) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 1456, "assert(" "!((src_first & 1) == 0 && src_first + 1 == src_second)"
") failed", "no transform"); ::breakpoint(); } } while (0);
1179 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform")do { if (!(!((dst_first & 1) == 0 && dst_first + 1
== dst_second))) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 1457, "assert(" "!((dst_first & 1) == 0 && dst_first + 1 == dst_second)"
") failed", "no transform"); ::breakpoint(); } } while (0);
1180 int offset = ra_->reg2offset(dst_first);
1181 if (cbuf) {
1182 MacroAssembler _masm(cbuf);
1183 ___masm. movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1184#ifndef PRODUCT
1185 } else {
1186 st->print("movss [rsp + #%d], %s\t# spill",
1187 offset,
1188 Matcher::regName[src_first]);
1189#endif
1190 }
1191 }
1192 return 0;
1193 } else if (dst_first_rc == rc_int) {
1194 // xmm -> gpr
1195 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1196 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1197 // 64-bit
1198 if (cbuf) {
1199 MacroAssembler _masm(cbuf);
1200 ___masm. movdq( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1201#ifndef PRODUCT
1202 } else {
1203 st->print("movdq %s, %s\t# spill",
1204 Matcher::regName[dst_first],
1205 Matcher::regName[src_first]);
1206#endif
1207 }
1208 } else {
1209 // 32-bit
1210 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform")do { if (!(!((src_first & 1) == 0 && src_first + 1
== src_second))) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 1488, "assert(" "!((src_first & 1) == 0 && src_first + 1 == src_second)"
") failed", "no transform"); ::breakpoint(); } } while (0);
1211 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform")do { if (!(!((dst_first & 1) == 0 && dst_first + 1
== dst_second))) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 1489, "assert(" "!((dst_first & 1) == 0 && dst_first + 1 == dst_second)"
") failed", "no transform"); ::breakpoint(); } } while (0);
1212 if (cbuf) {
1213 MacroAssembler _masm(cbuf);
1214 ___masm. movdl( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1215#ifndef PRODUCT
1216 } else {
1217 st->print("movdl %s, %s\t# spill",
1218 Matcher::regName[dst_first],
1219 Matcher::regName[src_first]);
1220#endif
1221 }
1222 }
1223 return 0;
1224 } else if (dst_first_rc == rc_float) {
1225 // xmm -> xmm
1226 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1227 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1228 // 64-bit
1229 if (cbuf) {
1230 MacroAssembler _masm(cbuf);
1231 ___masm. movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1232#ifndef PRODUCT
1233 } else {
1234 st->print("%s %s, %s\t# spill",
1235 UseXmmRegToRegMoveAll ? "movapd" : "movsd ",
1236 Matcher::regName[dst_first],
1237 Matcher::regName[src_first]);
1238#endif
1239 }
1240 } else {
1241 // 32-bit
1242 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform")do { if (!(!((src_first & 1) == 0 && src_first + 1
== src_second))) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 1520, "assert(" "!((src_first & 1) == 0 && src_first + 1 == src_second)"
") failed", "no transform"); ::breakpoint(); } } while (0);
1243 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform")do { if (!(!((dst_first & 1) == 0 && dst_first + 1
== dst_second))) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 1521, "assert(" "!((dst_first & 1) == 0 && dst_first + 1 == dst_second)"
") failed", "no transform"); ::breakpoint(); } } while (0);
1244 if (cbuf) {
1245 MacroAssembler _masm(cbuf);
1246 ___masm. movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1247#ifndef PRODUCT
1248 } else {
1249 st->print("%s %s, %s\t# spill",
1250 UseXmmRegToRegMoveAll ? "movaps" : "movss ",
1251 Matcher::regName[dst_first],
1252 Matcher::regName[src_first]);
1253#endif
1254 }
1255 }
1256 return 0;
1257 } else if (dst_first_rc == rc_kreg) {
1258 assert(false, "Illegal spilling")do { if (!(false)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 1536, "assert(" "false" ") failed", "Illegal spilling"); ::
breakpoint(); } } while (0);
1259 return 0;
1260 }
1261 } else if (src_first_rc == rc_kreg) {
1262 if (dst_first_rc == rc_stack) {
1263 // mem -> kreg
1264 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1265 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1266 // 64-bit
1267 int offset = ra_->reg2offset(dst_first);
1268 if (cbuf) {
1269 MacroAssembler _masm(cbuf);
1270 ___masm. kmov(Address(rsp, offset), as_KRegister(Matcher::_regEncode[src_first]));
1271#ifndef PRODUCT
1272 } else {
1273 st->print("kmovq [rsp + #%d] , %s\t# spill",
1274 offset,
1275 Matcher::regName[src_first]);
1276#endif
1277 }
1278 }
1279 return 0;
1280 } else if (dst_first_rc == rc_int) {
1281 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1282 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1283 // 64-bit
1284 if (cbuf) {
1285 MacroAssembler _masm(cbuf);
1286 ___masm. kmov(as_Register(Matcher::_regEncode[dst_first]), as_KRegister(Matcher::_regEncode[src_first]));
1287#ifndef PRODUCT
1288 } else {
1289 st->print("kmovq %s, %s\t# spill",
1290 Matcher::regName[dst_first],
1291 Matcher::regName[src_first]);
1292#endif
1293 }
1294 }
1295 Unimplemented()do { (*g_assert_poison) = 'X';; report_unimplemented("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 1573); ::breakpoint(); } while (0);
1296 return 0;
1297 } else if (dst_first_rc == rc_kreg) {
1298 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1299 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1300 // 64-bit
1301 if (cbuf) {
1302 MacroAssembler _masm(cbuf);
1303 ___masm. kmov(as_KRegister(Matcher::_regEncode[dst_first]), as_KRegister(Matcher::_regEncode[src_first]));
1304#ifndef PRODUCT
1305 } else {
1306 st->print("kmovq %s, %s\t# spill",
1307 Matcher::regName[dst_first],
1308 Matcher::regName[src_first]);
1309#endif
1310 }
1311 }
1312 return 0;
1313 } else if (dst_first_rc == rc_float) {
1314 assert(false, "Illegal spill")do { if (!(false)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 1592, "assert(" "false" ") failed", "Illegal spill"); ::breakpoint
(); } } while (0);
1315 return 0;
1316 }
1317 }
1318
1319 assert(0," foo ")do { if (!(0)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 1597, "assert(" "0" ") failed", " foo "); ::breakpoint(); }
} while (0);
1320 Unimplemented()do { (*g_assert_poison) = 'X';; report_unimplemented("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 1598); ::breakpoint(); } while (0);
1321 return 0;
1322}
1323
1324#ifndef PRODUCT
1325void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1326 implementation(NULL__null, ra_, false, st);
1327}
1328#endif
1329
1330void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1331 implementation(&cbuf, ra_, false, NULL__null);
1332}
1333
1334uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1335 return MachNode::size(ra_);
1336}
1337
1338//=============================================================================
1339#ifndef PRODUCT
1340void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1341{
1342 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1343 int reg = ra_->get_reg_first(this);
1344 st->print("leaq %s, [rsp + #%d]\t# box lock",
1345 Matcher::regName[reg], offset);
1346}
1347#endif
1348
1349void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1350{
1351 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1352 int reg = ra_->get_encode(this);
1353 if (offset >= 0x80) {
1354 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1355 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1356 emit_rm(cbuf, 0x2, reg & 7, 0x04);
1357 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1358 emit_d32(cbuf, offset);
1359 } else {
1360 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1361 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1362 emit_rm(cbuf, 0x1, reg & 7, 0x04);
1363 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1364 emit_d8(cbuf, offset);
1365 }
1366}
1367
1368uint BoxLockNode::size(PhaseRegAlloc *ra_) const
1369{
1370 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1371 return (offset < 0x80) ? 5 : 8; // REX
1372}
1373
1374//=============================================================================
1375#ifndef PRODUCT
1376void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1377{
1378 if (UseCompressedClassPointers) {
1379 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1380 st->print_cr("\tdecode_klass_not_null rscratch1, rscratch1");
1381 st->print_cr("\tcmpq rax, rscratch1\t # Inline cache check");
1382 } else {
1383 st->print_cr("\tcmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t"
1384 "# Inline cache check");
1385 }
1386 st->print_cr("\tjne SharedRuntime::_ic_miss_stub");
1387 st->print_cr("\tnop\t# nops to align entry point");
1388}
1389#endif
1390
1391void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1392{
1393 MacroAssembler masm(&cbuf);
1394 uint insts_size = cbuf.insts_size();
1395 if (UseCompressedClassPointers) {
1396 masm.load_klass(rscratch1, j_rarg0, rscratch2);
1397 masm.cmpptr(rax, rscratch1);
1398 } else {
1399 masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes()));
1400 }
1401
1402 masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1403
1404 /* WARNING these NOPs are critical so that verified entry point is properly
1405 4 bytes aligned for patching by NativeJump::patch_verified_entry() */
1406 int nops_cnt = 4 - ((cbuf.insts_size() - insts_size) & 0x3);
1407 if (OptoBreakpoint) {
1408 // Leave space for int3
1409 nops_cnt -= 1;
1410 }
1411 nops_cnt &= 0x3; // Do not add nops if code is aligned.
1412 if (nops_cnt > 0)
1413 masm.nop(nops_cnt);
1414}
1415
1416uint MachUEPNode::size(PhaseRegAlloc* ra_) const
1417{
1418 return MachNode::size(ra_); // too many variables; just compute it
1419 // the hard way
1420}
1421
1422
1423//=============================================================================
1424
1425const bool Matcher::supports_vector_calling_convention(void) {
1426 if (EnableVectorSupport && UseVectorStubs) {
1427 return true;
1428 }
1429 return false;
1430}
1431
1432OptoRegPair Matcher::vector_return_value(uint ideal_reg) {
1433 assert(EnableVectorSupport && UseVectorStubs, "sanity")do { if (!(EnableVectorSupport && UseVectorStubs)) { (
*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 1711, "assert(" "EnableVectorSupport && UseVectorStubs"
") failed", "sanity"); ::breakpoint(); } } while (0);
1434 int lo = XMM0_num;
1435 int hi = XMM0b_num;
1436 if (ideal_reg == Op_VecX) hi = XMM0d_num;
1437 else if (ideal_reg == Op_VecY) hi = XMM0h_num;
1438 else if (ideal_reg == Op_VecZ) hi = XMM0p_num;
1439 return OptoRegPair(hi, lo);
1440}
1441
1442// Is this branch offset short enough that a short branch can be used?
1443//
1444// NOTE: If the platform does not provide any short branch variants, then
1445// this method should return false for offset 0.
1446bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1447 // The passed offset is relative to address of the branch.
1448 // On 86 a branch displacement is calculated relative to address
1449 // of a next instruction.
1450 offset -= br_size;
1451
1452 // the short version of jmpConUCF2 contains multiple branches,
1453 // making the reach slightly less
1454 if (rule == jmpConUCF2_rule)
1455 return (-126 <= offset && offset <= 125);
1456 return (-128 <= offset && offset <= 127);
1457}
1458
1459// Return whether or not this register is ever used as an argument.
1460// This function is used on startup to build the trampoline stubs in
1461// generateOptoStub. Registers not mentioned will be killed by the VM
1462// call in the trampoline, and arguments in those registers not be
1463// available to the callee.
1464bool Matcher::can_be_java_arg(int reg)
1465{
1466 return
1467 reg == RDI_num || reg == RDI_H_num ||
1468 reg == RSI_num || reg == RSI_H_num ||
1469 reg == RDX_num || reg == RDX_H_num ||
1470 reg == RCX_num || reg == RCX_H_num ||
1471 reg == R8_num || reg == R8_H_num ||
1472 reg == R9_num || reg == R9_H_num ||
1473 reg == R12_num || reg == R12_H_num ||
1474 reg == XMM0_num || reg == XMM0b_num ||
1475 reg == XMM1_num || reg == XMM1b_num ||
1476 reg == XMM2_num || reg == XMM2b_num ||
1477 reg == XMM3_num || reg == XMM3b_num ||
1478 reg == XMM4_num || reg == XMM4b_num ||
1479 reg == XMM5_num || reg == XMM5b_num ||
1480 reg == XMM6_num || reg == XMM6b_num ||
1481 reg == XMM7_num || reg == XMM7b_num;
1482}
1483
1484bool Matcher::is_spillable_arg(int reg)
1485{
1486 return can_be_java_arg(reg);
1487}
1488
1489uint Matcher::int_pressure_limit()
1490{
1491 return (INTPRESSURE == -1) ? _INT_REG_mask.Size() : INTPRESSURE;
1492}
1493
1494uint Matcher::float_pressure_limit()
1495{
1496 // After experiment around with different values, the following default threshold
1497 // works best for LCM's register pressure scheduling on x64.
1498 uint dec_count = VM_Version::supports_evex() ? 4 : 2;
1499 uint default_float_pressure_threshold = _FLOAT_REG_mask.Size() - dec_count;
1500 return (FLOATPRESSURE == -1) ? default_float_pressure_threshold : FLOATPRESSURE;
1501}
1502
1503bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1504 // In 64 bit mode a code which use multiply when
1505 // devisor is constant is faster than hardware
1506 // DIV instruction (it uses MulHiL).
1507 return false;
1508}
1509
1510// Register for DIVI projection of divmodI
1511RegMask Matcher::divI_proj_mask() {
1512 return INT_RAX_REG_mask();
1513}
1514
1515// Register for MODI projection of divmodI
1516RegMask Matcher::modI_proj_mask() {
1517 return INT_RDX_REG_mask();
1518}
1519
1520// Register for DIVL projection of divmodL
1521RegMask Matcher::divL_proj_mask() {
1522 return LONG_RAX_REG_mask();
1523}
1524
1525// Register for MODL projection of divmodL
1526RegMask Matcher::modL_proj_mask() {
1527 return LONG_RDX_REG_mask();
1528}
1529
1530// Register for saving SP into on method handle invokes. Not used on x86_64.
1531const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1532 return NO_REG_mask();
1533}
1534
1535
1536#line 1536 "ad_x86.cpp"
1537
1538
1539//SourceForm
1540
1541#line 1258 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
1542
1543
1544#include "opto/addnode.hpp"
1545#include "c2_intelJccErratum_x86.hpp"
1546
1547void PhaseOutput::pd_perform_mach_node_analysis() {
1548 if (VM_Version::has_intel_jcc_erratum()) {
1549 int extra_padding = IntelJccErratum::tag_affected_machnodes(C, C->cfg(), C->regalloc());
1550 _buf_sizes._code += extra_padding;
1551 }
1552}
1553
1554int MachNode::pd_alignment_required() const {
1555 if (VM_Version::has_intel_jcc_erratum() && IntelJccErratum::is_jcc_erratum_branch(this)) {
1556 // Conservatively add worst case padding. We assume that relocInfo::addr_unit() is 1 on x86.
1557 return IntelJccErratum::largest_jcc_size() + 1;
1558 } else {
1559 return 1;
1560 }
1561}
1562
1563int MachNode::compute_padding(int current_offset) const {
1564 if (flags() & Node::PD::Flag_intel_jcc_erratum) {
1565 Compile* C = Compile::current();
1566 PhaseOutput* output = C->output();
1567 Block* block = output->block();
1568 int index = output->index();
1569 return IntelJccErratum::compute_padding(current_offset, this, block, index, C->regalloc());
1570 } else {
1571 return 0;
1572 }
1573}
1574
1575// Emit exception handler code.
1576// Stuff framesize into a register and call a VM stub routine.
1577int HandlerImpl::emit_exception_handler(CodeBuffer& cbuf) {
1578
1579 // Note that the code buffer's insts_mark is always relative to insts.
1580 // That's why we must use the macroassembler to generate a handler.
1581 C2_MacroAssembler _masm(&cbuf);
1582 address base = ___masm. start_a_stub(size_exception_handler());
1583 if (base == NULL__null) {
1584 ciEnv::current()->record_failure("CodeCache is full");
1585 return 0; // CodeBuffer::expand failed
1586 }
1587 int offset = ___masm. offset();
1588 ___masm. jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
1589 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow")do { if (!(_masm. offset() - offset <= (int) size_exception_handler
())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 1305, "assert(" "_masm. offset() - offset <= (int) size_exception_handler()"
") failed", "overflow"); ::breakpoint(); } } while (0);
1590 ___masm. end_a_stub();
1591 return offset;
1592}
1593
1594// Emit deopt handler code.
1595int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) {
1596
1597 // Note that the code buffer's insts_mark is always relative to insts.
1598 // That's why we must use the macroassembler to generate a handler.
1599 C2_MacroAssembler _masm(&cbuf);
1600 address base = ___masm. start_a_stub(size_deopt_handler());
1601 if (base == NULL__null) {
1602 ciEnv::current()->record_failure("CodeCache is full");
1603 return 0; // CodeBuffer::expand failed
1604 }
1605 int offset = ___masm. offset();
1606
1607#ifdef _LP641
1608 address the_pc = (address) ___masm. pc();
1609 Label next;
1610 // push a "the_pc" on the stack without destroying any registers
1611 // as they all may be live.
1612
1613 // push address of "next"
1614 ___masm. call(next, relocInfo::none); // reloc none is fine since it is a disp32
1615 ___masm. bind(next);
1616 // adjust it so it matches "the_pc"
1617 ___masm. subptr(Address(rsp, 0), ___masm. offset() - offset);
1618#else
1619 InternalAddress here(___masm. pc());
1620 ___masm. pushptr(here.addr());
1621#endif
1622
1623 ___masm. jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1624 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow %d", (__ offset() - offset))do { if (!(_masm. offset() - offset <= (int) size_deopt_handler
())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 1340, "assert(" "_masm. offset() - offset <= (int) size_deopt_handler()"
") failed", "overflow %d", (_masm. offset() - offset)); ::breakpoint
(); } } while (0);
1625 ___masm. end_a_stub();
1626 return offset;
1627}
1628
1629Assembler::Width widthForType(BasicType bt) {
1630 if (bt == T_BYTE) {
1631 return Assembler::B;
1632 } else if (bt == T_SHORT) {
1633 return Assembler::W;
1634 } else if (bt == T_INT) {
1635 return Assembler::D;
1636 } else {
1637 assert(bt == T_LONG, "not a long: %s", type2name(bt))do { if (!(bt == T_LONG)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
1353, "assert(" "bt == T_LONG" ") failed", "not a long: %s",
type2name(bt)); ::breakpoint(); } } while (0);
1638 return Assembler::Q;
1639 }
1640}
1641
1642//=============================================================================
1643
1644 // Float masks come from different places depending on platform.
1645#ifdef _LP641
1646 static address float_signmask() { return StubRoutines::x86::float_sign_mask(); }
1647 static address float_signflip() { return StubRoutines::x86::float_sign_flip(); }
1648 static address double_signmask() { return StubRoutines::x86::double_sign_mask(); }
1649 static address double_signflip() { return StubRoutines::x86::double_sign_flip(); }
1650#else
1651 static address float_signmask() { return (address)float_signmask_pool; }
1652 static address float_signflip() { return (address)float_signflip_pool; }
1653 static address double_signmask() { return (address)double_signmask_pool; }
1654 static address double_signflip() { return (address)double_signflip_pool; }
1655#endif
1656 static address vector_short_to_byte_mask() { return StubRoutines::x86::vector_short_to_byte_mask(); }
1657 static address vector_int_to_byte_mask() { return StubRoutines::x86::vector_int_to_byte_mask(); }
1658 static address vector_byte_perm_mask() { return StubRoutines::x86::vector_byte_perm_mask(); }
1659 static address vector_long_sign_mask() { return StubRoutines::x86::vector_long_sign_mask(); }
1660 static address vector_all_bits_set() { return StubRoutines::x86::vector_all_bits_set(); }
1661 static address vector_int_mask_cmp_bits() { return StubRoutines::x86::vector_int_mask_cmp_bits(); }
1662 static address vector_int_to_short_mask() { return StubRoutines::x86::vector_int_to_short_mask(); }
1663 static address vector_byte_shufflemask() { return StubRoutines::x86::vector_byte_shuffle_mask(); }
1664 static address vector_short_shufflemask() { return StubRoutines::x86::vector_short_shuffle_mask(); }
1665 static address vector_int_shufflemask() { return StubRoutines::x86::vector_int_shuffle_mask(); }
1666 static address vector_long_shufflemask() { return StubRoutines::x86::vector_long_shuffle_mask(); }
1667 static address vector_32_bit_mask() { return StubRoutines::x86::vector_32_bit_mask(); }
1668 static address vector_64_bit_mask() { return StubRoutines::x86::vector_64_bit_mask(); }
1669 static address vector_float_signflip() { return StubRoutines::x86::vector_float_sign_flip();}
1670 static address vector_double_signflip() { return StubRoutines::x86::vector_double_sign_flip();}
1671
1672//=============================================================================
1673const bool Matcher::match_rule_supported(int opcode) {
1674 if (!has_match_rule(opcode)) {
1675 return false; // no match rule present
1676 }
1677 const bool is_LP64 = LP64_ONLY(true)true NOT_LP64(false);
1678 switch (opcode) {
1679 case Op_AbsVL:
1680 case Op_StoreVectorScatter:
1681 if (UseAVX < 3) {
1682 return false;
1683 }
1684 break;
1685 case Op_PopCountI:
1686 case Op_PopCountL:
1687 if (!UsePopCountInstruction) {
1688 return false;
1689 }
1690 break;
1691 case Op_PopCountVI:
1692 if (!UsePopCountInstruction || !VM_Version::supports_avx512_vpopcntdq()) {
1693 return false;
1694 }
1695 break;
1696 case Op_MulVI:
1697 if ((UseSSE < 4) && (UseAVX < 1)) { // only with SSE4_1 or AVX
1698 return false;
1699 }
1700 break;
1701 case Op_MulVL:
1702 if (UseSSE < 4) { // only with SSE4_1 or AVX
1703 return false;
1704 }
1705 break;
1706 case Op_MulReductionVL:
1707 if (VM_Version::supports_avx512dq() == false) {
1708 return false;
1709 }
1710 break;
1711 case Op_AddReductionVL:
1712 if (UseSSE < 2) { // requires at least SSE2
1713 return false;
1714 }
1715 break;
1716 case Op_AbsVB:
1717 case Op_AbsVS:
1718 case Op_AbsVI:
1719 case Op_AddReductionVI:
1720 case Op_AndReductionV:
1721 case Op_OrReductionV:
1722 case Op_XorReductionV:
1723 if (UseSSE < 3) { // requires at least SSSE3
1724 return false;
1725 }
1726 break;
1727 case Op_VectorLoadShuffle:
1728 case Op_VectorRearrange:
1729 case Op_MulReductionVI:
1730 if (UseSSE < 4) { // requires at least SSE4
1731 return false;
1732 }
1733 break;
1734 case Op_SqrtVD:
1735 case Op_SqrtVF:
1736 case Op_VectorMaskCmp:
1737 case Op_VectorCastB2X:
1738 case Op_VectorCastS2X:
1739 case Op_VectorCastI2X:
1740 case Op_VectorCastL2X:
1741 case Op_VectorCastF2X:
1742 case Op_VectorCastD2X:
1743 if (UseAVX < 1) { // enabled for AVX only
1744 return false;
1745 }
1746 break;
1747 case Op_CompareAndSwapL:
1748#ifdef _LP641
1749 case Op_CompareAndSwapP:
1750#endif
1751 if (!VM_Version::supports_cx8()) {
1752 return false;
1753 }
1754 break;
1755 case Op_CMoveVF:
1756 case Op_CMoveVD:
1757 if (UseAVX < 1) { // enabled for AVX only
1758 return false;
1759 }
1760 break;
1761 case Op_StrIndexOf:
1762 if (!UseSSE42Intrinsics) {
1763 return false;
1764 }
1765 break;
1766 case Op_StrIndexOfChar:
1767 if (!UseSSE42Intrinsics) {
1768 return false;
1769 }
1770 break;
1771 case Op_OnSpinWait:
1772 if (VM_Version::supports_on_spin_wait() == false) {
1773 return false;
1774 }
1775 break;
1776 case Op_MulVB:
1777 case Op_LShiftVB:
1778 case Op_RShiftVB:
1779 case Op_URShiftVB:
1780 case Op_VectorInsert:
1781 case Op_VectorLoadMask:
1782 case Op_VectorStoreMask:
1783 case Op_VectorBlend:
1784 if (UseSSE < 4) {
1785 return false;
1786 }
1787 break;
1788#ifdef _LP641
1789 case Op_MaxD:
1790 case Op_MaxF:
1791 case Op_MinD:
1792 case Op_MinF:
1793 if (UseAVX < 1) { // enabled for AVX only
1794 return false;
1795 }
1796 break;
1797#endif
1798 case Op_CacheWB:
1799 case Op_CacheWBPreSync:
1800 case Op_CacheWBPostSync:
1801 if (!VM_Version::supports_data_cache_line_flush()) {
1802 return false;
1803 }
1804 break;
1805 case Op_ExtractB:
1806 case Op_ExtractL:
1807 case Op_ExtractI:
1808 case Op_RoundDoubleMode:
1809 if (UseSSE < 4) {
1810 return false;
1811 }
1812 break;
1813 case Op_RoundDoubleModeV:
1814 if (VM_Version::supports_avx() == false) {
1815 return false; // 128bit vroundpd is not available
1816 }
1817 break;
1818 case Op_LoadVectorGather:
1819 if (UseAVX < 2) {
1820 return false;
1821 }
1822 break;
1823 case Op_FmaVD:
1824 case Op_FmaVF:
1825 if (!UseFMA) {
1826 return false;
1827 }
1828 break;
1829 case Op_MacroLogicV:
1830 if (UseAVX < 3 || !UseVectorMacroLogic) {
1831 return false;
1832 }
1833 break;
1834
1835 case Op_VectorCmpMasked:
1836 case Op_VectorMaskGen:
1837 case Op_LoadVectorMasked:
1838 case Op_StoreVectorMasked:
1839 if (!is_LP64 || UseAVX < 3 || !VM_Version::supports_bmi2()) {
1840 return false;
1841 }
1842 break;
1843 case Op_VectorMaskFirstTrue:
1844 case Op_VectorMaskLastTrue:
1845 case Op_VectorMaskTrueCount:
1846 case Op_VectorMaskToLong:
1847 if (!is_LP64 || UseAVX < 1) {
1848 return false;
1849 }
1850 break;
1851 case Op_CopySignD:
1852 case Op_CopySignF:
1853 if (UseAVX < 3 || !is_LP64) {
1854 return false;
1855 }
1856 if (!VM_Version::supports_avx512vl()) {
1857 return false;
1858 }
1859 break;
1860#ifndef _LP641
1861 case Op_AddReductionVF:
1862 case Op_AddReductionVD:
1863 case Op_MulReductionVF:
1864 case Op_MulReductionVD:
1865 if (UseSSE < 1) { // requires at least SSE
1866 return false;
1867 }
1868 break;
1869 case Op_MulAddVS2VI:
1870 case Op_RShiftVL:
1871 case Op_AbsVD:
1872 case Op_NegVD:
1873 if (UseSSE < 2) {
1874 return false;
1875 }
1876 break;
1877#endif // !LP64
1878 case Op_SignumF:
1879 if (UseSSE < 1) {
1880 return false;
1881 }
1882 break;
1883 case Op_SignumD:
1884 if (UseSSE < 2) {
1885 return false;
1886 }
1887 break;
1888 }
1889 return true; // Match rules are supported by default.
1890}
1891
1892//------------------------------------------------------------------------
1893
1894// Identify extra cases that we might want to provide match rules for vector nodes and
1895// other intrinsics guarded with vector length (vlen) and element type (bt).
1896const bool Matcher::match_rule_supported_vector(int opcode, int vlen, BasicType bt) {
1897 const bool is_LP64 = LP64_ONLY(true)true NOT_LP64(false);
1898 if (!match_rule_supported(opcode)) {
1899 return false;
1900 }
1901 // Matcher::vector_size_supported() restricts vector sizes in the following way (see Matcher::vector_width_in_bytes):
1902 // * SSE2 supports 128bit vectors for all types;
1903 // * AVX1 supports 256bit vectors only for FLOAT and DOUBLE types;
1904 // * AVX2 supports 256bit vectors for all types;
1905 // * AVX512F supports 512bit vectors only for INT, FLOAT, and DOUBLE types;
1906 // * AVX512BW supports 512bit vectors for BYTE, SHORT, and CHAR types.
1907 // There's also a limit on minimum vector size supported: 2 elements (or 4 bytes for BYTE).
1908 // And MaxVectorSize is taken into account as well.
1909 if (!vector_size_supported(bt, vlen)) {
1910 return false;
1911 }
1912 // Special cases which require vector length follow:
1913 // * implementation limitations
1914 // * some 512bit vector operations on FLOAT and DOUBLE types require AVX512DQ
1915 // * 128bit vroundpd instruction is present only in AVX1
1916 int size_in_bits = vlen * type2aelembytes(bt) * BitsPerByte;
1917 switch (opcode) {
1918 case Op_AbsVF:
1919 case Op_NegVF:
1920 if ((vlen == 16) && (VM_Version::supports_avx512dq() == false)) {
1921 return false; // 512bit vandps and vxorps are not available
1922 }
1923 break;
1924 case Op_AbsVD:
1925 case Op_NegVD:
1926 case Op_MulVL:
1927 if ((vlen == 8) && (VM_Version::supports_avx512dq() == false)) {
1928 return false; // 512bit vpmullq, vandpd and vxorpd are not available
1929 }
1930 break;
1931 case Op_CMoveVF:
1932 if (vlen != 8) {
1933 return false; // implementation limitation (only vcmov8F_reg is present)
1934 }
1935 break;
1936 case Op_RotateRightV:
1937 case Op_RotateLeftV:
1938 if (bt != T_INT && bt != T_LONG) {
1939 return false;
1940 } // fallthrough
1941 case Op_MacroLogicV:
1942 if (!VM_Version::supports_evex() ||
1943 ((size_in_bits != 512) && !VM_Version::supports_avx512vl())) {
1944 return false;
1945 }
1946 break;
1947 case Op_ClearArray:
1948 case Op_VectorMaskGen:
1949 case Op_VectorCmpMasked:
1950 case Op_LoadVectorMasked:
1951 case Op_StoreVectorMasked:
1952 if (!is_LP64 || !VM_Version::supports_avx512bw()) {
1953 return false;
1954 }
1955 if ((size_in_bits != 512) && !VM_Version::supports_avx512vl()) {
1956 return false;
1957 }
1958 break;
1959 case Op_CMoveVD:
1960 if (vlen != 4) {
1961 return false; // implementation limitation (only vcmov4D_reg is present)
1962 }
1963 break;
1964 case Op_MaxV:
1965 case Op_MinV:
1966 if (UseSSE < 4 && is_integral_type(bt)) {
1967 return false;
1968 }
1969 if ((bt == T_FLOAT || bt == T_DOUBLE)) {
1970 // Float/Double intrinsics are enabled for AVX family currently.
1971 if (UseAVX == 0) {
1972 return false;
1973 }
1974 if (UseAVX > 2 && (!VM_Version::supports_avx512dq() && size_in_bits == 512)) { // 512 bit Float/Double intrinsics need AVX512DQ
1975 return false;
1976 }
1977 }
1978 break;
1979 case Op_CallLeafVector:
1980 if (size_in_bits == 512 && !VM_Version::supports_avx512vlbwdq()) {
1981 return false;
1982 }
1983 break;
1984 case Op_AddReductionVI:
1985 if (bt == T_INT && (UseSSE < 3 || !VM_Version::supports_ssse3())) {
1986 return false;
1987 }
1988 // fallthrough
1989 case Op_AndReductionV:
1990 case Op_OrReductionV:
1991 case Op_XorReductionV:
1992 if (is_subword_type(bt) && (UseSSE < 4)) {
1993 return false;
1994 }
1995#ifndef _LP641
1996 if (bt == T_BYTE || bt == T_LONG) {
1997 return false;
1998 }
1999#endif
2000 break;
2001#ifndef _LP641
2002 case Op_VectorInsert:
2003 if (bt == T_LONG || bt == T_DOUBLE) {
2004 return false;
2005 }
2006 break;
2007#endif
2008 case Op_MinReductionV:
2009 case Op_MaxReductionV:
2010 if ((bt == T_INT || is_subword_type(bt)) && UseSSE < 4) {
2011 return false;
2012 } else if (bt == T_LONG && (UseAVX < 3 || !VM_Version::supports_avx512vlbwdq())) {
2013 return false;
2014 }
2015 // Float/Double intrinsics enabled for AVX family.
2016 if (UseAVX == 0 && (bt == T_FLOAT || bt == T_DOUBLE)) {
2017 return false;
2018 }
2019 if (UseAVX > 2 && (!VM_Version::supports_avx512dq() && size_in_bits == 512)) {
2020 return false;
2021 }
2022#ifndef _LP641
2023 if (bt == T_BYTE || bt == T_LONG) {
2024 return false;
2025 }
2026#endif
2027 break;
2028 case Op_VectorTest:
2029 if (UseSSE < 4) {
2030 return false; // Implementation limitation
2031 } else if (size_in_bits < 32) {
2032 return false; // Implementation limitation
2033 } else if (size_in_bits == 512 && (VM_Version::supports_avx512bw() == false)) {
2034 return false; // Implementation limitation
2035 }
2036 break;
2037 case Op_VectorLoadShuffle:
2038 case Op_VectorRearrange:
2039 if(vlen == 2) {
2040 return false; // Implementation limitation due to how shuffle is loaded
2041 } else if (size_in_bits == 256 && UseAVX < 2) {
2042 return false; // Implementation limitation
2043 } else if (bt == T_BYTE && size_in_bits > 256 && !VM_Version::supports_avx512_vbmi()) {
2044 return false; // Implementation limitation
2045 } else if (bt == T_SHORT && size_in_bits > 256 && !VM_Version::supports_avx512bw()) {
2046 return false; // Implementation limitation
2047 }
2048 break;
2049 case Op_VectorLoadMask:
2050 if (size_in_bits == 256 && UseAVX < 2) {
2051 return false; // Implementation limitation
2052 }
2053 // fallthrough
2054 case Op_VectorStoreMask:
2055 if (vlen == 2) {
2056 return false; // Implementation limitation
2057 }
2058 break;
2059 case Op_VectorCastB2X:
2060 if (size_in_bits == 256 && UseAVX < 2) {
2061 return false; // Implementation limitation
2062 }
2063 break;
2064 case Op_VectorCastS2X:
2065 if (is_integral_type(bt) && size_in_bits == 256 && UseAVX < 2) {
2066 return false;
2067 }
2068 break;
2069 case Op_VectorCastI2X:
2070 if (is_integral_type(bt) && size_in_bits == 256 && UseAVX < 2) {
2071 return false;
2072 }
2073 break;
2074 case Op_VectorCastL2X:
2075 if (is_integral_type(bt) && size_in_bits == 256 && UseAVX < 2) {
2076 return false;
2077 } else if (!is_integral_type(bt) && !VM_Version::supports_avx512dq()) {
2078 return false;
2079 }
2080 break;
2081 case Op_VectorCastD2X:
2082 if (is_subword_type(bt) || bt == T_INT) {
2083 return false;
2084 }
2085 if (bt == T_LONG && !VM_Version::supports_avx512dq()) {
2086 return false;
2087 }
2088 break;
2089 case Op_VectorCastF2X:
2090 if (is_subword_type(bt) || bt == T_LONG) {
2091 return false;
2092 }
2093 break;
2094 case Op_MulReductionVI:
2095 if (bt == T_BYTE && size_in_bits == 512 && !VM_Version::supports_avx512bw()) {
2096 return false;
2097 }
2098 break;
2099 case Op_LoadVectorGatherMasked:
2100 case Op_StoreVectorScatterMasked:
2101 case Op_StoreVectorScatter:
2102 if(is_subword_type(bt)) {
2103 return false;
2104 } else if (size_in_bits < 512 && !VM_Version::supports_avx512vl()) {
2105 return false;
2106 }
2107 // fallthrough
2108 case Op_LoadVectorGather:
2109 if (size_in_bits == 64 ) {
2110 return false;
2111 }
2112 break;
2113 case Op_MaskAll:
2114 if (!is_LP64 || !VM_Version::supports_evex()) {
2115 return false;
2116 }
2117 if ((vlen > 16 || is_subword_type(bt)) && !VM_Version::supports_avx512bw()) {
2118 return false;
2119 }
2120 if (size_in_bits < 512 && !VM_Version::supports_avx512vl()) {
2121 return false;
2122 }
2123 break;
2124 case Op_VectorMaskCmp:
2125 if (vlen < 2 || size_in_bits < 32) {
2126 return false;
2127 }
2128 break;
2129 case Op_VectorLongToMask:
2130 if (UseAVX < 1 || !is_LP64) {
2131 return false;
2132 }
2133 if (UseAVX < 3 && !VM_Version::supports_bmi2()) {
2134 return false;
2135 }
2136 break;
2137 }
2138 return true; // Per default match rules are supported.
2139}
2140
2141const bool Matcher::match_rule_supported_vector_masked(int opcode, int vlen, BasicType bt) {
2142 // ADLC based match_rule_supported routine checks for the existence of pattern based
2143 // on IR opcode. Most of the unary/binary/ternary masked operation share the IR nodes
2144 // of their non-masked counterpart with mask edge being the differentiator.
2145 // This routine does a strict check on the existence of masked operation patterns
2146 // by returning a default false value for all the other opcodes apart from the
2147 // ones whose masked instruction patterns are defined in this file.
2148 if (!match_rule_supported_vector(opcode, vlen, bt)) {
2149 return false;
2150 }
2151
2152 const bool is_LP64 = LP64_ONLY(true)true NOT_LP64(false);
2153 int size_in_bits = vlen * type2aelembytes(bt) * BitsPerByte;
2154 if (size_in_bits != 512 && !VM_Version::supports_avx512vl()) {
2155 return false;
2156 }
2157 switch(opcode) {
2158 // Unary masked operations
2159 case Op_AbsVB:
2160 case Op_AbsVS:
2161 if(!VM_Version::supports_avx512bw()) {
2162 return false; // Implementation limitation
2163 }
2164 case Op_AbsVI:
2165 case Op_AbsVL:
2166 return true;
2167
2168 // Ternary masked operations
2169 case Op_FmaVF:
2170 case Op_FmaVD:
2171 return true;
2172
2173 // Binary masked operations
2174 case Op_AddVB:
2175 case Op_AddVS:
2176 case Op_SubVB:
2177 case Op_SubVS:
2178 case Op_MulVS:
2179 case Op_LShiftVS:
2180 case Op_RShiftVS:
2181 case Op_URShiftVS:
2182 assert(size_in_bits == 512 || VM_Version::supports_avx512vl(), "")do { if (!(size_in_bits == 512 || VM_Version::supports_avx512vl
())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 1898, "assert(" "size_in_bits == 512 || VM_Version::supports_avx512vl()"
") failed", ""); ::breakpoint(); } } while (0);
2183 if (!VM_Version::supports_avx512bw()) {
2184 return false; // Implementation limitation
2185 }
2186 return true;
2187
2188 case Op_MulVL:
2189 assert(size_in_bits == 512 || VM_Version::supports_avx512vl(), "")do { if (!(size_in_bits == 512 || VM_Version::supports_avx512vl
())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 1905, "assert(" "size_in_bits == 512 || VM_Version::supports_avx512vl()"
") failed", ""); ::breakpoint(); } } while (0);
2190 if (!VM_Version::supports_avx512dq()) {
2191 return false; // Implementation limitation
2192 }
2193 return true;
2194
2195 case Op_AndV:
2196 case Op_OrV:
2197 case Op_XorV:
2198 case Op_RotateRightV:
2199 case Op_RotateLeftV:
2200 if (bt != T_INT && bt != T_LONG) {
2201 return false; // Implementation limitation
2202 }
2203 return true;
2204
2205 case Op_VectorLoadMask:
2206 assert(size_in_bits == 512 || VM_Version::supports_avx512vl(), "")do { if (!(size_in_bits == 512 || VM_Version::supports_avx512vl
())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 1922, "assert(" "size_in_bits == 512 || VM_Version::supports_avx512vl()"
") failed", ""); ::breakpoint(); } } while (0);
2207 if (is_subword_type(bt) && !VM_Version::supports_avx512bw()) {
2208 return false;
2209 }
2210 return true;
2211
2212 case Op_AddVI:
2213 case Op_AddVL:
2214 case Op_AddVF:
2215 case Op_AddVD:
2216 case Op_SubVI:
2217 case Op_SubVL:
2218 case Op_SubVF:
2219 case Op_SubVD:
2220 case Op_MulVI:
2221 case Op_MulVF:
2222 case Op_MulVD:
2223 case Op_DivVF:
2224 case Op_DivVD:
2225 case Op_SqrtVF:
2226 case Op_SqrtVD:
2227 case Op_LShiftVI:
2228 case Op_LShiftVL:
2229 case Op_RShiftVI:
2230 case Op_RShiftVL:
2231 case Op_URShiftVI:
2232 case Op_URShiftVL:
2233 case Op_LoadVectorMasked:
2234 case Op_StoreVectorMasked:
2235 case Op_LoadVectorGatherMasked:
2236 case Op_StoreVectorScatterMasked:
2237 return true;
2238
2239 case Op_MaxV:
2240 case Op_MinV:
2241 if (is_subword_type(bt) && !VM_Version::supports_avx512bw()) {
2242 return false; // Implementation limitation
2243 }
2244 if (is_floating_point_type(bt)) {
2245 return false; // Implementation limitation
2246 }
2247 return true;
2248
2249 case Op_VectorMaskCmp:
2250 if (is_subword_type(bt) && !VM_Version::supports_avx512bw()) {
2251 return false; // Implementation limitation
2252 }
2253 return true;
2254
2255 case Op_VectorRearrange:
2256 if (bt == T_SHORT && !VM_Version::supports_avx512bw()) {
2257 return false; // Implementation limitation
2258 }
2259 if (bt == T_BYTE && !VM_Version::supports_avx512_vbmi()) {
2260 return false; // Implementation limitation
2261 } else if ((bt == T_INT || bt == T_FLOAT) && size_in_bits < 256) {
2262 return false; // Implementation limitation
2263 }
2264 return true;
2265
2266 // Binary Logical operations
2267 case Op_AndVMask:
2268 case Op_OrVMask:
2269 case Op_XorVMask:
2270 if (vlen > 16 && !VM_Version::supports_avx512bw()) {
2271 return false; // Implementation limitation
2272 }
2273 return true;
2274
2275 case Op_MaskAll:
2276 return true;
2277
2278 default:
2279 return false;
2280 }
2281}
2282
2283MachOper* Matcher::pd_specialize_generic_vector_operand(MachOper* generic_opnd, uint ideal_reg, bool is_temp) {
2284 assert(Matcher::is_generic_vector(generic_opnd), "not generic")do { if (!(Matcher::is_generic_vector(generic_opnd))) { (*g_assert_poison
) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 2000, "assert(" "Matcher::is_generic_vector(generic_opnd)" ") failed"
, "not generic"); ::breakpoint(); } } while (0);
2285 bool legacy = (generic_opnd->opcode() == LEGVEC);
2286 if (!VM_Version::supports_avx512vlbwdq() && // KNL
2287 is_temp && !legacy && (ideal_reg == Op_VecZ)) {
2288 // Conservatively specialize 512bit vec TEMP operands to legVecZ (zmm0-15) on KNL.
2289 return new legVecZOper();
2290 }
2291 if (legacy) {
2292 switch (ideal_reg) {
2293 case Op_VecS: return new legVecSOper();
2294 case Op_VecD: return new legVecDOper();
2295 case Op_VecX: return new legVecXOper();
2296 case Op_VecY: return new legVecYOper();
2297 case Op_VecZ: return new legVecZOper();
2298 }
2299 } else {
2300 switch (ideal_reg) {
2301 case Op_VecS: return new vecSOper();
2302 case Op_VecD: return new vecDOper();
2303 case Op_VecX: return new vecXOper();
2304 case Op_VecY: return new vecYOper();
2305 case Op_VecZ: return new vecZOper();
2306 }
2307 }
2308 ShouldNotReachHere()do { (*g_assert_poison) = 'X';; report_should_not_reach_here(
"/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad", 2024
); ::breakpoint(); } while (0);
2309 return NULL__null;
2310}
2311
2312bool Matcher::is_reg2reg_move(MachNode* m) {
2313 switch (m->rule()) {
2314 case MoveVec2Leg_rule:
2315 case MoveLeg2Vec_rule:
2316 case MoveF2VL_rule:
2317 case MoveF2LEG_rule:
2318 case MoveVL2F_rule:
2319 case MoveLEG2F_rule:
2320 case MoveD2VL_rule:
2321 case MoveD2LEG_rule:
2322 case MoveVL2D_rule:
2323 case MoveLEG2D_rule:
2324 return true;
2325 default:
2326 return false;
2327 }
2328}
2329
2330bool Matcher::is_generic_vector(MachOper* opnd) {
2331 switch (opnd->opcode()) {
2332 case VEC:
2333 case LEGVEC:
2334 return true;
2335 default:
2336 return false;
2337 }
2338}
2339
2340//------------------------------------------------------------------------
2341
2342const RegMask* Matcher::predicate_reg_mask(void) {
2343 return &_VECTMASK_REG_mask;
2344}
2345
2346const TypeVectMask* Matcher::predicate_reg_type(const Type* elemTy, int length) {
2347 return new TypeVectMask(elemTy, length);
2348}
2349
2350// Max vector size in bytes. 0 if not supported.
2351const int Matcher::vector_width_in_bytes(BasicType bt) {
2352 assert(is_java_primitive(bt), "only primitive type vectors")do { if (!(is_java_primitive(bt))) { (*g_assert_poison) = 'X'
;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 2068, "assert(" "is_java_primitive(bt)" ") failed", "only primitive type vectors"
); ::breakpoint(); } } while (0);
2353 if (UseSSE < 2) return 0;
2354 // SSE2 supports 128bit vectors for all types.
2355 // AVX2 supports 256bit vectors for all types.
2356 // AVX2/EVEX supports 512bit vectors for all types.
2357 int size = (UseAVX > 1) ? (1 << UseAVX) * 8 : 16;
2358 // AVX1 supports 256bit vectors only for FLOAT and DOUBLE.
2359 if (UseAVX > 0 && (bt == T_FLOAT || bt == T_DOUBLE))
2360 size = (UseAVX > 2) ? 64 : 32;
2361 if (UseAVX > 2 && (bt == T_BYTE || bt == T_SHORT || bt == T_CHAR))
2362 size = (VM_Version::supports_avx512bw()) ? 64 : 32;
2363 // Use flag to limit vector size.
2364 size = MIN2(size,(int)MaxVectorSize);
2365 // Minimum 2 values in vector (or 4 for bytes).
2366 switch (bt) {
2367 case T_DOUBLE:
2368 case T_LONG:
2369 if (size < 16) return 0;
2370 break;
2371 case T_FLOAT:
2372 case T_INT:
2373 if (size < 8) return 0;
2374 break;
2375 case T_BOOLEAN:
2376 if (size < 4) return 0;
2377 break;
2378 case T_CHAR:
2379 if (size < 4) return 0;
2380 break;
2381 case T_BYTE:
2382 if (size < 4) return 0;
2383 break;
2384 case T_SHORT:
2385 if (size < 4) return 0;
2386 break;
2387 default:
2388 ShouldNotReachHere()do { (*g_assert_poison) = 'X';; report_should_not_reach_here(
"/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad", 2104
); ::breakpoint(); } while (0);
2389 }
2390 return size;
2391}
2392
2393// Limits on vector size (number of elements) loaded into vector.
2394const int Matcher::max_vector_size(const BasicType bt) {
2395 return vector_width_in_bytes(bt)/type2aelembytes(bt);
2396}
2397const int Matcher::min_vector_size(const BasicType bt) {
2398 int max_size = max_vector_size(bt);
2399 // Min size which can be loaded into vector is 4 bytes.
2400 int size = (type2aelembytes(bt) == 1) ? 4 : 2;
2401 // Support for calling svml double64 vectors
2402 if (bt == T_DOUBLE) {
2403 size = 1;
2404 }
2405 return MIN2(size,max_size);
2406}
2407
2408const int Matcher::scalable_vector_reg_size(const BasicType bt) {
2409 return -1;
2410}
2411
2412// Vector ideal reg corresponding to specified size in bytes
2413const uint Matcher::vector_ideal_reg(int size) {
2414 assert(MaxVectorSize >= size, "")do { if (!(MaxVectorSize >= size)) { (*g_assert_poison) = 'X'
;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 2130, "assert(" "MaxVectorSize >= size" ") failed", "");
::breakpoint(); } } while (0);
2415 switch(size) {
2416 case 4: return Op_VecS;
2417 case 8: return Op_VecD;
2418 case 16: return Op_VecX;
2419 case 32: return Op_VecY;
2420 case 64: return Op_VecZ;
2421 }
2422 ShouldNotReachHere()do { (*g_assert_poison) = 'X';; report_should_not_reach_here(
"/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad", 2138
); ::breakpoint(); } while (0);
2423 return 0;
2424}
2425
2426// Check for shift by small constant as well
2427static bool clone_shift(Node* shift, Matcher* matcher, Matcher::MStack& mstack, VectorSet& address_visited) {
2428 if (shift->Opcode() == Op_LShiftXOp_LShiftL && shift->in(2)->is_Con() &&
2429 shift->in(2)->get_int() <= 3 &&
2430 // Are there other uses besides address expressions?
2431 !matcher->is_visited(shift)) {
2432 address_visited.set(shift->_idx); // Flag as address_visited
2433 mstack.push(shift->in(2), Matcher::Visit);
2434 Node *conv = shift->in(1);
2435#ifdef _LP641
2436 // Allow Matcher to match the rule which bypass
2437 // ConvI2L operation for an array index on LP64
2438 // if the index value is positive.
2439 if (conv->Opcode() == Op_ConvI2L &&
2440 conv->as_Type()->type()->is_long()->_lo >= 0 &&
2441 // Are there other uses besides address expressions?
2442 !matcher->is_visited(conv)) {
2443 address_visited.set(conv->_idx); // Flag as address_visited
2444 mstack.push(conv->in(1), Matcher::Pre_Visit);
2445 } else
2446#endif
2447 mstack.push(conv, Matcher::Pre_Visit);
2448 return true;
2449 }
2450 return false;
2451}
2452
2453// This function identifies sub-graphs in which a 'load' node is
2454// input to two different nodes, and such that it can be matched
2455// with BMI instructions like blsi, blsr, etc.
2456// Example : for b = -a[i] & a[i] can be matched to blsi r32, m32.
2457// The graph is (AndL (SubL Con0 LoadL*) LoadL*), where LoadL*
2458// refers to the same node.
2459//
2460// Match the generic fused operations pattern (op1 (op2 Con{ConType} mop) mop)
2461// This is a temporary solution until we make DAGs expressible in ADL.
2462template<typename ConType>
2463class FusedPatternMatcher {
2464 Node* _op1_node;
2465 Node* _mop_node;
2466 int _con_op;
2467
2468 static int match_next(Node* n, int next_op, int next_op_idx) {
2469 if (n->in(1) == NULL__null || n->in(2) == NULL__null) {
2470 return -1;
2471 }
2472
2473 if (next_op_idx == -1) { // n is commutative, try rotations
2474 if (n->in(1)->Opcode() == next_op) {
2475 return 1;
2476 } else if (n->in(2)->Opcode() == next_op) {
2477 return 2;
2478 }
2479 } else {
2480 assert(next_op_idx > 0 && next_op_idx <= 2, "Bad argument index")do { if (!(next_op_idx > 0 && next_op_idx <= 2)
) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 2196, "assert(" "next_op_idx > 0 && next_op_idx <= 2"
") failed", "Bad argument index"); ::breakpoint(); } } while
(0);
2481 if (n->in(next_op_idx)->Opcode() == next_op) {
2482 return next_op_idx;
2483 }
2484 }
2485 return -1;
2486 }
2487
2488 public:
2489 FusedPatternMatcher(Node* op1_node, Node* mop_node, int con_op) :
2490 _op1_node(op1_node), _mop_node(mop_node), _con_op(con_op) { }
2491
2492 bool match(int op1, int op1_op2_idx, // op1 and the index of the op1->op2 edge, -1 if op1 is commutative
2493 int op2, int op2_con_idx, // op2 and the index of the op2->con edge, -1 if op2 is commutative
2494 typename ConType::NativeType con_value) {
2495 if (_op1_node->Opcode() != op1) {
2496 return false;
2497 }
2498 if (_mop_node->outcnt() > 2) {
2499 return false;
2500 }
2501 op1_op2_idx = match_next(_op1_node, op2, op1_op2_idx);
2502 if (op1_op2_idx == -1) {
2503 return false;
2504 }
2505 // Memory operation must be the other edge
2506 int op1_mop_idx = (op1_op2_idx & 1) + 1;
2507
2508 // Check that the mop node is really what we want
2509 if (_op1_node->in(op1_mop_idx) == _mop_node) {
2510 Node* op2_node = _op1_node->in(op1_op2_idx);
2511 if (op2_node->outcnt() > 1) {
2512 return false;
2513 }
2514 assert(op2_node->Opcode() == op2, "Should be")do { if (!(op2_node->Opcode() == op2)) { (*g_assert_poison
) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 2230, "assert(" "op2_node->Opcode() == op2" ") failed", "Should be"
); ::breakpoint(); } } while (0);
2515 op2_con_idx = match_next(op2_node, _con_op, op2_con_idx);
2516 if (op2_con_idx == -1) {
2517 return false;
2518 }
2519 // Memory operation must be the other edge
2520 int op2_mop_idx = (op2_con_idx & 1) + 1;
2521 // Check that the memory operation is the same node
2522 if (op2_node->in(op2_mop_idx) == _mop_node) {
2523 // Now check the constant
2524 const Type* con_type = op2_node->in(op2_con_idx)->bottom_type();
2525 if (con_type != Type::TOP && ConType::as_self(con_type)->get_con() == con_value) {
2526 return true;
2527 }
2528 }
2529 }
2530 return false;
2531 }
2532};
2533
2534static bool is_bmi_pattern(Node* n, Node* m) {
2535 assert(UseBMI1Instructions, "sanity")do { if (!(UseBMI1Instructions)) { (*g_assert_poison) = 'X';;
report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 2251, "assert(" "UseBMI1Instructions" ") failed", "sanity")
; ::breakpoint(); } } while (0);
2536 if (n != NULL__null && m != NULL__null) {
2537 if (m->Opcode() == Op_LoadI) {
2538 FusedPatternMatcher<TypeInt> bmii(n, m, Op_ConI);
2539 return bmii.match(Op_AndI, -1, Op_SubI, 1, 0) ||
2540 bmii.match(Op_AndI, -1, Op_AddI, -1, -1) ||
2541 bmii.match(Op_XorI, -1, Op_AddI, -1, -1);
2542 } else if (m->Opcode() == Op_LoadL) {
2543 FusedPatternMatcher<TypeLong> bmil(n, m, Op_ConL);
2544 return bmil.match(Op_AndL, -1, Op_SubL, 1, 0) ||
2545 bmil.match(Op_AndL, -1, Op_AddL, -1, -1) ||
2546 bmil.match(Op_XorL, -1, Op_AddL, -1, -1);
2547 }
2548 }
2549 return false;
2550}
2551
2552// Should the matcher clone input 'm' of node 'n'?
2553bool Matcher::pd_clone_node(Node* n, Node* m, Matcher::MStack& mstack) {
2554 // If 'n' and 'm' are part of a graph for BMI instruction, clone the input 'm'.
2555 if (UseBMI1Instructions && is_bmi_pattern(n, m)) {
2556 mstack.push(m, Visit);
2557 return true;
2558 }
2559 if (is_vshift_con_pattern(n, m)) { // ShiftV src (ShiftCntV con)
2560 mstack.push(m, Visit); // m = ShiftCntV
2561 return true;
2562 }
2563 return false;
2564}
2565
2566// Should the Matcher clone shifts on addressing modes, expecting them
2567// to be subsumed into complex addressing expressions or compute them
2568// into registers?
2569bool Matcher::pd_clone_address_expressions(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
2570 Node *off = m->in(AddPNode::Offset);
2571 if (off->is_Con()) {
2572 address_visited.test_set(m->_idx); // Flag as address_visited
2573 Node *adr = m->in(AddPNode::Address);
2574
2575 // Intel can handle 2 adds in addressing mode
2576 // AtomicAdd is not an addressing expression.
2577 // Cheap to find it by looking for screwy base.
2578 if (adr->is_AddP() &&
2579 !adr->in(AddPNode::Base)->is_top() &&
2580 LP64_ONLY( off->get_long() == (int) (off->get_long()) && )off->get_long() == (int) (off->get_long()) && // immL32
2581 // Are there other uses besides address expressions?
2582 !is_visited(adr)) {
2583 address_visited.set(adr->_idx); // Flag as address_visited
2584 Node *shift = adr->in(AddPNode::Offset);
2585 if (!clone_shift(shift, this, mstack, address_visited)) {
2586 mstack.push(shift, Pre_Visit);
2587 }
2588 mstack.push(adr->in(AddPNode::Address), Pre_Visit);
2589 mstack.push(adr->in(AddPNode::Base), Pre_Visit);
2590 } else {
2591 mstack.push(adr, Pre_Visit);
2592 }
2593
2594 // Clone X+offset as it also folds into most addressing expressions
2595 mstack.push(off, Visit);
2596 mstack.push(m->in(AddPNode::Base), Pre_Visit);
2597 return true;
2598 } else if (clone_shift(off, this, mstack, address_visited)) {
2599 address_visited.test_set(m->_idx); // Flag as address_visited
2600 mstack.push(m->in(AddPNode::Address), Pre_Visit);
2601 mstack.push(m->in(AddPNode::Base), Pre_Visit);
2602 return true;
2603 }
2604 return false;
2605}
2606
2607static inline Assembler::ComparisonPredicate booltest_pred_to_comparison_pred(int bt) {
2608 switch (bt) {
2609 case BoolTest::eq:
2610 return Assembler::eq;
2611 case BoolTest::ne:
2612 return Assembler::neq;
2613 case BoolTest::le:
2614 case BoolTest::ule:
2615 return Assembler::le;
2616 case BoolTest::ge:
2617 case BoolTest::uge:
2618 return Assembler::nlt;
2619 case BoolTest::lt:
2620 case BoolTest::ult:
2621 return Assembler::lt;
2622 case BoolTest::gt:
2623 case BoolTest::ugt:
2624 return Assembler::nle;
2625 default : ShouldNotReachHere()do { (*g_assert_poison) = 'X';; report_should_not_reach_here(
"/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad", 2341
); ::breakpoint(); } while (0); return Assembler::_false;
2626 }
2627}
2628
2629static inline Assembler::ComparisonPredicateFP booltest_pred_to_comparison_pred_fp(int bt) {
2630 switch (bt) {
2631 case BoolTest::eq: return Assembler::EQ_OQ; // ordered non-signaling
2632 // As per JLS 15.21.1, != of NaNs is true. Thus use unordered compare.
2633 case BoolTest::ne: return Assembler::NEQ_UQ; // unordered non-signaling
2634 case BoolTest::le: return Assembler::LE_OQ; // ordered non-signaling
2635 case BoolTest::ge: return Assembler::GE_OQ; // ordered non-signaling
2636 case BoolTest::lt: return Assembler::LT_OQ; // ordered non-signaling
2637 case BoolTest::gt: return Assembler::GT_OQ; // ordered non-signaling
2638 default: ShouldNotReachHere()do { (*g_assert_poison) = 'X';; report_should_not_reach_here(
"/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad", 2354
); ::breakpoint(); } while (0); return Assembler::FALSE_OS;
2639 }
2640}
2641
2642// Helper methods for MachSpillCopyNode::implementation().
2643static void vec_mov_helper(CodeBuffer *cbuf, int src_lo, int dst_lo,
2644 int src_hi, int dst_hi, uint ireg, outputStream* st) {
2645 assert(ireg == Op_VecS || // 32bit vectordo { if (!(ireg == Op_VecS || (src_lo & 1) == 0 &&
(src_lo + 1) == src_hi && (dst_lo & 1) == 0 &&
(dst_lo + 1) == dst_hi)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
2364, "assert(" "ireg == Op_VecS || (src_lo & 1) == 0 && (src_lo + 1) == src_hi && (dst_lo & 1) == 0 && (dst_lo + 1) == dst_hi"
") failed", "no non-adjacent vector moves"); ::breakpoint();
} } while (0)
2646 (src_lo & 1) == 0 && (src_lo + 1) == src_hi &&do { if (!(ireg == Op_VecS || (src_lo & 1) == 0 &&
(src_lo + 1) == src_hi && (dst_lo & 1) == 0 &&
(dst_lo + 1) == dst_hi)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
2364, "assert(" "ireg == Op_VecS || (src_lo & 1) == 0 && (src_lo + 1) == src_hi && (dst_lo & 1) == 0 && (dst_lo + 1) == dst_hi"
") failed", "no non-adjacent vector moves"); ::breakpoint();
} } while (0)
2647 (dst_lo & 1) == 0 && (dst_lo + 1) == dst_hi,do { if (!(ireg == Op_VecS || (src_lo & 1) == 0 &&
(src_lo + 1) == src_hi && (dst_lo & 1) == 0 &&
(dst_lo + 1) == dst_hi)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
2364, "assert(" "ireg == Op_VecS || (src_lo & 1) == 0 && (src_lo + 1) == src_hi && (dst_lo & 1) == 0 && (dst_lo + 1) == dst_hi"
") failed", "no non-adjacent vector moves"); ::breakpoint();
} } while (0)
2648 "no non-adjacent vector moves" )do { if (!(ireg == Op_VecS || (src_lo & 1) == 0 &&
(src_lo + 1) == src_hi && (dst_lo & 1) == 0 &&
(dst_lo + 1) == dst_hi)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
2364, "assert(" "ireg == Op_VecS || (src_lo & 1) == 0 && (src_lo + 1) == src_hi && (dst_lo & 1) == 0 && (dst_lo + 1) == dst_hi"
") failed", "no non-adjacent vector moves"); ::breakpoint();
} } while (0);
2649 if (cbuf) {
2650 C2_MacroAssembler _masm(cbuf);
2651 switch (ireg) {
2652 case Op_VecS: // copy whole register
2653 case Op_VecD:
2654 case Op_VecX:
2655#ifndef _LP641
2656 ___masm. movdqu(as_XMMRegister(Matcher::_regEncode[dst_lo]), as_XMMRegister(Matcher::_regEncode[src_lo]));
2657#else
2658 if ((UseAVX < 3) || VM_Version::supports_avx512vl()) {
2659 ___masm. movdqu(as_XMMRegister(Matcher::_regEncode[dst_lo]), as_XMMRegister(Matcher::_regEncode[src_lo]));
2660 } else {
2661 ___masm. vextractf32x4(as_XMMRegister(Matcher::_regEncode[dst_lo]), as_XMMRegister(Matcher::_regEncode[src_lo]), 0x0);
2662 }
2663#endif
2664 break;
2665 case Op_VecY:
2666#ifndef _LP641
2667 ___masm. vmovdqu(as_XMMRegister(Matcher::_regEncode[dst_lo]), as_XMMRegister(Matcher::_regEncode[src_lo]));
2668#else
2669 if ((UseAVX < 3) || VM_Version::supports_avx512vl()) {
2670 ___masm. vmovdqu(as_XMMRegister(Matcher::_regEncode[dst_lo]), as_XMMRegister(Matcher::_regEncode[src_lo]));
2671 } else {
2672 ___masm. vextractf64x4(as_XMMRegister(Matcher::_regEncode[dst_lo]), as_XMMRegister(Matcher::_regEncode[src_lo]), 0x0);
2673 }
2674#endif
2675 break;
2676 case Op_VecZ:
2677 ___masm. evmovdquq(as_XMMRegister(Matcher::_regEncode[dst_lo]), as_XMMRegister(Matcher::_regEncode[src_lo]), 2);
2678 break;
2679 default:
2680 ShouldNotReachHere()do { (*g_assert_poison) = 'X';; report_should_not_reach_here(
"/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad", 2396
); ::breakpoint(); } while (0);
2681 }
2682#ifndef PRODUCT
2683 } else {
2684 switch (ireg) {
2685 case Op_VecS:
2686 case Op_VecD:
2687 case Op_VecX:
2688 st->print("movdqu %s,%s\t# spill",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
2689 break;
2690 case Op_VecY:
2691 case Op_VecZ:
2692 st->print("vmovdqu %s,%s\t# spill",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
2693 break;
2694 default:
2695 ShouldNotReachHere()do { (*g_assert_poison) = 'X';; report_should_not_reach_here(
"/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad", 2411
); ::breakpoint(); } while (0);
2696 }
2697#endif
2698 }
2699}
2700
2701void vec_spill_helper(CodeBuffer *cbuf, bool is_load,
2702 int stack_offset, int reg, uint ireg, outputStream* st) {
2703 if (cbuf) {
2704 C2_MacroAssembler _masm(cbuf);
2705 if (is_load) {
2706 switch (ireg) {
2707 case Op_VecS:
2708 ___masm. movdl(as_XMMRegister(Matcher::_regEncode[reg]), Address(rsp, stack_offset));
2709 break;
2710 case Op_VecD:
2711 ___masm. movq(as_XMMRegister(Matcher::_regEncode[reg]), Address(rsp, stack_offset));
2712 break;
2713 case Op_VecX:
2714#ifndef _LP641
2715 ___masm. movdqu(as_XMMRegister(Matcher::_regEncode[reg]), Address(rsp, stack_offset));
2716#else
2717 if ((UseAVX < 3) || VM_Version::supports_avx512vl()) {
2718 ___masm. movdqu(as_XMMRegister(Matcher::_regEncode[reg]), Address(rsp, stack_offset));
2719 } else {
2720 ___masm. vpxor(as_XMMRegister(Matcher::_regEncode[reg]), as_XMMRegister(Matcher::_regEncode[reg]), as_XMMRegister(Matcher::_regEncode[reg]), 2);
2721 ___masm. vinsertf32x4(as_XMMRegister(Matcher::_regEncode[reg]), as_XMMRegister(Matcher::_regEncode[reg]), Address(rsp, stack_offset),0x0);
2722 }
2723#endif
2724 break;
2725 case Op_VecY:
2726#ifndef _LP641
2727 ___masm. vmovdqu(as_XMMRegister(Matcher::_regEncode[reg]), Address(rsp, stack_offset));
2728#else
2729 if ((UseAVX < 3) || VM_Version::supports_avx512vl()) {
2730 ___masm. vmovdqu(as_XMMRegister(Matcher::_regEncode[reg]), Address(rsp, stack_offset));
2731 } else {
2732 ___masm. vpxor(as_XMMRegister(Matcher::_regEncode[reg]), as_XMMRegister(Matcher::_regEncode[reg]), as_XMMRegister(Matcher::_regEncode[reg]), 2);
2733 ___masm. vinsertf64x4(as_XMMRegister(Matcher::_regEncode[reg]), as_XMMRegister(Matcher::_regEncode[reg]), Address(rsp, stack_offset),0x0);
2734 }
2735#endif
2736 break;
2737 case Op_VecZ:
2738 ___masm. evmovdquq(as_XMMRegister(Matcher::_regEncode[reg]), Address(rsp, stack_offset), 2);
2739 break;
2740 default:
2741 ShouldNotReachHere()do { (*g_assert_poison) = 'X';; report_should_not_reach_here(
"/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad", 2457
); ::breakpoint(); } while (0);
2742 }
2743 } else { // store
2744 switch (ireg) {
2745 case Op_VecS:
2746 ___masm. movdl(Address(rsp, stack_offset), as_XMMRegister(Matcher::_regEncode[reg]));
2747 break;
2748 case Op_VecD:
2749 ___masm. movq(Address(rsp, stack_offset), as_XMMRegister(Matcher::_regEncode[reg]));
2750 break;
2751 case Op_VecX:
2752#ifndef _LP641
2753 ___masm. movdqu(Address(rsp, stack_offset), as_XMMRegister(Matcher::_regEncode[reg]));
2754#else
2755 if ((UseAVX < 3) || VM_Version::supports_avx512vl()) {
2756 ___masm. movdqu(Address(rsp, stack_offset), as_XMMRegister(Matcher::_regEncode[reg]));
2757 }
2758 else {
2759 ___masm. vextractf32x4(Address(rsp, stack_offset), as_XMMRegister(Matcher::_regEncode[reg]), 0x0);
2760 }
2761#endif
2762 break;
2763 case Op_VecY:
2764#ifndef _LP641
2765 ___masm. vmovdqu(Address(rsp, stack_offset), as_XMMRegister(Matcher::_regEncode[reg]));
2766#else
2767 if ((UseAVX < 3) || VM_Version::supports_avx512vl()) {
2768 ___masm. vmovdqu(Address(rsp, stack_offset), as_XMMRegister(Matcher::_regEncode[reg]));
2769 }
2770 else {
2771 ___masm. vextractf64x4(Address(rsp, stack_offset), as_XMMRegister(Matcher::_regEncode[reg]), 0x0);
2772 }
2773#endif
2774 break;
2775 case Op_VecZ:
2776 ___masm. evmovdquq(Address(rsp, stack_offset), as_XMMRegister(Matcher::_regEncode[reg]), 2);
2777 break;
2778 default:
2779 ShouldNotReachHere()do { (*g_assert_poison) = 'X';; report_should_not_reach_here(
"/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad", 2495
); ::breakpoint(); } while (0);
2780 }
2781 }
2782#ifndef PRODUCT
2783 } else {
2784 if (is_load) {
2785 switch (ireg) {
2786 case Op_VecS:
2787 st->print("movd %s,[rsp + %d]\t# spill", Matcher::regName[reg], stack_offset);
2788 break;
2789 case Op_VecD:
2790 st->print("movq %s,[rsp + %d]\t# spill", Matcher::regName[reg], stack_offset);
2791 break;
2792 case Op_VecX:
2793 st->print("movdqu %s,[rsp + %d]\t# spill", Matcher::regName[reg], stack_offset);
2794 break;
2795 case Op_VecY:
2796 case Op_VecZ:
2797 st->print("vmovdqu %s,[rsp + %d]\t# spill", Matcher::regName[reg], stack_offset);
2798 break;
2799 default:
2800 ShouldNotReachHere()do { (*g_assert_poison) = 'X';; report_should_not_reach_here(
"/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad", 2516
); ::breakpoint(); } while (0);
2801 }
2802 } else { // store
2803 switch (ireg) {
2804 case Op_VecS:
2805 st->print("movd [rsp + %d],%s\t# spill", stack_offset, Matcher::regName[reg]);
2806 break;
2807 case Op_VecD:
2808 st->print("movq [rsp + %d],%s\t# spill", stack_offset, Matcher::regName[reg]);
2809 break;
2810 case Op_VecX:
2811 st->print("movdqu [rsp + %d],%s\t# spill", stack_offset, Matcher::regName[reg]);
2812 break;
2813 case Op_VecY:
2814 case Op_VecZ:
2815 st->print("vmovdqu [rsp + %d],%s\t# spill", stack_offset, Matcher::regName[reg]);
2816 break;
2817 default:
2818 ShouldNotReachHere()do { (*g_assert_poison) = 'X';; report_should_not_reach_here(
"/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad", 2534
); ::breakpoint(); } while (0);
2819 }
2820 }
2821#endif
2822 }
2823}
2824
2825static inline jlong replicate8_imm(int con, int width) {
2826 // Load a constant of "width" (in bytes) and replicate it to fill 64bit.
2827 assert(width == 1 || width == 2 || width == 4, "only byte, short or int types here")do { if (!(width == 1 || width == 2 || width == 4)) { (*g_assert_poison
) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 2543, "assert(" "width == 1 || width == 2 || width == 4" ") failed"
, "only byte, short or int types here"); ::breakpoint(); } } while
(0);
2828 int bit_width = width * 8;
2829 jlong val = con;
2830 val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits
2831 while(bit_width < 64) {
2832 val |= (val << bit_width);
2833 bit_width <<= 1;
2834 }
2835 return val;
2836}
2837
2838#ifndef PRODUCT
2839 void MachNopNode::format(PhaseRegAlloc*, outputStream* st) const {
2840 st->print("nop \t# %d bytes pad for loops and calls", _count);
2841 }
2842#endif
2843
2844 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc*) const {
2845 C2_MacroAssembler _masm(&cbuf);
2846 ___masm. nop(_count);
2847 }
2848
2849 uint MachNopNode::size(PhaseRegAlloc*) const {
2850 return _count;
2851 }
2852
2853#ifndef PRODUCT
2854 void MachBreakpointNode::format(PhaseRegAlloc*, outputStream* st) const {
2855 st->print("# breakpoint");
2856 }
2857#endif
2858
2859 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc* ra_) const {
2860 C2_MacroAssembler _masm(&cbuf);
2861 ___masm. int3();
2862 }
2863
2864 uint MachBreakpointNode::size(PhaseRegAlloc* ra_) const {
2865 return MachNode::size(ra_);
2866 }
2867
2868
2869#line 2869 "ad_x86.cpp"
2870
2871
2872//SourceForm
2873
2874#line 32 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/gc/z/z_x86_64.ad"
2875
2876
2877#include "c2_intelJccErratum_x86.hpp"
2878
2879static void z_load_barrier(MacroAssembler& _masm, const MachNode* node, Address ref_addr, Register ref, Register tmp, uint8_t barrier_data) {
2880 if (barrier_data == ZLoadBarrierElided) {
2881 return; // Elided.
2882 }
2883 ZLoadBarrierStubC2* const stub = ZLoadBarrierStubC2::create(node, ref_addr, ref, tmp, barrier_data);
2884 {
2885 IntelJccErratumAlignment intel_alignment(_masm, 10 /* jcc_size */);
2886 ___masm. testptr(ref, Address(r15_thread, ZThreadLocalData::address_bad_mask_offset()));
2887 ___masm. jcc(Assembler::notZero, *stub->entry());
2888 }
2889 ___masm. bind(*stub->continuation());
2890}
2891
2892static void z_load_barrier_cmpxchg(MacroAssembler& _masm, const MachNode* node, Address ref_addr, Register ref, Register tmp, Label& good) {
2893 ZLoadBarrierStubC2* const stub = ZLoadBarrierStubC2::create(node, ref_addr, ref, tmp, ZLoadBarrierStrong);
2894 {
2895 IntelJccErratumAlignment intel_alignment(_masm, 10 /* jcc_size */);
2896 ___masm. testptr(ref, Address(r15_thread, ZThreadLocalData::address_bad_mask_offset()));
2897 ___masm. jcc(Assembler::zero, good);
2898 }
2899 {
2900 IntelJccErratumAlignment intel_alignment(_masm, 5 /* jcc_size */);
2901 ___masm. jmp(*stub->entry());
2902 }
2903 ___masm. bind(*stub->continuation());
2904}
2905
2906
2907#line 2907 "ad_x86.cpp"
2908
2909
2910#ifndef PRODUCT
2911void Compile::adlc_verification() {
2912
2913 // Following assertions generated from definition section
2914}
2915#endif
2916
2917// Map from machine-independent register number to register_save_policy
2918const char register_save_policy[] = {
2919 'C', // R10
2920 'C', // R10_H
2921 'C', // R11
2922 'C', // R11_H
2923 'C', // R8
2924 'C', // R8_H
2925 'C', // R9
2926 'C', // R9_H
2927 'C', // R12
2928 'C', // R12_H
2929 'C', // RCX
2930 'C', // RCX_H
2931 'C', // RBX
2932 'C', // RBX_H
2933 'C', // RDI
2934 'C', // RDI_H
2935 'C', // RDX
2936 'C', // RDX_H
2937 'C', // RSI
2938 'C', // RSI_H
2939 'C', // RAX
2940 'C', // RAX_H
2941 'N', // RBP
2942 'N', // RBP_H
2943 'C', // R13
2944 'C', // R13_H
2945 'C', // R14
2946 'C', // R14_H
2947 'C', // R15
2948 'C', // R15_H
2949 'N', // RSP
2950 'N', // RSP_H
2951 'C', // XMM0
2952 'C', // XMM0b
2953 'C', // XMM0c
2954 'C', // XMM0d
2955 'C', // XMM0e
2956 'C', // XMM0f
2957 'C', // XMM0g
2958 'C', // XMM0h
2959 'C', // XMM0i
2960 'C', // XMM0j
2961 'C', // XMM0k
2962 'C', // XMM0l
2963 'C', // XMM0m
2964 'C', // XMM0n
2965 'C', // XMM0o
2966 'C', // XMM0p
2967 'C', // XMM1
2968 'C', // XMM1b
2969 'C', // XMM1c
2970 'C', // XMM1d
2971 'C', // XMM1e
2972 'C', // XMM1f
2973 'C', // XMM1g
2974 'C', // XMM1h
2975 'C', // XMM1i
2976 'C', // XMM1j
2977 'C', // XMM1k
2978 'C', // XMM1l
2979 'C', // XMM1m
2980 'C', // XMM1n
2981 'C', // XMM1o
2982 'C', // XMM1p
2983 'C', // XMM2
2984 'C', // XMM2b
2985 'C', // XMM2c
2986 'C', // XMM2d
2987 'C', // XMM2e
2988 'C', // XMM2f
2989 'C', // XMM2g
2990 'C', // XMM2h
2991 'C', // XMM2i
2992 'C', // XMM2j
2993 'C', // XMM2k
2994 'C', // XMM2l
2995 'C', // XMM2m
2996 'C', // XMM2n
2997 'C', // XMM2o
2998 'C', // XMM2p
2999 'C', // XMM3
3000 'C', // XMM3b
3001 'C', // XMM3c
3002 'C', // XMM3d
3003 'C', // XMM3e
3004 'C', // XMM3f
3005 'C', // XMM3g
3006 'C', // XMM3h
3007 'C', // XMM3i
3008 'C', // XMM3j
3009 'C', // XMM3k
3010 'C', // XMM3l
3011 'C', // XMM3m
3012 'C', // XMM3n
3013 'C', // XMM3o
3014 'C', // XMM3p
3015 'C', // XMM4
3016 'C', // XMM4b
3017 'C', // XMM4c
3018 'C', // XMM4d
3019 'C', // XMM4e
3020 'C', // XMM4f
3021 'C', // XMM4g
3022 'C', // XMM4h
3023 'C', // XMM4i
3024 'C', // XMM4j
3025 'C', // XMM4k
3026 'C', // XMM4l
3027 'C', // XMM4m
3028 'C', // XMM4n
3029 'C', // XMM4o
3030 'C', // XMM4p
3031 'C', // XMM5
3032 'C', // XMM5b
3033 'C', // XMM5c
3034 'C', // XMM5d
3035 'C', // XMM5e
3036 'C', // XMM5f
3037 'C', // XMM5g
3038 'C', // XMM5h
3039 'C', // XMM5i
3040 'C', // XMM5j
3041 'C', // XMM5k
3042 'C', // XMM5l
3043 'C', // XMM5m
3044 'C', // XMM5n
3045 'C', // XMM5o
3046 'C', // XMM5p
3047 'C', // XMM6
3048 'C', // XMM6b
3049 'C', // XMM6c
3050 'C', // XMM6d
3051 'C', // XMM6e
3052 'C', // XMM6f
3053 'C', // XMM6g
3054 'C', // XMM6h
3055 'C', // XMM6i
3056 'C', // XMM6j
3057 'C', // XMM6k
3058 'C', // XMM6l
3059 'C', // XMM6m
3060 'C', // XMM6n
3061 'C', // XMM6o
3062 'C', // XMM6p
3063 'C', // XMM7
3064 'C', // XMM7b
3065 'C', // XMM7c
3066 'C', // XMM7d
3067 'C', // XMM7e
3068 'C', // XMM7f
3069 'C', // XMM7g
3070 'C', // XMM7h
3071 'C', // XMM7i
3072 'C', // XMM7j
3073 'C', // XMM7k
3074 'C', // XMM7l
3075 'C', // XMM7m
3076 'C', // XMM7n
3077 'C', // XMM7o
3078 'C', // XMM7p
3079 'C', // XMM8
3080 'C', // XMM8b
3081 'C', // XMM8c
3082 'C', // XMM8d
3083 'C', // XMM8e
3084 'C', // XMM8f
3085 'C', // XMM8g
3086 'C', // XMM8h
3087 'C', // XMM8i
3088 'C', // XMM8j
3089 'C', // XMM8k
3090 'C', // XMM8l
3091 'C', // XMM8m
3092 'C', // XMM8n
3093 'C', // XMM8o
3094 'C', // XMM8p
3095 'C', // XMM9
3096 'C', // XMM9b
3097 'C', // XMM9c
3098 'C', // XMM9d
3099 'C', // XMM9e
3100 'C', // XMM9f
3101 'C', // XMM9g
3102 'C', // XMM9h
3103 'C', // XMM9i
3104 'C', // XMM9j
3105 'C', // XMM9k
3106 'C', // XMM9l
3107 'C', // XMM9m
3108 'C', // XMM9n
3109 'C', // XMM9o
3110 'C', // XMM9p
3111 'C', // XMM10
3112 'C', // XMM10b
3113 'C', // XMM10c
3114 'C', // XMM10d
3115 'C', // XMM10e
3116 'C', // XMM10f
3117 'C', // XMM10g
3118 'C', // XMM10h
3119 'C', // XMM10i
3120 'C', // XMM10j
3121 'C', // XMM10k
3122 'C', // XMM10l
3123 'C', // XMM10m
3124 'C', // XMM10n
3125 'C', // XMM10o
3126 'C', // XMM10p
3127 'C', // XMM11
3128 'C', // XMM11b
3129 'C', // XMM11c
3130 'C', // XMM11d
3131 'C', // XMM11e
3132 'C', // XMM11f
3133 'C', // XMM11g
3134 'C', // XMM11h
3135 'C', // XMM11i
3136 'C', // XMM11j
3137 'C', // XMM11k
3138 'C', // XMM11l
3139 'C', // XMM11m
3140 'C', // XMM11n
3141 'C', // XMM11o
3142 'C', // XMM11p
3143 'C', // XMM12
3144 'C', // XMM12b
3145 'C', // XMM12c
3146 'C', // XMM12d
3147 'C', // XMM12e
3148 'C', // XMM12f
3149 'C', // XMM12g
3150 'C', // XMM12h
3151 'C', // XMM12i
3152 'C', // XMM12j
3153 'C', // XMM12k
3154 'C', // XMM12l
3155 'C', // XMM12m
3156 'C', // XMM12n
3157 'C', // XMM12o
3158 'C', // XMM12p
3159 'C', // XMM13
3160 'C', // XMM13b
3161 'C', // XMM13c
3162 'C', // XMM13d
3163 'C', // XMM13e
3164 'C', // XMM13f
3165 'C', // XMM13g
3166 'C', // XMM13h
3167 'C', // XMM13i
3168 'C', // XMM13j
3169 'C', // XMM13k
3170 'C', // XMM13l
3171 'C', // XMM13m
3172 'C', // XMM13n
3173 'C', // XMM13o
3174 'C', // XMM13p
3175 'C', // XMM14
3176 'C', // XMM14b
3177 'C', // XMM14c
3178 'C', // XMM14d
3179 'C', // XMM14e
3180 'C', // XMM14f
3181 'C', // XMM14g
3182 'C', // XMM14h
3183 'C', // XMM14i
3184 'C', // XMM14j
3185 'C', // XMM14k
3186 'C', // XMM14l
3187 'C', // XMM14m
3188 'C', // XMM14n
3189 'C', // XMM14o
3190 'C', // XMM14p
3191 'C', // XMM15
3192 'C', // XMM15b
3193 'C', // XMM15c
3194 'C', // XMM15d
3195 'C', // XMM15e
3196 'C', // XMM15f
3197 'C', // XMM15g
3198 'C', // XMM15h
3199 'C', // XMM15i
3200 'C', // XMM15j
3201 'C', // XMM15k
3202 'C', // XMM15l
3203 'C', // XMM15m
3204 'C', // XMM15n
3205 'C', // XMM15o
3206 'C', // XMM15p
3207 'C', // XMM16
3208 'C', // XMM16b
3209 'C', // XMM16c
3210 'C', // XMM16d
3211 'C', // XMM16e
3212 'C', // XMM16f
3213 'C', // XMM16g
3214 'C', // XMM16h
3215 'C', // XMM16i
3216 'C', // XMM16j
3217 'C', // XMM16k
3218 'C', // XMM16l
3219 'C', // XMM16m
3220 'C', // XMM16n
3221 'C', // XMM16o
3222 'C', // XMM16p
3223 'C', // XMM17
3224 'C', // XMM17b
3225 'C', // XMM17c
3226 'C', // XMM17d
3227 'C', // XMM17e
3228 'C', // XMM17f
3229 'C', // XMM17g
3230 'C', // XMM17h
3231 'C', // XMM17i
3232 'C', // XMM17j
3233 'C', // XMM17k
3234 'C', // XMM17l
3235 'C', // XMM17m
3236 'C', // XMM17n
3237 'C', // XMM17o
3238 'C', // XMM17p
3239 'C', // XMM18
3240 'C', // XMM18b
3241 'C', // XMM18c
3242 'C', // XMM18d
3243 'C', // XMM18e
3244 'C', // XMM18f
3245 'C', // XMM18g
3246 'C', // XMM18h
3247 'C', // XMM18i
3248 'C', // XMM18j
3249 'C', // XMM18k
3250 'C', // XMM18l
3251 'C', // XMM18m
3252 'C', // XMM18n
3253 'C', // XMM18o
3254 'C', // XMM18p
3255 'C', // XMM19
3256 'C', // XMM19b
3257 'C', // XMM19c
3258 'C', // XMM19d
3259 'C', // XMM19e
3260 'C', // XMM19f
3261 'C', // XMM19g
3262 'C', // XMM19h
3263 'C', // XMM19i
3264 'C', // XMM19j
3265 'C', // XMM19k
3266 'C', // XMM19l
3267 'C', // XMM19m
3268 'C', // XMM19n
3269 'C', // XMM19o
3270 'C', // XMM19p
3271 'C', // XMM20
3272 'C', // XMM20b
3273 'C', // XMM20c
3274 'C', // XMM20d
3275 'C', // XMM20e
3276 'C', // XMM20f
3277 'C', // XMM20g
3278 'C', // XMM20h
3279 'C', // XMM20i
3280 'C', // XMM20j
3281 'C', // XMM20k
3282 'C', // XMM20l
3283 'C', // XMM20m
3284 'C', // XMM20n
3285 'C', // XMM20o
3286 'C', // XMM20p
3287 'C', // XMM21
3288 'C', // XMM21b
3289 'C', // XMM21c
3290 'C', // XMM21d
3291 'C', // XMM21e
3292 'C', // XMM21f
3293 'C', // XMM21g
3294 'C', // XMM21h
3295 'C', // XMM21i
3296 'C', // XMM21j
3297 'C', // XMM21k
3298 'C', // XMM21l
3299 'C', // XMM21m
3300 'C', // XMM21n
3301 'C', // XMM21o
3302 'C', // XMM21p
3303 'C', // XMM22
3304 'C', // XMM22b
3305 'C', // XMM22c
3306 'C', // XMM22d
3307 'C', // XMM22e
3308 'C', // XMM22f
3309 'C', // XMM22g
3310 'C', // XMM22h
3311 'C', // XMM22i
3312 'C', // XMM22j
3313 'C', // XMM22k
3314 'C', // XMM22l
3315 'C', // XMM22m
3316 'C', // XMM22n
3317 'C', // XMM22o
3318 'C', // XMM22p
3319 'C', // XMM23
3320 'C', // XMM23b
3321 'C', // XMM23c
3322 'C', // XMM23d
3323 'C', // XMM23e
3324 'C', // XMM23f
3325 'C', // XMM23g
3326 'C', // XMM23h
3327 'C', // XMM23i
3328 'C', // XMM23j
3329 'C', // XMM23k
3330 'C', // XMM23l
3331 'C', // XMM23m
3332 'C', // XMM23n
3333 'C', // XMM23o
3334 'C', // XMM23p
3335 'C', // XMM24
3336 'C', // XMM24b
3337 'C', // XMM24c
3338 'C', // XMM24d
3339 'C', // XMM24e
3340 'C', // XMM24f
3341 'C', // XMM24g
3342 'C', // XMM24h
3343 'C', // XMM24i
3344 'C', // XMM24j
3345 'C', // XMM24k
3346 'C', // XMM24l
3347 'C', // XMM24m
3348 'C', // XMM24n
3349 'C', // XMM24o
3350 'C', // XMM24p
3351 'C', // XMM25
3352 'C', // XMM25b
3353 'C', // XMM25c
3354 'C', // XMM25d
3355 'C', // XMM25e
3356 'C', // XMM25f
3357 'C', // XMM25g
3358 'C', // XMM25h
3359 'C', // XMM25i
3360 'C', // XMM25j
3361 'C', // XMM25k
3362 'C', // XMM25l
3363 'C', // XMM25m
3364 'C', // XMM25n
3365 'C', // XMM25o
3366 'C', // XMM25p
3367 'C', // XMM26
3368 'C', // XMM26b
3369 'C', // XMM26c
3370 'C', // XMM26d
3371 'C', // XMM26e
3372 'C', // XMM26f
3373 'C', // XMM26g
3374 'C', // XMM26h
3375 'C', // XMM26i
3376 'C', // XMM26j
3377 'C', // XMM26k
3378 'C', // XMM26l
3379 'C', // XMM26m
3380 'C', // XMM26n
3381 'C', // XMM26o
3382 'C', // XMM26p
3383 'C', // XMM27
3384 'C', // XMM27b
3385 'C', // XMM27c
3386 'C', // XMM27d
3387 'C', // XMM27e
3388 'C', // XMM27f
3389 'C', // XMM27g
3390 'C', // XMM27h
3391 'C', // XMM27i
3392 'C', // XMM27j
3393 'C', // XMM27k
3394 'C', // XMM27l
3395 'C', // XMM27m
3396 'C', // XMM27n
3397 'C', // XMM27o
3398 'C', // XMM27p
3399 'C', // XMM28
3400 'C', // XMM28b
3401 'C', // XMM28c
3402 'C', // XMM28d
3403 'C', // XMM28e
3404 'C', // XMM28f
3405 'C', // XMM28g
3406 'C', // XMM28h
3407 'C', // XMM28i
3408 'C', // XMM28j
3409 'C', // XMM28k
3410 'C', // XMM28l
3411 'C', // XMM28m
3412 'C', // XMM28n
3413 'C', // XMM28o
3414 'C', // XMM28p
3415 'C', // XMM29
3416 'C', // XMM29b
3417 'C', // XMM29c
3418 'C', // XMM29d
3419 'C', // XMM29e
3420 'C', // XMM29f
3421 'C', // XMM29g
3422 'C', // XMM29h
3423 'C', // XMM29i
3424 'C', // XMM29j
3425 'C', // XMM29k
3426 'C', // XMM29l
3427 'C', // XMM29m
3428 'C', // XMM29n
3429 'C', // XMM29o
3430 'C', // XMM29p
3431 'C', // XMM30
3432 'C', // XMM30b
3433 'C', // XMM30c
3434 'C', // XMM30d
3435 'C', // XMM30e
3436 'C', // XMM30f
3437 'C', // XMM30g
3438 'C', // XMM30h
3439 'C', // XMM30i
3440 'C', // XMM30j
3441 'C', // XMM30k
3442 'C', // XMM30l
3443 'C', // XMM30m
3444 'C', // XMM30n
3445 'C', // XMM30o
3446 'C', // XMM30p
3447 'C', // XMM31
3448 'C', // XMM31b
3449 'C', // XMM31c
3450 'C', // XMM31d
3451 'C', // XMM31e
3452 'C', // XMM31f
3453 'C', // XMM31g
3454 'C', // XMM31h
3455 'C', // XMM31i
3456 'C', // XMM31j
3457 'C', // XMM31k
3458 'C', // XMM31l
3459 'C', // XMM31m
3460 'C', // XMM31n
3461 'C', // XMM31o
3462 'C', // XMM31p
3463 'C', // K7
3464 'C', // K7_H
3465 'C', // K6
3466 'C', // K6_H
3467 'C', // K5
3468 'C', // K5_H
3469 'C', // K4
3470 'C', // K4_H
3471 'C', // K3
3472 'C', // K3_H
3473 'C', // K2
3474 'C', // K2_H
3475 'C', // K1
3476 'C', // K1_H
3477 'C' // no trailing comma // RFLAGS
3478};
3479
3480// Map from machine-independent register number to c_reg_save_policy
3481const char c_reg_save_policy[] = {
3482 'C', // R10
3483 'C', // R10_H
3484 'C', // R11
3485 'C', // R11_H
3486 'C', // R8
3487 'C', // R8_H
3488 'C', // R9
3489 'C', // R9_H
3490 'E', // R12
3491 'E', // R12_H
3492 'C', // RCX
3493 'C', // RCX_H
3494 'E', // RBX
3495 'E', // RBX_H
3496 'C', // RDI
3497 'C', // RDI_H
3498 'C', // RDX
3499 'C', // RDX_H
3500 'C', // RSI
3501 'C', // RSI_H
3502 'C', // RAX
3503 'C', // RAX_H
3504 'E', // RBP
3505 'E', // RBP_H
3506 'E', // R13
3507 'E', // R13_H
3508 'E', // R14
3509 'E', // R14_H
3510 'E', // R15
3511 'E', // R15_H
3512 'N', // RSP
3513 'N', // RSP_H
3514 'C', // XMM0
3515 'C', // XMM0b
3516 'C', // XMM0c
3517 'C', // XMM0d
3518 'C', // XMM0e
3519 'C', // XMM0f
3520 'C', // XMM0g
3521 'C', // XMM0h
3522 'C', // XMM0i
3523 'C', // XMM0j
3524 'C', // XMM0k
3525 'C', // XMM0l
3526 'C', // XMM0m
3527 'C', // XMM0n
3528 'C', // XMM0o
3529 'C', // XMM0p
3530 'C', // XMM1
3531 'C', // XMM1b
3532 'C', // XMM1c
3533 'C', // XMM1d
3534 'C', // XMM1e
3535 'C', // XMM1f
3536 'C', // XMM1g
3537 'C', // XMM1h
3538 'C', // XMM1i
3539 'C', // XMM1j
3540 'C', // XMM1k
3541 'C', // XMM1l
3542 'C', // XMM1m
3543 'C', // XMM1n
3544 'C', // XMM1o
3545 'C', // XMM1p
3546 'C', // XMM2
3547 'C', // XMM2b
3548 'C', // XMM2c
3549 'C', // XMM2d
3550 'C', // XMM2e
3551 'C', // XMM2f
3552 'C', // XMM2g
3553 'C', // XMM2h
3554 'C', // XMM2i
3555 'C', // XMM2j
3556 'C', // XMM2k
3557 'C', // XMM2l
3558 'C', // XMM2m
3559 'C', // XMM2n
3560 'C', // XMM2o
3561 'C', // XMM2p
3562 'C', // XMM3
3563 'C', // XMM3b
3564 'C', // XMM3c
3565 'C', // XMM3d
3566 'C', // XMM3e
3567 'C', // XMM3f
3568 'C', // XMM3g
3569 'C', // XMM3h
3570 'C', // XMM3i
3571 'C', // XMM3j
3572 'C', // XMM3k
3573 'C', // XMM3l
3574 'C', // XMM3m
3575 'C', // XMM3n
3576 'C', // XMM3o
3577 'C', // XMM3p
3578 'C', // XMM4
3579 'C', // XMM4b
3580 'C', // XMM4c
3581 'C', // XMM4d
3582 'C', // XMM4e
3583 'C', // XMM4f
3584 'C', // XMM4g
3585 'C', // XMM4h
3586 'C', // XMM4i
3587 'C', // XMM4j
3588 'C', // XMM4k
3589 'C', // XMM4l
3590 'C', // XMM4m
3591 'C', // XMM4n
3592 'C', // XMM4o
3593 'C', // XMM4p
3594 'C', // XMM5
3595 'C', // XMM5b
3596 'C', // XMM5c
3597 'C', // XMM5d
3598 'C', // XMM5e
3599 'C', // XMM5f
3600 'C', // XMM5g
3601 'C', // XMM5h
3602 'C', // XMM5i
3603 'C', // XMM5j
3604 'C', // XMM5k
3605 'C', // XMM5l
3606 'C', // XMM5m
3607 'C', // XMM5n
3608 'C', // XMM5o
3609 'C', // XMM5p
3610 'C', // XMM6
3611 'C', // XMM6b
3612 'C', // XMM6c
3613 'C', // XMM6d
3614 'C', // XMM6e
3615 'C', // XMM6f
3616 'C', // XMM6g
3617 'C', // XMM6h
3618 'C', // XMM6i
3619 'C', // XMM6j
3620 'C', // XMM6k
3621 'C', // XMM6l
3622 'C', // XMM6m
3623 'C', // XMM6n
3624 'C', // XMM6o
3625 'C', // XMM6p
3626 'C', // XMM7
3627 'C', // XMM7b
3628 'C', // XMM7c
3629 'C', // XMM7d
3630 'C', // XMM7e
3631 'C', // XMM7f
3632 'C', // XMM7g
3633 'C', // XMM7h
3634 'C', // XMM7i
3635 'C', // XMM7j
3636 'C', // XMM7k
3637 'C', // XMM7l
3638 'C', // XMM7m
3639 'C', // XMM7n
3640 'C', // XMM7o
3641 'C', // XMM7p
3642 'C', // XMM8
3643 'C', // XMM8b
3644 'C', // XMM8c
3645 'C', // XMM8d
3646 'C', // XMM8e
3647 'C', // XMM8f
3648 'C', // XMM8g
3649 'C', // XMM8h
3650 'C', // XMM8i
3651 'C', // XMM8j
3652 'C', // XMM8k
3653 'C', // XMM8l
3654 'C', // XMM8m
3655 'C', // XMM8n
3656 'C', // XMM8o
3657 'C', // XMM8p
3658 'C', // XMM9
3659 'C', // XMM9b
3660 'C', // XMM9c
3661 'C', // XMM9d
3662 'C', // XMM9e
3663 'C', // XMM9f
3664 'C', // XMM9g
3665 'C', // XMM9h
3666 'C', // XMM9i
3667 'C', // XMM9j
3668 'C', // XMM9k
3669 'C', // XMM9l
3670 'C', // XMM9m
3671 'C', // XMM9n
3672 'C', // XMM9o
3673 'C', // XMM9p
3674 'C', // XMM10
3675 'C', // XMM10b
3676 'C', // XMM10c
3677 'C', // XMM10d
3678 'C', // XMM10e
3679 'C', // XMM10f
3680 'C', // XMM10g
3681 'C', // XMM10h
3682 'C', // XMM10i
3683 'C', // XMM10j
3684 'C', // XMM10k
3685 'C', // XMM10l
3686 'C', // XMM10m
3687 'C', // XMM10n
3688 'C', // XMM10o
3689 'C', // XMM10p
3690 'C', // XMM11
3691 'C', // XMM11b
3692 'C', // XMM11c
3693 'C', // XMM11d
3694 'C', // XMM11e
3695 'C', // XMM11f
3696 'C', // XMM11g
3697 'C', // XMM11h
3698 'C', // XMM11i
3699 'C', // XMM11j
3700 'C', // XMM11k
3701 'C', // XMM11l
3702 'C', // XMM11m
3703 'C', // XMM11n
3704 'C', // XMM11o
3705 'C', // XMM11p
3706 'C', // XMM12
3707 'C', // XMM12b
3708 'C', // XMM12c
3709 'C', // XMM12d
3710 'C', // XMM12e
3711 'C', // XMM12f
3712 'C', // XMM12g
3713 'C', // XMM12h
3714 'C', // XMM12i
3715 'C', // XMM12j
3716 'C', // XMM12k
3717 'C', // XMM12l
3718 'C', // XMM12m
3719 'C', // XMM12n
3720 'C', // XMM12o
3721 'C', // XMM12p
3722 'C', // XMM13
3723 'C', // XMM13b
3724 'C', // XMM13c
3725 'C', // XMM13d
3726 'C', // XMM13e
3727 'C', // XMM13f
3728 'C', // XMM13g
3729 'C', // XMM13h
3730 'C', // XMM13i
3731 'C', // XMM13j
3732 'C', // XMM13k
3733 'C', // XMM13l
3734 'C', // XMM13m
3735 'C', // XMM13n
3736 'C', // XMM13o
3737 'C', // XMM13p
3738 'C', // XMM14
3739 'C', // XMM14b
3740 'C', // XMM14c
3741 'C', // XMM14d
3742 'C', // XMM14e
3743 'C', // XMM14f
3744 'C', // XMM14g
3745 'C', // XMM14h
3746 'C', // XMM14i
3747 'C', // XMM14j
3748 'C', // XMM14k
3749 'C', // XMM14l
3750 'C', // XMM14m
3751 'C', // XMM14n
3752 'C', // XMM14o
3753 'C', // XMM14p
3754 'C', // XMM15
3755 'C', // XMM15b
3756 'C', // XMM15c
3757 'C', // XMM15d
3758 'C', // XMM15e
3759 'C', // XMM15f
3760 'C', // XMM15g
3761 'C', // XMM15h
3762 'C', // XMM15i
3763 'C', // XMM15j
3764 'C', // XMM15k
3765 'C', // XMM15l
3766 'C', // XMM15m
3767 'C', // XMM15n
3768 'C', // XMM15o
3769 'C', // XMM15p
3770 'C', // XMM16
3771 'C', // XMM16b
3772 'C', // XMM16c
3773 'C', // XMM16d
3774 'C', // XMM16e
3775 'C', // XMM16f
3776 'C', // XMM16g
3777 'C', // XMM16h
3778 'C', // XMM16i
3779 'C', // XMM16j
3780 'C', // XMM16k
3781 'C', // XMM16l
3782 'C', // XMM16m
3783 'C', // XMM16n
3784 'C', // XMM16o
3785 'C', // XMM16p
3786 'C', // XMM17
3787 'C', // XMM17b
3788 'C', // XMM17c
3789 'C', // XMM17d
3790 'C', // XMM17e
3791 'C', // XMM17f
3792 'C', // XMM17g
3793 'C', // XMM17h
3794 'C', // XMM17i
3795 'C', // XMM17j
3796 'C', // XMM17k
3797 'C', // XMM17l
3798 'C', // XMM17m
3799 'C', // XMM17n
3800 'C', // XMM17o
3801 'C', // XMM17p
3802 'C', // XMM18
3803 'C', // XMM18b
3804 'C', // XMM18c
3805 'C', // XMM18d
3806 'C', // XMM18e
3807 'C', // XMM18f
3808 'C', // XMM18g
3809 'C', // XMM18h
3810 'C', // XMM18i
3811 'C', // XMM18j
3812 'C', // XMM18k
3813 'C', // XMM18l
3814 'C', // XMM18m
3815 'C', // XMM18n
3816 'C', // XMM18o
3817 'C', // XMM18p
3818 'C', // XMM19
3819 'C', // XMM19b
3820 'C', // XMM19c
3821 'C', // XMM19d
3822 'C', // XMM19e
3823 'C', // XMM19f
3824 'C', // XMM19g
3825 'C', // XMM19h
3826 'C', // XMM19i
3827 'C', // XMM19j
3828 'C', // XMM19k
3829 'C', // XMM19l
3830 'C', // XMM19m
3831 'C', // XMM19n
3832 'C', // XMM19o
3833 'C', // XMM19p
3834 'C', // XMM20
3835 'C', // XMM20b
3836 'C', // XMM20c
3837 'C', // XMM20d
3838 'C', // XMM20e
3839 'C', // XMM20f
3840 'C', // XMM20g
3841 'C', // XMM20h
3842 'C', // XMM20i
3843 'C', // XMM20j
3844 'C', // XMM20k
3845 'C', // XMM20l
3846 'C', // XMM20m
3847 'C', // XMM20n
3848 'C', // XMM20o
3849 'C', // XMM20p
3850 'C', // XMM21
3851 'C', // XMM21b
3852 'C', // XMM21c
3853 'C', // XMM21d
3854 'C', // XMM21e
3855 'C', // XMM21f
3856 'C', // XMM21g
3857 'C', // XMM21h
3858 'C', // XMM21i
3859 'C', // XMM21j
3860 'C', // XMM21k
3861 'C', // XMM21l
3862 'C', // XMM21m
3863 'C', // XMM21n
3864 'C', // XMM21o
3865 'C', // XMM21p
3866 'C', // XMM22
3867 'C', // XMM22b
3868 'C', // XMM22c
3869 'C', // XMM22d
3870 'C', // XMM22e
3871 'C', // XMM22f
3872 'C', // XMM22g
3873 'C', // XMM22h
3874 'C', // XMM22i
3875 'C', // XMM22j
3876 'C', // XMM22k
3877 'C', // XMM22l
3878 'C', // XMM22m
3879 'C', // XMM22n
3880 'C', // XMM22o
3881 'C', // XMM22p
3882 'C', // XMM23
3883 'C', // XMM23b
3884 'C', // XMM23c
3885 'C', // XMM23d
3886 'C', // XMM23e
3887 'C', // XMM23f
3888 'C', // XMM23g
3889 'C', // XMM23h
3890 'C', // XMM23i
3891 'C', // XMM23j
3892 'C', // XMM23k
3893 'C', // XMM23l
3894 'C', // XMM23m
3895 'C', // XMM23n
3896 'C', // XMM23o
3897 'C', // XMM23p
3898 'C', // XMM24
3899 'C', // XMM24b
3900 'C', // XMM24c
3901 'C', // XMM24d
3902 'C', // XMM24e
3903 'C', // XMM24f
3904 'C', // XMM24g
3905 'C', // XMM24h
3906 'C', // XMM24i
3907 'C', // XMM24j
3908 'C', // XMM24k
3909 'C', // XMM24l
3910 'C', // XMM24m
3911 'C', // XMM24n
3912 'C', // XMM24o
3913 'C', // XMM24p
3914 'C', // XMM25
3915 'C', // XMM25b
3916 'C', // XMM25c
3917 'C', // XMM25d
3918 'C', // XMM25e
3919 'C', // XMM25f
3920 'C', // XMM25g
3921 'C', // XMM25h
3922 'C', // XMM25i
3923 'C', // XMM25j
3924 'C', // XMM25k
3925 'C', // XMM25l
3926 'C', // XMM25m
3927 'C', // XMM25n
3928 'C', // XMM25o
3929 'C', // XMM25p
3930 'C', // XMM26
3931 'C', // XMM26b
3932 'C', // XMM26c
3933 'C', // XMM26d
3934 'C', // XMM26e
3935 'C', // XMM26f
3936 'C', // XMM26g
3937 'C', // XMM26h
3938 'C', // XMM26i
3939 'C', // XMM26j
3940 'C', // XMM26k
3941 'C', // XMM26l
3942 'C', // XMM26m
3943 'C', // XMM26n
3944 'C', // XMM26o
3945 'C', // XMM26p
3946 'C', // XMM27
3947 'C', // XMM27b
3948 'C', // XMM27c
3949 'C', // XMM27d
3950 'C', // XMM27e
3951 'C', // XMM27f
3952 'C', // XMM27g
3953 'C', // XMM27h
3954 'C', // XMM27i
3955 'C', // XMM27j
3956 'C', // XMM27k
3957 'C', // XMM27l
3958 'C', // XMM27m
3959 'C', // XMM27n
3960 'C', // XMM27o
3961 'C', // XMM27p
3962 'C', // XMM28
3963 'C', // XMM28b
3964 'C', // XMM28c
3965 'C', // XMM28d
3966 'C', // XMM28e
3967 'C', // XMM28f
3968 'C', // XMM28g
3969 'C', // XMM28h
3970 'C', // XMM28i
3971 'C', // XMM28j
3972 'C', // XMM28k
3973 'C', // XMM28l
3974 'C', // XMM28m
3975 'C', // XMM28n
3976 'C', // XMM28o
3977 'C', // XMM28p
3978 'C', // XMM29
3979 'C', // XMM29b
3980 'C', // XMM29c
3981 'C', // XMM29d
3982 'C', // XMM29e
3983 'C', // XMM29f
3984 'C', // XMM29g
3985 'C', // XMM29h
3986 'C', // XMM29i
3987 'C', // XMM29j
3988 'C', // XMM29k
3989 'C', // XMM29l
3990 'C', // XMM29m
3991 'C', // XMM29n
3992 'C', // XMM29o
3993 'C', // XMM29p
3994 'C', // XMM30
3995 'C', // XMM30b
3996 'C', // XMM30c
3997 'C', // XMM30d
3998 'C', // XMM30e
3999 'C', // XMM30f
4000 'C', // XMM30g
4001 'C', // XMM30h
4002 'C', // XMM30i
4003 'C', // XMM30j
4004 'C', // XMM30k
4005 'C', // XMM30l
4006 'C', // XMM30m
4007 'C', // XMM30n
4008 'C', // XMM30o
4009 'C', // XMM30p
4010 'C', // XMM31
4011 'C', // XMM31b
4012 'C', // XMM31c
4013 'C', // XMM31d
4014 'C', // XMM31e
4015 'C', // XMM31f
4016 'C', // XMM31g
4017 'C', // XMM31h
4018 'C', // XMM31i
4019 'C', // XMM31j
4020 'C', // XMM31k
4021 'C', // XMM31l
4022 'C', // XMM31m
4023 'C', // XMM31n
4024 'C', // XMM31o
4025 'C', // XMM31p
4026 'C', // K7
4027 'C', // K7_H
4028 'C', // K6
4029 'C', // K6_H
4030 'C', // K5
4031 'C', // K5_H
4032 'C', // K4
4033 'C', // K4_H
4034 'C', // K3
4035 'C', // K3_H
4036 'C', // K2
4037 'C', // K2_H
4038 'C', // K1
4039 'C', // K1_H
4040 'C' // no trailing comma // RFLAGS
4041};
4042
4043// Map from machine-independent register number to register_save_type
4044const int register_save_type[] = {
4045 Op_RegI,
4046 Op_RegI,
4047 Op_RegI,
4048 Op_RegI,
4049 Op_RegI,
4050 Op_RegI,
4051 Op_RegI,
4052 Op_RegI,
4053 Op_RegI,
4054 Op_RegI,
4055 Op_RegI,
4056 Op_RegI,
4057 Op_RegI,
4058 Op_RegI,
4059 Op_RegI,
4060 Op_RegI,
4061 Op_RegI,
4062 Op_RegI,
4063 Op_RegI,
4064 Op_RegI,
4065 Op_RegI,
4066 Op_RegI,
4067 Op_RegI,
4068 Op_RegI,
4069 Op_RegI,
4070 Op_RegI,
4071 Op_RegI,
4072 Op_RegI,
4073 Op_RegI,
4074 Op_RegI,
4075 Op_RegI,
4076 Op_RegI,
4077 Op_RegF,
4078 Op_RegF,
4079 Op_RegF,
4080 Op_RegF,
4081 Op_RegF,
4082 Op_RegF,
4083 Op_RegF,
4084 Op_RegF,
4085 Op_RegF,
4086 Op_RegF,
4087 Op_RegF,
4088 Op_RegF,
4089 Op_RegF,
4090 Op_RegF,
4091 Op_RegF,
4092 Op_RegF,
4093 Op_RegF,
4094 Op_RegF,
4095 Op_RegF,
4096 Op_RegF,
4097 Op_RegF,
4098 Op_RegF,
4099 Op_RegF,
4100 Op_RegF,
4101 Op_RegF,
4102 Op_RegF,
4103 Op_RegF,
4104 Op_RegF,
4105 Op_RegF,
4106 Op_RegF,
4107 Op_RegF,
4108 Op_RegF,
4109 Op_RegF,
4110 Op_RegF,
4111 Op_RegF,
4112 Op_RegF,
4113 Op_RegF,
4114 Op_RegF,
4115 Op_RegF,
4116 Op_RegF,
4117 Op_RegF,
4118 Op_RegF,
4119 Op_RegF,
4120 Op_RegF,
4121 Op_RegF,
4122 Op_RegF,
4123 Op_RegF,
4124 Op_RegF,
4125 Op_RegF,
4126 Op_RegF,
4127 Op_RegF,
4128 Op_RegF,
4129 Op_RegF,
4130 Op_RegF,
4131 Op_RegF,
4132 Op_RegF,
4133 Op_RegF,
4134 Op_RegF,
4135 Op_RegF,
4136 Op_RegF,
4137 Op_RegF,
4138 Op_RegF,
4139 Op_RegF,
4140 Op_RegF,
4141 Op_RegF,
4142 Op_RegF,
4143 Op_RegF,
4144 Op_RegF,
4145 Op_RegF,
4146 Op_RegF,
4147 Op_RegF,
4148 Op_RegF,
4149 Op_RegF,
4150 Op_RegF,
4151 Op_RegF,
4152 Op_RegF,
4153 Op_RegF,
4154 Op_RegF,
4155 Op_RegF,
4156 Op_RegF,
4157 Op_RegF,
4158 Op_RegF,
4159 Op_RegF,
4160 Op_RegF,
4161 Op_RegF,
4162 Op_RegF,
4163 Op_RegF,
4164 Op_RegF,
4165 Op_RegF,
4166 Op_RegF,
4167 Op_RegF,
4168 Op_RegF,
4169 Op_RegF,
4170 Op_RegF,
4171 Op_RegF,
4172 Op_RegF,
4173 Op_RegF,
4174 Op_RegF,
4175 Op_RegF,
4176 Op_RegF,
4177 Op_RegF,
4178 Op_RegF,
4179 Op_RegF,
4180 Op_RegF,
4181 Op_RegF,
4182 Op_RegF,
4183 Op_RegF,
4184 Op_RegF,
4185 Op_RegF,
4186 Op_RegF,
4187 Op_RegF,
4188 Op_RegF,
4189 Op_RegF,
4190 Op_RegF,
4191 Op_RegF,
4192 Op_RegF,
4193 Op_RegF,
4194 Op_RegF,
4195 Op_RegF,
4196 Op_RegF,
4197 Op_RegF,
4198 Op_RegF,
4199 Op_RegF,
4200 Op_RegF,
4201 Op_RegF,
4202 Op_RegF,
4203 Op_RegF,
4204 Op_RegF,
4205 Op_RegF,
4206 Op_RegF,
4207 Op_RegF,
4208 Op_RegF,
4209 Op_RegF,
4210 Op_RegF,
4211 Op_RegF,
4212 Op_RegF,
4213 Op_RegF,
4214 Op_RegF,
4215 Op_RegF,
4216 Op_RegF,
4217 Op_RegF,
4218 Op_RegF,
4219 Op_RegF,
4220 Op_RegF,
4221 Op_RegF,
4222 Op_RegF,
4223 Op_RegF,
4224 Op_RegF,
4225 Op_RegF,
4226 Op_RegF,
4227 Op_RegF,
4228 Op_RegF,
4229 Op_RegF,
4230 Op_RegF,
4231 Op_RegF,
4232 Op_RegF,
4233 Op_RegF,
4234 Op_RegF,
4235 Op_RegF,
4236 Op_RegF,
4237 Op_RegF,
4238 Op_RegF,
4239 Op_RegF,
4240 Op_RegF,
4241 Op_RegF,
4242 Op_RegF,
4243 Op_RegF,
4244 Op_RegF,
4245 Op_RegF,
4246 Op_RegF,
4247 Op_RegF,
4248 Op_RegF,
4249 Op_RegF,
4250 Op_RegF,
4251 Op_RegF,
4252 Op_RegF,
4253 Op_RegF,
4254 Op_RegF,
4255 Op_RegF,
4256 Op_RegF,
4257 Op_RegF,
4258 Op_RegF,
4259 Op_RegF,
4260 Op_RegF,
4261 Op_RegF,
4262 Op_RegF,
4263 Op_RegF,
4264 Op_RegF,
4265 Op_RegF,
4266 Op_RegF,
4267 Op_RegF,
4268 Op_RegF,
4269 Op_RegF,
4270 Op_RegF,
4271 Op_RegF,
4272 Op_RegF,
4273 Op_RegF,
4274 Op_RegF,
4275 Op_RegF,
4276 Op_RegF,
4277 Op_RegF,
4278 Op_RegF,
4279 Op_RegF,
4280 Op_RegF,
4281 Op_RegF,
4282 Op_RegF,
4283 Op_RegF,
4284 Op_RegF,
4285 Op_RegF,
4286 Op_RegF,
4287 Op_RegF,
4288 Op_RegF,
4289 Op_RegF,
4290 Op_RegF,
4291 Op_RegF,
4292 Op_RegF,
4293 Op_RegF,
4294 Op_RegF,
4295 Op_RegF,
4296 Op_RegF,
4297 Op_RegF,
4298 Op_RegF,
4299 Op_RegF,
4300 Op_RegF,
4301 Op_RegF,
4302 Op_RegF,
4303 Op_RegF,
4304 Op_RegF,
4305 Op_RegF,
4306 Op_RegF,
4307 Op_RegF,
4308 Op_RegF,
4309 Op_RegF,
4310 Op_RegF,
4311 Op_RegF,
4312 Op_RegF,
4313 Op_RegF,
4314 Op_RegF,
4315 Op_RegF,
4316 Op_RegF,
4317 Op_RegF,
4318 Op_RegF,
4319 Op_RegF,
4320 Op_RegF,
4321 Op_RegF,
4322 Op_RegF,
4323 Op_RegF,
4324 Op_RegF,
4325 Op_RegF,
4326 Op_RegF,
4327 Op_RegF,
4328 Op_RegF,
4329 Op_RegF,
4330 Op_RegF,
4331 Op_RegF,
4332 Op_RegF,
4333 Op_RegF,
4334 Op_RegF,
4335 Op_RegF,
4336 Op_RegF,
4337 Op_RegF,
4338 Op_RegF,
4339 Op_RegF,
4340 Op_RegF,
4341 Op_RegF,
4342 Op_RegF,
4343 Op_RegF,
4344 Op_RegF,
4345 Op_RegF,
4346 Op_RegF,
4347 Op_RegF,
4348 Op_RegF,
4349 Op_RegF,
4350 Op_RegF,
4351 Op_RegF,
4352 Op_RegF,
4353 Op_RegF,
4354 Op_RegF,
4355 Op_RegF,
4356 Op_RegF,
4357 Op_RegF,
4358 Op_RegF,
4359 Op_RegF,
4360 Op_RegF,
4361 Op_RegF,
4362 Op_RegF,
4363 Op_RegF,
4364 Op_RegF,
4365 Op_RegF,
4366 Op_RegF,
4367 Op_RegF,
4368 Op_RegF,
4369 Op_RegF,
4370 Op_RegF,
4371 Op_RegF,
4372 Op_RegF,
4373 Op_RegF,
4374 Op_RegF,
4375 Op_RegF,
4376 Op_RegF,
4377 Op_RegF,
4378 Op_RegF,
4379 Op_RegF,
4380 Op_RegF,
4381 Op_RegF,
4382 Op_RegF,
4383 Op_RegF,
4384 Op_RegF,
4385 Op_RegF,
4386 Op_RegF,
4387 Op_RegF,
4388 Op_RegF,
4389 Op_RegF,
4390 Op_RegF,
4391 Op_RegF,
4392 Op_RegF,
4393 Op_RegF,
4394 Op_RegF,
4395 Op_RegF,
4396 Op_RegF,
4397 Op_RegF,
4398 Op_RegF,
4399 Op_RegF,
4400 Op_RegF,
4401 Op_RegF,
4402 Op_RegF,
4403 Op_RegF,
4404 Op_RegF,
4405 Op_RegF,
4406 Op_RegF,
4407 Op_RegF,
4408 Op_RegF,
4409 Op_RegF,
4410 Op_RegF,
4411 Op_RegF,
4412 Op_RegF,
4413 Op_RegF,
4414 Op_RegF,
4415 Op_RegF,
4416 Op_RegF,
4417 Op_RegF,
4418 Op_RegF,
4419 Op_RegF,
4420 Op_RegF,
4421 Op_RegF,
4422 Op_RegF,
4423 Op_RegF,
4424 Op_RegF,
4425 Op_RegF,
4426 Op_RegF,
4427 Op_RegF,
4428 Op_RegF,
4429 Op_RegF,
4430 Op_RegF,
4431 Op_RegF,
4432 Op_RegF,
4433 Op_RegF,
4434 Op_RegF,
4435 Op_RegF,
4436 Op_RegF,
4437 Op_RegF,
4438 Op_RegF,
4439 Op_RegF,
4440 Op_RegF,
4441 Op_RegF,
4442 Op_RegF,
4443 Op_RegF,
4444 Op_RegF,
4445 Op_RegF,
4446 Op_RegF,
4447 Op_RegF,
4448 Op_RegF,
4449 Op_RegF,
4450 Op_RegF,
4451 Op_RegF,
4452 Op_RegF,
4453 Op_RegF,
4454 Op_RegF,
4455 Op_RegF,
4456 Op_RegF,
4457 Op_RegF,
4458 Op_RegF,
4459 Op_RegF,
4460 Op_RegF,
4461 Op_RegF,
4462 Op_RegF,
4463 Op_RegF,
4464 Op_RegF,
4465 Op_RegF,
4466 Op_RegF,
4467 Op_RegF,
4468 Op_RegF,
4469 Op_RegF,
4470 Op_RegF,
4471 Op_RegF,
4472 Op_RegF,
4473 Op_RegF,
4474 Op_RegF,
4475 Op_RegF,
4476 Op_RegF,
4477 Op_RegF,
4478 Op_RegF,
4479 Op_RegF,
4480 Op_RegF,
4481 Op_RegF,
4482 Op_RegF,
4483 Op_RegF,
4484 Op_RegF,
4485 Op_RegF,
4486 Op_RegF,
4487 Op_RegF,
4488 Op_RegF,
4489 Op_RegF,
4490 Op_RegF,
4491 Op_RegF,
4492 Op_RegF,
4493 Op_RegF,
4494 Op_RegF,
4495 Op_RegF,
4496 Op_RegF,
4497 Op_RegF,
4498 Op_RegF,
4499 Op_RegF,
4500 Op_RegF,
4501 Op_RegF,
4502 Op_RegF,
4503 Op_RegF,
4504 Op_RegF,
4505 Op_RegF,
4506 Op_RegF,
4507 Op_RegF,
4508 Op_RegF,
4509 Op_RegF,
4510 Op_RegF,
4511 Op_RegF,
4512 Op_RegF,
4513 Op_RegF,
4514 Op_RegF,
4515 Op_RegF,
4516 Op_RegF,
4517 Op_RegF,
4518 Op_RegF,
4519 Op_RegF,
4520 Op_RegF,
4521 Op_RegF,
4522 Op_RegF,
4523 Op_RegF,
4524 Op_RegF,
4525 Op_RegF,
4526 Op_RegF,
4527 Op_RegF,
4528 Op_RegF,
4529 Op_RegF,
4530 Op_RegF,
4531 Op_RegF,
4532 Op_RegF,
4533 Op_RegF,
4534 Op_RegF,
4535 Op_RegF,
4536 Op_RegF,
4537 Op_RegF,
4538 Op_RegF,
4539 Op_RegF,
4540 Op_RegF,
4541 Op_RegF,
4542 Op_RegF,
4543 Op_RegF,
4544 Op_RegF,
4545 Op_RegF,
4546 Op_RegF,
4547 Op_RegF,
4548 Op_RegF,
4549 Op_RegF,
4550 Op_RegF,
4551 Op_RegF,
4552 Op_RegF,
4553 Op_RegF,
4554 Op_RegF,
4555 Op_RegF,
4556 Op_RegF,
4557 Op_RegF,
4558 Op_RegF,
4559 Op_RegF,
4560 Op_RegF,
4561 Op_RegF,
4562 Op_RegF,
4563 Op_RegF,
4564 Op_RegF,
4565 Op_RegF,
4566 Op_RegF,
4567 Op_RegF,
4568 Op_RegF,
4569 Op_RegF,
4570 Op_RegF,
4571 Op_RegF,
4572 Op_RegF,
4573 Op_RegF,
4574 Op_RegF,
4575 Op_RegF,
4576 Op_RegF,
4577 Op_RegF,
4578 Op_RegF,
4579 Op_RegF,
4580 Op_RegF,
4581 Op_RegF,
4582 Op_RegF,
4583 Op_RegF,
4584 Op_RegF,
4585 Op_RegF,
4586 Op_RegF,
4587 Op_RegF,
4588 Op_RegF,
4589 Op_RegI,
4590 Op_RegI,
4591 Op_RegI,
4592 Op_RegI,
4593 Op_RegI,
4594 Op_RegI,
4595 Op_RegI,
4596 Op_RegI,
4597 Op_RegI,
4598 Op_RegI,
4599 Op_RegI,
4600 Op_RegI,
4601 Op_RegI,
4602 Op_RegI,
4603 0 // no trailing comma
4604};
4605
4606
4607const int reduceOp[] = {
4608 /* 0 */ 0,
4609 /* 1 */ 0,
4610 /* 2 */ 0,
4611 /* 3 */ 0,
4612 /* 4 */ 0,
4613 /* 5 */ 0,
4614 /* 6 */ 0,
4615 /* 7 */ 0,
4616 /* 8 */ immI_rule,
4617 /* 9 */ immI_0_rule,
4618 /* 10 */ immI_1_rule,
4619 /* 11 */ immI_M1_rule,
4620 /* 12 */ immI_2_rule,
4621 /* 13 */ immI_4_rule,
4622 /* 14 */ immI_8_rule,
4623 /* 15 */ immI2_rule,
4624 /* 16 */ immU7_rule,
4625 /* 17 */ immI8_rule,
4626 /* 18 */ immU8_rule,
4627 /* 19 */ immI16_rule,
4628 /* 20 */ immU31_rule,
4629 /* 21 */ immI_32_rule,
4630 /* 22 */ immI_64_rule,
4631 /* 23 */ immP_rule,
4632 /* 24 */ immP0_rule,
4633 /* 25 */ immN_rule,
4634 /* 26 */ immNKlass_rule,
4635 /* 27 */ immN0_rule,
4636 /* 28 */ immP31_rule,
4637 /* 29 */ immL_rule,
4638 /* 30 */ immL8_rule,
4639 /* 31 */ immUL32_rule,
4640 /* 32 */ immL32_rule,
4641 /* 33 */ immL_Pow2_rule,
4642 /* 34 */ immL_NotPow2_rule,
4643 /* 35 */ immL0_rule,
4644 /* 36 */ immL1_rule,
4645 /* 37 */ immL_M1_rule,
4646 /* 38 */ immL10_rule,
4647 /* 39 */ immL_127_rule,
4648 /* 40 */ immL_32bits_rule,
4649 /* 41 */ immI_Pow2M1_rule,
4650 /* 42 */ immF0_rule,
4651 /* 43 */ immF_rule,
4652 /* 44 */ immD0_rule,
4653 /* 45 */ immD_rule,
4654 /* 46 */ immI_16_rule,
4655 /* 47 */ immI_24_rule,
4656 /* 48 */ immI_255_rule,
4657 /* 49 */ immI_65535_rule,
4658 /* 50 */ immL_255_rule,
4659 /* 51 */ immL_65535_rule,
4660 /* 52 */ kReg_rule,
4661 /* 53 */ kReg_K1_rule,
4662 /* 54 */ kReg_K2_rule,
4663 /* 55 */ kReg_K3_rule,
4664 /* 56 */ kReg_K4_rule,
4665 /* 57 */ kReg_K5_rule,
4666 /* 58 */ kReg_K6_rule,
4667 /* 59 */ kReg_K7_rule,
4668 /* 60 */ rRegI_rule,
4669 /* 61 */ rax_RegI_rule,
4670 /* 62 */ rbx_RegI_rule,
4671 /* 63 */ rcx_RegI_rule,
4672 /* 64 */ rdx_RegI_rule,
4673 /* 65 */ rdi_RegI_rule,
4674 /* 66 */ no_rax_rdx_RegI_rule,
4675 /* 67 */ any_RegP_rule,
4676 /* 68 */ rRegP_rule,
4677 /* 69 */ rRegN_rule,
4678 /* 70 */ no_rax_RegP_rule,
4679 /* 71 */ no_rbp_RegP_rule,
4680 /* 72 */ no_rax_rbx_RegP_rule,
4681 /* 73 */ rax_RegP_rule,
4682 /* 74 */ rax_RegN_rule,
4683 /* 75 */ rbx_RegP_rule,
4684 /* 76 */ rsi_RegP_rule,
4685 /* 77 */ rbp_RegP_rule,
4686 /* 78 */ rdi_RegP_rule,
4687 /* 79 */ r15_RegP_rule,
4688 /* 80 */ rRegL_rule,
4689 /* 81 */ no_rax_rdx_RegL_rule,
4690 /* 82 */ no_rax_RegL_rule,
4691 /* 83 */ rax_RegL_rule,
4692 /* 84 */ rcx_RegL_rule,
4693 /* 85 */ rdx_RegL_rule,
4694 /* 86 */ rFlagsReg_rule,
4695 /* 87 */ rFlagsRegU_rule,
4696 /* 88 */ rFlagsRegUCF_rule,
4697 /* 89 */ regF_rule,
4698 /* 90 */ legRegF_rule,
4699 /* 91 */ vlRegF_rule,
4700 /* 92 */ regD_rule,
4701 /* 93 */ legRegD_rule,
4702 /* 94 */ vlRegD_rule,
4703 /* 95 */ indirect_rule,
4704 /* 96 */ indOffset8_rule,
4705 /* 97 */ indOffset32_rule,
4706 /* 98 */ indIndexOffset_rule,
4707 /* 99 */ indIndex_rule,
4708 /* 100 */ indIndexScale_rule,
4709 /* 101 */ indPosIndexScale_rule,
4710 /* 102 */ indIndexScaleOffset_rule,
4711 /* 103 */ indPosIndexOffset_rule,
4712 /* 104 */ indPosIndexScaleOffset_rule,
4713 /* 105 */ indCompressedOopOffset_rule,
4714 /* 106 */ indirectNarrow_rule,
4715 /* 107 */ indOffset8Narrow_rule,
4716 /* 108 */ indOffset32Narrow_rule,
4717 /* 109 */ indIndexOffsetNarrow_rule,
4718 /* 110 */ indIndexNarrow_rule,
4719 /* 111 */ indIndexScaleNarrow_rule,
4720 /* 112 */ indIndexScaleOffsetNarrow_rule,
4721 /* 113 */ indPosIndexOffsetNarrow_rule,
4722 /* 114 */ indPosIndexScaleOffsetNarrow_rule,
4723 /* 115 */ stackSlotP_rule,
4724 /* 116 */ stackSlotI_rule,
4725 /* 117 */ stackSlotF_rule,
4726 /* 118 */ stackSlotD_rule,
4727 /* 119 */ stackSlotL_rule,
4728 /* 120 */ cmpOp_rule,
4729 /* 121 */ cmpOpU_rule,
4730 /* 122 */ cmpOpUCF_rule,
4731 /* 123 */ cmpOpUCF2_rule,
4732 /* 124 */ rxmm0_rule,
4733 /* 125 */ vec_rule,
4734 /* 126 */ legVec_rule,
4735 /* 127 */ vecS_rule,
4736 /* 128 */ legVecS_rule,
4737 /* 129 */ vecD_rule,
4738 /* 130 */ legVecD_rule,
4739 /* 131 */ vecX_rule,
4740 /* 132 */ legVecX_rule,
4741 /* 133 */ vecY_rule,
4742 /* 134 */ legVecY_rule,
4743 /* 135 */ vecZ_rule,
4744 /* 136 */ legVecZ_rule,
4745 /* 137 */ cmpOp_vcmppd_rule,
4746 // last operand
4747 /* 138 */ memory_rule,
4748 // last operand class
4749 /* 139 */ _AddP_any_RegP_rRegL_rule,
4750 /* 140 */ _LShiftL_rRegL_immI2_rule,
4751 /* 141 */ _ConvI2L_rRegI__rule,
4752 /* 142 */ _LShiftL__ConvI2L_rRegI__immI2_rule,
4753 /* 143 */ _AddP_any_RegP__LShiftL_rRegL_immI2_rule,
4754 /* 144 */ _AddP_any_RegP__ConvI2L_rRegI__rule,
4755 /* 145 */ _AddP_any_RegP__LShiftL__ConvI2L_rRegI__immI2_rule,
4756 /* 146 */ _DecodeN_rRegN__rule,
4757 /* 147 */ _AddP__DecodeN_rRegN__rRegL_rule,
4758 /* 148 */ _AddP__DecodeN_rRegN___LShiftL_rRegL_immI2_rule,
4759 /* 149 */ _AddP__DecodeN_rRegN___ConvI2L_rRegI__rule,
4760 /* 150 */ _AddP__DecodeN_rRegN___LShiftL__ConvI2L_rRegI__immI2_rule,
4761 /* 151 */ _LoadB_memory__rule,
4762 /* 152 */ _LoadUB_memory__rule,
4763 /* 153 */ _AndI__LoadUB_memory__immI_rule,
4764 /* 154 */ _LoadS_memory__rule,
4765 /* 155 */ _LShiftI__LoadS_memory__immI_24_rule,
4766 /* 156 */ _LoadUS_memory__rule,
4767 /* 157 */ _LShiftI__LoadUS_memory__immI_24_rule,
4768 /* 158 */ _AndI__LoadUS_memory__immI_255_rule,
4769 /* 159 */ _AndI__LoadUS_memory__immI_rule,
4770 /* 160 */ _LoadI_memory__rule,
4771 /* 161 */ _LShiftI__LoadI_memory__immI_24_rule,
4772 /* 162 */ _LShiftI__LoadI_memory__immI_16_rule,
4773 /* 163 */ _AndI__LoadI_memory__immI_255_rule,
4774 /* 164 */ _AndI__LoadI_memory__immI_65535_rule,
4775 /* 165 */ _AndI__LoadI_memory__immU31_rule,
4776 /* 166 */ _ConvI2L__LoadI_memory___rule,
4777 /* 167 */ _LoadL_memory__rule,
4778 /* 168 */ _CastP2X_rRegP__rule,
4779 /* 169 */ _CastP2X__DecodeN_rRegN___rule,
4780 /* 170 */ _AddL__LShiftL_rRegL_immI2_immL32_rule,
4781 /* 171 */ _Binary_cmpOp_rFlagsReg_rule,
4782 /* 172 */ _Binary_rRegI_rRegI_rule,
4783 /* 173 */ _Binary_cmpOpU_rFlagsRegU_rule,
4784 /* 174 */ _Binary_cmpOpUCF_rFlagsRegUCF_rule,
4785 /* 175 */ _Binary_rRegI__LoadI_memory__rule,
4786 /* 176 */ _Binary_rRegN_rRegN_rule,
4787 /* 177 */ _Binary_rRegP_rRegP_rule,
4788 /* 178 */ _Binary_rRegL_rRegL_rule,
4789 /* 179 */ _Binary_rRegL__LoadL_memory__rule,
4790 /* 180 */ _Binary_regF_regF_rule,
4791 /* 181 */ _Binary_regD_regD_rule,
4792 /* 182 */ _AddI__LoadI_memory__rRegI_rule,
4793 /* 183 */ _AddI_rRegI__LoadI_memory__rule,
4794 /* 184 */ _AddI__LoadI_memory__immI_rule,
4795 /* 185 */ _AddI__LoadI_memory__immI_1_rule,
4796 /* 186 */ _AddI__LoadI_memory__immI_M1_rule,
4797 /* 187 */ _AddL__LoadL_memory__rRegL_rule,
4798 /* 188 */ _AddL_rRegL__LoadL_memory__rule,
4799 /* 189 */ _AddL__LoadL_memory__immL32_rule,
4800 /* 190 */ _AddL__LoadL_memory__immL1_rule,
4801 /* 191 */ _AddL__LoadL_memory__immL_M1_rule,
4802 /* 192 */ _Binary_rax_RegP_rRegP_rule,
4803 /* 193 */ _Binary_rax_RegI_rRegI_rule,
4804 /* 194 */ _Binary_rax_RegL_rRegL_rule,
4805 /* 195 */ _Binary_rax_RegN_rRegN_rule,
4806 /* 196 */ _SubI__LoadI_memory__rRegI_rule,
4807 /* 197 */ _SubI__LoadI_memory__immI_rule,
4808 /* 198 */ _SubL__LoadL_memory__rRegL_rule,
4809 /* 199 */ _SubL__LoadL_memory__immL32_rule,
4810 /* 200 */ _SubI_immI_0_rRegI_rule,
4811 /* 201 */ _SubI_immI_0__LoadI_memory__rule,
4812 /* 202 */ _SubL_immL0__LoadL_memory__rule,
4813 /* 203 */ _LShiftI__LoadI_memory__immI_1_rule,
4814 /* 204 */ _LShiftI__LoadI_memory__immI8_rule,
4815 /* 205 */ _LShiftI__LoadI_memory__rcx_RegI_rule,
4816 /* 206 */ _RShiftI__LoadI_memory__immI_1_rule,
4817 /* 207 */ _RShiftI__LoadI_memory__immI8_rule,
4818 /* 208 */ _RShiftI__LoadI_memory__rcx_RegI_rule,
4819 /* 209 */ _URShiftI__LoadI_memory__immI_1_rule,
4820 /* 210 */ _URShiftI__LoadI_memory__immI8_rule,
4821 /* 211 */ _URShiftI__LoadI_memory__rcx_RegI_rule,
4822 /* 212 */ _LShiftL__LoadL_memory__immI_1_rule,
4823 /* 213 */ _LShiftL__LoadL_memory__immI8_rule,
4824 /* 214 */ _LShiftL__LoadL_memory__rcx_RegI_rule,
4825 /* 215 */ _RShiftL__LoadL_memory__immI_1_rule,
4826 /* 216 */ _RShiftL__LoadL_memory__immI8_rule,
4827 /* 217 */ _RShiftL__LoadL_memory__rcx_RegI_rule,
4828 /* 218 */ _URShiftL__LoadL_memory__immI_1_rule,
4829 /* 219 */ _URShiftL__LoadL_memory__immI8_rule,
4830 /* 220 */ _URShiftL__LoadL_memory__rcx_RegI_rule,
4831 /* 221 */ _LShiftI_rRegI_immI_24_rule,
4832 /* 222 */ _LShiftI_rRegI_immI_16_rule,
4833 /* 223 */ _AndI_rRegI_immI_255_rule,
4834 /* 224 */ _AndI_rRegI_immI_65535_rule,
4835 /* 225 */ _AndI_rRegI_immI_Pow2M1_rule,
4836 /* 226 */ _AndI__LoadB_memory__rRegI_rule,
4837 /* 227 */ _AndI_rRegI__LoadB_memory__rule,
4838 /* 228 */ _AndI__LoadI_memory__rRegI_rule,
4839 /* 229 */ _AndI_rRegI__LoadI_memory__rule,
4840 /* 230 */ _AndI__LoadI_memory__immI_rule,
4841 /* 231 */ _XorI_rRegI_immI_M1_rule,
4842 /* 232 */ _AddI_rRegI_immI_M1_rule,
4843 /* 233 */ _OrI__LoadB_memory__rRegI_rule,
4844 /* 234 */ _OrI_rRegI__LoadB_memory__rule,
4845 /* 235 */ _OrI__LoadI_memory__rRegI_rule,
4846 /* 236 */ _OrI_rRegI__LoadI_memory__rule,
4847 /* 237 */ _OrI__LoadI_memory__immI_rule,
4848 /* 238 */ _XorI__LoadB_memory__rRegI_rule,
4849 /* 239 */ _XorI_rRegI__LoadB_memory__rule,
4850 /* 240 */ _XorI__LoadI_memory__rRegI_rule,
4851 /* 241 */ _XorI_rRegI__LoadI_memory__rule,
4852 /* 242 */ _XorI__LoadI_memory__immI_rule,
4853 /* 243 */ _AndL__LoadL_memory__rRegL_rule,
4854 /* 244 */ _AndL_rRegL__LoadL_memory__rule,
4855 /* 245 */ _AndL__LoadL_memory__immL32_rule,
4856 /* 246 */ _AndL__LoadL_memory__immL_NotPow2_rule,
4857 /* 247 */ _XorL_rRegL_immL_M1_rule,
4858 /* 248 */ _SubL_immL0_rRegL_rule,
4859 /* 249 */ _AddL_rRegL_immL_M1_rule,
4860 /* 250 */ _CastP2X_any_RegP__rule,
4861 /* 251 */ _OrL__LoadL_memory__rRegL_rule,
4862 /* 252 */ _OrL_rRegL__LoadL_memory__rule,
4863 /* 253 */ _OrL__LoadL_memory__immL32_rule,
4864 /* 254 */ _OrL__LoadL_memory__immL_Pow2_rule,
4865 /* 255 */ _XorL__LoadL_memory__rRegL_rule,
4866 /* 256 */ _XorL_rRegL__LoadL_memory__rule,
4867 /* 257 */ _XorL__LoadL_memory__immL32_rule,
4868 /* 258 */ _CmpLTMask_rRegI_rRegI_rule,
4869 /* 259 */ _AndI__CmpLTMask_rRegI_rRegI_rRegI_rule,
4870 /* 260 */ _SubI_rRegI_rRegI_rule,
4871 /* 261 */ _AndI_rRegI__CmpLTMask_rRegI_rRegI_rule,
4872 /* 262 */ _LoadF_memory__rule,
4873 /* 263 */ _LoadD_memory__rule,
4874 /* 264 */ _Binary_rdi_RegP_rcx_RegI_rule,
4875 /* 265 */ _Binary_rsi_RegP_rdx_RegI_rule,
4876 /* 266 */ _Binary_rdi_RegP_rdx_RegI_rule,
4877 /* 267 */ _Binary_rsi_RegP_immI_rule,
4878 /* 268 */ _Binary_rsi_RegP_rax_RegI_rule,
4879 /* 269 */ _Binary_rdi_RegP_rsi_RegP_rule,
4880 /* 270 */ _AndI_rRegI_immI_rule,
4881 /* 271 */ _LoadP_memory__rule,
4882 /* 272 */ _LoadN_memory__rule,
4883 /* 273 */ _LoadNKlass_memory__rule,
4884 /* 274 */ _AndL_rRegL_immL32_rule,
4885 /* 275 */ _AndL__CastP2X_rRegP___LoadL_memory__rule,
4886 /* 276 */ _AndL__LoadL_memory___CastP2X_rRegP__rule,
4887 /* 277 */ _AndI__LoadUB_memory__immU7_rule,
4888 /* 278 */ _AndI__LoadB_memory__immI8_rule,
4889 /* 279 */ _PartialSubtypeCheck_rsi_RegP_rax_RegP_rule,
4890 /* 280 */ _LoadVector_memory__rule,
4891 /* 281 */ _Binary_vec_kReg_rule,
4892 /* 282 */ _Binary_vec_vec_rule,
4893 /* 283 */ _Binary_vec__Binary_vec_kReg_rule,
4894 /* 284 */ _Binary_vec_rRegI_rule,
4895 /* 285 */ _Binary_vec_rRegL_rule,
4896 /* 286 */ _Binary_vec_regF_rule,
4897 /* 287 */ _Binary_vec_regD_rule,
4898 /* 288 */ _Binary_cmpOp_vcmppd_immI8_rule,
4899 /* 289 */ _Binary_legVec_legVec_rule,
4900 /* 290 */ _Binary_regD_immD_rule,
4901 /* 291 */ _LShiftCntV_immI8__rule,
4902 /* 292 */ _RShiftCntV_immI8__rule,
4903 /* 293 */ _VectorTest_legVec_legVec_rule,
4904 /* 294 */ _VectorTest_kReg_kReg_rule,
4905 /* 295 */ _Binary_vec__LoadVector_memory__rule,
4906 /* 296 */ _MulAddVS2VI_vec_vec_rule,
4907 /* 297 */ _Binary_vec_immU8_rule,
4908 /* 298 */ _Binary__LoadVector_memory__immU8_rule,
4909 /* 299 */ _VectorStoreMask_vec_immI_rule,
4910 /* 300 */ _Binary_vec_immI8_rule,
4911 /* 301 */ _Binary_vec__LShiftCntV_immI8__rule,
4912 /* 302 */ _Binary_vec__RShiftCntV_immI8__rule,
4913 /* 303 */ _Binary__LoadVector_memory__kReg_rule,
4914 /* 304 */ _Binary_immI8_kReg_rule,
4915 /* 305 */ _MaskAll_immI_M1__rule,
4916 // last internally defined operand
4917 /* 306 */ stackSlotI_rule,
4918 /* 307 */ stackSlotL_rule,
4919 /* 308 */ stackSlotP_rule,
4920 /* 309 */ stackSlotF_rule,
4921 /* 310 */ stackSlotD_rule,
4922 /* 311 */ vlRegF_rule,
4923 /* 312 */ legRegF_rule,
4924 /* 313 */ regF_rule,
4925 /* 314 */ regF_rule,
4926 /* 315 */ vlRegD_rule,
4927 /* 316 */ legRegD_rule,
4928 /* 317 */ regD_rule,
4929 /* 318 */ regD_rule,
4930 /* 319 */ rRegP_rule,
4931 /* 320 */ rRegP_rule,
4932 /* 321 */ rRegP_rule,
4933 /* 322 */ rRegP_rule,
4934 /* 323 */ rRegP_rule,
4935 /* 324 */ rRegP_rule,
4936 /* 325 */ rRegP_rule,
4937 /* 326 */ rRegP_rule,
4938 /* 327 */ rRegP_rule,
4939 /* 328 */ rRegP_rule,
4940 /* 329 */ rRegP_rule,
4941 /* 330 */ rRegP_rule,
4942 /* 331 */ rRegP_rule,
4943 /* 332 */ rRegP_rule,
4944 /* 333 */ rRegP_rule,
4945 /* 334 */ rRegP_rule,
4946 /* 335 */ rRegI_rule,
4947 /* 336 */ rRegI_rule,
4948 /* 337 */ rRegL_rule,
4949 /* 338 */ rRegL_rule,
4950 /* 339 */ rRegL_rule,
4951 /* 340 */ rRegL_rule,
4952 /* 341 */ rRegP_rule,
4953 /* 342 */ rRegP_rule,
4954 /* 343 */ rRegP_rule,
4955 /* 344 */ regF_rule,
4956 /* 345 */ rRegN_rule,
4957 /* 346 */ rRegN_rule,
4958 /* 347 */ rRegN_rule,
4959 /* 348 */ regF_rule,
4960 /* 349 */ regD_rule,
4961 /* 350 */ regD_rule,
4962 /* 351 */ rRegI_rule,
4963 /* 352 */ rRegL_rule,
4964 /* 353 */ rRegP_rule,
4965 /* 354 */ regF_rule,
4966 /* 355 */ regD_rule,
4967 /* 356 */ legVec_rule,
4968 /* 357 */ vec_rule,
4969 /* 358 */ Universe_rule,
4970 /* 359 */ rRegP_rule,
4971 /* 360 */ rRegL_rule,
4972 /* 361 */ rRegP_rule,
4973 /* 362 */ rRegP_rule,
4974 /* 363 */ rRegI_rule,
4975 /* 364 */ rRegL_rule,
4976 /* 365 */ regF_rule,
4977 /* 366 */ regD_rule,
4978 /* 367 */ rFlagsReg_rule,
4979 /* 368 */ rFlagsReg_rule,
4980 /* 369 */ rFlagsReg_rule,
4981 /* 370 */ rFlagsRegU_rule,
4982 /* 371 */ rFlagsRegUCF_rule,
4983 /* 372 */ rFlagsRegU_rule,
4984 /* 373 */ rFlagsRegUCF_rule,
4985 /* 374 */ rFlagsRegU_rule,
4986 /* 375 */ rFlagsRegUCF_rule,
4987 /* 376 */ rFlagsRegU_rule,
4988 /* 377 */ rFlagsRegUCF_rule,
4989 /* 378 */ rFlagsRegU_rule,
4990 /* 379 */ rFlagsRegUCF_rule,
4991 /* 380 */ rFlagsRegU_rule,
4992 /* 381 */ rFlagsRegUCF_rule,
4993 /* 382 */ rRegI_rule,
4994 /* 383 */ regF_rule,
4995 /* 384 */ rRegL_rule,
4996 /* 385 */ regD_rule,
4997 /* 386 */ regD_rule,
4998 /* 387 */ rRegI_rule,
4999 /* 388 */ rRegL_rule,
5000 /* 389 */ regF_rule,
5001 /* 390 */ regD_rule,
5002 /* 391 */ rFlagsReg_rule,
5003 /* 392 */ rFlagsReg_rule,
5004 /* 393 */ rFlagsReg_rule,
5005 /* 394 */ rFlagsReg_rule,
5006 /* 395 */ rFlagsReg_rule,
5007 /* 396 */ rFlagsReg_rule,
5008 /* 397 */ rFlagsReg_rule,
5009 /* 398 */ rFlagsReg_rule,
5010 /* 399 */ rFlagsReg_rule,
5011 /* 400 */ rFlagsReg_rule,
5012 /* 401 */ rFlagsReg_rule,
5013 /* 402 */ rFlagsReg_rule,
5014 /* 403 */ rFlagsReg_rule,
5015 /* 404 */ rFlagsReg_rule,
5016 /* 405 */ rFlagsReg_rule,
5017 /* 406 */ rFlagsReg_rule,
5018 /* 407 */ rFlagsReg_rule,
5019 /* 408 */ rFlagsReg_rule,
5020 /* 409 */ rFlagsReg_rule,
5021 /* 410 */ rFlagsReg_rule,
5022 /* 411 */ rFlagsReg_rule,
5023 /* 412 */ rFlagsRegU_rule,
5024 /* 413 */ rFlagsRegU_rule,
5025 /* 414 */ rFlagsRegU_rule,
5026 /* 415 */ rFlagsRegU_rule,
5027 /* 416 */ rFlagsRegU_rule,
5028 /* 417 */ rFlagsRegU_rule,
5029 /* 418 */ rFlagsRegU_rule,
5030 /* 419 */ rFlagsReg_rule,
5031 /* 420 */ rFlagsReg_rule,
5032 /* 421 */ rFlagsReg_rule,
5033 /* 422 */ rFlagsRegU_rule,
5034 /* 423 */ rFlagsRegU_rule,
5035 /* 424 */ rFlagsRegU_rule,
5036 /* 425 */ rFlagsRegU_rule,
5037 /* 426 */ rFlagsRegU_rule,
5038 /* 427 */ rFlagsRegU_rule,
5039 /* 428 */ rFlagsReg_rule,
5040 /* 429 */ rFlagsReg_rule,
5041 /* 430 */ rFlagsReg_rule,
5042 /* 431 */ rFlagsReg_rule,
5043 /* 432 */ rFlagsReg_rule,
5044 /* 433 */ rFlagsReg_rule,
5045 /* 434 */ rFlagsReg_rule,
5046 /* 435 */ rFlagsReg_rule,
5047 /* 436 */ rFlagsReg_rule,
5048 /* 437 */ rFlagsReg_rule,
5049 /* 438 */ rFlagsReg_rule,
5050 /* 439 */ rFlagsReg_rule,
5051 /* 440 */ rFlagsRegU_rule,
5052 /* 441 */ rFlagsRegU_rule,
5053 /* 442 */ rFlagsRegU_rule,
5054 /* 443 */ rFlagsRegU_rule,
5055 /* 444 */ rFlagsReg_rule,
5056 /* 445 */ rFlagsReg_rule,
5057 /* 446 */ rFlagsReg_rule,
5058 /* 447 */ rFlagsReg_rule,
5059 /* 448 */ rFlagsReg_rule,
5060 /* 449 */ rFlagsReg_rule,
5061 /* 450 */ rFlagsReg_rule,
5062 /* 451 */ r15_RegP_rule,
5063 /* 452 */ regF_rule,
5064 /* 453 */ vlRegF_rule,
5065 /* 454 */ regD_rule,
5066 /* 455 */ vlRegD_rule,
5067 /* 456 */ regF_rule,
5068 /* 457 */ vlRegF_rule,
5069 /* 458 */ regD_rule,
5070 /* 459 */ vlRegD_rule,
5071 /* 460 */ kReg_rule,
5072 /* 461 */ vec_rule,
5073 /* 462 */ legVec_rule,
5074 /* 463 */ vec_rule,
5075 /* 464 */ vec_rule,
5076 /* 465 */ vec_rule,
5077 /* 466 */ vec_rule,
5078 /* 467 */ vec_rule,
5079 /* 468 */ vec_rule,
5080 /* 469 */ vec_rule,
5081 /* 470 */ vec_rule,
5082 /* 471 */ vec_rule,
5083 /* 472 */ vec_rule,
5084 /* 473 */ vec_rule,
5085 /* 474 */ vec_rule,
5086 /* 475 */ vec_rule,
5087 /* 476 */ vec_rule,
5088 /* 477 */ vec_rule,
5089 /* 478 */ vec_rule,
5090 /* 479 */ vec_rule,
5091 /* 480 */ rFlagsReg_rule,
5092 /* 481 */ rFlagsReg_rule,
5093 /* 482 */ rFlagsReg_rule,
5094 /* 483 */ kReg_rule,
5095 /* 484 */ vec_rule,
5096 /* 485 */ vec_rule,
5097 /* 486 */ vec_rule,
5098 /* 487 */ vec_rule,
5099 /* 488 */ vec_rule,
5100 /* 489 */ vec_rule,
5101 /* 490 */ kReg_rule,
5102 /* 491 */ kReg_rule,
5103 /* 492 */ vec_rule,
5104 /* 493 */ legVec_rule,
5105 /* 494 */ rRegI_rule,
5106 /* 495 */ rRegL_rule,
5107 /* 496 */ rRegI_rule,
5108 /* 497 */ rRegL_rule,
5109 /* 498 */ rRegL_rule,
5110 /* 499 */ rRegI_rule,
5111 /* 500 */ rRegI_rule,
5112 /* 501 */ rRegL_rule,
5113 /* 502 */ rRegI_rule,
5114 /* 503 */ rRegI_rule,
5115 /* 504 */ rRegL_rule,
5116 /* 505 */ rRegL_rule,
5117 /* 506 */ rRegL_rule,
5118 /* 507 */ rRegI_rule,
5119 /* 508 */ rRegI_rule,
5120 /* 509 */ rRegI_rule,
5121 /* 510 */ rRegI_rule,
5122 /* 511 */ rRegI_rule,
5123 /* 512 */ rRegL_rule,
5124 /* 513 */ rRegL_rule,
5125 /* 514 */ rRegL_rule,
5126 /* 515 */ rRegL_rule,
5127 /* 516 */ rRegL_rule,
5128 /* 517 */ rRegL_rule,
5129 /* 518 */ rRegI_rule,
5130 /* 519 */ rRegP_rule,
5131 /* 520 */ rRegN_rule,
5132 /* 521 */ rRegP_rule,
5133 /* 522 */ rRegN_rule,
5134 /* 523 */ regF_rule,
5135 /* 524 */ regD_rule,
5136 /* 525 */ regD_rule,
5137 /* 526 */ legRegF_rule,
5138 /* 527 */ legRegF_rule,
5139 /* 528 */ legRegD_rule,
5140 /* 529 */ legRegD_rule,
5141 /* 530 */ legRegF_rule,
5142 /* 531 */ legRegF_rule,
5143 /* 532 */ legRegD_rule,
5144 /* 533 */ legRegD_rule,
5145 /* 534 */ Universe_rule,
5146 /* 535 */ Universe_rule,
5147 /* 536 */ Universe_rule,
5148 /* 537 */ Universe_rule,
5149 /* 538 */ Universe_rule,
5150 /* 539 */ Universe_rule,
5151 /* 540 */ Universe_rule,
5152 /* 541 */ Universe_rule,
5153 /* 542 */ Universe_rule,
5154 /* 543 */ Universe_rule,
5155 /* 544 */ Universe_rule,
5156 /* 545 */ Universe_rule,
5157 /* 546 */ Universe_rule,
5158 /* 547 */ Universe_rule,
5159 /* 548 */ Universe_rule,
5160 /* 549 */ Universe_rule,
5161 /* 550 */ Universe_rule,
5162 /* 551 */ Universe_rule,
5163 /* 552 */ Universe_rule,
5164 /* 553 */ Universe_rule,
5165 /* 554 */ Universe_rule,
5166 /* 555 */ Universe_rule,
5167 /* 556 */ Universe_rule,
5168 /* 557 */ Universe_rule,
5169 /* 558 */ Universe_rule,
5170 /* 559 */ Universe_rule,
5171 /* 560 */ Universe_rule,
5172 /* 561 */ Universe_rule,
5173 /* 562 */ Universe_rule,
5174 /* 563 */ Universe_rule,
5175 /* 564 */ Universe_rule,
5176 /* 565 */ Universe_rule,
5177 /* 566 */ Universe_rule,
5178 /* 567 */ Universe_rule,
5179 /* 568 */ Universe_rule,
5180 /* 569 */ rRegI_rule,
5181 /* 570 */ rRegL_rule,
5182 /* 571 */ rRegI_rule,
5183 /* 572 */ rRegI_rule,
5184 /* 573 */ rRegI_rule,
5185 /* 574 */ rRegI_rule,
5186 /* 575 */ rRegI_rule,
5187 /* 576 */ rRegI_rule,
5188 /* 577 */ rRegI_rule,
5189 /* 578 */ rRegI_rule,
5190 /* 579 */ rRegI_rule,
5191 /* 580 */ rRegI_rule,
5192 /* 581 */ rRegI_rule,
5193 /* 582 */ rRegI_rule,
5194 /* 583 */ rRegI_rule,
5195 /* 584 */ rRegI_rule,
5196 /* 585 */ Universe_rule,
5197 /* 586 */ Universe_rule,
5198 /* 587 */ Universe_rule,
5199 /* 588 */ Universe_rule,
5200 /* 589 */ Universe_rule,
5201 /* 590 */ Universe_rule,
5202 /* 591 */ Universe_rule,
5203 /* 592 */ Universe_rule,
5204 /* 593 */ Universe_rule,
5205 /* 594 */ rRegI_rule,
5206 /* 595 */ rRegI_rule,
5207 /* 596 */ rRegN_rule,
5208 /* 597 */ rRegN_rule,
5209 /* 598 */ rRegP_rule,
5210 /* 599 */ rRegP_rule,
5211 /* 600 */ rRegN_rule,
5212 /* 601 */ rRegP_rule,
5213 /* 602 */ Universe_rule,
5214 /* 603 */ Universe_rule,
5215 /* 604 */ Universe_rule,
5216 /* 605 */ rRegI_rule,
5217 /* 606 */ rRegI_rule,
5218 /* 607 */ rRegI_rule,
5219 /* 608 */ rRegI_rule,
5220 /* 609 */ rRegI_rule,
5221 /* 610 */ rRegI_rule,
5222 /* 611 */ rRegN_rule,
5223 /* 612 */ rRegN_rule,
5224 /* 613 */ rRegN_rule,
5225 /* 614 */ rRegP_rule,
5226 /* 615 */ rRegP_rule,
5227 /* 616 */ rRegP_rule,
5228 /* 617 */ rRegL_rule,
5229 /* 618 */ rRegL_rule,
5230 /* 619 */ rRegL_rule,
5231 /* 620 */ rRegL_rule,
5232 /* 621 */ rRegL_rule,
5233 /* 622 */ rRegL_rule,
5234 /* 623 */ regF_rule,
5235 /* 624 */ regF_rule,
5236 /* 625 */ regF_rule,
5237 /* 626 */ regD_rule,
5238 /* 627 */ regD_rule,
5239 /* 628 */ regD_rule,
5240 /* 629 */ rRegI_rule,
5241 /* 630 */ rRegI_rule,
5242 /* 631 */ rRegI_rule,
5243 /* 632 */ rRegI_rule,
5244 /* 633 */ Universe_rule,
5245 /* 634 */ Universe_rule,
5246 /* 635 */ Universe_rule,
5247 /* 636 */ rRegI_rule,
5248 /* 637 */ Universe_rule,
5249 /* 638 */ rRegI_rule,
5250 /* 639 */ Universe_rule,
5251 /* 640 */ rRegI_rule,
5252 /* 641 */ rRegL_rule,
5253 /* 642 */ rRegL_rule,
5254 /* 643 */ rRegL_rule,
5255 /* 644 */ rRegL_rule,
5256 /* 645 */ Universe_rule,
5257 /* 646 */ Universe_rule,
5258 /* 647 */ Universe_rule,
5259 /* 648 */ rRegI_rule,
5260 /* 649 */ Universe_rule,
5261 /* 650 */ rRegL_rule,
5262 /* 651 */ Universe_rule,
5263 /* 652 */ rRegL_rule,
5264 /* 653 */ rRegP_rule,
5265 /* 654 */ rRegP_rule,
5266 /* 655 */ rRegP_rule,
5267 /* 656 */ rRegP_rule,
5268 /* 657 */ rRegI_rule,
5269 /* 658 */ rRegI_rule,
5270 /* 659 */ rRegI_rule,
5271 /* 660 */ rRegI_rule,
5272 /* 661 */ rRegI_rule,
5273 /* 662 */ rRegI_rule,
5274 /* 663 */ rRegI_rule,
5275 /* 664 */ rRegI_rule,
5276 /* 665 */ rRegI_rule,
5277 /* 666 */ rRegI_rule,
5278 /* 667 */ rRegI_rule,
5279 /* 668 */ rRegI_rule,
5280 /* 669 */ rax_RegI_rule,
5281 /* 670 */ rax_RegI_rule,
5282 /* 671 */ rax_RegI_rule,
5283 /* 672 */ rax_RegL_rule,
5284 /* 673 */ rax_RegN_rule,
5285 /* 674 */ rax_RegP_rule,
5286 /* 675 */ Universe_rule,
5287 /* 676 */ rRegI_rule,
5288 /* 677 */ Universe_rule,
5289 /* 678 */ rRegI_rule,
5290 /* 679 */ Universe_rule,
5291 /* 680 */ rRegI_rule,
5292 /* 681 */ Universe_rule,
5293 /* 682 */ rRegL_rule,
5294 /* 683 */ rRegI_rule,
5295 /* 684 */ rRegI_rule,
5296 /* 685 */ rRegI_rule,
5297 /* 686 */ rRegL_rule,
5298 /* 687 */ rRegP_rule,
5299 /* 688 */ rRegN_rule,
5300 /* 689 */ rRegI_rule,
5301 /* 690 */ rRegL_rule,
5302 /* 691 */ rRegI_rule,
5303 /* 692 */ rRegI_rule,
5304 /* 693 */ rRegI_rule,
5305 /* 694 */ Universe_rule,
5306 /* 695 */ Universe_rule,
5307 /* 696 */ rRegL_rule,
5308 /* 697 */ rRegI_rule,
5309 /* 698 */ rRegL_rule,
5310 /* 699 */ Universe_rule,
5311 /* 700 */ Universe_rule,
5312 /* 701 */ rRegP_rule,
5313 /* 702 */ rRegI_rule,
5314 /* 703 */ rRegI_rule,
5315 /* 704 */ Universe_rule,
5316 /* 705 */ rRegL_rule,
5317 /* 706 */ rRegL_rule,
5318 /* 707 */ Universe_rule,
5319 /* 708 */ rRegI_rule,
5320 /* 709 */ rRegI_rule,
5321 /* 710 */ rRegI_rule,
5322 /* 711 */ rRegI_rule,
5323 /* 712 */ rRegI_rule,
5324 /* 713 */ rRegI_rule,
5325 /* 714 */ rRegL_rule,
5326 /* 715 */ rRegL_rule,
5327 /* 716 */ rRegL_rule,
5328 /* 717 */ rRegL_rule,
5329 /* 718 */ rRegL_rule,
5330 /* 719 */ rdx_RegL_rule,
5331 /* 720 */ rdx_RegL_rule,
5332 /* 721 */ rax_RegI_rule,
5333 /* 722 */ rax_RegL_rule,
5334 /* 723 */ Universe_rule,
5335 /* 724 */ Universe_rule,
5336 /* 725 */ 0,
5337 /* 726 */ 0,
5338 /* 727 */ 0,
5339 /* 728 */ 0,
5340 /* 729 */ rdx_RegL_rule,
5341 /* 730 */ rdx_RegI_rule,
5342 /* 731 */ rdx_RegL_rule,
5343 /* 732 */ rRegI_rule,
5344 /* 733 */ Universe_rule,
5345 /* 734 */ rRegI_rule,
5346 /* 735 */ Universe_rule,
5347 /* 736 */ rRegI_rule,
5348 /* 737 */ Universe_rule,
5349 /* 738 */ rRegI_rule,
5350 /* 739 */ Universe_rule,
5351 /* 740 */ rRegI_rule,
5352 /* 741 */ Universe_rule,
5353 /* 742 */ rRegI_rule,
5354 /* 743 */ Universe_rule,
5355 /* 744 */ rRegI_rule,
5356 /* 745 */ Universe_rule,
5357 /* 746 */ rRegI_rule,
5358 /* 747 */ Universe_rule,
5359 /* 748 */ rRegI_rule,
5360 /* 749 */ Universe_rule,
5361 /* 750 */ rRegL_rule,
5362 /* 751 */ Universe_rule,
5363 /* 752 */ rRegL_rule,
5364 /* 753 */ Universe_rule,
5365 /* 754 */ rRegL_rule,
5366 /* 755 */ Universe_rule,
5367 /* 756 */ rRegL_rule,
5368 /* 757 */ Universe_rule,
5369 /* 758 */ rRegL_rule,
5370 /* 759 */ Universe_rule,
5371 /* 760 */ rRegL_rule,
5372 /* 761 */ Universe_rule,
5373 /* 762 */ rRegL_rule,
5374 /* 763 */ Universe_rule,
5375 /* 764 */ rRegL_rule,
5376 /* 765 */ Universe_rule,
5377 /* 766 */ rRegL_rule,
5378 /* 767 */ Universe_rule,
5379 /* 768 */ rRegI_rule,
5380 /* 769 */ rRegI_rule,
5381 /* 770 */ rRegI_rule,
5382 /* 771 */ rRegI_rule,
5383 /* 772 */ rRegI_rule,
5384 /* 773 */ rRegI_rule,
5385 /* 774 */ rRegI_rule,
5386 /* 775 */ rRegL_rule,
5387 /* 776 */ rRegL_rule,
5388 /* 777 */ rRegL_rule,
5389 /* 778 */ rRegL_rule,
5390 /* 779 */ rRegL_rule,
5391 /* 780 */ rRegI_rule,
5392 /* 781 */ rRegI_rule,
5393 /* 782 */ rRegL_rule,
5394 /* 783 */ rRegI_rule,
5395 /* 784 */ rRegL_rule,
5396 /* 785 */ rRegL_rule,
5397 /* 786 */ rRegI_rule,
5398 /* 787 */ rRegI_rule,
5399 /* 788 */ rRegI_rule,
5400 /* 789 */ Universe_rule,
5401 /* 790 */ Universe_rule,
5402 /* 791 */ Universe_rule,
5403 /* 792 */ Universe_rule,
5404 /* 793 */ Universe_rule,
5405 /* 794 */ rRegI_rule,
5406 /* 795 */ rRegI_rule,
5407 /* 796 */ rRegI_rule,
5408 /* 797 */ rRegI_rule,
5409 /* 798 */ rRegI_rule,
5410 /* 799 */ rRegI_rule,
5411 /* 800 */ rRegI_rule,
5412 /* 801 */ rRegI_rule,
5413 /* 802 */ rRegI_rule,
5414 /* 803 */ rRegI_rule,
5415 /* 804 */ rRegI_rule,
5416 /* 805 */ rRegI_rule,
5417 /* 806 */ rRegI_rule,
5418 /* 807 */ rRegI_rule,
5419 /* 808 */ rRegI_rule,
5420 /* 809 */ rRegI_rule,
5421 /* 810 */ rRegI_rule,
5422 /* 811 */ rRegI_rule,
5423 /* 812 */ rRegI_rule,
5424 /* 813 */ rRegI_rule,
5425 /* 814 */ Universe_rule,
5426 /* 815 */ Universe_rule,
5427 /* 816 */ Universe_rule,
5428 /* 817 */ Universe_rule,
5429 /* 818 */ Universe_rule,
5430 /* 819 */ rRegI_rule,
5431 /* 820 */ rRegI_rule,
5432 /* 821 */ rRegI_rule,
5433 /* 822 */ rRegI_rule,
5434 /* 823 */ rRegI_rule,
5435 /* 824 */ Universe_rule,
5436 /* 825 */ Universe_rule,
5437 /* 826 */ Universe_rule,
5438 /* 827 */ Universe_rule,
5439 /* 828 */ Universe_rule,
5440 /* 829 */ rRegL_rule,
5441 /* 830 */ rRegL_rule,
5442 /* 831 */ rRegL_rule,
5443 /* 832 */ rRegL_rule,
5444 /* 833 */ rRegL_rule,
5445 /* 834 */ rRegL_rule,
5446 /* 835 */ Universe_rule,
5447 /* 836 */ Universe_rule,
5448 /* 837 */ Universe_rule,
5449 /* 838 */ Universe_rule,
5450 /* 839 */ rRegL_rule,
5451 /* 840 */ rRegL_rule,
5452 /* 841 */ rRegL_rule,
5453 /* 842 */ rRegL_rule,
5454 /* 843 */ rRegL_rule,
5455 /* 844 */ rRegL_rule,
5456 /* 845 */ rRegL_rule,
5457 /* 846 */ rRegL_rule,
5458 /* 847 */ rRegL_rule,
5459 /* 848 */ rRegL_rule,
5460 /* 849 */ rRegL_rule,
5461 /* 850 */ rRegL_rule,
5462 /* 851 */ rRegL_rule,
5463 /* 852 */ rRegL_rule,
5464 /* 853 */ rRegL_rule,
5465 /* 854 */ rRegL_rule,
5466 /* 855 */ rRegL_rule,
5467 /* 856 */ rRegL_rule,
5468 /* 857 */ rRegL_rule,
5469 /* 858 */ rRegL_rule,
5470 /* 859 */ rRegL_rule,
5471 /* 860 */ rRegL_rule,
5472 /* 861 */ Universe_rule,
5473 /* 862 */ Universe_rule,
5474 /* 863 */ Universe_rule,
5475 /* 864 */ Universe_rule,
5476 /* 865 */ rRegL_rule,
5477 /* 866 */ rRegL_rule,
5478 /* 867 */ rRegL_rule,
5479 /* 868 */ rRegL_rule,
5480 /* 869 */ rRegL_rule,
5481 /* 870 */ Universe_rule,
5482 /* 871 */ Universe_rule,
5483 /* 872 */ Universe_rule,
5484 /* 873 */ rRegI_rule,
5485 /* 874 */ rRegI_rule,
5486 /* 875 */ rRegI_rule,
5487 /* 876 */ rRegI_rule,
5488 /* 877 */ rRegI_rule,
5489 /* 878 */ rRegI_rule,
5490 /* 879 */ rRegI_rule,
5491 /* 880 */ rRegI_rule,
5492 /* 881 */ rRegI_rule,
5493 /* 882 */ rRegI_rule,
5494 /* 883 */ rRegI_rule,
5495 /* 884 */ rRegI_rule,
5496 /* 885 */ rRegI_rule,
5497 /* 886 */ rRegI_rule,
5498 /* 887 */ rRegI_rule,
5499 /* 888 */ rRegI_rule,
5500 /* 889 */ regD_rule,
5501 /* 890 */ regD_rule,
5502 /* 891 */ regF_rule,
5503 /* 892 */ regF_rule,
5504 /* 893 */ rRegI_rule,
5505 /* 894 */ rRegL_rule,
5506 /* 895 */ rRegI_rule,
5507 /* 896 */ rRegL_rule,
5508 /* 897 */ regF_rule,
5509 /* 898 */ regF_rule,
5510 /* 899 */ regD_rule,
5511 /* 900 */ regD_rule,
5512 /* 901 */ regF_rule,
5513 /* 902 */ regD_rule,
5514 /* 903 */ regF_rule,
5515 /* 904 */ regF_rule,
5516 /* 905 */ regD_rule,
5517 /* 906 */ regD_rule,
5518 /* 907 */ rRegL_rule,
5519 /* 908 */ rRegL_rule,
5520 /* 909 */ rRegL_rule,
5521 /* 910 */ rRegL_rule,
5522 /* 911 */ rRegI_rule,
5523 /* 912 */ stackSlotI_rule,
5524 /* 913 */ stackSlotF_rule,
5525 /* 914 */ stackSlotL_rule,
5526 /* 915 */ stackSlotD_rule,
5527 /* 916 */ Universe_rule,
5528 /* 917 */ Universe_rule,
5529 /* 918 */ Universe_rule,
5530 /* 919 */ Universe_rule,
5531 /* 920 */ Universe_rule,
5532 /* 921 */ rax_RegI_rule,
5533 /* 922 */ rax_RegI_rule,
5534 /* 923 */ rax_RegI_rule,
5535 /* 924 */ rax_RegI_rule,
5536 /* 925 */ rax_RegI_rule,
5537 /* 926 */ rax_RegI_rule,
5538 /* 927 */ rax_RegI_rule,
5539 /* 928 */ rax_RegI_rule,
5540 /* 929 */ rbx_RegI_rule,
5541 /* 930 */ rbx_RegI_rule,
5542 /* 931 */ rbx_RegI_rule,
5543 /* 932 */ rbx_RegI_rule,
5544 /* 933 */ rbx_RegI_rule,
5545 /* 934 */ rbx_RegI_rule,
5546 /* 935 */ rbx_RegI_rule,
5547 /* 936 */ rbx_RegI_rule,
5548 /* 937 */ rax_RegI_rule,
5549 /* 938 */ rax_RegI_rule,
5550 /* 939 */ rax_RegI_rule,
5551 /* 940 */ rax_RegI_rule,
5552 /* 941 */ rax_RegI_rule,
5553 /* 942 */ rax_RegI_rule,
5554 /* 943 */ rax_RegI_rule,
5555 /* 944 */ rax_RegI_rule,
5556 /* 945 */ rax_RegI_rule,
5557 /* 946 */ rax_RegI_rule,
5558 /* 947 */ Universe_rule,
5559 /* 948 */ Universe_rule,
5560 /* 949 */ rax_RegI_rule,
5561 /* 950 */ rax_RegI_rule,
5562 /* 951 */ rRegI_rule,
5563 /* 952 */ 0,
5564 /* 953 */ rRegI_rule,
5565 /* 954 */ 0,
5566 /* 955 */ rRegI_rule,
5567 /* 956 */ Universe_rule,
5568 /* 957 */ Universe_rule,
5569 /* 958 */ Universe_rule,
5570 /* 959 */ Universe_rule,
5571 /* 960 */ Universe_rule,
5572 /* 961 */ Universe_rule,
5573 /* 962 */ Universe_rule,
5574 /* 963 */ Universe_rule,
5575 /* 964 */ Universe_rule,
5576 /* 965 */ Universe_rule,
5577 /* 966 */ Universe_rule,
5578 /* 967 */ rdi_RegP_rule,
5579 /* 968 */ Universe_rule,
5580 /* 969 */ Universe_rule,
5581 /* 970 */ Universe_rule,
5582 /* 971 */ Universe_rule,
5583 /* 972 */ Universe_rule,
5584 /* 973 */ Universe_rule,
5585 /* 974 */ Universe_rule,
5586 /* 975 */ Universe_rule,
5587 /* 976 */ Universe_rule,
5588 /* 977 */ Universe_rule,
5589 /* 978 */ Universe_rule,
5590 /* 979 */ Universe_rule,
5591 /* 980 */ Universe_rule,
5592 /* 981 */ Universe_rule,
5593 /* 982 */ Universe_rule,
5594 /* 983 */ Universe_rule,
5595 /* 984 */ Universe_rule,
5596 /* 985 */ Universe_rule,
5597 /* 986 */ Universe_rule,
5598 /* 987 */ rax_RegP_rule,
5599 /* 988 */ Universe_rule,
5600 /* 989 */ Universe_rule,
5601 /* 990 */ rRegI_rule,
5602 /* 991 */ regF_rule,
5603 /* 992 */ regF_rule,
5604 /* 993 */ regF_rule,
5605 /* 994 */ regF_rule,
5606 /* 995 */ regF_rule,
5607 /* 996 */ regF_rule,
5608 /* 997 */ regF_rule,
5609 /* 998 */ regF_rule,
5610 /* 999 */ regD_rule,
5611 /* 1000 */ regD_rule,
5612 /* 1001 */ regD_rule,
5613 /* 1002 */ regD_rule,
5614 /* 1003 */ regD_rule,
5615 /* 1004 */ regD_rule,
5616 /* 1005 */ regD_rule,
5617 /* 1006 */ regD_rule,
5618 /* 1007 */ regF_rule,
5619 /* 1008 */ regF_rule,
5620 /* 1009 */ regF_rule,
5621 /* 1010 */ regF_rule,
5622 /* 1011 */ regF_rule,
5623 /* 1012 */ regF_rule,
5624 /* 1013 */ regD_rule,
5625 /* 1014 */ regD_rule,
5626 /* 1015 */ regD_rule,
5627 /* 1016 */ regD_rule,
5628 /* 1017 */ regD_rule,
5629 /* 1018 */ regD_rule,
5630 /* 1019 */ regF_rule,
5631 /* 1020 */ regF_rule,
5632 /* 1021 */ regF_rule,
5633 /* 1022 */ regF_rule,
5634 /* 1023 */ regF_rule,
5635 /* 1024 */ regF_rule,
5636 /* 1025 */ regF_rule,
5637 /* 1026 */ regF_rule,
5638 /* 1027 */ regD_rule,
5639 /* 1028 */ regD_rule,
5640 /* 1029 */ regD_rule,
5641 /* 1030 */ regD_rule,
5642 /* 1031 */ regD_rule,
5643 /* 1032 */ regD_rule,
5644 /* 1033 */ regD_rule,
5645 /* 1034 */ regD_rule,
5646 /* 1035 */ regF_rule,
5647 /* 1036 */ regF_rule,
5648 /* 1037 */ regF_rule,
5649 /* 1038 */ regF_rule,
5650 /* 1039 */ regF_rule,
5651 /* 1040 */ regF_rule,
5652 /* 1041 */ regD_rule,
5653 /* 1042 */ regD_rule,
5654 /* 1043 */ regD_rule,
5655 /* 1044 */ regD_rule,
5656 /* 1045 */ regD_rule,
5657 /* 1046 */ regD_rule,
5658 /* 1047 */ regF_rule,
5659 /* 1048 */ regD_rule,
5660 /* 1049 */ kReg_rule,
5661 /* 1050 */ kReg_rule,
5662 /* 1051 */ kReg_rule,
5663 /* 1052 */ vec_rule,
5664 /* 1053 */ legVec_rule,
5665 /* 1054 */ legRegD_rule,
5666 /* 1055 */ legRegD_rule,
5667 /* 1056 */ legRegD_rule,
5668 /* 1057 */ legVec_rule,
5669 /* 1058 */ vec_rule,
5670 /* 1059 */ legVec_rule,
5671 /* 1060 */ vec_rule,
5672 /* 1061 */ Universe_rule,
5673 /* 1062 */ regD_rule,
5674 /* 1063 */ regF_rule,
5675 /* 1064 */ vec_rule,
5676 /* 1065 */ Universe_rule,
5677 /* 1066 */ legVec_rule,
5678 /* 1067 */ vec_rule,
5679 /* 1068 */ vec_rule,
5680 /* 1069 */ Universe_rule,
5681 /* 1070 */ Universe_rule,
5682 /* 1071 */ vec_rule,
5683 /* 1072 */ vec_rule,
5684 /* 1073 */ vec_rule,
5685 /* 1074 */ vec_rule,
5686 /* 1075 */ vec_rule,
5687 /* 1076 */ vec_rule,
5688 /* 1077 */ vec_rule,
5689 /* 1078 */ vec_rule,
5690 /* 1079 */ vec_rule,
5691 /* 1080 */ vec_rule,
5692 /* 1081 */ vec_rule,
5693 /* 1082 */ vec_rule,
5694 /* 1083 */ vec_rule,
5695 /* 1084 */ vec_rule,
5696 /* 1085 */ vec_rule,
5697 /* 1086 */ vec_rule,
5698 /* 1087 */ vec_rule,
5699 /* 1088 */ vec_rule,
5700 /* 1089 */ vec_rule,
5701 /* 1090 */ vec_rule,
5702 /* 1091 */ vec_rule,
5703 /* 1092 */ vec_rule,
5704 /* 1093 */ vec_rule,
5705 /* 1094 */ vec_rule,
5706 /* 1095 */ vec_rule,
5707 /* 1096 */ vec_rule,
5708 /* 1097 */ vec_rule,
5709 /* 1098 */ vec_rule,
5710 /* 1099 */ vec_rule,
5711 /* 1100 */ vec_rule,
5712 /* 1101 */ vec_rule,
5713 /* 1102 */ vec_rule,
5714 /* 1103 */ vec_rule,
5715 /* 1104 */ vec_rule,
5716 /* 1105 */ vec_rule,
5717 /* 1106 */ vec_rule,
5718 /* 1107 */ vec_rule,
5719 /* 1108 */ rRegI_rule,
5720 /* 1109 */ rRegI_rule,
5721 /* 1110 */ rRegI_rule,
5722 /* 1111 */ rRegI_rule,
5723 /* 1112 */ rRegI_rule,
5724 /* 1113 */ rRegI_rule,
5725 /* 1114 */ rRegI_rule,
5726 /* 1115 */ rRegL_rule,
5727 /* 1116 */ rRegL_rule,
5728 /* 1117 */ rRegL_rule,
5729 /* 1118 */ rRegL_rule,
5730 /* 1119 */ rRegL_rule,
5731 /* 1120 */ rRegL_rule,
5732 /* 1121 */ rRegL_rule,
5733 /* 1122 */ rRegL_rule,
5734 /* 1123 */ rRegL_rule,
5735 /* 1124 */ rRegL_rule,
5736 /* 1125 */ rRegL_rule,
5737 /* 1126 */ rRegL_rule,
5738 /* 1127 */ rRegL_rule,
5739 /* 1128 */ rRegL_rule,
5740 /* 1129 */ regF_rule,
5741 /* 1130 */ regF_rule,
5742 /* 1131 */ regF_rule,
5743 /* 1132 */ regF_rule,
5744 /* 1133 */ regF_rule,
5745 /* 1134 */ regF_rule,
5746 /* 1135 */ regD_rule,
5747 /* 1136 */ regD_rule,
5748 /* 1137 */ regD_rule,
5749 /* 1138 */ regD_rule,
5750 /* 1139 */ regD_rule,
5751 /* 1140 */ regD_rule,
5752 /* 1141 */ rRegI_rule,
5753 /* 1142 */ rRegI_rule,
5754 /* 1143 */ rRegI_rule,
5755 /* 1144 */ rRegI_rule,
5756 /* 1145 */ rRegI_rule,
5757 /* 1146 */ rRegI_rule,
5758 /* 1147 */ rRegI_rule,
5759 /* 1148 */ rRegI_rule,
5760 /* 1149 */ rRegI_rule,
5761 /* 1150 */ rRegI_rule,
5762 /* 1151 */ rRegI_rule,
5763 /* 1152 */ rRegI_rule,
5764 /* 1153 */ rRegI_rule,
5765 /* 1154 */ rRegI_rule,
5766 /* 1155 */ rRegI_rule,
5767 /* 1156 */ rRegI_rule,
5768 /* 1157 */ rRegI_rule,
5769 /* 1158 */ rRegI_rule,
5770 /* 1159 */ rRegI_rule,
5771 /* 1160 */ rRegI_rule,
5772 /* 1161 */ rRegI_rule,
5773 /* 1162 */ legRegF_rule,
5774 /* 1163 */ legRegF_rule,
5775 /* 1164 */ legRegF_rule,
5776 /* 1165 */ legRegF_rule,
5777 /* 1166 */ legRegF_rule,
5778 /* 1167 */ legRegF_rule,
5779 /* 1168 */ legRegF_rule,
5780 /* 1169 */ legRegF_rule,
5781 /* 1170 */ legRegD_rule,
5782 /* 1171 */ legRegD_rule,
5783 /* 1172 */ legRegD_rule,
5784 /* 1173 */ legRegD_rule,
5785 /* 1174 */ legRegD_rule,
5786 /* 1175 */ legRegD_rule,
5787 /* 1176 */ legRegD_rule,
5788 /* 1177 */ legRegD_rule,
5789 /* 1178 */ vec_rule,
5790 /* 1179 */ vec_rule,
5791 /* 1180 */ vec_rule,
5792 /* 1181 */ vec_rule,
5793 /* 1182 */ vec_rule,
5794 /* 1183 */ vec_rule,
5795 /* 1184 */ vec_rule,
5796 /* 1185 */ vec_rule,
5797 /* 1186 */ vec_rule,
5798 /* 1187 */ vec_rule,
5799 /* 1188 */ vec_rule,
5800 /* 1189 */ vec_rule,
5801 /* 1190 */ vec_rule,
5802 /* 1191 */ vec_rule,
5803 /* 1192 */ vec_rule,
5804 /* 1193 */ vec_rule,
5805 /* 1194 */ vec_rule,
5806 /* 1195 */ vec_rule,
5807 /* 1196 */ vec_rule,
5808 /* 1197 */ vec_rule,
5809 /* 1198 */ vec_rule,
5810 /* 1199 */ vec_rule,
5811 /* 1200 */ vec_rule,
5812 /* 1201 */ vec_rule,
5813 /* 1202 */ vec_rule,
5814 /* 1203 */ vec_rule,
5815 /* 1204 */ vec_rule,
5816 /* 1205 */ vec_rule,
5817 /* 1206 */ vec_rule,
5818 /* 1207 */ vec_rule,
5819 /* 1208 */ vec_rule,
5820 /* 1209 */ vec_rule,
5821 /* 1210 */ vec_rule,
5822 /* 1211 */ vec_rule,
5823 /* 1212 */ vec_rule,
5824 /* 1213 */ vec_rule,
5825 /* 1214 */ vec_rule,
5826 /* 1215 */ vec_rule,
5827 /* 1216 */ vec_rule,
5828 /* 1217 */ vec_rule,
5829 /* 1218 */ vec_rule,
5830 /* 1219 */ vec_rule,
5831 /* 1220 */ vec_rule,
5832 /* 1221 */ vec_rule,
5833 /* 1222 */ vec_rule,
5834 /* 1223 */ vec_rule,
5835 /* 1224 */ vec_rule,
5836 /* 1225 */ vec_rule,
5837 /* 1226 */ vec_rule,
5838 /* 1227 */ vec_rule,
5839 /* 1228 */ vec_rule,
5840 /* 1229 */ vec_rule,
5841 /* 1230 */ vec_rule,
5842 /* 1231 */ vec_rule,
5843 /* 1232 */ vec_rule,
5844 /* 1233 */ vec_rule,
5845 /* 1234 */ vec_rule,
5846 /* 1235 */ vec_rule,
5847 /* 1236 */ vec_rule,
5848 /* 1237 */ vec_rule,
5849 /* 1238 */ vec_rule,
5850 /* 1239 */ vec_rule,
5851 /* 1240 */ vec_rule,
5852 /* 1241 */ vec_rule,
5853 /* 1242 */ vec_rule,
5854 /* 1243 */ vec_rule,
5855 /* 1244 */ vec_rule,
5856 /* 1245 */ vec_rule,
5857 /* 1246 */ legVec_rule,
5858 /* 1247 */ legVec_rule,
5859 /* 1248 */ vec_rule,
5860 /* 1249 */ vec_rule,
5861 /* 1250 */ vec_rule,
5862 /* 1251 */ vec_rule,
5863 /* 1252 */ vec_rule,
5864 /* 1253 */ vec_rule,
5865 /* 1254 */ vec_rule,
5866 /* 1255 */ vec_rule,
5867 /* 1256 */ vec_rule,
5868 /* 1257 */ vec_rule,
5869 /* 1258 */ vec_rule,
5870 /* 1259 */ vec_rule,
5871 /* 1260 */ legVec_rule,
5872 /* 1261 */ legVec_rule,
5873 /* 1262 */ vec_rule,
5874 /* 1263 */ vec_rule,
5875 /* 1264 */ legVec_rule,
5876 /* 1265 */ legVec_rule,
5877 /* 1266 */ vec_rule,
5878 /* 1267 */ vec_rule,
5879 /* 1268 */ regF_rule,
5880 /* 1269 */ regD_rule,
5881 /* 1270 */ regF_rule,
5882 /* 1271 */ regD_rule,
5883 /* 1272 */ vec_rule,
5884 /* 1273 */ vec_rule,
5885 /* 1274 */ vec_rule,
5886 /* 1275 */ vec_rule,
5887 /* 1276 */ vec_rule,
5888 /* 1277 */ vec_rule,
5889 /* 1278 */ vec_rule,
5890 /* 1279 */ vec_rule,
5891 /* 1280 */ vec_rule,
5892 /* 1281 */ vec_rule,
5893 /* 1282 */ vec_rule,
5894 /* 1283 */ vec_rule,
5895 /* 1284 */ vec_rule,
5896 /* 1285 */ vec_rule,
5897 /* 1286 */ vec_rule,
5898 /* 1287 */ vec_rule,
5899 /* 1288 */ vec_rule,
5900 /* 1289 */ vec_rule,
5901 /* 1290 */ vec_rule,
5902 /* 1291 */ vec_rule,
5903 /* 1292 */ vec_rule,
5904 /* 1293 */ vec_rule,
5905 /* 1294 */ vec_rule,
5906 /* 1295 */ vec_rule,
5907 /* 1296 */ vec_rule,
5908 /* 1297 */ vec_rule,
5909 /* 1298 */ vec_rule,
5910 /* 1299 */ vec_rule,
5911 /* 1300 */ vec_rule,
5912 /* 1301 */ vec_rule,
5913 /* 1302 */ vec_rule,
5914 /* 1303 */ vec_rule,
5915 /* 1304 */ vec_rule,
5916 /* 1305 */ vec_rule,
5917 /* 1306 */ vec_rule,
5918 /* 1307 */ vec_rule,
5919 /* 1308 */ vec_rule,
5920 /* 1309 */ vec_rule,
5921 /* 1310 */ vec_rule,
5922 /* 1311 */ vec_rule,
5923 /* 1312 */ vec_rule,
5924 /* 1313 */ vec_rule,
5925 /* 1314 */ vec_rule,
5926 /* 1315 */ vec_rule,
5927 /* 1316 */ vec_rule,
5928 /* 1317 */ vec_rule,
5929 /* 1318 */ vec_rule,
5930 /* 1319 */ vec_rule,
5931 /* 1320 */ vec_rule,
5932 /* 1321 */ vec_rule,
5933 /* 1322 */ vec_rule,
5934 /* 1323 */ vec_rule,
5935 /* 1324 */ vec_rule,
5936 /* 1325 */ vec_rule,
5937 /* 1326 */ vec_rule,
5938 /* 1327 */ vec_rule,
5939 /* 1328 */ vec_rule,
5940 /* 1329 */ vec_rule,
5941 /* 1330 */ vec_rule,
5942 /* 1331 */ vec_rule,
5943 /* 1332 */ vec_rule,
5944 /* 1333 */ vec_rule,
5945 /* 1334 */ vec_rule,
5946 /* 1335 */ vec_rule,
5947 /* 1336 */ vec_rule,
5948 /* 1337 */ vec_rule,
5949 /* 1338 */ vec_rule,
5950 /* 1339 */ vec_rule,
5951 /* 1340 */ vec_rule,
5952 /* 1341 */ vec_rule,
5953 /* 1342 */ vec_rule,
5954 /* 1343 */ vec_rule,
5955 /* 1344 */ vec_rule,
5956 /* 1345 */ vec_rule,
5957 /* 1346 */ vec_rule,
5958 /* 1347 */ vec_rule,
5959 /* 1348 */ vec_rule,
5960 /* 1349 */ vec_rule,
5961 /* 1350 */ vec_rule,
5962 /* 1351 */ vec_rule,
5963 /* 1352 */ vec_rule,
5964 /* 1353 */ legVec_rule,
5965 /* 1354 */ vec_rule,
5966 /* 1355 */ kReg_rule,
5967 /* 1356 */ legVec_rule,
5968 /* 1357 */ legVec_rule,
5969 /* 1358 */ legVec_rule,
5970 /* 1359 */ vec_rule,
5971 /* 1360 */ kReg_rule,
5972 /* 1361 */ rRegI_rule,
5973 /* 1362 */ rRegI_rule,
5974 /* 1363 */ rRegI_rule,
5975 /* 1364 */ rRegI_rule,
5976 /* 1365 */ rRegI_rule,
5977 /* 1366 */ rRegI_rule,
5978 /* 1367 */ rRegL_rule,
5979 /* 1368 */ rRegL_rule,
5980 /* 1369 */ legRegF_rule,
5981 /* 1370 */ legRegF_rule,
5982 /* 1371 */ legRegD_rule,
5983 /* 1372 */ legRegD_rule,
5984 /* 1373 */ vec_rule,
5985 /* 1374 */ legVec_rule,
5986 /* 1375 */ legVec_rule,
5987 /* 1376 */ vec_rule,
5988 /* 1377 */ vec_rule,
5989 /* 1378 */ vec_rule,
5990 /* 1379 */ vec_rule,
5991 /* 1380 */ vec_rule,
5992 /* 1381 */ vec_rule,
5993 /* 1382 */ vec_rule,
5994 /* 1383 */ vec_rule,
5995 /* 1384 */ rRegI_rule,
5996 /* 1385 */ rRegI_rule,
5997 /* 1386 */ rRegI_rule,
5998 /* 1387 */ rRegI_rule,
5999 /* 1388 */ rRegI_rule,
6000 /* 1389 */ rRegI_rule,
6001 /* 1390 */ rRegI_rule,
6002 /* 1391 */ legVec_rule,
6003 /* 1392 */ kReg_rule,
6004 /* 1393 */ kReg_rule,
6005 /* 1394 */ vec_rule,
6006 /* 1395 */ vec_rule,
6007 /* 1396 */ vec_rule,
6008 /* 1397 */ vec_rule,
6009 /* 1398 */ vec_rule,
6010 /* 1399 */ vec_rule,
6011 /* 1400 */ vec_rule,
6012 /* 1401 */ vec_rule,
6013 /* 1402 */ vec_rule,
6014 /* 1403 */ vec_rule,
6015 /* 1404 */ vec_rule,
6016 /* 1405 */ legVec_rule,
6017 /* 1406 */ vec_rule,
6018 /* 1407 */ vec_rule,
6019 /* 1408 */ vec_rule,
6020 /* 1409 */ legVec_rule,
6021 /* 1410 */ vec_rule,
6022 /* 1411 */ vec_rule,
6023 /* 1412 */ vec_rule,
6024 /* 1413 */ vec_rule,
6025 /* 1414 */ vec_rule,
6026 /* 1415 */ vec_rule,
6027 /* 1416 */ vec_rule,
6028 /* 1417 */ vec_rule,
6029 /* 1418 */ vec_rule,
6030 /* 1419 */ vec_rule,
6031 /* 1420 */ vec_rule,
6032 /* 1421 */ vec_rule,
6033 /* 1422 */ vec_rule,
6034 /* 1423 */ vec_rule,
6035 /* 1424 */ vec_rule,
6036 /* 1425 */ vec_rule,
6037 /* 1426 */ vec_rule,
6038 /* 1427 */ vec_rule,
6039 /* 1428 */ vec_rule,
6040 /* 1429 */ vec_rule,
6041 /* 1430 */ vec_rule,
6042 /* 1431 */ rRegI_rule,
6043 /* 1432 */ vec_rule,
6044 /* 1433 */ kReg_rule,
6045 /* 1434 */ kReg_rule,
6046 /* 1435 */ Universe_rule,
6047 /* 1436 */ rRegL_rule,
6048 /* 1437 */ rRegL_rule,
6049 /* 1438 */ rRegL_rule,
6050 /* 1439 */ rRegI_rule,
6051 /* 1440 */ rRegI_rule,
6052 /* 1441 */ rRegI_rule,
6053 /* 1442 */ rRegI_rule,
6054 /* 1443 */ rRegI_rule,
6055 /* 1444 */ rRegI_rule,
6056 /* 1445 */ rRegI_rule,
6057 /* 1446 */ rRegI_rule,
6058 /* 1447 */ rRegI_rule,
6059 /* 1448 */ vec_rule,
6060 /* 1449 */ vec_rule,
6061 /* 1450 */ vec_rule,
6062 /* 1451 */ vec_rule,
6063 /* 1452 */ vec_rule,
6064 /* 1453 */ vec_rule,
6065 /* 1454 */ vec_rule,
6066 /* 1455 */ vec_rule,
6067 /* 1456 */ vec_rule,
6068 /* 1457 */ vec_rule,
6069 /* 1458 */ vec_rule,
6070 /* 1459 */ vec_rule,
6071 /* 1460 */ vec_rule,
6072 /* 1461 */ vec_rule,
6073 /* 1462 */ vec_rule,
6074 /* 1463 */ vec_rule,
6075 /* 1464 */ vec_rule,
6076 /* 1465 */ vec_rule,
6077 /* 1466 */ vec_rule,
6078 /* 1467 */ vec_rule,
6079 /* 1468 */ vec_rule,
6080 /* 1469 */ vec_rule,
6081 /* 1470 */ vec_rule,
6082 /* 1471 */ vec_rule,
6083 /* 1472 */ vec_rule,
6084 /* 1473 */ vec_rule,
6085 /* 1474 */ vec_rule,
6086 /* 1475 */ vec_rule,
6087 /* 1476 */ vec_rule,
6088 /* 1477 */ vec_rule,
6089 /* 1478 */ vec_rule,
6090 /* 1479 */ vec_rule,
6091 /* 1480 */ vec_rule,
6092 /* 1481 */ vec_rule,
6093 /* 1482 */ vec_rule,
6094 /* 1483 */ vec_rule,
6095 /* 1484 */ vec_rule,
6096 /* 1485 */ vec_rule,
6097 /* 1486 */ vec_rule,
6098 /* 1487 */ vec_rule,
6099 /* 1488 */ vec_rule,
6100 /* 1489 */ vec_rule,
6101 /* 1490 */ vec_rule,
6102 /* 1491 */ vec_rule,
6103 /* 1492 */ vec_rule,
6104 /* 1493 */ vec_rule,
6105 /* 1494 */ vec_rule,
6106 /* 1495 */ vec_rule,
6107 /* 1496 */ vec_rule,
6108 /* 1497 */ vec_rule,
6109 /* 1498 */ vec_rule,
6110 /* 1499 */ vec_rule,
6111 /* 1500 */ vec_rule,
6112 /* 1501 */ vec_rule,
6113 /* 1502 */ vec_rule,
6114 /* 1503 */ vec_rule,
6115 /* 1504 */ vec_rule,
6116 /* 1505 */ vec_rule,
6117 /* 1506 */ vec_rule,
6118 /* 1507 */ vec_rule,
6119 /* 1508 */ vec_rule,
6120 /* 1509 */ vec_rule,
6121 /* 1510 */ vec_rule,
6122 /* 1511 */ vec_rule,
6123 /* 1512 */ vec_rule,
6124 /* 1513 */ vec_rule,
6125 /* 1514 */ vec_rule,
6126 /* 1515 */ vec_rule,
6127 /* 1516 */ vec_rule,
6128 /* 1517 */ vec_rule,
6129 /* 1518 */ vec_rule,
6130 /* 1519 */ vec_rule,
6131 /* 1520 */ vec_rule,
6132 /* 1521 */ vec_rule,
6133 /* 1522 */ vec_rule,
6134 /* 1523 */ vec_rule,
6135 /* 1524 */ vec_rule,
6136 /* 1525 */ vec_rule,
6137 /* 1526 */ vec_rule,
6138 /* 1527 */ vec_rule,
6139 /* 1528 */ vec_rule,
6140 /* 1529 */ vec_rule,
6141 /* 1530 */ vec_rule,
6142 /* 1531 */ vec_rule,
6143 /* 1532 */ vec_rule,
6144 /* 1533 */ vec_rule,
6145 /* 1534 */ vec_rule,
6146 /* 1535 */ vec_rule,
6147 /* 1536 */ vec_rule,
6148 /* 1537 */ vec_rule,
6149 /* 1538 */ vec_rule,
6150 /* 1539 */ vec_rule,
6151 /* 1540 */ vec_rule,
6152 /* 1541 */ vec_rule,
6153 /* 1542 */ vec_rule,
6154 /* 1543 */ vec_rule,
6155 /* 1544 */ vec_rule,
6156 /* 1545 */ vec_rule,
6157 /* 1546 */ vec_rule,
6158 /* 1547 */ kReg_rule,
6159 /* 1548 */ kReg_rule,
6160 /* 1549 */ kReg_rule,
6161 /* 1550 */ kReg_rule,
6162 /* 1551 */ kReg_rule,
6163 /* 1552 */ kReg_rule,
6164 /* 1553 */ vec_rule,
6165 /* 1554 */ vec_rule,
6166 /* 1555 */ kReg_rule,
6167 /* 1556 */ kReg_rule,
6168 /* 1557 */ kReg_rule,
6169 /* 1558 */ rRegI_rule,
6170 /* 1559 */ rRegI_rule,
6171 /* 1560 */ rRegI_rule,
6172 /* 1561 */ rRegI_rule,
6173 /* 1562 */ rax_RegN_rule,
6174 /* 1563 */ rax_RegP_rule,
6175 /* 1564 */ rRegP_rule,
6176 /* 1565 */ rax_RegP_rule,
6177 /* 1566 */ rRegI_rule,
6178 /* 1567 */ rRegI_rule,
6179 /* 1568 */ rRegP_rule,
6180 // last instruction
6181 0 // no trailing comma
6182};
6183
6184const int leftOp[] = {
6185 /* 0 */ 0,
6186 /* 1 */ 0,
6187 /* 2 */ 0,
6188 /* 3 */ 0,
6189 /* 4 */ 0,
6190 /* 5 */ 0,
6191 /* 6 */ 0,
6192 /* 7 */ 0,
6193 /* 8 */ 0,
6194 /* 9 */ 0,
6195 /* 10 */ 0,
6196 /* 11 */ 0,
6197 /* 12 */ 0,
6198 /* 13 */ 0,
6199 /* 14 */ 0,
6200 /* 15 */ 0,
6201 /* 16 */ 0,
6202 /* 17 */ 0,
6203 /* 18 */ 0,
6204 /* 19 */ 0,
6205 /* 20 */ 0,
6206 /* 21 */ 0,
6207 /* 22 */ 0,
6208 /* 23 */ 0,
6209 /* 24 */ 0,
6210 /* 25 */ 0,
6211 /* 26 */ 0,
6212 /* 27 */ 0,
6213 /* 28 */ 0,
6214 /* 29 */ 0,
6215 /* 30 */ 0,
6216 /* 31 */ 0,
6217 /* 32 */ 0,
6218 /* 33 */ 0,
6219 /* 34 */ 0,
6220 /* 35 */ 0,
6221 /* 36 */ 0,
6222 /* 37 */ 0,
6223 /* 38 */ 0,
6224 /* 39 */ 0,
6225 /* 40 */ 0,
6226 /* 41 */ 0,
6227 /* 42 */ 0,
6228 /* 43 */ 0,
6229 /* 44 */ 0,
6230 /* 45 */ 0,
6231 /* 46 */ 0,
6232 /* 47 */ 0,
6233 /* 48 */ 0,
6234 /* 49 */ 0,
6235 /* 50 */ 0,
6236 /* 51 */ 0,
6237 /* 52 */ 0,
6238 /* 53 */ 0,
6239 /* 54 */ 0,
6240 /* 55 */ 0,
6241 /* 56 */ 0,
6242 /* 57 */ 0,
6243 /* 58 */ 0,
6244 /* 59 */ 0,
6245 /* 60 */ 0,
6246 /* 61 */ 0,
6247 /* 62 */ 0,
6248 /* 63 */ 0,
6249 /* 64 */ 0,
6250 /* 65 */ 0,
6251 /* 66 */ 0,
6252 /* 67 */ 0,
6253 /* 68 */ 0,
6254 /* 69 */ 0,
6255 /* 70 */ 0,
6256 /* 71 */ 0,
6257 /* 72 */ 0,
6258 /* 73 */ 0,
6259 /* 74 */ 0,
6260 /* 75 */ 0,
6261 /* 76 */ 0,
6262 /* 77 */ 0,
6263 /* 78 */ 0,
6264 /* 79 */ 0,
6265 /* 80 */ 0,
6266 /* 81 */ 0,
6267 /* 82 */ 0,
6268 /* 83 */ 0,
6269 /* 84 */ 0,
6270 /* 85 */ 0,
6271 /* 86 */ 0,
6272 /* 87 */ 0,
6273 /* 88 */ 0,
6274 /* 89 */ 0,
6275 /* 90 */ 0,
6276 /* 91 */ 0,
6277 /* 92 */ 0,
6278 /* 93 */ 0,
6279 /* 94 */ 0,
6280 /* 95 */ 0,
6281 /* 96 */ any_RegP_rule,
6282 /* 97 */ any_RegP_rule,
6283 /* 98 */ _AddP_any_RegP_rRegL_rule,
6284 /* 99 */ any_RegP_rule,
6285 /* 100 */ any_RegP_rule,
6286 /* 101 */ any_RegP_rule,
6287 /* 102 */ _AddP_any_RegP__LShiftL_rRegL_immI2_rule,
6288 /* 103 */ _AddP_any_RegP__ConvI2L_rRegI__rule,
6289 /* 104 */ _AddP_any_RegP__LShiftL__ConvI2L_rRegI__immI2_rule,
6290 /* 105 */ _DecodeN_rRegN__rule,
6291 /* 106 */ rRegN_rule,
6292 /* 107 */ _DecodeN_rRegN__rule,
6293 /* 108 */ _DecodeN_rRegN__rule,
6294 /* 109 */ _AddP__DecodeN_rRegN__rRegL_rule,
6295 /* 110 */ _DecodeN_rRegN__rule,
6296 /* 111 */ _DecodeN_rRegN__rule,
6297 /* 112 */ _AddP__DecodeN_rRegN___LShiftL_rRegL_immI2_rule,
6298 /* 113 */ _AddP__DecodeN_rRegN___ConvI2L_rRegI__rule,
6299 /* 114 */ _AddP__DecodeN_rRegN___LShiftL__ConvI2L_rRegI__immI2_rule,
6300 /* 115 */ 0,
6301 /* 116 */ 0,
6302 /* 117 */ 0,
6303 /* 118 */ 0,
6304 /* 119 */ 0,
6305 /* 120 */ 0,
6306 /* 121 */ 0,
6307 /* 122 */ 0,
6308 /* 123 */ 0,
6309 /* 124 */ 0,
6310 /* 125 */ 0,
6311 /* 126 */ 0,
6312 /* 127 */ 0,
6313 /* 128 */ 0,
6314 /* 129 */ 0,
6315 /* 130 */ 0,
6316 /* 131 */ 0,
6317 /* 132 */ 0,
6318 /* 133 */ 0,
6319 /* 134 */ 0,
6320 /* 135 */ 0,
6321 /* 136 */ 0,
6322 /* 137 */ 0,
6323 // last operand
6324 /* 138 */ 0,
6325 // last operand class
6326 /* 139 */ any_RegP_rule,
6327 /* 140 */ rRegL_rule,
6328 /* 141 */ rRegI_rule,
6329 /* 142 */ _ConvI2L_rRegI__rule,
6330 /* 143 */ any_RegP_rule,
6331 /* 144 */ any_RegP_rule,
6332 /* 145 */ any_RegP_rule,
6333 /* 146 */ rRegN_rule,
6334 /* 147 */ _DecodeN_rRegN__rule,
6335 /* 148 */ _DecodeN_rRegN__rule,
6336 /* 149 */ _DecodeN_rRegN__rule,
6337 /* 150 */ _DecodeN_rRegN__rule,
6338 /* 151 */ memory_rule,
6339 /* 152 */ memory_rule,
6340 /* 153 */ _LoadUB_memory__rule,
6341 /* 154 */ memory_rule,
6342 /* 155 */ _LoadS_memory__rule,
6343 /* 156 */ memory_rule,
6344 /* 157 */ _LoadUS_memory__rule,
6345 /* 158 */ _LoadUS_memory__rule,
6346 /* 159 */ _LoadUS_memory__rule,
6347 /* 160 */ memory_rule,
6348 /* 161 */ _LoadI_memory__rule,
6349 /* 162 */ _LoadI_memory__rule,
6350 /* 163 */ _LoadI_memory__rule,
6351 /* 164 */ _LoadI_memory__rule,
6352 /* 165 */ _LoadI_memory__rule,
6353 /* 166 */ _LoadI_memory__rule,
6354 /* 167 */ memory_rule,
6355 /* 168 */ rRegP_rule,
6356 /* 169 */ _DecodeN_rRegN__rule,
6357 /* 170 */ _LShiftL_rRegL_immI2_rule,
6358 /* 171 */ cmpOp_rule,
6359 /* 172 */ rRegI_rule,
6360 /* 173 */ cmpOpU_rule,
6361 /* 174 */ cmpOpUCF_rule,
6362 /* 175 */ rRegI_rule,
6363 /* 176 */ rRegN_rule,
6364 /* 177 */ rRegP_rule,
6365 /* 178 */ rRegL_rule,
6366 /* 179 */ rRegL_rule,
6367 /* 180 */ regF_rule,
6368 /* 181 */ regD_rule,
6369 /* 182 */ _LoadI_memory__rule,
6370 /* 183 */ rRegI_rule,
6371 /* 184 */ _LoadI_memory__rule,
6372 /* 185 */ _LoadI_memory__rule,
6373 /* 186 */ _LoadI_memory__rule,
6374 /* 187 */ _LoadL_memory__rule,
6375 /* 188 */ rRegL_rule,
6376 /* 189 */ _LoadL_memory__rule,
6377 /* 190 */ _LoadL_memory__rule,
6378 /* 191 */ _LoadL_memory__rule,
6379 /* 192 */ rax_RegP_rule,
6380 /* 193 */ rax_RegI_rule,
6381 /* 194 */ rax_RegL_rule,
6382 /* 195 */ rax_RegN_rule,
6383 /* 196 */ _LoadI_memory__rule,
6384 /* 197 */ _LoadI_memory__rule,
6385 /* 198 */ _LoadL_memory__rule,
6386 /* 199 */ _LoadL_memory__rule,
6387 /* 200 */ immI_0_rule,
6388 /* 201 */ immI_0_rule,
6389 /* 202 */ immL0_rule,
6390 /* 203 */ _LoadI_memory__rule,
6391 /* 204 */ _LoadI_memory__rule,
6392 /* 205 */ _LoadI_memory__rule,
6393 /* 206 */ _LoadI_memory__rule,
6394 /* 207 */ _LoadI_memory__rule,
6395 /* 208 */ _LoadI_memory__rule,
6396 /* 209 */ _LoadI_memory__rule,
6397 /* 210 */ _LoadI_memory__rule,
6398 /* 211 */ _LoadI_memory__rule,
6399 /* 212 */ _LoadL_memory__rule,
6400 /* 213 */ _LoadL_memory__rule,
6401 /* 214 */ _LoadL_memory__rule,
6402 /* 215 */ _LoadL_memory__rule,
6403 /* 216 */ _LoadL_memory__rule,
6404 /* 217 */ _LoadL_memory__rule,
6405 /* 218 */ _LoadL_memory__rule,
6406 /* 219 */ _LoadL_memory__rule,
6407 /* 220 */ _LoadL_memory__rule,
6408 /* 221 */ rRegI_rule,
6409 /* 222 */ rRegI_rule,
6410 /* 223 */ rRegI_rule,
6411 /* 224 */ rRegI_rule,
6412 /* 225 */ rRegI_rule,
6413 /* 226 */ _LoadB_memory__rule,
6414 /* 227 */ rRegI_rule,
6415 /* 228 */ _LoadI_memory__rule,
6416 /* 229 */ rRegI_rule,
6417 /* 230 */ _LoadI_memory__rule,
6418 /* 231 */ rRegI_rule,
6419 /* 232 */ rRegI_rule,
6420 /* 233 */ _LoadB_memory__rule,
6421 /* 234 */ rRegI_rule,
6422 /* 235 */ _LoadI_memory__rule,
6423 /* 236 */ rRegI_rule,
6424 /* 237 */ _LoadI_memory__rule,
6425 /* 238 */ _LoadB_memory__rule,
6426 /* 239 */ rRegI_rule,
6427 /* 240 */ _LoadI_memory__rule,
6428 /* 241 */ rRegI_rule,
6429 /* 242 */ _LoadI_memory__rule,
6430 /* 243 */ _LoadL_memory__rule,
6431 /* 244 */ rRegL_rule,
6432 /* 245 */ _LoadL_memory__rule,
6433 /* 246 */ _LoadL_memory__rule,
6434 /* 247 */ rRegL_rule,
6435 /* 248 */ immL0_rule,
6436 /* 249 */ rRegL_rule,
6437 /* 250 */ any_RegP_rule,
6438 /* 251 */ _LoadL_memory__rule,
6439 /* 252 */ rRegL_rule,
6440 /* 253 */ _LoadL_memory__rule,
6441 /* 254 */ _LoadL_memory__rule,
6442 /* 255 */ _LoadL_memory__rule,
6443 /* 256 */ rRegL_rule,
6444 /* 257 */ _LoadL_memory__rule,
6445 /* 258 */ rRegI_rule,
6446 /* 259 */ _CmpLTMask_rRegI_rRegI_rule,
6447 /* 260 */ rRegI_rule,
6448 /* 261 */ rRegI_rule,
6449 /* 262 */ memory_rule,
6450 /* 263 */ memory_rule,
6451 /* 264 */ rdi_RegP_rule,
6452 /* 265 */ rsi_RegP_rule,
6453 /* 266 */ rdi_RegP_rule,
6454 /* 267 */ rsi_RegP_rule,
6455 /* 268 */ rsi_RegP_rule,
6456 /* 269 */ rdi_RegP_rule,
6457 /* 270 */ rRegI_rule,
6458 /* 271 */ memory_rule,
6459 /* 272 */ memory_rule,
6460 /* 273 */ memory_rule,
6461 /* 274 */ rRegL_rule,
6462 /* 275 */ _CastP2X_rRegP__rule,
6463 /* 276 */ _LoadL_memory__rule,
6464 /* 277 */ _LoadUB_memory__rule,
6465 /* 278 */ _LoadB_memory__rule,
6466 /* 279 */ rsi_RegP_rule,
6467 /* 280 */ memory_rule,
6468 /* 281 */ vec_rule,
6469 /* 282 */ vec_rule,
6470 /* 283 */ vec_rule,
6471 /* 284 */ vec_rule,
6472 /* 285 */ vec_rule,
6473 /* 286 */ vec_rule,
6474 /* 287 */ vec_rule,
6475 /* 288 */ cmpOp_vcmppd_rule,
6476 /* 289 */ legVec_rule,
6477 /* 290 */ regD_rule,
6478 /* 291 */ immI8_rule,
6479 /* 292 */ immI8_rule,
6480 /* 293 */ legVec_rule,
6481 /* 294 */ kReg_rule,
6482 /* 295 */ vec_rule,
6483 /* 296 */ vec_rule,
6484 /* 297 */ vec_rule,
6485 /* 298 */ _LoadVector_memory__rule,
6486 /* 299 */ vec_rule,
6487 /* 300 */ vec_rule,
6488 /* 301 */ vec_rule,
6489 /* 302 */ vec_rule,
6490 /* 303 */ _LoadVector_memory__rule,
6491 /* 304 */ immI8_rule,
6492 /* 305 */ immI_M1_rule,
6493 // last internally defined operand
6494 /* 306 */ rRegI_rule,
6495 /* 307 */ rRegL_rule,
6496 /* 308 */ rRegP_rule,
6497 /* 309 */ regF_rule,
6498 /* 310 */ regD_rule,
6499 /* 311 */ regF_rule,
6500 /* 312 */ regF_rule,
6501 /* 313 */ vlRegF_rule,
6502 /* 314 */ legRegF_rule,
6503 /* 315 */ regD_rule,
6504 /* 316 */ regD_rule,
6505 /* 317 */ vlRegD_rule,
6506 /* 318 */ legRegD_rule,
6507 /* 319 */ indOffset8_rule,
6508 /* 320 */ indOffset32_rule,
6509 /* 321 */ indIndexOffset_rule,
6510 /* 322 */ indIndexScale_rule,
6511 /* 323 */ indPosIndexScale_rule,
6512 /* 324 */ indIndexScaleOffset_rule,
6513 /* 325 */ indPosIndexOffset_rule,
6514 /* 326 */ indPosIndexScaleOffset_rule,
6515 /* 327 */ indCompressedOopOffset_rule,
6516 /* 328 */ indOffset8Narrow_rule,
6517 /* 329 */ indOffset32Narrow_rule,
6518 /* 330 */ indIndexOffsetNarrow_rule,
6519 /* 331 */ indIndexScaleNarrow_rule,
6520 /* 332 */ indIndexScaleOffsetNarrow_rule,
6521 /* 333 */ indPosIndexOffsetNarrow_rule,
6522 /* 334 */ indPosIndexScaleOffsetNarrow_rule,
6523 /* 335 */ immI_rule,
6524 /* 336 */ immI_0_rule,
6525 /* 337 */ immL_rule,
6526 /* 338 */ immL0_rule,
6527 /* 339 */ immUL32_rule,
6528 /* 340 */ immL32_rule,
6529 /* 341 */ immP_rule,
6530 /* 342 */ immP0_rule,
6531 /* 343 */ immP31_rule,
6532 /* 344 */ immF_rule,
6533 /* 345 */ immN0_rule,
6534 /* 346 */ immN_rule,
6535 /* 347 */ immNKlass_rule,
6536 /* 348 */ immF0_rule,
6537 /* 349 */ immD_rule,
6538 /* 350 */ immD0_rule,
6539 /* 351 */ stackSlotI_rule,
6540 /* 352 */ stackSlotL_rule,
6541 /* 353 */ stackSlotP_rule,
6542 /* 354 */ stackSlotF_rule,
6543 /* 355 */ stackSlotD_rule,
6544 /* 356 */ vec_rule,
6545 /* 357 */ legVec_rule,
6546 /* 358 */ 0,
6547 /* 359 */ rRegL_rule,
6548 /* 360 */ rRegP_rule,
6549 /* 361 */ rRegP_rule,
6550 /* 362 */ rRegP_rule,
6551 /* 363 */ rRegI_rule,
6552 /* 364 */ rRegL_rule,
6553 /* 365 */ regF_rule,
6554 /* 366 */ regD_rule,
6555 /* 367 */ memory_rule,
6556 /* 368 */ memory_rule,
6557 /* 369 */ memory_rule,
6558 /* 370 */ regF_rule,
6559 /* 371 */ regF_rule,
6560 /* 372 */ regF_rule,
6561 /* 373 */ regF_rule,
6562 /* 374 */ regF_rule,
6563 /* 375 */ regF_rule,
6564 /* 376 */ regD_rule,
6565 /* 377 */ regD_rule,
6566 /* 378 */ regD_rule,
6567 /* 379 */ regD_rule,
6568 /* 380 */ regD_rule,
6569 /* 381 */ regD_rule,
6570 /* 382 */ stackSlotF_rule,
6571 /* 383 */ stackSlotI_rule,
6572 /* 384 */ stackSlotD_rule,
6573 /* 385 */ stackSlotL_rule,
6574 /* 386 */ stackSlotL_rule,
6575 /* 387 */ regF_rule,
6576 /* 388 */ regD_rule,
6577 /* 389 */ rRegI_rule,
6578 /* 390 */ rRegL_rule,
6579 /* 391 */ rax_RegI_rule,
6580 /* 392 */ rax_RegI_rule,
6581 /* 393 */ rax_RegL_rule,
6582 /* 394 */ rax_RegL_rule,
6583 /* 395 */ rRegI_rule,
6584 /* 396 */ rRegI_rule,
6585 /* 397 */ rRegL_rule,
6586 /* 398 */ rRegL_rule,
6587 /* 399 */ immI_0_rule,
6588 /* 400 */ immL0_rule,
6589 /* 401 */ rax_RegI_rule,
6590 /* 402 */ rRegI_rule,
6591 /* 403 */ rax_RegL_rule,
6592 /* 404 */ rRegL_rule,
6593 /* 405 */ rRegI_rule,
6594 /* 406 */ rRegI_rule,
6595 /* 407 */ rRegI_rule,
6596 /* 408 */ rRegI_rule,
6597 /* 409 */ _AndI_rRegI_immI_rule,
6598 /* 410 */ _AndI_rRegI__LoadI_memory__rule,
6599 /* 411 */ _AndI__LoadI_memory__rRegI_rule,
6600 /* 412 */ rRegI_rule,
6601 /* 413 */ rRegI_rule,
6602 /* 414 */ rRegI_rule,
6603 /* 415 */ rRegI_rule,
6604 /* 416 */ rRegP_rule,
6605 /* 417 */ rRegP_rule,
6606 /* 418 */ rRegP_rule,
6607 /* 419 */ rRegP_rule,
6608 /* 420 */ _LoadP_memory__rule,
6609 /* 421 */ _LoadP_memory__rule,
6610 /* 422 */ rRegN_rule,
6611 /* 423 */ rRegN_rule,
6612 /* 424 */ rRegN_rule,
6613 /* 425 */ immN_rule,
6614 /* 426 */ rRegN_rule,
6615 /* 427 */ immNKlass_rule,
6616 /* 428 */ rRegN_rule,
6617 /* 429 */ _LoadN_memory__rule,
6618 /* 430 */ _LoadN_memory__rule,
6619 /* 431 */ rRegL_rule,
6620 /* 432 */ rRegL_rule,
6621 /* 433 */ rRegL_rule,
6622 /* 434 */ rRegL_rule,
6623 /* 435 */ _AndL_rRegL_immL32_rule,
6624 /* 436 */ _AndL_rRegL__LoadL_memory__rule,
6625 /* 437 */ _AndL__LoadL_memory__rRegL_rule,
6626 /* 438 */ _AndL__CastP2X_rRegP___LoadL_memory__rule,
6627 /* 439 */ _AndL__LoadL_memory___CastP2X_rRegP__rule,
6628 /* 440 */ rRegL_rule,
6629 /* 441 */ rRegL_rule,
6630 /* 442 */ rRegL_rule,
6631 /* 443 */ rRegL_rule,
6632 /* 444 */ _LoadB_memory__rule,
6633 /* 445 */ _AndI__LoadUB_memory__immU7_rule,
6634 /* 446 */ _AndI__LoadB_memory__immI8_rule,
6635 /* 447 */ _PartialSubtypeCheck_rsi_RegP_rax_RegP_rule,
6636 /* 448 */ rRegP_rule,
6637 /* 449 */ rRegP_rule,
6638 /* 450 */ rRegP_rule,
6639 /* 451 */ 0,
6640 /* 452 */ regF_rule,
6641 /* 453 */ vlRegF_rule,
6642 /* 454 */ regD_rule,
6643 /* 455 */ vlRegD_rule,
6644 /* 456 */ regF_rule,
6645 /* 457 */ vlRegF_rule,
6646 /* 458 */ regD_rule,
6647 /* 459 */ vlRegD_rule,
6648 /* 460 */ kReg_rule,
6649 /* 461 */ vec_rule,
6650 /* 462 */ vec_rule,
6651 /* 463 */ legVec_rule,
6652 /* 464 */ vec_rule,
6653 /* 465 */ _LoadVector_memory__rule,
6654 /* 466 */ vec_rule,
6655 /* 467 */ _LoadVector_memory__rule,
6656 /* 468 */ rRegI_rule,
6657 /* 469 */ rRegI_rule,
6658 /* 470 */ vec_rule,
6659 /* 471 */ vec_rule,
6660 /* 472 */ vec_rule,
6661 /* 473 */ vec_rule,
6662 /* 474 */ vec_rule,
6663 /* 475 */ vec_rule,
6664 /* 476 */ vec_rule,
6665 /* 477 */ vec_rule,
6666 /* 478 */ vec_rule,
6667 /* 479 */ vec_rule,
6668 /* 480 */ _VectorTest_legVec_legVec_rule,
6669 /* 481 */ _VectorTest_legVec_legVec_rule,
6670 /* 482 */ _VectorTest_kReg_kReg_rule,
6671 /* 483 */ kReg_rule,
6672 /* 484 */ vec_rule,
6673 /* 485 */ vec_rule,
6674 /* 486 */ vec_rule,
6675 /* 487 */ vec_rule,
6676 /* 488 */ vec_rule,
6677 /* 489 */ vec_rule,
6678 /* 490 */ rRegL_rule,
6679 /* 491 */ kReg_rule,
6680 /* 492 */ vec_rule,
6681 /* 493 */ legVec_rule,
6682 /* 494 */ memory_rule,
6683 /* 495 */ _LoadB_memory__rule,
6684 /* 496 */ memory_rule,
6685 /* 497 */ _LoadUB_memory__rule,
6686 /* 498 */ _AndI__LoadUB_memory__immI_rule,
6687 /* 499 */ memory_rule,
6688 /* 500 */ _LShiftI__LoadS_memory__immI_24_rule,
6689 /* 501 */ _LoadS_memory__rule,
6690 /* 502 */ memory_rule,
6691 /* 503 */ _LShiftI__LoadUS_memory__immI_24_rule,
6692 /* 504 */ _LoadUS_memory__rule,
6693 /* 505 */ _AndI__LoadUS_memory__immI_255_rule,
6694 /* 506 */ _AndI__LoadUS_memory__immI_rule,
6695 /* 507 */ memory_rule,
6696 /* 508 */ _LShiftI__LoadI_memory__immI_24_rule,
6697 /* 509 */ _LoadI_memory__rule,
6698 /* 510 */ _LShiftI__LoadI_memory__immI_16_rule,
6699 /* 511 */ _LoadI_memory__rule,
6700 /* 512 */ _LoadI_memory__rule,
6701 /* 513 */ _AndI__LoadI_memory__immI_255_rule,
6702 /* 514 */ _AndI__LoadI_memory__immI_65535_rule,
6703 /* 515 */ _AndI__LoadI_memory__immU31_rule,
6704 /* 516 */ _ConvI2L__LoadI_memory___rule,
6705 /* 517 */ memory_rule,
6706 /* 518 */ memory_rule,
6707 /* 519 */ memory_rule,
6708 /* 520 */ memory_rule,
6709 /* 521 */ memory_rule,
6710 /* 522 */ memory_rule,
6711 /* 523 */ memory_rule,
6712 /* 524 */ memory_rule,
6713 /* 525 */ memory_rule,
6714 /* 526 */ legRegF_rule,
6715 /* 527 */ legRegF_rule,
6716 /* 528 */ legRegD_rule,
6717 /* 529 */ legRegD_rule,
6718 /* 530 */ legRegF_rule,
6719 /* 531 */ legRegF_rule,
6720 /* 532 */ legRegD_rule,
6721 /* 533 */ legRegD_rule,
6722 /* 534 */ memory_rule,
6723 /* 535 */ memory_rule,
6724 /* 536 */ memory_rule,
6725 /* 537 */ memory_rule,
6726 /* 538 */ memory_rule,
6727 /* 539 */ memory_rule,
6728 /* 540 */ memory_rule,
6729 /* 541 */ memory_rule,
6730 /* 542 */ memory_rule,
6731 /* 543 */ memory_rule,
6732 /* 544 */ memory_rule,
6733 /* 545 */ memory_rule,
6734 /* 546 */ memory_rule,
6735 /* 547 */ memory_rule,
6736 /* 548 */ memory_rule,
6737 /* 549 */ memory_rule,
6738 /* 550 */ memory_rule,
6739 /* 551 */ memory_rule,
6740 /* 552 */ memory_rule,
6741 /* 553 */ memory_rule,
6742 /* 554 */ memory_rule,
6743 /* 555 */ memory_rule,
6744 /* 556 */ memory_rule,
6745 /* 557 */ memory_rule,
6746 /* 558 */ memory_rule,
6747 /* 559 */ memory_rule,
6748 /* 560 */ memory_rule,
6749 /* 561 */ memory_rule,
6750 /* 562 */ memory_rule,
6751 /* 563 */ memory_rule,
6752 /* 564 */ memory_rule,
6753 /* 565 */ memory_rule,
6754 /* 566 */ indirect_rule,
6755 /* 567 */ 0,
6756 /* 568 */ 0,
6757 /* 569 */ rRegI_rule,
6758 /* 570 */ rRegL_rule,
6759 /* 571 */ rRegI_rule,
6760 /* 572 */ rRegI_rule,
6761 /* 573 */ rRegI_rule,
6762 /* 574 */ rRegI_rule,
6763 /* 575 */ rRegL_rule,
6764 /* 576 */ rRegL_rule,
6765 /* 577 */ rRegI_rule,
6766 /* 578 */ rRegI_rule,
6767 /* 579 */ rRegL_rule,
6768 /* 580 */ rRegL_rule,
6769 /* 581 */ rRegI_rule,
6770 /* 582 */ _LoadI_memory__rule,
6771 /* 583 */ rRegL_rule,
6772 /* 584 */ _LoadL_memory__rule,
6773 /* 585 */ 0,
6774 /* 586 */ 0,
6775 /* 587 */ 0,
6776 /* 588 */ 0,
6777 /* 589 */ 0,
6778 /* 590 */ 0,
6779 /* 591 */ 0,
6780 /* 592 */ 0,
6781 /* 593 */ 0,
6782 /* 594 */ _CastP2X_rRegP__rule,
6783 /* 595 */ _CastP2X__DecodeN_rRegN___rule,
6784 /* 596 */ rRegP_rule,
6785 /* 597 */ rRegP_rule,
6786 /* 598 */ rRegN_rule,
6787 /* 599 */ rRegN_rule,
6788 /* 600 */ rRegP_rule,
6789 /* 601 */ rRegN_rule,
6790 /* 602 */ _LShiftL_rRegL_immI2_rule,
6791 /* 603 */ _AddL__LShiftL_rRegL_immI2_immL32_rule,
6792 /* 604 */ rRegL_rule,
6793 /* 605 */ _Binary_cmpOp_rFlagsReg_rule,
6794 /* 606 */ _Binary_cmpOpU_rFlagsRegU_rule,
6795 /* 607 */ _Binary_cmpOpUCF_rFlagsRegUCF_rule,
6796 /* 608 */ _Binary_cmpOp_rFlagsReg_rule,
6797 /* 609 */ _Binary_cmpOpU_rFlagsRegU_rule,
6798 /* 610 */ _Binary_cmpOpUCF_rFlagsRegUCF_rule,
6799 /* 611 */ _Binary_cmpOp_rFlagsReg_rule,
6800 /* 612 */ _Binary_cmpOpU_rFlagsRegU_rule,
6801 /* 613 */ _Binary_cmpOpUCF_rFlagsRegUCF_rule,
6802 /* 614 */ _Binary_cmpOp_rFlagsReg_rule,
6803 /* 615 */ _Binary_cmpOpU_rFlagsRegU_rule,
6804 /* 616 */ _Binary_cmpOpUCF_rFlagsRegUCF_rule,
6805 /* 617 */ _Binary_cmpOp_rFlagsReg_rule,
6806 /* 618 */ _Binary_cmpOp_rFlagsReg_rule,
6807 /* 619 */ _Binary_cmpOpU_rFlagsRegU_rule,
6808 /* 620 */ _Binary_cmpOpUCF_rFlagsRegUCF_rule,
6809 /* 621 */ _Binary_cmpOpU_rFlagsRegU_rule,
6810 /* 622 */ _Binary_cmpOpUCF_rFlagsRegUCF_rule,
6811 /* 623 */ _Binary_cmpOp_rFlagsReg_rule,
6812 /* 624 */ _Binary_cmpOpU_rFlagsRegU_rule,
6813 /* 625 */ _Binary_cmpOpUCF_rFlagsRegUCF_rule,
6814 /* 626 */ _Binary_cmpOp_rFlagsReg_rule,
6815 /* 627 */ _Binary_cmpOpU_rFlagsRegU_rule,
6816 /* 628 */ _Binary_cmpOpUCF_rFlagsRegUCF_rule,
6817 /* 629 */ rRegI_rule,
6818 /* 630 */ rRegI_rule,
6819 /* 631 */ rRegI_rule,
6820 /* 632 */ _LoadI_memory__rule,
6821 /* 633 */ memory_rule,
6822 /* 634 */ memory_rule,
6823 /* 635 */ memory_rule,
6824 /* 636 */ rRegI_rule,
6825 /* 637 */ memory_rule,
6826 /* 638 */ rRegI_rule,
6827 /* 639 */ memory_rule,
6828 /* 640 */ rRegI_rule,
6829 /* 641 */ rRegL_rule,
6830 /* 642 */ rRegL_rule,
6831 /* 643 */ rRegL_rule,
6832 /* 644 */ _LoadL_memory__rule,
6833 /* 645 */ memory_rule,
6834 /* 646 */ memory_rule,
6835 /* 647 */ memory_rule,
6836 /* 648 */ rRegI_rule,
6837 /* 649 */ memory_rule,
6838 /* 650 */ rRegL_rule,
6839 /* 651 */ memory_rule,
6840 /* 652 */ rRegL_rule,
6841 /* 653 */ rRegP_rule,
6842 /* 654 */ rRegP_rule,
6843 /* 655 */ rRegP_rule,
6844 /* 656 */ memory_rule,
6845 /* 657 */ memory_rule,
6846 /* 658 */ memory_rule,
6847 /* 659 */ memory_rule,
6848 /* 660 */ memory_rule,
6849 /* 661 */ memory_rule,
6850 /* 662 */ memory_rule,
6851 /* 663 */ memory_rule,
6852 /* 664 */ memory_rule,
6853 /* 665 */ memory_rule,
6854 /* 666 */ memory_rule,
6855 /* 667 */ memory_rule,
6856 /* 668 */ memory_rule,
6857 /* 669 */ memory_rule,
6858 /* 670 */ memory_rule,
6859 /* 671 */ memory_rule,
6860 /* 672 */ memory_rule,
6861 /* 673 */ memory_rule,
6862 /* 674 */ memory_rule,
6863 /* 675 */ memory_rule,
6864 /* 676 */ memory_rule,
6865 /* 677 */ memory_rule,
6866 /* 678 */ memory_rule,
6867 /* 679 */ memory_rule,
6868 /* 680 */ memory_rule,
6869 /* 681 */ memory_rule,
6870 /* 682 */ memory_rule,
6871 /* 683 */ memory_rule,
6872 /* 684 */ memory_rule,
6873 /* 685 */ memory_rule,
6874 /* 686 */ memory_rule,
6875 /* 687 */ memory_rule,
6876 /* 688 */ memory_rule,
6877 /* 689 */ rRegI_rule,
6878 /* 690 */ rRegL_rule,
6879 /* 691 */ rRegI_rule,
6880 /* 692 */ rRegI_rule,
6881 /* 693 */ rRegI_rule,
6882 /* 694 */ memory_rule,
6883 /* 695 */ memory_rule,
6884 /* 696 */ rRegL_rule,
6885 /* 697 */ rRegI_rule,
6886 /* 698 */ rRegL_rule,
6887 /* 699 */ memory_rule,
6888 /* 700 */ memory_rule,
6889 /* 701 */ rRegP_rule,
6890 /* 702 */ immI_0_rule,
6891 /* 703 */ rRegI_rule,
6892 /* 704 */ memory_rule,
6893 /* 705 */ immL0_rule,
6894 /* 706 */ rRegL_rule,
6895 /* 707 */ memory_rule,
6896 /* 708 */ rRegI_rule,
6897 /* 709 */ rRegI_rule,
6898 /* 710 */ rRegI_rule,
6899 /* 711 */ _LoadI_memory__rule,
6900 /* 712 */ _LoadI_memory__rule,
6901 /* 713 */ _Binary_rRegI_rRegI_rule,
6902 /* 714 */ rRegL_rule,
6903 /* 715 */ rRegL_rule,
6904 /* 716 */ rRegL_rule,
6905 /* 717 */ _LoadL_memory__rule,
6906 /* 718 */ _LoadL_memory__rule,
6907 /* 719 */ no_rax_RegL_rule,
6908 /* 720 */ no_rax_RegL_rule,
6909 /* 721 */ rax_RegI_rule,
6910 /* 722 */ rax_RegL_rule,
6911 /* 723 */ rax_RegI_rule,
6912 /* 724 */ rax_RegL_rule,
6913 /* 725 */ 0,
6914 /* 726 */ 0,
6915 /* 727 */ 0,
6916 /* 728 */ 0,
6917 /* 729 */ no_rax_RegL_rule,
6918 /* 730 */ rax_RegI_rule,
6919 /* 731 */ rax_RegL_rule,
6920 /* 732 */ rRegI_rule,
6921 /* 733 */ memory_rule,
6922 /* 734 */ rRegI_rule,
6923 /* 735 */ memory_rule,
6924 /* 736 */ rRegI_rule,
6925 /* 737 */ memory_rule,
6926 /* 738 */ rRegI_rule,
6927 /* 739 */ memory_rule,
6928 /* 740 */ rRegI_rule,
6929 /* 741 */ memory_rule,
6930 /* 742 */ rRegI_rule,
6931 /* 743 */ memory_rule,
6932 /* 744 */ rRegI_rule,
6933 /* 745 */ memory_rule,
6934 /* 746 */ rRegI_rule,
6935 /* 747 */ memory_rule,
6936 /* 748 */ rRegI_rule,
6937 /* 749 */ memory_rule,
6938 /* 750 */ rRegL_rule,
6939 /* 751 */ memory_rule,
6940 /* 752 */ rRegL_rule,
6941 /* 753 */ memory_rule,
6942 /* 754 */ rRegL_rule,
6943 /* 755 */ memory_rule,
6944 /* 756 */ rRegL_rule,
6945 /* 757 */ memory_rule,
6946 /* 758 */ rRegL_rule,
6947 /* 759 */ memory_rule,
6948 /* 760 */ rRegL_rule,
6949 /* 761 */ memory_rule,
6950 /* 762 */ rRegL_rule,
6951 /* 763 */ memory_rule,
6952 /* 764 */ rRegL_rule,
6953 /* 765 */ memory_rule,
6954 /* 766 */ rRegL_rule,
6955 /* 767 */ memory_rule,
6956 /* 768 */ _LShiftI_rRegI_immI_24_rule,
6957 /* 769 */ _LShiftI_rRegI_immI_16_rule,
6958 /* 770 */ rRegI_rule,
6959 /* 771 */ rRegI_rule,
6960 /* 772 */ rRegI_rule,
6961 /* 773 */ rRegI_rule,
6962 /* 774 */ rRegI_rule,
6963 /* 775 */ rRegL_rule,
6964 /* 776 */ rRegL_rule,
6965 /* 777 */ rRegL_rule,
6966 /* 778 */ rRegL_rule,
6967 /* 779 */ rRegL_rule,
6968 /* 780 */ rRegI_rule,
6969 /* 781 */ rRegI_rule,
6970 /* 782 */ _AndI_rRegI_immI_255_rule,
6971 /* 783 */ rRegI_rule,
6972 /* 784 */ _AndI_rRegI_immI_65535_rule,
6973 /* 785 */ _AndI_rRegI_immI_Pow2M1_rule,
6974 /* 786 */ rRegI_rule,
6975 /* 787 */ rRegI_rule,
6976 /* 788 */ _LoadI_memory__rule,
6977 /* 789 */ memory_rule,
6978 /* 790 */ memory_rule,
6979 /* 791 */ memory_rule,
6980 /* 792 */ memory_rule,
6981 /* 793 */ memory_rule,
6982 /* 794 */ _XorI_rRegI_immI_M1_rule,
6983 /* 795 */ _LoadI_memory__rule,
6984 /* 796 */ _XorI_rRegI_immI_M1_rule,
6985 /* 797 */ rRegI_rule,
6986 /* 798 */ _SubI_immI_0_rRegI_rule,
6987 /* 799 */ rRegI_rule,
6988 /* 800 */ _SubI_immI_0__LoadI_memory__rule,
6989 /* 801 */ _LoadI_memory__rule,
6990 /* 802 */ _AddI__LoadI_memory__immI_M1_rule,
6991 /* 803 */ _LoadI_memory__rule,
6992 /* 804 */ _AddI_rRegI_immI_M1_rule,
6993 /* 805 */ rRegI_rule,
6994 /* 806 */ _AddI_rRegI_immI_M1_rule,
6995 /* 807 */ rRegI_rule,
6996 /* 808 */ _AddI__LoadI_memory__immI_M1_rule,
6997 /* 809 */ _LoadI_memory__rule,
6998 /* 810 */ rRegI_rule,
6999 /* 811 */ rRegI_rule,
7000 /* 812 */ rRegI_rule,
7001 /* 813 */ _LoadI_memory__rule,
7002 /* 814 */ memory_rule,
7003 /* 815 */ memory_rule,
7004 /* 816 */ memory_rule,
7005 /* 817 */ memory_rule,
7006 /* 818 */ memory_rule,
7007 /* 819 */ rRegI_rule,
7008 /* 820 */ rRegI_rule,
7009 /* 821 */ rRegI_rule,
7010 /* 822 */ rRegI_rule,
7011 /* 823 */ _LoadI_memory__rule,
7012 /* 824 */ memory_rule,
7013 /* 825 */ memory_rule,
7014 /* 826 */ memory_rule,
7015 /* 827 */ memory_rule,
7016 /* 828 */ memory_rule,
7017 /* 829 */ rRegL_rule,
7018 /* 830 */ rRegL_rule,
7019 /* 831 */ rRegL_rule,
7020 /* 832 */ rRegL_rule,
7021 /* 833 */ rRegL_rule,
7022 /* 834 */ _LoadL_memory__rule,
7023 /* 835 */ memory_rule,
7024 /* 836 */ memory_rule,
7025 /* 837 */ memory_rule,
7026 /* 838 */ memory_rule,
7027 /* 839 */ _XorL_rRegL_immL_M1_rule,
7028 /* 840 */ _LoadL_memory__rule,
7029 /* 841 */ _XorL_rRegL_immL_M1_rule,
7030 /* 842 */ rRegL_rule,
7031 /* 843 */ _SubL_immL0_rRegL_rule,
7032 /* 844 */ rRegL_rule,
7033 /* 845 */ _SubL_immL0__LoadL_memory__rule,
7034 /* 846 */ _LoadL_memory__rule,
7035 /* 847 */ _AddL__LoadL_memory__immL_M1_rule,
7036 /* 848 */ _LoadL_memory__rule,
7037 /* 849 */ _AddL_rRegL_immL_M1_rule,
7038 /* 850 */ rRegL_rule,
7039 /* 851 */ _AddL_rRegL_immL_M1_rule,
7040 /* 852 */ rRegL_rule,
7041 /* 853 */ _AddL__LoadL_memory__immL_M1_rule,
7042 /* 854 */ _LoadL_memory__rule,
7043 /* 855 */ rRegL_rule,
7044 /* 856 */ rRegL_rule,
7045 /* 857 */ _CastP2X_any_RegP__rule,
7046 /* 858 */ rRegL_rule,
7047 /* 859 */ rRegL_rule,
7048 /* 860 */ _LoadL_memory__rule,
7049 /* 861 */ memory_rule,
7050 /* 862 */ memory_rule,
7051 /* 863 */ memory_rule,
7052 /* 864 */ memory_rule,
7053 /* 865 */ rRegL_rule,
7054 /* 866 */ rRegL_rule,
7055 /* 867 */ rRegL_rule,
7056 /* 868 */ rRegL_rule,
7057 /* 869 */ _LoadL_memory__rule,
7058 /* 870 */ memory_rule,
7059 /* 871 */ memory_rule,
7060 /* 872 */ memory_rule,
7061 /* 873 */ rRegI_rule,
7062 /* 874 */ rRegP_rule,
7063 /* 875 */ rRegI_rule,
7064 /* 876 */ rRegI_rule,
7065 /* 877 */ _AndI__CmpLTMask_rRegI_rRegI_rRegI_rule,
7066 /* 878 */ _SubI_rRegI_rRegI_rule,
7067 /* 879 */ _AndI_rRegI__CmpLTMask_rRegI_rRegI_rule,
7068 /* 880 */ _SubI_rRegI_rRegI_rule,
7069 /* 881 */ _CmpLTMask_rRegI_rRegI_rule,
7070 /* 882 */ rRegI_rule,
7071 /* 883 */ regF_rule,
7072 /* 884 */ regF_rule,
7073 /* 885 */ regF_rule,
7074 /* 886 */ regD_rule,
7075 /* 887 */ regD_rule,
7076 /* 888 */ regD_rule,
7077 /* 889 */ regF_rule,
7078 /* 890 */ _LoadF_memory__rule,
7079 /* 891 */ regD_rule,
7080 /* 892 */ _LoadD_memory__rule,
7081 /* 893 */ regF_rule,
7082 /* 894 */ regF_rule,
7083 /* 895 */ regD_rule,
7084 /* 896 */ regD_rule,
7085 /* 897 */ rRegI_rule,
7086 /* 898 */ _LoadI_memory__rule,
7087 /* 899 */ rRegI_rule,
7088 /* 900 */ _LoadI_memory__rule,
7089 /* 901 */ rRegI_rule,
7090 /* 902 */ rRegI_rule,
7091 /* 903 */ rRegL_rule,
7092 /* 904 */ _LoadL_memory__rule,
7093 /* 905 */ rRegL_rule,
7094 /* 906 */ _LoadL_memory__rule,
7095 /* 907 */ rRegI_rule,
7096 /* 908 */ _ConvI2L_rRegI__rule,
7097 /* 909 */ _ConvI2L__LoadI_memory___rule,
7098 /* 910 */ rRegL_rule,
7099 /* 911 */ rRegL_rule,
7100 /* 912 */ regF_rule,
7101 /* 913 */ rRegI_rule,
7102 /* 914 */ regD_rule,
7103 /* 915 */ rRegL_rule,
7104 /* 916 */ rcx_RegL_rule,
7105 /* 917 */ rcx_RegL_rule,
7106 /* 918 */ rcx_RegL_rule,
7107 /* 919 */ rcx_RegL_rule,
7108 /* 920 */ immL_rule,
7109 /* 921 */ _Binary_rdi_RegP_rcx_RegI_rule,
7110 /* 922 */ _Binary_rdi_RegP_rcx_RegI_rule,
7111 /* 923 */ _Binary_rdi_RegP_rcx_RegI_rule,
7112 /* 924 */ _Binary_rdi_RegP_rcx_RegI_rule,
7113 /* 925 */ _Binary_rdi_RegP_rcx_RegI_rule,
7114 /* 926 */ _Binary_rdi_RegP_rcx_RegI_rule,
7115 /* 927 */ _Binary_rsi_RegP_rdx_RegI_rule,
7116 /* 928 */ _Binary_rsi_RegP_rdx_RegI_rule,
7117 /* 929 */ _Binary_rdi_RegP_rdx_RegI_rule,
7118 /* 930 */ _Binary_rdi_RegP_rdx_RegI_rule,
7119 /* 931 */ _Binary_rdi_RegP_rdx_RegI_rule,
7120 /* 932 */ _Binary_rdi_RegP_rdx_RegI_rule,
7121 /* 933 */ _Binary_rdi_RegP_rdx_RegI_rule,
7122 /* 934 */ _Binary_rdi_RegP_rdx_RegI_rule,
7123 /* 935 */ _Binary_rdi_RegP_rdx_RegI_rule,
7124 /* 936 */ _Binary_rdi_RegP_rdx_RegI_rule,
7125 /* 937 */ _Binary_rdi_RegP_rsi_RegP_rule,
7126 /* 938 */ _Binary_rdi_RegP_rsi_RegP_rule,
7127 /* 939 */ rdi_RegP_rule,
7128 /* 940 */ rdi_RegP_rule,
7129 /* 941 */ rdi_RegP_rule,
7130 /* 942 */ rdi_RegP_rule,
7131 /* 943 */ rsi_RegP_rule,
7132 /* 944 */ rsi_RegP_rule,
7133 /* 945 */ rsi_RegP_rule,
7134 /* 946 */ rsi_RegP_rule,
7135 /* 947 */ rsi_RegP_rule,
7136 /* 948 */ rsi_RegP_rule,
7137 /* 949 */ rsi_RegP_rule,
7138 /* 950 */ rsi_RegP_rule,
7139 /* 951 */ rRegL_rule,
7140 /* 952 */ 0,
7141 /* 953 */ rRegI_rule,
7142 /* 954 */ 0,
7143 /* 955 */ rRegI_rule,
7144 /* 956 */ 0,
7145 /* 957 */ cmpOp_rule,
7146 /* 958 */ cmpOp_rule,
7147 /* 959 */ cmpOpU_rule,
7148 /* 960 */ cmpOpUCF_rule,
7149 /* 961 */ cmpOp_rule,
7150 /* 962 */ cmpOpU_rule,
7151 /* 963 */ cmpOpUCF_rule,
7152 /* 964 */ cmpOpU_rule,
7153 /* 965 */ cmpOpUCF_rule,
7154 /* 966 */ cmpOpUCF2_rule,
7155 /* 967 */ rsi_RegP_rule,
7156 /* 968 */ 0,
7157 /* 969 */ cmpOp_rule,
7158 /* 970 */ cmpOp_rule,
7159 /* 971 */ cmpOpU_rule,
7160 /* 972 */ cmpOpUCF_rule,
7161 /* 973 */ cmpOpU_rule,
7162 /* 974 */ cmpOpUCF_rule,
7163 /* 975 */ cmpOpUCF2_rule,
7164 /* 976 */ rRegP_rule,
7165 /* 977 */ 0,
7166 /* 978 */ 0,
7167 /* 979 */ 0,
7168 /* 980 */ 0,
7169 /* 981 */ 0,
7170 /* 982 */ 0,
7171 /* 983 */ 0,
7172 /* 984 */ 0,
7173 /* 985 */ no_rbp_RegP_rule,
7174 /* 986 */ no_rbp_RegP_rule,
7175 /* 987 */ 0,
7176 /* 988 */ 0,
7177 /* 989 */ 0,
7178 /* 990 */ rRegI_rule,
7179 /* 991 */ regF_rule,
7180 /* 992 */ regF_rule,
7181 /* 993 */ _LoadF_memory__rule,
7182 /* 994 */ regF_rule,
7183 /* 995 */ regF_rule,
7184 /* 996 */ regF_rule,
7185 /* 997 */ _LoadF_memory__rule,
7186 /* 998 */ regF_rule,
7187 /* 999 */ regD_rule,
7188 /* 1000 */ regD_rule,
7189 /* 1001 */ _LoadD_memory__rule,
7190 /* 1002 */ regD_rule,
7191 /* 1003 */ regD_rule,
7192 /* 1004 */ regD_rule,
7193 /* 1005 */ _LoadD_memory__rule,
7194 /* 1006 */ regD_rule,
7195 /* 1007 */ regF_rule,
7196 /* 1008 */ regF_rule,
7197 /* 1009 */ regF_rule,
7198 /* 1010 */ regF_rule,
7199 /* 1011 */ regF_rule,
7200 /* 1012 */ regF_rule,
7201 /* 1013 */ regD_rule,
7202 /* 1014 */ regD_rule,
7203 /* 1015 */ regD_rule,
7204 /* 1016 */ regD_rule,
7205 /* 1017 */ regD_rule,
7206 /* 1018 */ regD_rule,
7207 /* 1019 */ regF_rule,
7208 /* 1020 */ regF_rule,
7209 /* 1021 */ _LoadF_memory__rule,
7210 /* 1022 */ regF_rule,
7211 /* 1023 */ regF_rule,
7212 /* 1024 */ regF_rule,
7213 /* 1025 */ _LoadF_memory__rule,
7214 /* 1026 */ regF_rule,
7215 /* 1027 */ regD_rule,
7216 /* 1028 */ regD_rule,
7217 /* 1029 */ _LoadD_memory__rule,
7218 /* 1030 */ regD_rule,
7219 /* 1031 */ regD_rule,
7220 /* 1032 */ regD_rule,
7221 /* 1033 */ _LoadD_memory__rule,
7222 /* 1034 */ regD_rule,
7223 /* 1035 */ regF_rule,
7224 /* 1036 */ regF_rule,
7225 /* 1037 */ regF_rule,
7226 /* 1038 */ regF_rule,
7227 /* 1039 */ regF_rule,
7228 /* 1040 */ regF_rule,
7229 /* 1041 */ regD_rule,
7230 /* 1042 */ regD_rule,
7231 /* 1043 */ regD_rule,
7232 /* 1044 */ regD_rule,
7233 /* 1045 */ regD_rule,
7234 /* 1046 */ regD_rule,
7235 /* 1047 */ regF_rule,
7236 /* 1048 */ regD_rule,
7237 /* 1049 */ kReg_rule,
7238 /* 1050 */ kReg_rule,
7239 /* 1051 */ kReg_rule,
7240 /* 1052 */ vec_rule,
7241 /* 1053 */ vec_rule,
7242 /* 1054 */ legRegD_rule,
7243 /* 1055 */ _LoadD_memory__rule,
7244 /* 1056 */ immD_rule,
7245 /* 1057 */ legVec_rule,
7246 /* 1058 */ vec_rule,
7247 /* 1059 */ _LoadVector_memory__rule,
7248 /* 1060 */ _LoadVector_memory__rule,
7249 /* 1061 */ 0,
7250 /* 1062 */ regD_rule,
7251 /* 1063 */ regF_rule,
7252 /* 1064 */ memory_rule,
7253 /* 1065 */ memory_rule,
7254 /* 1066 */ memory_rule,
7255 /* 1067 */ memory_rule,
7256 /* 1068 */ memory_rule,
7257 /* 1069 */ memory_rule,
7258 /* 1070 */ memory_rule,
7259 /* 1071 */ rRegI_rule,
7260 /* 1072 */ _LoadB_memory__rule,
7261 /* 1073 */ immI_rule,
7262 /* 1074 */ immI_0_rule,
7263 /* 1075 */ rRegI_rule,
7264 /* 1076 */ _LoadS_memory__rule,
7265 /* 1077 */ immI_rule,
7266 /* 1078 */ immI_0_rule,
7267 /* 1079 */ rRegI_rule,
7268 /* 1080 */ _LoadI_memory__rule,
7269 /* 1081 */ immI_rule,
7270 /* 1082 */ immI_0_rule,
7271 /* 1083 */ immI_M1_rule,
7272 /* 1084 */ immI_M1_rule,
7273 /* 1085 */ immI_M1_rule,
7274 /* 1086 */ rRegL_rule,
7275 /* 1087 */ _LoadL_memory__rule,
7276 /* 1088 */ immL_rule,
7277 /* 1089 */ immL0_rule,
7278 /* 1090 */ immL_M1_rule,
7279 /* 1091 */ vlRegF_rule,
7280 /* 1092 */ _LoadF_memory__rule,
7281 /* 1093 */ immF0_rule,
7282 /* 1094 */ vlRegD_rule,
7283 /* 1095 */ _LoadD_memory__rule,
7284 /* 1096 */ immD0_rule,
7285 /* 1097 */ _Binary_vec_rRegI_rule,
7286 /* 1098 */ _Binary_vec_rRegI_rule,
7287 /* 1099 */ _Binary_vec_rRegI_rule,
7288 /* 1100 */ _Binary_vec_rRegL_rule,
7289 /* 1101 */ _Binary_vec_rRegL_rule,
7290 /* 1102 */ _Binary_vec_rRegL_rule,
7291 /* 1103 */ _Binary_vec_regF_rule,
7292 /* 1104 */ _Binary_vec_regF_rule,
7293 /* 1105 */ _Binary_vec_regD_rule,
7294 /* 1106 */ _Binary_vec_regD_rule,
7295 /* 1107 */ _Binary_vec_regD_rule,
7296 /* 1108 */ rRegI_rule,
7297 /* 1109 */ rRegI_rule,
7298 /* 1110 */ rRegI_rule,
7299 /* 1111 */ rRegI_rule,
7300 /* 1112 */ rRegI_rule,
7301 /* 1113 */ rRegI_rule,
7302 /* 1114 */ rRegI_rule,
7303 /* 1115 */ rRegL_rule,
7304 /* 1116 */ rRegL_rule,
7305 /* 1117 */ rRegL_rule,
7306 /* 1118 */ rRegL_rule,
7307 /* 1119 */ rRegL_rule,
7308 /* 1120 */ rRegL_rule,
7309 /* 1121 */ rRegL_rule,
7310 /* 1122 */ rRegL_rule,
7311 /* 1123 */ rRegL_rule,
7312 /* 1124 */ rRegL_rule,
7313 /* 1125 */ rRegL_rule,
7314 /* 1126 */ rRegL_rule,
7315 /* 1127 */ rRegL_rule,
7316 /* 1128 */ rRegL_rule,
7317 /* 1129 */ regF_rule,
7318 /* 1130 */ regF_rule,
7319 /* 1131 */ regF_rule,
7320 /* 1132 */ regF_rule,
7321 /* 1133 */ regF_rule,
7322 /* 1134 */ regF_rule,
7323 /* 1135 */ regD_rule,
7324 /* 1136 */ regD_rule,
7325 /* 1137 */ regD_rule,
7326 /* 1138 */ regD_rule,
7327 /* 1139 */ regD_rule,
7328 /* 1140 */ regD_rule,
7329 /* 1141 */ rRegI_rule,
7330 /* 1142 */ rRegI_rule,
7331 /* 1143 */ rRegI_rule,
7332 /* 1144 */ rRegI_rule,
7333 /* 1145 */ rRegI_rule,
7334 /* 1146 */ rRegI_rule,
7335 /* 1147 */ rRegI_rule,
7336 /* 1148 */ rRegI_rule,
7337 /* 1149 */ rRegI_rule,
7338 /* 1150 */ rRegI_rule,
7339 /* 1151 */ rRegI_rule,
7340 /* 1152 */ rRegI_rule,
7341 /* 1153 */ rRegI_rule,
7342 /* 1154 */ rRegI_rule,
7343 /* 1155 */ rRegI_rule,
7344 /* 1156 */ rRegI_rule,
7345 /* 1157 */ rRegI_rule,
7346 /* 1158 */ rRegI_rule,
7347 /* 1159 */ rRegI_rule,
7348 /* 1160 */ rRegI_rule,
7349 /* 1161 */ rRegI_rule,
7350 /* 1162 */ immF_rule,
7351 /* 1163 */ immF_rule,
7352 /* 1164 */ immF_rule,
7353 /* 1165 */ immF_rule,
7354 /* 1166 */ legRegF_rule,
7355 /* 1167 */ legRegF_rule,
7356 /* 1168 */ legRegF_rule,
7357 /* 1169 */ legRegF_rule,
7358 /* 1170 */ immD_rule,
7359 /* 1171 */ immD_rule,
7360 /* 1172 */ immD_rule,
7361 /* 1173 */ immD_rule,
7362 /* 1174 */ legRegD_rule,
7363 /* 1175 */ legRegD_rule,
7364 /* 1176 */ legRegD_rule,
7365 /* 1177 */ legRegD_rule,
7366 /* 1178 */ vec_rule,
7367 /* 1179 */ vec_rule,
7368 /* 1180 */ vec_rule,
7369 /* 1181 */ _LoadVector_memory__rule,
7370 /* 1182 */ vec_rule,
7371 /* 1183 */ vec_rule,
7372 /* 1184 */ vec_rule,
7373 /* 1185 */ _LoadVector_memory__rule,
7374 /* 1186 */ vec_rule,
7375 /* 1187 */ vec_rule,
7376 /* 1188 */ vec_rule,
7377 /* 1189 */ _LoadVector_memory__rule,
7378 /* 1190 */ vec_rule,
7379 /* 1191 */ vec_rule,
7380 /* 1192 */ vec_rule,
7381 /* 1193 */ _LoadVector_memory__rule,
7382 /* 1194 */ vec_rule,
7383 /* 1195 */ vec_rule,
7384 /* 1196 */ vec_rule,
7385 /* 1197 */ _LoadVector_memory__rule,
7386 /* 1198 */ vec_rule,
7387 /* 1199 */ vec_rule,
7388 /* 1200 */ vec_rule,
7389 /* 1201 */ _LoadVector_memory__rule,
7390 /* 1202 */ vec_rule,
7391 /* 1203 */ vec_rule,
7392 /* 1204 */ vec_rule,
7393 /* 1205 */ vec_rule,
7394 /* 1206 */ vec_rule,
7395 /* 1207 */ vec_rule,
7396 /* 1208 */ vec_rule,
7397 /* 1209 */ vec_rule,
7398 /* 1210 */ vec_rule,
7399 /* 1211 */ vec_rule,
7400 /* 1212 */ vec_rule,
7401 /* 1213 */ vec_rule,
7402 /* 1214 */ vec_rule,
7403 /* 1215 */ vec_rule,
7404 /* 1216 */ vec_rule,
7405 /* 1217 */ vec_rule,
7406 /* 1218 */ vec_rule,
7407 /* 1219 */ vec_rule,
7408 /* 1220 */ vec_rule,
7409 /* 1221 */ vec_rule,
7410 /* 1222 */ vec_rule,
7411 /* 1223 */ vec_rule,
7412 /* 1224 */ vec_rule,
7413 /* 1225 */ vec_rule,
7414 /* 1226 */ vec_rule,
7415 /* 1227 */ vec_rule,
7416 /* 1228 */ _LoadVector_memory__rule,
7417 /* 1229 */ vec_rule,
7418 /* 1230 */ vec_rule,
7419 /* 1231 */ vec_rule,
7420 /* 1232 */ _LoadVector_memory__rule,
7421 /* 1233 */ vec_rule,
7422 /* 1234 */ vec_rule,
7423 /* 1235 */ _LoadVector_memory__rule,
7424 /* 1236 */ vec_rule,
7425 /* 1237 */ vec_rule,
7426 /* 1238 */ vec_rule,
7427 /* 1239 */ vec_rule,
7428 /* 1240 */ vec_rule,
7429 /* 1241 */ _LoadVector_memory__rule,
7430 /* 1242 */ vec_rule,
7431 /* 1243 */ vec_rule,
7432 /* 1244 */ vec_rule,
7433 /* 1245 */ _LoadVector_memory__rule,
7434 /* 1246 */ _Binary_cmpOp_vcmppd_immI8_rule,
7435 /* 1247 */ _Binary_cmpOp_vcmppd_immI8_rule,
7436 /* 1248 */ vec_rule,
7437 /* 1249 */ vec_rule,
7438 /* 1250 */ vec_rule,
7439 /* 1251 */ vec_rule,
7440 /* 1252 */ vec_rule,
7441 /* 1253 */ vec_rule,
7442 /* 1254 */ vec_rule,
7443 /* 1255 */ vec_rule,
7444 /* 1256 */ vec_rule,
7445 /* 1257 */ vec_rule,
7446 /* 1258 */ vec_rule,
7447 /* 1259 */ vec_rule,
7448 /* 1260 */ legVec_rule,
7449 /* 1261 */ legVec_rule,
7450 /* 1262 */ vec_rule,
7451 /* 1263 */ vec_rule,
7452 /* 1264 */ legVec_rule,
7453 /* 1265 */ legVec_rule,
7454 /* 1266 */ vec_rule,
7455 /* 1267 */ vec_rule,
7456 /* 1268 */ regF_rule,
7457 /* 1269 */ regD_rule,
7458 /* 1270 */ regF_rule,
7459 /* 1271 */ regD_rule,
7460 /* 1272 */ vec_rule,
7461 /* 1273 */ vec_rule,
7462 /* 1274 */ vec_rule,
7463 /* 1275 */ vec_rule,
7464 /* 1276 */ vec_rule,
7465 /* 1277 */ vec_rule,
7466 /* 1278 */ vec_rule,
7467 /* 1279 */ vec_rule,
7468 /* 1280 */ vec_rule,
7469 /* 1281 */ vec_rule,
7470 /* 1282 */ vec_rule,
7471 /* 1283 */ vec_rule,
7472 /* 1284 */ vec_rule,
7473 /* 1285 */ vec_rule,
7474 /* 1286 */ vec_rule,
7475 /* 1287 */ vec_rule,
7476 /* 1288 */ vec_rule,
7477 /* 1289 */ vec_rule,
7478 /* 1290 */ vec_rule,
7479 /* 1291 */ vec_rule,
7480 /* 1292 */ vec_rule,
7481 /* 1293 */ vec_rule,
7482 /* 1294 */ vec_rule,
7483 /* 1295 */ vec_rule,
7484 /* 1296 */ vec_rule,
7485 /* 1297 */ vec_rule,
7486 /* 1298 */ vec_rule,
7487 /* 1299 */ vec_rule,
7488 /* 1300 */ vec_rule,
7489 /* 1301 */ vec_rule,
7490 /* 1302 */ vec_rule,
7491 /* 1303 */ vec_rule,
7492 /* 1304 */ vec_rule,
7493 /* 1305 */ vec_rule,
7494 /* 1306 */ vec_rule,
7495 /* 1307 */ vec_rule,
7496 /* 1308 */ vec_rule,
7497 /* 1309 */ vec_rule,
7498 /* 1310 */ vec_rule,
7499 /* 1311 */ vec_rule,
7500 /* 1312 */ vec_rule,
7501 /* 1313 */ vec_rule,
7502 /* 1314 */ vec_rule,
7503 /* 1315 */ vec_rule,
7504 /* 1316 */ vec_rule,
7505 /* 1317 */ vec_rule,
7506 /* 1318 */ vec_rule,
7507 /* 1319 */ vec_rule,
7508 /* 1320 */ vec_rule,
7509 /* 1321 */ vec_rule,
7510 /* 1322 */ vec_rule,
7511 /* 1323 */ vec_rule,
7512 /* 1324 */ vec_rule,
7513 /* 1325 */ vec_rule,
7514 /* 1326 */ vec_rule,
7515 /* 1327 */ vec_rule,
7516 /* 1328 */ vec_rule,
7517 /* 1329 */ vec_rule,
7518 /* 1330 */ vec_rule,
7519 /* 1331 */ vec_rule,
7520 /* 1332 */ vec_rule,
7521 /* 1333 */ vec_rule,
7522 /* 1334 */ vec_rule,
7523 /* 1335 */ vec_rule,
7524 /* 1336 */ _LoadVector_memory__rule,
7525 /* 1337 */ vec_rule,
7526 /* 1338 */ vec_rule,
7527 /* 1339 */ vec_rule,
7528 /* 1340 */ _LoadVector_memory__rule,
7529 /* 1341 */ vec_rule,
7530 /* 1342 */ vec_rule,
7531 /* 1343 */ vec_rule,
7532 /* 1344 */ _LoadVector_memory__rule,
7533 /* 1345 */ vec_rule,
7534 /* 1346 */ vec_rule,
7535 /* 1347 */ vec_rule,
7536 /* 1348 */ vec_rule,
7537 /* 1349 */ vec_rule,
7538 /* 1350 */ vec_rule,
7539 /* 1351 */ vec_rule,
7540 /* 1352 */ vec_rule,
7541 /* 1353 */ _Binary_legVec_legVec_rule,
7542 /* 1354 */ _Binary_vec_vec_rule,
7543 /* 1355 */ _Binary_vec_vec_rule,
7544 /* 1356 */ _Binary_legVec_legVec_rule,
7545 /* 1357 */ _Binary_legVec_legVec_rule,
7546 /* 1358 */ _Binary_legVec_legVec_rule,
7547 /* 1359 */ _Binary_vec_vec_rule,
7548 /* 1360 */ _Binary_vec_vec_rule,
7549 /* 1361 */ legVec_rule,
7550 /* 1362 */ legVec_rule,
7551 /* 1363 */ legVec_rule,
7552 /* 1364 */ legVec_rule,
7553 /* 1365 */ legVec_rule,
7554 /* 1366 */ legVec_rule,
7555 /* 1367 */ legVec_rule,
7556 /* 1368 */ legVec_rule,
7557 /* 1369 */ legVec_rule,
7558 /* 1370 */ legVec_rule,
7559 /* 1371 */ legVec_rule,
7560 /* 1372 */ legVec_rule,
7561 /* 1373 */ _Binary_vec_vec_rule,
7562 /* 1374 */ _Binary_legVec_legVec_rule,
7563 /* 1375 */ _Binary_legVec_legVec_rule,
7564 /* 1376 */ _Binary_vec_vec_rule,
7565 /* 1377 */ _Binary_vec_vec_rule,
7566 /* 1378 */ vec_rule,
7567 /* 1379 */ vec_rule,
7568 /* 1380 */ vec_rule,
7569 /* 1381 */ vec_rule,
7570 /* 1382 */ vec_rule,
7571 /* 1383 */ vec_rule,
7572 /* 1384 */ legVec_rule,
7573 /* 1385 */ legVec_rule,
7574 /* 1386 */ kReg_rule,
7575 /* 1387 */ kReg_rule,
7576 /* 1388 */ legVec_rule,
7577 /* 1389 */ legVec_rule,
7578 /* 1390 */ kReg_rule,
7579 /* 1391 */ legVec_rule,
7580 /* 1392 */ vec_rule,
7581 /* 1393 */ vec_rule,
7582 /* 1394 */ vec_rule,
7583 /* 1395 */ vec_rule,
7584 /* 1396 */ vec_rule,
7585 /* 1397 */ vec_rule,
7586 /* 1398 */ vec_rule,
7587 /* 1399 */ vec_rule,
7588 /* 1400 */ vec_rule,
7589 /* 1401 */ kReg_rule,
7590 /* 1402 */ kReg_rule,
7591 /* 1403 */ immI_0_rule,
7592 /* 1404 */ vec_rule,
7593 /* 1405 */ legVec_rule,
7594 /* 1406 */ vec_rule,
7595 /* 1407 */ vec_rule,
7596 /* 1408 */ vec_rule,
7597 /* 1409 */ legVec_rule,
7598 /* 1410 */ vec_rule,
7599 /* 1411 */ vec_rule,
7600 /* 1412 */ vec_rule,
7601 /* 1413 */ vec_rule,
7602 /* 1414 */ vec_rule,
7603 /* 1415 */ vec_rule,
7604 /* 1416 */ vec_rule,
7605 /* 1417 */ vec_rule,
7606 /* 1418 */ vec_rule,
7607 /* 1419 */ vec_rule,
7608 /* 1420 */ vec_rule,
7609 /* 1421 */ vec_rule,
7610 /* 1422 */ vec_rule,
7611 /* 1423 */ _MulAddVS2VI_vec_vec_rule,
7612 /* 1424 */ vec_rule,
7613 /* 1425 */ _Binary_vec_vec_rule,
7614 /* 1426 */ _Binary_vec_vec_rule,
7615 /* 1427 */ vec_rule,
7616 /* 1428 */ vec_rule,
7617 /* 1429 */ vec_rule,
7618 /* 1430 */ vec_rule,
7619 /* 1431 */ vec_rule,
7620 /* 1432 */ memory_rule,
7621 /* 1433 */ rRegL_rule,
7622 /* 1434 */ immL_rule,
7623 /* 1435 */ memory_rule,
7624 /* 1436 */ kReg_rule,
7625 /* 1437 */ vec_rule,
7626 /* 1438 */ _VectorStoreMask_vec_immI_rule,
7627 /* 1439 */ kReg_rule,
7628 /* 1440 */ vec_rule,
7629 /* 1441 */ _VectorStoreMask_vec_immI_rule,
7630 /* 1442 */ kReg_rule,
7631 /* 1443 */ kReg_rule,
7632 /* 1444 */ vec_rule,
7633 /* 1445 */ vec_rule,
7634 /* 1446 */ _VectorStoreMask_vec_immI_rule,
7635 /* 1447 */ _VectorStoreMask_vec_immI_rule,
7636 /* 1448 */ _Binary_vec_vec_rule,
7637 /* 1449 */ _Binary_vec_vec_rule,
7638 /* 1450 */ _Binary_vec_vec_rule,
7639 /* 1451 */ _Binary_vec_vec_rule,
7640 /* 1452 */ _Binary_vec_vec_rule,
7641 /* 1453 */ _Binary_vec_vec_rule,
7642 /* 1454 */ _Binary_vec__LoadVector_memory__rule,
7643 /* 1455 */ _Binary_vec__LoadVector_memory__rule,
7644 /* 1456 */ _Binary_vec__LoadVector_memory__rule,
7645 /* 1457 */ _Binary_vec__LoadVector_memory__rule,
7646 /* 1458 */ _Binary_vec__LoadVector_memory__rule,
7647 /* 1459 */ _Binary_vec__LoadVector_memory__rule,
7648 /* 1460 */ _Binary_vec_vec_rule,
7649 /* 1461 */ _Binary_vec__LoadVector_memory__rule,
7650 /* 1462 */ _Binary_vec_vec_rule,
7651 /* 1463 */ _Binary_vec__LoadVector_memory__rule,
7652 /* 1464 */ _Binary_vec_vec_rule,
7653 /* 1465 */ _Binary_vec__LoadVector_memory__rule,
7654 /* 1466 */ _Binary_vec_vec_rule,
7655 /* 1467 */ _Binary_vec_vec_rule,
7656 /* 1468 */ _Binary_vec_vec_rule,
7657 /* 1469 */ _Binary_vec_vec_rule,
7658 /* 1470 */ _Binary_vec_vec_rule,
7659 /* 1471 */ _Binary_vec_vec_rule,
7660 /* 1472 */ _Binary_vec__LoadVector_memory__rule,
7661 /* 1473 */ _Binary_vec__LoadVector_memory__rule,
7662 /* 1474 */ _Binary_vec__LoadVector_memory__rule,
7663 /* 1475 */ _Binary_vec__LoadVector_memory__rule,
7664 /* 1476 */ _Binary_vec__LoadVector_memory__rule,
7665 /* 1477 */ _Binary_vec__LoadVector_memory__rule,
7666 /* 1478 */ _Binary_vec_vec_rule,
7667 /* 1479 */ _Binary_vec_vec_rule,
7668 /* 1480 */ _Binary_vec_vec_rule,
7669 /* 1481 */ _Binary_vec_vec_rule,
7670 /* 1482 */ _Binary_vec_vec_rule,
7671 /* 1483 */ _Binary_vec__LoadVector_memory__rule,
7672 /* 1484 */ _Binary_vec__LoadVector_memory__rule,
7673 /* 1485 */ _Binary_vec__LoadVector_memory__rule,
7674 /* 1486 */ _Binary_vec__LoadVector_memory__rule,
7675 /* 1487 */ _Binary_vec__LoadVector_memory__rule,
7676 /* 1488 */ vec_rule,
7677 /* 1489 */ vec_rule,
7678 /* 1490 */ _Binary_vec_vec_rule,
7679 /* 1491 */ _Binary_vec_vec_rule,
7680 /* 1492 */ _Binary_vec__LoadVector_memory__rule,
7681 /* 1493 */ _Binary_vec__LoadVector_memory__rule,
7682 /* 1494 */ _Binary_vec_immI8_rule,
7683 /* 1495 */ _Binary_vec_immI8_rule,
7684 /* 1496 */ _Binary_vec_vec_rule,
7685 /* 1497 */ _Binary_vec_vec_rule,
7686 /* 1498 */ _Binary_vec__LShiftCntV_immI8__rule,
7687 /* 1499 */ _Binary_vec__LShiftCntV_immI8__rule,
7688 /* 1500 */ _Binary_vec__LShiftCntV_immI8__rule,
7689 /* 1501 */ _Binary_vec_vec_rule,
7690 /* 1502 */ _Binary_vec_vec_rule,
7691 /* 1503 */ _Binary_vec_vec_rule,
7692 /* 1504 */ _Binary_vec_vec_rule,
7693 /* 1505 */ _Binary_vec_vec_rule,
7694 /* 1506 */ _Binary_vec_vec_rule,
7695 /* 1507 */ _Binary_vec__LoadVector_memory__rule,
7696 /* 1508 */ _Binary_vec__LoadVector_memory__rule,
7697 /* 1509 */ _Binary_vec__LoadVector_memory__rule,
7698 /* 1510 */ _Binary_vec__RShiftCntV_immI8__rule,
7699 /* 1511 */ _Binary_vec__RShiftCntV_immI8__rule,
7700 /* 1512 */ _Binary_vec__RShiftCntV_immI8__rule,
7701 /* 1513 */ _Binary_vec_vec_rule,
7702 /* 1514 */ _Binary_vec_vec_rule,
7703 /* 1515 */ _Binary_vec_vec_rule,
7704 /* 1516 */ _Binary_vec_vec_rule,
7705 /* 1517 */ _Binary_vec_vec_rule,
7706 /* 1518 */ _Binary_vec_vec_rule,
7707 /* 1519 */ _Binary_vec__LoadVector_memory__rule,
7708 /* 1520 */ _Binary_vec__LoadVector_memory__rule,
7709 /* 1521 */ _Binary_vec__LoadVector_memory__rule,
7710 /* 1522 */ _Binary_vec__RShiftCntV_immI8__rule,
7711 /* 1523 */ _Binary_vec__RShiftCntV_immI8__rule,
7712 /* 1524 */ _Binary_vec__RShiftCntV_immI8__rule,
7713 /* 1525 */ _Binary_vec_vec_rule,
7714 /* 1526 */ _Binary_vec_vec_rule,
7715 /* 1527 */ _Binary_vec_vec_rule,
7716 /* 1528 */ _Binary_vec_vec_rule,
7717 /* 1529 */ _Binary_vec_vec_rule,
7718 /* 1530 */ _Binary_vec_vec_rule,
7719 /* 1531 */ _Binary_vec__LoadVector_memory__rule,
7720 /* 1532 */ _Binary_vec__LoadVector_memory__rule,
7721 /* 1533 */ _Binary_vec__LoadVector_memory__rule,
7722 /* 1534 */ _Binary_vec_vec_rule,
7723 /* 1535 */ _Binary_vec__LoadVector_memory__rule,
7724 /* 1536 */ _Binary_vec_vec_rule,
7725 /* 1537 */ _Binary_vec__LoadVector_memory__rule,
7726 /* 1538 */ _Binary_vec_vec_rule,
7727 /* 1539 */ vec_rule,
7728 /* 1540 */ vec_rule,
7729 /* 1541 */ vec_rule,
7730 /* 1542 */ vec_rule,
7731 /* 1543 */ _Binary_vec_vec_rule,
7732 /* 1544 */ _Binary_vec_vec_rule,
7733 /* 1545 */ _Binary_vec_vec_rule,
7734 /* 1546 */ _Binary_vec_vec_rule,
7735 /* 1547 */ _Binary_vec_vec_rule,
7736 /* 1548 */ immI_rule,
7737 /* 1549 */ rRegI_rule,
7738 /* 1550 */ rRegL_rule,
7739 /* 1551 */ kReg_rule,
7740 /* 1552 */ kReg_rule,
7741 /* 1553 */ rRegL_rule,
7742 /* 1554 */ rRegL_rule,
7743 /* 1555 */ kReg_rule,
7744 /* 1556 */ kReg_rule,
7745 /* 1557 */ kReg_rule,
7746 /* 1558 */ memory_rule,
7747 /* 1559 */ memory_rule,
7748 /* 1560 */ memory_rule,
7749 /* 1561 */ memory_rule,
7750 /* 1562 */ memory_rule,
7751 /* 1563 */ memory_rule,
7752 /* 1564 */ memory_rule,
7753 /* 1565 */ memory_rule,
7754 /* 1566 */ memory_rule,
7755 /* 1567 */ memory_rule,
7756 /* 1568 */ memory_rule,
7757 // last instruction
7758 0 // no trailing comma
7759};
7760
7761const int rightOp[] = {
7762 /* 0 */ 0,
7763 /* 1 */ 0,
7764 /* 2 */ 0,
7765 /* 3 */ 0,
7766 /* 4 */ 0,
7767 /* 5 */ 0,
7768 /* 6 */ 0,
7769 /* 7 */ 0,
7770 /* 8 */ 0,
7771 /* 9 */ 0,
7772 /* 10 */ 0,
7773 /* 11 */ 0,
7774 /* 12 */ 0,
7775 /* 13 */ 0,
7776 /* 14 */ 0,
7777 /* 15 */ 0,
7778 /* 16 */ 0,
7779 /* 17 */ 0,
7780 /* 18 */ 0,
7781 /* 19 */ 0,
7782 /* 20 */ 0,
7783 /* 21 */ 0,
7784 /* 22 */ 0,
7785 /* 23 */ 0,
7786 /* 24 */ 0,
7787 /* 25 */ 0,
7788 /* 26 */ 0,
7789 /* 27 */ 0,
7790 /* 28 */ 0,
7791 /* 29 */ 0,
7792 /* 30 */ 0,
7793 /* 31 */ 0,
7794 /* 32 */ 0,
7795 /* 33 */ 0,
7796 /* 34 */ 0,
7797 /* 35 */ 0,
7798 /* 36 */ 0,
7799 /* 37 */ 0,
7800 /* 38 */ 0,
7801 /* 39 */ 0,
7802 /* 40 */ 0,
7803 /* 41 */ 0,
7804 /* 42 */ 0,
7805 /* 43 */ 0,
7806 /* 44 */ 0,
7807 /* 45 */ 0,
7808 /* 46 */ 0,
7809 /* 47 */ 0,
7810 /* 48 */ 0,
7811 /* 49 */ 0,
7812 /* 50 */ 0,
7813 /* 51 */ 0,
7814 /* 52 */ 0,
7815 /* 53 */ 0,
7816 /* 54 */ 0,
7817 /* 55 */ 0,
7818 /* 56 */ 0,
7819 /* 57 */ 0,
7820 /* 58 */ 0,
7821 /* 59 */ 0,
7822 /* 60 */ 0,
7823 /* 61 */ 0,
7824 /* 62 */ 0,
7825 /* 63 */ 0,
7826 /* 64 */ 0,
7827 /* 65 */ 0,
7828 /* 66 */ 0,
7829 /* 67 */ 0,
7830 /* 68 */ 0,
7831 /* 69 */ 0,
7832 /* 70 */ 0,
7833 /* 71 */ 0,
7834 /* 72 */ 0,
7835 /* 73 */ 0,
7836 /* 74 */ 0,
7837 /* 75 */ 0,
7838 /* 76 */ 0,
7839 /* 77 */ 0,
7840 /* 78 */ 0,
7841 /* 79 */ 0,
7842 /* 80 */ 0,
7843 /* 81 */ 0,
7844 /* 82 */ 0,
7845 /* 83 */ 0,
7846 /* 84 */ 0,
7847 /* 85 */ 0,
7848 /* 86 */ 0,
7849 /* 87 */ 0,
7850 /* 88 */ 0,
7851 /* 89 */ 0,
7852 /* 90 */ 0,
7853 /* 91 */ 0,
7854 /* 92 */ 0,
7855 /* 93 */ 0,
7856 /* 94 */ 0,
7857 /* 95 */ 0,
7858 /* 96 */ immL8_rule,
7859 /* 97 */ immL32_rule,
7860 /* 98 */ immL32_rule,
7861 /* 99 */ rRegL_rule,
7862 /* 100 */ _LShiftL_rRegL_immI2_rule,
7863 /* 101 */ _LShiftL__ConvI2L_rRegI__immI2_rule,
7864 /* 102 */ immL32_rule,
7865 /* 103 */ immL32_rule,
7866 /* 104 */ immL32_rule,
7867 /* 105 */ immL32_rule,
7868 /* 106 */ 0,
7869 /* 107 */ immL8_rule,
7870 /* 108 */ immL32_rule,
7871 /* 109 */ immL32_rule,
7872 /* 110 */ rRegL_rule,
7873 /* 111 */ _LShiftL_rRegL_immI2_rule,
7874 /* 112 */ immL32_rule,
7875 /* 113 */ immL32_rule,
7876 /* 114 */ immL32_rule,
7877 /* 115 */ 0,
7878 /* 116 */ 0,
7879 /* 117 */ 0,
7880 /* 118 */ 0,
7881 /* 119 */ 0,
7882 /* 120 */ 0,
7883 /* 121 */ 0,
7884 /* 122 */ 0,
7885 /* 123 */ 0,
7886 /* 124 */ 0,
7887 /* 125 */ 0,
7888 /* 126 */ 0,
7889 /* 127 */ 0,
7890 /* 128 */ 0,
7891 /* 129 */ 0,
7892 /* 130 */ 0,
7893 /* 131 */ 0,
7894 /* 132 */ 0,
7895 /* 133 */ 0,
7896 /* 134 */ 0,
7897 /* 135 */ 0,
7898 /* 136 */ 0,
7899 /* 137 */ 0,
7900 // last operand
7901 /* 138 */ 0,
7902 // last operand class
7903 /* 139 */ rRegL_rule,
7904 /* 140 */ immI2_rule,
7905 /* 141 */ 0,
7906 /* 142 */ immI2_rule,
7907 /* 143 */ _LShiftL_rRegL_immI2_rule,
7908 /* 144 */ _ConvI2L_rRegI__rule,
7909 /* 145 */ _LShiftL__ConvI2L_rRegI__immI2_rule,
7910 /* 146 */ 0,
7911 /* 147 */ rRegL_rule,
7912 /* 148 */ _LShiftL_rRegL_immI2_rule,
7913 /* 149 */ _ConvI2L_rRegI__rule,
7914 /* 150 */ _LShiftL__ConvI2L_rRegI__immI2_rule,
7915 /* 151 */ 0,
7916 /* 152 */ 0,
7917 /* 153 */ immI_rule,
7918 /* 154 */ 0,
7919 /* 155 */ immI_24_rule,
7920 /* 156 */ 0,
7921 /* 157 */ immI_24_rule,
7922 /* 158 */ immI_255_rule,
7923 /* 159 */ immI_rule,
7924 /* 160 */ 0,
7925 /* 161 */ immI_24_rule,
7926 /* 162 */ immI_16_rule,
7927 /* 163 */ immI_255_rule,
7928 /* 164 */ immI_65535_rule,
7929 /* 165 */ immU31_rule,
7930 /* 166 */ 0,
7931 /* 167 */ 0,
7932 /* 168 */ 0,
7933 /* 169 */ 0,
7934 /* 170 */ immL32_rule,
7935 /* 171 */ rFlagsReg_rule,
7936 /* 172 */ rRegI_rule,
7937 /* 173 */ rFlagsRegU_rule,
7938 /* 174 */ rFlagsRegUCF_rule,
7939 /* 175 */ _LoadI_memory__rule,
7940 /* 176 */ rRegN_rule,
7941 /* 177 */ rRegP_rule,
7942 /* 178 */ rRegL_rule,
7943 /* 179 */ _LoadL_memory__rule,
7944 /* 180 */ regF_rule,
7945 /* 181 */ regD_rule,
7946 /* 182 */ rRegI_rule,
7947 /* 183 */ _LoadI_memory__rule,
7948 /* 184 */ immI_rule,
7949 /* 185 */ immI_1_rule,
7950 /* 186 */ immI_M1_rule,
7951 /* 187 */ rRegL_rule,
7952 /* 188 */ _LoadL_memory__rule,
7953 /* 189 */ immL32_rule,
7954 /* 190 */ immL1_rule,
7955 /* 191 */ immL_M1_rule,
7956 /* 192 */ rRegP_rule,
7957 /* 193 */ rRegI_rule,
7958 /* 194 */ rRegL_rule,
7959 /* 195 */ rRegN_rule,
7960 /* 196 */ rRegI_rule,
7961 /* 197 */ immI_rule,
7962 /* 198 */ rRegL_rule,
7963 /* 199 */ immL32_rule,
7964 /* 200 */ rRegI_rule,
7965 /* 201 */ _LoadI_memory__rule,
7966 /* 202 */ _LoadL_memory__rule,
7967 /* 203 */ immI_1_rule,
7968 /* 204 */ immI8_rule,
7969 /* 205 */ rcx_RegI_rule,
7970 /* 206 */ immI_1_rule,
7971 /* 207 */ immI8_rule,
7972 /* 208 */ rcx_RegI_rule,
7973 /* 209 */ immI_1_rule,
7974 /* 210 */ immI8_rule,
7975 /* 211 */ rcx_RegI_rule,
7976 /* 212 */ immI_1_rule,
7977 /* 213 */ immI8_rule,
7978 /* 214 */ rcx_RegI_rule,
7979 /* 215 */ immI_1_rule,
7980 /* 216 */ immI8_rule,
7981 /* 217 */ rcx_RegI_rule,
7982 /* 218 */ immI_1_rule,
7983 /* 219 */ immI8_rule,
7984 /* 220 */ rcx_RegI_rule,
7985 /* 221 */ immI_24_rule,
7986 /* 222 */ immI_16_rule,
7987 /* 223 */ immI_255_rule,
7988 /* 224 */ immI_65535_rule,
7989 /* 225 */ immI_Pow2M1_rule,
7990 /* 226 */ rRegI_rule,
7991 /* 227 */ _LoadB_memory__rule,
7992 /* 228 */ rRegI_rule,
7993 /* 229 */ _LoadI_memory__rule,
7994 /* 230 */ immI_rule,
7995 /* 231 */ immI_M1_rule,
7996 /* 232 */ immI_M1_rule,
7997 /* 233 */ rRegI_rule,
7998 /* 234 */ _LoadB_memory__rule,
7999 /* 235 */ rRegI_rule,
8000 /* 236 */ _LoadI_memory__rule,
8001 /* 237 */ immI_rule,
8002 /* 238 */ rRegI_rule,
8003 /* 239 */ _LoadB_memory__rule,
8004 /* 240 */ rRegI_rule,
8005 /* 241 */ _LoadI_memory__rule,
8006 /* 242 */ immI_rule,
8007 /* 243 */ rRegL_rule,
8008 /* 244 */ _LoadL_memory__rule,
8009 /* 245 */ immL32_rule,
8010 /* 246 */ immL_NotPow2_rule,
8011 /* 247 */ immL_M1_rule,
8012 /* 248 */ rRegL_rule,
8013 /* 249 */ immL_M1_rule,
8014 /* 250 */ 0,
8015 /* 251 */ rRegL_rule,
8016 /* 252 */ _LoadL_memory__rule,
8017 /* 253 */ immL32_rule,
8018 /* 254 */ immL_Pow2_rule,
8019 /* 255 */ rRegL_rule,
8020 /* 256 */ _LoadL_memory__rule,
8021 /* 257 */ immL32_rule,
8022 /* 258 */ rRegI_rule,
8023 /* 259 */ rRegI_rule,
8024 /* 260 */ rRegI_rule,
8025 /* 261 */ _CmpLTMask_rRegI_rRegI_rule,
8026 /* 262 */ 0,
8027 /* 263 */ 0,
8028 /* 264 */ rcx_RegI_rule,
8029 /* 265 */ rdx_RegI_rule,
8030 /* 266 */ rdx_RegI_rule,
8031 /* 267 */ immI_rule,
8032 /* 268 */ rax_RegI_rule,
8033 /* 269 */ rsi_RegP_rule,
8034 /* 270 */ immI_rule,
8035 /* 271 */ 0,
8036 /* 272 */ 0,
8037 /* 273 */ 0,
8038 /* 274 */ immL32_rule,
8039 /* 275 */ _LoadL_memory__rule,
8040 /* 276 */ _CastP2X_rRegP__rule,
8041 /* 277 */ immU7_rule,
8042 /* 278 */ immI8_rule,
8043 /* 279 */ rax_RegP_rule,
8044 /* 280 */ 0,
8045 /* 281 */ kReg_rule,
8046 /* 282 */ vec_rule,
8047 /* 283 */ _Binary_vec_kReg_rule,
8048 /* 284 */ rRegI_rule,
8049 /* 285 */ rRegL_rule,
8050 /* 286 */ regF_rule,
8051 /* 287 */ regD_rule,
8052 /* 288 */ immI8_rule,
8053 /* 289 */ legVec_rule,
8054 /* 290 */ immD_rule,
8055 /* 291 */ 0,
8056 /* 292 */ 0,
8057 /* 293 */ legVec_rule,
8058 /* 294 */ kReg_rule,
8059 /* 295 */ _LoadVector_memory__rule,
8060 /* 296 */ vec_rule,
8061 /* 297 */ immU8_rule,
8062 /* 298 */ immU8_rule,
8063 /* 299 */ immI_rule,
8064 /* 300 */ immI8_rule,
8065 /* 301 */ _LShiftCntV_immI8__rule,
8066 /* 302 */ _RShiftCntV_immI8__rule,
8067 /* 303 */ kReg_rule,
8068 /* 304 */ kReg_rule,
8069 /* 305 */ 0,
8070 // last internally defined operand
8071 /* 306 */ 0,
8072 /* 307 */ 0,
8073 /* 308 */ 0,
8074 /* 309 */ 0,
8075 /* 310 */ 0,
8076 /* 311 */ 0,
8077 /* 312 */ 0,
8078 /* 313 */ 0,
8079 /* 314 */ 0,
8080 /* 315 */ 0,
8081 /* 316 */ 0,
8082 /* 317 */ 0,
8083 /* 318 */ 0,
8084 /* 319 */ 0,
8085 /* 320 */ 0,
8086 /* 321 */ 0,
8087 /* 322 */ 0,
8088 /* 323 */ 0,
8089 /* 324 */ 0,
8090 /* 325 */ 0,
8091 /* 326 */ 0,
8092 /* 327 */ 0,
8093 /* 328 */ 0,
8094 /* 329 */ 0,
8095 /* 330 */ 0,
8096 /* 331 */ 0,
8097 /* 332 */ 0,
8098 /* 333 */ 0,
8099 /* 334 */ 0,
8100 /* 335 */ 0,
8101 /* 336 */ 0,
8102 /* 337 */ 0,
8103 /* 338 */ 0,
8104 /* 339 */ 0,
8105 /* 340 */ 0,
8106 /* 341 */ 0,
8107 /* 342 */ 0,
8108 /* 343 */ 0,
8109 /* 344 */ 0,
8110 /* 345 */ 0,
8111 /* 346 */ 0,
8112 /* 347 */ 0,
8113 /* 348 */ 0,
8114 /* 349 */ 0,
8115 /* 350 */ 0,
8116 /* 351 */ 0,
8117 /* 352 */ 0,
8118 /* 353 */ 0,
8119 /* 354 */ 0,
8120 /* 355 */ 0,
8121 /* 356 */ 0,
8122 /* 357 */ 0,
8123 /* 358 */ 0,
8124 /* 359 */ 0,
8125 /* 360 */ 0,
8126 /* 361 */ 0,
8127 /* 362 */ 0,
8128 /* 363 */ 0,
8129 /* 364 */ 0,
8130 /* 365 */ 0,
8131 /* 366 */ 0,
8132 /* 367 */ _Binary_rax_RegP_rRegP_rule,
8133 /* 368 */ _Binary_rax_RegI_rRegI_rule,
8134 /* 369 */ _Binary_rax_RegL_rRegL_rule,
8135 /* 370 */ regF_rule,
8136 /* 371 */ regF_rule,
8137 /* 372 */ _LoadF_memory__rule,
8138 /* 373 */ _LoadF_memory__rule,
8139 /* 374 */ immF_rule,
8140 /* 375 */ immF_rule,
8141 /* 376 */ regD_rule,
8142 /* 377 */ regD_rule,
8143 /* 378 */ _LoadD_memory__rule,
8144 /* 379 */ _LoadD_memory__rule,
8145 /* 380 */ immD_rule,
8146 /* 381 */ immD_rule,
8147 /* 382 */ 0,
8148 /* 383 */ 0,
8149 /* 384 */ 0,
8150 /* 385 */ 0,
8151 /* 386 */ 0,
8152 /* 387 */ 0,
8153 /* 388 */ 0,
8154 /* 389 */ 0,
8155 /* 390 */ 0,
8156 /* 391 */ rRegI_rule,
8157 /* 392 */ immI_rule,
8158 /* 393 */ rRegL_rule,
8159 /* 394 */ immL32_rule,
8160 /* 395 */ rRegI_rule,
8161 /* 396 */ immI_rule,
8162 /* 397 */ rRegL_rule,
8163 /* 398 */ immL32_rule,
8164 /* 399 */ rax_RegI_rule,
8165 /* 400 */ rax_RegL_rule,
8166 /* 401 */ rRegI_rule,
8167 /* 402 */ immI_rule,
8168 /* 403 */ rRegL_rule,
8169 /* 404 */ immL32_rule,
8170 /* 405 */ rRegI_rule,
8171 /* 406 */ immI_rule,
8172 /* 407 */ _LoadI_memory__rule,
8173 /* 408 */ immI_0_rule,
8174 /* 409 */ immI_0_rule,
8175 /* 410 */ immI_0_rule,
8176 /* 411 */ immI_0_rule,
8177 /* 412 */ rRegI_rule,
8178 /* 413 */ immI_rule,
8179 /* 414 */ _LoadI_memory__rule,
8180 /* 415 */ immI_0_rule,
8181 /* 416 */ rRegP_rule,
8182 /* 417 */ _LoadP_memory__rule,
8183 /* 418 */ _LoadP_memory__rule,
8184 /* 419 */ immP0_rule,
8185 /* 420 */ immP0_rule,
8186 /* 421 */ immP0_rule,
8187 /* 422 */ rRegN_rule,
8188 /* 423 */ _LoadN_memory__rule,
8189 /* 424 */ immN_rule,
8190 /* 425 */ _LoadN_memory__rule,
8191 /* 426 */ immNKlass_rule,
8192 /* 427 */ _LoadNKlass_memory__rule,
8193 /* 428 */ immN0_rule,
8194 /* 429 */ immN0_rule,
8195 /* 430 */ immN0_rule,
8196 /* 431 */ rRegL_rule,
8197 /* 432 */ immL32_rule,
8198 /* 433 */ _LoadL_memory__rule,
8199 /* 434 */ immL0_rule,
8200 /* 435 */ immL0_rule,
8201 /* 436 */ immL0_rule,
8202 /* 437 */ immL0_rule,
8203 /* 438 */ immL0_rule,
8204 /* 439 */ immL0_rule,
8205 /* 440 */ rRegL_rule,
8206 /* 441 */ immL32_rule,
8207 /* 442 */ _LoadL_memory__rule,
8208 /* 443 */ immL0_rule,
8209 /* 444 */ immI8_rule,
8210 /* 445 */ immI_0_rule,
8211 /* 446 */ immI_0_rule,
8212 /* 447 */ immP0_rule,
8213 /* 448 */ rbx_RegP_rule,
8214 /* 449 */ rbx_RegP_rule,
8215 /* 450 */ rax_RegP_rule,
8216 /* 451 */ 0,
8217 /* 452 */ 0,
8218 /* 453 */ 0,
8219 /* 454 */ 0,
8220 /* 455 */ 0,
8221 /* 456 */ 0,
8222 /* 457 */ 0,
8223 /* 458 */ 0,
8224 /* 459 */ 0,
8225 /* 460 */ 0,
8226 /* 461 */ 0,
8227 /* 462 */ 0,
8228 /* 463 */ 0,
8229 /* 464 */ 0,
8230 /* 465 */ 0,
8231 /* 466 */ 0,
8232 /* 467 */ 0,
8233 /* 468 */ 0,
8234 /* 469 */ 0,
8235 /* 470 */ 0,
8236 /* 471 */ 0,
8237 /* 472 */ 0,
8238 /* 473 */ 0,
8239 /* 474 */ 0,
8240 /* 475 */ 0,
8241 /* 476 */ 0,
8242 /* 477 */ 0,
8243 /* 478 */ 0,
8244 /* 479 */ 0,
8245 /* 480 */ immI_0_rule,
8246 /* 481 */ immI_0_rule,
8247 /* 482 */ immI_0_rule,
8248 /* 483 */ 0,
8249 /* 484 */ 0,
8250 /* 485 */ 0,
8251 /* 486 */ 0,
8252 /* 487 */ 0,
8253 /* 488 */ 0,
8254 /* 489 */ 0,
8255 /* 490 */ 0,
8256 /* 491 */ 0,
8257 /* 492 */ 0,
8258 /* 493 */ 0,
8259 /* 494 */ 0,
8260 /* 495 */ 0,
8261 /* 496 */ 0,
8262 /* 497 */ 0,
8263 /* 498 */ 0,
8264 /* 499 */ 0,
8265 /* 500 */ immI_24_rule,
8266 /* 501 */ 0,
8267 /* 502 */ 0,
8268 /* 503 */ immI_24_rule,
8269 /* 504 */ 0,
8270 /* 505 */ 0,
8271 /* 506 */ 0,
8272 /* 507 */ 0,
8273 /* 508 */ immI_24_rule,
8274 /* 509 */ immI_255_rule,
8275 /* 510 */ immI_16_rule,
8276 /* 511 */ immI_65535_rule,
8277 /* 512 */ 0,
8278 /* 513 */ 0,
8279 /* 514 */ 0,
8280 /* 515 */ 0,
8281 /* 516 */ immL_32bits_rule,
8282 /* 517 */ 0,
8283 /* 518 */ 0,
8284 /* 519 */ 0,
8285 /* 520 */ 0,
8286 /* 521 */ 0,
8287 /* 522 */ 0,
8288 /* 523 */ 0,
8289 /* 524 */ 0,
8290 /* 525 */ 0,
8291 /* 526 */ legRegF_rule,
8292 /* 527 */ legRegF_rule,
8293 /* 528 */ legRegD_rule,
8294 /* 529 */ legRegD_rule,
8295 /* 530 */ legRegF_rule,
8296 /* 531 */ legRegF_rule,
8297 /* 532 */ legRegD_rule,
8298 /* 533 */ legRegD_rule,
8299 /* 534 */ 0,
8300 /* 535 */ 0,
8301 /* 536 */ 0,
8302 /* 537 */ 0,
8303 /* 538 */ rRegI_rule,
8304 /* 539 */ rRegI_rule,
8305 /* 540 */ rRegI_rule,
8306 /* 541 */ rRegL_rule,
8307 /* 542 */ any_RegP_rule,
8308 /* 543 */ immP0_rule,
8309 /* 544 */ immP31_rule,
8310 /* 545 */ rRegN_rule,
8311 /* 546 */ rRegN_rule,
8312 /* 547 */ immN0_rule,
8313 /* 548 */ immN_rule,
8314 /* 549 */ immNKlass_rule,
8315 /* 550 */ immI_0_rule,
8316 /* 551 */ immI_rule,
8317 /* 552 */ immL0_rule,
8318 /* 553 */ immL32_rule,
8319 /* 554 */ immI_0_rule,
8320 /* 555 */ immI16_rule,
8321 /* 556 */ immI_0_rule,
8322 /* 557 */ immI8_rule,
8323 /* 558 */ immI_0_rule,
8324 /* 559 */ immI_0_rule,
8325 /* 560 */ regF_rule,
8326 /* 561 */ immF0_rule,
8327 /* 562 */ immF_rule,
8328 /* 563 */ regD_rule,
8329 /* 564 */ immD0_rule,
8330 /* 565 */ immD0_rule,
8331 /* 566 */ 0,
8332 /* 567 */ 0,
8333 /* 568 */ 0,
8334 /* 569 */ 0,
8335 /* 570 */ 0,
8336 /* 571 */ 0,
8337 /* 572 */ 0,
8338 /* 573 */ 0,
8339 /* 574 */ 0,
8340 /* 575 */ 0,
8341 /* 576 */ 0,
8342 /* 577 */ 0,
8343 /* 578 */ 0,
8344 /* 579 */ 0,
8345 /* 580 */ 0,
8346 /* 581 */ 0,
8347 /* 582 */ 0,
8348 /* 583 */ 0,
8349 /* 584 */ 0,
8350 /* 585 */ 0,
8351 /* 586 */ 0,
8352 /* 587 */ 0,
8353 /* 588 */ 0,
8354 /* 589 */ 0,
8355 /* 590 */ 0,
8356 /* 591 */ 0,
8357 /* 592 */ 0,
8358 /* 593 */ 0,
8359 /* 594 */ 0,
8360 /* 595 */ 0,
8361 /* 596 */ 0,
8362 /* 597 */ 0,
8363 /* 598 */ 0,
8364 /* 599 */ 0,
8365 /* 600 */ 0,
8366 /* 601 */ 0,
8367 /* 602 */ 0,
8368 /* 603 */ 0,
8369 /* 604 */ 0,
8370 /* 605 */ _Binary_rRegI_rRegI_rule,
8371 /* 606 */ _Binary_rRegI_rRegI_rule,
8372 /* 607 */ _Binary_rRegI_rRegI_rule,
8373 /* 608 */ _Binary_rRegI__LoadI_memory__rule,
8374 /* 609 */ _Binary_rRegI__LoadI_memory__rule,
8375 /* 610 */ _Binary_rRegI__LoadI_memory__rule,
8376 /* 611 */ _Binary_rRegN_rRegN_rule,
8377 /* 612 */ _Binary_rRegN_rRegN_rule,
8378 /* 613 */ _Binary_rRegN_rRegN_rule,
8379 /* 614 */ _Binary_rRegP_rRegP_rule,
8380 /* 615 */ _Binary_rRegP_rRegP_rule,
8381 /* 616 */ _Binary_rRegP_rRegP_rule,
8382 /* 617 */ _Binary_rRegL_rRegL_rule,
8383 /* 618 */ _Binary_rRegL__LoadL_memory__rule,
8384 /* 619 */ _Binary_rRegL_rRegL_rule,
8385 /* 620 */ _Binary_rRegL_rRegL_rule,
8386 /* 621 */ _Binary_rRegL__LoadL_memory__rule,
8387 /* 622 */ _Binary_rRegL__LoadL_memory__rule,
8388 /* 623 */ _Binary_regF_regF_rule,
8389 /* 624 */ _Binary_regF_regF_rule,
8390 /* 625 */ _Binary_regF_regF_rule,
8391 /* 626 */ _Binary_regD_regD_rule,
8392 /* 627 */ _Binary_regD_regD_rule,
8393 /* 628 */ _Binary_regD_regD_rule,
8394 /* 629 */ rRegI_rule,
8395 /* 630 */ immI_rule,
8396 /* 631 */ _LoadI_memory__rule,
8397 /* 632 */ rRegI_rule,
8398 /* 633 */ _AddI__LoadI_memory__rRegI_rule,
8399 /* 634 */ _AddI_rRegI__LoadI_memory__rule,
8400 /* 635 */ _AddI__LoadI_memory__immI_rule,
8401 /* 636 */ immI_1_rule,
8402 /* 637 */ _AddI__LoadI_memory__immI_1_rule,
8403 /* 638 */ immI_M1_rule,
8404 /* 639 */ _AddI__LoadI_memory__immI_M1_rule,
8405 /* 640 */ immI_rule,
8406 /* 641 */ rRegL_rule,
8407 /* 642 */ immL32_rule,
8408 /* 643 */ _LoadL_memory__rule,
8409 /* 644 */ rRegL_rule,
8410 /* 645 */ _AddL__LoadL_memory__rRegL_rule,
8411 /* 646 */ _AddL_rRegL__LoadL_memory__rule,
8412 /* 647 */ _AddL__LoadL_memory__immL32_rule,
8413 /* 648 */ immL1_rule,
8414 /* 649 */ _AddL__LoadL_memory__immL1_rule,
8415 /* 650 */ immL_M1_rule,
8416 /* 651 */ _AddL__LoadL_memory__immL_M1_rule,
8417 /* 652 */ immL32_rule,
8418 /* 653 */ rRegL_rule,
8419 /* 654 */ immL32_rule,
8420 /* 655 */ immL32_rule,
8421 /* 656 */ 0,
8422 /* 657 */ _Binary_rax_RegP_rRegP_rule,
8423 /* 658 */ _Binary_rax_RegP_rRegP_rule,
8424 /* 659 */ _Binary_rax_RegL_rRegL_rule,
8425 /* 660 */ _Binary_rax_RegL_rRegL_rule,
8426 /* 661 */ _Binary_rax_RegI_rRegI_rule,
8427 /* 662 */ _Binary_rax_RegI_rRegI_rule,
8428 /* 663 */ _Binary_rax_RegI_rRegI_rule,
8429 /* 664 */ _Binary_rax_RegI_rRegI_rule,
8430 /* 665 */ _Binary_rax_RegI_rRegI_rule,
8431 /* 666 */ _Binary_rax_RegI_rRegI_rule,
8432 /* 667 */ _Binary_rax_RegN_rRegN_rule,
8433 /* 668 */ _Binary_rax_RegN_rRegN_rule,
8434 /* 669 */ _Binary_rax_RegI_rRegI_rule,
8435 /* 670 */ _Binary_rax_RegI_rRegI_rule,
8436 /* 671 */ _Binary_rax_RegI_rRegI_rule,
8437 /* 672 */ _Binary_rax_RegL_rRegL_rule,
8438 /* 673 */ _Binary_rax_RegN_rRegN_rule,
8439 /* 674 */ _Binary_rax_RegP_rRegP_rule,
8440 /* 675 */ immI_rule,
8441 /* 676 */ rRegI_rule,
8442 /* 677 */ immI_rule,
8443 /* 678 */ rRegI_rule,
8444 /* 679 */ immI_rule,
8445 /* 680 */ rRegI_rule,
8446 /* 681 */ immL32_rule,
8447 /* 682 */ rRegL_rule,
8448 /* 683 */ rRegI_rule,
8449 /* 684 */ rRegI_rule,
8450 /* 685 */ rRegI_rule,
8451 /* 686 */ rRegL_rule,
8452 /* 687 */ rRegP_rule,
8453 /* 688 */ rRegN_rule,
8454 /* 689 */ 0,
8455 /* 690 */ 0,
8456 /* 691 */ rRegI_rule,
8457 /* 692 */ immI_rule,
8458 /* 693 */ _LoadI_memory__rule,
8459 /* 694 */ _SubI__LoadI_memory__rRegI_rule,
8460 /* 695 */ _SubI__LoadI_memory__immI_rule,
8461 /* 696 */ rRegL_rule,
8462 /* 697 */ immL32_rule,
8463 /* 698 */ _LoadL_memory__rule,
8464 /* 699 */ _SubL__LoadL_memory__rRegL_rule,
8465 /* 700 */ _SubL__LoadL_memory__immL32_rule,
8466 /* 701 */ _SubI_immI_0_rRegI_rule,
8467 /* 702 */ rRegI_rule,
8468 /* 703 */ 0,
8469 /* 704 */ _SubI_immI_0__LoadI_memory__rule,
8470 /* 705 */ rRegL_rule,
8471 /* 706 */ 0,
8472 /* 707 */ _SubL_immL0__LoadL_memory__rule,
8473 /* 708 */ rRegI_rule,
8474 /* 709 */ immI_rule,
8475 /* 710 */ _LoadI_memory__rule,
8476 /* 711 */ rRegI_rule,
8477 /* 712 */ immI_rule,
8478 /* 713 */ _Binary_rRegI_rRegI_rule,
8479 /* 714 */ rRegL_rule,
8480 /* 715 */ immL32_rule,
8481 /* 716 */ _LoadL_memory__rule,
8482 /* 717 */ rRegL_rule,
8483 /* 718 */ immL32_rule,
8484 /* 719 */ rax_RegL_rule,
8485 /* 720 */ rax_RegL_rule,
8486 /* 721 */ no_rax_rdx_RegI_rule,
8487 /* 722 */ no_rax_rdx_RegL_rule,
8488 /* 723 */ no_rax_rdx_RegI_rule,
8489 /* 724 */ no_rax_rdx_RegL_rule,
8490 /* 725 */ 0,
8491 /* 726 */ 0,
8492 /* 727 */ 0,
8493 /* 728 */ 0,
8494 /* 729 */ immL10_rule,
8495 /* 730 */ no_rax_rdx_RegI_rule,
8496 /* 731 */ no_rax_rdx_RegL_rule,
8497 /* 732 */ immI_1_rule,
8498 /* 733 */ _LShiftI__LoadI_memory__immI_1_rule,
8499 /* 734 */ immI8_rule,
8500 /* 735 */ _LShiftI__LoadI_memory__immI8_rule,
8501 /* 736 */ rcx_RegI_rule,
8502 /* 737 */ _LShiftI__LoadI_memory__rcx_RegI_rule,
8503 /* 738 */ immI_1_rule,
8504 /* 739 */ _RShiftI__LoadI_memory__immI_1_rule,
8505 /* 740 */ immI8_rule,
8506 /* 741 */ _RShiftI__LoadI_memory__immI8_rule,
8507 /* 742 */ rcx_RegI_rule,
8508 /* 743 */ _RShiftI__LoadI_memory__rcx_RegI_rule,
8509 /* 744 */ immI_1_rule,
8510 /* 745 */ _URShiftI__LoadI_memory__immI_1_rule,
8511 /* 746 */ immI8_rule,
8512 /* 747 */ _URShiftI__LoadI_memory__immI8_rule,
8513 /* 748 */ rcx_RegI_rule,
8514 /* 749 */ _URShiftI__LoadI_memory__rcx_RegI_rule,
8515 /* 750 */ immI_1_rule,
8516 /* 751 */ _LShiftL__LoadL_memory__immI_1_rule,
8517 /* 752 */ immI8_rule,
8518 /* 753 */ _LShiftL__LoadL_memory__immI8_rule,
8519 /* 754 */ rcx_RegI_rule,
8520 /* 755 */ _LShiftL__LoadL_memory__rcx_RegI_rule,
8521 /* 756 */ immI_1_rule,
8522 /* 757 */ _RShiftL__LoadL_memory__immI_1_rule,
8523 /* 758 */ immI8_rule,
8524 /* 759 */ _RShiftL__LoadL_memory__immI8_rule,
8525 /* 760 */ rcx_RegI_rule,
8526 /* 761 */ _RShiftL__LoadL_memory__rcx_RegI_rule,
8527 /* 762 */ immI_1_rule,
8528 /* 763 */ _URShiftL__LoadL_memory__immI_1_rule,
8529 /* 764 */ immI8_rule,
8530 /* 765 */ _URShiftL__LoadL_memory__immI8_rule,
8531 /* 766 */ rcx_RegI_rule,
8532 /* 767 */ _URShiftL__LoadL_memory__rcx_RegI_rule,
8533 /* 768 */ immI_24_rule,
8534 /* 769 */ immI_16_rule,
8535 /* 770 */ immI8_rule,
8536 /* 771 */ rcx_RegI_rule,
8537 /* 772 */ immI8_rule,
8538 /* 773 */ immI8_rule,
8539 /* 774 */ rcx_RegI_rule,
8540 /* 775 */ immI8_rule,
8541 /* 776 */ rcx_RegI_rule,
8542 /* 777 */ immI8_rule,
8543 /* 778 */ immI8_rule,
8544 /* 779 */ rcx_RegI_rule,
8545 /* 780 */ rRegI_rule,
8546 /* 781 */ immI_255_rule,
8547 /* 782 */ 0,
8548 /* 783 */ immI_65535_rule,
8549 /* 784 */ 0,
8550 /* 785 */ 0,
8551 /* 786 */ immI_rule,
8552 /* 787 */ _LoadI_memory__rule,
8553 /* 788 */ rRegI_rule,
8554 /* 789 */ _AndI__LoadB_memory__rRegI_rule,
8555 /* 790 */ _AndI_rRegI__LoadB_memory__rule,
8556 /* 791 */ _AndI__LoadI_memory__rRegI_rule,
8557 /* 792 */ _AndI_rRegI__LoadI_memory__rule,
8558 /* 793 */ _AndI__LoadI_memory__immI_rule,
8559 /* 794 */ _LoadI_memory__rule,
8560 /* 795 */ _XorI_rRegI_immI_M1_rule,
8561 /* 796 */ rRegI_rule,
8562 /* 797 */ _XorI_rRegI_immI_M1_rule,
8563 /* 798 */ rRegI_rule,
8564 /* 799 */ _SubI_immI_0_rRegI_rule,
8565 /* 800 */ _LoadI_memory__rule,
8566 /* 801 */ _SubI_immI_0__LoadI_memory__rule,
8567 /* 802 */ _LoadI_memory__rule,
8568 /* 803 */ _AddI__LoadI_memory__immI_M1_rule,
8569 /* 804 */ rRegI_rule,
8570 /* 805 */ _AddI_rRegI_immI_M1_rule,
8571 /* 806 */ rRegI_rule,
8572 /* 807 */ _AddI_rRegI_immI_M1_rule,
8573 /* 808 */ _LoadI_memory__rule,
8574 /* 809 */ _AddI__LoadI_memory__immI_M1_rule,
8575 /* 810 */ rRegI_rule,
8576 /* 811 */ immI_rule,
8577 /* 812 */ _LoadI_memory__rule,
8578 /* 813 */ rRegI_rule,
8579 /* 814 */ _OrI__LoadB_memory__rRegI_rule,
8580 /* 815 */ _OrI_rRegI__LoadB_memory__rule,
8581 /* 816 */ _OrI__LoadI_memory__rRegI_rule,
8582 /* 817 */ _OrI_rRegI__LoadI_memory__rule,
8583 /* 818 */ _OrI__LoadI_memory__immI_rule,
8584 /* 819 */ rRegI_rule,
8585 /* 820 */ immI_M1_rule,
8586 /* 821 */ immI_rule,
8587 /* 822 */ _LoadI_memory__rule,
8588 /* 823 */ rRegI_rule,
8589 /* 824 */ _XorI__LoadB_memory__rRegI_rule,
8590 /* 825 */ _XorI_rRegI__LoadB_memory__rule,
8591 /* 826 */ _XorI__LoadI_memory__rRegI_rule,
8592 /* 827 */ _XorI_rRegI__LoadI_memory__rule,
8593 /* 828 */ _XorI__LoadI_memory__immI_rule,
8594 /* 829 */ rRegL_rule,
8595 /* 830 */ immL_255_rule,
8596 /* 831 */ immL_65535_rule,
8597 /* 832 */ immL32_rule,
8598 /* 833 */ _LoadL_memory__rule,
8599 /* 834 */ rRegL_rule,
8600 /* 835 */ _AndL__LoadL_memory__rRegL_rule,
8601 /* 836 */ _AndL_rRegL__LoadL_memory__rule,
8602 /* 837 */ _AndL__LoadL_memory__immL32_rule,
8603 /* 838 */ _AndL__LoadL_memory__immL_NotPow2_rule,
8604 /* 839 */ _LoadL_memory__rule,
8605 /* 840 */ _XorL_rRegL_immL_M1_rule,
8606 /* 841 */ rRegL_rule,
8607 /* 842 */ _XorL_rRegL_immL_M1_rule,
8608 /* 843 */ rRegL_rule,
8609 /* 844 */ _SubL_immL0_rRegL_rule,
8610 /* 845 */ _LoadL_memory__rule,
8611 /* 846 */ _SubL_immL0__LoadL_memory__rule,
8612 /* 847 */ _LoadL_memory__rule,
8613 /* 848 */ _AddL__LoadL_memory__immL_M1_rule,
8614 /* 849 */ rRegL_rule,
8615 /* 850 */ _AddL_rRegL_immL_M1_rule,
8616 /* 851 */ rRegL_rule,
8617 /* 852 */ _AddL_rRegL_immL_M1_rule,
8618 /* 853 */ _LoadL_memory__rule,
8619 /* 854 */ _AddL__LoadL_memory__immL_M1_rule,
8620 /* 855 */ rRegL_rule,
8621 /* 856 */ _CastP2X_any_RegP__rule,
8622 /* 857 */ rRegL_rule,
8623 /* 858 */ immL32_rule,
8624 /* 859 */ _LoadL_memory__rule,
8625 /* 860 */ rRegL_rule,
8626 /* 861 */ _OrL__LoadL_memory__rRegL_rule,
8627 /* 862 */ _OrL_rRegL__LoadL_memory__rule,
8628 /* 863 */ _OrL__LoadL_memory__immL32_rule,
8629 /* 864 */ _OrL__LoadL_memory__immL_Pow2_rule,
8630 /* 865 */ rRegL_rule,
8631 /* 866 */ immL_M1_rule,
8632 /* 867 */ immL32_rule,
8633 /* 868 */ _LoadL_memory__rule,
8634 /* 869 */ rRegL_rule,
8635 /* 870 */ _XorL__LoadL_memory__rRegL_rule,
8636 /* 871 */ _XorL_rRegL__LoadL_memory__rule,
8637 /* 872 */ _XorL__LoadL_memory__immL32_rule,
8638 /* 873 */ 0,
8639 /* 874 */ 0,
8640 /* 875 */ rRegI_rule,
8641 /* 876 */ immI_0_rule,
8642 /* 877 */ _SubI_rRegI_rRegI_rule,
8643 /* 878 */ _AndI__CmpLTMask_rRegI_rRegI_rRegI_rule,
8644 /* 879 */ _SubI_rRegI_rRegI_rule,
8645 /* 880 */ _AndI_rRegI__CmpLTMask_rRegI_rRegI_rule,
8646 /* 881 */ rRegI_rule,
8647 /* 882 */ _CmpLTMask_rRegI_rRegI_rule,
8648 /* 883 */ regF_rule,
8649 /* 884 */ _LoadF_memory__rule,
8650 /* 885 */ immF_rule,
8651 /* 886 */ regD_rule,
8652 /* 887 */ _LoadD_memory__rule,
8653 /* 888 */ immD_rule,
8654 /* 889 */ 0,
8655 /* 890 */ 0,
8656 /* 891 */ 0,
8657 /* 892 */ 0,
8658 /* 893 */ 0,
8659 /* 894 */ 0,
8660 /* 895 */ 0,
8661 /* 896 */ 0,
8662 /* 897 */ 0,
8663 /* 898 */ 0,
8664 /* 899 */ 0,
8665 /* 900 */ 0,
8666 /* 901 */ 0,
8667 /* 902 */ 0,
8668 /* 903 */ 0,
8669 /* 904 */ 0,
8670 /* 905 */ 0,
8671 /* 906 */ 0,
8672 /* 907 */ 0,
8673 /* 908 */ immL_32bits_rule,
8674 /* 909 */ immL_32bits_rule,
8675 /* 910 */ immL_32bits_rule,
8676 /* 911 */ 0,
8677 /* 912 */ 0,
8678 /* 913 */ 0,
8679 /* 914 */ 0,
8680 /* 915 */ 0,
8681 /* 916 */ rdi_RegP_rule,
8682 /* 917 */ rdi_RegP_rule,
8683 /* 918 */ rdi_RegP_rule,
8684 /* 919 */ rdi_RegP_rule,
8685 /* 920 */ rRegP_rule,
8686 /* 921 */ _Binary_rsi_RegP_rdx_RegI_rule,
8687 /* 922 */ _Binary_rsi_RegP_rdx_RegI_rule,
8688 /* 923 */ _Binary_rsi_RegP_rdx_RegI_rule,
8689 /* 924 */ _Binary_rsi_RegP_rdx_RegI_rule,
8690 /* 925 */ _Binary_rsi_RegP_rdx_RegI_rule,
8691 /* 926 */ _Binary_rsi_RegP_rdx_RegI_rule,
8692 /* 927 */ _Binary_rdi_RegP_rcx_RegI_rule,
8693 /* 928 */ _Binary_rdi_RegP_rcx_RegI_rule,
8694 /* 929 */ _Binary_rsi_RegP_immI_rule,
8695 /* 930 */ _Binary_rsi_RegP_immI_rule,
8696 /* 931 */ _Binary_rsi_RegP_immI_rule,
8697 /* 932 */ _Binary_rsi_RegP_rax_RegI_rule,
8698 /* 933 */ _Binary_rsi_RegP_rax_RegI_rule,
8699 /* 934 */ _Binary_rsi_RegP_rax_RegI_rule,
8700 /* 935 */ rax_RegI_rule,
8701 /* 936 */ rax_RegI_rule,
8702 /* 937 */ rcx_RegI_rule,
8703 /* 938 */ rcx_RegI_rule,
8704 /* 939 */ rsi_RegP_rule,
8705 /* 940 */ rsi_RegP_rule,
8706 /* 941 */ rsi_RegP_rule,
8707 /* 942 */ rsi_RegP_rule,
8708 /* 943 */ rcx_RegI_rule,
8709 /* 944 */ rcx_RegI_rule,
8710 /* 945 */ _Binary_rdi_RegP_rdx_RegI_rule,
8711 /* 946 */ _Binary_rdi_RegP_rdx_RegI_rule,
8712 /* 947 */ _Binary_rdi_RegP_rdx_RegI_rule,
8713 /* 948 */ _Binary_rdi_RegP_rdx_RegI_rule,
8714 /* 949 */ _Binary_rdi_RegP_rdx_RegI_rule,
8715 /* 950 */ _Binary_rdi_RegP_rdx_RegI_rule,
8716 /* 951 */ rRegL_rule,
8717 /* 952 */ 0,
8718 /* 953 */ rRegI_rule,
8719 /* 954 */ 0,
8720 /* 955 */ rRegI_rule,
8721 /* 956 */ 0,
8722 /* 957 */ rFlagsReg_rule,
8723 /* 958 */ rFlagsReg_rule,
8724 /* 959 */ rFlagsRegU_rule,
8725 /* 960 */ rFlagsRegUCF_rule,
8726 /* 961 */ rFlagsReg_rule,
8727 /* 962 */ rFlagsRegU_rule,
8728 /* 963 */ rFlagsRegUCF_rule,
8729 /* 964 */ rFlagsRegU_rule,
8730 /* 965 */ rFlagsRegUCF_rule,
8731 /* 966 */ rFlagsRegUCF_rule,
8732 /* 967 */ rax_RegP_rule,
8733 /* 968 */ 0,
8734 /* 969 */ rFlagsReg_rule,
8735 /* 970 */ rFlagsReg_rule,
8736 /* 971 */ rFlagsRegU_rule,
8737 /* 972 */ rFlagsRegUCF_rule,
8738 /* 973 */ rFlagsRegU_rule,
8739 /* 974 */ rFlagsRegUCF_rule,
8740 /* 975 */ rFlagsRegUCF_rule,
8741 /* 976 */ 0,
8742 /* 977 */ 0,
8743 /* 978 */ 0,
8744 /* 979 */ 0,
8745 /* 980 */ 0,
8746 /* 981 */ 0,
8747 /* 982 */ 0,
8748 /* 983 */ 0,
8749 /* 984 */ 0,
8750 /* 985 */ rbx_RegP_rule,
8751 /* 986 */ rax_RegP_rule,
8752 /* 987 */ 0,
8753 /* 988 */ 0,
8754 /* 989 */ 0,
8755 /* 990 */ 0,
8756 /* 991 */ regF_rule,
8757 /* 992 */ _LoadF_memory__rule,
8758 /* 993 */ regF_rule,
8759 /* 994 */ immF_rule,
8760 /* 995 */ regF_rule,
8761 /* 996 */ _LoadF_memory__rule,
8762 /* 997 */ regF_rule,
8763 /* 998 */ immF_rule,
8764 /* 999 */ regD_rule,
8765 /* 1000 */ _LoadD_memory__rule,
8766 /* 1001 */ regD_rule,
8767 /* 1002 */ immD_rule,
8768 /* 1003 */ regD_rule,
8769 /* 1004 */ _LoadD_memory__rule,
8770 /* 1005 */ regD_rule,
8771 /* 1006 */ immD_rule,
8772 /* 1007 */ regF_rule,
8773 /* 1008 */ _LoadF_memory__rule,
8774 /* 1009 */ immF_rule,
8775 /* 1010 */ regF_rule,
8776 /* 1011 */ _LoadF_memory__rule,
8777 /* 1012 */ immF_rule,
8778 /* 1013 */ regD_rule,
8779 /* 1014 */ _LoadD_memory__rule,
8780 /* 1015 */ immD_rule,
8781 /* 1016 */ regD_rule,
8782 /* 1017 */ _LoadD_memory__rule,
8783 /* 1018 */ immD_rule,
8784 /* 1019 */ regF_rule,
8785 /* 1020 */ _LoadF_memory__rule,
8786 /* 1021 */ regF_rule,
8787 /* 1022 */ immF_rule,
8788 /* 1023 */ regF_rule,
8789 /* 1024 */ _LoadF_memory__rule,
8790 /* 1025 */ regF_rule,
8791 /* 1026 */ immF_rule,
8792 /* 1027 */ regD_rule,
8793 /* 1028 */ _LoadD_memory__rule,
8794 /* 1029 */ regD_rule,
8795 /* 1030 */ immD_rule,
8796 /* 1031 */ regD_rule,
8797 /* 1032 */ _LoadD_memory__rule,
8798 /* 1033 */ regD_rule,
8799 /* 1034 */ immD_rule,
8800 /* 1035 */ regF_rule,
8801 /* 1036 */ _LoadF_memory__rule,
8802 /* 1037 */ immF_rule,
8803 /* 1038 */ regF_rule,
8804 /* 1039 */ _LoadF_memory__rule,
8805 /* 1040 */ immF_rule,
8806 /* 1041 */ regD_rule,
8807 /* 1042 */ _LoadD_memory__rule,
8808 /* 1043 */ immD_rule,
8809 /* 1044 */ regD_rule,
8810 /* 1045 */ _LoadD_memory__rule,
8811 /* 1046 */ immD_rule,
8812 /* 1047 */ 0,
8813 /* 1048 */ 0,
8814 /* 1049 */ 0,
8815 /* 1050 */ 0,
8816 /* 1051 */ 0,
8817 /* 1052 */ 0,
8818 /* 1053 */ 0,
8819 /* 1054 */ immU8_rule,
8820 /* 1055 */ immU8_rule,
8821 /* 1056 */ immU8_rule,
8822 /* 1057 */ immU8_rule,
8823 /* 1058 */ immU8_rule,
8824 /* 1059 */ immU8_rule,
8825 /* 1060 */ immU8_rule,
8826 /* 1061 */ 0,
8827 /* 1062 */ _Binary_regD_regD_rule,
8828 /* 1063 */ _Binary_regF_regF_rule,
8829 /* 1064 */ 0,
8830 /* 1065 */ vec_rule,
8831 /* 1066 */ legVec_rule,
8832 /* 1067 */ vec_rule,
8833 /* 1068 */ _Binary_vec_kReg_rule,
8834 /* 1069 */ _Binary_vec_vec_rule,
8835 /* 1070 */ _Binary_vec__Binary_vec_kReg_rule,
8836 /* 1071 */ 0,
8837 /* 1072 */ 0,
8838 /* 1073 */ 0,
8839 /* 1074 */ 0,
8840 /* 1075 */ 0,
8841 /* 1076 */ 0,
8842 /* 1077 */ 0,
8843 /* 1078 */ 0,
8844 /* 1079 */ 0,
8845 /* 1080 */ 0,
8846 /* 1081 */ 0,
8847 /* 1082 */ 0,
8848 /* 1083 */ 0,
8849 /* 1084 */ 0,
8850 /* 1085 */ 0,
8851 /* 1086 */ 0,
8852 /* 1087 */ 0,
8853 /* 1088 */ 0,
8854 /* 1089 */ 0,
8855 /* 1090 */ 0,
8856 /* 1091 */ 0,
8857 /* 1092 */ 0,
8858 /* 1093 */ 0,
8859 /* 1094 */ 0,
8860 /* 1095 */ 0,
8861 /* 1096 */ 0,
8862 /* 1097 */ immU8_rule,
8863 /* 1098 */ immU8_rule,
8864 /* 1099 */ immU8_rule,
8865 /* 1100 */ immU8_rule,
8866 /* 1101 */ immU8_rule,
8867 /* 1102 */ immU8_rule,
8868 /* 1103 */ immU8_rule,
8869 /* 1104 */ immU8_rule,
8870 /* 1105 */ immU8_rule,
8871 /* 1106 */ immU8_rule,
8872 /* 1107 */ immI_rule,
8873 /* 1108 */ legVec_rule,
8874 /* 1109 */ legVec_rule,
8875 /* 1110 */ legVec_rule,
8876 /* 1111 */ legVec_rule,
8877 /* 1112 */ legVec_rule,
8878 /* 1113 */ legVec_rule,
8879 /* 1114 */ legVec_rule,
8880 /* 1115 */ legVec_rule,
8881 /* 1116 */ legVec_rule,
8882 /* 1117 */ legVec_rule,
8883 /* 1118 */ legVec_rule,
8884 /* 1119 */ legVec_rule,
8885 /* 1120 */ legVec_rule,
8886 /* 1121 */ legVec_rule,
8887 /* 1122 */ vec_rule,
8888 /* 1123 */ vec_rule,
8889 /* 1124 */ vec_rule,
8890 /* 1125 */ vec_rule,
8891 /* 1126 */ vec_rule,
8892 /* 1127 */ vec_rule,
8893 /* 1128 */ vec_rule,
8894 /* 1129 */ vec_rule,
8895 /* 1130 */ vec_rule,
8896 /* 1131 */ vec_rule,
8897 /* 1132 */ vec_rule,
8898 /* 1133 */ legVec_rule,
8899 /* 1134 */ legVec_rule,
8900 /* 1135 */ vec_rule,
8901 /* 1136 */ vec_rule,
8902 /* 1137 */ vec_rule,
8903 /* 1138 */ vec_rule,
8904 /* 1139 */ legVec_rule,
8905 /* 1140 */ legVec_rule,
8906 /* 1141 */ legVec_rule,
8907 /* 1142 */ legVec_rule,
8908 /* 1143 */ legVec_rule,
8909 /* 1144 */ legVec_rule,
8910 /* 1145 */ legVec_rule,
8911 /* 1146 */ legVec_rule,
8912 /* 1147 */ vec_rule,
8913 /* 1148 */ vec_rule,
8914 /* 1149 */ vec_rule,
8915 /* 1150 */ vec_rule,
8916 /* 1151 */ vec_rule,
8917 /* 1152 */ vec_rule,
8918 /* 1153 */ legVec_rule,
8919 /* 1154 */ legVec_rule,
8920 /* 1155 */ legVec_rule,
8921 /* 1156 */ legVec_rule,
8922 /* 1157 */ legVec_rule,
8923 /* 1158 */ legVec_rule,
8924 /* 1159 */ legVec_rule,
8925 /* 1160 */ vec_rule,
8926 /* 1161 */ legVec_rule,
8927 /* 1162 */ legVec_rule,
8928 /* 1163 */ legVec_rule,
8929 /* 1164 */ legVec_rule,
8930 /* 1165 */ legVec_rule,
8931 /* 1166 */ legVec_rule,
8932 /* 1167 */ legVec_rule,
8933 /* 1168 */ legVec_rule,
8934 /* 1169 */ legVec_rule,
8935 /* 1170 */ legVec_rule,
8936 /* 1171 */ legVec_rule,
8937 /* 1172 */ legVec_rule,
8938 /* 1173 */ legVec_rule,
8939 /* 1174 */ legVec_rule,
8940 /* 1175 */ legVec_rule,
8941 /* 1176 */ legVec_rule,
8942 /* 1177 */ legVec_rule,
8943 /* 1178 */ vec_rule,
8944 /* 1179 */ vec_rule,
8945 /* 1180 */ _LoadVector_memory__rule,
8946 /* 1181 */ vec_rule,
8947 /* 1182 */ vec_rule,
8948 /* 1183 */ vec_rule,
8949 /* 1184 */ _LoadVector_memory__rule,
8950 /* 1185 */ vec_rule,
8951 /* 1186 */ vec_rule,
8952 /* 1187 */ vec_rule,
8953 /* 1188 */ _LoadVector_memory__rule,
8954 /* 1189 */ vec_rule,
8955 /* 1190 */ vec_rule,
8956 /* 1191 */ vec_rule,
8957 /* 1192 */ _LoadVector_memory__rule,
8958 /* 1193 */ vec_rule,
8959 /* 1194 */ vec_rule,
8960 /* 1195 */ vec_rule,
8961 /* 1196 */ _LoadVector_memory__rule,
8962 /* 1197 */ vec_rule,
8963 /* 1198 */ vec_rule,
8964 /* 1199 */ vec_rule,
8965 /* 1200 */ _LoadVector_memory__rule,
8966 /* 1201 */ vec_rule,
8967 /* 1202 */ vec_rule,
8968 /* 1203 */ vec_rule,
8969 /* 1204 */ _LoadVector_memory__rule,
8970 /* 1205 */ vec_rule,
8971 /* 1206 */ vec_rule,
8972 /* 1207 */ _LoadVector_memory__rule,
8973 /* 1208 */ vec_rule,
8974 /* 1209 */ vec_rule,
8975 /* 1210 */ _LoadVector_memory__rule,
8976 /* 1211 */ vec_rule,
8977 /* 1212 */ vec_rule,
8978 /* 1213 */ _LoadVector_memory__rule,
8979 /* 1214 */ vec_rule,
8980 /* 1215 */ vec_rule,
8981 /* 1216 */ _LoadVector_memory__rule,
8982 /* 1217 */ vec_rule,
8983 /* 1218 */ vec_rule,
8984 /* 1219 */ _LoadVector_memory__rule,
8985 /* 1220 */ vec_rule,
8986 /* 1221 */ vec_rule,
8987 /* 1222 */ vec_rule,
8988 /* 1223 */ vec_rule,
8989 /* 1224 */ vec_rule,
8990 /* 1225 */ vec_rule,
8991 /* 1226 */ vec_rule,
8992 /* 1227 */ _LoadVector_memory__rule,
8993 /* 1228 */ vec_rule,
8994 /* 1229 */ vec_rule,
8995 /* 1230 */ vec_rule,
8996 /* 1231 */ _LoadVector_memory__rule,
8997 /* 1232 */ vec_rule,
8998 /* 1233 */ vec_rule,
8999 /* 1234 */ _LoadVector_memory__rule,
9000 /* 1235 */ vec_rule,
9001 /* 1236 */ vec_rule,
9002 /* 1237 */ vec_rule,
9003 /* 1238 */ vec_rule,
9004 /* 1239 */ vec_rule,
9005 /* 1240 */ _LoadVector_memory__rule,
9006 /* 1241 */ vec_rule,
9007 /* 1242 */ vec_rule,
9008 /* 1243 */ vec_rule,
9009 /* 1244 */ _LoadVector_memory__rule,
9010 /* 1245 */ vec_rule,
9011 /* 1246 */ _Binary_legVec_legVec_rule,
9012 /* 1247 */ _Binary_legVec_legVec_rule,
9013 /* 1248 */ vec_rule,
9014 /* 1249 */ vec_rule,
9015 /* 1250 */ _LoadVector_memory__rule,
9016 /* 1251 */ vec_rule,
9017 /* 1252 */ vec_rule,
9018 /* 1253 */ _LoadVector_memory__rule,
9019 /* 1254 */ vec_rule,
9020 /* 1255 */ vec_rule,
9021 /* 1256 */ vec_rule,
9022 /* 1257 */ vec_rule,
9023 /* 1258 */ vec_rule,
9024 /* 1259 */ vec_rule,
9025 /* 1260 */ legVec_rule,
9026 /* 1261 */ legVec_rule,
9027 /* 1262 */ vec_rule,
9028 /* 1263 */ vec_rule,
9029 /* 1264 */ legVec_rule,
9030 /* 1265 */ legVec_rule,
9031 /* 1266 */ vec_rule,
9032 /* 1267 */ vec_rule,
9033 /* 1268 */ _Binary_regF_regF_rule,
9034 /* 1269 */ _Binary_regD_regD_rule,
9035 /* 1270 */ regF_rule,
9036 /* 1271 */ _Binary_regD_immD_rule,
9037 /* 1272 */ vec_rule,
9038 /* 1273 */ vec_rule,
9039 /* 1274 */ vec_rule,
9040 /* 1275 */ vec_rule,
9041 /* 1276 */ vec_rule,
9042 /* 1277 */ vec_rule,
9043 /* 1278 */ vec_rule,
9044 /* 1279 */ vec_rule,
9045 /* 1280 */ vec_rule,
9046 /* 1281 */ vec_rule,
9047 /* 1282 */ vec_rule,
9048 /* 1283 */ vec_rule,
9049 /* 1284 */ vec_rule,
9050 /* 1285 */ vec_rule,
9051 /* 1286 */ vec_rule,
9052 /* 1287 */ vec_rule,
9053 /* 1288 */ vec_rule,
9054 /* 1289 */ vec_rule,
9055 /* 1290 */ vec_rule,
9056 /* 1291 */ vec_rule,
9057 /* 1292 */ vec_rule,
9058 /* 1293 */ _LShiftCntV_immI8__rule,
9059 /* 1294 */ _RShiftCntV_immI8__rule,
9060 /* 1295 */ _RShiftCntV_immI8__rule,
9061 /* 1296 */ vec_rule,
9062 /* 1297 */ vec_rule,
9063 /* 1298 */ _LShiftCntV_immI8__rule,
9064 /* 1299 */ _RShiftCntV_immI8__rule,
9065 /* 1300 */ vec_rule,
9066 /* 1301 */ vec_rule,
9067 /* 1302 */ vec_rule,
9068 /* 1303 */ vec_rule,
9069 /* 1304 */ vec_rule,
9070 /* 1305 */ vec_rule,
9071 /* 1306 */ vec_rule,
9072 /* 1307 */ vec_rule,
9073 /* 1308 */ vec_rule,
9074 /* 1309 */ vec_rule,
9075 /* 1310 */ vec_rule,
9076 /* 1311 */ vec_rule,
9077 /* 1312 */ vec_rule,
9078 /* 1313 */ vec_rule,
9079 /* 1314 */ vec_rule,
9080 /* 1315 */ vec_rule,
9081 /* 1316 */ vec_rule,
9082 /* 1317 */ vec_rule,
9083 /* 1318 */ vec_rule,
9084 /* 1319 */ vec_rule,
9085 /* 1320 */ vec_rule,
9086 /* 1321 */ vec_rule,
9087 /* 1322 */ vec_rule,
9088 /* 1323 */ vec_rule,
9089 /* 1324 */ vec_rule,
9090 /* 1325 */ vec_rule,
9091 /* 1326 */ vec_rule,
9092 /* 1327 */ vec_rule,
9093 /* 1328 */ vec_rule,
9094 /* 1329 */ vec_rule,
9095 /* 1330 */ vec_rule,
9096 /* 1331 */ vec_rule,
9097 /* 1332 */ vec_rule,
9098 /* 1333 */ vec_rule,
9099 /* 1334 */ vec_rule,
9100 /* 1335 */ _LoadVector_memory__rule,
9101 /* 1336 */ vec_rule,
9102 /* 1337 */ vec_rule,
9103 /* 1338 */ vec_rule,
9104 /* 1339 */ _LoadVector_memory__rule,
9105 /* 1340 */ vec_rule,
9106 /* 1341 */ vec_rule,
9107 /* 1342 */ vec_rule,
9108 /* 1343 */ _LoadVector_memory__rule,
9109 /* 1344 */ vec_rule,
9110 /* 1345 */ 0,
9111 /* 1346 */ 0,
9112 /* 1347 */ 0,
9113 /* 1348 */ 0,
9114 /* 1349 */ 0,
9115 /* 1350 */ 0,
9116 /* 1351 */ 0,
9117 /* 1352 */ 0,
9118 /* 1353 */ immI8_rule,
9119 /* 1354 */ immI8_rule,
9120 /* 1355 */ immI8_rule,
9121 /* 1356 */ immI8_rule,
9122 /* 1357 */ immI8_rule,
9123 /* 1358 */ immI8_rule,
9124 /* 1359 */ immI8_rule,
9125 /* 1360 */ immI8_rule,
9126 /* 1361 */ immU8_rule,
9127 /* 1362 */ immU8_rule,
9128 /* 1363 */ immU8_rule,
9129 /* 1364 */ immI_rule,
9130 /* 1365 */ immI_rule,
9131 /* 1366 */ immI_rule,
9132 /* 1367 */ immU8_rule,
9133 /* 1368 */ immU8_rule,
9134 /* 1369 */ immU8_rule,
9135 /* 1370 */ immU8_rule,
9136 /* 1371 */ immU8_rule,
9137 /* 1372 */ immU8_rule,
9138 /* 1373 */ vec_rule,
9139 /* 1374 */ legVec_rule,
9140 /* 1375 */ legVec_rule,
9141 /* 1376 */ vec_rule,
9142 /* 1377 */ kReg_rule,
9143 /* 1378 */ 0,
9144 /* 1379 */ 0,
9145 /* 1380 */ 0,
9146 /* 1381 */ 0,
9147 /* 1382 */ 0,
9148 /* 1383 */ 0,
9149 /* 1384 */ legVec_rule,
9150 /* 1385 */ legVec_rule,
9151 /* 1386 */ kReg_rule,
9152 /* 1387 */ kReg_rule,
9153 /* 1388 */ legVec_rule,
9154 /* 1389 */ legVec_rule,
9155 /* 1390 */ kReg_rule,
9156 /* 1391 */ 0,
9157 /* 1392 */ 0,
9158 /* 1393 */ 0,
9159 /* 1394 */ immI_1_rule,
9160 /* 1395 */ immI_2_rule,
9161 /* 1396 */ immI_4_rule,
9162 /* 1397 */ immI_8_rule,
9163 /* 1398 */ immI_8_rule,
9164 /* 1399 */ immI_4_rule,
9165 /* 1400 */ immI_8_rule,
9166 /* 1401 */ immI_rule,
9167 /* 1402 */ immI_rule,
9168 /* 1403 */ 0,
9169 /* 1404 */ vec_rule,
9170 /* 1405 */ vec_rule,
9171 /* 1406 */ vec_rule,
9172 /* 1407 */ 0,
9173 /* 1408 */ vec_rule,
9174 /* 1409 */ vec_rule,
9175 /* 1410 */ vec_rule,
9176 /* 1411 */ 0,
9177 /* 1412 */ vec_rule,
9178 /* 1413 */ vec_rule,
9179 /* 1414 */ 0,
9180 /* 1415 */ vec_rule,
9181 /* 1416 */ vec_rule,
9182 /* 1417 */ _Binary_vec_vec_rule,
9183 /* 1418 */ _Binary_vec__LoadVector_memory__rule,
9184 /* 1419 */ _Binary_vec_vec_rule,
9185 /* 1420 */ _Binary_vec__LoadVector_memory__rule,
9186 /* 1421 */ vec_rule,
9187 /* 1422 */ vec_rule,
9188 /* 1423 */ vec_rule,
9189 /* 1424 */ _MulAddVS2VI_vec_vec_rule,
9190 /* 1425 */ _Binary_vec_immU8_rule,
9191 /* 1426 */ _Binary__LoadVector_memory__immU8_rule,
9192 /* 1427 */ immI8_rule,
9193 /* 1428 */ immI8_rule,
9194 /* 1429 */ vec_rule,
9195 /* 1430 */ vec_rule,
9196 /* 1431 */ _Binary_vec_kReg_rule,
9197 /* 1432 */ kReg_rule,
9198 /* 1433 */ 0,
9199 /* 1434 */ 0,
9200 /* 1435 */ _Binary_vec_kReg_rule,
9201 /* 1436 */ 0,
9202 /* 1437 */ 0,
9203 /* 1438 */ 0,
9204 /* 1439 */ 0,
9205 /* 1440 */ 0,
9206 /* 1441 */ 0,
9207 /* 1442 */ 0,
9208 /* 1443 */ 0,
9209 /* 1444 */ 0,
9210 /* 1445 */ 0,
9211 /* 1446 */ 0,
9212 /* 1447 */ 0,
9213 /* 1448 */ kReg_rule,
9214 /* 1449 */ kReg_rule,
9215 /* 1450 */ kReg_rule,
9216 /* 1451 */ kReg_rule,
9217 /* 1452 */ kReg_rule,
9218 /* 1453 */ kReg_rule,
9219 /* 1454 */ kReg_rule,
9220 /* 1455 */ kReg_rule,
9221 /* 1456 */ kReg_rule,
9222 /* 1457 */ kReg_rule,
9223 /* 1458 */ kReg_rule,
9224 /* 1459 */ kReg_rule,
9225 /* 1460 */ kReg_rule,
9226 /* 1461 */ kReg_rule,
9227 /* 1462 */ kReg_rule,
9228 /* 1463 */ kReg_rule,
9229 /* 1464 */ kReg_rule,
9230 /* 1465 */ kReg_rule,
9231 /* 1466 */ kReg_rule,
9232 /* 1467 */ kReg_rule,
9233 /* 1468 */ kReg_rule,
9234 /* 1469 */ kReg_rule,
9235 /* 1470 */ kReg_rule,
9236 /* 1471 */ kReg_rule,
9237 /* 1472 */ kReg_rule,
9238 /* 1473 */ kReg_rule,
9239 /* 1474 */ kReg_rule,
9240 /* 1475 */ kReg_rule,
9241 /* 1476 */ kReg_rule,
9242 /* 1477 */ kReg_rule,
9243 /* 1478 */ kReg_rule,
9244 /* 1479 */ kReg_rule,
9245 /* 1480 */ kReg_rule,
9246 /* 1481 */ kReg_rule,
9247 /* 1482 */ kReg_rule,
9248 /* 1483 */ kReg_rule,
9249 /* 1484 */ kReg_rule,
9250 /* 1485 */ kReg_rule,
9251 /* 1486 */ kReg_rule,
9252 /* 1487 */ kReg_rule,
9253 /* 1488 */ kReg_rule,
9254 /* 1489 */ kReg_rule,
9255 /* 1490 */ kReg_rule,
9256 /* 1491 */ kReg_rule,
9257 /* 1492 */ kReg_rule,
9258 /* 1493 */ kReg_rule,
9259 /* 1494 */ kReg_rule,
9260 /* 1495 */ kReg_rule,
9261 /* 1496 */ kReg_rule,
9262 /* 1497 */ kReg_rule,
9263 /* 1498 */ kReg_rule,
9264 /* 1499 */ kReg_rule,
9265 /* 1500 */ kReg_rule,
9266 /* 1501 */ kReg_rule,
9267 /* 1502 */ kReg_rule,
9268 /* 1503 */ kReg_rule,
9269 /* 1504 */ kReg_rule,
9270 /* 1505 */ kReg_rule,
9271 /* 1506 */ kReg_rule,
9272 /* 1507 */ kReg_rule,
9273 /* 1508 */ kReg_rule,
9274 /* 1509 */ kReg_rule,
9275 /* 1510 */ kReg_rule,
9276 /* 1511 */ kReg_rule,
9277 /* 1512 */ kReg_rule,
9278 /* 1513 */ kReg_rule,
9279 /* 1514 */ kReg_rule,
9280 /* 1515 */ kReg_rule,
9281 /* 1516 */ kReg_rule,
9282 /* 1517 */ kReg_rule,
9283 /* 1518 */ kReg_rule,
9284 /* 1519 */ kReg_rule,
9285 /* 1520 */ kReg_rule,
9286 /* 1521 */ kReg_rule,
9287 /* 1522 */ kReg_rule,
9288 /* 1523 */ kReg_rule,
9289 /* 1524 */ kReg_rule,
9290 /* 1525 */ kReg_rule,
9291 /* 1526 */ kReg_rule,
9292 /* 1527 */ kReg_rule,
9293 /* 1528 */ kReg_rule,
9294 /* 1529 */ kReg_rule,
9295 /* 1530 */ kReg_rule,
9296 /* 1531 */ kReg_rule,
9297 /* 1532 */ kReg_rule,
9298 /* 1533 */ kReg_rule,
9299 /* 1534 */ kReg_rule,
9300 /* 1535 */ kReg_rule,
9301 /* 1536 */ kReg_rule,
9302 /* 1537 */ kReg_rule,
9303 /* 1538 */ kReg_rule,
9304 /* 1539 */ kReg_rule,
9305 /* 1540 */ kReg_rule,
9306 /* 1541 */ kReg_rule,
9307 /* 1542 */ kReg_rule,
9308 /* 1543 */ _Binary_vec_kReg_rule,
9309 /* 1544 */ _Binary_vec_kReg_rule,
9310 /* 1545 */ _Binary__LoadVector_memory__kReg_rule,
9311 /* 1546 */ _Binary__LoadVector_memory__kReg_rule,
9312 /* 1547 */ _Binary_immI8_kReg_rule,
9313 /* 1548 */ 0,
9314 /* 1549 */ 0,
9315 /* 1550 */ 0,
9316 /* 1551 */ _MaskAll_immI_M1__rule,
9317 /* 1552 */ _MaskAll_immI_M1__rule,
9318 /* 1553 */ 0,
9319 /* 1554 */ 0,
9320 /* 1555 */ kReg_rule,
9321 /* 1556 */ kReg_rule,
9322 /* 1557 */ kReg_rule,
9323 /* 1558 */ _Binary_rax_RegP_rRegP_rule,
9324 /* 1559 */ _Binary_rax_RegP_rRegP_rule,
9325 /* 1560 */ _Binary_rax_RegN_rRegN_rule,
9326 /* 1561 */ _Binary_rax_RegN_rRegN_rule,
9327 /* 1562 */ _Binary_rax_RegN_rRegN_rule,
9328 /* 1563 */ _Binary_rax_RegP_rRegP_rule,
9329 /* 1564 */ 0,
9330 /* 1565 */ _Binary_rax_RegP_rRegP_rule,
9331 /* 1566 */ _Binary_rax_RegP_rRegP_rule,
9332 /* 1567 */ _Binary_rax_RegP_rRegP_rule,
9333 /* 1568 */ rRegP_rule,
9334 // last instruction
9335 0 // no trailing comma
9336};
9337
9338const char *ruleName[] = {
9339 /* 0 */ "UNIVERSE",
9340 /* 1 */ "LABEL",
9341 /* 2 */ "SREGI",
9342 /* 3 */ "SREGP",
9343 /* 4 */ "SREGF",
9344 /* 5 */ "SREGD",
9345 /* 6 */ "SREGL",
9346 /* 7 */ "METHOD",
9347 /* 8 */ "IMMI",
9348 /* 9 */ "IMMI_0",
9349 /* 10 */ "IMMI_1",
9350 /* 11 */ "IMMI_M1",
9351 /* 12 */ "IMMI_2",
9352 /* 13 */ "IMMI_4",
9353 /* 14 */ "IMMI_8",
9354 /* 15 */ "IMMI2",
9355 /* 16 */ "IMMU7",
9356 /* 17 */ "IMMI8",
9357 /* 18 */ "IMMU8",
9358 /* 19 */ "IMMI16",
9359 /* 20 */ "IMMU31",
9360 /* 21 */ "IMMI_32",
9361 /* 22 */ "IMMI_64",
9362 /* 23 */ "IMMP",
9363 /* 24 */ "IMMP0",
9364 /* 25 */ "IMMN",
9365 /* 26 */ "IMMNKLASS",
9366 /* 27 */ "IMMN0",
9367 /* 28 */ "IMMP31",
9368 /* 29 */ "IMML",
9369 /* 30 */ "IMML8",
9370 /* 31 */ "IMMUL32",
9371 /* 32 */ "IMML32",
9372 /* 33 */ "IMML_POW2",
9373 /* 34 */ "IMML_NOTPOW2",
9374 /* 35 */ "IMML0",
9375 /* 36 */ "IMML1",
9376 /* 37 */ "IMML_M1",
9377 /* 38 */ "IMML10",
9378 /* 39 */ "IMML_127",
9379 /* 40 */ "IMML_32BITS",
9380 /* 41 */ "IMMI_POW2M1",
9381 /* 42 */ "IMMF0",
9382 /* 43 */ "IMMF",
9383 /* 44 */ "IMMD0",
9384 /* 45 */ "IMMD",
9385 /* 46 */ "IMMI_16",
9386 /* 47 */ "IMMI_24",
9387 /* 48 */ "IMMI_255",
9388 /* 49 */ "IMMI_65535",
9389 /* 50 */ "IMML_255",
9390 /* 51 */ "IMML_65535",
9391 /* 52 */ "KREG",
9392 /* 53 */ "KREG_K1",
9393 /* 54 */ "KREG_K2",
9394 /* 55 */ "KREG_K3",
9395 /* 56 */ "KREG_K4",
9396 /* 57 */ "KREG_K5",
9397 /* 58 */ "KREG_K6",
9398 /* 59 */ "KREG_K7",
9399 /* 60 */ "RREGI",
9400 /* 61 */ "RAX_REGI",
9401 /* 62 */ "RBX_REGI",
9402 /* 63 */ "RCX_REGI",
9403 /* 64 */ "RDX_REGI",
9404 /* 65 */ "RDI_REGI",
9405 /* 66 */ "NO_RAX_RDX_REGI",
9406 /* 67 */ "ANY_REGP",
9407 /* 68 */ "RREGP",
9408 /* 69 */ "RREGN",
9409 /* 70 */ "NO_RAX_REGP",
9410 /* 71 */ "NO_RBP_REGP",
9411 /* 72 */ "NO_RAX_RBX_REGP",
9412 /* 73 */ "RAX_REGP",
9413 /* 74 */ "RAX_REGN",
9414 /* 75 */ "RBX_REGP",
9415 /* 76 */ "RSI_REGP",
9416 /* 77 */ "RBP_REGP",
9417 /* 78 */ "RDI_REGP",
9418 /* 79 */ "R15_REGP",
9419 /* 80 */ "RREGL",
9420 /* 81 */ "NO_RAX_RDX_REGL",
9421 /* 82 */ "NO_RAX_REGL",
9422 /* 83 */ "RAX_REGL",
9423 /* 84 */ "RCX_REGL",
9424 /* 85 */ "RDX_REGL",
9425 /* 86 */ "RFLAGSREG",
9426 /* 87 */ "RFLAGSREGU",
9427 /* 88 */ "RFLAGSREGUCF",
9428 /* 89 */ "REGF",
9429 /* 90 */ "LEGREGF",
9430 /* 91 */ "VLREGF",
9431 /* 92 */ "REGD",
9432 /* 93 */ "LEGREGD",
9433 /* 94 */ "VLREGD",
9434 /* 95 */ "INDIRECT",
9435 /* 96 */ "INDOFFSET8",
9436 /* 97 */ "INDOFFSET32",
9437 /* 98 */ "INDINDEXOFFSET",
9438 /* 99 */ "INDINDEX",
9439 /* 100 */ "INDINDEXSCALE",
9440 /* 101 */ "INDPOSINDEXSCALE",
9441 /* 102 */ "INDINDEXSCALEOFFSET",
9442 /* 103 */ "INDPOSINDEXOFFSET",
9443 /* 104 */ "INDPOSINDEXSCALEOFFSET",
9444 /* 105 */ "INDCOMPRESSEDOOPOFFSET",
9445 /* 106 */ "INDIRECTNARROW",
9446 /* 107 */ "INDOFFSET8NARROW",
9447 /* 108 */ "INDOFFSET32NARROW",
9448 /* 109 */ "INDINDEXOFFSETNARROW",
9449 /* 110 */ "INDINDEXNARROW",
9450 /* 111 */ "INDINDEXSCALENARROW",
9451 /* 112 */ "INDINDEXSCALEOFFSETNARROW",
9452 /* 113 */ "INDPOSINDEXOFFSETNARROW",
9453 /* 114 */ "INDPOSINDEXSCALEOFFSETNARROW",
9454 /* 115 */ "STACKSLOTP",
9455 /* 116 */ "STACKSLOTI",
9456 /* 117 */ "STACKSLOTF",
9457 /* 118 */ "STACKSLOTD",
9458 /* 119 */ "STACKSLOTL",
9459 /* 120 */ "CMPOP",
9460 /* 121 */ "CMPOPU",
9461 /* 122 */ "CMPOPUCF",
9462 /* 123 */ "CMPOPUCF2",
9463 /* 124 */ "RXMM0",
9464 /* 125 */ "VEC",
9465 /* 126 */ "LEGVEC",
9466 /* 127 */ "VECS",
9467 /* 128 */ "LEGVECS",
9468 /* 129 */ "VECD",
9469 /* 130 */ "LEGVECD",
9470 /* 131 */ "VECX",
9471 /* 132 */ "LEGVECX",
9472 /* 133 */ "VECY",
9473 /* 134 */ "LEGVECY",
9474 /* 135 */ "VECZ",
9475 /* 136 */ "LEGVECZ",
9476 /* 137 */ "CMPOP_VCMPPD",
9477 // last operand
9478 /* 138 */ "MEMORY",
9479 // last operand class
9480 /* 139 */ "_AddP_any_RegP_rRegL",
9481 /* 140 */ "_LShiftL_rRegL_immI2",
9482 /* 141 */ "_ConvI2L_rRegI_",
9483 /* 142 */ "_LShiftL__ConvI2L_rRegI__immI2",
9484 /* 143 */ "_AddP_any_RegP__LShiftL_rRegL_immI2",
9485 /* 144 */ "_AddP_any_RegP__ConvI2L_rRegI_",
9486 /* 145 */ "_AddP_any_RegP__LShiftL__ConvI2L_rRegI__immI2",
9487 /* 146 */ "_DecodeN_rRegN_",
9488 /* 147 */ "_AddP__DecodeN_rRegN__rRegL",
9489 /* 148 */ "_AddP__DecodeN_rRegN___LShiftL_rRegL_immI2",
9490 /* 149 */ "_AddP__DecodeN_rRegN___ConvI2L_rRegI_",
9491 /* 150 */ "_AddP__DecodeN_rRegN___LShiftL__ConvI2L_rRegI__immI2",
9492 /* 151 */ "_LoadB_memory_",
9493 /* 152 */ "_LoadUB_memory_",
9494 /* 153 */ "_AndI__LoadUB_memory__immI",
9495 /* 154 */ "_LoadS_memory_",
9496 /* 155 */ "_LShiftI__LoadS_memory__immI_24",
9497 /* 156 */ "_LoadUS_memory_",
9498 /* 157 */ "_LShiftI__LoadUS_memory__immI_24",
9499 /* 158 */ "_AndI__LoadUS_memory__immI_255",
9500 /* 159 */ "_AndI__LoadUS_memory__immI",
9501 /* 160 */ "_LoadI_memory_",
9502 /* 161 */ "_LShiftI__LoadI_memory__immI_24",
9503 /* 162 */ "_LShiftI__LoadI_memory__immI_16",
9504 /* 163 */ "_AndI__LoadI_memory__immI_255",
9505 /* 164 */ "_AndI__LoadI_memory__immI_65535",
9506 /* 165 */ "_AndI__LoadI_memory__immU31",
9507 /* 166 */ "_ConvI2L__LoadI_memory__",
9508 /* 167 */ "_LoadL_memory_",
9509 /* 168 */ "_CastP2X_rRegP_",
9510 /* 169 */ "_CastP2X__DecodeN_rRegN__",
9511 /* 170 */ "_AddL__LShiftL_rRegL_immI2_immL32",
9512 /* 171 */ "_Binary_cmpOp_rFlagsReg",
9513 /* 172 */ "_Binary_rRegI_rRegI",
9514 /* 173 */ "_Binary_cmpOpU_rFlagsRegU",
9515 /* 174 */ "_Binary_cmpOpUCF_rFlagsRegUCF",
9516 /* 175 */ "_Binary_rRegI__LoadI_memory_",
9517 /* 176 */ "_Binary_rRegN_rRegN",
9518 /* 177 */ "_Binary_rRegP_rRegP",
9519 /* 178 */ "_Binary_rRegL_rRegL",
9520 /* 179 */ "_Binary_rRegL__LoadL_memory_",
9521 /* 180 */ "_Binary_regF_regF",
9522 /* 181 */ "_Binary_regD_regD",
9523 /* 182 */ "_AddI__LoadI_memory__rRegI",
9524 /* 183 */ "_AddI_rRegI__LoadI_memory_",
9525 /* 184 */ "_AddI__LoadI_memory__immI",
9526 /* 185 */ "_AddI__LoadI_memory__immI_1",
9527 /* 186 */ "_AddI__LoadI_memory__immI_M1",
9528 /* 187 */ "_AddL__LoadL_memory__rRegL",
9529 /* 188 */ "_AddL_rRegL__LoadL_memory_",
9530 /* 189 */ "_AddL__LoadL_memory__immL32",
9531 /* 190 */ "_AddL__LoadL_memory__immL1",
9532 /* 191 */ "_AddL__LoadL_memory__immL_M1",
9533 /* 192 */ "_Binary_rax_RegP_rRegP",
9534 /* 193 */ "_Binary_rax_RegI_rRegI",
9535 /* 194 */ "_Binary_rax_RegL_rRegL",
9536 /* 195 */ "_Binary_rax_RegN_rRegN",
9537 /* 196 */ "_SubI__LoadI_memory__rRegI",
9538 /* 197 */ "_SubI__LoadI_memory__immI",
9539 /* 198 */ "_SubL__LoadL_memory__rRegL",
9540 /* 199 */ "_SubL__LoadL_memory__immL32",
9541 /* 200 */ "_SubI_immI_0_rRegI",
9542 /* 201 */ "_SubI_immI_0__LoadI_memory_",
9543 /* 202 */ "_SubL_immL0__LoadL_memory_",
9544 /* 203 */ "_LShiftI__LoadI_memory__immI_1",
9545 /* 204 */ "_LShiftI__LoadI_memory__immI8",
9546 /* 205 */ "_LShiftI__LoadI_memory__rcx_RegI",
9547 /* 206 */ "_RShiftI__LoadI_memory__immI_1",
9548 /* 207 */ "_RShiftI__LoadI_memory__immI8",
9549 /* 208 */ "_RShiftI__LoadI_memory__rcx_RegI",
9550 /* 209 */ "_URShiftI__LoadI_memory__immI_1",
9551 /* 210 */ "_URShiftI__LoadI_memory__immI8",
9552 /* 211 */ "_URShiftI__LoadI_memory__rcx_RegI",
9553 /* 212 */ "_LShiftL__LoadL_memory__immI_1",
9554 /* 213 */ "_LShiftL__LoadL_memory__immI8",
9555 /* 214 */ "_LShiftL__LoadL_memory__rcx_RegI",
9556 /* 215 */ "_RShiftL__LoadL_memory__immI_1",
9557 /* 216 */ "_RShiftL__LoadL_memory__immI8",
9558 /* 217 */ "_RShiftL__LoadL_memory__rcx_RegI",
9559 /* 218 */ "_URShiftL__LoadL_memory__immI_1",
9560 /* 219 */ "_URShiftL__LoadL_memory__immI8",
9561 /* 220 */ "_URShiftL__LoadL_memory__rcx_RegI",
9562 /* 221 */ "_LShiftI_rRegI_immI_24",
9563 /* 222 */ "_LShiftI_rRegI_immI_16",
9564 /* 223 */ "_AndI_rRegI_immI_255",
9565 /* 224 */ "_AndI_rRegI_immI_65535",
9566 /* 225 */ "_AndI_rRegI_immI_Pow2M1",
9567 /* 226 */ "_AndI__LoadB_memory__rRegI",
9568 /* 227 */ "_AndI_rRegI__LoadB_memory_",
9569 /* 228 */ "_AndI__LoadI_memory__rRegI",
9570 /* 229 */ "_AndI_rRegI__LoadI_memory_",
9571 /* 230 */ "_AndI__LoadI_memory__immI",
9572 /* 231 */ "_XorI_rRegI_immI_M1",
9573 /* 232 */ "_AddI_rRegI_immI_M1",
9574 /* 233 */ "_OrI__LoadB_memory__rRegI",
9575 /* 234 */ "_OrI_rRegI__LoadB_memory_",
9576 /* 235 */ "_OrI__LoadI_memory__rRegI",
9577 /* 236 */ "_OrI_rRegI__LoadI_memory_",
9578 /* 237 */ "_OrI__LoadI_memory__immI",
9579 /* 238 */ "_XorI__LoadB_memory__rRegI",
9580 /* 239 */ "_XorI_rRegI__LoadB_memory_",
9581 /* 240 */ "_XorI__LoadI_memory__rRegI",
9582 /* 241 */ "_XorI_rRegI__LoadI_memory_",
9583 /* 242 */ "_XorI__LoadI_memory__immI",
9584 /* 243 */ "_AndL__LoadL_memory__rRegL",
9585 /* 244 */ "_AndL_rRegL__LoadL_memory_",
9586 /* 245 */ "_AndL__LoadL_memory__immL32",
9587 /* 246 */ "_AndL__LoadL_memory__immL_NotPow2",
9588 /* 247 */ "_XorL_rRegL_immL_M1",
9589 /* 248 */ "_SubL_immL0_rRegL",
9590 /* 249 */ "_AddL_rRegL_immL_M1",
9591 /* 250 */ "_CastP2X_any_RegP_",
9592 /* 251 */ "_OrL__LoadL_memory__rRegL",
9593 /* 252 */ "_OrL_rRegL__LoadL_memory_",
9594 /* 253 */ "_OrL__LoadL_memory__immL32",
9595 /* 254 */ "_OrL__LoadL_memory__immL_Pow2",
9596 /* 255 */ "_XorL__LoadL_memory__rRegL",
9597 /* 256 */ "_XorL_rRegL__LoadL_memory_",
9598 /* 257 */ "_XorL__LoadL_memory__immL32",
9599 /* 258 */ "_CmpLTMask_rRegI_rRegI",
9600 /* 259 */ "_AndI__CmpLTMask_rRegI_rRegI_rRegI",
9601 /* 260 */ "_SubI_rRegI_rRegI",
9602 /* 261 */ "_AndI_rRegI__CmpLTMask_rRegI_rRegI",
9603 /* 262 */ "_LoadF_memory_",
9604 /* 263 */ "_LoadD_memory_",
9605 /* 264 */ "_Binary_rdi_RegP_rcx_RegI",
9606 /* 265 */ "_Binary_rsi_RegP_rdx_RegI",
9607 /* 266 */ "_Binary_rdi_RegP_rdx_RegI",
9608 /* 267 */ "_Binary_rsi_RegP_immI",
9609 /* 268 */ "_Binary_rsi_RegP_rax_RegI",
9610 /* 269 */ "_Binary_rdi_RegP_rsi_RegP",
9611 /* 270 */ "_AndI_rRegI_immI",
9612 /* 271 */ "_LoadP_memory_",
9613 /* 272 */ "_LoadN_memory_",
9614 /* 273 */ "_LoadNKlass_memory_",
9615 /* 274 */ "_AndL_rRegL_immL32",
9616 /* 275 */ "_AndL__CastP2X_rRegP___LoadL_memory_",
9617 /* 276 */ "_AndL__LoadL_memory___CastP2X_rRegP_",
9618 /* 277 */ "_AndI__LoadUB_memory__immU7",
9619 /* 278 */ "_AndI__LoadB_memory__immI8",
9620 /* 279 */ "_PartialSubtypeCheck_rsi_RegP_rax_RegP",
9621 /* 280 */ "_LoadVector_memory_",
9622 /* 281 */ "_Binary_vec_kReg",
9623 /* 282 */ "_Binary_vec_vec",
9624 /* 283 */ "_Binary_vec__Binary_vec_kReg",
9625 /* 284 */ "_Binary_vec_rRegI",
9626 /* 285 */ "_Binary_vec_rRegL",
9627 /* 286 */ "_Binary_vec_regF",
9628 /* 287 */ "_Binary_vec_regD",
9629 /* 288 */ "_Binary_cmpOp_vcmppd_immI8",
9630 /* 289 */ "_Binary_legVec_legVec",
9631 /* 290 */ "_Binary_regD_immD",
9632 /* 291 */ "_LShiftCntV_immI8_",
9633 /* 292 */ "_RShiftCntV_immI8_",
9634 /* 293 */ "_VectorTest_legVec_legVec",
9635 /* 294 */ "_VectorTest_kReg_kReg",
9636 /* 295 */ "_Binary_vec__LoadVector_memory_",
9637 /* 296 */ "_MulAddVS2VI_vec_vec",
9638 /* 297 */ "_Binary_vec_immU8",
9639 /* 298 */ "_Binary__LoadVector_memory__immU8",
9640 /* 299 */ "_VectorStoreMask_vec_immI",
9641 /* 300 */ "_Binary_vec_immI8",
9642 /* 301 */ "_Binary_vec__LShiftCntV_immI8_",
9643 /* 302 */ "_Binary_vec__RShiftCntV_immI8_",
9644 /* 303 */ "_Binary__LoadVector_memory__kReg",
9645 /* 304 */ "_Binary_immI8_kReg",
9646 /* 305 */ "_MaskAll_immI_M1_",
9647 // last internally defined operand
9648 /* 306 */ "storeSSI",
9649 /* 307 */ "storeSSL",
9650 /* 308 */ "storeSSP",
9651 /* 309 */ "storeSSF",
9652 /* 310 */ "storeSSD",
9653 /* 311 */ "MoveF2VL",
9654 /* 312 */ "MoveF2LEG",
9655 /* 313 */ "MoveVL2F",
9656 /* 314 */ "MoveLEG2F",
9657 /* 315 */ "MoveD2VL",
9658 /* 316 */ "MoveD2LEG",
9659 /* 317 */ "MoveVL2D",
9660 /* 318 */ "MoveLEG2D",
9661 /* 319 */ "leaP8",
9662 /* 320 */ "leaP32",
9663 /* 321 */ "leaPIdxOff",
9664 /* 322 */ "leaPIdxScale",
9665 /* 323 */ "leaPPosIdxScale",
9666 /* 324 */ "leaPIdxScaleOff",
9667 /* 325 */ "leaPPosIdxOff",
9668 /* 326 */ "leaPPosIdxScaleOff",
9669 /* 327 */ "leaPCompressedOopOffset",
9670 /* 328 */ "leaP8Narrow",
9671 /* 329 */ "leaP32Narrow",
9672 /* 330 */ "leaPIdxOffNarrow",
9673 /* 331 */ "leaPIdxScaleNarrow",
9674 /* 332 */ "leaPIdxScaleOffNarrow",
9675 /* 333 */ "leaPPosIdxOffNarrow",
9676 /* 334 */ "leaPPosIdxScaleOffNarrow",
9677 /* 335 */ "loadConI",
9678 /* 336 */ "loadConI0",
9679 /* 337 */ "loadConL",
9680 /* 338 */ "loadConL0",
9681 /* 339 */ "loadConUL32",
9682 /* 340 */ "loadConL32",
9683 /* 341 */ "loadConP",
9684 /* 342 */ "loadConP0",
9685 /* 343 */ "loadConP31",
9686 /* 344 */ "loadConF",
9687 /* 345 */ "loadConN0",
9688 /* 346 */ "loadConN",
9689 /* 347 */ "loadConNKlass",
9690 /* 348 */ "loadConF0",
9691 /* 349 */ "loadConD",
9692 /* 350 */ "loadConD0",
9693 /* 351 */ "loadSSI",
9694 /* 352 */ "loadSSL",
9695 /* 353 */ "loadSSP",
9696 /* 354 */ "loadSSF",
9697 /* 355 */ "loadSSD",
9698 /* 356 */ "MoveVec2Leg",
9699 /* 357 */ "MoveLeg2Vec",
9700 /* 358 */ "membar_volatile",
9701 /* 359 */ "castX2P",
9702 /* 360 */ "castP2X",
9703 /* 361 */ "checkCastPP",
9704 /* 362 */ "castPP",
9705 /* 363 */ "castII",
9706 /* 364 */ "castLL",
9707 /* 365 */ "castFF",
9708 /* 366 */ "castDD",
9709 /* 367 */ "storePConditional",
9710 /* 368 */ "storeIConditional",
9711 /* 369 */ "storeLConditional",
9712 /* 370 */ "cmpF_cc_reg",
9713 /* 371 */ "cmpF_cc_reg_CF",
9714 /* 372 */ "cmpF_cc_mem",
9715 /* 373 */ "cmpF_cc_memCF",
9716 /* 374 */ "cmpF_cc_imm",
9717 /* 375 */ "cmpF_cc_immCF",
9718 /* 376 */ "cmpD_cc_reg",
9719 /* 377 */ "cmpD_cc_reg_CF",
9720 /* 378 */ "cmpD_cc_mem",
9721 /* 379 */ "cmpD_cc_memCF",
9722 /* 380 */ "cmpD_cc_imm",
9723 /* 381 */ "cmpD_cc_immCF",
9724 /* 382 */ "MoveF2I_stack_reg",
9725 /* 383 */ "MoveI2F_stack_reg",
9726 /* 384 */ "MoveD2L_stack_reg",
9727 /* 385 */ "MoveL2D_stack_reg_partial",
9728 /* 386 */ "MoveL2D_stack_reg",
9729 /* 387 */ "MoveF2I_reg_reg",
9730 /* 388 */ "MoveD2L_reg_reg",
9731 /* 389 */ "MoveI2F_reg_reg",
9732 /* 390 */ "MoveL2D_reg_reg",
9733 /* 391 */ "overflowAddI_rReg",
9734 /* 392 */ "overflowAddI_rReg_imm",
9735 /* 393 */ "overflowAddL_rReg",
9736 /* 394 */ "overflowAddL_rReg_imm",
9737 /* 395 */ "overflowSubI_rReg",
9738 /* 396 */ "overflowSubI_rReg_imm",
9739 /* 397 */ "overflowSubL_rReg",
9740 /* 398 */ "overflowSubL_rReg_imm",
9741 /* 399 */ "overflowNegI_rReg",
9742 /* 400 */ "overflowNegL_rReg",
9743 /* 401 */ "overflowMulI_rReg",
9744 /* 402 */ "overflowMulI_rReg_imm",
9745 /* 403 */ "overflowMulL_rReg",
9746 /* 404 */ "overflowMulL_rReg_imm",
9747 /* 405 */ "compI_rReg",
9748 /* 406 */ "compI_rReg_imm",
9749 /* 407 */ "compI_rReg_mem",
9750 /* 408 */ "testI_reg",
9751 /* 409 */ "testI_reg_imm",
9752 /* 410 */ "testI_reg_mem",
9753 /* 411 */ "testI_reg_mem_0",
9754 /* 412 */ "compU_rReg",
9755 /* 413 */ "compU_rReg_imm",
9756 /* 414 */ "compU_rReg_mem",
9757 /* 415 */ "testU_reg",
9758 /* 416 */ "compP_rReg",
9759 /* 417 */ "compP_rReg_mem",
9760 /* 418 */ "compP_mem_rReg",
9761 /* 419 */ "testP_reg",
9762 /* 420 */ "testP_mem",
9763 /* 421 */ "testP_mem_reg0",
9764 /* 422 */ "compN_rReg",
9765 /* 423 */ "compN_rReg_mem",
9766 /* 424 */ "compN_rReg_imm",
9767 /* 425 */ "compN_mem_imm",
9768 /* 426 */ "compN_rReg_imm_klass",
9769 /* 427 */ "compN_mem_imm_klass",
9770 /* 428 */ "testN_reg",
9771 /* 429 */ "testN_mem",
9772 /* 430 */ "testN_mem_reg0",
9773 /* 431 */ "compL_rReg",
9774 /* 432 */ "compL_rReg_imm",
9775 /* 433 */ "compL_rReg_mem",
9776 /* 434 */ "testL_reg",
9777 /* 435 */ "testL_reg_imm",
9778 /* 436 */ "testL_reg_mem",
9779 /* 437 */ "testL_reg_mem_0",
9780 /* 438 */ "testL_reg_mem2",
9781 /* 439 */ "testL_reg_mem2_0",
9782 /* 440 */ "compUL_rReg",
9783 /* 441 */ "compUL_rReg_imm",
9784 /* 442 */ "compUL_rReg_mem",
9785 /* 443 */ "testUL_reg",
9786 /* 444 */ "compB_mem_imm",
9787 /* 445 */ "testUB_mem_imm",
9788 /* 446 */ "testB_mem_imm",
9789 /* 447 */ "partialSubtypeCheck_vs_Zero",
9790 /* 448 */ "cmpFastLockRTM",
9791 /* 449 */ "cmpFastLock",
9792 /* 450 */ "cmpFastUnlock",
9793 /* 451 */ "tlsLoadP",
9794 /* 452 */ "absF_reg",
9795 /* 453 */ "absF_reg_reg",
9796 /* 454 */ "absD_reg",
9797 /* 455 */ "absD_reg_reg",
9798 /* 456 */ "negF_reg",
9799 /* 457 */ "negF_reg_reg",
9800 /* 458 */ "negD_reg",
9801 /* 459 */ "negD_reg_reg",
9802 /* 460 */ "reinterpret_mask",
9803 /* 461 */ "reinterpret",
9804 /* 462 */ "vreinterpret_expand",
9805 /* 463 */ "reinterpret_shrink",
9806 /* 464 */ "vsqrtF_reg",
9807 /* 465 */ "vsqrtF_mem",
9808 /* 466 */ "vsqrtD_reg",
9809 /* 467 */ "vsqrtD_mem",
9810 /* 468 */ "vshiftcnt",
9811 /* 469 */ "vshiftcnt_0",
9812 /* 470 */ "vcastBtoX",
9813 /* 471 */ "vcastStoX_evex",
9814 /* 472 */ "vcastItoX_evex",
9815 /* 473 */ "vcastLtoX_evex",
9816 /* 474 */ "vcastFtoD_reg",
9817 /* 475 */ "vcastDtoF_reg",
9818 /* 476 */ "vabsB_reg",
9819 /* 477 */ "vabsS_reg",
9820 /* 478 */ "vabsI_reg",
9821 /* 479 */ "vabsL_reg",
9822 /* 480 */ "cmpvptest_anytrue_lt16",
9823 /* 481 */ "cmpvptest_anytrue_ge16",
9824 /* 482 */ "cmpvptest_anytrue_evex",
9825 /* 483 */ "vmaskcast_evex",
9826 /* 484 */ "vmaskcast",
9827 /* 485 */ "loadShuffleB",
9828 /* 486 */ "loadShuffleS_evex",
9829 /* 487 */ "loadShuffleI_avx",
9830 /* 488 */ "loadShuffleL_evex",
9831 /* 489 */ "vpopcountI",
9832 /* 490 */ "long_to_mask_evex",
9833 /* 491 */ "castMM",
9834 /* 492 */ "castVV",
9835 /* 493 */ "castVVLeg",
9836 /* 494 */ "loadB",
9837 /* 495 */ "loadB2L",
9838 /* 496 */ "loadUB",
9839 /* 497 */ "loadUB2L",
9840 /* 498 */ "loadUB2L_immI",
9841 /* 499 */ "loadS",
9842 /* 500 */ "loadS2B",
9843 /* 501 */ "loadS2L",
9844 /* 502 */ "loadUS",
9845 /* 503 */ "loadUS2B",
9846 /* 504 */ "loadUS2L",
9847 /* 505 */ "loadUS2L_immI_255",
9848 /* 506 */ "loadUS2L_immI",
9849 /* 507 */ "loadI",
9850 /* 508 */ "loadI2B",
9851 /* 509 */ "loadI2UB",
9852 /* 510 */ "loadI2S",
9853 /* 511 */ "loadI2US",
9854 /* 512 */ "loadI2L",
9855 /* 513 */ "loadI2L_immI_255",
9856 /* 514 */ "loadI2L_immI_65535",
9857 /* 515 */ "loadI2L_immU31",
9858 /* 516 */ "loadUI2L",
9859 /* 517 */ "loadL",
9860 /* 518 */ "loadRange",
9861 /* 519 */ "loadP",
9862 /* 520 */ "loadN",
9863 /* 521 */ "loadKlass",
9864 /* 522 */ "loadNKlass",
9865 /* 523 */ "loadF",
9866 /* 524 */ "loadD_partial",
9867 /* 525 */ "loadD",
9868 /* 526 */ "maxF_reg",
9869 /* 527 */ "maxF_reduction_reg",
9870 /* 528 */ "maxD_reg",
9871 /* 529 */ "maxD_reduction_reg",
9872 /* 530 */ "minF_reg",
9873 /* 531 */ "minF_reduction_reg",
9874 /* 532 */ "minD_reg",
9875 /* 533 */ "minD_reduction_reg",
9876 /* 534 */ "prefetchAlloc",
9877 /* 535 */ "prefetchAllocNTA",
9878 /* 536 */ "prefetchAllocT0",
9879 /* 537 */ "prefetchAllocT2",
9880 /* 538 */ "storeB",
9881 /* 539 */ "storeC",
9882 /* 540 */ "storeI",
9883 /* 541 */ "storeL",
9884 /* 542 */ "storeP",
9885 /* 543 */ "storeImmP0",
9886 /* 544 */ "storeImmP",
9887 /* 545 */ "storeN",
9888 /* 546 */ "storeNKlass",
9889 /* 547 */ "storeImmN0",
9890 /* 548 */ "storeImmN",
9891 /* 549 */ "storeImmNKlass",
9892 /* 550 */ "storeImmI0",
9893 /* 551 */ "storeImmI",
9894 /* 552 */ "storeImmL0",
9895 /* 553 */ "storeImmL",
9896 /* 554 */ "storeImmC0",
9897 /* 555 */ "storeImmI16",
9898 /* 556 */ "storeImmB0",
9899 /* 557 */ "storeImmB",
9900 /* 558 */ "storeImmCM0_reg",
9901 /* 559 */ "storeImmCM0",
9902 /* 560 */ "storeF",
9903 /* 561 */ "storeF0",
9904 /* 562 */ "storeF_imm",
9905 /* 563 */ "storeD",
9906 /* 564 */ "storeD0_imm",
9907 /* 565 */ "storeD0",
9908 /* 566 */ "cacheWB",
9909 /* 567 */ "cacheWBPreSync",
9910 /* 568 */ "cacheWBPostSync",
9911 /* 569 */ "bytes_reverse_int",
9912 /* 570 */ "bytes_reverse_long",
9913 /* 571 */ "bytes_reverse_unsigned_short",
9914 /* 572 */ "bytes_reverse_short",
9915 /* 573 */ "countLeadingZerosI",
9916 /* 574 */ "countLeadingZerosI_bsr",
9917 /* 575 */ "countLeadingZerosL",
9918 /* 576 */ "countLeadingZerosL_bsr",
9919 /* 577 */ "countTrailingZerosI",
9920 /* 578 */ "countTrailingZerosI_bsf",
9921 /* 579 */ "countTrailingZerosL",
9922 /* 580 */ "countTrailingZerosL_bsf",
9923 /* 581 */ "popCountI",
9924 /* 582 */ "popCountI_mem",
9925 /* 583 */ "popCountL",
9926 /* 584 */ "popCountL_mem",
9927 /* 585 */ "membar_acquire",
9928 /* 586 */ "membar_acquire_0",
9929 /* 587 */ "membar_acquire_lock",
9930 /* 588 */ "membar_release",
9931 /* 589 */ "membar_release_0",
9932 /* 590 */ "membar_release_lock",
9933 /* 591 */ "unnecessary_membar_volatile",
9934 /* 592 */ "membar_storestore",
9935 /* 593 */ "membar_storestore_0",
9936 /* 594 */ "convP2I",
9937 /* 595 */ "convN2I",
9938 /* 596 */ "encodeHeapOop",
9939 /* 597 */ "encodeHeapOop_not_null",
9940 /* 598 */ "decodeHeapOop",
9941 /* 599 */ "decodeHeapOop_not_null",
9942 /* 600 */ "encodeKlass_not_null",
9943 /* 601 */ "decodeKlass_not_null",
9944 /* 602 */ "jumpXtnd_offset",
9945 /* 603 */ "jumpXtnd_addr",
9946 /* 604 */ "jumpXtnd",
9947 /* 605 */ "cmovI_reg",
9948 /* 606 */ "cmovI_regU",
9949 /* 607 */ "cmovI_regUCF",
9950 /* 608 */ "cmovI_mem",
9951 /* 609 */ "cmovI_memU",
9952 /* 610 */ "cmovI_memUCF",
9953 /* 611 */ "cmovN_reg",
9954 /* 612 */ "cmovN_regU",
9955 /* 613 */ "cmovN_regUCF",
9956 /* 614 */ "cmovP_reg",
9957 /* 615 */ "cmovP_regU",
9958 /* 616 */ "cmovP_regUCF",
9959 /* 617 */ "cmovL_reg",
9960 /* 618 */ "cmovL_mem",
9961 /* 619 */ "cmovL_regU",
9962 /* 620 */ "cmovL_regUCF",
9963 /* 621 */ "cmovL_memU",
9964 /* 622 */ "cmovL_memUCF",
9965 /* 623 */ "cmovF_reg",
9966 /* 624 */ "cmovF_regU",
9967 /* 625 */ "cmovF_regUCF",
9968 /* 626 */ "cmovD_reg",
9969 /* 627 */ "cmovD_regU",
9970 /* 628 */ "cmovD_regUCF",
9971 /* 629 */ "addI_rReg",
9972 /* 630 */ "addI_rReg_imm",
9973 /* 631 */ "addI_rReg_mem",
9974 /* 632 */ "addI_rReg_mem_0",
9975 /* 633 */ "addI_mem_rReg",
9976 /* 634 */ "addI_mem_rReg_0",
9977 /* 635 */ "addI_mem_imm",
9978 /* 636 */ "incI_rReg",
9979 /* 637 */ "incI_mem",
9980 /* 638 */ "decI_rReg",
9981 /* 639 */ "decI_mem",
9982 /* 640 */ "leaI_rReg_immI",
9983 /* 641 */ "addL_rReg",
9984 /* 642 */ "addL_rReg_imm",
9985 /* 643 */ "addL_rReg_mem",
9986 /* 644 */ "addL_rReg_mem_0",
9987 /* 645 */ "addL_mem_rReg",
9988 /* 646 */ "addL_mem_rReg_0",
9989 /* 647 */ "addL_mem_imm",
9990 /* 648 */ "incL_rReg",
9991 /* 649 */ "incL_mem",
9992 /* 650 */ "decL_rReg",
9993 /* 651 */ "decL_mem",
9994 /* 652 */ "leaL_rReg_immL",
9995 /* 653 */ "addP_rReg",
9996 /* 654 */ "addP_rReg_imm",
9997 /* 655 */ "leaP_rReg_imm",
9998 /* 656 */ "loadPLocked",
9999 /* 657 */ "compareAndSwapP",
10000 /* 658 */ "compareAndSwapP_0",
10001 /* 659 */ "compareAndSwapL",
10002 /* 660 */ "compareAndSwapL_0",
10003 /* 661 */ "compareAndSwapI",
10004 /* 662 */ "compareAndSwapI_0",
10005 /* 663 */ "compareAndSwapB",
10006 /* 664 */ "compareAndSwapB_0",
10007 /* 665 */ "compareAndSwapS",
10008 /* 666 */ "compareAndSwapS_0",
10009 /* 667 */ "compareAndSwapN",
10010 /* 668 */ "compareAndSwapN_0",
10011 /* 669 */ "compareAndExchangeB",
10012 /* 670 */ "compareAndExchangeS",
10013 /* 671 */ "compareAndExchangeI",
10014 /* 672 */ "compareAndExchangeL",
10015 /* 673 */ "compareAndExchangeN",
10016 /* 674 */ "compareAndExchangeP",
10017 /* 675 */ "xaddB_no_res",
10018 /* 676 */ "xaddB",
10019 /* 677 */ "xaddS_no_res",
10020 /* 678 */ "xaddS",
10021 /* 679 */ "xaddI_no_res",
10022 /* 680 */ "xaddI",
10023 /* 681 */ "xaddL_no_res",
10024 /* 682 */ "xaddL",
10025 /* 683 */ "xchgB",
10026 /* 684 */ "xchgS",
10027 /* 685 */ "xchgI",
10028 /* 686 */ "xchgL",
10029 /* 687 */ "xchgP",
10030 /* 688 */ "xchgN",
10031 /* 689 */ "absI_rReg",
10032 /* 690 */ "absL_rReg",
10033 /* 691 */ "subI_rReg",
10034 /* 692 */ "subI_rReg_imm",
10035 /* 693 */ "subI_rReg_mem",
10036 /* 694 */ "subI_mem_rReg",
10037 /* 695 */ "subI_mem_imm",
10038 /* 696 */ "subL_rReg",
10039 /* 697 */ "subL_rReg_imm",
10040 /* 698 */ "subL_rReg_mem",
10041 /* 699 */ "subL_mem_rReg",
10042 /* 700 */ "subL_mem_imm",
10043 /* 701 */ "subP_rReg",
10044 /* 702 */ "negI_rReg",
10045 /* 703 */ "negI_rReg_2",
10046 /* 704 */ "negI_mem",
10047 /* 705 */ "negL_rReg",
10048 /* 706 */ "negL_rReg_2",
10049 /* 707 */ "negL_mem",
10050 /* 708 */ "mulI_rReg",
10051 /* 709 */ "mulI_rReg_imm",
10052 /* 710 */ "mulI_mem",
10053 /* 711 */ "mulI_mem_0",
10054 /* 712 */ "mulI_mem_imm",
10055 /* 713 */ "mulAddS2I_rReg",
10056 /* 714 */ "mulL_rReg",
10057 /* 715 */ "mulL_rReg_imm",
10058 /* 716 */ "mulL_mem",
10059 /* 717 */ "mulL_mem_0",
10060 /* 718 */ "mulL_mem_imm",
10061 /* 719 */ "mulHiL_rReg",
10062 /* 720 */ "umulHiL_rReg",
10063 /* 721 */ "divI_rReg",
10064 /* 722 */ "divL_rReg",
10065 /* 723 */ "divModI_rReg_divmod",
10066 /* 724 */ "divModL_rReg_divmod",
10067 /* 725 */ "loadConL_0x6666666666666667",
10068 /* 726 */ "mul_hi",
10069 /* 727 */ "sarL_rReg_63",
10070 /* 728 */ "sarL_rReg_2",
10071 /* 729 */ "divL_10",
10072 /* 730 */ "modI_rReg",
10073 /* 731 */ "modL_rReg",
10074 /* 732 */ "salI_rReg_1",
10075 /* 733 */ "salI_mem_1",
10076 /* 734 */ "salI_rReg_imm",
10077 /* 735 */ "salI_mem_imm",
10078 /* 736 */ "salI_rReg_CL",
10079 /* 737 */ "salI_mem_CL",
10080 /* 738 */ "sarI_rReg_1",
10081 /* 739 */ "sarI_mem_1",
10082 /* 740 */ "sarI_rReg_imm",
10083 /* 741 */ "sarI_mem_imm",
10084 /* 742 */ "sarI_rReg_CL",
10085 /* 743 */ "sarI_mem_CL",
10086 /* 744 */ "shrI_rReg_1",
10087 /* 745 */ "shrI_mem_1",
10088 /* 746 */ "shrI_rReg_imm",
10089 /* 747 */ "shrI_mem_imm",
10090 /* 748 */ "shrI_rReg_CL",
10091 /* 749 */ "shrI_mem_CL",
10092 /* 750 */ "salL_rReg_1",
10093 /* 751 */ "salL_mem_1",
10094 /* 752 */ "salL_rReg_imm",
10095 /* 753 */ "salL_mem_imm",
10096 /* 754 */ "salL_rReg_CL",
10097 /* 755 */ "salL_mem_CL",
10098 /* 756 */ "sarL_rReg_1",
10099 /* 757 */ "sarL_mem_1",
10100 /* 758 */ "sarL_rReg_imm",
10101 /* 759 */ "sarL_mem_imm",
10102 /* 760 */ "sarL_rReg_CL",
10103 /* 761 */ "sarL_mem_CL",
10104 /* 762 */ "shrL_rReg_1",
10105 /* 763 */ "shrL_mem_1",
10106 /* 764 */ "shrL_rReg_imm",
10107 /* 765 */ "shrL_mem_imm",
10108 /* 766 */ "shrL_rReg_CL",
10109 /* 767 */ "shrL_mem_CL",
10110 /* 768 */ "i2b",
10111 /* 769 */ "i2s",
10112 /* 770 */ "rolI_imm",
10113 /* 771 */ "rolI_rReg_Var",
10114 /* 772 */ "rorI_immI8_legacy",
10115 /* 773 */ "rorI_immI8",
10116 /* 774 */ "rorI_rReg_Var",
10117 /* 775 */ "rolL_immI8",
10118 /* 776 */ "rolL_rReg_Var",
10119 /* 777 */ "rorL_immI8_legacy",
10120 /* 778 */ "rorL_immI8",
10121 /* 779 */ "rorL_rReg_Var",
10122 /* 780 */ "andI_rReg",
10123 /* 781 */ "andI_rReg_imm255",
10124 /* 782 */ "andI2L_rReg_imm255",
10125 /* 783 */ "andI_rReg_imm65535",
10126 /* 784 */ "andI2L_rReg_imm65535",
10127 /* 785 */ "convI2LAndI_reg_immIbitmask",
10128 /* 786 */ "andI_rReg_imm",
10129 /* 787 */ "andI_rReg_mem",
10130 /* 788 */ "andI_rReg_mem_0",
10131 /* 789 */ "andB_mem_rReg",
10132 /* 790 */ "andB_mem_rReg_0",
10133 /* 791 */ "andI_mem_rReg",
10134 /* 792 */ "andI_mem_rReg_0",
10135 /* 793 */ "andI_mem_imm",
10136 /* 794 */ "andnI_rReg_rReg_mem",
10137 /* 795 */ "andnI_rReg_rReg_mem_0",
10138 /* 796 */ "andnI_rReg_rReg_rReg",
10139 /* 797 */ "andnI_rReg_rReg_rReg_0",
10140 /* 798 */ "blsiI_rReg_rReg",
10141 /* 799 */ "blsiI_rReg_rReg_0",
10142 /* 800 */ "blsiI_rReg_mem",
10143 /* 801 */ "blsiI_rReg_mem_0",
10144 /* 802 */ "blsmskI_rReg_mem",
10145 /* 803 */ "blsmskI_rReg_mem_0",
10146 /* 804 */ "blsmskI_rReg_rReg",
10147 /* 805 */ "blsmskI_rReg_rReg_0",
10148 /* 806 */ "blsrI_rReg_rReg",
10149 /* 807 */ "blsrI_rReg_rReg_0",
10150 /* 808 */ "blsrI_rReg_mem",
10151 /* 809 */ "blsrI_rReg_mem_0",
10152 /* 810 */ "orI_rReg",
10153 /* 811 */ "orI_rReg_imm",
10154 /* 812 */ "orI_rReg_mem",
10155 /* 813 */ "orI_rReg_mem_0",
10156 /* 814 */ "orB_mem_rReg",
10157 /* 815 */ "orB_mem_rReg_0",
10158 /* 816 */ "orI_mem_rReg",
10159 /* 817 */ "orI_mem_rReg_0",
10160 /* 818 */ "orI_mem_imm",
10161 /* 819 */ "xorI_rReg",
10162 /* 820 */ "xorI_rReg_im1",
10163 /* 821 */ "xorI_rReg_imm",
10164 /* 822 */ "xorI_rReg_mem",
10165 /* 823 */ "xorI_rReg_mem_0",
10166 /* 824 */ "xorB_mem_rReg",
10167 /* 825 */ "xorB_mem_rReg_0",
10168 /* 826 */ "xorI_mem_rReg",
10169 /* 827 */ "xorI_mem_rReg_0",
10170 /* 828 */ "xorI_mem_imm",
10171 /* 829 */ "andL_rReg",
10172 /* 830 */ "andL_rReg_imm255",
10173 /* 831 */ "andL_rReg_imm65535",
10174 /* 832 */ "andL_rReg_imm",
10175 /* 833 */ "andL_rReg_mem",
10176 /* 834 */ "andL_rReg_mem_0",
10177 /* 835 */ "andL_mem_rReg",
10178 /* 836 */ "andL_mem_rReg_0",
10179 /* 837 */ "andL_mem_imm",
10180 /* 838 */ "btrL_mem_imm",
10181 /* 839 */ "andnL_rReg_rReg_mem",
10182 /* 840 */ "andnL_rReg_rReg_mem_0",
10183 /* 841 */ "andnL_rReg_rReg_rReg",
10184 /* 842 */ "andnL_rReg_rReg_rReg_0",
10185 /* 843 */ "blsiL_rReg_rReg",
10186 /* 844 */ "blsiL_rReg_rReg_0",
10187 /* 845 */ "blsiL_rReg_mem",
10188 /* 846 */ "blsiL_rReg_mem_0",
10189 /* 847 */ "blsmskL_rReg_mem",
10190 /* 848 */ "blsmskL_rReg_mem_0",
10191 /* 849 */ "blsmskL_rReg_rReg",
10192 /* 850 */ "blsmskL_rReg_rReg_0",
10193 /* 851 */ "blsrL_rReg_rReg",
10194 /* 852 */ "blsrL_rReg_rReg_0",
10195 /* 853 */ "blsrL_rReg_mem",
10196 /* 854 */ "blsrL_rReg_mem_0",
10197 /* 855 */ "orL_rReg",
10198 /* 856 */ "orL_rReg_castP2X",
10199 /* 857 */ "orL_rReg_castP2X_0",
10200 /* 858 */ "orL_rReg_imm",
10201 /* 859 */ "orL_rReg_mem",
10202 /* 860 */ "orL_rReg_mem_0",
10203 /* 861 */ "orL_mem_rReg",
10204 /* 862 */ "orL_mem_rReg_0",
10205 /* 863 */ "orL_mem_imm",
10206 /* 864 */ "btsL_mem_imm",
10207 /* 865 */ "xorL_rReg",
10208 /* 866 */ "xorL_rReg_im1",
10209 /* 867 */ "xorL_rReg_imm",
10210 /* 868 */ "xorL_rReg_mem",
10211 /* 869 */ "xorL_rReg_mem_0",
10212 /* 870 */ "xorL_mem_rReg",
10213 /* 871 */ "xorL_mem_rReg_0",
10214 /* 872 */ "xorL_mem_imm",
10215 /* 873 */ "convI2B",
10216 /* 874 */ "convP2B",
10217 /* 875 */ "cmpLTMask",
10218 /* 876 */ "cmpLTMask0",
10219 /* 877 */ "cadd_cmpLTMask",
10220 /* 878 */ "cadd_cmpLTMask_1",
10221 /* 879 */ "cadd_cmpLTMask_0",
10222 /* 880 */ "cadd_cmpLTMask_2",
10223 /* 881 */ "and_cmpLTMask",
10224 /* 882 */ "and_cmpLTMask_0",
10225 /* 883 */ "cmpF_reg",
10226 /* 884 */ "cmpF_mem",
10227 /* 885 */ "cmpF_imm",
10228 /* 886 */ "cmpD_reg",
10229 /* 887 */ "cmpD_mem",
10230 /* 888 */ "cmpD_imm",
10231 /* 889 */ "convF2D_reg_reg",
10232 /* 890 */ "convF2D_reg_mem",
10233 /* 891 */ "convD2F_reg_reg",
10234 /* 892 */ "convD2F_reg_mem",
10235 /* 893 */ "convF2I_reg_reg",
10236 /* 894 */ "convF2L_reg_reg",
10237 /* 895 */ "convD2I_reg_reg",
10238 /* 896 */ "convD2L_reg_reg",
10239 /* 897 */ "convI2F_reg_reg",
10240 /* 898 */ "convI2F_reg_mem",
10241 /* 899 */ "convI2D_reg_reg",
10242 /* 900 */ "convI2D_reg_mem",
10243 /* 901 */ "convXI2F_reg",
10244 /* 902 */ "convXI2D_reg",
10245 /* 903 */ "convL2F_reg_reg",
10246 /* 904 */ "convL2F_reg_mem",
10247 /* 905 */ "convL2D_reg_reg",
10248 /* 906 */ "convL2D_reg_mem",
10249 /* 907 */ "convI2L_reg_reg",
10250 /* 908 */ "convI2L_reg_reg_zex",
10251 /* 909 */ "convI2L_reg_mem_zex",
10252 /* 910 */ "zerox_long_reg_reg",
10253 /* 911 */ "convL2I_reg_reg",
10254 /* 912 */ "MoveF2I_reg_stack",
10255 /* 913 */ "MoveI2F_reg_stack",
10256 /* 914 */ "MoveD2L_reg_stack",
10257 /* 915 */ "MoveL2D_reg_stack",
10258 /* 916 */ "rep_stos",
10259 /* 917 */ "rep_stos_evex",
10260 /* 918 */ "rep_stos_large",
10261 /* 919 */ "rep_stos_large_evex",
10262 /* 920 */ "rep_stos_im",
10263 /* 921 */ "string_compareL",
10264 /* 922 */ "string_compareL_evex",
10265 /* 923 */ "string_compareU",
10266 /* 924 */ "string_compareU_evex",
10267 /* 925 */ "string_compareLU",
10268 /* 926 */ "string_compareLU_evex",
10269 /* 927 */ "string_compareUL",
10270 /* 928 */ "string_compareUL_evex",
10271 /* 929 */ "string_indexof_conL",
10272 /* 930 */ "string_indexof_conU",
10273 /* 931 */ "string_indexof_conUL",
10274 /* 932 */ "string_indexofL",
10275 /* 933 */ "string_indexofU",
10276 /* 934 */ "string_indexofUL",
10277 /* 935 */ "string_indexof_char",
10278 /* 936 */ "stringL_indexof_char",
10279 /* 937 */ "string_equals",
10280 /* 938 */ "string_equals_evex",
10281 /* 939 */ "array_equalsB",
10282 /* 940 */ "array_equalsB_evex",
10283 /* 941 */ "array_equalsC",
10284 /* 942 */ "array_equalsC_evex",
10285 /* 943 */ "has_negatives",
10286 /* 944 */ "has_negatives_evex",
10287 /* 945 */ "string_compress",
10288 /* 946 */ "string_compress_evex",
10289 /* 947 */ "string_inflate",
10290 /* 948 */ "string_inflate_evex",
10291 /* 949 */ "encode_iso_array",
10292 /* 950 */ "encode_ascii_array",
10293 /* 951 */ "cmpL3_reg_reg",
10294 /* 952 */ "cmovI_reg_g",
10295 /* 953 */ "minI_rReg",
10296 /* 954 */ "cmovI_reg_l",
10297 /* 955 */ "maxI_rReg",
10298 /* 956 */ "jmpDir",
10299 /* 957 */ "jmpCon",
10300 /* 958 */ "jmpLoopEnd",
10301 /* 959 */ "jmpLoopEndU",
10302 /* 960 */ "jmpLoopEndUCF",
10303 /* 961 */ "jmpLoopEnd_and_restoreMask",
10304 /* 962 */ "jmpLoopEndU_and_restoreMask",
10305 /* 963 */ "jmpLoopEndUCF_and_restoreMask",
10306 /* 964 */ "jmpConU",
10307 /* 965 */ "jmpConUCF",
10308 /* 966 */ "jmpConUCF2",
10309 /* 967 */ "partialSubtypeCheck",
10310 /* 968 */ "jmpDir_short",
10311 /* 969 */ "jmpCon_short",
10312 /* 970 */ "jmpLoopEnd_short",
10313 /* 971 */ "jmpLoopEndU_short",
10314 /* 972 */ "jmpLoopEndUCF_short",
10315 /* 973 */ "jmpConU_short",
10316 /* 974 */ "jmpConUCF_short",
10317 /* 975 */ "jmpConUCF2_short",
10318 /* 976 */ "safePoint_poll_tls",
10319 /* 977 */ "CallStaticJavaDirect",
10320 /* 978 */ "CallDynamicJavaDirect",
10321 /* 979 */ "CallRuntimeDirect",
10322 /* 980 */ "CallLeafDirect",
10323 /* 981 */ "CallLeafDirectVector",
10324 /* 982 */ "CallNativeDirect",
10325 /* 983 */ "CallLeafNoFPDirect",
10326 /* 984 */ "Ret",
10327 /* 985 */ "TailCalljmpInd",
10328 /* 986 */ "tailjmpInd",
10329 /* 987 */ "CreateException",
10330 /* 988 */ "RethrowException",
10331 /* 989 */ "ShouldNotReachHere",
10332 /* 990 */ "setMask",
10333 /* 991 */ "addF_reg",
10334 /* 992 */ "addF_mem",
10335 /* 993 */ "addF_mem_0",
10336 /* 994 */ "addF_imm",
10337 /* 995 */ "addF_reg_reg",
10338 /* 996 */ "addF_reg_mem",
10339 /* 997 */ "addF_reg_mem_0",
10340 /* 998 */ "addF_reg_imm",
10341 /* 999 */ "addD_reg",
10342 /* 1000 */ "addD_mem",
10343 /* 1001 */ "addD_mem_0",
10344 /* 1002 */ "addD_imm",
10345 /* 1003 */ "addD_reg_reg",
10346 /* 1004 */ "addD_reg_mem",
10347 /* 1005 */ "addD_reg_mem_0",
10348 /* 1006 */ "addD_reg_imm",
10349 /* 1007 */ "subF_reg",
10350 /* 1008 */ "subF_mem",
10351 /* 1009 */ "subF_imm",
10352 /* 1010 */ "subF_reg_reg",
10353 /* 1011 */ "subF_reg_mem",
10354 /* 1012 */ "subF_reg_imm",
10355 /* 1013 */ "subD_reg",
10356 /* 1014 */ "subD_mem",
10357 /* 1015 */ "subD_imm",
10358 /* 1016 */ "subD_reg_reg",
10359 /* 1017 */ "subD_reg_mem",
10360 /* 1018 */ "subD_reg_imm",
10361 /* 1019 */ "mulF_reg",
10362 /* 1020 */ "mulF_mem",
10363 /* 1021 */ "mulF_mem_0",
10364 /* 1022 */ "mulF_imm",
10365 /* 1023 */ "mulF_reg_reg",
10366 /* 1024 */ "mulF_reg_mem",
10367 /* 1025 */ "mulF_reg_mem_0",
10368 /* 1026 */ "mulF_reg_imm",
10369 /* 1027 */ "mulD_reg",
10370 /* 1028 */ "mulD_mem",
10371 /* 1029 */ "mulD_mem_0",
10372 /* 1030 */ "mulD_imm",
10373 /* 1031 */ "mulD_reg_reg",
10374 /* 1032 */ "mulD_reg_mem",
10375 /* 1033 */ "mulD_reg_mem_0",
10376 /* 1034 */ "mulD_reg_imm",
10377 /* 1035 */ "divF_reg",
10378 /* 1036 */ "divF_mem",
10379 /* 1037 */ "divF_imm",
10380 /* 1038 */ "divF_reg_reg",
10381 /* 1039 */ "divF_reg_mem",
10382 /* 1040 */ "divF_reg_imm",
10383 /* 1041 */ "divD_reg",
10384 /* 1042 */ "divD_mem",
10385 /* 1043 */ "divD_imm",
10386 /* 1044 */ "divD_reg_reg",
10387 /* 1045 */ "divD_reg_mem",
10388 /* 1046 */ "divD_reg_imm",
10389 /* 1047 */ "sqrtF_reg",
10390 /* 1048 */ "sqrtD_reg",
10391 /* 1049 */ "reinterpret_mask_W2B",
10392 /* 1050 */ "reinterpret_mask_D2B",
10393 /* 1051 */ "reinterpret_mask_Q2B",
10394 /* 1052 */ "reinterpret_expand",
10395 /* 1053 */ "vreinterpret_expand4",
10396 /* 1054 */ "roundD_reg",
10397 /* 1055 */ "roundD_mem",
10398 /* 1056 */ "roundD_imm",
10399 /* 1057 */ "vroundD_reg",
10400 /* 1058 */ "vround8D_reg",
10401 /* 1059 */ "vroundD_mem",
10402 /* 1060 */ "vround8D_mem",
10403 /* 1061 */ "onspinwait",
10404 /* 1062 */ "fmaD_reg",
10405 /* 1063 */ "fmaF_reg",
10406 /* 1064 */ "loadV",
10407 /* 1065 */ "storeV",
10408 /* 1066 */ "gather",
10409 /* 1067 */ "evgather",
10410 /* 1068 */ "evgather_masked",
10411 /* 1069 */ "scatter",
10412 /* 1070 */ "scatter_masked",
10413 /* 1071 */ "ReplB_reg",
10414 /* 1072 */ "ReplB_mem",
10415 /* 1073 */ "ReplB_imm",
10416 /* 1074 */ "ReplB_zero",
10417 /* 1075 */ "ReplS_reg",
10418 /* 1076 */ "ReplS_mem",
10419 /* 1077 */ "ReplS_imm",
10420 /* 1078 */ "ReplS_zero",
10421 /* 1079 */ "ReplI_reg",
10422 /* 1080 */ "ReplI_mem",
10423 /* 1081 */ "ReplI_imm",
10424 /* 1082 */ "ReplI_zero",
10425 /* 1083 */ "ReplI_M1",
10426 /* 1084 */ "ReplI_M1_0",
10427 /* 1085 */ "ReplI_M1_1",
10428 /* 1086 */ "ReplL_reg",
10429 /* 1087 */ "ReplL_mem",
10430 /* 1088 */ "ReplL_imm",
10431 /* 1089 */ "ReplL_zero",
10432 /* 1090 */ "ReplL_M1",
10433 /* 1091 */ "ReplF_reg",
10434 /* 1092 */ "ReplF_mem",
10435 /* 1093 */ "ReplF_zero",
10436 /* 1094 */ "ReplD_reg",
10437 /* 1095 */ "ReplD_mem",
10438 /* 1096 */ "ReplD_zero",
10439 /* 1097 */ "insert",
10440 /* 1098 */ "insert32",
10441 /* 1099 */ "insert64",
10442 /* 1100 */ "insert2L",
10443 /* 1101 */ "insert4L",
10444 /* 1102 */ "insert8L",
10445 /* 1103 */ "insertF",
10446 /* 1104 */ "vinsertF",
10447 /* 1105 */ "insert2D",
10448 /* 1106 */ "insert4D",
10449 /* 1107 */ "insert8D",
10450 /* 1108 */ "reductionI",
10451 /* 1109 */ "reductionI_0",
10452 /* 1110 */ "reductionI_1",
10453 /* 1111 */ "reductionI_2",
10454 /* 1112 */ "reductionI_3",
10455 /* 1113 */ "reductionI_4",
10456 /* 1114 */ "reductionI_5",
10457 /* 1115 */ "reductionL",
10458 /* 1116 */ "reductionL_0",
10459 /* 1117 */ "reductionL_1",
10460 /* 1118 */ "reductionL_2",
10461 /* 1119 */ "reductionL_3",
10462 /* 1120 */ "reductionL_4",
10463 /* 1121 */ "reductionL_5",
10464 /* 1122 */ "reductionL_avx512dq",
10465 /* 1123 */ "reductionL_avx512dq_0",
10466 /* 1124 */ "reductionL_avx512dq_1",
10467 /* 1125 */ "reductionL_avx512dq_2",
10468 /* 1126 */ "reductionL_avx512dq_3",
10469 /* 1127 */ "reductionL_avx512dq_4",
10470 /* 1128 */ "reductionL_avx512dq_5",
10471 /* 1129 */ "reductionF128",
10472 /* 1130 */ "reductionF128_0",
10473 /* 1131 */ "reduction8F",
10474 /* 1132 */ "reduction8F_0",
10475 /* 1133 */ "reduction16F",
10476 /* 1134 */ "reduction16F_0",
10477 /* 1135 */ "reduction2D",
10478 /* 1136 */ "reduction2D_0",
10479 /* 1137 */ "reduction4D",
10480 /* 1138 */ "reduction4D_0",
10481 /* 1139 */ "reduction8D",
10482 /* 1140 */ "reduction8D_0",
10483 /* 1141 */ "reductionB",
10484 /* 1142 */ "reductionB_0",
10485 /* 1143 */ "reductionB_1",
10486 /* 1144 */ "reductionB_2",
10487 /* 1145 */ "reductionB_3",
10488 /* 1146 */ "reductionB_4",
10489 /* 1147 */ "reductionB_avx512bw",
10490 /* 1148 */ "reductionB_avx512bw_0",
10491 /* 1149 */ "reductionB_avx512bw_1",
10492 /* 1150 */ "reductionB_avx512bw_2",
10493 /* 1151 */ "reductionB_avx512bw_3",
10494 /* 1152 */ "reductionB_avx512bw_4",
10495 /* 1153 */ "reductionS",
10496 /* 1154 */ "reductionS_0",
10497 /* 1155 */ "reductionS_1",
10498 /* 1156 */ "reductionS_2",
10499 /* 1157 */ "reductionS_3",
10500 /* 1158 */ "reductionS_4",
10501 /* 1159 */ "reductionS_5",
10502 /* 1160 */ "mul_reductionB",
10503 /* 1161 */ "mul_reduction64B",
10504 /* 1162 */ "minmax_reduction2F",
10505 /* 1163 */ "minmax_reduction2F_0",
10506 /* 1164 */ "minmax_reductionF",
10507 /* 1165 */ "minmax_reductionF_0",
10508 /* 1166 */ "minmax_reduction2F_av",
10509 /* 1167 */ "minmax_reduction2F_av_0",
10510 /* 1168 */ "minmax_reductionF_av",
10511 /* 1169 */ "minmax_reductionF_av_0",
10512 /* 1170 */ "minmax_reduction2D",
10513 /* 1171 */ "minmax_reduction2D_0",
10514 /* 1172 */ "minmax_reductionD",
10515 /* 1173 */ "minmax_reductionD_0",
10516 /* 1174 */ "minmax_reduction2D_av",
10517 /* 1175 */ "minmax_reduction2D_av_0",
10518 /* 1176 */ "minmax_reductionD_av",
10519 /* 1177 */ "minmax_reductionD_av_0",
10520 /* 1178 */ "vaddB",
10521 /* 1179 */ "vaddB_reg",
10522 /* 1180 */ "vaddB_mem",
10523 /* 1181 */ "vaddB_mem_0",
10524 /* 1182 */ "vaddS",
10525 /* 1183 */ "vaddS_reg",
10526 /* 1184 */ "vaddS_mem",
10527 /* 1185 */ "vaddS_mem_0",
10528 /* 1186 */ "vaddI",
10529 /* 1187 */ "vaddI_reg",
10530 /* 1188 */ "vaddI_mem",
10531 /* 1189 */ "vaddI_mem_0",
10532 /* 1190 */ "vaddL",
10533 /* 1191 */ "vaddL_reg",
10534 /* 1192 */ "vaddL_mem",
10535 /* 1193 */ "vaddL_mem_0",
10536 /* 1194 */ "vaddF",
10537 /* 1195 */ "vaddF_reg",
10538 /* 1196 */ "vaddF_mem",
10539 /* 1197 */ "vaddF_mem_0",
10540 /* 1198 */ "vaddD",
10541 /* 1199 */ "vaddD_reg",
10542 /* 1200 */ "vaddD_mem",
10543 /* 1201 */ "vaddD_mem_0",
10544 /* 1202 */ "vsubB",
10545 /* 1203 */ "vsubB_reg",
10546 /* 1204 */ "vsubB_mem",
10547 /* 1205 */ "vsubS",
10548 /* 1206 */ "vsubS_reg",
10549 /* 1207 */ "vsubS_mem",
10550 /* 1208 */ "vsubI",
10551 /* 1209 */ "vsubI_reg",
10552 /* 1210 */ "vsubI_mem",
10553 /* 1211 */ "vsubL",
10554 /* 1212 */ "vsubL_reg",
10555 /* 1213 */ "vsubL_mem",
10556 /* 1214 */ "vsubF",
10557 /* 1215 */ "vsubF_reg",
10558 /* 1216 */ "vsubF_mem",
10559 /* 1217 */ "vsubD",
10560 /* 1218 */ "vsubD_reg",
10561 /* 1219 */ "vsubD_mem",
10562 /* 1220 */ "mulB_reg",
10563 /* 1221 */ "mul16B_reg",
10564 /* 1222 */ "vmul16B_reg_avx",
10565 /* 1223 */ "vmul32B_reg_avx",
10566 /* 1224 */ "vmul64B_reg_avx",
10567 /* 1225 */ "vmulS",
10568 /* 1226 */ "vmulS_reg",
10569 /* 1227 */ "vmulS_mem",
10570 /* 1228 */ "vmulS_mem_0",
10571 /* 1229 */ "vmulI",
10572 /* 1230 */ "vmulI_reg",
10573 /* 1231 */ "vmulI_mem",
10574 /* 1232 */ "vmulI_mem_0",
10575 /* 1233 */ "vmulL_reg",
10576 /* 1234 */ "vmulL_mem",
10577 /* 1235 */ "vmulL_mem_0",
10578 /* 1236 */ "mul2L_reg",
10579 /* 1237 */ "vmul4L_reg_avx",
10580 /* 1238 */ "vmulF",
10581 /* 1239 */ "vmulF_reg",
10582 /* 1240 */ "vmulF_mem",
10583 /* 1241 */ "vmulF_mem_0",
10584 /* 1242 */ "vmulD",
10585 /* 1243 */ "vmulD_reg",
10586 /* 1244 */ "vmulD_mem",
10587 /* 1245 */ "vmulD_mem_0",
10588 /* 1246 */ "vcmov8F_reg",
10589 /* 1247 */ "vcmov4D_reg",
10590 /* 1248 */ "vdivF",
10591 /* 1249 */ "vdivF_reg",
10592 /* 1250 */ "vdivF_mem",
10593 /* 1251 */ "vdivD",
10594 /* 1252 */ "vdivD_reg",
10595 /* 1253 */ "vdivD_mem",
10596 /* 1254 */ "minmax_reg_sse",
10597 /* 1255 */ "minmax_reg_sse_0",
10598 /* 1256 */ "vminmax_reg",
10599 /* 1257 */ "vminmax_reg_0",
10600 /* 1258 */ "minmaxL_reg_sse",
10601 /* 1259 */ "minmaxL_reg_sse_0",
10602 /* 1260 */ "vminmaxL_reg_avx",
10603 /* 1261 */ "vminmaxL_reg_avx_0",
10604 /* 1262 */ "vminmaxL_reg_evex",
10605 /* 1263 */ "vminmaxL_reg_evex_0",
10606 /* 1264 */ "minmaxFP_reg",
10607 /* 1265 */ "minmaxFP_reg_0",
10608 /* 1266 */ "evminmaxFP_reg_eavx",
10609 /* 1267 */ "evminmaxFP_reg_eavx_0",
10610 /* 1268 */ "signumF_reg",
10611 /* 1269 */ "signumD_reg",
10612 /* 1270 */ "copySignF_reg",
10613 /* 1271 */ "copySignD_imm",
10614 /* 1272 */ "vshiftB",
10615 /* 1273 */ "vshiftB_0",
10616 /* 1274 */ "vshiftB_1",
10617 /* 1275 */ "vshift16B",
10618 /* 1276 */ "vshift16B_0",
10619 /* 1277 */ "vshift16B_1",
10620 /* 1278 */ "vshift16B_avx",
10621 /* 1279 */ "vshift16B_avx_0",
10622 /* 1280 */ "vshift16B_avx_1",
10623 /* 1281 */ "vshift32B_avx",
10624 /* 1282 */ "vshift32B_avx_0",
10625 /* 1283 */ "vshift32B_avx_1",
10626 /* 1284 */ "vshift64B_avx",
10627 /* 1285 */ "vshift64B_avx_0",
10628 /* 1286 */ "vshift64B_avx_1",
10629 /* 1287 */ "vshiftS",
10630 /* 1288 */ "vshiftS_0",
10631 /* 1289 */ "vshiftS_1",
10632 /* 1290 */ "vshiftI",
10633 /* 1291 */ "vshiftI_0",
10634 /* 1292 */ "vshiftI_1",
10635 /* 1293 */ "vshiftI_imm",
10636 /* 1294 */ "vshiftI_imm_0",
10637 /* 1295 */ "vshiftI_imm_1",
10638 /* 1296 */ "vshiftL",
10639 /* 1297 */ "vshiftL_0",
10640 /* 1298 */ "vshiftL_imm",
10641 /* 1299 */ "vshiftL_imm_0",
10642 /* 1300 */ "vshiftL_arith_reg",
10643 /* 1301 */ "vshiftL_arith_reg_evex",
10644 /* 1302 */ "vshift8B_var_nobw",
10645 /* 1303 */ "vshift8B_var_nobw_0",
10646 /* 1304 */ "vshift8B_var_nobw_1",
10647 /* 1305 */ "vshift16B_var_nobw",
10648 /* 1306 */ "vshift16B_var_nobw_0",
10649 /* 1307 */ "vshift16B_var_nobw_1",
10650 /* 1308 */ "vshift32B_var_nobw",
10651 /* 1309 */ "vshift32B_var_nobw_0",
10652 /* 1310 */ "vshift32B_var_nobw_1",
10653 /* 1311 */ "vshiftB_var_evex_bw",
10654 /* 1312 */ "vshiftB_var_evex_bw_0",
10655 /* 1313 */ "vshiftB_var_evex_bw_1",
10656 /* 1314 */ "vshift64B_var_evex_bw",
10657 /* 1315 */ "vshift64B_var_evex_bw_0",
10658 /* 1316 */ "vshift64B_var_evex_bw_1",
10659 /* 1317 */ "vshift8S_var_nobw",
10660 /* 1318 */ "vshift8S_var_nobw_0",
10661 /* 1319 */ "vshift8S_var_nobw_1",
10662 /* 1320 */ "vshift16S_var_nobw",
10663 /* 1321 */ "vshift16S_var_nobw_0",
10664 /* 1322 */ "vshift16S_var_nobw_1",
10665 /* 1323 */ "vshift16S_var_evex_bw",
10666 /* 1324 */ "vshift16S_var_evex_bw_0",
10667 /* 1325 */ "vshift16S_var_evex_bw_1",
10668 /* 1326 */ "vshiftI_var",
10669 /* 1327 */ "vshiftI_var_0",
10670 /* 1328 */ "vshiftI_var_1",
10671 /* 1329 */ "vshiftL_var",
10672 /* 1330 */ "vshiftL_var_0",
10673 /* 1331 */ "vshiftL_arith_var",
10674 /* 1332 */ "vshiftL_arith_var_evex",
10675 /* 1333 */ "vand",
10676 /* 1334 */ "vand_reg",
10677 /* 1335 */ "vand_mem",
10678 /* 1336 */ "vand_mem_0",
10679 /* 1337 */ "vor",
10680 /* 1338 */ "vor_reg",
10681 /* 1339 */ "vor_mem",
10682 /* 1340 */ "vor_mem_0",
10683 /* 1341 */ "vxor",
10684 /* 1342 */ "vxor_reg",
10685 /* 1343 */ "vxor_mem",
10686 /* 1344 */ "vxor_mem_0",
10687 /* 1345 */ "castStoX",
10688 /* 1346 */ "vcastStoX",
10689 /* 1347 */ "castItoX",
10690 /* 1348 */ "vcastItoX",
10691 /* 1349 */ "vcastLtoBS",
10692 /* 1350 */ "vcastFtoI_reg_avx",
10693 /* 1351 */ "vcastFtoI_reg_evex",
10694 /* 1352 */ "vcastDtoL_reg_evex",
10695 /* 1353 */ "vcmpFD",
10696 /* 1354 */ "evcmpFD64",
10697 /* 1355 */ "evcmpFD",
10698 /* 1356 */ "vcmp",
10699 /* 1357 */ "vcmpu",
10700 /* 1358 */ "vcmpu32",
10701 /* 1359 */ "vcmpu64",
10702 /* 1360 */ "evcmp",
10703 /* 1361 */ "extractI",
10704 /* 1362 */ "extractI_0",
10705 /* 1363 */ "extractI_1",
10706 /* 1364 */ "vextractI",
10707 /* 1365 */ "vextractI_0",
10708 /* 1366 */ "vextractI_1",
10709 /* 1367 */ "extractL",
10710 /* 1368 */ "vextractL",
10711 /* 1369 */ "extractF",
10712 /* 1370 */ "vextractF",
10713 /* 1371 */ "extractD",
10714 /* 1372 */ "vextractD",
10715 /* 1373 */ "blendvp",
10716 /* 1374 */ "vblendvpI",
10717 /* 1375 */ "vblendvpFD",
10718 /* 1376 */ "evblendvp64",
10719 /* 1377 */ "evblendvp64_masked",
10720 /* 1378 */ "vabsnegF",
10721 /* 1379 */ "vabsnegF_0",
10722 /* 1380 */ "vabsneg4F",
10723 /* 1381 */ "vabsneg4F_0",
10724 /* 1382 */ "vabsnegD",
10725 /* 1383 */ "vabsnegD_0",
10726 /* 1384 */ "vptest_alltrue_lt16",
10727 /* 1385 */ "vptest_alltrue_ge16",
10728 /* 1386 */ "vptest_alltrue_lt8_evex",
10729 /* 1387 */ "vptest_alltrue_ge8_evex",
10730 /* 1388 */ "vptest_anytrue_lt16",
10731 /* 1389 */ "vptest_anytrue_ge16",
10732 /* 1390 */ "vptest_anytrue_evex",
10733 /* 1391 */ "loadMask",
10734 /* 1392 */ "loadMask64",
10735 /* 1393 */ "loadMask_evex",
10736 /* 1394 */ "vstoreMask1B",
10737 /* 1395 */ "vstoreMask2B",
10738 /* 1396 */ "vstoreMask4B",
10739 /* 1397 */ "storeMask8B",
10740 /* 1398 */ "storeMask8B_avx",
10741 /* 1399 */ "vstoreMask4B_evex_novectmask",
10742 /* 1400 */ "vstoreMask8B_evex_novectmask",
10743 /* 1401 */ "vstoreMask_evex_vectmask",
10744 /* 1402 */ "vstoreMask_evex",
10745 /* 1403 */ "loadIotaIndices",
10746 /* 1404 */ "rearrangeB",
10747 /* 1405 */ "rearrangeB_avx",
10748 /* 1406 */ "rearrangeB_evex",
10749 /* 1407 */ "loadShuffleS",
10750 /* 1408 */ "rearrangeS",
10751 /* 1409 */ "rearrangeS_avx",
10752 /* 1410 */ "rearrangeS_evex",
10753 /* 1411 */ "loadShuffleI",
10754 /* 1412 */ "rearrangeI",
10755 /* 1413 */ "rearrangeI_avx",
10756 /* 1414 */ "loadShuffleL",
10757 /* 1415 */ "rearrangeL",
10758 /* 1416 */ "rearrangeL_evex",
10759 /* 1417 */ "vfmaF_reg",
10760 /* 1418 */ "vfmaF_mem",
10761 /* 1419 */ "vfmaD_reg",
10762 /* 1420 */ "vfmaD_mem",
10763 /* 1421 */ "vmuladdS2I_reg_sse",
10764 /* 1422 */ "vmuladdS2I_reg_avx",
10765 /* 1423 */ "vmuladdaddS2I_reg",
10766 /* 1424 */ "vmuladdaddS2I_reg_0",
10767 /* 1425 */ "vpternlog",
10768 /* 1426 */ "vpternlog_mem",
10769 /* 1427 */ "vprotate_immI8",
10770 /* 1428 */ "vprotate_immI8_0",
10771 /* 1429 */ "vprorate",
10772 /* 1430 */ "vprorate_0",
10773 /* 1431 */ "vmask_cmp_node",
10774 /* 1432 */ "vmasked_load64",
10775 /* 1433 */ "vmask_gen",
10776 /* 1434 */ "vmask_gen_imm",
10777 /* 1435 */ "vmasked_store64",
10778 /* 1436 */ "vmask_tolong_evex",
10779 /* 1437 */ "vmask_tolong_bool",
10780 /* 1438 */ "vmask_tolong_avx",
10781 /* 1439 */ "vmask_truecount_evex",
10782 /* 1440 */ "vmask_truecount_bool",
10783 /* 1441 */ "vmask_truecount_avx",
10784 /* 1442 */ "vmask_first_or_last_true_evex",
10785 /* 1443 */ "vmask_first_or_last_true_evex_0",
10786 /* 1444 */ "vmask_first_or_last_true_bool",
10787 /* 1445 */ "vmask_first_or_last_true_bool_0",
10788 /* 1446 */ "vmask_first_or_last_true_avx",
10789 /* 1447 */ "vmask_first_or_last_true_avx_0",
10790 /* 1448 */ "vadd_reg_masked",
10791 /* 1449 */ "vadd_reg_masked_0",
10792 /* 1450 */ "vadd_reg_masked_1",
10793 /* 1451 */ "vadd_reg_masked_2",
10794 /* 1452 */ "vadd_reg_masked_3",
10795 /* 1453 */ "vadd_reg_masked_4",
10796 /* 1454 */ "vadd_mem_masked",
10797 /* 1455 */ "vadd_mem_masked_0",
10798 /* 1456 */ "vadd_mem_masked_1",
10799 /* 1457 */ "vadd_mem_masked_2",
10800 /* 1458 */ "vadd_mem_masked_3",
10801 /* 1459 */ "vadd_mem_masked_4",
10802 /* 1460 */ "vxor_reg_masked",
10803 /* 1461 */ "vxor_mem_masked",
10804 /* 1462 */ "vor_reg_masked",
10805 /* 1463 */ "vor_mem_masked",
10806 /* 1464 */ "vand_reg_masked",
10807 /* 1465 */ "vand_mem_masked",
10808 /* 1466 */ "vsub_reg_masked",
10809 /* 1467 */ "vsub_reg_masked_0",
10810 /* 1468 */ "vsub_reg_masked_1",
10811 /* 1469 */ "vsub_reg_masked_2",
10812 /* 1470 */ "vsub_reg_masked_3",
10813 /* 1471 */ "vsub_reg_masked_4",
10814 /* 1472 */ "vsub_mem_masked",
10815 /* 1473 */ "vsub_mem_masked_0",
10816 /* 1474 */ "vsub_mem_masked_1",
10817 /* 1475 */ "vsub_mem_masked_2",
10818 /* 1476 */ "vsub_mem_masked_3",
10819 /* 1477 */ "vsub_mem_masked_4",
10820 /* 1478 */ "vmul_reg_masked",
10821 /* 1479 */ "vmul_reg_masked_0",
10822 /* 1480 */ "vmul_reg_masked_1",
10823 /* 1481 */ "vmul_reg_masked_2",
10824 /* 1482 */ "vmul_reg_masked_3",
10825 /* 1483 */ "vmul_mem_masked",
10826 /* 1484 */ "vmul_mem_masked_0",
10827 /* 1485 */ "vmul_mem_masked_1",
10828 /* 1486 */ "vmul_mem_masked_2",
10829 /* 1487 */ "vmul_mem_masked_3",
10830 /* 1488 */ "vsqrt_reg_masked",
10831 /* 1489 */ "vsqrt_reg_masked_0",
10832 /* 1490 */ "vdiv_reg_masked",
10833 /* 1491 */ "vdiv_reg_masked_0",
10834 /* 1492 */ "vdiv_mem_masked",
10835 /* 1493 */ "vdiv_mem_masked_0",
10836 /* 1494 */ "vrol_imm_masked",
10837 /* 1495 */ "vrol_imm_masked_0",
10838 /* 1496 */ "vrol_reg_masked",
10839 /* 1497 */ "vrol_reg_masked_0",
10840 /* 1498 */ "vlshift_imm_masked",
10841 /* 1499 */ "vlshift_imm_masked_0",
10842 /* 1500 */ "vlshift_imm_masked_1",
10843 /* 1501 */ "vlshift_reg_masked",
10844 /* 1502 */ "vlshift_reg_masked_0",
10845 /* 1503 */ "vlshift_reg_masked_1",
10846 /* 1504 */ "vlshiftv_reg_masked",
10847 /* 1505 */ "vlshiftv_reg_masked_0",
10848 /* 1506 */ "vlshiftv_reg_masked_1",
10849 /* 1507 */ "vlshift_mem_masked",
10850 /* 1508 */ "vlshift_mem_masked_0",
10851 /* 1509 */ "vlshift_mem_masked_1",
10852 /* 1510 */ "vrshift_imm_masked",
10853 /* 1511 */ "vrshift_imm_masked_0",
10854 /* 1512 */ "vrshift_imm_masked_1",
10855 /* 1513 */ "vrshift_reg_masked",
10856 /* 1514 */ "vrshift_reg_masked_0",
10857 /* 1515 */ "vrshift_reg_masked_1",
10858 /* 1516 */ "vrshiftv_reg_masked",
10859 /* 1517 */ "vrshiftv_reg_masked_0",
10860 /* 1518 */ "vrshiftv_reg_masked_1",
10861 /* 1519 */ "vrshift_mem_masked",
10862 /* 1520 */ "vrshift_mem_masked_0",
10863 /* 1521 */ "vrshift_mem_masked_1",
10864 /* 1522 */ "vurshift_imm_masked",
10865 /* 1523 */ "vurshift_imm_masked_0",
10866 /* 1524 */ "vurshift_imm_masked_1",
10867 /* 1525 */ "vurshift_reg_masked",
10868 /* 1526 */ "vurshift_reg_masked_0",
10869 /* 1527 */ "vurshift_reg_masked_1",
10870 /* 1528 */ "vurshiftv_reg_masked",
10871 /* 1529 */ "vurshiftv_reg_masked_0",
10872 /* 1530 */ "vurshiftv_reg_masked_1",
10873 /* 1531 */ "vurshift_mem_masked",
10874 /* 1532 */ "vurshift_mem_masked_0",
10875 /* 1533 */ "vurshift_mem_masked_1",
10876 /* 1534 */ "vmaxv_reg_masked",
10877 /* 1535 */ "vmaxv_mem_masked",
10878 /* 1536 */ "vminv_reg_masked",
10879 /* 1537 */ "vminv_mem_masked",
10880 /* 1538 */ "vrearrangev_reg_masked",
10881 /* 1539 */ "vabs_masked",
10882 /* 1540 */ "vabs_masked_0",
10883 /* 1541 */ "vabs_masked_1",
10884 /* 1542 */ "vabs_masked_2",
10885 /* 1543 */ "vfma_reg_masked",
10886 /* 1544 */ "vfma_reg_masked_0",
10887 /* 1545 */ "vfma_mem_masked",
10888 /* 1546 */ "vfma_mem_masked_0",
10889 /* 1547 */ "evcmp_masked",
10890 /* 1548 */ "mask_all_evexI_imm",
10891 /* 1549 */ "mask_all_evexI",
10892 /* 1550 */ "mask_all_evexL",
10893 /* 1551 */ "mask_not_immLT8",
10894 /* 1552 */ "mask_not_imm",
10895 /* 1553 */ "long_to_maskLE8_avx",
10896 /* 1554 */ "long_to_maskGT8_avx",
10897 /* 1555 */ "mask_opers_evex",
10898 /* 1556 */ "mask_opers_evex_0",
10899 /* 1557 */ "mask_opers_evex_1",
10900 /* 1558 */ "compareAndSwapP_shenandoah",
10901 /* 1559 */ "compareAndSwapP_shenandoah_0",
10902 /* 1560 */ "compareAndSwapN_shenandoah",
10903 /* 1561 */ "compareAndSwapN_shenandoah_0",
10904 /* 1562 */ "compareAndExchangeN_shenandoah",
10905 /* 1563 */ "compareAndExchangeP_shenandoah",
10906 /* 1564 */ "zLoadP",
10907 /* 1565 */ "zCompareAndExchangeP",
10908 /* 1566 */ "zCompareAndSwapP",
10909 /* 1567 */ "zCompareAndSwapP_0",
10910 /* 1568 */ "zXChgP",
10911 // last instruction
10912 "invalid rule name" // no trailing comma
10913};
10914
10915const bool swallowed[] = {
10916 /* 0 */ false,
10917 /* 1 */ false,
10918 /* 2 */ false,
10919 /* 3 */ false,
10920 /* 4 */ false,
10921 /* 5 */ false,
10922 /* 6 */ false,
10923 /* 7 */ false,
10924 /* 8 */ true,
10925 /* 9 */ true,
10926 /* 10 */ true,
10927 /* 11 */ true,
10928 /* 12 */ true,
10929 /* 13 */ true,
10930 /* 14 */ true,
10931 /* 15 */ true,
10932 /* 16 */ true,
10933 /* 17 */ true,
10934 /* 18 */ true,
10935 /* 19 */ true,
10936 /* 20 */ true,
10937 /* 21 */ true,
10938 /* 22 */ true,
10939 /* 23 */ true,
10940 /* 24 */ true,
10941 /* 25 */ true,
10942 /* 26 */ true,
10943 /* 27 */ true,
10944 /* 28 */ true,
10945 /* 29 */ true,
10946 /* 30 */ true,
10947 /* 31 */ true,
10948 /* 32 */ true,
10949 /* 33 */ true,
10950 /* 34 */ true,
10951 /* 35 */ true,
10952 /* 36 */ true,
10953 /* 37 */ true,
10954 /* 38 */ true,
10955 /* 39 */ true,
10956 /* 40 */ true,
10957 /* 41 */ true,
10958 /* 42 */ true,
10959 /* 43 */ true,
10960 /* 44 */ true,
10961 /* 45 */ true,
10962 /* 46 */ true,
10963 /* 47 */ true,
10964 /* 48 */ true,
10965 /* 49 */ true,
10966 /* 50 */ true,
10967 /* 51 */ true,
10968 /* 52 */ false,
10969 /* 53 */ false,
10970 /* 54 */ false,
10971 /* 55 */ false,
10972 /* 56 */ false,
10973 /* 57 */ false,
10974 /* 58 */ false,
10975 /* 59 */ false,
10976 /* 60 */ false,
10977 /* 61 */ false,
10978 /* 62 */ false,
10979 /* 63 */ false,
10980 /* 64 */ false,
10981 /* 65 */ false,
10982 /* 66 */ false,
10983 /* 67 */ false,
10984 /* 68 */ false,
10985 /* 69 */ false,
10986 /* 70 */ false,
10987 /* 71 */ false,
10988 /* 72 */ false,
10989 /* 73 */ false,
10990 /* 74 */ false,
10991 /* 75 */ false,
10992 /* 76 */ false,
10993 /* 77 */ false,
10994 /* 78 */ false,
10995 /* 79 */ false,
10996 /* 80 */ false,
10997 /* 81 */ false,
10998 /* 82 */ false,
10999 /* 83 */ false,
11000 /* 84 */ false,
11001 /* 85 */ false,
11002 /* 86 */ false,
11003 /* 87 */ false,
11004 /* 88 */ false,
11005 /* 89 */ false,
11006 /* 90 */ false,
11007 /* 91 */ false,
11008 /* 92 */ false,
11009 /* 93 */ false,
11010 /* 94 */ false,
11011 /* 95 */ false,
11012 /* 96 */ false,
11013 /* 97 */ false,
11014 /* 98 */ false,
11015 /* 99 */ false,
11016 /* 100 */ false,
11017 /* 101 */ false,
11018 /* 102 */ false,
11019 /* 103 */ false,
11020 /* 104 */ false,
11021 /* 105 */ false,
11022 /* 106 */ false,
11023 /* 107 */ false,
11024 /* 108 */ false,
11025 /* 109 */ false,
11026 /* 110 */ false,
11027 /* 111 */ false,
11028 /* 112 */ false,
11029 /* 113 */ false,
11030 /* 114 */ false,
11031 /* 115 */ false,
11032 /* 116 */ false,
11033 /* 117 */ false,
11034 /* 118 */ false,
11035 /* 119 */ false,
11036 /* 120 */ true,
11037 /* 121 */ true,
11038 /* 122 */ true,
11039 /* 123 */ true,
11040 /* 124 */ false,
11041 /* 125 */ false,
11042 /* 126 */ false,
11043 /* 127 */ false,
11044 /* 128 */ false,
11045 /* 129 */ false,
11046 /* 130 */ false,
11047 /* 131 */ false,
11048 /* 132 */ false,
11049 /* 133 */ false,
11050 /* 134 */ false,
11051 /* 135 */ false,
11052 /* 136 */ false,
11053 /* 137 */ true,
11054 // last operand
11055 /* 138 */ false,
11056 // last operand class
11057 /* 139 */ false,
11058 /* 140 */ false,
11059 /* 141 */ false,
11060 /* 142 */ false,
11061 /* 143 */ false,
11062 /* 144 */ false,
11063 /* 145 */ false,
11064 /* 146 */ false,
11065 /* 147 */ false,
11066 /* 148 */ false,
11067 /* 149 */ false,
11068 /* 150 */ false,
11069 /* 151 */ false,
11070 /* 152 */ false,
11071 /* 153 */ false,
11072 /* 154 */ false,
11073 /* 155 */ false,
11074 /* 156 */ false,
11075 /* 157 */ false,
11076 /* 158 */ false,
11077 /* 159 */ false,
11078 /* 160 */ false,
11079 /* 161 */ false,
11080 /* 162 */ false,
11081 /* 163 */ false,
11082 /* 164 */ false,
11083 /* 165 */ false,
11084 /* 166 */ false,
11085 /* 167 */ false,
11086 /* 168 */ false,
11087 /* 169 */ false,
11088 /* 170 */ false,
11089 /* 171 */ false,
11090 /* 172 */ false,
11091 /* 173 */ false,
11092 /* 174 */ false,
11093 /* 175 */ false,
11094 /* 176 */ false,
11095 /* 177 */ false,
11096 /* 178 */ false,
11097 /* 179 */ false,
11098 /* 180 */ false,
11099 /* 181 */ false,
11100 /* 182 */ false,
11101 /* 183 */ false,
11102 /* 184 */ false,
11103 /* 185 */ false,
11104 /* 186 */ false,
11105 /* 187 */ false,
11106 /* 188 */ false,
11107 /* 189 */ false,
11108 /* 190 */ false,
11109 /* 191 */ false,
11110 /* 192 */ false,
11111 /* 193 */ false,
11112 /* 194 */ false,
11113 /* 195 */ false,
11114 /* 196 */ false,
11115 /* 197 */ false,
11116 /* 198 */ false,
11117 /* 199 */ false,
11118 /* 200 */ false,
11119 /* 201 */ false,
11120 /* 202 */ false,
11121 /* 203 */ false,
11122 /* 204 */ false,
11123 /* 205 */ false,
11124 /* 206 */ false,
11125 /* 207 */ false,
11126 /* 208 */ false,
11127 /* 209 */ false,
11128 /* 210 */ false,
11129 /* 211 */ false,
11130 /* 212 */ false,
11131 /* 213 */ false,
11132 /* 214 */ false,
11133 /* 215 */ false,
11134 /* 216 */ false,
11135 /* 217 */ false,
11136 /* 218 */ false,
11137 /* 219 */ false,
11138 /* 220 */ false,
11139 /* 221 */ false,
11140 /* 222 */ false,
11141 /* 223 */ false,
11142 /* 224 */ false,
11143 /* 225 */ false,
11144 /* 226 */ false,
11145 /* 227 */ false,
11146 /* 228 */ false,
11147 /* 229 */ false,
11148 /* 230 */ false,
11149 /* 231 */ false,
11150 /* 232 */ false,
11151 /* 233 */ false,
11152 /* 234 */ false,
11153 /* 235 */ false,
11154 /* 236 */ false,
11155 /* 237 */ false,
11156 /* 238 */ false,
11157 /* 239 */ false,
11158 /* 240 */ false,
11159 /* 241 */ false,
11160 /* 242 */ false,
11161 /* 243 */ false,
11162 /* 244 */ false,
11163 /* 245 */ false,
11164 /* 246 */ false,
11165 /* 247 */ false,
11166 /* 248 */ false,
11167 /* 249 */ false,
11168 /* 250 */ false,
11169 /* 251 */ false,
11170 /* 252 */ false,
11171 /* 253 */ false,
11172 /* 254 */ false,
11173 /* 255 */ false,
11174 /* 256 */ false,
11175 /* 257 */ false,
11176 /* 258 */ false,
11177 /* 259 */ false,
11178 /* 260 */ false,
11179 /* 261 */ false,
11180 /* 262 */ false,
11181 /* 263 */ false,
11182 /* 264 */ false,
11183 /* 265 */ false,
11184 /* 266 */ false,
11185 /* 267 */ false,
11186 /* 268 */ false,
11187 /* 269 */ false,
11188 /* 270 */ false,
11189 /* 271 */ false,
11190 /* 272 */ false,
11191 /* 273 */ false,
11192 /* 274 */ false,
11193 /* 275 */ false,
11194 /* 276 */ false,
11195 /* 277 */ false,
11196 /* 278 */ false,
11197 /* 279 */ false,
11198 /* 280 */ false,
11199 /* 281 */ false,
11200 /* 282 */ false,
11201 /* 283 */ false,
11202 /* 284 */ false,
11203 /* 285 */ false,
11204 /* 286 */ false,
11205 /* 287 */ false,
11206 /* 288 */ false,
11207 /* 289 */ false,
11208 /* 290 */ false,
11209 /* 291 */ false,
11210 /* 292 */ false,
11211 /* 293 */ false,
11212 /* 294 */ false,
11213 /* 295 */ false,
11214 /* 296 */ false,
11215 /* 297 */ false,
11216 /* 298 */ false,
11217 /* 299 */ false,
11218 /* 300 */ false,
11219 /* 301 */ false,
11220 /* 302 */ false,
11221 /* 303 */ false,
11222 /* 304 */ false,
11223 /* 305 */ false,
11224 // last internally defined operand
11225 /* 306 */ false,
11226 /* 307 */ false,
11227 /* 308 */ false,
11228 /* 309 */ false,
11229 /* 310 */ false,
11230 /* 311 */ false,
11231 /* 312 */ false,
11232 /* 313 */ false,
11233 /* 314 */ false,
11234 /* 315 */ false,
11235 /* 316 */ false,
11236 /* 317 */ false,
11237 /* 318 */ false,
11238 /* 319 */ false,
11239 /* 320 */ false,
11240 /* 321 */ false,
11241 /* 322 */ false,
11242 /* 323 */ false,
11243 /* 324 */ false,
11244 /* 325 */ false,
11245 /* 326 */ false,
11246 /* 327 */ false,
11247 /* 328 */ false,
11248 /* 329 */ false,
11249 /* 330 */ false,
11250 /* 331 */ false,
11251 /* 332 */ false,
11252 /* 333 */ false,
11253 /* 334 */ false,
11254 /* 335 */ false,
11255 /* 336 */ false,
11256 /* 337 */ false,
11257 /* 338 */ false,
11258 /* 339 */ false,
11259 /* 340 */ false,
11260 /* 341 */ false,
11261 /* 342 */ false,
11262 /* 343 */ false,
11263 /* 344 */ false,
11264 /* 345 */ false,
11265 /* 346 */ false,
11266 /* 347 */ false,
11267 /* 348 */ false,
11268 /* 349 */ false,
11269 /* 350 */ false,
11270 /* 351 */ false,
11271 /* 352 */ false,
11272 /* 353 */ false,
11273 /* 354 */ false,
11274 /* 355 */ false,
11275 /* 356 */ false,
11276 /* 357 */ false,
11277 /* 358 */ false,
11278 /* 359 */ false,
11279 /* 360 */ false,
11280 /* 361 */ false,
11281 /* 362 */ false,
11282 /* 363 */ false,
11283 /* 364 */ false,
11284 /* 365 */ false,
11285 /* 366 */ false,
11286 /* 367 */ false,
11287 /* 368 */ false,
11288 /* 369 */ false,
11289 /* 370 */ false,
11290 /* 371 */ false,
11291 /* 372 */ false,
11292 /* 373 */ false,
11293 /* 374 */ false,
11294 /* 375 */ false,
11295 /* 376 */ false,
11296 /* 377 */ false,
11297 /* 378 */ false,
11298 /* 379 */ false,
11299 /* 380 */ false,
11300 /* 381 */ false,
11301 /* 382 */ false,
11302 /* 383 */ false,
11303 /* 384 */ false,
11304 /* 385 */ false,
11305 /* 386 */ false,
11306 /* 387 */ false,
11307 /* 388 */ false,
11308 /* 389 */ false,
11309 /* 390 */ false,
11310 /* 391 */ false,
11311 /* 392 */ false,
11312 /* 393 */ false,
11313 /* 394 */ false,
11314 /* 395 */ false,
11315 /* 396 */ false,
11316 /* 397 */ false,
11317 /* 398 */ false,
11318 /* 399 */ false,
11319 /* 400 */ false,
11320 /* 401 */ false,
11321 /* 402 */ false,
11322 /* 403 */ false,
11323 /* 404 */ false,
11324 /* 405 */ false,
11325 /* 406 */ false,
11326 /* 407 */ false,
11327 /* 408 */ false,
11328 /* 409 */ false,
11329 /* 410 */ false,
11330 /* 411 */ false,
11331 /* 412 */ false,
11332 /* 413 */ false,
11333 /* 414 */ false,
11334 /* 415 */ false,
11335 /* 416 */ false,
11336 /* 417 */ false,
11337 /* 418 */ false,
11338 /* 419 */ false,
11339 /* 420 */ false,
11340 /* 421 */ false,
11341 /* 422 */ false,
11342 /* 423 */ false,
11343 /* 424 */ false,
11344 /* 425 */ false,
11345 /* 426 */ false,
11346 /* 427 */ false,
11347 /* 428 */ false,
11348 /* 429 */ false,
11349 /* 430 */ false,
11350 /* 431 */ false,
11351 /* 432 */ false,
11352 /* 433 */ false,
11353 /* 434 */ false,
11354 /* 435 */ false,
11355 /* 436 */ false,
11356 /* 437 */ false,
11357 /* 438 */ false,
11358 /* 439 */ false,
11359 /* 440 */ false,
11360 /* 441 */ false,
11361 /* 442 */ false,
11362 /* 443 */ false,
11363 /* 444 */ false,
11364 /* 445 */ false,
11365 /* 446 */ false,
11366 /* 447 */ false,
11367 /* 448 */ false,
11368 /* 449 */ false,
11369 /* 450 */ false,
11370 /* 451 */ false,
11371 /* 452 */ false,
11372 /* 453 */ false,
11373 /* 454 */ false,
11374 /* 455 */ false,
11375 /* 456 */ false,
11376 /* 457 */ false,
11377 /* 458 */ false,
11378 /* 459 */ false,
11379 /* 460 */ false,
11380 /* 461 */ false,
11381 /* 462 */ false,
11382 /* 463 */ false,
11383 /* 464 */ false,
11384 /* 465 */ false,
11385 /* 466 */ false,
11386 /* 467 */ false,
11387 /* 468 */ false,
11388 /* 469 */ false,
11389 /* 470 */ false,
11390 /* 471 */ false,
11391 /* 472 */ false,
11392 /* 473 */ false,
11393 /* 474 */ false,
11394 /* 475 */ false,
11395 /* 476 */ false,
11396 /* 477 */ false,
11397 /* 478 */ false,
11398 /* 479 */ false,
11399 /* 480 */ false,
11400 /* 481 */ false,
11401 /* 482 */ false,
11402 /* 483 */ false,
11403 /* 484 */ false,
11404 /* 485 */ false,
11405 /* 486 */ false,
11406 /* 487 */ false,
11407 /* 488 */ false,
11408 /* 489 */ false,
11409 /* 490 */ false,
11410 /* 491 */ false,
11411 /* 492 */ false,
11412 /* 493 */ false,
11413 /* 494 */ false,
11414 /* 495 */ false,
11415 /* 496 */ false,
11416 /* 497 */ false,
11417 /* 498 */ false,
11418 /* 499 */ false,
11419 /* 500 */ false,
11420 /* 501 */ false,
11421 /* 502 */ false,
11422 /* 503 */ false,
11423 /* 504 */ false,
11424 /* 505 */ false,
11425 /* 506 */ false,
11426 /* 507 */ false,
11427 /* 508 */ false,
11428 /* 509 */ false,
11429 /* 510 */ false,
11430 /* 511 */ false,
11431 /* 512 */ false,
11432 /* 513 */ false,
11433 /* 514 */ false,
11434 /* 515 */ false,
11435 /* 516 */ false,
11436 /* 517 */ false,
11437 /* 518 */ false,
11438 /* 519 */ false,
11439 /* 520 */ false,
11440 /* 521 */ false,
11441 /* 522 */ false,
11442 /* 523 */ false,
11443 /* 524 */ false,
11444 /* 525 */ false,
11445 /* 526 */ false,
11446 /* 527 */ false,
11447 /* 528 */ false,
11448 /* 529 */ false,
11449 /* 530 */ false,
11450 /* 531 */ false,
11451 /* 532 */ false,
11452 /* 533 */ false,
11453 /* 534 */ false,
11454 /* 535 */ false,
11455 /* 536 */ false,
11456 /* 537 */ false,
11457 /* 538 */ false,
11458 /* 539 */ false,
11459 /* 540 */ false,
11460 /* 541 */ false,
11461 /* 542 */ false,
11462 /* 543 */ false,
11463 /* 544 */ false,
11464 /* 545 */ false,
11465 /* 546 */ false,
11466 /* 547 */ false,
11467 /* 548 */ false,
11468 /* 549 */ false,
11469 /* 550 */ false,
11470 /* 551 */ false,
11471 /* 552 */ false,
11472 /* 553 */ false,
11473 /* 554 */ false,
11474 /* 555 */ false,
11475 /* 556 */ false,
11476 /* 557 */ false,
11477 /* 558 */ false,
11478 /* 559 */ false,
11479 /* 560 */ false,
11480 /* 561 */ false,
11481 /* 562 */ false,
11482 /* 563 */ false,
11483 /* 564 */ false,
11484 /* 565 */ false,
11485 /* 566 */ false,
11486 /* 567 */ false,
11487 /* 568 */ false,
11488 /* 569 */ false,
11489 /* 570 */ false,
11490 /* 571 */ false,
11491 /* 572 */ false,
11492 /* 573 */ false,
11493 /* 574 */ false,
11494 /* 575 */ false,
11495 /* 576 */ false,
11496 /* 577 */ false,
11497 /* 578 */ false,
11498 /* 579 */ false,
11499 /* 580 */ false,
11500 /* 581 */ false,
11501 /* 582 */ false,
11502 /* 583 */ false,
11503 /* 584 */ false,
11504 /* 585 */ false,
11505 /* 586 */ false,
11506 /* 587 */ false,
11507 /* 588 */ false,
11508 /* 589 */ false,
11509 /* 590 */ false,
11510 /* 591 */ false,
11511 /* 592 */ false,
11512 /* 593 */ false,
11513 /* 594 */ false,
11514 /* 595 */ false,
11515 /* 596 */ false,
11516 /* 597 */ false,
11517 /* 598 */ false,
11518 /* 599 */ false,
11519 /* 600 */ false,
11520 /* 601 */ false,
11521 /* 602 */ false,
11522 /* 603 */ false,
11523 /* 604 */ false,
11524 /* 605 */ false,
11525 /* 606 */ false,
11526 /* 607 */ false,
11527 /* 608 */ false,
11528 /* 609 */ false,
11529 /* 610 */ false,
11530 /* 611 */ false,
11531 /* 612 */ false,
11532 /* 613 */ false,
11533 /* 614 */ false,
11534 /* 615 */ false,
11535 /* 616 */ false,
11536 /* 617 */ false,
11537 /* 618 */ false,
11538 /* 619 */ false,
11539 /* 620 */ false,
11540 /* 621 */ false,
11541 /* 622 */ false,
11542 /* 623 */ false,
11543 /* 624 */ false,
11544 /* 625 */ false,
11545 /* 626 */ false,
11546 /* 627 */ false,
11547 /* 628 */ false,
11548 /* 629 */ false,
11549 /* 630 */ false,
11550 /* 631 */ false,
11551 /* 632 */ false,
11552 /* 633 */ false,
11553 /* 634 */ false,
11554 /* 635 */ false,
11555 /* 636 */ false,
11556 /* 637 */ false,
11557 /* 638 */ false,
11558 /* 639 */ false,
11559 /* 640 */ false,
11560 /* 641 */ false,
11561 /* 642 */ false,
11562 /* 643 */ false,
11563 /* 644 */ false,
11564 /* 645 */ false,
11565 /* 646 */ false,
11566 /* 647 */ false,
11567 /* 648 */ false,
11568 /* 649 */ false,
11569 /* 650 */ false,
11570 /* 651 */ false,
11571 /* 652 */ false,
11572 /* 653 */ false,
11573 /* 654 */ false,
11574 /* 655 */ false,
11575 /* 656 */ false,
11576 /* 657 */ false,
11577 /* 658 */ false,
11578 /* 659 */ false,
11579 /* 660 */ false,
11580 /* 661 */ false,
11581 /* 662 */ false,
11582 /* 663 */ false,
11583 /* 664 */ false,
11584 /* 665 */ false,
11585 /* 666 */ false,
11586 /* 667 */ false,
11587 /* 668 */ false,
11588 /* 669 */ false,
11589 /* 670 */ false,
11590 /* 671 */ false,
11591 /* 672 */ false,
11592 /* 673 */ false,
11593 /* 674 */ false,
11594 /* 675 */ false,
11595 /* 676 */ false,
11596 /* 677 */ false,
11597 /* 678 */ false,
11598 /* 679 */ false,
11599 /* 680 */ false,
11600 /* 681 */ false,
11601 /* 682 */ false,
11602 /* 683 */ false,
11603 /* 684 */ false,
11604 /* 685 */ false,
11605 /* 686 */ false,
11606 /* 687 */ false,
11607 /* 688 */ false,
11608 /* 689 */ false,
11609 /* 690 */ false,
11610 /* 691 */ false,
11611 /* 692 */ false,
11612 /* 693 */ false,
11613 /* 694 */ false,
11614 /* 695 */ false,
11615 /* 696 */ false,
11616 /* 697 */ false,
11617 /* 698 */ false,
11618 /* 699 */ false,
11619 /* 700 */ false,
11620 /* 701 */ false,
11621 /* 702 */ false,
11622 /* 703 */ false,
11623 /* 704 */ false,
11624 /* 705 */ false,
11625 /* 706 */ false,
11626 /* 707 */ false,
11627 /* 708 */ false,
11628 /* 709 */ false,
11629 /* 710 */ false,
11630 /* 711 */ false,
11631 /* 712 */ false,
11632 /* 713 */ false,
11633 /* 714 */ false,
11634 /* 715 */ false,
11635 /* 716 */ false,
11636 /* 717 */ false,
11637 /* 718 */ false,
11638 /* 719 */ false,
11639 /* 720 */ false,
11640 /* 721 */ false,
11641 /* 722 */ false,
11642 /* 723 */ false,
11643 /* 724 */ false,
11644 /* 725 */ false,
11645 /* 726 */ false,
11646 /* 727 */ false,
11647 /* 728 */ false,
11648 /* 729 */ false,
11649 /* 730 */ false,
11650 /* 731 */ false,
11651 /* 732 */ false,
11652 /* 733 */ false,
11653 /* 734 */ false,
11654 /* 735 */ false,
11655 /* 736 */ false,
11656 /* 737 */ false,
11657 /* 738 */ false,
11658 /* 739 */ false,
11659 /* 740 */ false,
11660 /* 741 */ false,
11661 /* 742 */ false,
11662 /* 743 */ false,
11663 /* 744 */ false,
11664 /* 745 */ false,
11665 /* 746 */ false,
11666 /* 747 */ false,
11667 /* 748 */ false,
11668 /* 749 */ false,
11669 /* 750 */ false,
11670 /* 751 */ false,
11671 /* 752 */ false,
11672 /* 753 */ false,
11673 /* 754 */ false,
11674 /* 755 */ false,
11675 /* 756 */ false,
11676 /* 757 */ false,
11677 /* 758 */ false,
11678 /* 759 */ false,
11679 /* 760 */ false,
11680 /* 761 */ false,
11681 /* 762 */ false,
11682 /* 763 */ false,
11683 /* 764 */ false,
11684 /* 765 */ false,
11685 /* 766 */ false,
11686 /* 767 */ false,
11687 /* 768 */ false,
11688 /* 769 */ false,
11689 /* 770 */ false,
11690 /* 771 */ false,
11691 /* 772 */ false,
11692 /* 773 */ false,
11693 /* 774 */ false,
11694 /* 775 */ false,
11695 /* 776 */ false,
11696 /* 777 */ false,
11697 /* 778 */ false,
11698 /* 779 */ false,
11699 /* 780 */ false,
11700 /* 781 */ false,
11701 /* 782 */ false,
11702 /* 783 */ false,
11703 /* 784 */ false,
11704 /* 785 */ false,
11705 /* 786 */ false,
11706 /* 787 */ false,
11707 /* 788 */ false,
11708 /* 789 */ false,
11709 /* 790 */ false,
11710 /* 791 */ false,
11711 /* 792 */ false,
11712 /* 793 */ false,
11713 /* 794 */ false,
11714 /* 795 */ false,
11715 /* 796 */ false,
11716 /* 797 */ false,
11717 /* 798 */ false,
11718 /* 799 */ false,
11719 /* 800 */ false,
11720 /* 801 */ false,
11721 /* 802 */ false,
11722 /* 803 */ false,
11723 /* 804 */ false,
11724 /* 805 */ false,
11725 /* 806 */ false,
11726 /* 807 */ false,
11727 /* 808 */ false,
11728 /* 809 */ false,
11729 /* 810 */ false,
11730 /* 811 */ false,
11731 /* 812 */ false,
11732 /* 813 */ false,
11733 /* 814 */ false,
11734 /* 815 */ false,
11735 /* 816 */ false,
11736 /* 817 */ false,
11737 /* 818 */ false,
11738 /* 819 */ false,
11739 /* 820 */ false,
11740 /* 821 */ false,
11741 /* 822 */ false,
11742 /* 823 */ false,
11743 /* 824 */ false,
11744 /* 825 */ false,
11745 /* 826 */ false,
11746 /* 827 */ false,
11747 /* 828 */ false,
11748 /* 829 */ false,
11749 /* 830 */ false,
11750 /* 831 */ false,
11751 /* 832 */ false,
11752 /* 833 */ false,
11753 /* 834 */ false,
11754 /* 835 */ false,
11755 /* 836 */ false,
11756 /* 837 */ false,
11757 /* 838 */ false,
11758 /* 839 */ false,
11759 /* 840 */ false,
11760 /* 841 */ false,
11761 /* 842 */ false,
11762 /* 843 */ false,
11763 /* 844 */ false,
11764 /* 845 */ false,
11765 /* 846 */ false,
11766 /* 847 */ false,
11767 /* 848 */ false,
11768 /* 849 */ false,
11769 /* 850 */ false,
11770 /* 851 */ false,
11771 /* 852 */ false,
11772 /* 853 */ false,
11773 /* 854 */ false,
11774 /* 855 */ false,
11775 /* 856 */ false,
11776 /* 857 */ false,
11777 /* 858 */ false,
11778 /* 859 */ false,
11779 /* 860 */ false,
11780 /* 861 */ false,
11781 /* 862 */ false,
11782 /* 863 */ false,
11783 /* 864 */ false,
11784 /* 865 */ false,
11785 /* 866 */ false,
11786 /* 867 */ false,
11787 /* 868 */ false,
11788 /* 869 */ false,
11789 /* 870 */ false,
11790 /* 871 */ false,
11791 /* 872 */ false,
11792 /* 873 */ false,
11793 /* 874 */ false,
11794 /* 875 */ false,
11795 /* 876 */ false,
11796 /* 877 */ false,
11797 /* 878 */ false,
11798 /* 879 */ false,
11799 /* 880 */ false,
11800 /* 881 */ false,
11801 /* 882 */ false,
11802 /* 883 */ false,
11803 /* 884 */ false,
11804 /* 885 */ false,
11805 /* 886 */ false,
11806 /* 887 */ false,
11807 /* 888 */ false,
11808 /* 889 */ false,
11809 /* 890 */ false,
11810 /* 891 */ false,
11811 /* 892 */ false,
11812 /* 893 */ false,
11813 /* 894 */ false,
11814 /* 895 */ false,
11815 /* 896 */ false,
11816 /* 897 */ false,
11817 /* 898 */ false,
11818 /* 899 */ false,
11819 /* 900 */ false,
11820 /* 901 */ false,
11821 /* 902 */ false,
11822 /* 903 */ false,
11823 /* 904 */ false,
11824 /* 905 */ false,
11825 /* 906 */ false,
11826 /* 907 */ false,
11827 /* 908 */ false,
11828 /* 909 */ false,
11829 /* 910 */ false,
11830 /* 911 */ false,
11831 /* 912 */ false,
11832 /* 913 */ false,
11833 /* 914 */ false,
11834 /* 915 */ false,
11835 /* 916 */ false,
11836 /* 917 */ false,
11837 /* 918 */ false,
11838 /* 919 */ false,
11839 /* 920 */ false,
11840 /* 921 */ false,
11841 /* 922 */ false,
11842 /* 923 */ false,
11843 /* 924 */ false,
11844 /* 925 */ false,
11845 /* 926 */ false,
11846 /* 927 */ false,
11847 /* 928 */ false,
11848 /* 929 */ false,
11849 /* 930 */ false,
11850 /* 931 */ false,
11851 /* 932 */ false,
11852 /* 933 */ false,
11853 /* 934 */ false,
11854 /* 935 */ false,
11855 /* 936 */ false,
11856 /* 937 */ false,
11857 /* 938 */ false,
11858 /* 939 */ false,
11859 /* 940 */ false,
11860 /* 941 */ false,
11861 /* 942 */ false,
11862 /* 943 */ false,
11863 /* 944 */ false,
11864 /* 945 */ false,
11865 /* 946 */ false,
11866 /* 947 */ false,
11867 /* 948 */ false,
11868 /* 949 */ false,
11869 /* 950 */ false,
11870 /* 951 */ false,
11871 /* 952 */ false,
11872 /* 953 */ false,
11873 /* 954 */ false,
11874 /* 955 */ false,
11875 /* 956 */ false,
11876 /* 957 */ false,
11877 /* 958 */ false,
11878 /* 959 */ false,
11879 /* 960 */ false,
11880 /* 961 */ false,
11881 /* 962 */ false,
11882 /* 963 */ false,
11883 /* 964 */ false,
11884 /* 965 */ false,
11885 /* 966 */ false,
11886 /* 967 */ false,
11887 /* 968 */ false,
11888 /* 969 */ false,
11889 /* 970 */ false,
11890 /* 971 */ false,
11891 /* 972 */ false,
11892 /* 973 */ false,
11893 /* 974 */ false,
11894 /* 975 */ false,
11895 /* 976 */ false,
11896 /* 977 */ false,
11897 /* 978 */ false,
11898 /* 979 */ false,
11899 /* 980 */ false,
11900 /* 981 */ false,
11901 /* 982 */ false,
11902 /* 983 */ false,
11903 /* 984 */ false,
11904 /* 985 */ false,
11905 /* 986 */ false,
11906 /* 987 */ false,
11907 /* 988 */ false,
11908 /* 989 */ false,
11909 /* 990 */ false,
11910 /* 991 */ false,
11911 /* 992 */ false,
11912 /* 993 */ false,
11913 /* 994 */ false,
11914 /* 995 */ false,
11915 /* 996 */ false,
11916 /* 997 */ false,
11917 /* 998 */ false,
11918 /* 999 */ false,
11919 /* 1000 */ false,
11920 /* 1001 */ false,
11921 /* 1002 */ false,
11922 /* 1003 */ false,
11923 /* 1004 */ false,
11924 /* 1005 */ false,
11925 /* 1006 */ false,
11926 /* 1007 */ false,
11927 /* 1008 */ false,
11928 /* 1009 */ false,
11929 /* 1010 */ false,
11930 /* 1011 */ false,
11931 /* 1012 */ false,
11932 /* 1013 */ false,
11933 /* 1014 */ false,
11934 /* 1015 */ false,
11935 /* 1016 */ false,
11936 /* 1017 */ false,
11937 /* 1018 */ false,
11938 /* 1019 */ false,
11939 /* 1020 */ false,
11940 /* 1021 */ false,
11941 /* 1022 */ false,
11942 /* 1023 */ false,
11943 /* 1024 */ false,
11944 /* 1025 */ false,
11945 /* 1026 */ false,
11946 /* 1027 */ false,
11947 /* 1028 */ false,
11948 /* 1029 */ false,
11949 /* 1030 */ false,
11950 /* 1031 */ false,
11951 /* 1032 */ false,
11952 /* 1033 */ false,
11953 /* 1034 */ false,
11954 /* 1035 */ false,
11955 /* 1036 */ false,
11956 /* 1037 */ false,
11957 /* 1038 */ false,
11958 /* 1039 */ false,
11959 /* 1040 */ false,
11960 /* 1041 */ false,
11961 /* 1042 */ false,
11962 /* 1043 */ false,
11963 /* 1044 */ false,
11964 /* 1045 */ false,
11965 /* 1046 */ false,
11966 /* 1047 */ false,
11967 /* 1048 */ false,
11968 /* 1049 */ false,
11969 /* 1050 */ false,
11970 /* 1051 */ false,
11971 /* 1052 */ false,
11972 /* 1053 */ false,
11973 /* 1054 */ false,
11974 /* 1055 */ false,
11975 /* 1056 */ false,
11976 /* 1057 */ false,
11977 /* 1058 */ false,
11978 /* 1059 */ false,
11979 /* 1060 */ false,
11980 /* 1061 */ false,
11981 /* 1062 */ false,
11982 /* 1063 */ false,
11983 /* 1064 */ false,
11984 /* 1065 */ false,
11985 /* 1066 */ false,
11986 /* 1067 */ false,
11987 /* 1068 */ false,
11988 /* 1069 */ false,
11989 /* 1070 */ false,
11990 /* 1071 */ false,
11991 /* 1072 */ false,
11992 /* 1073 */ false,
11993 /* 1074 */ false,
11994 /* 1075 */ false,
11995 /* 1076 */ false,
11996 /* 1077 */ false,
11997 /* 1078 */ false,
11998 /* 1079 */ false,
11999 /* 1080 */ false,
12000 /* 1081 */ false,
12001 /* 1082 */ false,
12002 /* 1083 */ false,
12003 /* 1084 */ false,
12004 /* 1085 */ false,
12005 /* 1086 */ false,
12006 /* 1087 */ false,
12007 /* 1088 */ false,
12008 /* 1089 */ false,
12009 /* 1090 */ false,
12010 /* 1091 */ false,
12011 /* 1092 */ false,
12012 /* 1093 */ false,
12013 /* 1094 */ false,
12014 /* 1095 */ false,
12015 /* 1096 */ false,
12016 /* 1097 */ false,
12017 /* 1098 */ false,
12018 /* 1099 */ false,
12019 /* 1100 */ false,
12020 /* 1101 */ false,
12021 /* 1102 */ false,
12022 /* 1103 */ false,
12023 /* 1104 */ false,
12024 /* 1105 */ false,
12025 /* 1106 */ false,
12026 /* 1107 */ false,
12027 /* 1108 */ false,
12028 /* 1109 */ false,
12029 /* 1110 */ false,
12030 /* 1111 */ false,
12031 /* 1112 */ false,
12032 /* 1113 */ false,
12033 /* 1114 */ false,
12034 /* 1115 */ false,
12035 /* 1116 */ false,
12036 /* 1117 */ false,
12037 /* 1118 */ false,
12038 /* 1119 */ false,
12039 /* 1120 */ false,
12040 /* 1121 */ false,
12041 /* 1122 */ false,
12042 /* 1123 */ false,
12043 /* 1124 */ false,
12044 /* 1125 */ false,
12045 /* 1126 */ false,
12046 /* 1127 */ false,
12047 /* 1128 */ false,
12048 /* 1129 */ false,
12049 /* 1130 */ false,
12050 /* 1131 */ false,
12051 /* 1132 */ false,
12052 /* 1133 */ false,
12053 /* 1134 */ false,
12054 /* 1135 */ false,
12055 /* 1136 */ false,
12056 /* 1137 */ false,
12057 /* 1138 */ false,
12058 /* 1139 */ false,
12059 /* 1140 */ false,
12060 /* 1141 */ false,
12061 /* 1142 */ false,
12062 /* 1143 */ false,
12063 /* 1144 */ false,
12064 /* 1145 */ false,
12065 /* 1146 */ false,
12066 /* 1147 */ false,
12067 /* 1148 */ false,
12068 /* 1149 */ false,
12069 /* 1150 */ false,
12070 /* 1151 */ false,
12071 /* 1152 */ false,
12072 /* 1153 */ false,
12073 /* 1154 */ false,
12074 /* 1155 */ false,
12075 /* 1156 */ false,
12076 /* 1157 */ false,
12077 /* 1158 */ false,
12078 /* 1159 */ false,
12079 /* 1160 */ false,
12080 /* 1161 */ false,
12081 /* 1162 */ false,
12082 /* 1163 */ false,
12083 /* 1164 */ false,
12084 /* 1165 */ false,
12085 /* 1166 */ false,
12086 /* 1167 */ false,
12087 /* 1168 */ false,
12088 /* 1169 */ false,
12089 /* 1170 */ false,
12090 /* 1171 */ false,
12091 /* 1172 */ false,
12092 /* 1173 */ false,
12093 /* 1174 */ false,
12094 /* 1175 */ false,
12095 /* 1176 */ false,
12096 /* 1177 */ false,
12097 /* 1178 */ false,
12098 /* 1179 */ false,
12099 /* 1180 */ false,
12100 /* 1181 */ false,
12101 /* 1182 */ false,
12102 /* 1183 */ false,
12103 /* 1184 */ false,
12104 /* 1185 */ false,
12105 /* 1186 */ false,
12106 /* 1187 */ false,
12107 /* 1188 */ false,
12108 /* 1189 */ false,
12109 /* 1190 */ false,
12110 /* 1191 */ false,
12111 /* 1192 */ false,
12112 /* 1193 */ false,
12113 /* 1194 */ false,
12114 /* 1195 */ false,
12115 /* 1196 */ false,
12116 /* 1197 */ false,
12117 /* 1198 */ false,
12118 /* 1199 */ false,
12119 /* 1200 */ false,
12120 /* 1201 */ false,
12121 /* 1202 */ false,
12122 /* 1203 */ false,
12123 /* 1204 */ false,
12124 /* 1205 */ false,
12125 /* 1206 */ false,
12126 /* 1207 */ false,
12127 /* 1208 */ false,
12128 /* 1209 */ false,
12129 /* 1210 */ false,
12130 /* 1211 */ false,
12131 /* 1212 */ false,
12132 /* 1213 */ false,
12133 /* 1214 */ false,
12134 /* 1215 */ false,
12135 /* 1216 */ false,
12136 /* 1217 */ false,
12137 /* 1218 */ false,
12138 /* 1219 */ false,
12139 /* 1220 */ false,
12140 /* 1221 */ false,
12141 /* 1222 */ false,
12142 /* 1223 */ false,
12143 /* 1224 */ false,
12144 /* 1225 */ false,
12145 /* 1226 */ false,
12146 /* 1227 */ false,
12147 /* 1228 */ false,
12148 /* 1229 */ false,
12149 /* 1230 */ false,
12150 /* 1231 */ false,
12151 /* 1232 */ false,
12152 /* 1233 */ false,
12153 /* 1234 */ false,
12154 /* 1235 */ false,
12155 /* 1236 */ false,
12156 /* 1237 */ false,
12157 /* 1238 */ false,
12158 /* 1239 */ false,
12159 /* 1240 */ false,
12160 /* 1241 */ false,
12161 /* 1242 */ false,
12162 /* 1243 */ false,
12163 /* 1244 */ false,
12164 /* 1245 */ false,
12165 /* 1246 */ false,
12166 /* 1247 */ false,
12167 /* 1248 */ false,
12168 /* 1249 */ false,
12169 /* 1250 */ false,
12170 /* 1251 */ false,
12171 /* 1252 */ false,
12172 /* 1253 */ false,
12173 /* 1254 */ false,
12174 /* 1255 */ false,
12175 /* 1256 */ false,
12176 /* 1257 */ false,
12177 /* 1258 */ false,
12178 /* 1259 */ false,
12179 /* 1260 */ false,
12180 /* 1261 */ false,
12181 /* 1262 */ false,
12182 /* 1263 */ false,
12183 /* 1264 */ false,
12184 /* 1265 */ false,
12185 /* 1266 */ false,
12186 /* 1267 */ false,
12187 /* 1268 */ false,
12188 /* 1269 */ false,
12189 /* 1270 */ false,
12190 /* 1271 */ false,
12191 /* 1272 */ false,
12192 /* 1273 */ false,
12193 /* 1274 */ false,
12194 /* 1275 */ false,
12195 /* 1276 */ false,
12196 /* 1277 */ false,
12197 /* 1278 */ false,
12198 /* 1279 */ false,
12199 /* 1280 */ false,
12200 /* 1281 */ false,
12201 /* 1282 */ false,
12202 /* 1283 */ false,
12203 /* 1284 */ false,
12204 /* 1285 */ false,
12205 /* 1286 */ false,
12206 /* 1287 */ false,
12207 /* 1288 */ false,
12208 /* 1289 */ false,
12209 /* 1290 */ false,
12210 /* 1291 */ false,
12211 /* 1292 */ false,
12212 /* 1293 */ false,
12213 /* 1294 */ false,
12214 /* 1295 */ false,
12215 /* 1296 */ false,
12216 /* 1297 */ false,
12217 /* 1298 */ false,
12218 /* 1299 */ false,
12219 /* 1300 */ false,
12220 /* 1301 */ false,
12221 /* 1302 */ false,
12222 /* 1303 */ false,
12223 /* 1304 */ false,
12224 /* 1305 */ false,
12225 /* 1306 */ false,
12226 /* 1307 */ false,
12227 /* 1308 */ false,
12228 /* 1309 */ false,
12229 /* 1310 */ false,
12230 /* 1311 */ false,
12231 /* 1312 */ false,
12232 /* 1313 */ false,
12233 /* 1314 */ false,
12234 /* 1315 */ false,
12235 /* 1316 */ false,
12236 /* 1317 */ false,
12237 /* 1318 */ false,
12238 /* 1319 */ false,
12239 /* 1320 */ false,
12240 /* 1321 */ false,
12241 /* 1322 */ false,
12242 /* 1323 */ false,
12243 /* 1324 */ false,
12244 /* 1325 */ false,
12245 /* 1326 */ false,
12246 /* 1327 */ false,
12247 /* 1328 */ false,
12248 /* 1329 */ false,
12249 /* 1330 */ false,
12250 /* 1331 */ false,
12251 /* 1332 */ false,
12252 /* 1333 */ false,
12253 /* 1334 */ false,
12254 /* 1335 */ false,
12255 /* 1336 */ false,
12256 /* 1337 */ false,
12257 /* 1338 */ false,
12258 /* 1339 */ false,
12259 /* 1340 */ false,
12260 /* 1341 */ false,
12261 /* 1342 */ false,
12262 /* 1343 */ false,
12263 /* 1344 */ false,
12264 /* 1345 */ false,
12265 /* 1346 */ false,
12266 /* 1347 */ false,
12267 /* 1348 */ false,
12268 /* 1349 */ false,
12269 /* 1350 */ false,
12270 /* 1351 */ false,
12271 /* 1352 */ false,
12272 /* 1353 */ false,
12273 /* 1354 */ false,
12274 /* 1355 */ false,
12275 /* 1356 */ false,
12276 /* 1357 */ false,
12277 /* 1358 */ false,
12278 /* 1359 */ false,
12279 /* 1360 */ false,
12280 /* 1361 */ false,
12281 /* 1362 */ false,
12282 /* 1363 */ false,
12283 /* 1364 */ false,
12284 /* 1365 */ false,
12285 /* 1366 */ false,
12286 /* 1367 */ false,
12287 /* 1368 */ false,
12288 /* 1369 */ false,
12289 /* 1370 */ false,
12290 /* 1371 */ false,
12291 /* 1372 */ false,
12292 /* 1373 */ false,
12293 /* 1374 */ false,
12294 /* 1375 */ false,
12295 /* 1376 */ false,
12296 /* 1377 */ false,
12297 /* 1378 */ false,
12298 /* 1379 */ false,
12299 /* 1380 */ false,
12300 /* 1381 */ false,
12301 /* 1382 */ false,
12302 /* 1383 */ false,
12303 /* 1384 */ false,
12304 /* 1385 */ false,
12305 /* 1386 */ false,
12306 /* 1387 */ false,
12307 /* 1388 */ false,
12308 /* 1389 */ false,
12309 /* 1390 */ false,
12310 /* 1391 */ false,
12311 /* 1392 */ false,
12312 /* 1393 */ false,
12313 /* 1394 */ false,
12314 /* 1395 */ false,
12315 /* 1396 */ false,
12316 /* 1397 */ false,
12317 /* 1398 */ false,
12318 /* 1399 */ false,
12319 /* 1400 */ false,
12320 /* 1401 */ false,
12321 /* 1402 */ false,
12322 /* 1403 */ false,
12323 /* 1404 */ false,
12324 /* 1405 */ false,
12325 /* 1406 */ false,
12326 /* 1407 */ false,
12327 /* 1408 */ false,
12328 /* 1409 */ false,
12329 /* 1410 */ false,
12330 /* 1411 */ false,
12331 /* 1412 */ false,
12332 /* 1413 */ false,
12333 /* 1414 */ false,
12334 /* 1415 */ false,
12335 /* 1416 */ false,
12336 /* 1417 */ false,
12337 /* 1418 */ false,
12338 /* 1419 */ false,
12339 /* 1420 */ false,
12340 /* 1421 */ false,
12341 /* 1422 */ false,
12342 /* 1423 */ false,
12343 /* 1424 */ false,
12344 /* 1425 */ false,
12345 /* 1426 */ false,
12346 /* 1427 */ false,
12347 /* 1428 */ false,
12348 /* 1429 */ false,
12349 /* 1430 */ false,
12350 /* 1431 */ false,
12351 /* 1432 */ false,
12352 /* 1433 */ false,
12353 /* 1434 */ false,
12354 /* 1435 */ false,
12355 /* 1436 */ false,
12356 /* 1437 */ false,
12357 /* 1438 */ false,
12358 /* 1439 */ false,
12359 /* 1440 */ false,
12360 /* 1441 */ false,
12361 /* 1442 */ false,
12362 /* 1443 */ false,
12363 /* 1444 */ false,
12364 /* 1445 */ false,
12365 /* 1446 */ false,
12366 /* 1447 */ false,
12367 /* 1448 */ false,
12368 /* 1449 */ false,
12369 /* 1450 */ false,
12370 /* 1451 */ false,
12371 /* 1452 */ false,
12372 /* 1453 */ false,
12373 /* 1454 */ false,
12374 /* 1455 */ false,
12375 /* 1456 */ false,
12376 /* 1457 */ false,
12377 /* 1458 */ false,
12378 /* 1459 */ false,
12379 /* 1460 */ false,
12380 /* 1461 */ false,
12381 /* 1462 */ false,
12382 /* 1463 */ false,
12383 /* 1464 */ false,
12384 /* 1465 */ false,
12385 /* 1466 */ false,
12386 /* 1467 */ false,
12387 /* 1468 */ false,
12388 /* 1469 */ false,
12389 /* 1470 */ false,
12390 /* 1471 */ false,
12391 /* 1472 */ false,
12392 /* 1473 */ false,
12393 /* 1474 */ false,
12394 /* 1475 */ false,
12395 /* 1476 */ false,
12396 /* 1477 */ false,
12397 /* 1478 */ false,
12398 /* 1479 */ false,
12399 /* 1480 */ false,
12400 /* 1481 */ false,
12401 /* 1482 */ false,
12402 /* 1483 */ false,
12403 /* 1484 */ false,
12404 /* 1485 */ false,
12405 /* 1486 */ false,
12406 /* 1487 */ false,
12407 /* 1488 */ false,
12408 /* 1489 */ false,
12409 /* 1490 */ false,
12410 /* 1491 */ false,
12411 /* 1492 */ false,
12412 /* 1493 */ false,
12413 /* 1494 */ false,
12414 /* 1495 */ false,
12415 /* 1496 */ false,
12416 /* 1497 */ false,
12417 /* 1498 */ false,
12418 /* 1499 */ false,
12419 /* 1500 */ false,
12420 /* 1501 */ false,
12421 /* 1502 */ false,
12422 /* 1503 */ false,
12423 /* 1504 */ false,
12424 /* 1505 */ false,
12425 /* 1506 */ false,
12426 /* 1507 */ false,
12427 /* 1508 */ false,
12428 /* 1509 */ false,
12429 /* 1510 */ false,
12430 /* 1511 */ false,
12431 /* 1512 */ false,
12432 /* 1513 */ false,
12433 /* 1514 */ false,
12434 /* 1515 */ false,
12435 /* 1516 */ false,
12436 /* 1517 */ false,
12437 /* 1518 */ false,
12438 /* 1519 */ false,
12439 /* 1520 */ false,
12440 /* 1521 */ false,
12441 /* 1522 */ false,
12442 /* 1523 */ false,
12443 /* 1524 */ false,
12444 /* 1525 */ false,
12445 /* 1526 */ false,
12446 /* 1527 */ false,
12447 /* 1528 */ false,
12448 /* 1529 */ false,
12449 /* 1530 */ false,
12450 /* 1531 */ false,
12451 /* 1532 */ false,
12452 /* 1533 */ false,
12453 /* 1534 */ false,
12454 /* 1535 */ false,
12455 /* 1536 */ false,
12456 /* 1537 */ false,
12457 /* 1538 */ false,
12458 /* 1539 */ false,
12459 /* 1540 */ false,
12460 /* 1541 */ false,
12461 /* 1542 */ false,
12462 /* 1543 */ false,
12463 /* 1544 */ false,
12464 /* 1545 */ false,
12465 /* 1546 */ false,
12466 /* 1547 */ false,
12467 /* 1548 */ false,
12468 /* 1549 */ false,
12469 /* 1550 */ false,
12470 /* 1551 */ false,
12471 /* 1552 */ false,
12472 /* 1553 */ false,
12473 /* 1554 */ false,
12474 /* 1555 */ false,
12475 /* 1556 */ false,
12476 /* 1557 */ false,
12477 /* 1558 */ false,
12478 /* 1559 */ false,
12479 /* 1560 */ false,
12480 /* 1561 */ false,
12481 /* 1562 */ false,
12482 /* 1563 */ false,
12483 /* 1564 */ false,
12484 /* 1565 */ false,
12485 /* 1566 */ false,
12486 /* 1567 */ false,
12487 /* 1568 */ false,
12488 // last instruction
12489 false // no trailing comma
12490};
12491
12492// Mapping from machine-independent opcode to boolean
12493const char must_clone[] = {
12494 0, // Node: 0
12495 0, // Set: 1
12496 0, // RegN: 2
12497 0, // RegI: 3
12498 0, // RegP: 4
12499 0, // RegF: 5
12500 0, // RegD: 6
12501 0, // RegL: 7
12502 0, // VecA: 8
12503 0, // VecS: 9
12504 0, // VecD: 10
12505 0, // VecX: 11
12506 0, // VecY: 12
12507 0, // VecZ: 13
12508 0, // RegVectMask: 14
12509 0, // RegFlags: 15
12510 0, // _last_machine_leaf: 16
12511 0, // AbsD: 17
12512 0, // AbsF: 18
12513 0, // AbsI: 19
12514 0, // AbsL: 20
12515 0, // AddD: 21
12516 0, // AddF: 22
12517 0, // AddI: 23
12518 0, // AddL: 24
12519 0, // AddP: 25
12520 0, // Allocate: 26
12521 0, // AllocateArray: 27
12522 0, // AndI: 28
12523 0, // AndL: 29
12524 0, // ArrayCopy: 30
12525 0, // AryEq: 31
12526 0, // AtanD: 32
12527 1, // Binary: 33
12528 0, // Blackhole: 34
12529 1, // Bool: 35
12530 0, // BoxLock: 36
12531 0, // ReverseBytesI: 37
12532 0, // ReverseBytesL: 38
12533 0, // ReverseBytesUS: 39
12534 0, // ReverseBytesS: 40
12535 0, // CProj: 41
12536 0, // CacheWB: 42
12537 0, // CacheWBPreSync: 43
12538 0, // CacheWBPostSync: 44
12539 0, // CallDynamicJava: 45
12540 0, // CallJava: 46
12541 0, // CallLeaf: 47
12542 0, // CallLeafNoFP: 48
12543 0, // CallLeafVector: 49
12544 0, // CallRuntime: 50
12545 0, // CallNative: 51
12546 0, // CallStaticJava: 52
12547 0, // CastDD: 53
12548 0, // CastFF: 54
12549 0, // CastII: 55
12550 0, // CastLL: 56
12551 0, // CastVV: 57
12552 0, // CastX2P: 58
12553 0, // CastP2X: 59
12554 0, // CastPP: 60
12555 0, // Catch: 61
12556 0, // CatchProj: 62
12557 0, // CheckCastPP: 63
12558 0, // ClearArray: 64
12559 0, // ConstraintCast: 65
12560 0, // CMoveD: 66
12561 0, // CMoveVD: 67
12562 0, // CMoveF: 68
12563 0, // CMoveVF: 69
12564 0, // CMoveI: 70
12565 0, // CMoveL: 71
12566 0, // CMoveP: 72
12567 0, // CMoveN: 73
12568 1, // CmpN: 74
12569 1, // CmpD: 75
12570 0, // CmpD3: 76
12571 1, // CmpF: 77
12572 0, // CmpF3: 78
12573 1, // CmpI: 79
12574 1, // CmpL: 80
12575 0, // CmpL3: 81
12576 0, // CmpLTMask: 82
12577 1, // CmpP: 83
12578 1, // CmpU: 84
12579 1, // CmpUL: 85
12580 0, // CompareAndSwapB: 86
12581 0, // CompareAndSwapS: 87
12582 0, // CompareAndSwapI: 88
12583 0, // CompareAndSwapL: 89
12584 0, // CompareAndSwapP: 90
12585 0, // CompareAndSwapN: 91
12586 0, // WeakCompareAndSwapB: 92
12587 0, // WeakCompareAndSwapS: 93
12588 0, // WeakCompareAndSwapI: 94
12589 0, // WeakCompareAndSwapL: 95
12590 0, // WeakCompareAndSwapP: 96
12591 0, // WeakCompareAndSwapN: 97
12592 0, // CompareAndExchangeB: 98
12593 0, // CompareAndExchangeS: 99
12594 0, // CompareAndExchangeI: 100
12595 0, // CompareAndExchangeL: 101
12596 0, // CompareAndExchangeP: 102
12597 0, // CompareAndExchangeN: 103
12598 0, // GetAndAddB: 104
12599 0, // GetAndAddS: 105
12600 0, // GetAndAddI: 106
12601 0, // GetAndAddL: 107
12602 0, // GetAndSetB: 108
12603 0, // GetAndSetS: 109
12604 0, // GetAndSetI: 110
12605 0, // GetAndSetL: 111
12606 0, // GetAndSetP: 112
12607 0, // GetAndSetN: 113
12608 0, // Con: 114
12609 0, // ConN: 115
12610 0, // ConNKlass: 116
12611 0, // ConD: 117
12612 0, // ConF: 118
12613 0, // ConI: 119
12614 0, // ConL: 120
12615 0, // ConP: 121
12616 0, // Conv2B: 122
12617 0, // ConvD2F: 123
12618 0, // ConvD2I: 124
12619 0, // ConvD2L: 125
12620 0, // ConvF2D: 126
12621 0, // ConvF2I: 127
12622 0, // ConvF2L: 128
12623 0, // ConvI2D: 129
12624 0, // ConvI2F: 130
12625 0, // ConvI2L: 131
12626 0, // ConvL2D: 132
12627 0, // ConvL2F: 133
12628 0, // ConvL2I: 134
12629 0, // CountedLoop: 135
12630 0, // CountedLoopEnd: 136
12631 0, // OuterStripMinedLoop: 137
12632 0, // OuterStripMinedLoopEnd: 138
12633 0, // LongCountedLoop: 139
12634 0, // LongCountedLoopEnd: 140
12635 0, // CountLeadingZerosI: 141
12636 0, // CountLeadingZerosL: 142
12637 0, // CountTrailingZerosI: 143
12638 0, // CountTrailingZerosL: 144
12639 0, // CreateEx: 145
12640 0, // DecodeN: 146
12641 0, // DecodeNKlass: 147
12642 0, // DivD: 148
12643 0, // DivF: 149
12644 0, // DivI: 150
12645 0, // DivL: 151
12646 0, // DivMod: 152
12647 0, // DivModI: 153
12648 0, // DivModL: 154
12649 0, // EncodeISOArray: 155
12650 0, // EncodeP: 156
12651 0, // EncodePKlass: 157
12652 1, // FastLock: 158
12653 1, // FastUnlock: 159
12654 0, // FmaD: 160
12655 0, // FmaF: 161
12656 0, // Goto: 162
12657 0, // Halt: 163
12658 0, // HasNegatives: 164
12659 0, // If: 165
12660 0, // RangeCheck: 166
12661 0, // IfFalse: 167
12662 0, // IfTrue: 168
12663 0, // Initialize: 169
12664 0, // JProj: 170
12665 0, // Jump: 171
12666 0, // JumpProj: 172
12667 0, // LShiftI: 173
12668 0, // LShiftL: 174
12669 0, // LoadB: 175
12670 0, // LoadUB: 176
12671 0, // LoadUS: 177
12672 0, // LoadD: 178
12673 0, // LoadD_unaligned: 179
12674 0, // LoadF: 180
12675 0, // LoadI: 181
12676 0, // LoadKlass: 182
12677 0, // LoadNKlass: 183
12678 0, // LoadL: 184
12679 0, // LoadL_unaligned: 185
12680 0, // LoadPLocked: 186
12681 0, // LoadP: 187
12682 0, // LoadN: 188
12683 0, // LoadRange: 189
12684 0, // LoadS: 190
12685 0, // Lock: 191
12686 0, // Loop: 192
12687 0, // LoopLimit: 193
12688 0, // Mach: 194
12689 0, // MachNullCheck: 195
12690 0, // MachProj: 196
12691 0, // MulAddS2I: 197
12692 0, // MaxI: 198
12693 0, // MaxL: 199
12694 0, // MaxD: 200
12695 0, // MaxF: 201
12696 0, // MemBarAcquire: 202
12697 0, // LoadFence: 203
12698 0, // SetVectMaskI: 204
12699 0, // MemBarAcquireLock: 205
12700 0, // MemBarCPUOrder: 206
12701 0, // MemBarRelease: 207
12702 0, // StoreFence: 208
12703 0, // StoreStoreFence: 209
12704 0, // MemBarReleaseLock: 210
12705 0, // MemBarVolatile: 211
12706 0, // MemBarStoreStore: 212
12707 0, // MergeMem: 213
12708 0, // MinI: 214
12709 0, // MinL: 215
12710 0, // MinF: 216
12711 0, // MinD: 217
12712 0, // ModD: 218
12713 0, // ModF: 219
12714 0, // ModI: 220
12715 0, // ModL: 221
12716 0, // MoveI2F: 222
12717 0, // MoveF2I: 223
12718 0, // MoveL2D: 224
12719 0, // MoveD2L: 225
12720 0, // MulD: 226
12721 0, // MulF: 227
12722 0, // MulHiL: 228
12723 0, // UMulHiL: 229
12724 0, // MulI: 230
12725 0, // MulL: 231
12726 0, // Multi: 232
12727 0, // NegI: 233
12728 0, // NegL: 234
12729 0, // NegD: 235
12730 0, // NegF: 236
12731 0, // NeverBranch: 237
12732 0, // OnSpinWait: 238
12733 0, // Opaque1: 239
12734 0, // OpaqueLoopInit: 240
12735 0, // OpaqueLoopStride: 241
12736 0, // Opaque2: 242
12737 0, // Opaque3: 243
12738 0, // Opaque4: 244
12739 0, // ProfileBoolean: 245
12740 0, // OrI: 246
12741 0, // OrL: 247
12742 1, // OverflowAddI: 248
12743 1, // OverflowSubI: 249
12744 1, // OverflowMulI: 250
12745 1, // OverflowAddL: 251
12746 1, // OverflowSubL: 252
12747 1, // OverflowMulL: 253
12748 0, // PCTable: 254
12749 0, // Parm: 255
12750 0, // PartialSubtypeCheck: 256
12751 0, // SubTypeCheck: 257
12752 0, // Phi: 258
12753 0, // PopCountI: 259
12754 0, // PopCountL: 260
12755 0, // PopCountVI: 261
12756 0, // PrefetchAllocation: 262
12757 0, // Proj: 263
12758 0, // RShiftI: 264
12759 0, // RShiftL: 265
12760 0, // Region: 266
12761 0, // Rethrow: 267
12762 0, // Return: 268
12763 0, // Root: 269
12764 0, // RoundDouble: 270
12765 0, // RoundDoubleMode: 271
12766 0, // RoundDoubleModeV: 272
12767 0, // RoundFloat: 273
12768 0, // RotateLeft: 274
12769 0, // RotateLeftV: 275
12770 0, // RotateRight: 276
12771 0, // RotateRightV: 277
12772 0, // SafePoint: 278
12773 0, // SafePointScalarObject: 279
12774 0, // ShenandoahCompareAndExchangeP: 280
12775 0, // ShenandoahCompareAndExchangeN: 281
12776 0, // ShenandoahCompareAndSwapN: 282
12777 0, // ShenandoahCompareAndSwapP: 283
12778 0, // ShenandoahWeakCompareAndSwapN: 284
12779 0, // ShenandoahWeakCompareAndSwapP: 285
12780 0, // ShenandoahIUBarrier: 286
12781 0, // ShenandoahLoadReferenceBarrier: 287
12782 0, // SCMemProj: 288
12783 0, // CopySignD: 289
12784 0, // CopySignF: 290
12785 0, // SignumD: 291
12786 0, // SignumF: 292
12787 0, // SqrtD: 293
12788 0, // SqrtF: 294
12789 0, // Start: 295
12790 0, // StartOSR: 296
12791 0, // StoreB: 297
12792 0, // StoreC: 298
12793 0, // StoreCM: 299
12794 0, // StorePConditional: 300
12795 0, // StoreIConditional: 301
12796 0, // StoreLConditional: 302
12797 0, // StoreD: 303
12798 0, // StoreF: 304
12799 0, // StoreI: 305
12800 0, // StoreL: 306
12801 0, // StoreP: 307
12802 0, // StoreN: 308
12803 0, // StoreNKlass: 309
12804 0, // StrComp: 310
12805 0, // StrCompressedCopy: 311
12806 0, // StrEquals: 312
12807 0, // StrIndexOf: 313
12808 0, // StrIndexOfChar: 314
12809 0, // StrInflatedCopy: 315
12810 0, // SubD: 316
12811 0, // SubF: 317
12812 0, // SubI: 318
12813 0, // SubL: 319
12814 0, // TailCall: 320
12815 0, // TailJump: 321
12816 0, // MacroLogicV: 322
12817 0, // ThreadLocal: 323
12818 0, // Unlock: 324
12819 0, // URShiftB: 325
12820 0, // URShiftS: 326
12821 0, // URShiftI: 327
12822 0, // URShiftL: 328
12823 0, // XorI: 329
12824 0, // XorL: 330
12825 0, // Vector: 331
12826 0, // AddVB: 332
12827 0, // AddVS: 333
12828 0, // AddVI: 334
12829 0, // AddReductionVI: 335
12830 0, // AddVL: 336
12831 0, // AddReductionVL: 337
12832 0, // AddVF: 338
12833 0, // AddReductionVF: 339
12834 0, // AddVD: 340
12835 0, // AddReductionVD: 341
12836 0, // SubVB: 342
12837 0, // SubVS: 343
12838 0, // SubVI: 344
12839 0, // SubVL: 345
12840 0, // SubVF: 346
12841 0, // SubVD: 347
12842 0, // MulVB: 348
12843 0, // MulVS: 349
12844 0, // MulVI: 350
12845 0, // MulReductionVI: 351
12846 0, // MulVL: 352
12847 0, // MulReductionVL: 353
12848 0, // MulVF: 354
12849 0, // MulReductionVF: 355
12850 0, // MulVD: 356
12851 0, // MulReductionVD: 357
12852 0, // MulAddVS2VI: 358
12853 0, // FmaVD: 359
12854 0, // FmaVF: 360
12855 0, // DivVF: 361
12856 0, // DivVD: 362
12857 0, // AbsVB: 363
12858 0, // AbsVS: 364
12859 0, // AbsVI: 365
12860 0, // AbsVL: 366
12861 0, // AbsVF: 367
12862 0, // AbsVD: 368
12863 0, // NegVI: 369
12864 0, // NegVF: 370
12865 0, // NegVD: 371
12866 0, // SqrtVD: 372
12867 0, // SqrtVF: 373
12868 0, // LShiftCntV: 374
12869 0, // RShiftCntV: 375
12870 0, // LShiftVB: 376
12871 0, // LShiftVS: 377
12872 0, // LShiftVI: 378
12873 0, // LShiftVL: 379
12874 0, // RShiftVB: 380
12875 0, // RShiftVS: 381
12876 0, // RShiftVI: 382
12877 0, // RShiftVL: 383
12878 0, // URShiftVB: 384
12879 0, // URShiftVS: 385
12880 0, // URShiftVI: 386
12881 0, // URShiftVL: 387
12882 0, // AndV: 388
12883 0, // AndReductionV: 389
12884 0, // OrV: 390
12885 0, // OrReductionV: 391
12886 0, // XorV: 392
12887 0, // XorReductionV: 393
12888 0, // MinV: 394
12889 0, // MaxV: 395
12890 0, // MinReductionV: 396
12891 0, // MaxReductionV: 397
12892 0, // LoadVector: 398
12893 0, // LoadVectorGather: 399
12894 0, // LoadVectorGatherMasked: 400
12895 0, // StoreVector: 401
12896 0, // StoreVectorScatter: 402
12897 0, // StoreVectorScatterMasked: 403
12898 0, // LoadVectorMasked: 404
12899 0, // StoreVectorMasked: 405
12900 0, // VectorCmpMasked: 406
12901 0, // VectorMaskGen: 407
12902 0, // VectorMaskOp: 408
12903 0, // VectorMaskTrueCount: 409
12904 0, // VectorMaskFirstTrue: 410
12905 0, // VectorMaskLastTrue: 411
12906 0, // VectorMaskToLong: 412
12907 0, // VectorLongToMask: 413
12908 0, // Pack: 414
12909 0, // PackB: 415
12910 0, // PackS: 416
12911 0, // PackI: 417
12912 0, // PackL: 418
12913 0, // PackF: 419
12914 0, // PackD: 420
12915 0, // Pack2L: 421
12916 0, // Pack2D: 422
12917 0, // ReplicateB: 423
12918 0, // ReplicateS: 424
12919 0, // ReplicateI: 425
12920 0, // ReplicateL: 426
12921 0, // ReplicateF: 427
12922 0, // ReplicateD: 428
12923 0, // Extract: 429
12924 0, // ExtractB: 430
12925 0, // ExtractUB: 431
12926 0, // ExtractC: 432
12927 0, // ExtractS: 433
12928 0, // ExtractI: 434
12929 0, // ExtractL: 435
12930 0, // ExtractF: 436
12931 0, // ExtractD: 437
12932 0, // Digit: 438
12933 0, // LowerCase: 439
12934 0, // UpperCase: 440
12935 0, // Whitespace: 441
12936 0, // VectorBox: 442
12937 0, // VectorBoxAllocate: 443
12938 0, // VectorUnbox: 444
12939 0, // VectorMaskWrapper: 445
12940 0, // VectorMaskCmp: 446
12941 0, // VectorMaskCast: 447
12942 0, // VectorTest: 448
12943 0, // VectorBlend: 449
12944 0, // VectorRearrange: 450
12945 0, // VectorLoadMask: 451
12946 0, // VectorLoadShuffle: 452
12947 0, // VectorLoadConst: 453
12948 0, // VectorStoreMask: 454
12949 0, // VectorReinterpret: 455
12950 0, // VectorCast: 456
12951 0, // VectorCastB2X: 457
12952 0, // VectorCastS2X: 458
12953 0, // VectorCastI2X: 459
12954 0, // VectorCastL2X: 460
12955 0, // VectorCastF2X: 461
12956 0, // VectorCastD2X: 462
12957 0, // VectorInsert: 463
12958 0, // MaskAll: 464
12959 0, // AndVMask: 465
12960 0, // OrVMask: 466
12961 0 // no trailing comma // XorVMask: 467
12962};
12963// The following instructions can cisc-spill
12964// MoveVL2F can cisc-spill operand 1 to loadF
12965// MoveLEG2F can cisc-spill operand 1 to loadF
12966// MoveVL2D can cisc-spill operand 1 to loadSSD
12967// MoveLEG2D can cisc-spill operand 1 to loadSSD
12968// popCountI can cisc-spill operand 1 to popCountI_mem
12969// popCountL can cisc-spill operand 1 to popCountL_mem
12970// cmovI_reg can cisc-spill operand 4 to cmovI_mem
12971// cmovI_regU can cisc-spill operand 4 to cmovI_memU
12972// cmovI_regUCF can cisc-spill operand 4 to cmovI_memUCF
12973// cmovL_reg can cisc-spill operand 4 to cmovL_mem
12974// cmovL_regU can cisc-spill operand 4 to cmovL_memU
12975// cmovL_regUCF can cisc-spill operand 4 to cmovL_memUCF
12976// addI_rReg can cisc-spill operand 2 to addI_rReg_mem
12977// addL_rReg can cisc-spill operand 2 to addL_rReg_mem
12978// subI_rReg can cisc-spill operand 2 to subI_rReg_mem
12979// subL_rReg can cisc-spill operand 2 to subL_rReg_mem
12980// mulI_rReg can cisc-spill operand 2 to mulI_mem
12981// mulI_rReg_imm can cisc-spill operand 1 to mulI_mem_imm
12982// mulL_rReg can cisc-spill operand 2 to mulL_mem
12983// mulL_rReg_imm can cisc-spill operand 1 to mulL_mem_imm
12984// i2b can cisc-spill operand 1 to loadI2B
12985// i2s can cisc-spill operand 1 to loadI2S
12986// andI_rReg can cisc-spill operand 2 to andI_rReg_mem
12987// andI2L_rReg_imm255 can cisc-spill operand 1 to loadI2L_immI_255
12988// andI2L_rReg_imm65535 can cisc-spill operand 1 to loadI2L_immI_65535
12989// andnI_rReg_rReg_rReg can cisc-spill operand 3 to andnI_rReg_rReg_mem
12990// andnI_rReg_rReg_rReg_0 can cisc-spill operand 1 to andnI_rReg_rReg_mem_0
12991// orI_rReg can cisc-spill operand 2 to orI_rReg_mem
12992// xorI_rReg can cisc-spill operand 2 to xorI_rReg_mem
12993// andL_rReg can cisc-spill operand 2 to andL_rReg_mem
12994// andnL_rReg_rReg_rReg can cisc-spill operand 3 to andnL_rReg_rReg_mem
12995// andnL_rReg_rReg_rReg_0 can cisc-spill operand 1 to andnL_rReg_rReg_mem_0
12996// orL_rReg can cisc-spill operand 2 to orL_rReg_mem
12997// xorL_rReg can cisc-spill operand 2 to xorL_rReg_mem
12998// cmpF_cc_reg can cisc-spill operand 2 to cmpF_cc_mem
12999// cmpF_cc_reg_CF can cisc-spill operand 2 to cmpF_cc_memCF
13000// cmpD_cc_reg can cisc-spill operand 2 to cmpD_cc_mem
13001// cmpD_cc_reg_CF can cisc-spill operand 2 to cmpD_cc_memCF
13002// cmpF_reg can cisc-spill operand 2 to cmpF_mem
13003// cmpD_reg can cisc-spill operand 2 to cmpD_mem
13004// convF2D_reg_reg can cisc-spill operand 1 to convF2D_reg_mem
13005// convD2F_reg_reg can cisc-spill operand 1 to convD2F_reg_mem
13006// convL2F_reg_reg can cisc-spill operand 1 to convL2F_reg_mem
13007// convL2D_reg_reg can cisc-spill operand 1 to convL2D_reg_mem
13008// convI2L_reg_reg can cisc-spill operand 1 to loadI2L
13009// convI2L_reg_reg_zex can cisc-spill operand 1 to loadUI2L
13010// MoveF2I_reg_reg can cisc-spill operand 1 to MoveF2I_stack_reg
13011// MoveD2L_reg_reg can cisc-spill operand 1 to MoveD2L_stack_reg
13012// MoveI2F_reg_reg can cisc-spill operand 1 to MoveI2F_stack_reg
13013// compI_rReg can cisc-spill operand 2 to compI_rReg_mem
13014// compU_rReg can cisc-spill operand 2 to compU_rReg_mem
13015// compL_rReg can cisc-spill operand 2 to compL_rReg_mem
13016// compUL_rReg can cisc-spill operand 2 to compUL_rReg_mem
13017// addF_reg can cisc-spill operand 2 to addF_mem
13018// addF_reg_reg can cisc-spill operand 2 to addF_reg_mem
13019// addD_reg can cisc-spill operand 2 to addD_mem
13020// addD_reg_reg can cisc-spill operand 2 to addD_reg_mem
13021// subF_reg can cisc-spill operand 2 to subF_mem
13022// subF_reg_reg can cisc-spill operand 2 to subF_reg_mem
13023// subD_reg can cisc-spill operand 2 to subD_mem
13024// subD_reg_reg can cisc-spill operand 2 to subD_reg_mem
13025// mulF_reg can cisc-spill operand 2 to mulF_mem
13026// mulF_reg_reg can cisc-spill operand 2 to mulF_reg_mem
13027// mulD_reg can cisc-spill operand 2 to mulD_mem
13028// mulD_reg_reg can cisc-spill operand 2 to mulD_reg_mem
13029// divF_reg can cisc-spill operand 2 to divF_mem
13030// divF_reg_reg can cisc-spill operand 2 to divF_reg_mem
13031// divD_reg can cisc-spill operand 2 to divD_mem
13032// divD_reg_reg can cisc-spill operand 2 to divD_reg_mem
13033// roundD_reg can cisc-spill operand 1 to roundD_mem
13034// ReplI_reg can cisc-spill operand 1 to ReplI_mem
13035// ReplL_reg can cisc-spill operand 1 to ReplL_mem
13036// ReplF_reg can cisc-spill operand 1 to ReplF_mem
13037// ReplD_reg can cisc-spill operand 1 to ReplD_mem
13038
13039
13040
13041// An array of character pointers to machine register names.
13042const char *Matcher::regName[REG_COUNT559] = {
13043 "R10",
13044 "R10_H",
13045 "R11",
13046 "R11_H",
13047 "R8",
13048 "R8_H",
13049 "R9",
13050 "R9_H",
13051 "R12",
13052 "R12_H",
13053 "RCX",
13054 "RCX_H",
13055 "RBX",
13056 "RBX_H",
13057 "RDI",
13058 "RDI_H",
13059 "RDX",
13060 "RDX_H",
13061 "RSI",
13062 "RSI_H",
13063 "RAX",
13064 "RAX_H",
13065 "RBP",
13066 "RBP_H",
13067 "R13",
13068 "R13_H",
13069 "R14",
13070 "R14_H",
13071 "R15",
13072 "R15_H",
13073 "RSP",
13074 "RSP_H",
13075 "XMM0",
13076 "XMM0b",
13077 "XMM0c",
13078 "XMM0d",
13079 "XMM0e",
13080 "XMM0f",
13081 "XMM0g",
13082 "XMM0h",
13083 "XMM0i",
13084 "XMM0j",
13085 "XMM0k",
13086 "XMM0l",
13087 "XMM0m",
13088 "XMM0n",
13089 "XMM0o",
13090 "XMM0p",
13091 "XMM1",
13092 "XMM1b",
13093 "XMM1c",
13094 "XMM1d",
13095 "XMM1e",
13096 "XMM1f",
13097 "XMM1g",
13098 "XMM1h",
13099 "XMM1i",
13100 "XMM1j",
13101 "XMM1k",
13102 "XMM1l",
13103 "XMM1m",
13104 "XMM1n",
13105 "XMM1o",
13106 "XMM1p",
13107 "XMM2",
13108 "XMM2b",
13109 "XMM2c",
13110 "XMM2d",
13111 "XMM2e",
13112 "XMM2f",
13113 "XMM2g",
13114 "XMM2h",
13115 "XMM2i",
13116 "XMM2j",
13117 "XMM2k",
13118 "XMM2l",
13119 "XMM2m",
13120 "XMM2n",
13121 "XMM2o",
13122 "XMM2p",
13123 "XMM3",
13124 "XMM3b",
13125 "XMM3c",
13126 "XMM3d",
13127 "XMM3e",
13128 "XMM3f",
13129 "XMM3g",
13130 "XMM3h",
13131 "XMM3i",
13132 "XMM3j",
13133 "XMM3k",
13134 "XMM3l",
13135 "XMM3m",
13136 "XMM3n",
13137 "XMM3o",
13138 "XMM3p",
13139 "XMM4",
13140 "XMM4b",
13141 "XMM4c",
13142 "XMM4d",
13143 "XMM4e",
13144 "XMM4f",
13145 "XMM4g",
13146 "XMM4h",
13147 "XMM4i",
13148 "XMM4j",
13149 "XMM4k",
13150 "XMM4l",
13151 "XMM4m",
13152 "XMM4n",
13153 "XMM4o",
13154 "XMM4p",
13155 "XMM5",
13156 "XMM5b",
13157 "XMM5c",
13158 "XMM5d",
13159 "XMM5e",
13160 "XMM5f",
13161 "XMM5g",
13162 "XMM5h",
13163 "XMM5i",
13164 "XMM5j",
13165 "XMM5k",
13166 "XMM5l",
13167 "XMM5m",
13168 "XMM5n",
13169 "XMM5o",
13170 "XMM5p",
13171 "XMM6",
13172 "XMM6b",
13173 "XMM6c",
13174 "XMM6d",
13175 "XMM6e",
13176 "XMM6f",
13177 "XMM6g",
13178 "XMM6h",
13179 "XMM6i",
13180 "XMM6j",
13181 "XMM6k",
13182 "XMM6l",
13183 "XMM6m",
13184 "XMM6n",
13185 "XMM6o",
13186 "XMM6p",
13187 "XMM7",
13188 "XMM7b",
13189 "XMM7c",
13190 "XMM7d",
13191 "XMM7e",
13192 "XMM7f",
13193 "XMM7g",
13194 "XMM7h",
13195 "XMM7i",
13196 "XMM7j",
13197 "XMM7k",
13198 "XMM7l",
13199 "XMM7m",
13200 "XMM7n",
13201 "XMM7o",
13202 "XMM7p",
13203 "XMM8",
13204 "XMM8b",
13205 "XMM8c",
13206 "XMM8d",
13207 "XMM8e",
13208 "XMM8f",
13209 "XMM8g",
13210 "XMM8h",
13211 "XMM8i",
13212 "XMM8j",
13213 "XMM8k",
13214 "XMM8l",
13215 "XMM8m",
13216 "XMM8n",
13217 "XMM8o",
13218 "XMM8p",
13219 "XMM9",
13220 "XMM9b",
13221 "XMM9c",
13222 "XMM9d",
13223 "XMM9e",
13224 "XMM9f",
13225 "XMM9g",
13226 "XMM9h",
13227 "XMM9i",
13228 "XMM9j",
13229 "XMM9k",
13230 "XMM9l",
13231 "XMM9m",
13232 "XMM9n",
13233 "XMM9o",
13234 "XMM9p",
13235 "XMM10",
13236 "XMM10b",
13237 "XMM10c",
13238 "XMM10d",
13239 "XMM10e",
13240 "XMM10f",
13241 "XMM10g",
13242 "XMM10h",
13243 "XMM10i",
13244 "XMM10j",
13245 "XMM10k",
13246 "XMM10l",
13247 "XMM10m",
13248 "XMM10n",
13249 "XMM10o",
13250 "XMM10p",
13251 "XMM11",
13252 "XMM11b",
13253 "XMM11c",
13254 "XMM11d",
13255 "XMM11e",
13256 "XMM11f",
13257 "XMM11g",
13258 "XMM11h",
13259 "XMM11i",
13260 "XMM11j",
13261 "XMM11k",
13262 "XMM11l",
13263 "XMM11m",
13264 "XMM11n",
13265 "XMM11o",
13266 "XMM11p",
13267 "XMM12",
13268 "XMM12b",
13269 "XMM12c",
13270 "XMM12d",
13271 "XMM12e",
13272 "XMM12f",
13273 "XMM12g",
13274 "XMM12h",
13275 "XMM12i",
13276 "XMM12j",
13277 "XMM12k",
13278 "XMM12l",
13279 "XMM12m",
13280 "XMM12n",
13281 "XMM12o",
13282 "XMM12p",
13283 "XMM13",
13284 "XMM13b",
13285 "XMM13c",
13286 "XMM13d",
13287 "XMM13e",
13288 "XMM13f",
13289 "XMM13g",
13290 "XMM13h",
13291 "XMM13i",
13292 "XMM13j",
13293 "XMM13k",
13294 "XMM13l",
13295 "XMM13m",
13296 "XMM13n",
13297 "XMM13o",
13298 "XMM13p",
13299 "XMM14",
13300 "XMM14b",
13301 "XMM14c",
13302 "XMM14d",
13303 "XMM14e",
13304 "XMM14f",
13305 "XMM14g",
13306 "XMM14h",
13307 "XMM14i",
13308 "XMM14j",
13309 "XMM14k",
13310 "XMM14l",
13311 "XMM14m",
13312 "XMM14n",
13313 "XMM14o",
13314 "XMM14p",
13315 "XMM15",
13316 "XMM15b",
13317 "XMM15c",
13318 "XMM15d",
13319 "XMM15e",
13320 "XMM15f",
13321 "XMM15g",
13322 "XMM15h",
13323 "XMM15i",
13324 "XMM15j",
13325 "XMM15k",
13326 "XMM15l",
13327 "XMM15m",
13328 "XMM15n",
13329 "XMM15o",
13330 "XMM15p",
13331 "XMM16",
13332 "XMM16b",
13333 "XMM16c",
13334 "XMM16d",
13335 "XMM16e",
13336 "XMM16f",
13337 "XMM16g",
13338 "XMM16h",
13339 "XMM16i",
13340 "XMM16j",
13341 "XMM16k",
13342 "XMM16l",
13343 "XMM16m",
13344 "XMM16n",
13345 "XMM16o",
13346 "XMM16p",
13347 "XMM17",
13348 "XMM17b",
13349 "XMM17c",
13350 "XMM17d",
13351 "XMM17e",
13352 "XMM17f",
13353 "XMM17g",
13354 "XMM17h",
13355 "XMM17i",
13356 "XMM17j",
13357 "XMM17k",
13358 "XMM17l",
13359 "XMM17m",
13360 "XMM17n",
13361 "XMM17o",
13362 "XMM17p",
13363 "XMM18",
13364 "XMM18b",
13365 "XMM18c",
13366 "XMM18d",
13367 "XMM18e",
13368 "XMM18f",
13369 "XMM18g",
13370 "XMM18h",
13371 "XMM18i",
13372 "XMM18j",
13373 "XMM18k",
13374 "XMM18l",
13375 "XMM18m",
13376 "XMM18n",
13377 "XMM18o",
13378 "XMM18p",
13379 "XMM19",
13380 "XMM19b",
13381 "XMM19c",
13382 "XMM19d",
13383 "XMM19e",
13384 "XMM19f",
13385 "XMM19g",
13386 "XMM19h",
13387 "XMM19i",
13388 "XMM19j",
13389 "XMM19k",
13390 "XMM19l",
13391 "XMM19m",
13392 "XMM19n",
13393 "XMM19o",
13394 "XMM19p",
13395 "XMM20",
13396 "XMM20b",
13397 "XMM20c",
13398 "XMM20d",
13399 "XMM20e",
13400 "XMM20f",
13401 "XMM20g",
13402 "XMM20h",
13403 "XMM20i",
13404 "XMM20j",
13405 "XMM20k",
13406 "XMM20l",
13407 "XMM20m",
13408 "XMM20n",
13409 "XMM20o",
13410 "XMM20p",
13411 "XMM21",
13412 "XMM21b",
13413 "XMM21c",
13414 "XMM21d",
13415 "XMM21e",
13416 "XMM21f",
13417 "XMM21g",
13418 "XMM21h",
13419 "XMM21i",
13420 "XMM21j",
13421 "XMM21k",
13422 "XMM21l",
13423 "XMM21m",
13424 "XMM21n",
13425 "XMM21o",
13426 "XMM21p",
13427 "XMM22",
13428 "XMM22b",
13429 "XMM22c",
13430 "XMM22d",
13431 "XMM22e",
13432 "XMM22f",
13433 "XMM22g",
13434 "XMM22h",
13435 "XMM22i",
13436 "XMM22j",
13437 "XMM22k",
13438 "XMM22l",
13439 "XMM22m",
13440 "XMM22n",
13441 "XMM22o",
13442 "XMM22p",
13443 "XMM23",
13444 "XMM23b",
13445 "XMM23c",
13446 "XMM23d",
13447 "XMM23e",
13448 "XMM23f",
13449 "XMM23g",
13450 "XMM23h",
13451 "XMM23i",
13452 "XMM23j",
13453 "XMM23k",
13454 "XMM23l",
13455 "XMM23m",
13456 "XMM23n",
13457 "XMM23o",
13458 "XMM23p",
13459 "XMM24",
13460 "XMM24b",
13461 "XMM24c",
13462 "XMM24d",
13463 "XMM24e",
13464 "XMM24f",
13465 "XMM24g",
13466 "XMM24h",
13467 "XMM24i",
13468 "XMM24j",
13469 "XMM24k",
13470 "XMM24l",
13471 "XMM24m",
13472 "XMM24n",
13473 "XMM24o",
13474 "XMM24p",
13475 "XMM25",
13476 "XMM25b",
13477 "XMM25c",
13478 "XMM25d",
13479 "XMM25e",
13480 "XMM25f",
13481 "XMM25g",
13482 "XMM25h",
13483 "XMM25i",
13484 "XMM25j",
13485 "XMM25k",
13486 "XMM25l",
13487 "XMM25m",
13488 "XMM25n",
13489 "XMM25o",
13490 "XMM25p",
13491 "XMM26",
13492 "XMM26b",
13493 "XMM26c",
13494 "XMM26d",
13495 "XMM26e",
13496 "XMM26f",
13497 "XMM26g",
13498 "XMM26h",
13499 "XMM26i",
13500 "XMM26j",
13501 "XMM26k",
13502 "XMM26l",
13503 "XMM26m",
13504 "XMM26n",
13505 "XMM26o",
13506 "XMM26p",
13507 "XMM27",
13508 "XMM27b",
13509 "XMM27c",
13510 "XMM27d",
13511 "XMM27e",
13512 "XMM27f",
13513 "XMM27g",
13514 "XMM27h",
13515 "XMM27i",
13516 "XMM27j",
13517 "XMM27k",
13518 "XMM27l",
13519 "XMM27m",
13520 "XMM27n",
13521 "XMM27o",
13522 "XMM27p",
13523 "XMM28",
13524 "XMM28b",
13525 "XMM28c",
13526 "XMM28d",
13527 "XMM28e",
13528 "XMM28f",
13529 "XMM28g",
13530 "XMM28h",
13531 "XMM28i",
13532 "XMM28j",
13533 "XMM28k",
13534 "XMM28l",
13535 "XMM28m",
13536 "XMM28n",
13537 "XMM28o",
13538 "XMM28p",
13539 "XMM29",
13540 "XMM29b",
13541 "XMM29c",
13542 "XMM29d",
13543 "XMM29e",
13544 "XMM29f",
13545 "XMM29g",
13546 "XMM29h",
13547 "XMM29i",
13548 "XMM29j",
13549 "XMM29k",
13550 "XMM29l",
13551 "XMM29m",
13552 "XMM29n",
13553 "XMM29o",
13554 "XMM29p",
13555 "XMM30",
13556 "XMM30b",
13557 "XMM30c",
13558 "XMM30d",
13559 "XMM30e",
13560 "XMM30f",
13561 "XMM30g",
13562 "XMM30h",
13563 "XMM30i",
13564 "XMM30j",
13565 "XMM30k",
13566 "XMM30l",
13567 "XMM30m",
13568 "XMM30n",
13569 "XMM30o",
13570 "XMM30p",
13571 "XMM31",
13572 "XMM31b",
13573 "XMM31c",
13574 "XMM31d",
13575 "XMM31e",
13576 "XMM31f",
13577 "XMM31g",
13578 "XMM31h",
13579 "XMM31i",
13580 "XMM31j",
13581 "XMM31k",
13582 "XMM31l",
13583 "XMM31m",
13584 "XMM31n",
13585 "XMM31o",
13586 "XMM31p",
13587 "K7",
13588 "K7_H",
13589 "K6",
13590 "K6_H",
13591 "K5",
13592 "K5_H",
13593 "K4",
13594 "K4_H",
13595 "K3",
13596 "K3_H",
13597 "K2",
13598 "K2_H",
13599 "K1",
13600 "K1_H",
13601 "RFLAGS" // no trailing comma
13602};
13603
13604// An array of character pointers to machine register names.
13605const VMReg OptoReg::opto2vm[REG_COUNT559] = {
13606 r10->as_VMReg(),
13607 r10->as_VMReg()->next(),
13608 r11->as_VMReg(),
13609 r11->as_VMReg()->next(),
13610 r8->as_VMReg(),
13611 r8->as_VMReg()->next(),
13612 r9->as_VMReg(),
13613 r9->as_VMReg()->next(),
13614 r12->as_VMReg(),
13615 r12->as_VMReg()->next(),
13616 rcx->as_VMReg(),
13617 rcx->as_VMReg()->next(),
13618 rbx->as_VMReg(),
13619 rbx->as_VMReg()->next(),
13620 rdi->as_VMReg(),
13621 rdi->as_VMReg()->next(),
13622 rdx->as_VMReg(),
13623 rdx->as_VMReg()->next(),
13624 rsi->as_VMReg(),
13625 rsi->as_VMReg()->next(),
13626 rax->as_VMReg(),
13627 rax->as_VMReg()->next(),
13628 rbp->as_VMReg(),
13629 rbp->as_VMReg()->next(),
13630 r13->as_VMReg(),
13631 r13->as_VMReg()->next(),
13632 r14->as_VMReg(),
13633 r14->as_VMReg()->next(),
13634 r15->as_VMReg(),
13635 r15->as_VMReg()->next(),
13636 rsp->as_VMReg(),
13637 rsp->as_VMReg()->next(),
13638 xmm0->as_VMReg(),
13639 xmm0->as_VMReg()->next(1),
13640 xmm0->as_VMReg()->next(2),
13641 xmm0->as_VMReg()->next(3),
13642 xmm0->as_VMReg()->next(4),
13643 xmm0->as_VMReg()->next(5),
13644 xmm0->as_VMReg()->next(6),
13645 xmm0->as_VMReg()->next(7),
13646 xmm0->as_VMReg()->next(8),
13647 xmm0->as_VMReg()->next(9),
13648 xmm0->as_VMReg()->next(10),
13649 xmm0->as_VMReg()->next(11),
13650 xmm0->as_VMReg()->next(12),
13651 xmm0->as_VMReg()->next(13),
13652 xmm0->as_VMReg()->next(14),
13653 xmm0->as_VMReg()->next(15),
13654 xmm1->as_VMReg(),
13655 xmm1->as_VMReg()->next(1),
13656 xmm1->as_VMReg()->next(2),
13657 xmm1->as_VMReg()->next(3),
13658 xmm1->as_VMReg()->next(4),
13659 xmm1->as_VMReg()->next(5),
13660 xmm1->as_VMReg()->next(6),
13661 xmm1->as_VMReg()->next(7),
13662 xmm1->as_VMReg()->next(8),
13663 xmm1->as_VMReg()->next(9),
13664 xmm1->as_VMReg()->next(10),
13665 xmm1->as_VMReg()->next(11),
13666 xmm1->as_VMReg()->next(12),
13667 xmm1->as_VMReg()->next(13),
13668 xmm1->as_VMReg()->next(14),
13669 xmm1->as_VMReg()->next(15),
13670 xmm2->as_VMReg(),
13671 xmm2->as_VMReg()->next(1),
13672 xmm2->as_VMReg()->next(2),
13673 xmm2->as_VMReg()->next(3),
13674 xmm2->as_VMReg()->next(4),
13675 xmm2->as_VMReg()->next(5),
13676 xmm2->as_VMReg()->next(6),
13677 xmm2->as_VMReg()->next(7),
13678 xmm2->as_VMReg()->next(8),
13679 xmm2->as_VMReg()->next(9),
13680 xmm2->as_VMReg()->next(10),
13681 xmm2->as_VMReg()->next(11),
13682 xmm2->as_VMReg()->next(12),
13683 xmm2->as_VMReg()->next(13),
13684 xmm2->as_VMReg()->next(14),
13685 xmm2->as_VMReg()->next(15),
13686 xmm3->as_VMReg(),
13687 xmm3->as_VMReg()->next(1),
13688 xmm3->as_VMReg()->next(2),
13689 xmm3->as_VMReg()->next(3),
13690 xmm3->as_VMReg()->next(4),
13691 xmm3->as_VMReg()->next(5),
13692 xmm3->as_VMReg()->next(6),
13693 xmm3->as_VMReg()->next(7),
13694 xmm3->as_VMReg()->next(8),
13695 xmm3->as_VMReg()->next(9),
13696 xmm3->as_VMReg()->next(10),
13697 xmm3->as_VMReg()->next(11),
13698 xmm3->as_VMReg()->next(12),
13699 xmm3->as_VMReg()->next(13),
13700 xmm3->as_VMReg()->next(14),
13701 xmm3->as_VMReg()->next(15),
13702 xmm4->as_VMReg(),
13703 xmm4->as_VMReg()->next(1),
13704 xmm4->as_VMReg()->next(2),
13705 xmm4->as_VMReg()->next(3),
13706 xmm4->as_VMReg()->next(4),
13707 xmm4->as_VMReg()->next(5),
13708 xmm4->as_VMReg()->next(6),
13709 xmm4->as_VMReg()->next(7),
13710 xmm4->as_VMReg()->next(8),
13711 xmm4->as_VMReg()->next(9),
13712 xmm4->as_VMReg()->next(10),
13713 xmm4->as_VMReg()->next(11),
13714 xmm4->as_VMReg()->next(12),
13715 xmm4->as_VMReg()->next(13),
13716 xmm4->as_VMReg()->next(14),
13717 xmm4->as_VMReg()->next(15),
13718 xmm5->as_VMReg(),
13719 xmm5->as_VMReg()->next(1),
13720 xmm5->as_VMReg()->next(2),
13721 xmm5->as_VMReg()->next(3),
13722 xmm5->as_VMReg()->next(4),
13723 xmm5->as_VMReg()->next(5),
13724 xmm5->as_VMReg()->next(6),
13725 xmm5->as_VMReg()->next(7),
13726 xmm5->as_VMReg()->next(8),
13727 xmm5->as_VMReg()->next(9),
13728 xmm5->as_VMReg()->next(10),
13729 xmm5->as_VMReg()->next(11),
13730 xmm5->as_VMReg()->next(12),
13731 xmm5->as_VMReg()->next(13),
13732 xmm5->as_VMReg()->next(14),
13733 xmm5->as_VMReg()->next(15),
13734 xmm6->as_VMReg(),
13735 xmm6->as_VMReg()->next(1),
13736 xmm6->as_VMReg()->next(2),
13737 xmm6->as_VMReg()->next(3),
13738 xmm6->as_VMReg()->next(4),
13739 xmm6->as_VMReg()->next(5),
13740 xmm6->as_VMReg()->next(6),
13741 xmm6->as_VMReg()->next(7),
13742 xmm6->as_VMReg()->next(8),
13743 xmm6->as_VMReg()->next(9),
13744 xmm6->as_VMReg()->next(10),
13745 xmm6->as_VMReg()->next(11),
13746 xmm6->as_VMReg()->next(12),
13747 xmm6->as_VMReg()->next(13),
13748 xmm6->as_VMReg()->next(14),
13749 xmm6->as_VMReg()->next(15),
13750 xmm7->as_VMReg(),
13751 xmm7->as_VMReg()->next(1),
13752 xmm7->as_VMReg()->next(2),
13753 xmm7->as_VMReg()->next(3),
13754 xmm7->as_VMReg()->next(4),
13755 xmm7->as_VMReg()->next(5),
13756 xmm7->as_VMReg()->next(6),
13757 xmm7->as_VMReg()->next(7),
13758 xmm7->as_VMReg()->next(8),
13759 xmm7->as_VMReg()->next(9),
13760 xmm7->as_VMReg()->next(10),
13761 xmm7->as_VMReg()->next(11),
13762 xmm7->as_VMReg()->next(12),
13763 xmm7->as_VMReg()->next(13),
13764 xmm7->as_VMReg()->next(14),
13765 xmm7->as_VMReg()->next(15),
13766 xmm8->as_VMReg(),
13767 xmm8->as_VMReg()->next(1),
13768 xmm8->as_VMReg()->next(2),
13769 xmm8->as_VMReg()->next(3),
13770 xmm8->as_VMReg()->next(4),
13771 xmm8->as_VMReg()->next(5),
13772 xmm8->as_VMReg()->next(6),
13773 xmm8->as_VMReg()->next(7),
13774 xmm8->as_VMReg()->next(8),
13775 xmm8->as_VMReg()->next(9),
13776 xmm8->as_VMReg()->next(10),
13777 xmm8->as_VMReg()->next(11),
13778 xmm8->as_VMReg()->next(12),
13779 xmm8->as_VMReg()->next(13),
13780 xmm8->as_VMReg()->next(14),
13781 xmm8->as_VMReg()->next(15),
13782 xmm9->as_VMReg(),
13783 xmm9->as_VMReg()->next(1),
13784 xmm9->as_VMReg()->next(2),
13785 xmm9->as_VMReg()->next(3),
13786 xmm9->as_VMReg()->next(4),
13787 xmm9->as_VMReg()->next(5),
13788 xmm9->as_VMReg()->next(6),
13789 xmm9->as_VMReg()->next(7),
13790 xmm9->as_VMReg()->next(8),
13791 xmm9->as_VMReg()->next(9),
13792 xmm9->as_VMReg()->next(10),
13793 xmm9->as_VMReg()->next(11),
13794 xmm9->as_VMReg()->next(12),
13795 xmm9->as_VMReg()->next(13),
13796 xmm9->as_VMReg()->next(14),
13797 xmm9->as_VMReg()->next(15),
13798 xmm10->as_VMReg(),
13799 xmm10->as_VMReg()->next(1),
13800 xmm10->as_VMReg()->next(2),
13801 xmm10->as_VMReg()->next(3),
13802 xmm10->as_VMReg()->next(4),
13803 xmm10->as_VMReg()->next(5),
13804 xmm10->as_VMReg()->next(6),
13805 xmm10->as_VMReg()->next(7),
13806 xmm10->as_VMReg()->next(8),
13807 xmm10->as_VMReg()->next(9),
13808 xmm10->as_VMReg()->next(10),
13809 xmm10->as_VMReg()->next(11),
13810 xmm10->as_VMReg()->next(12),
13811 xmm10->as_VMReg()->next(13),
13812 xmm10->as_VMReg()->next(14),
13813 xmm10->as_VMReg()->next(15),
13814 xmm11->as_VMReg(),
13815 xmm11->as_VMReg()->next(1),
13816 xmm11->as_VMReg()->next(2),
13817 xmm11->as_VMReg()->next(3),
13818 xmm11->as_VMReg()->next(4),
13819 xmm11->as_VMReg()->next(5),
13820 xmm11->as_VMReg()->next(6),
13821 xmm11->as_VMReg()->next(7),
13822 xmm11->as_VMReg()->next(8),
13823 xmm11->as_VMReg()->next(9),
13824 xmm11->as_VMReg()->next(10),
13825 xmm11->as_VMReg()->next(11),
13826 xmm11->as_VMReg()->next(12),
13827 xmm11->as_VMReg()->next(13),
13828 xmm11->as_VMReg()->next(14),
13829 xmm11->as_VMReg()->next(15),
13830 xmm12->as_VMReg(),
13831 xmm12->as_VMReg()->next(1),
13832 xmm12->as_VMReg()->next(2),
13833 xmm12->as_VMReg()->next(3),
13834 xmm12->as_VMReg()->next(4),
13835 xmm12->as_VMReg()->next(5),
13836 xmm12->as_VMReg()->next(6),
13837 xmm12->as_VMReg()->next(7),
13838 xmm12->as_VMReg()->next(8),
13839 xmm12->as_VMReg()->next(9),
13840 xmm12->as_VMReg()->next(10),
13841 xmm12->as_VMReg()->next(11),
13842 xmm12->as_VMReg()->next(12),
13843 xmm12->as_VMReg()->next(13),
13844 xmm12->as_VMReg()->next(14),
13845 xmm12->as_VMReg()->next(15),
13846 xmm13->as_VMReg(),
13847 xmm13->as_VMReg()->next(1),
13848 xmm13->as_VMReg()->next(2),
13849 xmm13->as_VMReg()->next(3),
13850 xmm13->as_VMReg()->next(4),
13851 xmm13->as_VMReg()->next(5),
13852 xmm13->as_VMReg()->next(6),
13853 xmm13->as_VMReg()->next(7),
13854 xmm13->as_VMReg()->next(8),
13855 xmm13->as_VMReg()->next(9),
13856 xmm13->as_VMReg()->next(10),
13857 xmm13->as_VMReg()->next(11),
13858 xmm13->as_VMReg()->next(12),
13859 xmm13->as_VMReg()->next(13),
13860 xmm13->as_VMReg()->next(14),
13861 xmm13->as_VMReg()->next(15),
13862 xmm14->as_VMReg(),
13863 xmm14->as_VMReg()->next(1),
13864 xmm14->as_VMReg()->next(2),
13865 xmm14->as_VMReg()->next(3),
13866 xmm14->as_VMReg()->next(4),
13867 xmm14->as_VMReg()->next(5),
13868 xmm14->as_VMReg()->next(6),
13869 xmm14->as_VMReg()->next(7),
13870 xmm14->as_VMReg()->next(8),
13871 xmm14->as_VMReg()->next(9),
13872 xmm14->as_VMReg()->next(10),
13873 xmm14->as_VMReg()->next(11),
13874 xmm14->as_VMReg()->next(12),
13875 xmm14->as_VMReg()->next(13),
13876 xmm14->as_VMReg()->next(14),
13877 xmm14->as_VMReg()->next(15),
13878 xmm15->as_VMReg(),
13879 xmm15->as_VMReg()->next(1),
13880 xmm15->as_VMReg()->next(2),
13881 xmm15->as_VMReg()->next(3),
13882 xmm15->as_VMReg()->next(4),
13883 xmm15->as_VMReg()->next(5),
13884 xmm15->as_VMReg()->next(6),
13885 xmm15->as_VMReg()->next(7),
13886 xmm15->as_VMReg()->next(8),
13887 xmm15->as_VMReg()->next(9),
13888 xmm15->as_VMReg()->next(10),
13889 xmm15->as_VMReg()->next(11),
13890 xmm15->as_VMReg()->next(12),
13891 xmm15->as_VMReg()->next(13),
13892 xmm15->as_VMReg()->next(14),
13893 xmm15->as_VMReg()->next(15),
13894 xmm16->as_VMReg(),
13895 xmm16->as_VMReg()->next(1),
13896 xmm16->as_VMReg()->next(2),
13897 xmm16->as_VMReg()->next(3),
13898 xmm16->as_VMReg()->next(4),
13899 xmm16->as_VMReg()->next(5),
13900 xmm16->as_VMReg()->next(6),
13901 xmm16->as_VMReg()->next(7),
13902 xmm16->as_VMReg()->next(8),
13903 xmm16->as_VMReg()->next(9),
13904 xmm16->as_VMReg()->next(10),
13905 xmm16->as_VMReg()->next(11),
13906 xmm16->as_VMReg()->next(12),
13907 xmm16->as_VMReg()->next(13),
13908 xmm16->as_VMReg()->next(14),
13909 xmm16->as_VMReg()->next(15),
13910 xmm17->as_VMReg(),
13911 xmm17->as_VMReg()->next(1),
13912 xmm17->as_VMReg()->next(2),
13913 xmm17->as_VMReg()->next(3),
13914 xmm17->as_VMReg()->next(4),
13915 xmm17->as_VMReg()->next(5),
13916 xmm17->as_VMReg()->next(6),
13917 xmm17->as_VMReg()->next(7),
13918 xmm17->as_VMReg()->next(8),
13919 xmm17->as_VMReg()->next(9),
13920 xmm17->as_VMReg()->next(10),
13921 xmm17->as_VMReg()->next(11),
13922 xmm17->as_VMReg()->next(12),
13923 xmm17->as_VMReg()->next(13),
13924 xmm17->as_VMReg()->next(14),
13925 xmm17->as_VMReg()->next(15),
13926 xmm18->as_VMReg(),
13927 xmm18->as_VMReg()->next(1),
13928 xmm18->as_VMReg()->next(2),
13929 xmm18->as_VMReg()->next(3),
13930 xmm18->as_VMReg()->next(4),
13931 xmm18->as_VMReg()->next(5),
13932 xmm18->as_VMReg()->next(6),
13933 xmm18->as_VMReg()->next(7),
13934 xmm18->as_VMReg()->next(8),
13935 xmm18->as_VMReg()->next(9),
13936 xmm18->as_VMReg()->next(10),
13937 xmm18->as_VMReg()->next(11),
13938 xmm18->as_VMReg()->next(12),
13939 xmm18->as_VMReg()->next(13),
13940 xmm18->as_VMReg()->next(14),
13941 xmm18->as_VMReg()->next(15),
13942 xmm19->as_VMReg(),
13943 xmm19->as_VMReg()->next(1),
13944 xmm19->as_VMReg()->next(2),
13945 xmm19->as_VMReg()->next(3),
13946 xmm19->as_VMReg()->next(4),
13947 xmm19->as_VMReg()->next(5),
13948 xmm19->as_VMReg()->next(6),
13949 xmm19->as_VMReg()->next(7),
13950 xmm19->as_VMReg()->next(8),
13951 xmm19->as_VMReg()->next(9),
13952 xmm19->as_VMReg()->next(10),
13953 xmm19->as_VMReg()->next(11),
13954 xmm19->as_VMReg()->next(12),
13955 xmm19->as_VMReg()->next(13),
13956 xmm19->as_VMReg()->next(14),
13957 xmm19->as_VMReg()->next(15),
13958 xmm20->as_VMReg(),
13959 xmm20->as_VMReg()->next(1),
13960 xmm20->as_VMReg()->next(2),
13961 xmm20->as_VMReg()->next(3),
13962 xmm20->as_VMReg()->next(4),
13963 xmm20->as_VMReg()->next(5),
13964 xmm20->as_VMReg()->next(6),
13965 xmm20->as_VMReg()->next(7),
13966 xmm20->as_VMReg()->next(8),
13967 xmm20->as_VMReg()->next(9),
13968 xmm20->as_VMReg()->next(10),
13969 xmm20->as_VMReg()->next(11),
13970 xmm20->as_VMReg()->next(12),
13971 xmm20->as_VMReg()->next(13),
13972 xmm20->as_VMReg()->next(14),
13973 xmm20->as_VMReg()->next(15),
13974 xmm21->as_VMReg(),
13975 xmm21->as_VMReg()->next(1),
13976 xmm21->as_VMReg()->next(2),
13977 xmm21->as_VMReg()->next(3),
13978 xmm21->as_VMReg()->next(4),
13979 xmm21->as_VMReg()->next(5),
13980 xmm21->as_VMReg()->next(6),
13981 xmm21->as_VMReg()->next(7),
13982 xmm21->as_VMReg()->next(8),
13983 xmm21->as_VMReg()->next(9),
13984 xmm21->as_VMReg()->next(10),
13985 xmm21->as_VMReg()->next(11),
13986 xmm21->as_VMReg()->next(12),
13987 xmm21->as_VMReg()->next(13),
13988 xmm21->as_VMReg()->next(14),
13989 xmm21->as_VMReg()->next(15),
13990 xmm22->as_VMReg(),
13991 xmm22->as_VMReg()->next(1),
13992 xmm22->as_VMReg()->next(2),
13993 xmm22->as_VMReg()->next(3),
13994 xmm22->as_VMReg()->next(4),
13995 xmm22->as_VMReg()->next(5),
13996 xmm22->as_VMReg()->next(6),
13997 xmm22->as_VMReg()->next(7),
13998 xmm22->as_VMReg()->next(8),
13999 xmm22->as_VMReg()->next(9),
14000 xmm22->as_VMReg()->next(10),
14001 xmm22->as_VMReg()->next(11),
14002 xmm22->as_VMReg()->next(12),
14003 xmm22->as_VMReg()->next(13),
14004 xmm22->as_VMReg()->next(14),
14005 xmm22->as_VMReg()->next(15),
14006 xmm23->as_VMReg(),
14007 xmm23->as_VMReg()->next(1),
14008 xmm23->as_VMReg()->next(2),
14009 xmm23->as_VMReg()->next(3),
14010 xmm23->as_VMReg()->next(4),
14011 xmm23->as_VMReg()->next(5),
14012 xmm23->as_VMReg()->next(6),
14013 xmm23->as_VMReg()->next(7),
14014 xmm23->as_VMReg()->next(8),
14015 xmm23->as_VMReg()->next(9),
14016 xmm23->as_VMReg()->next(10),
14017 xmm23->as_VMReg()->next(11),
14018 xmm23->as_VMReg()->next(12),
14019 xmm23->as_VMReg()->next(13),
14020 xmm23->as_VMReg()->next(14),
14021 xmm23->as_VMReg()->next(15),
14022 xmm24->as_VMReg(),
14023 xmm24->as_VMReg()->next(1),
14024 xmm24->as_VMReg()->next(2),
14025 xmm24->as_VMReg()->next(3),
14026 xmm24->as_VMReg()->next(4),
14027 xmm24->as_VMReg()->next(5),
14028 xmm24->as_VMReg()->next(6),
14029 xmm24->as_VMReg()->next(7),
14030 xmm24->as_VMReg()->next(8),
14031 xmm24->as_VMReg()->next(9),
14032 xmm24->as_VMReg()->next(10),
14033 xmm24->as_VMReg()->next(11),
14034 xmm24->as_VMReg()->next(12),
14035 xmm24->as_VMReg()->next(13),
14036 xmm24->as_VMReg()->next(14),
14037 xmm24->as_VMReg()->next(15),
14038 xmm25->as_VMReg(),
14039 xmm25->as_VMReg()->next(1),
14040 xmm25->as_VMReg()->next(2),
14041 xmm25->as_VMReg()->next(3),
14042 xmm25->as_VMReg()->next(4),
14043 xmm25->as_VMReg()->next(5),
14044 xmm25->as_VMReg()->next(6),
14045 xmm25->as_VMReg()->next(7),
14046 xmm25->as_VMReg()->next(8),
14047 xmm25->as_VMReg()->next(9),
14048 xmm25->as_VMReg()->next(10),
14049 xmm25->as_VMReg()->next(11),
14050 xmm25->as_VMReg()->next(12),
14051 xmm25->as_VMReg()->next(13),
14052 xmm25->as_VMReg()->next(14),
14053 xmm25->as_VMReg()->next(15),
14054 xmm26->as_VMReg(),
14055 xmm26->as_VMReg()->next(1),
14056 xmm26->as_VMReg()->next(2),
14057 xmm26->as_VMReg()->next(3),
14058 xmm26->as_VMReg()->next(4),
14059 xmm26->as_VMReg()->next(5),
14060 xmm26->as_VMReg()->next(6),
14061 xmm26->as_VMReg()->next(7),
14062 xmm26->as_VMReg()->next(8),
14063 xmm26->as_VMReg()->next(9),
14064 xmm26->as_VMReg()->next(10),
14065 xmm26->as_VMReg()->next(11),
14066 xmm26->as_VMReg()->next(12),
14067 xmm26->as_VMReg()->next(13),
14068 xmm26->as_VMReg()->next(14),
14069 xmm26->as_VMReg()->next(15),
14070 xmm27->as_VMReg(),
14071 xmm27->as_VMReg()->next(1),
14072 xmm27->as_VMReg()->next(2),
14073 xmm27->as_VMReg()->next(3),
14074 xmm27->as_VMReg()->next(4),
14075 xmm27->as_VMReg()->next(5),
14076 xmm27->as_VMReg()->next(6),
14077 xmm27->as_VMReg()->next(7),
14078 xmm27->as_VMReg()->next(8),
14079 xmm27->as_VMReg()->next(9),
14080 xmm27->as_VMReg()->next(10),
14081 xmm27->as_VMReg()->next(11),
14082 xmm27->as_VMReg()->next(12),
14083 xmm27->as_VMReg()->next(13),
14084 xmm27->as_VMReg()->next(14),
14085 xmm27->as_VMReg()->next(15),
14086 xmm28->as_VMReg(),
14087 xmm28->as_VMReg()->next(1),
14088 xmm28->as_VMReg()->next(2),
14089 xmm28->as_VMReg()->next(3),
14090 xmm28->as_VMReg()->next(4),
14091 xmm28->as_VMReg()->next(5),
14092 xmm28->as_VMReg()->next(6),
14093 xmm28->as_VMReg()->next(7),
14094 xmm28->as_VMReg()->next(8),
14095 xmm28->as_VMReg()->next(9),
14096 xmm28->as_VMReg()->next(10),
14097 xmm28->as_VMReg()->next(11),
14098 xmm28->as_VMReg()->next(12),
14099 xmm28->as_VMReg()->next(13),
14100 xmm28->as_VMReg()->next(14),
14101 xmm28->as_VMReg()->next(15),
14102 xmm29->as_VMReg(),
14103 xmm29->as_VMReg()->next(1),
14104 xmm29->as_VMReg()->next(2),
14105 xmm29->as_VMReg()->next(3),
14106 xmm29->as_VMReg()->next(4),
14107 xmm29->as_VMReg()->next(5),
14108 xmm29->as_VMReg()->next(6),
14109 xmm29->as_VMReg()->next(7),
14110 xmm29->as_VMReg()->next(8),
14111 xmm29->as_VMReg()->next(9),
14112 xmm29->as_VMReg()->next(10),
14113 xmm29->as_VMReg()->next(11),
14114 xmm29->as_VMReg()->next(12),
14115 xmm29->as_VMReg()->next(13),
14116 xmm29->as_VMReg()->next(14),
14117 xmm29->as_VMReg()->next(15),
14118 xmm30->as_VMReg(),
14119 xmm30->as_VMReg()->next(1),
14120 xmm30->as_VMReg()->next(2),
14121 xmm30->as_VMReg()->next(3),
14122 xmm30->as_VMReg()->next(4),
14123 xmm30->as_VMReg()->next(5),
14124 xmm30->as_VMReg()->next(6),
14125 xmm30->as_VMReg()->next(7),
14126 xmm30->as_VMReg()->next(8),
14127 xmm30->as_VMReg()->next(9),
14128 xmm30->as_VMReg()->next(10),
14129 xmm30->as_VMReg()->next(11),
14130 xmm30->as_VMReg()->next(12),
14131 xmm30->as_VMReg()->next(13),
14132 xmm30->as_VMReg()->next(14),
14133 xmm30->as_VMReg()->next(15),
14134 xmm31->as_VMReg(),
14135 xmm31->as_VMReg()->next(1),
14136 xmm31->as_VMReg()->next(2),
14137 xmm31->as_VMReg()->next(3),
14138 xmm31->as_VMReg()->next(4),
14139 xmm31->as_VMReg()->next(5),
14140 xmm31->as_VMReg()->next(6),
14141 xmm31->as_VMReg()->next(7),
14142 xmm31->as_VMReg()->next(8),
14143 xmm31->as_VMReg()->next(9),
14144 xmm31->as_VMReg()->next(10),
14145 xmm31->as_VMReg()->next(11),
14146 xmm31->as_VMReg()->next(12),
14147 xmm31->as_VMReg()->next(13),
14148 xmm31->as_VMReg()->next(14),
14149 xmm31->as_VMReg()->next(15),
14150 k7->as_VMReg(),
14151 k7->as_VMReg()->next(),
14152 k6->as_VMReg(),
14153 k6->as_VMReg()->next(),
14154 k5->as_VMReg(),
14155 k5->as_VMReg()->next(),
14156 k4->as_VMReg(),
14157 k4->as_VMReg()->next(),
14158 k3->as_VMReg(),
14159 k3->as_VMReg()->next(),
14160 k2->as_VMReg(),
14161 k2->as_VMReg()->next(),
14162 k1->as_VMReg(),
14163 k1->as_VMReg()->next(),
14164 VMRegImpl::Bad() // no trailing comma
14165 };
14166
14167 OptoReg::Name OptoReg::vm2opto[ConcreteRegisterImpl::number_of_registers];
14168
14169// An array of the machine register encode values
14170const unsigned char Matcher::_regEncode[REG_COUNT559] = {
14171 (unsigned char)'\xA', // R10
14172 (unsigned char)'\xA', // R10_H
14173 (unsigned char)'\xB', // R11
14174 (unsigned char)'\xB', // R11_H
14175 (unsigned char)'\x8', // R8
14176 (unsigned char)'\x8', // R8_H
14177 (unsigned char)'\x9', // R9
14178 (unsigned char)'\x9', // R9_H
14179 (unsigned char)'\xC', // R12
14180 (unsigned char)'\xC', // R12_H
14181 (unsigned char)'\x1', // RCX
14182 (unsigned char)'\x1', // RCX_H
14183 (unsigned char)'\x3', // RBX
14184 (unsigned char)'\x3', // RBX_H
14185 (unsigned char)'\x7', // RDI
14186 (unsigned char)'\x7', // RDI_H
14187 (unsigned char)'\x2', // RDX
14188 (unsigned char)'\x2', // RDX_H
14189 (unsigned char)'\x6', // RSI
14190 (unsigned char)'\x6', // RSI_H
14191 (unsigned char)'\x0', // RAX
14192 (unsigned char)'\x0', // RAX_H
14193 (unsigned char)'\x5', // RBP
14194 (unsigned char)'\x5', // RBP_H
14195 (unsigned char)'\xD', // R13
14196 (unsigned char)'\xD', // R13_H
14197 (unsigned char)'\xE', // R14
14198 (unsigned char)'\xE', // R14_H
14199 (unsigned char)'\xF', // R15
14200 (unsigned char)'\xF', // R15_H
14201 (unsigned char)'\x4', // RSP
14202 (unsigned char)'\x4', // RSP_H
14203 (unsigned char)'\x0', // XMM0
14204 (unsigned char)'\x0', // XMM0b
14205 (unsigned char)'\x0', // XMM0c
14206 (unsigned char)'\x0', // XMM0d
14207 (unsigned char)'\x0', // XMM0e
14208 (unsigned char)'\x0', // XMM0f
14209 (unsigned char)'\x0', // XMM0g
14210 (unsigned char)'\x0', // XMM0h
14211 (unsigned char)'\x0', // XMM0i
14212 (unsigned char)'\x0', // XMM0j
14213 (unsigned char)'\x0', // XMM0k
14214 (unsigned char)'\x0', // XMM0l
14215 (unsigned char)'\x0', // XMM0m
14216 (unsigned char)'\x0', // XMM0n
14217 (unsigned char)'\x0', // XMM0o
14218 (unsigned char)'\x0', // XMM0p
14219 (unsigned char)'\x1', // XMM1
14220 (unsigned char)'\x1', // XMM1b
14221 (unsigned char)'\x1', // XMM1c
14222 (unsigned char)'\x1', // XMM1d
14223 (unsigned char)'\x1', // XMM1e
14224 (unsigned char)'\x1', // XMM1f
14225 (unsigned char)'\x1', // XMM1g
14226 (unsigned char)'\x1', // XMM1h
14227 (unsigned char)'\x1', // XMM1i
14228 (unsigned char)'\x1', // XMM1j
14229 (unsigned char)'\x1', // XMM1k
14230 (unsigned char)'\x1', // XMM1l
14231 (unsigned char)'\x1', // XMM1m
14232 (unsigned char)'\x1', // XMM1n
14233 (unsigned char)'\x1', // XMM1o
14234 (unsigned char)'\x1', // XMM1p
14235 (unsigned char)'\x2', // XMM2
14236 (unsigned char)'\x2', // XMM2b
14237 (unsigned char)'\x2', // XMM2c
14238 (unsigned char)'\x2', // XMM2d
14239 (unsigned char)'\x2', // XMM2e
14240 (unsigned char)'\x2', // XMM2f
14241 (unsigned char)'\x2', // XMM2g
14242 (unsigned char)'\x2', // XMM2h
14243 (unsigned char)'\x2', // XMM2i
14244 (unsigned char)'\x2', // XMM2j
14245 (unsigned char)'\x2', // XMM2k
14246 (unsigned char)'\x2', // XMM2l
14247 (unsigned char)'\x2', // XMM2m
14248 (unsigned char)'\x2', // XMM2n
14249 (unsigned char)'\x2', // XMM2o
14250 (unsigned char)'\x2', // XMM2p
14251 (unsigned char)'\x3', // XMM3
14252 (unsigned char)'\x3', // XMM3b
14253 (unsigned char)'\x3', // XMM3c
14254 (unsigned char)'\x3', // XMM3d
14255 (unsigned char)'\x3', // XMM3e
14256 (unsigned char)'\x3', // XMM3f
14257 (unsigned char)'\x3', // XMM3g
14258 (unsigned char)'\x3', // XMM3h
14259 (unsigned char)'\x3', // XMM3i
14260 (unsigned char)'\x3', // XMM3j
14261 (unsigned char)'\x3', // XMM3k
14262 (unsigned char)'\x3', // XMM3l
14263 (unsigned char)'\x3', // XMM3m
14264 (unsigned char)'\x3', // XMM3n
14265 (unsigned char)'\x3', // XMM3o
14266 (unsigned char)'\x3', // XMM3p
14267 (unsigned char)'\x4', // XMM4
14268 (unsigned char)'\x4', // XMM4b
14269 (unsigned char)'\x4', // XMM4c
14270 (unsigned char)'\x4', // XMM4d
14271 (unsigned char)'\x4', // XMM4e
14272 (unsigned char)'\x4', // XMM4f
14273 (unsigned char)'\x4', // XMM4g
14274 (unsigned char)'\x4', // XMM4h
14275 (unsigned char)'\x4', // XMM4i
14276 (unsigned char)'\x4', // XMM4j
14277 (unsigned char)'\x4', // XMM4k
14278 (unsigned char)'\x4', // XMM4l
14279 (unsigned char)'\x4', // XMM4m
14280 (unsigned char)'\x4', // XMM4n
14281 (unsigned char)'\x4', // XMM4o
14282 (unsigned char)'\x4', // XMM4p
14283 (unsigned char)'\x5', // XMM5
14284 (unsigned char)'\x5', // XMM5b
14285 (unsigned char)'\x5', // XMM5c
14286 (unsigned char)'\x5', // XMM5d
14287 (unsigned char)'\x5', // XMM5e
14288 (unsigned char)'\x5', // XMM5f
14289 (unsigned char)'\x5', // XMM5g
14290 (unsigned char)'\x5', // XMM5h
14291 (unsigned char)'\x5', // XMM5i
14292 (unsigned char)'\x5', // XMM5j
14293 (unsigned char)'\x5', // XMM5k
14294 (unsigned char)'\x5', // XMM5l
14295 (unsigned char)'\x5', // XMM5m
14296 (unsigned char)'\x5', // XMM5n
14297 (unsigned char)'\x5', // XMM5o
14298 (unsigned char)'\x5', // XMM5p
14299 (unsigned char)'\x6', // XMM6
14300 (unsigned char)'\x6', // XMM6b
14301 (unsigned char)'\x6', // XMM6c
14302 (unsigned char)'\x6', // XMM6d
14303 (unsigned char)'\x6', // XMM6e
14304 (unsigned char)'\x6', // XMM6f
14305 (unsigned char)'\x6', // XMM6g
14306 (unsigned char)'\x6', // XMM6h
14307 (unsigned char)'\x6', // XMM6i
14308 (unsigned char)'\x6', // XMM6j
14309 (unsigned char)'\x6', // XMM6k
14310 (unsigned char)'\x6', // XMM6l
14311 (unsigned char)'\x6', // XMM6m
14312 (unsigned char)'\x6', // XMM6n
14313 (unsigned char)'\x6', // XMM6o
14314 (unsigned char)'\x6', // XMM6p
14315 (unsigned char)'\x7', // XMM7
14316 (unsigned char)'\x7', // XMM7b
14317 (unsigned char)'\x7', // XMM7c
14318 (unsigned char)'\x7', // XMM7d
14319 (unsigned char)'\x7', // XMM7e
14320 (unsigned char)'\x7', // XMM7f
14321 (unsigned char)'\x7', // XMM7g
14322 (unsigned char)'\x7', // XMM7h
14323 (unsigned char)'\x7', // XMM7i
14324 (unsigned char)'\x7', // XMM7j
14325 (unsigned char)'\x7', // XMM7k
14326 (unsigned char)'\x7', // XMM7l
14327 (unsigned char)'\x7', // XMM7m
14328 (unsigned char)'\x7', // XMM7n
14329 (unsigned char)'\x7', // XMM7o
14330 (unsigned char)'\x7', // XMM7p
14331 (unsigned char)'\x8', // XMM8
14332 (unsigned char)'\x8', // XMM8b
14333 (unsigned char)'\x8', // XMM8c
14334 (unsigned char)'\x8', // XMM8d
14335 (unsigned char)'\x8', // XMM8e
14336 (unsigned char)'\x8', // XMM8f
14337 (unsigned char)'\x8', // XMM8g
14338 (unsigned char)'\x8', // XMM8h
14339 (unsigned char)'\x8', // XMM8i
14340 (unsigned char)'\x8', // XMM8j
14341 (unsigned char)'\x8', // XMM8k
14342 (unsigned char)'\x8', // XMM8l
14343 (unsigned char)'\x8', // XMM8m
14344 (unsigned char)'\x8', // XMM8n
14345 (unsigned char)'\x8', // XMM8o
14346 (unsigned char)'\x8', // XMM8p
14347 (unsigned char)'\x9', // XMM9
14348 (unsigned char)'\x9', // XMM9b
14349 (unsigned char)'\x9', // XMM9c
14350 (unsigned char)'\x9', // XMM9d
14351 (unsigned char)'\x9', // XMM9e
14352 (unsigned char)'\x9', // XMM9f
14353 (unsigned char)'\x9', // XMM9g
14354 (unsigned char)'\x9', // XMM9h
14355 (unsigned char)'\x9', // XMM9i
14356 (unsigned char)'\x9', // XMM9j
14357 (unsigned char)'\x9', // XMM9k
14358 (unsigned char)'\x9', // XMM9l
14359 (unsigned char)'\x9', // XMM9m
14360 (unsigned char)'\x9', // XMM9n
14361 (unsigned char)'\x9', // XMM9o
14362 (unsigned char)'\x9', // XMM9p
14363 (unsigned char)'\xA', // XMM10
14364 (unsigned char)'\xA', // XMM10b
14365 (unsigned char)'\xA', // XMM10c
14366 (unsigned char)'\xA', // XMM10d
14367 (unsigned char)'\xA', // XMM10e
14368 (unsigned char)'\xA', // XMM10f
14369 (unsigned char)'\xA', // XMM10g
14370 (unsigned char)'\xA', // XMM10h
14371 (unsigned char)'\xA', // XMM10i
14372 (unsigned char)'\xA', // XMM10j
14373 (unsigned char)'\xA', // XMM10k
14374 (unsigned char)'\xA', // XMM10l
14375 (unsigned char)'\xA', // XMM10m
14376 (unsigned char)'\xA', // XMM10n
14377 (unsigned char)'\xA', // XMM10o
14378 (unsigned char)'\xA', // XMM10p
14379 (unsigned char)'\xB', // XMM11
14380 (unsigned char)'\xB', // XMM11b
14381 (unsigned char)'\xB', // XMM11c
14382 (unsigned char)'\xB', // XMM11d
14383 (unsigned char)'\xB', // XMM11e
14384 (unsigned char)'\xB', // XMM11f
14385 (unsigned char)'\xB', // XMM11g
14386 (unsigned char)'\xB', // XMM11h
14387 (unsigned char)'\xB', // XMM11i
14388 (unsigned char)'\xB', // XMM11j
14389 (unsigned char)'\xB', // XMM11k
14390 (unsigned char)'\xB', // XMM11l
14391 (unsigned char)'\xB', // XMM11m
14392 (unsigned char)'\xB', // XMM11n
14393 (unsigned char)'\xB', // XMM11o
14394 (unsigned char)'\xB', // XMM11p
14395 (unsigned char)'\xC', // XMM12
14396 (unsigned char)'\xC', // XMM12b
14397 (unsigned char)'\xC', // XMM12c
14398 (unsigned char)'\xC', // XMM12d
14399 (unsigned char)'\xC', // XMM12e
14400 (unsigned char)'\xC', // XMM12f
14401 (unsigned char)'\xC', // XMM12g
14402 (unsigned char)'\xC', // XMM12h
14403 (unsigned char)'\xC', // XMM12i
14404 (unsigned char)'\xC', // XMM12j
14405 (unsigned char)'\xC', // XMM12k
14406 (unsigned char)'\xC', // XMM12l
14407 (unsigned char)'\xC', // XMM12m
14408 (unsigned char)'\xC', // XMM12n
14409 (unsigned char)'\xC', // XMM12o
14410 (unsigned char)'\xC', // XMM12p
14411 (unsigned char)'\xD', // XMM13
14412 (unsigned char)'\xD', // XMM13b
14413 (unsigned char)'\xD', // XMM13c
14414 (unsigned char)'\xD', // XMM13d
14415 (unsigned char)'\xD', // XMM13e
14416 (unsigned char)'\xD', // XMM13f
14417 (unsigned char)'\xD', // XMM13g
14418 (unsigned char)'\xD', // XMM13h
14419 (unsigned char)'\xD', // XMM13i
14420 (unsigned char)'\xD', // XMM13j
14421 (unsigned char)'\xD', // XMM13k
14422 (unsigned char)'\xD', // XMM13l
14423 (unsigned char)'\xD', // XMM13m
14424 (unsigned char)'\xD', // XMM13n
14425 (unsigned char)'\xD', // XMM13o
14426 (unsigned char)'\xD', // XMM13p
14427 (unsigned char)'\xE', // XMM14
14428 (unsigned char)'\xE', // XMM14b
14429 (unsigned char)'\xE', // XMM14c
14430 (unsigned char)'\xE', // XMM14d
14431 (unsigned char)'\xE', // XMM14e
14432 (unsigned char)'\xE', // XMM14f
14433 (unsigned char)'\xE', // XMM14g
14434 (unsigned char)'\xE', // XMM14h
14435 (unsigned char)'\xE', // XMM14i
14436 (unsigned char)'\xE', // XMM14j
14437 (unsigned char)'\xE', // XMM14k
14438 (unsigned char)'\xE', // XMM14l
14439 (unsigned char)'\xE', // XMM14m
14440 (unsigned char)'\xE', // XMM14n
14441 (unsigned char)'\xE', // XMM14o
14442 (unsigned char)'\xE', // XMM14p
14443 (unsigned char)'\xF', // XMM15
14444 (unsigned char)'\xF', // XMM15b
14445 (unsigned char)'\xF', // XMM15c
14446 (unsigned char)'\xF', // XMM15d
14447 (unsigned char)'\xF', // XMM15e
14448 (unsigned char)'\xF', // XMM15f
14449 (unsigned char)'\xF', // XMM15g
14450 (unsigned char)'\xF', // XMM15h
14451 (unsigned char)'\xF', // XMM15i
14452 (unsigned char)'\xF', // XMM15j
14453 (unsigned char)'\xF', // XMM15k
14454 (unsigned char)'\xF', // XMM15l
14455 (unsigned char)'\xF', // XMM15m
14456 (unsigned char)'\xF', // XMM15n
14457 (unsigned char)'\xF', // XMM15o
14458 (unsigned char)'\xF', // XMM15p
14459 (unsigned char)'\x10', // XMM16
14460 (unsigned char)'\x10', // XMM16b
14461 (unsigned char)'\x10', // XMM16c
14462 (unsigned char)'\x10', // XMM16d
14463 (unsigned char)'\x10', // XMM16e
14464 (unsigned char)'\x10', // XMM16f
14465 (unsigned char)'\x10', // XMM16g
14466 (unsigned char)'\x10', // XMM16h
14467 (unsigned char)'\x10', // XMM16i
14468 (unsigned char)'\x10', // XMM16j
14469 (unsigned char)'\x10', // XMM16k
14470 (unsigned char)'\x10', // XMM16l
14471 (unsigned char)'\x10', // XMM16m
14472 (unsigned char)'\x10', // XMM16n
14473 (unsigned char)'\x10', // XMM16o
14474 (unsigned char)'\x10', // XMM16p
14475 (unsigned char)'\x11', // XMM17
14476 (unsigned char)'\x11', // XMM17b
14477 (unsigned char)'\x11', // XMM17c
14478 (unsigned char)'\x11', // XMM17d
14479 (unsigned char)'\x11', // XMM17e
14480 (unsigned char)'\x11', // XMM17f
14481 (unsigned char)'\x11', // XMM17g
14482 (unsigned char)'\x11', // XMM17h
14483 (unsigned char)'\x11', // XMM17i
14484 (unsigned char)'\x11', // XMM17j
14485 (unsigned char)'\x11', // XMM17k
14486 (unsigned char)'\x11', // XMM17l
14487 (unsigned char)'\x11', // XMM17m
14488 (unsigned char)'\x11', // XMM17n
14489 (unsigned char)'\x11', // XMM17o
14490 (unsigned char)'\x11', // XMM17p
14491 (unsigned char)'\x12', // XMM18
14492 (unsigned char)'\x12', // XMM18b
14493 (unsigned char)'\x12', // XMM18c
14494 (unsigned char)'\x12', // XMM18d
14495 (unsigned char)'\x12', // XMM18e
14496 (unsigned char)'\x12', // XMM18f
14497 (unsigned char)'\x12', // XMM18g
14498 (unsigned char)'\x12', // XMM18h
14499 (unsigned char)'\x12', // XMM18i
14500 (unsigned char)'\x12', // XMM18j
14501 (unsigned char)'\x12', // XMM18k
14502 (unsigned char)'\x12', // XMM18l
14503 (unsigned char)'\x12', // XMM18m
14504 (unsigned char)'\x12', // XMM18n
14505 (unsigned char)'\x12', // XMM18o
14506 (unsigned char)'\x12', // XMM18p
14507 (unsigned char)'\x13', // XMM19
14508 (unsigned char)'\x13', // XMM19b
14509 (unsigned char)'\x13', // XMM19c
14510 (unsigned char)'\x13', // XMM19d
14511 (unsigned char)'\x13', // XMM19e
14512 (unsigned char)'\x13', // XMM19f
14513 (unsigned char)'\x13', // XMM19g
14514 (unsigned char)'\x13', // XMM19h
14515 (unsigned char)'\x13', // XMM19i
14516 (unsigned char)'\x13', // XMM19j
14517 (unsigned char)'\x13', // XMM19k
14518 (unsigned char)'\x13', // XMM19l
14519 (unsigned char)'\x13', // XMM19m
14520 (unsigned char)'\x13', // XMM19n
14521 (unsigned char)'\x13', // XMM19o
14522 (unsigned char)'\x13', // XMM19p
14523 (unsigned char)'\x14', // XMM20
14524 (unsigned char)'\x14', // XMM20b
14525 (unsigned char)'\x14', // XMM20c
14526 (unsigned char)'\x14', // XMM20d
14527 (unsigned char)'\x14', // XMM20e
14528 (unsigned char)'\x14', // XMM20f
14529 (unsigned char)'\x14', // XMM20g
14530 (unsigned char)'\x14', // XMM20h
14531 (unsigned char)'\x14', // XMM20i
14532 (unsigned char)'\x14', // XMM20j
14533 (unsigned char)'\x14', // XMM20k
14534 (unsigned char)'\x14', // XMM20l
14535 (unsigned char)'\x14', // XMM20m
14536 (unsigned char)'\x14', // XMM20n
14537 (unsigned char)'\x14', // XMM20o
14538 (unsigned char)'\x14', // XMM20p
14539 (unsigned char)'\x15', // XMM21
14540 (unsigned char)'\x15', // XMM21b
14541 (unsigned char)'\x15', // XMM21c
14542 (unsigned char)'\x15', // XMM21d
14543 (unsigned char)'\x15', // XMM21e
14544 (unsigned char)'\x15', // XMM21f
14545 (unsigned char)'\x15', // XMM21g
14546 (unsigned char)'\x15', // XMM21h
14547 (unsigned char)'\x15', // XMM21i
14548 (unsigned char)'\x15', // XMM21j
14549 (unsigned char)'\x15', // XMM21k
14550 (unsigned char)'\x15', // XMM21l
14551 (unsigned char)'\x15', // XMM21m
14552 (unsigned char)'\x15', // XMM21n
14553 (unsigned char)'\x15', // XMM21o
14554 (unsigned char)'\x15', // XMM21p
14555 (unsigned char)'\x16', // XMM22
14556 (unsigned char)'\x16', // XMM22b
14557 (unsigned char)'\x16', // XMM22c
14558 (unsigned char)'\x16', // XMM22d
14559 (unsigned char)'\x16', // XMM22e
14560 (unsigned char)'\x16', // XMM22f
14561 (unsigned char)'\x16', // XMM22g
14562 (unsigned char)'\x16', // XMM22h
14563 (unsigned char)'\x16', // XMM22i
14564 (unsigned char)'\x16', // XMM22j
14565 (unsigned char)'\x16', // XMM22k
14566 (unsigned char)'\x16', // XMM22l
14567 (unsigned char)'\x16', // XMM22m
14568 (unsigned char)'\x16', // XMM22n
14569 (unsigned char)'\x16', // XMM22o
14570 (unsigned char)'\x16', // XMM22p
14571 (unsigned char)'\x17', // XMM23
14572 (unsigned char)'\x17', // XMM23b
14573 (unsigned char)'\x17', // XMM23c
14574 (unsigned char)'\x17', // XMM23d
14575 (unsigned char)'\x17', // XMM23e
14576 (unsigned char)'\x17', // XMM23f
14577 (unsigned char)'\x17', // XMM23g
14578 (unsigned char)'\x17', // XMM23h
14579 (unsigned char)'\x17', // XMM23i
14580 (unsigned char)'\x17', // XMM23j
14581 (unsigned char)'\x17', // XMM23k
14582 (unsigned char)'\x17', // XMM23l
14583 (unsigned char)'\x17', // XMM23m
14584 (unsigned char)'\x17', // XMM23n
14585 (unsigned char)'\x17', // XMM23o
14586 (unsigned char)'\x17', // XMM23p
14587 (unsigned char)'\x18', // XMM24
14588 (unsigned char)'\x18', // XMM24b
14589 (unsigned char)'\x18', // XMM24c
14590 (unsigned char)'\x18', // XMM24d
14591 (unsigned char)'\x18', // XMM24e
14592 (unsigned char)'\x18', // XMM24f
14593 (unsigned char)'\x18', // XMM24g
14594 (unsigned char)'\x18', // XMM24h
14595 (unsigned char)'\x18', // XMM24i
14596 (unsigned char)'\x18', // XMM24j
14597 (unsigned char)'\x18', // XMM24k
14598 (unsigned char)'\x18', // XMM24l
14599 (unsigned char)'\x18', // XMM24m
14600 (unsigned char)'\x18', // XMM24n
14601 (unsigned char)'\x18', // XMM24o
14602 (unsigned char)'\x18', // XMM24p
14603 (unsigned char)'\x19', // XMM25
14604 (unsigned char)'\x19', // XMM25b
14605 (unsigned char)'\x19', // XMM25c
14606 (unsigned char)'\x19', // XMM25d
14607 (unsigned char)'\x19', // XMM25e
14608 (unsigned char)'\x19', // XMM25f
14609 (unsigned char)'\x19', // XMM25g
14610 (unsigned char)'\x19', // XMM25h
14611 (unsigned char)'\x19', // XMM25i
14612 (unsigned char)'\x19', // XMM25j
14613 (unsigned char)'\x19', // XMM25k
14614 (unsigned char)'\x19', // XMM25l
14615 (unsigned char)'\x19', // XMM25m
14616 (unsigned char)'\x19', // XMM25n
14617 (unsigned char)'\x19', // XMM25o
14618 (unsigned char)'\x19', // XMM25p
14619 (unsigned char)'\x1A', // XMM26
14620 (unsigned char)'\x1A', // XMM26b
14621 (unsigned char)'\x1A', // XMM26c
14622 (unsigned char)'\x1A', // XMM26d
14623 (unsigned char)'\x1A', // XMM26e
14624 (unsigned char)'\x1A', // XMM26f
14625 (unsigned char)'\x1A', // XMM26g
14626 (unsigned char)'\x1A', // XMM26h
14627 (unsigned char)'\x1A', // XMM26i
14628 (unsigned char)'\x1A', // XMM26j
14629 (unsigned char)'\x1A', // XMM26k
14630 (unsigned char)'\x1A', // XMM26l
14631 (unsigned char)'\x1A', // XMM26m
14632 (unsigned char)'\x1A', // XMM26n
14633 (unsigned char)'\x1A', // XMM26o
14634 (unsigned char)'\x1A', // XMM26p
14635 (unsigned char)'\x1B', // XMM27
14636 (unsigned char)'\x1B', // XMM27b
14637 (unsigned char)'\x1B', // XMM27c
14638 (unsigned char)'\x1B', // XMM27d
14639 (unsigned char)'\x1B', // XMM27e
14640 (unsigned char)'\x1B', // XMM27f
14641 (unsigned char)'\x1B', // XMM27g
14642 (unsigned char)'\x1B', // XMM27h
14643 (unsigned char)'\x1B', // XMM27i
14644 (unsigned char)'\x1B', // XMM27j
14645 (unsigned char)'\x1B', // XMM27k
14646 (unsigned char)'\x1B', // XMM27l
14647 (unsigned char)'\x1B', // XMM27m
14648 (unsigned char)'\x1B', // XMM27n
14649 (unsigned char)'\x1B', // XMM27o
14650 (unsigned char)'\x1B', // XMM27p
14651 (unsigned char)'\x1C', // XMM28
14652 (unsigned char)'\x1C', // XMM28b
14653 (unsigned char)'\x1C', // XMM28c
14654 (unsigned char)'\x1C', // XMM28d
14655 (unsigned char)'\x1C', // XMM28e
14656 (unsigned char)'\x1C', // XMM28f
14657 (unsigned char)'\x1C', // XMM28g
14658 (unsigned char)'\x1C', // XMM28h
14659 (unsigned char)'\x1C', // XMM28i
14660 (unsigned char)'\x1C', // XMM28j
14661 (unsigned char)'\x1C', // XMM28k
14662 (unsigned char)'\x1C', // XMM28l
14663 (unsigned char)'\x1C', // XMM28m
14664 (unsigned char)'\x1C', // XMM28n
14665 (unsigned char)'\x1C', // XMM28o
14666 (unsigned char)'\x1C', // XMM28p
14667 (unsigned char)'\x1D', // XMM29
14668 (unsigned char)'\x1D', // XMM29b
14669 (unsigned char)'\x1D', // XMM29c
14670 (unsigned char)'\x1D', // XMM29d
14671 (unsigned char)'\x1D', // XMM29e
14672 (unsigned char)'\x1D', // XMM29f
14673 (unsigned char)'\x1D', // XMM29g
14674 (unsigned char)'\x1D', // XMM29h
14675 (unsigned char)'\x1D', // XMM29i
14676 (unsigned char)'\x1D', // XMM29j
14677 (unsigned char)'\x1D', // XMM29k
14678 (unsigned char)'\x1D', // XMM29l
14679 (unsigned char)'\x1D', // XMM29m
14680 (unsigned char)'\x1D', // XMM29n
14681 (unsigned char)'\x1D', // XMM29o
14682 (unsigned char)'\x1D', // XMM29p
14683 (unsigned char)'\x1E', // XMM30
14684 (unsigned char)'\x1E', // XMM30b
14685 (unsigned char)'\x1E', // XMM30c
14686 (unsigned char)'\x1E', // XMM30d
14687 (unsigned char)'\x1E', // XMM30e
14688 (unsigned char)'\x1E', // XMM30f
14689 (unsigned char)'\x1E', // XMM30g
14690 (unsigned char)'\x1E', // XMM30h
14691 (unsigned char)'\x1E', // XMM30i
14692 (unsigned char)'\x1E', // XMM30j
14693 (unsigned char)'\x1E', // XMM30k
14694 (unsigned char)'\x1E', // XMM30l
14695 (unsigned char)'\x1E', // XMM30m
14696 (unsigned char)'\x1E', // XMM30n
14697 (unsigned char)'\x1E', // XMM30o
14698 (unsigned char)'\x1E', // XMM30p
14699 (unsigned char)'\x1F', // XMM31
14700 (unsigned char)'\x1F', // XMM31b
14701 (unsigned char)'\x1F', // XMM31c
14702 (unsigned char)'\x1F', // XMM31d
14703 (unsigned char)'\x1F', // XMM31e
14704 (unsigned char)'\x1F', // XMM31f
14705 (unsigned char)'\x1F', // XMM31g
14706 (unsigned char)'\x1F', // XMM31h
14707 (unsigned char)'\x1F', // XMM31i
14708 (unsigned char)'\x1F', // XMM31j
14709 (unsigned char)'\x1F', // XMM31k
14710 (unsigned char)'\x1F', // XMM31l
14711 (unsigned char)'\x1F', // XMM31m
14712 (unsigned char)'\x1F', // XMM31n
14713 (unsigned char)'\x1F', // XMM31o
14714 (unsigned char)'\x1F', // XMM31p
14715 (unsigned char)'\x7', // K7
14716 (unsigned char)'\x7', // K7_H
14717 (unsigned char)'\x6', // K6
14718 (unsigned char)'\x6', // K6_H
14719 (unsigned char)'\x5', // K5
14720 (unsigned char)'\x5', // K5_H
14721 (unsigned char)'\x4', // K4
14722 (unsigned char)'\x4', // K4_H
14723 (unsigned char)'\x3', // K3
14724 (unsigned char)'\x3', // K3_H
14725 (unsigned char)'\x2', // K2
14726 (unsigned char)'\x2', // K2_H
14727 (unsigned char)'\x1', // K1
14728 (unsigned char)'\x1', // K1_H
14729 (unsigned char)'\x10' // no trailing comma // RFLAGS
14730};
14731
14732
14733//------------------Define classes derived from MachOper---------------------
14734MachOper *labelOper::clone() const {
14735 return new labelOper(_label, _block_num);
14736}
14737uint labelOper::opcode() const { return LABEL; }
14738
14739const RegMask *sRegIOper::in_RegMask(int index) const {
14740 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 14739, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
14741 return &(Compile::current()->FIRST_STACK_mask());
14742}
14743
14744const RegMask *sRegPOper::in_RegMask(int index) const {
14745 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 14744, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
14746 return &(Compile::current()->FIRST_STACK_mask());
14747}
14748
14749const RegMask *sRegFOper::in_RegMask(int index) const {
14750 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 14749, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
14751 return &(Compile::current()->FIRST_STACK_mask());
14752}
14753
14754const RegMask *sRegDOper::in_RegMask(int index) const {
14755 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 14754, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
14756 return &(Compile::current()->FIRST_STACK_mask());
14757}
14758
14759const RegMask *sRegLOper::in_RegMask(int index) const {
14760 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 14759, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
14761 return &(Compile::current()->FIRST_STACK_mask());
14762}
14763
14764MachOper *methodOper::clone() const {
14765 return new methodOper(_method);
14766}
14767uint methodOper::opcode() const { return METHOD; }
14768
14769const RegMask *kRegOper::in_RegMask(int index) const {
14770 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 14769, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
14771 return &VECTMASK_REG_mask();
14772}
14773
14774const RegMask *kReg_K1Oper::in_RegMask(int index) const {
14775 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 14774, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
14776 return &VECTMASK_REG_K1_mask();
14777}
14778
14779const RegMask *kReg_K2Oper::in_RegMask(int index) const {
14780 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 14779, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
14781 return &VECTMASK_REG_K2_mask();
14782}
14783
14784const RegMask *kReg_K3Oper::in_RegMask(int index) const {
14785 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 14784, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
14786 return &VECTMASK_REG_K3_mask();
14787}
14788
14789const RegMask *kReg_K4Oper::in_RegMask(int index) const {
14790 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 14789, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
14791 return &VECTMASK_REG_K4_mask();
14792}
14793
14794const RegMask *kReg_K5Oper::in_RegMask(int index) const {
14795 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 14794, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
14796 return &VECTMASK_REG_K5_mask();
14797}
14798
14799const RegMask *kReg_K6Oper::in_RegMask(int index) const {
14800 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 14799, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
14801 return &VECTMASK_REG_K6_mask();
14802}
14803
14804const RegMask *kReg_K7Oper::in_RegMask(int index) const {
14805 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 14804, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
14806 return &VECTMASK_REG_K7_mask();
14807}
14808
14809const RegMask *rRegIOper::in_RegMask(int index) const {
14810 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 14809, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
14811 return &INT_REG_mask();
14812}
14813
14814const RegMask *rax_RegIOper::in_RegMask(int index) const {
14815 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 14814, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
14816 return &INT_RAX_REG_mask();
14817}
14818
14819const RegMask *rbx_RegIOper::in_RegMask(int index) const {
14820 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 14819, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
14821 return &INT_RBX_REG_mask();
14822}
14823
14824const RegMask *rcx_RegIOper::in_RegMask(int index) const {
14825 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 14824, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
14826 return &INT_RCX_REG_mask();
14827}
14828
14829const RegMask *rdx_RegIOper::in_RegMask(int index) const {
14830 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 14829, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
14831 return &INT_RDX_REG_mask();
14832}
14833
14834const RegMask *rdi_RegIOper::in_RegMask(int index) const {
14835 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 14834, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
14836 return &INT_RDI_REG_mask();
14837}
14838
14839const RegMask *no_rax_rdx_RegIOper::in_RegMask(int index) const {
14840 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 14839, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
14841 return &INT_NO_RAX_RDX_REG_mask();
14842}
14843
14844const RegMask *any_RegPOper::in_RegMask(int index) const {
14845 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 14844, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
14846 return &ANY_REG_mask();
14847}
14848
14849const RegMask *rRegPOper::in_RegMask(int index) const {
14850 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 14849, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
14851 return &PTR_REG_mask();
14852}
14853
14854const RegMask *rRegNOper::in_RegMask(int index) const {
14855 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 14854, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
14856 return &INT_REG_mask();
14857}
14858
14859const RegMask *no_rax_RegPOper::in_RegMask(int index) const {
14860 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 14859, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
14861 return &PTR_NO_RAX_REG_mask();
14862}
14863
14864const RegMask *no_rbp_RegPOper::in_RegMask(int index) const {
14865 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 14864, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
14866 return &PTR_REG_NO_RBP_mask();
14867}
14868
14869const RegMask *no_rax_rbx_RegPOper::in_RegMask(int index) const {
14870 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 14869, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
14871 return &PTR_NO_RAX_RBX_REG_mask();
14872}
14873
14874const RegMask *rax_RegPOper::in_RegMask(int index) const {
14875 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 14874, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
14876 return &PTR_RAX_REG_mask();
14877}
14878
14879const RegMask *rax_RegNOper::in_RegMask(int index) const {
14880 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 14879, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
14881 return &INT_RAX_REG_mask();
14882}
14883
14884const RegMask *rbx_RegPOper::in_RegMask(int index) const {
14885 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 14884, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
14886 return &PTR_RBX_REG_mask();
14887}
14888
14889const RegMask *rsi_RegPOper::in_RegMask(int index) const {
14890 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 14889, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
14891 return &PTR_RSI_REG_mask();
14892}
14893
14894const RegMask *rbp_RegPOper::in_RegMask(int index) const {
14895 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 14894, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
14896 return &PTR_RBP_REG_mask();
14897}
14898
14899const RegMask *rdi_RegPOper::in_RegMask(int index) const {
14900 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 14899, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
14901 return &PTR_RDI_REG_mask();
14902}
14903
14904const RegMask *r15_RegPOper::in_RegMask(int index) const {
14905 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 14904, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
14906 return &PTR_R15_REG_mask();
14907}
14908
14909const RegMask *rRegLOper::in_RegMask(int index) const {
14910 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 14909, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
14911 return &LONG_REG_mask();
14912}
14913
14914const RegMask *no_rax_rdx_RegLOper::in_RegMask(int index) const {
14915 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 14914, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
14916 return &LONG_NO_RAX_RDX_REG_mask();
14917}
14918
14919const RegMask *no_rax_RegLOper::in_RegMask(int index) const {
14920 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 14919, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
14921 return &LONG_NO_RAX_RDX_REG_mask();
14922}
14923
14924const RegMask *rax_RegLOper::in_RegMask(int index) const {
14925 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 14924, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
14926 return &LONG_RAX_REG_mask();
14927}
14928
14929const RegMask *rcx_RegLOper::in_RegMask(int index) const {
14930 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 14929, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
14931 return &LONG_RCX_REG_mask();
14932}
14933
14934const RegMask *rdx_RegLOper::in_RegMask(int index) const {
14935 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 14934, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
14936 return &LONG_RDX_REG_mask();
14937}
14938
14939const RegMask *rFlagsRegOper::in_RegMask(int index) const {
14940 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 14939, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
14941 return &INT_FLAGS_mask();
14942}
14943
14944const RegMask *rFlagsRegUOper::in_RegMask(int index) const {
14945 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 14944, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
14946 return &INT_FLAGS_mask();
14947}
14948
14949const RegMask *rFlagsRegUCFOper::in_RegMask(int index) const {
14950 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 14949, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
14951 return &INT_FLAGS_mask();
14952}
14953
14954const RegMask *regFOper::in_RegMask(int index) const {
14955 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 14954, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
14956 return &FLOAT_REG_mask();
14957}
14958
14959const RegMask *legRegFOper::in_RegMask(int index) const {
14960 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 14959, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
14961 return &FLOAT_REG_LEGACY_mask();
14962}
14963
14964const RegMask *vlRegFOper::in_RegMask(int index) const {
14965 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 14964, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
14966 return &FLOAT_REG_VL_mask();
14967}
14968
14969const RegMask *regDOper::in_RegMask(int index) const {
14970 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 14969, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
14971 return &DOUBLE_REG_mask();
14972}
14973
14974const RegMask *legRegDOper::in_RegMask(int index) const {
14975 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 14974, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
14976 return &DOUBLE_REG_LEGACY_mask();
14977}
14978
14979const RegMask *vlRegDOper::in_RegMask(int index) const {
14980 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 14979, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
14981 return &DOUBLE_REG_VL_mask();
14982}
14983
14984const RegMask *indirectOper::in_RegMask(int index) const {
14985 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 14984, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
14986 return &PTR_REG_mask();
14987}
14988
14989const RegMask *indOffset8Oper::in_RegMask(int index) const {
14990 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 14989, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
14991 return &ANY_REG_mask();
14992}
14993
14994const RegMask *indOffset32Oper::in_RegMask(int index) const {
14995 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 14994, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
14996 return &ANY_REG_mask();
14997}
14998
14999const RegMask *indIndexOffsetOper::in_RegMask(int index) const {
15000 assert(0 <= index && index < 2, "index out of range")do { if (!(0 <= index && index < 2)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 14999, "assert(" "0 <= index && index < 2"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
15001 switch (index) {
15002 case 0: return &ANY_REG_mask();
15003 case 1: return &LONG_REG_mask();
15004 }
15005 ShouldNotReachHere()do { (*g_assert_poison) = 'X';; report_should_not_reach_here(
"ad_x86.cpp", 15004); ::breakpoint(); } while (0);
15006 return NULL__null;
15007}
15008
15009const RegMask *indIndexOper::in_RegMask(int index) const {
15010 assert(0 <= index && index < 2, "index out of range")do { if (!(0 <= index && index < 2)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 15009, "assert(" "0 <= index && index < 2"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
15011 switch (index) {
15012 case 0: return &ANY_REG_mask();
15013 case 1: return &LONG_REG_mask();
15014 }
15015 ShouldNotReachHere()do { (*g_assert_poison) = 'X';; report_should_not_reach_here(
"ad_x86.cpp", 15014); ::breakpoint(); } while (0);
15016 return NULL__null;
15017}
15018
15019const RegMask *indIndexScaleOper::in_RegMask(int index) const {
15020 assert(0 <= index && index < 2, "index out of range")do { if (!(0 <= index && index < 2)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 15019, "assert(" "0 <= index && index < 2"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
15021 switch (index) {
15022 case 0: return &ANY_REG_mask();
15023 case 1: return &LONG_REG_mask();
15024 }
15025 ShouldNotReachHere()do { (*g_assert_poison) = 'X';; report_should_not_reach_here(
"ad_x86.cpp", 15024); ::breakpoint(); } while (0);
15026 return NULL__null;
15027}
15028
15029const RegMask *indPosIndexScaleOper::in_RegMask(int index) const {
15030 assert(0 <= index && index < 2, "index out of range")do { if (!(0 <= index && index < 2)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 15029, "assert(" "0 <= index && index < 2"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
15031 switch (index) {
15032 case 0: return &ANY_REG_mask();
15033 case 1: return &INT_REG_mask();
15034 }
15035 ShouldNotReachHere()do { (*g_assert_poison) = 'X';; report_should_not_reach_here(
"ad_x86.cpp", 15034); ::breakpoint(); } while (0);
15036 return NULL__null;
15037}
15038
15039const RegMask *indIndexScaleOffsetOper::in_RegMask(int index) const {
15040 assert(0 <= index && index < 2, "index out of range")do { if (!(0 <= index && index < 2)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 15039, "assert(" "0 <= index && index < 2"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
15041 switch (index) {
15042 case 0: return &ANY_REG_mask();
15043 case 1: return &LONG_REG_mask();
15044 }
15045 ShouldNotReachHere()do { (*g_assert_poison) = 'X';; report_should_not_reach_here(
"ad_x86.cpp", 15044); ::breakpoint(); } while (0);
15046 return NULL__null;
15047}
15048
15049const RegMask *indPosIndexOffsetOper::in_RegMask(int index) const {
15050 assert(0 <= index && index < 2, "index out of range")do { if (!(0 <= index && index < 2)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 15049, "assert(" "0 <= index && index < 2"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
15051 switch (index) {
15052 case 0: return &ANY_REG_mask();
15053 case 1: return &INT_REG_mask();
15054 }
15055 ShouldNotReachHere()do { (*g_assert_poison) = 'X';; report_should_not_reach_here(
"ad_x86.cpp", 15054); ::breakpoint(); } while (0);
15056 return NULL__null;
15057}
15058
15059const RegMask *indPosIndexScaleOffsetOper::in_RegMask(int index) const {
15060 assert(0 <= index && index < 2, "index out of range")do { if (!(0 <= index && index < 2)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 15059, "assert(" "0 <= index && index < 2"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
15061 switch (index) {
15062 case 0: return &ANY_REG_mask();
15063 case 1: return &INT_REG_mask();
15064 }
15065 ShouldNotReachHere()do { (*g_assert_poison) = 'X';; report_should_not_reach_here(
"ad_x86.cpp", 15064); ::breakpoint(); } while (0);
15066 return NULL__null;
15067}
15068
15069const RegMask *indCompressedOopOffsetOper::in_RegMask(int index) const {
15070 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 15069, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
15071 return &INT_REG_mask();
15072}
15073
15074const RegMask *indirectNarrowOper::in_RegMask(int index) const {
15075 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 15074, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
15076 return &INT_REG_mask();
15077}
15078
15079const RegMask *indOffset8NarrowOper::in_RegMask(int index) const {
15080 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 15079, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
15081 return &INT_REG_mask();
15082}
15083
15084const RegMask *indOffset32NarrowOper::in_RegMask(int index) const {
15085 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 15084, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
15086 return &INT_REG_mask();
15087}
15088
15089const RegMask *indIndexOffsetNarrowOper::in_RegMask(int index) const {
15090 assert(0 <= index && index < 2, "index out of range")do { if (!(0 <= index && index < 2)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 15089, "assert(" "0 <= index && index < 2"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
15091 switch (index) {
15092 case 0: return &INT_REG_mask();
15093 case 1: return &LONG_REG_mask();
15094 }
15095 ShouldNotReachHere()do { (*g_assert_poison) = 'X';; report_should_not_reach_here(
"ad_x86.cpp", 15094); ::breakpoint(); } while (0);
15096 return NULL__null;
15097}
15098
15099const RegMask *indIndexNarrowOper::in_RegMask(int index) const {
15100 assert(0 <= index && index < 2, "index out of range")do { if (!(0 <= index && index < 2)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 15099, "assert(" "0 <= index && index < 2"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
15101 switch (index) {
15102 case 0: return &INT_REG_mask();
15103 case 1: return &LONG_REG_mask();
15104 }
15105 ShouldNotReachHere()do { (*g_assert_poison) = 'X';; report_should_not_reach_here(
"ad_x86.cpp", 15104); ::breakpoint(); } while (0);
15106 return NULL__null;
15107}
15108
15109const RegMask *indIndexScaleNarrowOper::in_RegMask(int index) const {
15110 assert(0 <= index && index < 2, "index out of range")do { if (!(0 <= index && index < 2)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 15109, "assert(" "0 <= index && index < 2"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
15111 switch (index) {
15112 case 0: return &INT_REG_mask();
15113 case 1: return &LONG_REG_mask();
15114 }
15115 ShouldNotReachHere()do { (*g_assert_poison) = 'X';; report_should_not_reach_here(
"ad_x86.cpp", 15114); ::breakpoint(); } while (0);
15116 return NULL__null;
15117}
15118
15119const RegMask *indIndexScaleOffsetNarrowOper::in_RegMask(int index) const {
15120 assert(0 <= index && index < 2, "index out of range")do { if (!(0 <= index && index < 2)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 15119, "assert(" "0 <= index && index < 2"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
15121 switch (index) {
15122 case 0: return &INT_REG_mask();
15123 case 1: return &LONG_REG_mask();
15124 }
15125 ShouldNotReachHere()do { (*g_assert_poison) = 'X';; report_should_not_reach_here(
"ad_x86.cpp", 15124); ::breakpoint(); } while (0);
15126 return NULL__null;
15127}
15128
15129const RegMask *indPosIndexOffsetNarrowOper::in_RegMask(int index) const {
15130 assert(0 <= index && index < 2, "index out of range")do { if (!(0 <= index && index < 2)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 15129, "assert(" "0 <= index && index < 2"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
15131 return &INT_REG_mask();
15132}
15133
15134const RegMask *indPosIndexScaleOffsetNarrowOper::in_RegMask(int index) const {
15135 assert(0 <= index && index < 2, "index out of range")do { if (!(0 <= index && index < 2)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 15134, "assert(" "0 <= index && index < 2"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
15136 return &INT_REG_mask();
15137}
15138
15139const RegMask *stackSlotPOper::in_RegMask(int index) const {
15140 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 15139, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
15141 return &(Compile::current()->FIRST_STACK_mask());
15142}
15143
15144const RegMask *stackSlotIOper::in_RegMask(int index) const {
15145 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 15144, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
15146 return &(Compile::current()->FIRST_STACK_mask());
15147}
15148
15149const RegMask *stackSlotFOper::in_RegMask(int index) const {
15150 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 15149, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
15151 return &(Compile::current()->FIRST_STACK_mask());
15152}
15153
15154const RegMask *stackSlotDOper::in_RegMask(int index) const {
15155 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 15154, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
15156 return &(Compile::current()->FIRST_STACK_mask());
15157}
15158
15159const RegMask *stackSlotLOper::in_RegMask(int index) const {
15160 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 15159, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
15161 return &(Compile::current()->FIRST_STACK_mask());
15162}
15163
15164const RegMask *rxmm0Oper::in_RegMask(int index) const {
15165 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 15164, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
15166 return &XMM0_REG_mask();
15167}
15168
15169const RegMask *vecOper::in_RegMask(int index) const {
15170 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 15169, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
15171 return &RegMask::Empty;
15172}
15173
15174const RegMask *legVecOper::in_RegMask(int index) const {
15175 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 15174, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
15176 return &RegMask::Empty;
15177}
15178
15179const RegMask *vecSOper::in_RegMask(int index) const {
15180 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 15179, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
15181 return &VECTORS_REG_VLBWDQ_mask();
15182}
15183
15184const RegMask *legVecSOper::in_RegMask(int index) const {
15185 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 15184, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
15186 return &VECTORS_REG_LEGACY_mask();
15187}
15188
15189const RegMask *vecDOper::in_RegMask(int index) const {
15190 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 15189, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
15191 return &VECTORD_REG_VLBWDQ_mask();
15192}
15193
15194const RegMask *legVecDOper::in_RegMask(int index) const {
15195 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 15194, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
15196 return &VECTORD_REG_LEGACY_mask();
15197}
15198
15199const RegMask *vecXOper::in_RegMask(int index) const {
15200 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 15199, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
15201 return &VECTORX_REG_VLBWDQ_mask();
15202}
15203
15204const RegMask *legVecXOper::in_RegMask(int index) const {
15205 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 15204, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
15206 return &VECTORX_REG_LEGACY_mask();
15207}
15208
15209const RegMask *vecYOper::in_RegMask(int index) const {
15210 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 15209, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
15211 return &VECTORY_REG_VLBWDQ_mask();
15212}
15213
15214const RegMask *legVecYOper::in_RegMask(int index) const {
15215 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 15214, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
15216 return &VECTORY_REG_LEGACY_mask();
15217}
15218
15219const RegMask *vecZOper::in_RegMask(int index) const {
15220 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 15219, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
15221 return &VECTORZ_REG_mask();
15222}
15223
15224const RegMask *legVecZOper::in_RegMask(int index) const {
15225 assert(0 <= index && index < 1, "index out of range")do { if (!(0 <= index && index < 1)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 15224, "assert(" "0 <= index && index < 1"
") failed", "index out of range"); ::breakpoint(); } } while
(0);
15226 return &VECTORZ_REG_LEGACY_mask();
15227}
15228
15229//------------------Define members for classes derived from MachNode----------
15230
15231void MoveVL2FNode::use_cisc_RegMask() {
15232 _cisc_RegMask = &STACK_OR_FLOAT_REG_VL_mask();
15233}
15234
15235// Build CISC version of this instruction
15236MachNode *MoveVL2FNode::cisc_version(int offset) {
15237 loadFNode *node = new loadFNode();
15238
15239 // Copy _idx, inputs and operands to new node
15240 fill_new_machnode(node);
15241 // Construct operand to access [stack_pointer + offset]
15242 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15243
15244 return node;
15245}
15246
15247
15248void MoveLEG2FNode::use_cisc_RegMask() {
15249 _cisc_RegMask = &STACK_OR_FLOAT_REG_LEGACY_mask();
15250}
15251
15252// Build CISC version of this instruction
15253MachNode *MoveLEG2FNode::cisc_version(int offset) {
15254 loadFNode *node = new loadFNode();
15255
15256 // Copy _idx, inputs and operands to new node
15257 fill_new_machnode(node);
15258 // Construct operand to access [stack_pointer + offset]
15259 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15260
15261 return node;
15262}
15263
15264
15265void MoveVL2DNode::use_cisc_RegMask() {
15266 _cisc_RegMask = &STACK_OR_DOUBLE_REG_VL_mask();
15267}
15268
15269// Build CISC version of this instruction
15270MachNode *MoveVL2DNode::cisc_version(int offset) {
15271 loadSSDNode *node = new loadSSDNode();
15272
15273 // Copy _idx, inputs and operands to new node
15274 fill_new_machnode(node);
15275 // Construct operand to access [stack_pointer + offset]
15276 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15277
15278 return node;
15279}
15280
15281
15282void MoveLEG2DNode::use_cisc_RegMask() {
15283 _cisc_RegMask = &STACK_OR_DOUBLE_REG_LEGACY_mask();
15284}
15285
15286// Build CISC version of this instruction
15287MachNode *MoveLEG2DNode::cisc_version(int offset) {
15288 loadSSDNode *node = new loadSSDNode();
15289
15290 // Copy _idx, inputs and operands to new node
15291 fill_new_machnode(node);
15292 // Construct operand to access [stack_pointer + offset]
15293 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15294
15295 return node;
15296}
15297
15298
15299void popCountINode::use_cisc_RegMask() {
15300 _cisc_RegMask = &STACK_OR_INT_REG_mask();
15301}
15302
15303// Build CISC version of this instruction
15304MachNode *popCountINode::cisc_version(int offset) {
15305 popCountI_memNode *node = new popCountI_memNode();
15306
15307 // Copy _idx, inputs and operands to new node
15308 fill_new_machnode(node);
15309 // Construct operand to access [stack_pointer + offset]
15310 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15311
15312 return node;
15313}
15314
15315
15316void popCountLNode::use_cisc_RegMask() {
15317 _cisc_RegMask = &STACK_OR_LONG_REG_mask();
15318}
15319
15320// Build CISC version of this instruction
15321MachNode *popCountLNode::cisc_version(int offset) {
15322 popCountL_memNode *node = new popCountL_memNode();
15323
15324 // Copy _idx, inputs and operands to new node
15325 fill_new_machnode(node);
15326 // Construct operand to access [stack_pointer + offset]
15327 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15328
15329 return node;
15330}
15331
15332
15333void cmovI_regNode::use_cisc_RegMask() {
15334 _cisc_RegMask = &STACK_OR_INT_REG_mask();
15335}
15336
15337// Build CISC version of this instruction
15338MachNode *cmovI_regNode::cisc_version(int offset) {
15339 cmovI_memNode *node = new cmovI_memNode();
15340
15341 // Copy _idx, inputs and operands to new node
15342 fill_new_machnode(node);
15343 // Construct operand to access [stack_pointer + offset]
15344 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15345
15346 return node;
15347}
15348
15349
15350void cmovI_regUNode::use_cisc_RegMask() {
15351 _cisc_RegMask = &STACK_OR_INT_REG_mask();
15352}
15353
15354// Build CISC version of this instruction
15355MachNode *cmovI_regUNode::cisc_version(int offset) {
15356 cmovI_memUNode *node = new cmovI_memUNode();
15357
15358 // Copy _idx, inputs and operands to new node
15359 fill_new_machnode(node);
15360 // Construct operand to access [stack_pointer + offset]
15361 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15362
15363 return node;
15364}
15365
15366
15367void cmovI_regUCFNode::use_cisc_RegMask() {
15368 _cisc_RegMask = &STACK_OR_INT_REG_mask();
15369}
15370
15371// Build CISC version of this instruction
15372MachNode *cmovI_regUCFNode::cisc_version(int offset) {
15373 cmovI_memUCFNode *node = new cmovI_memUCFNode();
15374
15375 // Copy _idx, inputs and operands to new node
15376 fill_new_machnode(node);
15377 // Construct operand to access [stack_pointer + offset]
15378 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15379
15380 return node;
15381}
15382
15383
15384void cmovL_regNode::use_cisc_RegMask() {
15385 _cisc_RegMask = &STACK_OR_LONG_REG_mask();
15386}
15387
15388// Build CISC version of this instruction
15389MachNode *cmovL_regNode::cisc_version(int offset) {
15390 cmovL_memNode *node = new cmovL_memNode();
15391
15392 // Copy _idx, inputs and operands to new node
15393 fill_new_machnode(node);
15394 // Construct operand to access [stack_pointer + offset]
15395 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15396
15397 return node;
15398}
15399
15400
15401void cmovL_regUNode::use_cisc_RegMask() {
15402 _cisc_RegMask = &STACK_OR_LONG_REG_mask();
15403}
15404
15405// Build CISC version of this instruction
15406MachNode *cmovL_regUNode::cisc_version(int offset) {
15407 cmovL_memUNode *node = new cmovL_memUNode();
15408
15409 // Copy _idx, inputs and operands to new node
15410 fill_new_machnode(node);
15411 // Construct operand to access [stack_pointer + offset]
15412 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15413
15414 return node;
15415}
15416
15417
15418void cmovL_regUCFNode::use_cisc_RegMask() {
15419 _cisc_RegMask = &STACK_OR_LONG_REG_mask();
15420}
15421
15422// Build CISC version of this instruction
15423MachNode *cmovL_regUCFNode::cisc_version(int offset) {
15424 cmovL_memUCFNode *node = new cmovL_memUCFNode();
15425
15426 // Copy _idx, inputs and operands to new node
15427 fill_new_machnode(node);
15428 // Construct operand to access [stack_pointer + offset]
15429 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15430
15431 return node;
15432}
15433
15434
15435void addI_rRegNode::use_cisc_RegMask() {
15436 _cisc_RegMask = &STACK_OR_INT_REG_mask();
15437}
15438
15439// Build CISC version of this instruction
15440MachNode *addI_rRegNode::cisc_version(int offset) {
15441 addI_rReg_memNode *node = new addI_rReg_memNode();
15442
15443 // Copy _idx, inputs and operands to new node
15444 fill_new_machnode(node);
15445 // Construct operand to access [stack_pointer + offset]
15446 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15447
15448 return node;
15449}
15450
15451
15452void addL_rRegNode::use_cisc_RegMask() {
15453 _cisc_RegMask = &STACK_OR_LONG_REG_mask();
15454}
15455
15456// Build CISC version of this instruction
15457MachNode *addL_rRegNode::cisc_version(int offset) {
15458 addL_rReg_memNode *node = new addL_rReg_memNode();
15459
15460 // Copy _idx, inputs and operands to new node
15461 fill_new_machnode(node);
15462 // Construct operand to access [stack_pointer + offset]
15463 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15464
15465 return node;
15466}
15467
15468
15469void subI_rRegNode::use_cisc_RegMask() {
15470 _cisc_RegMask = &STACK_OR_INT_REG_mask();
15471}
15472
15473// Build CISC version of this instruction
15474MachNode *subI_rRegNode::cisc_version(int offset) {
15475 subI_rReg_memNode *node = new subI_rReg_memNode();
15476
15477 // Copy _idx, inputs and operands to new node
15478 fill_new_machnode(node);
15479 // Construct operand to access [stack_pointer + offset]
15480 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15481
15482 return node;
15483}
15484
15485
15486void subL_rRegNode::use_cisc_RegMask() {
15487 _cisc_RegMask = &STACK_OR_LONG_REG_mask();
15488}
15489
15490// Build CISC version of this instruction
15491MachNode *subL_rRegNode::cisc_version(int offset) {
15492 subL_rReg_memNode *node = new subL_rReg_memNode();
15493
15494 // Copy _idx, inputs and operands to new node
15495 fill_new_machnode(node);
15496 // Construct operand to access [stack_pointer + offset]
15497 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15498
15499 return node;
15500}
15501
15502
15503void mulI_rRegNode::use_cisc_RegMask() {
15504 _cisc_RegMask = &STACK_OR_INT_REG_mask();
15505}
15506
15507// Build CISC version of this instruction
15508MachNode *mulI_rRegNode::cisc_version(int offset) {
15509 mulI_memNode *node = new mulI_memNode();
15510
15511 // Copy _idx, inputs and operands to new node
15512 fill_new_machnode(node);
15513 // Construct operand to access [stack_pointer + offset]
15514 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15515
15516 return node;
15517}
15518
15519
15520void mulI_rReg_immNode::use_cisc_RegMask() {
15521 _cisc_RegMask = &STACK_OR_INT_REG_mask();
15522}
15523
15524// Build CISC version of this instruction
15525MachNode *mulI_rReg_immNode::cisc_version(int offset) {
15526 mulI_mem_immNode *node = new mulI_mem_immNode();
15527
15528 // Copy _idx, inputs and operands to new node
15529 fill_new_machnode(node);
15530 // Construct operand to access [stack_pointer + offset]
15531 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15532
15533 return node;
15534}
15535
15536
15537void mulL_rRegNode::use_cisc_RegMask() {
15538 _cisc_RegMask = &STACK_OR_LONG_REG_mask();
15539}
15540
15541// Build CISC version of this instruction
15542MachNode *mulL_rRegNode::cisc_version(int offset) {
15543 mulL_memNode *node = new mulL_memNode();
15544
15545 // Copy _idx, inputs and operands to new node
15546 fill_new_machnode(node);
15547 // Construct operand to access [stack_pointer + offset]
15548 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15549
15550 return node;
15551}
15552
15553
15554void mulL_rReg_immNode::use_cisc_RegMask() {
15555 _cisc_RegMask = &STACK_OR_LONG_REG_mask();
15556}
15557
15558// Build CISC version of this instruction
15559MachNode *mulL_rReg_immNode::cisc_version(int offset) {
15560 mulL_mem_immNode *node = new mulL_mem_immNode();
15561
15562 // Copy _idx, inputs and operands to new node
15563 fill_new_machnode(node);
15564 // Construct operand to access [stack_pointer + offset]
15565 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15566
15567 return node;
15568}
15569
15570
15571void i2bNode::use_cisc_RegMask() {
15572 _cisc_RegMask = &STACK_OR_INT_REG_mask();
15573}
15574
15575// Build CISC version of this instruction
15576MachNode *i2bNode::cisc_version(int offset) {
15577 loadI2BNode *node = new loadI2BNode();
15578 node->_num_opnds = 3;
15579
15580 // Copy _idx, inputs and operands to new node
15581 fill_new_machnode(node);
15582 // Construct operand to access [stack_pointer + offset]
15583 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15584
15585 return node;
15586}
15587
15588
15589void i2sNode::use_cisc_RegMask() {
15590 _cisc_RegMask = &STACK_OR_INT_REG_mask();
15591}
15592
15593// Build CISC version of this instruction
15594MachNode *i2sNode::cisc_version(int offset) {
15595 loadI2SNode *node = new loadI2SNode();
15596 node->_num_opnds = 3;
15597
15598 // Copy _idx, inputs and operands to new node
15599 fill_new_machnode(node);
15600 // Construct operand to access [stack_pointer + offset]
15601 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15602
15603 return node;
15604}
15605
15606
15607void andI_rRegNode::use_cisc_RegMask() {
15608 _cisc_RegMask = &STACK_OR_INT_REG_mask();
15609}
15610
15611// Build CISC version of this instruction
15612MachNode *andI_rRegNode::cisc_version(int offset) {
15613 andI_rReg_memNode *node = new andI_rReg_memNode();
15614
15615 // Copy _idx, inputs and operands to new node
15616 fill_new_machnode(node);
15617 // Construct operand to access [stack_pointer + offset]
15618 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15619
15620 return node;
15621}
15622
15623
15624void andI2L_rReg_imm255Node::use_cisc_RegMask() {
15625 _cisc_RegMask = &STACK_OR_INT_REG_mask();
15626}
15627
15628// Build CISC version of this instruction
15629MachNode *andI2L_rReg_imm255Node::cisc_version(int offset) {
15630 loadI2L_immI_255Node *node = new loadI2L_immI_255Node();
15631
15632 // Copy _idx, inputs and operands to new node
15633 fill_new_machnode(node);
15634 // Construct operand to access [stack_pointer + offset]
15635 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15636
15637 return node;
15638}
15639
15640
15641void andI2L_rReg_imm65535Node::use_cisc_RegMask() {
15642 _cisc_RegMask = &STACK_OR_INT_REG_mask();
15643}
15644
15645// Build CISC version of this instruction
15646MachNode *andI2L_rReg_imm65535Node::cisc_version(int offset) {
15647 loadI2L_immI_65535Node *node = new loadI2L_immI_65535Node();
15648
15649 // Copy _idx, inputs and operands to new node
15650 fill_new_machnode(node);
15651 // Construct operand to access [stack_pointer + offset]
15652 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15653
15654 return node;
15655}
15656
15657
15658void andnI_rReg_rReg_rRegNode::use_cisc_RegMask() {
15659 _cisc_RegMask = &STACK_OR_INT_REG_mask();
15660}
15661
15662// Build CISC version of this instruction
15663MachNode *andnI_rReg_rReg_rRegNode::cisc_version(int offset) {
15664 andnI_rReg_rReg_memNode *node = new andnI_rReg_rReg_memNode();
15665
15666 // Copy _idx, inputs and operands to new node
15667 fill_new_machnode(node);
15668 // Construct operand to access [stack_pointer + offset]
15669 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15670
15671 return node;
15672}
15673
15674
15675void andnI_rReg_rReg_rReg_0Node::use_cisc_RegMask() {
15676 _cisc_RegMask = &STACK_OR_INT_REG_mask();
15677}
15678
15679// Build CISC version of this instruction
15680MachNode *andnI_rReg_rReg_rReg_0Node::cisc_version(int offset) {
15681 andnI_rReg_rReg_mem_0Node *node = new andnI_rReg_rReg_mem_0Node();
15682
15683 // Copy _idx, inputs and operands to new node
15684 fill_new_machnode(node);
15685 // Construct operand to access [stack_pointer + offset]
15686 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15687
15688 return node;
15689}
15690
15691
15692void orI_rRegNode::use_cisc_RegMask() {
15693 _cisc_RegMask = &STACK_OR_INT_REG_mask();
15694}
15695
15696// Build CISC version of this instruction
15697MachNode *orI_rRegNode::cisc_version(int offset) {
15698 orI_rReg_memNode *node = new orI_rReg_memNode();
15699
15700 // Copy _idx, inputs and operands to new node
15701 fill_new_machnode(node);
15702 // Construct operand to access [stack_pointer + offset]
15703 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15704
15705 return node;
15706}
15707
15708
15709void xorI_rRegNode::use_cisc_RegMask() {
15710 _cisc_RegMask = &STACK_OR_INT_REG_mask();
15711}
15712
15713// Build CISC version of this instruction
15714MachNode *xorI_rRegNode::cisc_version(int offset) {
15715 xorI_rReg_memNode *node = new xorI_rReg_memNode();
15716
15717 // Copy _idx, inputs and operands to new node
15718 fill_new_machnode(node);
15719 // Construct operand to access [stack_pointer + offset]
15720 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15721
15722 return node;
15723}
15724
15725
15726void andL_rRegNode::use_cisc_RegMask() {
15727 _cisc_RegMask = &STACK_OR_LONG_REG_mask();
15728}
15729
15730// Build CISC version of this instruction
15731MachNode *andL_rRegNode::cisc_version(int offset) {
15732 andL_rReg_memNode *node = new andL_rReg_memNode();
15733
15734 // Copy _idx, inputs and operands to new node
15735 fill_new_machnode(node);
15736 // Construct operand to access [stack_pointer + offset]
15737 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15738
15739 return node;
15740}
15741
15742
15743void andnL_rReg_rReg_rRegNode::use_cisc_RegMask() {
15744 _cisc_RegMask = &STACK_OR_LONG_REG_mask();
15745}
15746
15747// Build CISC version of this instruction
15748MachNode *andnL_rReg_rReg_rRegNode::cisc_version(int offset) {
15749 andnL_rReg_rReg_memNode *node = new andnL_rReg_rReg_memNode();
15750
15751 // Copy _idx, inputs and operands to new node
15752 fill_new_machnode(node);
15753 // Construct operand to access [stack_pointer + offset]
15754 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15755
15756 return node;
15757}
15758
15759
15760void andnL_rReg_rReg_rReg_0Node::use_cisc_RegMask() {
15761 _cisc_RegMask = &STACK_OR_LONG_REG_mask();
15762}
15763
15764// Build CISC version of this instruction
15765MachNode *andnL_rReg_rReg_rReg_0Node::cisc_version(int offset) {
15766 andnL_rReg_rReg_mem_0Node *node = new andnL_rReg_rReg_mem_0Node();
15767
15768 // Copy _idx, inputs and operands to new node
15769 fill_new_machnode(node);
15770 // Construct operand to access [stack_pointer + offset]
15771 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15772
15773 return node;
15774}
15775
15776
15777void orL_rRegNode::use_cisc_RegMask() {
15778 _cisc_RegMask = &STACK_OR_LONG_REG_mask();
15779}
15780
15781// Build CISC version of this instruction
15782MachNode *orL_rRegNode::cisc_version(int offset) {
15783 orL_rReg_memNode *node = new orL_rReg_memNode();
15784
15785 // Copy _idx, inputs and operands to new node
15786 fill_new_machnode(node);
15787 // Construct operand to access [stack_pointer + offset]
15788 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15789
15790 return node;
15791}
15792
15793
15794void xorL_rRegNode::use_cisc_RegMask() {
15795 _cisc_RegMask = &STACK_OR_LONG_REG_mask();
15796}
15797
15798// Build CISC version of this instruction
15799MachNode *xorL_rRegNode::cisc_version(int offset) {
15800 xorL_rReg_memNode *node = new xorL_rReg_memNode();
15801
15802 // Copy _idx, inputs and operands to new node
15803 fill_new_machnode(node);
15804 // Construct operand to access [stack_pointer + offset]
15805 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15806
15807 return node;
15808}
15809
15810
15811void cmpF_cc_regNode::use_cisc_RegMask() {
15812 _cisc_RegMask = &STACK_OR_FLOAT_REG_mask();
15813}
15814
15815// Build CISC version of this instruction
15816MachNode *cmpF_cc_regNode::cisc_version(int offset) {
15817 cmpF_cc_memNode *node = new cmpF_cc_memNode();
15818
15819 // Copy _idx, inputs and operands to new node
15820 fill_new_machnode(node);
15821 // Construct operand to access [stack_pointer + offset]
15822 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15823
15824 return node;
15825}
15826
15827
15828void cmpF_cc_reg_CFNode::use_cisc_RegMask() {
15829 _cisc_RegMask = &STACK_OR_FLOAT_REG_mask();
15830}
15831
15832// Build CISC version of this instruction
15833MachNode *cmpF_cc_reg_CFNode::cisc_version(int offset) {
15834 cmpF_cc_memCFNode *node = new cmpF_cc_memCFNode();
15835
15836 // Copy _idx, inputs and operands to new node
15837 fill_new_machnode(node);
15838 // Construct operand to access [stack_pointer + offset]
15839 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15840
15841 return node;
15842}
15843
15844
15845void cmpD_cc_regNode::use_cisc_RegMask() {
15846 _cisc_RegMask = &STACK_OR_DOUBLE_REG_mask();
15847}
15848
15849// Build CISC version of this instruction
15850MachNode *cmpD_cc_regNode::cisc_version(int offset) {
15851 cmpD_cc_memNode *node = new cmpD_cc_memNode();
15852
15853 // Copy _idx, inputs and operands to new node
15854 fill_new_machnode(node);
15855 // Construct operand to access [stack_pointer + offset]
15856 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15857
15858 return node;
15859}
15860
15861
15862void cmpD_cc_reg_CFNode::use_cisc_RegMask() {
15863 _cisc_RegMask = &STACK_OR_DOUBLE_REG_mask();
15864}
15865
15866// Build CISC version of this instruction
15867MachNode *cmpD_cc_reg_CFNode::cisc_version(int offset) {
15868 cmpD_cc_memCFNode *node = new cmpD_cc_memCFNode();
15869
15870 // Copy _idx, inputs and operands to new node
15871 fill_new_machnode(node);
15872 // Construct operand to access [stack_pointer + offset]
15873 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15874
15875 return node;
15876}
15877
15878
15879void cmpF_regNode::use_cisc_RegMask() {
15880 _cisc_RegMask = &STACK_OR_FLOAT_REG_mask();
15881}
15882
15883// Build CISC version of this instruction
15884MachNode *cmpF_regNode::cisc_version(int offset) {
15885 cmpF_memNode *node = new cmpF_memNode();
15886
15887 // Copy _idx, inputs and operands to new node
15888 fill_new_machnode(node);
15889 // Construct operand to access [stack_pointer + offset]
15890 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15891
15892 return node;
15893}
15894
15895
15896void cmpD_regNode::use_cisc_RegMask() {
15897 _cisc_RegMask = &STACK_OR_DOUBLE_REG_mask();
15898}
15899
15900// Build CISC version of this instruction
15901MachNode *cmpD_regNode::cisc_version(int offset) {
15902 cmpD_memNode *node = new cmpD_memNode();
15903
15904 // Copy _idx, inputs and operands to new node
15905 fill_new_machnode(node);
15906 // Construct operand to access [stack_pointer + offset]
15907 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15908
15909 return node;
15910}
15911
15912
15913void convF2D_reg_regNode::use_cisc_RegMask() {
15914 _cisc_RegMask = &STACK_OR_FLOAT_REG_mask();
15915}
15916
15917// Build CISC version of this instruction
15918MachNode *convF2D_reg_regNode::cisc_version(int offset) {
15919 convF2D_reg_memNode *node = new convF2D_reg_memNode();
15920
15921 // Copy _idx, inputs and operands to new node
15922 fill_new_machnode(node);
15923 // Construct operand to access [stack_pointer + offset]
15924 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15925
15926 return node;
15927}
15928
15929
15930void convD2F_reg_regNode::use_cisc_RegMask() {
15931 _cisc_RegMask = &STACK_OR_DOUBLE_REG_mask();
15932}
15933
15934// Build CISC version of this instruction
15935MachNode *convD2F_reg_regNode::cisc_version(int offset) {
15936 convD2F_reg_memNode *node = new convD2F_reg_memNode();
15937
15938 // Copy _idx, inputs and operands to new node
15939 fill_new_machnode(node);
15940 // Construct operand to access [stack_pointer + offset]
15941 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15942
15943 return node;
15944}
15945
15946
15947void convL2F_reg_regNode::use_cisc_RegMask() {
15948 _cisc_RegMask = &STACK_OR_LONG_REG_mask();
15949}
15950
15951// Build CISC version of this instruction
15952MachNode *convL2F_reg_regNode::cisc_version(int offset) {
15953 convL2F_reg_memNode *node = new convL2F_reg_memNode();
15954
15955 // Copy _idx, inputs and operands to new node
15956 fill_new_machnode(node);
15957 // Construct operand to access [stack_pointer + offset]
15958 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15959
15960 return node;
15961}
15962
15963
15964void convL2D_reg_regNode::use_cisc_RegMask() {
15965 _cisc_RegMask = &STACK_OR_LONG_REG_mask();
15966}
15967
15968// Build CISC version of this instruction
15969MachNode *convL2D_reg_regNode::cisc_version(int offset) {
15970 convL2D_reg_memNode *node = new convL2D_reg_memNode();
15971
15972 // Copy _idx, inputs and operands to new node
15973 fill_new_machnode(node);
15974 // Construct operand to access [stack_pointer + offset]
15975 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15976
15977 return node;
15978}
15979
15980
15981void convI2L_reg_regNode::use_cisc_RegMask() {
15982 _cisc_RegMask = &STACK_OR_INT_REG_mask();
15983}
15984
15985// Build CISC version of this instruction
15986MachNode *convI2L_reg_regNode::cisc_version(int offset) {
15987 loadI2LNode *node = new loadI2LNode();
15988
15989 // Copy _idx, inputs and operands to new node
15990 fill_new_machnode(node);
15991 // Construct operand to access [stack_pointer + offset]
15992 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
15993
15994 return node;
15995}
15996
15997
15998void convI2L_reg_reg_zexNode::use_cisc_RegMask() {
15999 _cisc_RegMask = &STACK_OR_INT_REG_mask();
16000}
16001
16002// Build CISC version of this instruction
16003MachNode *convI2L_reg_reg_zexNode::cisc_version(int offset) {
16004 loadUI2LNode *node = new loadUI2LNode();
16005
16006 // Copy _idx, inputs and operands to new node
16007 fill_new_machnode(node);
16008 // Construct operand to access [stack_pointer + offset]
16009 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
16010
16011 return node;
16012}
16013
16014
16015void MoveF2I_reg_regNode::use_cisc_RegMask() {
16016 _cisc_RegMask = &STACK_OR_FLOAT_REG_mask();
16017}
16018
16019// Build CISC version of this instruction
16020MachNode *MoveF2I_reg_regNode::cisc_version(int offset) {
16021 MoveF2I_stack_regNode *node = new MoveF2I_stack_regNode();
16022
16023 // Copy _idx, inputs and operands to new node
16024 fill_new_machnode(node);
16025 // Construct operand to access [stack_pointer + offset]
16026 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
16027
16028 return node;
16029}
16030
16031
16032void MoveD2L_reg_regNode::use_cisc_RegMask() {
16033 _cisc_RegMask = &STACK_OR_DOUBLE_REG_mask();
16034}
16035
16036// Build CISC version of this instruction
16037MachNode *MoveD2L_reg_regNode::cisc_version(int offset) {
16038 MoveD2L_stack_regNode *node = new MoveD2L_stack_regNode();
16039
16040 // Copy _idx, inputs and operands to new node
16041 fill_new_machnode(node);
16042 // Construct operand to access [stack_pointer + offset]
16043 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
16044
16045 return node;
16046}
16047
16048
16049void MoveI2F_reg_regNode::use_cisc_RegMask() {
16050 _cisc_RegMask = &STACK_OR_INT_REG_mask();
16051}
16052
16053// Build CISC version of this instruction
16054MachNode *MoveI2F_reg_regNode::cisc_version(int offset) {
16055 MoveI2F_stack_regNode *node = new MoveI2F_stack_regNode();
16056
16057 // Copy _idx, inputs and operands to new node
16058 fill_new_machnode(node);
16059 // Construct operand to access [stack_pointer + offset]
16060 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
16061
16062 return node;
16063}
16064
16065
16066void compI_rRegNode::use_cisc_RegMask() {
16067 _cisc_RegMask = &STACK_OR_INT_REG_mask();
16068}
16069
16070// Build CISC version of this instruction
16071MachNode *compI_rRegNode::cisc_version(int offset) {
16072 compI_rReg_memNode *node = new compI_rReg_memNode();
16073
16074 // Copy _idx, inputs and operands to new node
16075 fill_new_machnode(node);
16076 // Construct operand to access [stack_pointer + offset]
16077 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
16078
16079 return node;
16080}
16081
16082
16083void compU_rRegNode::use_cisc_RegMask() {
16084 _cisc_RegMask = &STACK_OR_INT_REG_mask();
16085}
16086
16087// Build CISC version of this instruction
16088MachNode *compU_rRegNode::cisc_version(int offset) {
16089 compU_rReg_memNode *node = new compU_rReg_memNode();
16090
16091 // Copy _idx, inputs and operands to new node
16092 fill_new_machnode(node);
16093 // Construct operand to access [stack_pointer + offset]
16094 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
16095
16096 return node;
16097}
16098
16099
16100void compL_rRegNode::use_cisc_RegMask() {
16101 _cisc_RegMask = &STACK_OR_LONG_REG_mask();
16102}
16103
16104// Build CISC version of this instruction
16105MachNode *compL_rRegNode::cisc_version(int offset) {
16106 compL_rReg_memNode *node = new compL_rReg_memNode();
16107
16108 // Copy _idx, inputs and operands to new node
16109 fill_new_machnode(node);
16110 // Construct operand to access [stack_pointer + offset]
16111 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
16112
16113 return node;
16114}
16115
16116
16117void compUL_rRegNode::use_cisc_RegMask() {
16118 _cisc_RegMask = &STACK_OR_LONG_REG_mask();
16119}
16120
16121// Build CISC version of this instruction
16122MachNode *compUL_rRegNode::cisc_version(int offset) {
16123 compUL_rReg_memNode *node = new compUL_rReg_memNode();
16124
16125 // Copy _idx, inputs and operands to new node
16126 fill_new_machnode(node);
16127 // Construct operand to access [stack_pointer + offset]
16128 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
16129
16130 return node;
16131}
16132
16133// Build short branch version of this instruction
16134MachNode *jmpDirNode::short_branch_version() {
16135 jmpDir_shortNode *node = new jmpDir_shortNode();
16136
16137 // Copy _idx, inputs and operands to new node
16138 fill_new_machnode(node);
16139 return node;
16140}
16141
16142// Build short branch version of this instruction
16143MachNode *jmpConNode::short_branch_version() {
16144 jmpCon_shortNode *node = new jmpCon_shortNode();
16145 node->_prob = _prob;
16146 node->_fcnt = _fcnt;
16147
16148 // Copy _idx, inputs and operands to new node
16149 fill_new_machnode(node);
16150 return node;
16151}
16152
16153// Build short branch version of this instruction
16154MachNode *jmpLoopEndNode::short_branch_version() {
16155 jmpLoopEnd_shortNode *node = new jmpLoopEnd_shortNode();
16156 node->_prob = _prob;
16157 node->_fcnt = _fcnt;
16158
16159 // Copy _idx, inputs and operands to new node
16160 fill_new_machnode(node);
16161 return node;
16162}
16163
16164// Build short branch version of this instruction
16165MachNode *jmpLoopEndUNode::short_branch_version() {
16166 jmpLoopEndU_shortNode *node = new jmpLoopEndU_shortNode();
16167 node->_prob = _prob;
16168 node->_fcnt = _fcnt;
16169
16170 // Copy _idx, inputs and operands to new node
16171 fill_new_machnode(node);
16172 return node;
16173}
16174
16175// Build short branch version of this instruction
16176MachNode *jmpLoopEndUCFNode::short_branch_version() {
16177 jmpLoopEndUCF_shortNode *node = new jmpLoopEndUCF_shortNode();
16178 node->_prob = _prob;
16179 node->_fcnt = _fcnt;
16180
16181 // Copy _idx, inputs and operands to new node
16182 fill_new_machnode(node);
16183 return node;
16184}
16185
16186// Build short branch version of this instruction
16187MachNode *jmpConUNode::short_branch_version() {
16188 jmpConU_shortNode *node = new jmpConU_shortNode();
16189 node->_prob = _prob;
16190 node->_fcnt = _fcnt;
16191
16192 // Copy _idx, inputs and operands to new node
16193 fill_new_machnode(node);
16194 return node;
16195}
16196
16197// Build short branch version of this instruction
16198MachNode *jmpConUCFNode::short_branch_version() {
16199 jmpConUCF_shortNode *node = new jmpConUCF_shortNode();
16200 node->_prob = _prob;
16201 node->_fcnt = _fcnt;
16202
16203 // Copy _idx, inputs and operands to new node
16204 fill_new_machnode(node);
16205 return node;
16206}
16207
16208// Build short branch version of this instruction
16209MachNode *jmpConUCF2Node::short_branch_version() {
16210 jmpConUCF2_shortNode *node = new jmpConUCF2_shortNode();
16211 node->_prob = _prob;
16212 node->_fcnt = _fcnt;
16213
16214 // Copy _idx, inputs and operands to new node
16215 fill_new_machnode(node);
16216 return node;
16217}
16218
16219
16220void addF_regNode::use_cisc_RegMask() {
16221 _cisc_RegMask = &STACK_OR_FLOAT_REG_mask();
16222}
16223
16224// Build CISC version of this instruction
16225MachNode *addF_regNode::cisc_version(int offset) {
16226 addF_memNode *node = new addF_memNode();
16227
16228 // Copy _idx, inputs and operands to new node
16229 fill_new_machnode(node);
16230 // Construct operand to access [stack_pointer + offset]
16231 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
16232
16233 return node;
16234}
16235
16236
16237void addF_reg_regNode::use_cisc_RegMask() {
16238 _cisc_RegMask = &STACK_OR_FLOAT_REG_mask();
16239}
16240
16241// Build CISC version of this instruction
16242MachNode *addF_reg_regNode::cisc_version(int offset) {
16243 addF_reg_memNode *node = new addF_reg_memNode();
16244
16245 // Copy _idx, inputs and operands to new node
16246 fill_new_machnode(node);
16247 // Construct operand to access [stack_pointer + offset]
16248 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
16249
16250 return node;
16251}
16252
16253
16254void addD_regNode::use_cisc_RegMask() {
16255 _cisc_RegMask = &STACK_OR_DOUBLE_REG_mask();
16256}
16257
16258// Build CISC version of this instruction
16259MachNode *addD_regNode::cisc_version(int offset) {
16260 addD_memNode *node = new addD_memNode();
16261
16262 // Copy _idx, inputs and operands to new node
16263 fill_new_machnode(node);
16264 // Construct operand to access [stack_pointer + offset]
16265 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
16266
16267 return node;
16268}
16269
16270
16271void addD_reg_regNode::use_cisc_RegMask() {
16272 _cisc_RegMask = &STACK_OR_DOUBLE_REG_mask();
16273}
16274
16275// Build CISC version of this instruction
16276MachNode *addD_reg_regNode::cisc_version(int offset) {
16277 addD_reg_memNode *node = new addD_reg_memNode();
16278
16279 // Copy _idx, inputs and operands to new node
16280 fill_new_machnode(node);
16281 // Construct operand to access [stack_pointer + offset]
16282 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
16283
16284 return node;
16285}
16286
16287
16288void subF_regNode::use_cisc_RegMask() {
16289 _cisc_RegMask = &STACK_OR_FLOAT_REG_mask();
16290}
16291
16292// Build CISC version of this instruction
16293MachNode *subF_regNode::cisc_version(int offset) {
16294 subF_memNode *node = new subF_memNode();
16295
16296 // Copy _idx, inputs and operands to new node
16297 fill_new_machnode(node);
16298 // Construct operand to access [stack_pointer + offset]
16299 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
16300
16301 return node;
16302}
16303
16304
16305void subF_reg_regNode::use_cisc_RegMask() {
16306 _cisc_RegMask = &STACK_OR_FLOAT_REG_mask();
16307}
16308
16309// Build CISC version of this instruction
16310MachNode *subF_reg_regNode::cisc_version(int offset) {
16311 subF_reg_memNode *node = new subF_reg_memNode();
16312
16313 // Copy _idx, inputs and operands to new node
16314 fill_new_machnode(node);
16315 // Construct operand to access [stack_pointer + offset]
16316 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
16317
16318 return node;
16319}
16320
16321
16322void subD_regNode::use_cisc_RegMask() {
16323 _cisc_RegMask = &STACK_OR_DOUBLE_REG_mask();
16324}
16325
16326// Build CISC version of this instruction
16327MachNode *subD_regNode::cisc_version(int offset) {
16328 subD_memNode *node = new subD_memNode();
16329
16330 // Copy _idx, inputs and operands to new node
16331 fill_new_machnode(node);
16332 // Construct operand to access [stack_pointer + offset]
16333 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
16334
16335 return node;
16336}
16337
16338
16339void subD_reg_regNode::use_cisc_RegMask() {
16340 _cisc_RegMask = &STACK_OR_DOUBLE_REG_mask();
16341}
16342
16343// Build CISC version of this instruction
16344MachNode *subD_reg_regNode::cisc_version(int offset) {
16345 subD_reg_memNode *node = new subD_reg_memNode();
16346
16347 // Copy _idx, inputs and operands to new node
16348 fill_new_machnode(node);
16349 // Construct operand to access [stack_pointer + offset]
16350 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
16351
16352 return node;
16353}
16354
16355
16356void mulF_regNode::use_cisc_RegMask() {
16357 _cisc_RegMask = &STACK_OR_FLOAT_REG_mask();
16358}
16359
16360// Build CISC version of this instruction
16361MachNode *mulF_regNode::cisc_version(int offset) {
16362 mulF_memNode *node = new mulF_memNode();
16363
16364 // Copy _idx, inputs and operands to new node
16365 fill_new_machnode(node);
16366 // Construct operand to access [stack_pointer + offset]
16367 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
16368
16369 return node;
16370}
16371
16372
16373void mulF_reg_regNode::use_cisc_RegMask() {
16374 _cisc_RegMask = &STACK_OR_FLOAT_REG_mask();
16375}
16376
16377// Build CISC version of this instruction
16378MachNode *mulF_reg_regNode::cisc_version(int offset) {
16379 mulF_reg_memNode *node = new mulF_reg_memNode();
16380
16381 // Copy _idx, inputs and operands to new node
16382 fill_new_machnode(node);
16383 // Construct operand to access [stack_pointer + offset]
16384 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
16385
16386 return node;
16387}
16388
16389
16390void mulD_regNode::use_cisc_RegMask() {
16391 _cisc_RegMask = &STACK_OR_DOUBLE_REG_mask();
16392}
16393
16394// Build CISC version of this instruction
16395MachNode *mulD_regNode::cisc_version(int offset) {
16396 mulD_memNode *node = new mulD_memNode();
16397
16398 // Copy _idx, inputs and operands to new node
16399 fill_new_machnode(node);
16400 // Construct operand to access [stack_pointer + offset]
16401 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
16402
16403 return node;
16404}
16405
16406
16407void mulD_reg_regNode::use_cisc_RegMask() {
16408 _cisc_RegMask = &STACK_OR_DOUBLE_REG_mask();
16409}
16410
16411// Build CISC version of this instruction
16412MachNode *mulD_reg_regNode::cisc_version(int offset) {
16413 mulD_reg_memNode *node = new mulD_reg_memNode();
16414
16415 // Copy _idx, inputs and operands to new node
16416 fill_new_machnode(node);
16417 // Construct operand to access [stack_pointer + offset]
16418 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
16419
16420 return node;
16421}
16422
16423
16424void divF_regNode::use_cisc_RegMask() {
16425 _cisc_RegMask = &STACK_OR_FLOAT_REG_mask();
16426}
16427
16428// Build CISC version of this instruction
16429MachNode *divF_regNode::cisc_version(int offset) {
16430 divF_memNode *node = new divF_memNode();
16431
16432 // Copy _idx, inputs and operands to new node
16433 fill_new_machnode(node);
16434 // Construct operand to access [stack_pointer + offset]
16435 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
16436
16437 return node;
16438}
16439
16440
16441void divF_reg_regNode::use_cisc_RegMask() {
16442 _cisc_RegMask = &STACK_OR_FLOAT_REG_mask();
16443}
16444
16445// Build CISC version of this instruction
16446MachNode *divF_reg_regNode::cisc_version(int offset) {
16447 divF_reg_memNode *node = new divF_reg_memNode();
16448
16449 // Copy _idx, inputs and operands to new node
16450 fill_new_machnode(node);
16451 // Construct operand to access [stack_pointer + offset]
16452 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
16453
16454 return node;
16455}
16456
16457
16458void divD_regNode::use_cisc_RegMask() {
16459 _cisc_RegMask = &STACK_OR_DOUBLE_REG_mask();
16460}
16461
16462// Build CISC version of this instruction
16463MachNode *divD_regNode::cisc_version(int offset) {
16464 divD_memNode *node = new divD_memNode();
16465
16466 // Copy _idx, inputs and operands to new node
16467 fill_new_machnode(node);
16468 // Construct operand to access [stack_pointer + offset]
16469 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
16470
16471 return node;
16472}
16473
16474
16475void divD_reg_regNode::use_cisc_RegMask() {
16476 _cisc_RegMask = &STACK_OR_DOUBLE_REG_mask();
16477}
16478
16479// Build CISC version of this instruction
16480MachNode *divD_reg_regNode::cisc_version(int offset) {
16481 divD_reg_memNode *node = new divD_reg_memNode();
16482
16483 // Copy _idx, inputs and operands to new node
16484 fill_new_machnode(node);
16485 // Construct operand to access [stack_pointer + offset]
16486 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
16487
16488 return node;
16489}
16490
16491
16492void roundD_regNode::use_cisc_RegMask() {
16493 _cisc_RegMask = &STACK_OR_DOUBLE_REG_LEGACY_mask();
16494}
16495
16496// Build CISC version of this instruction
16497MachNode *roundD_regNode::cisc_version(int offset) {
16498 roundD_memNode *node = new roundD_memNode();
16499
16500 // Copy _idx, inputs and operands to new node
16501 fill_new_machnode(node);
16502 // Construct operand to access [stack_pointer + offset]
16503 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
16504
16505 return node;
16506}
16507
16508
16509void ReplI_regNode::use_cisc_RegMask() {
16510 _cisc_RegMask = &STACK_OR_INT_REG_mask();
16511}
16512
16513// Build CISC version of this instruction
16514MachNode *ReplI_regNode::cisc_version(int offset) {
16515 ReplI_memNode *node = new ReplI_memNode();
16516 node->_bottom_type = bottom_type();
16517
16518 // Copy _idx, inputs and operands to new node
16519 fill_new_machnode(node);
16520 // Construct operand to access [stack_pointer + offset]
16521 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
16522
16523 return node;
16524}
16525
16526
16527void ReplL_regNode::use_cisc_RegMask() {
16528 _cisc_RegMask = &STACK_OR_LONG_REG_mask();
16529}
16530
16531// Build CISC version of this instruction
16532MachNode *ReplL_regNode::cisc_version(int offset) {
16533 ReplL_memNode *node = new ReplL_memNode();
16534 node->_bottom_type = bottom_type();
16535
16536 // Copy _idx, inputs and operands to new node
16537 fill_new_machnode(node);
16538 // Construct operand to access [stack_pointer + offset]
16539 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
16540
16541 return node;
16542}
16543
16544
16545void ReplF_regNode::use_cisc_RegMask() {
16546 _cisc_RegMask = &STACK_OR_FLOAT_REG_VL_mask();
16547}
16548
16549// Build CISC version of this instruction
16550MachNode *ReplF_regNode::cisc_version(int offset) {
16551 ReplF_memNode *node = new ReplF_memNode();
16552 node->_bottom_type = bottom_type();
16553
16554 // Copy _idx, inputs and operands to new node
16555 fill_new_machnode(node);
16556 // Construct operand to access [stack_pointer + offset]
16557 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
16558
16559 return node;
16560}
16561
16562
16563void ReplD_regNode::use_cisc_RegMask() {
16564 _cisc_RegMask = &STACK_OR_DOUBLE_REG_VL_mask();
16565}
16566
16567// Build CISC version of this instruction
16568MachNode *ReplD_regNode::cisc_version(int offset) {
16569 ReplD_memNode *node = new ReplD_memNode();
16570 node->_bottom_type = bottom_type();
16571
16572 // Copy _idx, inputs and operands to new node
16573 fill_new_machnode(node);
16574 // Construct operand to access [stack_pointer + offset]
16575 node->set_opnd_array(cisc_operand(), new indOffset32Oper(offset));
16576
16577 return node;
16578}
16579
16580
16581// Copy _idx, inputs and operands to new node
16582void MachNode::fill_new_machnode(MachNode* node) const {
16583 // New node must use same node index
16584 node->set_idx( _idx );
16585 // Copy machine-independent inputs
16586 for( uint j = 0; j < req(); j++ ) {
16587 node->add_req(in(j));
16588 }
16589 // Copy my operands, except for cisc position
16590 int nopnds = num_opnds();
16591 assert( node->num_opnds() == (uint)nopnds, "Must have same number of operands")do { if (!(node->num_opnds() == (uint)nopnds)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 16590, "assert(" "node->num_opnds() == (uint)nopnds"
") failed", "Must have same number of operands"); ::breakpoint
(); } } while (0);
16592 MachOper **to = node->_opnds;
16593 for( int i = 0; i < nopnds; i++ ) {
16594 if( i != cisc_operand() )
16595 to[i] = _opnds[i]->clone();
16596 }
16597}
16598
16599void jmpDirNode::label_set( Label* label, uint block_num ) {
16600 labelOper* oper = (labelOper*)(opnd_array(1));
16601 oper->_label = label;
16602 oper->_block_num = block_num;
16603}
16604void jmpDirNode::save_label( Label** label, uint* block_num ) {
16605 labelOper* oper = (labelOper*)(opnd_array(1));
16606 *label = oper->_label;
16607 *block_num = oper->_block_num;
16608}
16609void jmpConNode::label_set( Label* label, uint block_num ) {
16610 labelOper* oper = (labelOper*)(opnd_array(3));
16611 oper->_label = label;
16612 oper->_block_num = block_num;
16613}
16614void jmpConNode::save_label( Label** label, uint* block_num ) {
16615 labelOper* oper = (labelOper*)(opnd_array(3));
16616 *label = oper->_label;
16617 *block_num = oper->_block_num;
16618}
16619void jmpLoopEndNode::label_set( Label* label, uint block_num ) {
16620 labelOper* oper = (labelOper*)(opnd_array(3));
16621 oper->_label = label;
16622 oper->_block_num = block_num;
16623}
16624void jmpLoopEndNode::save_label( Label** label, uint* block_num ) {
16625 labelOper* oper = (labelOper*)(opnd_array(3));
16626 *label = oper->_label;
16627 *block_num = oper->_block_num;
16628}
16629void jmpLoopEndUNode::label_set( Label* label, uint block_num ) {
16630 labelOper* oper = (labelOper*)(opnd_array(3));
16631 oper->_label = label;
16632 oper->_block_num = block_num;
16633}
16634void jmpLoopEndUNode::save_label( Label** label, uint* block_num ) {
16635 labelOper* oper = (labelOper*)(opnd_array(3));
16636 *label = oper->_label;
16637 *block_num = oper->_block_num;
16638}
16639void jmpLoopEndUCFNode::label_set( Label* label, uint block_num ) {
16640 labelOper* oper = (labelOper*)(opnd_array(3));
16641 oper->_label = label;
16642 oper->_block_num = block_num;
16643}
16644void jmpLoopEndUCFNode::save_label( Label** label, uint* block_num ) {
16645 labelOper* oper = (labelOper*)(opnd_array(3));
16646 *label = oper->_label;
16647 *block_num = oper->_block_num;
16648}
16649void jmpLoopEnd_and_restoreMaskNode::label_set( Label* label, uint block_num ) {
16650 labelOper* oper = (labelOper*)(opnd_array(4));
16651 oper->_label = label;
16652 oper->_block_num = block_num;
16653}
16654void jmpLoopEnd_and_restoreMaskNode::save_label( Label** label, uint* block_num ) {
16655 labelOper* oper = (labelOper*)(opnd_array(4));
16656 *label = oper->_label;
16657 *block_num = oper->_block_num;
16658}
16659void jmpLoopEndU_and_restoreMaskNode::label_set( Label* label, uint block_num ) {
16660 labelOper* oper = (labelOper*)(opnd_array(4));
16661 oper->_label = label;
16662 oper->_block_num = block_num;
16663}
16664void jmpLoopEndU_and_restoreMaskNode::save_label( Label** label, uint* block_num ) {
16665 labelOper* oper = (labelOper*)(opnd_array(4));
16666 *label = oper->_label;
16667 *block_num = oper->_block_num;
16668}
16669void jmpLoopEndUCF_and_restoreMaskNode::label_set( Label* label, uint block_num ) {
16670 labelOper* oper = (labelOper*)(opnd_array(4));
16671 oper->_label = label;
16672 oper->_block_num = block_num;
16673}
16674void jmpLoopEndUCF_and_restoreMaskNode::save_label( Label** label, uint* block_num ) {
16675 labelOper* oper = (labelOper*)(opnd_array(4));
16676 *label = oper->_label;
16677 *block_num = oper->_block_num;
16678}
16679void jmpConUNode::label_set( Label* label, uint block_num ) {
16680 labelOper* oper = (labelOper*)(opnd_array(3));
16681 oper->_label = label;
16682 oper->_block_num = block_num;
16683}
16684void jmpConUNode::save_label( Label** label, uint* block_num ) {
16685 labelOper* oper = (labelOper*)(opnd_array(3));
16686 *label = oper->_label;
16687 *block_num = oper->_block_num;
16688}
16689void jmpConUCFNode::label_set( Label* label, uint block_num ) {
16690 labelOper* oper = (labelOper*)(opnd_array(3));
16691 oper->_label = label;
16692 oper->_block_num = block_num;
16693}
16694void jmpConUCFNode::save_label( Label** label, uint* block_num ) {
16695 labelOper* oper = (labelOper*)(opnd_array(3));
16696 *label = oper->_label;
16697 *block_num = oper->_block_num;
16698}
16699void jmpConUCF2Node::label_set( Label* label, uint block_num ) {
16700 labelOper* oper = (labelOper*)(opnd_array(3));
16701 oper->_label = label;
16702 oper->_block_num = block_num;
16703}
16704void jmpConUCF2Node::save_label( Label** label, uint* block_num ) {
16705 labelOper* oper = (labelOper*)(opnd_array(3));
16706 *label = oper->_label;
16707 *block_num = oper->_block_num;
16708}
16709void jmpDir_shortNode::label_set( Label* label, uint block_num ) {
16710 labelOper* oper = (labelOper*)(opnd_array(1));
16711 oper->_label = label;
16712 oper->_block_num = block_num;
16713}
16714void jmpDir_shortNode::save_label( Label** label, uint* block_num ) {
16715 labelOper* oper = (labelOper*)(opnd_array(1));
16716 *label = oper->_label;
16717 *block_num = oper->_block_num;
16718}
16719void jmpCon_shortNode::label_set( Label* label, uint block_num ) {
16720 labelOper* oper = (labelOper*)(opnd_array(3));
16721 oper->_label = label;
16722 oper->_block_num = block_num;
16723}
16724void jmpCon_shortNode::save_label( Label** label, uint* block_num ) {
16725 labelOper* oper = (labelOper*)(opnd_array(3));
16726 *label = oper->_label;
16727 *block_num = oper->_block_num;
16728}
16729void jmpLoopEnd_shortNode::label_set( Label* label, uint block_num ) {
16730 labelOper* oper = (labelOper*)(opnd_array(3));
16731 oper->_label = label;
16732 oper->_block_num = block_num;
16733}
16734void jmpLoopEnd_shortNode::save_label( Label** label, uint* block_num ) {
16735 labelOper* oper = (labelOper*)(opnd_array(3));
16736 *label = oper->_label;
16737 *block_num = oper->_block_num;
16738}
16739void jmpLoopEndU_shortNode::label_set( Label* label, uint block_num ) {
16740 labelOper* oper = (labelOper*)(opnd_array(3));
16741 oper->_label = label;
16742 oper->_block_num = block_num;
16743}
16744void jmpLoopEndU_shortNode::save_label( Label** label, uint* block_num ) {
16745 labelOper* oper = (labelOper*)(opnd_array(3));
16746 *label = oper->_label;
16747 *block_num = oper->_block_num;
16748}
16749void jmpLoopEndUCF_shortNode::label_set( Label* label, uint block_num ) {
16750 labelOper* oper = (labelOper*)(opnd_array(3));
16751 oper->_label = label;
16752 oper->_block_num = block_num;
16753}
16754void jmpLoopEndUCF_shortNode::save_label( Label** label, uint* block_num ) {
16755 labelOper* oper = (labelOper*)(opnd_array(3));
16756 *label = oper->_label;
16757 *block_num = oper->_block_num;
16758}
16759void jmpConU_shortNode::label_set( Label* label, uint block_num ) {
16760 labelOper* oper = (labelOper*)(opnd_array(3));
16761 oper->_label = label;
16762 oper->_block_num = block_num;
16763}
16764void jmpConU_shortNode::save_label( Label** label, uint* block_num ) {
16765 labelOper* oper = (labelOper*)(opnd_array(3));
16766 *label = oper->_label;
16767 *block_num = oper->_block_num;
16768}
16769void jmpConUCF_shortNode::label_set( Label* label, uint block_num ) {
16770 labelOper* oper = (labelOper*)(opnd_array(3));
16771 oper->_label = label;
16772 oper->_block_num = block_num;
16773}
16774void jmpConUCF_shortNode::save_label( Label** label, uint* block_num ) {
16775 labelOper* oper = (labelOper*)(opnd_array(3));
16776 *label = oper->_label;
16777 *block_num = oper->_block_num;
16778}
16779void jmpConUCF2_shortNode::label_set( Label* label, uint block_num ) {
16780 labelOper* oper = (labelOper*)(opnd_array(3));
16781 oper->_label = label;
16782 oper->_block_num = block_num;
16783}
16784void jmpConUCF2_shortNode::save_label( Label** label, uint* block_num ) {
16785 labelOper* oper = (labelOper*)(opnd_array(3));
16786 *label = oper->_label;
16787 *block_num = oper->_block_num;
16788}
16789void CallStaticJavaDirectNode::method_set( intptr_t method ) {
16790 ((methodOper*)opnd_array(1))->_method = method;
16791}
16792
16793void CallDynamicJavaDirectNode::method_set( intptr_t method ) {
16794 ((methodOper*)opnd_array(1))->_method = method;
16795}
16796
16797void CallRuntimeDirectNode::method_set( intptr_t method ) {
16798 ((methodOper*)opnd_array(1))->_method = method;
16799}
16800
16801void CallLeafDirectNode::method_set( intptr_t method ) {
16802 ((methodOper*)opnd_array(1))->_method = method;
16803}
16804
16805void CallLeafDirectVectorNode::method_set( intptr_t method ) {
16806 ((methodOper*)opnd_array(1))->_method = method;
16807}
16808
16809void CallNativeDirectNode::method_set( intptr_t method ) {
16810 ((methodOper*)opnd_array(1))->_method = method;
16811}
16812
16813void CallLeafNoFPDirectNode::method_set( intptr_t method ) {
16814 ((methodOper*)opnd_array(1))->_method = method;
16815}
16816
16817int loadBNode::reloc() const {
16818 return 1;
16819}
16820
16821int loadB2LNode::reloc() const {
16822 return 1;
16823}
16824
16825int loadUBNode::reloc() const {
16826 return 1;
16827}
16828
16829int loadUB2LNode::reloc() const {
16830 return 1;
16831}
16832
16833int loadUB2L_immINode::reloc() const {
16834 return 1;
16835}
16836
16837int loadSNode::reloc() const {
16838 return 1;
16839}
16840
16841int loadS2BNode::reloc() const {
16842 return 1;
16843}
16844
16845int loadS2LNode::reloc() const {
16846 return 1;
16847}
16848
16849int loadUSNode::reloc() const {
16850 return 1;
16851}
16852
16853int loadUS2BNode::reloc() const {
16854 return 1;
16855}
16856
16857int loadUS2LNode::reloc() const {
16858 return 1;
16859}
16860
16861int loadUS2L_immI_255Node::reloc() const {
16862 return 1;
16863}
16864
16865int loadUS2L_immINode::reloc() const {
16866 return 1;
16867}
16868
16869int loadINode::reloc() const {
16870 return 1;
16871}
16872
16873int loadI2BNode::reloc() const {
16874 return 1;
16875}
16876
16877int loadI2UBNode::reloc() const {
16878 return 1;
16879}
16880
16881int loadI2SNode::reloc() const {
16882 return 1;
16883}
16884
16885int loadI2USNode::reloc() const {
16886 return 1;
16887}
16888
16889int loadI2LNode::reloc() const {
16890 return 1;
16891}
16892
16893int loadI2L_immI_255Node::reloc() const {
16894 return 1;
16895}
16896
16897int loadI2L_immI_65535Node::reloc() const {
16898 return 1;
16899}
16900
16901int loadI2L_immU31Node::reloc() const {
16902 return 1;
16903}
16904
16905int loadUI2LNode::reloc() const {
16906 return 1;
16907}
16908
16909int loadLNode::reloc() const {
16910 return 1;
16911}
16912
16913int loadRangeNode::reloc() const {
16914 return 1;
16915}
16916
16917int loadPNode::reloc() const {
16918 return 1;
16919}
16920
16921int loadNNode::reloc() const {
16922 return 1;
16923}
16924
16925int loadKlassNode::reloc() const {
16926 return 1;
16927}
16928
16929int loadNKlassNode::reloc() const {
16930 return 1;
16931}
16932
16933int loadFNode::reloc() const {
16934 return 1;
16935}
16936
16937int loadD_partialNode::reloc() const {
16938 return 1;
16939}
16940
16941int loadDNode::reloc() const {
16942 return 1;
16943}
16944
16945int loadConPNode::reloc() const {
16946 return 1;
16947}
16948
16949int loadConP0Node::reloc() const {
16950 return 1;
16951}
16952
16953int loadConP31Node::reloc() const {
16954 return 1;
16955}
16956
16957int loadConFNode::reloc() const {
16958 return 2;
16959}
16960
16961int loadConF0Node::reloc() const {
16962 return 2;
16963}
16964
16965int loadConDNode::reloc() const {
16966 return 2;
16967}
16968
16969int loadConD0Node::reloc() const {
16970 return 2;
16971}
16972
16973int prefetchAllocNode::reloc() const {
16974 return 1;
16975}
16976
16977int prefetchAllocNTANode::reloc() const {
16978 return 1;
16979}
16980
16981int prefetchAllocT0Node::reloc() const {
16982 return 1;
16983}
16984
16985int prefetchAllocT2Node::reloc() const {
16986 return 1;
16987}
16988
16989int storeBNode::reloc() const {
16990 return 2;
16991}
16992
16993int storeCNode::reloc() const {
16994 return 2;
16995}
16996
16997int storeINode::reloc() const {
16998 return 2;
16999}
17000
17001int storeLNode::reloc() const {
17002 return 2;
17003}
17004
17005int storePNode::reloc() const {
17006 return 2;
17007}
17008
17009int storeImmP0Node::reloc() const {
17010 return 3;
17011}
17012
17013int storeImmPNode::reloc() const {
17014 return 3;
17015}
17016
17017int storeNNode::reloc() const {
17018 return 2;
17019}
17020
17021int storeNKlassNode::reloc() const {
17022 return 2;
17023}
17024
17025int storeImmN0Node::reloc() const {
17026 return 2;
17027}
17028
17029int storeImmNNode::reloc() const {
17030 return 2;
17031}
17032
17033int storeImmNKlassNode::reloc() const {
17034 return 2;
17035}
17036
17037int storeImmI0Node::reloc() const {
17038 return 2;
17039}
17040
17041int storeImmINode::reloc() const {
17042 return 2;
17043}
17044
17045int storeImmL0Node::reloc() const {
17046 return 2;
17047}
17048
17049int storeImmLNode::reloc() const {
17050 return 2;
17051}
17052
17053int storeImmC0Node::reloc() const {
17054 return 2;
17055}
17056
17057int storeImmI16Node::reloc() const {
17058 return 2;
17059}
17060
17061int storeImmB0Node::reloc() const {
17062 return 2;
17063}
17064
17065int storeImmBNode::reloc() const {
17066 return 2;
17067}
17068
17069int storeImmCM0_regNode::reloc() const {
17070 return 2;
17071}
17072
17073int storeImmCM0Node::reloc() const {
17074 return 2;
17075}
17076
17077int storeFNode::reloc() const {
17078 return 2;
17079}
17080
17081int storeF0Node::reloc() const {
17082 return 3;
17083}
17084
17085int storeF_immNode::reloc() const {
17086 return 3;
17087}
17088
17089int storeDNode::reloc() const {
17090 return 2;
17091}
17092
17093int storeD0_immNode::reloc() const {
17094 return 3;
17095}
17096
17097int storeD0Node::reloc() const {
17098 return 3;
17099}
17100
17101int popCountI_memNode::reloc() const {
17102 return 1;
17103}
17104
17105int popCountL_memNode::reloc() const {
17106 return 1;
17107}
17108
17109int cmovI_memNode::reloc() const {
17110 return 1;
17111}
17112
17113int cmovI_memUNode::reloc() const {
17114 return 1;
17115}
17116
17117int cmovI_memUCFNode::reloc() const {
17118 return 1;
17119}
17120
17121int cmovL_memNode::reloc() const {
17122 return 1;
17123}
17124
17125int cmovL_memUNode::reloc() const {
17126 return 1;
17127}
17128
17129int cmovL_memUCFNode::reloc() const {
17130 return 1;
17131}
17132
17133int addI_rReg_memNode::reloc() const {
17134 return 1;
17135}
17136
17137int addI_rReg_mem_0Node::reloc() const {
17138 return 1;
17139}
17140
17141int addI_mem_rRegNode::reloc() const {
17142 return 3;
17143}
17144
17145int addI_mem_rReg_0Node::reloc() const {
17146 return 3;
17147}
17148
17149int addI_mem_immNode::reloc() const {
17150 return 3;
17151}
17152
17153int incI_memNode::reloc() const {
17154 return 3;
17155}
17156
17157int decI_memNode::reloc() const {
17158 return 3;
17159}
17160
17161int addL_rReg_memNode::reloc() const {
17162 return 1;
17163}
17164
17165int addL_rReg_mem_0Node::reloc() const {
17166 return 1;
17167}
17168
17169int addL_mem_rRegNode::reloc() const {
17170 return 3;
17171}
17172
17173int addL_mem_rReg_0Node::reloc() const {
17174 return 3;
17175}
17176
17177int addL_mem_immNode::reloc() const {
17178 return 3;
17179}
17180
17181int incL_memNode::reloc() const {
17182 return 3;
17183}
17184
17185int decL_memNode::reloc() const {
17186 return 3;
17187}
17188
17189int loadPLockedNode::reloc() const {
17190 return 1;
17191}
17192
17193int storePConditionalNode::reloc() const {
17194 return 1;
17195}
17196
17197int storeIConditionalNode::reloc() const {
17198 return 1;
17199}
17200
17201int storeLConditionalNode::reloc() const {
17202 return 1;
17203}
17204
17205int compareAndSwapPNode::reloc() const {
17206 return 1;
17207}
17208
17209int compareAndSwapP_0Node::reloc() const {
17210 return 1;
17211}
17212
17213int compareAndSwapLNode::reloc() const {
17214 return 1;
17215}
17216
17217int compareAndSwapL_0Node::reloc() const {
17218 return 1;
17219}
17220
17221int compareAndSwapINode::reloc() const {
17222 return 1;
17223}
17224
17225int compareAndSwapI_0Node::reloc() const {
17226 return 1;
17227}
17228
17229int compareAndSwapBNode::reloc() const {
17230 return 1;
17231}
17232
17233int compareAndSwapB_0Node::reloc() const {
17234 return 1;
17235}
17236
17237int compareAndSwapSNode::reloc() const {
17238 return 1;
17239}
17240
17241int compareAndSwapS_0Node::reloc() const {
17242 return 1;
17243}
17244
17245int compareAndSwapNNode::reloc() const {
17246 return 1;
17247}
17248
17249int compareAndSwapN_0Node::reloc() const {
17250 return 1;
17251}
17252
17253int compareAndExchangeBNode::reloc() const {
17254 return 1;
17255}
17256
17257int compareAndExchangeSNode::reloc() const {
17258 return 1;
17259}
17260
17261int compareAndExchangeINode::reloc() const {
17262 return 1;
17263}
17264
17265int compareAndExchangeLNode::reloc() const {
17266 return 1;
17267}
17268
17269int compareAndExchangeNNode::reloc() const {
17270 return 1;
17271}
17272
17273int compareAndExchangePNode::reloc() const {
17274 return 1;
17275}
17276
17277int xaddB_no_resNode::reloc() const {
17278 return 1;
17279}
17280
17281int xaddBNode::reloc() const {
17282 return 1;
17283}
17284
17285int xaddS_no_resNode::reloc() const {
17286 return 1;
17287}
17288
17289int xaddSNode::reloc() const {
17290 return 1;
17291}
17292
17293int xaddI_no_resNode::reloc() const {
17294 return 1;
17295}
17296
17297int xaddINode::reloc() const {
17298 return 1;
17299}
17300
17301int xaddL_no_resNode::reloc() const {
17302 return 1;
17303}
17304
17305int xaddLNode::reloc() const {
17306 return 1;
17307}
17308
17309int xchgBNode::reloc() const {
17310 return 1;
17311}
17312
17313int xchgSNode::reloc() const {
17314 return 1;
17315}
17316
17317int xchgINode::reloc() const {
17318 return 1;
17319}
17320
17321int xchgLNode::reloc() const {
17322 return 1;
17323}
17324
17325int xchgPNode::reloc() const {
17326 return 1;
17327}
17328
17329int xchgNNode::reloc() const {
17330 return 1;
17331}
17332
17333int subI_rReg_memNode::reloc() const {
17334 return 1;
17335}
17336
17337int subI_mem_rRegNode::reloc() const {
17338 return 3;
17339}
17340
17341int subI_mem_immNode::reloc() const {
17342 return 3;
17343}
17344
17345int subL_rReg_memNode::reloc() const {
17346 return 1;
17347}
17348
17349int subL_mem_rRegNode::reloc() const {
17350 return 3;
17351}
17352
17353int subL_mem_immNode::reloc() const {
17354 return 3;
17355}
17356
17357int negI_memNode::reloc() const {
17358 return 3;
17359}
17360
17361int negL_memNode::reloc() const {
17362 return 3;
17363}
17364
17365int mulI_memNode::reloc() const {
17366 return 1;
17367}
17368
17369int mulI_mem_0Node::reloc() const {
17370 return 1;
17371}
17372
17373int mulI_mem_immNode::reloc() const {
17374 return 1;
17375}
17376
17377int mulL_memNode::reloc() const {
17378 return 1;
17379}
17380
17381int mulL_mem_0Node::reloc() const {
17382 return 1;
17383}
17384
17385int mulL_mem_immNode::reloc() const {
17386 return 1;
17387}
17388
17389int salI_mem_1Node::reloc() const {
17390 return 3;
17391}
17392
17393int salI_mem_immNode::reloc() const {
17394 return 3;
17395}
17396
17397int salI_mem_CLNode::reloc() const {
17398 return 3;
17399}
17400
17401int sarI_mem_1Node::reloc() const {
17402 return 3;
17403}
17404
17405int sarI_mem_immNode::reloc() const {
17406 return 3;
17407}
17408
17409int sarI_mem_CLNode::reloc() const {
17410 return 3;
17411}
17412
17413int shrI_mem_1Node::reloc() const {
17414 return 3;
17415}
17416
17417int shrI_mem_immNode::reloc() const {
17418 return 3;
17419}
17420
17421int shrI_mem_CLNode::reloc() const {
17422 return 3;
17423}
17424
17425int salL_mem_1Node::reloc() const {
17426 return 3;
17427}
17428
17429int salL_mem_immNode::reloc() const {
17430 return 3;
17431}
17432
17433int salL_mem_CLNode::reloc() const {
17434 return 3;
17435}
17436
17437int sarL_mem_1Node::reloc() const {
17438 return 3;
17439}
17440
17441int sarL_mem_immNode::reloc() const {
17442 return 3;
17443}
17444
17445int sarL_mem_CLNode::reloc() const {
17446 return 3;
17447}
17448
17449int shrL_mem_1Node::reloc() const {
17450 return 3;
17451}
17452
17453int shrL_mem_immNode::reloc() const {
17454 return 3;
17455}
17456
17457int shrL_mem_CLNode::reloc() const {
17458 return 3;
17459}
17460
17461int andI_rReg_memNode::reloc() const {
17462 return 1;
17463}
17464
17465int andI_rReg_mem_0Node::reloc() const {
17466 return 1;
17467}
17468
17469int andB_mem_rRegNode::reloc() const {
17470 return 3;
17471}
17472
17473int andB_mem_rReg_0Node::reloc() const {
17474 return 3;
17475}
17476
17477int andI_mem_rRegNode::reloc() const {
17478 return 3;
17479}
17480
17481int andI_mem_rReg_0Node::reloc() const {
17482 return 3;
17483}
17484
17485int andI_mem_immNode::reloc() const {
17486 return 3;
17487}
17488
17489int andnI_rReg_rReg_memNode::reloc() const {
17490 return 1;
17491}
17492
17493int andnI_rReg_rReg_mem_0Node::reloc() const {
17494 return 1;
17495}
17496
17497int blsiI_rReg_memNode::reloc() const {
17498 return 2;
17499}
17500
17501int blsiI_rReg_mem_0Node::reloc() const {
17502 return 2;
17503}
17504
17505int blsmskI_rReg_memNode::reloc() const {
17506 return 2;
17507}
17508
17509int blsmskI_rReg_mem_0Node::reloc() const {
17510 return 2;
17511}
17512
17513int blsrI_rReg_memNode::reloc() const {
17514 return 2;
17515}
17516
17517int blsrI_rReg_mem_0Node::reloc() const {
17518 return 2;
17519}
17520
17521int orI_rReg_memNode::reloc() const {
17522 return 1;
17523}
17524
17525int orI_rReg_mem_0Node::reloc() const {
17526 return 1;
17527}
17528
17529int orB_mem_rRegNode::reloc() const {
17530 return 3;
17531}
17532
17533int orB_mem_rReg_0Node::reloc() const {
17534 return 3;
17535}
17536
17537int orI_mem_rRegNode::reloc() const {
17538 return 3;
17539}
17540
17541int orI_mem_rReg_0Node::reloc() const {
17542 return 3;
17543}
17544
17545int orI_mem_immNode::reloc() const {
17546 return 3;
17547}
17548
17549int xorI_rReg_memNode::reloc() const {
17550 return 1;
17551}
17552
17553int xorI_rReg_mem_0Node::reloc() const {
17554 return 1;
17555}
17556
17557int xorB_mem_rRegNode::reloc() const {
17558 return 3;
17559}
17560
17561int xorB_mem_rReg_0Node::reloc() const {
17562 return 3;
17563}
17564
17565int xorI_mem_rRegNode::reloc() const {
17566 return 3;
17567}
17568
17569int xorI_mem_rReg_0Node::reloc() const {
17570 return 3;
17571}
17572
17573int xorI_mem_immNode::reloc() const {
17574 return 3;
17575}
17576
17577int andL_rReg_memNode::reloc() const {
17578 return 1;
17579}
17580
17581int andL_rReg_mem_0Node::reloc() const {
17582 return 1;
17583}
17584
17585int andL_mem_rRegNode::reloc() const {
17586 return 3;
17587}
17588
17589int andL_mem_rReg_0Node::reloc() const {
17590 return 3;
17591}
17592
17593int andL_mem_immNode::reloc() const {
17594 return 3;
17595}
17596
17597int btrL_mem_immNode::reloc() const {
17598 return 3;
17599}
17600
17601int andnL_rReg_rReg_memNode::reloc() const {
17602 return 1;
17603}
17604
17605int andnL_rReg_rReg_mem_0Node::reloc() const {
17606 return 1;
17607}
17608
17609int blsiL_rReg_memNode::reloc() const {
17610 return 2;
17611}
17612
17613int blsiL_rReg_mem_0Node::reloc() const {
17614 return 2;
17615}
17616
17617int blsmskL_rReg_memNode::reloc() const {
17618 return 2;
17619}
17620
17621int blsmskL_rReg_mem_0Node::reloc() const {
17622 return 2;
17623}
17624
17625int blsrL_rReg_memNode::reloc() const {
17626 return 2;
17627}
17628
17629int blsrL_rReg_mem_0Node::reloc() const {
17630 return 2;
17631}
17632
17633int orL_rReg_memNode::reloc() const {
17634 return 1;
17635}
17636
17637int orL_rReg_mem_0Node::reloc() const {
17638 return 1;
17639}
17640
17641int orL_mem_rRegNode::reloc() const {
17642 return 3;
17643}
17644
17645int orL_mem_rReg_0Node::reloc() const {
17646 return 3;
17647}
17648
17649int orL_mem_immNode::reloc() const {
17650 return 3;
17651}
17652
17653int btsL_mem_immNode::reloc() const {
17654 return 3;
17655}
17656
17657int xorL_rReg_memNode::reloc() const {
17658 return 1;
17659}
17660
17661int xorL_rReg_mem_0Node::reloc() const {
17662 return 1;
17663}
17664
17665int xorL_mem_rRegNode::reloc() const {
17666 return 3;
17667}
17668
17669int xorL_mem_rReg_0Node::reloc() const {
17670 return 3;
17671}
17672
17673int xorL_mem_immNode::reloc() const {
17674 return 3;
17675}
17676
17677int cmpF_cc_memNode::reloc() const {
17678 return 1;
17679}
17680
17681int cmpF_cc_memCFNode::reloc() const {
17682 return 1;
17683}
17684
17685int cmpF_cc_immNode::reloc() const {
17686 return 1;
17687}
17688
17689int cmpF_cc_immCFNode::reloc() const {
17690 return 1;
17691}
17692
17693int cmpD_cc_memNode::reloc() const {
17694 return 1;
17695}
17696
17697int cmpD_cc_memCFNode::reloc() const {
17698 return 1;
17699}
17700
17701int cmpD_cc_immNode::reloc() const {
17702 return 1;
17703}
17704
17705int cmpD_cc_immCFNode::reloc() const {
17706 return 1;
17707}
17708
17709int cmpF_memNode::reloc() const {
17710 return 1;
17711}
17712
17713int cmpF_immNode::reloc() const {
17714 return 1;
17715}
17716
17717int cmpD_memNode::reloc() const {
17718 return 1;
17719}
17720
17721int cmpD_immNode::reloc() const {
17722 return 1;
17723}
17724
17725int convF2D_reg_memNode::reloc() const {
17726 return 1;
17727}
17728
17729int convD2F_reg_memNode::reloc() const {
17730 return 1;
17731}
17732
17733int convI2F_reg_memNode::reloc() const {
17734 return 1;
17735}
17736
17737int convI2D_reg_memNode::reloc() const {
17738 return 1;
17739}
17740
17741int convL2F_reg_memNode::reloc() const {
17742 return 1;
17743}
17744
17745int convL2D_reg_memNode::reloc() const {
17746 return 1;
17747}
17748
17749int convI2L_reg_mem_zexNode::reloc() const {
17750 return 1;
17751}
17752
17753int compI_rReg_memNode::reloc() const {
17754 return 1;
17755}
17756
17757int testI_reg_memNode::reloc() const {
17758 return 1;
17759}
17760
17761int testI_reg_mem_0Node::reloc() const {
17762 return 1;
17763}
17764
17765int compU_rReg_memNode::reloc() const {
17766 return 1;
17767}
17768
17769int compP_rReg_memNode::reloc() const {
17770 return 1;
17771}
17772
17773int compP_mem_rRegNode::reloc() const {
17774 return 1;
17775}
17776
17777int testP_regNode::reloc() const {
17778 return 1;
17779}
17780
17781int testP_memNode::reloc() const {
17782 return 2;
17783}
17784
17785int testP_mem_reg0Node::reloc() const {
17786 return 2;
17787}
17788
17789int compN_rReg_memNode::reloc() const {
17790 return 1;
17791}
17792
17793int compN_mem_immNode::reloc() const {
17794 return 1;
17795}
17796
17797int compN_mem_imm_klassNode::reloc() const {
17798 return 1;
17799}
17800
17801int testN_memNode::reloc() const {
17802 return 1;
17803}
17804
17805int testN_mem_reg0Node::reloc() const {
17806 return 1;
17807}
17808
17809int compL_rReg_memNode::reloc() const {
17810 return 1;
17811}
17812
17813int testL_reg_memNode::reloc() const {
17814 return 1;
17815}
17816
17817int testL_reg_mem_0Node::reloc() const {
17818 return 1;
17819}
17820
17821int testL_reg_mem2Node::reloc() const {
17822 return 1;
17823}
17824
17825int testL_reg_mem2_0Node::reloc() const {
17826 return 1;
17827}
17828
17829int compUL_rReg_memNode::reloc() const {
17830 return 1;
17831}
17832
17833int compB_mem_immNode::reloc() const {
17834 return 1;
17835}
17836
17837int testUB_mem_immNode::reloc() const {
17838 return 1;
17839}
17840
17841int testB_mem_immNode::reloc() const {
17842 return 1;
17843}
17844
17845int partialSubtypeCheck_vs_ZeroNode::reloc() const {
17846 return 1;
17847}
17848
17849int safePoint_poll_tlsNode::reloc() const {
17850 return 1;
17851}
17852
17853int CallStaticJavaDirectNode::reloc() const {
17854 return 1;
17855}
17856
17857int CallDynamicJavaDirectNode::reloc() const {
17858 return 1;
17859}
17860
17861int CallRuntimeDirectNode::reloc() const {
17862 return 1;
17863}
17864
17865int CallLeafDirectNode::reloc() const {
17866 return 1;
17867}
17868
17869int CallLeafDirectVectorNode::reloc() const {
17870 return 1;
17871}
17872
17873int CallNativeDirectNode::reloc() const {
17874 return 1;
17875}
17876
17877int CallLeafNoFPDirectNode::reloc() const {
17878 return 1;
17879}
17880
17881int RetNode::reloc() const {
17882 return 1;
17883}
17884
17885int TailCalljmpIndNode::reloc() const {
17886 return 1;
17887}
17888
17889int tailjmpIndNode::reloc() const {
17890 return 1;
17891}
17892
17893int RethrowExceptionNode::reloc() const {
17894 return 1;
17895}
17896
17897int addF_memNode::reloc() const {
17898 return 1;
17899}
17900
17901int addF_mem_0Node::reloc() const {
17902 return 1;
17903}
17904
17905int addF_immNode::reloc() const {
17906 return 1;
17907}
17908
17909int addF_reg_memNode::reloc() const {
17910 return 1;
17911}
17912
17913int addF_reg_mem_0Node::reloc() const {
17914 return 1;
17915}
17916
17917int addF_reg_immNode::reloc() const {
17918 return 1;
17919}
17920
17921int addD_memNode::reloc() const {
17922 return 1;
17923}
17924
17925int addD_mem_0Node::reloc() const {
17926 return 1;
17927}
17928
17929int addD_immNode::reloc() const {
17930 return 1;
17931}
17932
17933int addD_reg_memNode::reloc() const {
17934 return 1;
17935}
17936
17937int addD_reg_mem_0Node::reloc() const {
17938 return 1;
17939}
17940
17941int addD_reg_immNode::reloc() const {
17942 return 1;
17943}
17944
17945int subF_memNode::reloc() const {
17946 return 1;
17947}
17948
17949int subF_immNode::reloc() const {
17950 return 1;
17951}
17952
17953int subF_reg_memNode::reloc() const {
17954 return 1;
17955}
17956
17957int subF_reg_immNode::reloc() const {
17958 return 1;
17959}
17960
17961int subD_memNode::reloc() const {
17962 return 1;
17963}
17964
17965int subD_immNode::reloc() const {
17966 return 1;
17967}
17968
17969int subD_reg_memNode::reloc() const {
17970 return 1;
17971}
17972
17973int subD_reg_immNode::reloc() const {
17974 return 1;
17975}
17976
17977int mulF_memNode::reloc() const {
17978 return 1;
17979}
17980
17981int mulF_mem_0Node::reloc() const {
17982 return 1;
17983}
17984
17985int mulF_immNode::reloc() const {
17986 return 1;
17987}
17988
17989int mulF_reg_memNode::reloc() const {
17990 return 1;
17991}
17992
17993int mulF_reg_mem_0Node::reloc() const {
17994 return 1;
17995}
17996
17997int mulF_reg_immNode::reloc() const {
17998 return 1;
17999}
18000
18001int mulD_memNode::reloc() const {
18002 return 1;
18003}
18004
18005int mulD_mem_0Node::reloc() const {
18006 return 1;
18007}
18008
18009int mulD_immNode::reloc() const {
18010 return 1;
18011}
18012
18013int mulD_reg_memNode::reloc() const {
18014 return 1;
18015}
18016
18017int mulD_reg_mem_0Node::reloc() const {
18018 return 1;
18019}
18020
18021int mulD_reg_immNode::reloc() const {
18022 return 1;
18023}
18024
18025int divF_memNode::reloc() const {
18026 return 1;
18027}
18028
18029int divF_immNode::reloc() const {
18030 return 1;
18031}
18032
18033int divF_reg_memNode::reloc() const {
18034 return 1;
18035}
18036
18037int divF_reg_immNode::reloc() const {
18038 return 1;
18039}
18040
18041int divD_memNode::reloc() const {
18042 return 1;
18043}
18044
18045int divD_immNode::reloc() const {
18046 return 1;
18047}
18048
18049int divD_reg_memNode::reloc() const {
18050 return 1;
18051}
18052
18053int divD_reg_immNode::reloc() const {
18054 return 1;
18055}
18056
18057int roundD_memNode::reloc() const {
18058 return 1;
18059}
18060
18061int roundD_immNode::reloc() const {
18062 return 1;
18063}
18064
18065int vroundD_memNode::reloc() const {
18066 return 1;
18067}
18068
18069int vround8D_memNode::reloc() const {
18070 return 1;
18071}
18072
18073int loadVNode::reloc() const {
18074 return 1;
18075}
18076
18077int storeVNode::reloc() const {
18078 return 2;
18079}
18080
18081int gatherNode::reloc() const {
18082 return 1;
18083}
18084
18085int evgatherNode::reloc() const {
18086 return 1;
18087}
18088
18089int evgather_maskedNode::reloc() const {
18090 return 1;
18091}
18092
18093int scatterNode::reloc() const {
18094 return 2;
18095}
18096
18097int scatter_maskedNode::reloc() const {
18098 return 2;
18099}
18100
18101int ReplB_memNode::reloc() const {
18102 return 1;
18103}
18104
18105int ReplS_memNode::reloc() const {
18106 return 1;
18107}
18108
18109int ReplI_memNode::reloc() const {
18110 return 1;
18111}
18112
18113int ReplL_memNode::reloc() const {
18114 return 1;
18115}
18116
18117int ReplF_memNode::reloc() const {
18118 return 1;
18119}
18120
18121int ReplF_zeroNode::reloc() const {
18122 return 1;
18123}
18124
18125int ReplD_memNode::reloc() const {
18126 return 1;
18127}
18128
18129int ReplD_zeroNode::reloc() const {
18130 return 1;
18131}
18132
18133int minmax_reduction2FNode::reloc() const {
18134 return 1;
18135}
18136
18137int minmax_reduction2F_0Node::reloc() const {
18138 return 1;
18139}
18140
18141int minmax_reductionFNode::reloc() const {
18142 return 1;
18143}
18144
18145int minmax_reductionF_0Node::reloc() const {
18146 return 1;
18147}
18148
18149int minmax_reduction2DNode::reloc() const {
18150 return 1;
18151}
18152
18153int minmax_reduction2D_0Node::reloc() const {
18154 return 1;
18155}
18156
18157int minmax_reductionDNode::reloc() const {
18158 return 1;
18159}
18160
18161int minmax_reductionD_0Node::reloc() const {
18162 return 1;
18163}
18164
18165int vaddB_memNode::reloc() const {
18166 return 1;
18167}
18168
18169int vaddB_mem_0Node::reloc() const {
18170 return 1;
18171}
18172
18173int vaddS_memNode::reloc() const {
18174 return 1;
18175}
18176
18177int vaddS_mem_0Node::reloc() const {
18178 return 1;
18179}
18180
18181int vaddI_memNode::reloc() const {
18182 return 1;
18183}
18184
18185int vaddI_mem_0Node::reloc() const {
18186 return 1;
18187}
18188
18189int vaddL_memNode::reloc() const {
18190 return 1;
18191}
18192
18193int vaddL_mem_0Node::reloc() const {
18194 return 1;
18195}
18196
18197int vaddF_memNode::reloc() const {
18198 return 1;
18199}
18200
18201int vaddF_mem_0Node::reloc() const {
18202 return 1;
18203}
18204
18205int vaddD_memNode::reloc() const {
18206 return 1;
18207}
18208
18209int vaddD_mem_0Node::reloc() const {
18210 return 1;
18211}
18212
18213int vsubB_memNode::reloc() const {
18214 return 1;
18215}
18216
18217int vsubS_memNode::reloc() const {
18218 return 1;
18219}
18220
18221int vsubI_memNode::reloc() const {
18222 return 1;
18223}
18224
18225int vsubL_memNode::reloc() const {
18226 return 1;
18227}
18228
18229int vsubF_memNode::reloc() const {
18230 return 1;
18231}
18232
18233int vsubD_memNode::reloc() const {
18234 return 1;
18235}
18236
18237int vmulS_memNode::reloc() const {
18238 return 1;
18239}
18240
18241int vmulS_mem_0Node::reloc() const {
18242 return 1;
18243}
18244
18245int vmulI_memNode::reloc() const {
18246 return 1;
18247}
18248
18249int vmulI_mem_0Node::reloc() const {
18250 return 1;
18251}
18252
18253int vmulL_memNode::reloc() const {
18254 return 1;
18255}
18256
18257int vmulL_mem_0Node::reloc() const {
18258 return 1;
18259}
18260
18261int vmulF_memNode::reloc() const {
18262 return 1;
18263}
18264
18265int vmulF_mem_0Node::reloc() const {
18266 return 1;
18267}
18268
18269int vmulD_memNode::reloc() const {
18270 return 1;
18271}
18272
18273int vmulD_mem_0Node::reloc() const {
18274 return 1;
18275}
18276
18277int vdivF_memNode::reloc() const {
18278 return 1;
18279}
18280
18281int vdivD_memNode::reloc() const {
18282 return 1;
18283}
18284
18285int copySignD_immNode::reloc() const {
18286 return 1;
18287}
18288
18289int vsqrtF_memNode::reloc() const {
18290 return 1;
18291}
18292
18293int vsqrtD_memNode::reloc() const {
18294 return 1;
18295}
18296
18297int vand_memNode::reloc() const {
18298 return 1;
18299}
18300
18301int vand_mem_0Node::reloc() const {
18302 return 1;
18303}
18304
18305int vor_memNode::reloc() const {
18306 return 1;
18307}
18308
18309int vor_mem_0Node::reloc() const {
18310 return 1;
18311}
18312
18313int vxor_memNode::reloc() const {
18314 return 1;
18315}
18316
18317int vxor_mem_0Node::reloc() const {
18318 return 1;
18319}
18320
18321int vfmaF_memNode::reloc() const {
18322 return 1;
18323}
18324
18325int vfmaD_memNode::reloc() const {
18326 return 1;
18327}
18328
18329int vpternlog_memNode::reloc() const {
18330 return 1;
18331}
18332
18333int vmasked_load64Node::reloc() const {
18334 return 1;
18335}
18336
18337int vmasked_store64Node::reloc() const {
18338 return 2;
18339}
18340
18341int vadd_mem_maskedNode::reloc() const {
18342 return 1;
18343}
18344
18345int vadd_mem_masked_0Node::reloc() const {
18346 return 1;
18347}
18348
18349int vadd_mem_masked_1Node::reloc() const {
18350 return 1;
18351}
18352
18353int vadd_mem_masked_2Node::reloc() const {
18354 return 1;
18355}
18356
18357int vadd_mem_masked_3Node::reloc() const {
18358 return 1;
18359}
18360
18361int vadd_mem_masked_4Node::reloc() const {
18362 return 1;
18363}
18364
18365int vxor_mem_maskedNode::reloc() const {
18366 return 1;
18367}
18368
18369int vor_mem_maskedNode::reloc() const {
18370 return 1;
18371}
18372
18373int vand_mem_maskedNode::reloc() const {
18374 return 1;
18375}
18376
18377int vsub_mem_maskedNode::reloc() const {
18378 return 1;
18379}
18380
18381int vsub_mem_masked_0Node::reloc() const {
18382 return 1;
18383}
18384
18385int vsub_mem_masked_1Node::reloc() const {
18386 return 1;
18387}
18388
18389int vsub_mem_masked_2Node::reloc() const {
18390 return 1;
18391}
18392
18393int vsub_mem_masked_3Node::reloc() const {
18394 return 1;
18395}
18396
18397int vsub_mem_masked_4Node::reloc() const {
18398 return 1;
18399}
18400
18401int vmul_mem_maskedNode::reloc() const {
18402 return 1;
18403}
18404
18405int vmul_mem_masked_0Node::reloc() const {
18406 return 1;
18407}
18408
18409int vmul_mem_masked_1Node::reloc() const {
18410 return 1;
18411}
18412
18413int vmul_mem_masked_2Node::reloc() const {
18414 return 1;
18415}
18416
18417int vmul_mem_masked_3Node::reloc() const {
18418 return 1;
18419}
18420
18421int vdiv_mem_maskedNode::reloc() const {
18422 return 1;
18423}
18424
18425int vdiv_mem_masked_0Node::reloc() const {
18426 return 1;
18427}
18428
18429int vlshift_mem_maskedNode::reloc() const {
18430 return 1;
18431}
18432
18433int vlshift_mem_masked_0Node::reloc() const {
18434 return 1;
18435}
18436
18437int vlshift_mem_masked_1Node::reloc() const {
18438 return 1;
18439}
18440
18441int vrshift_mem_maskedNode::reloc() const {
18442 return 1;
18443}
18444
18445int vrshift_mem_masked_0Node::reloc() const {
18446 return 1;
18447}
18448
18449int vrshift_mem_masked_1Node::reloc() const {
18450 return 1;
18451}
18452
18453int vurshift_mem_maskedNode::reloc() const {
18454 return 1;
18455}
18456
18457int vurshift_mem_masked_0Node::reloc() const {
18458 return 1;
18459}
18460
18461int vurshift_mem_masked_1Node::reloc() const {
18462 return 1;
18463}
18464
18465int vmaxv_mem_maskedNode::reloc() const {
18466 return 1;
18467}
18468
18469int vminv_mem_maskedNode::reloc() const {
18470 return 1;
18471}
18472
18473int vfma_mem_maskedNode::reloc() const {
18474 return 1;
18475}
18476
18477int vfma_mem_masked_0Node::reloc() const {
18478 return 1;
18479}
18480
18481int compareAndSwapP_shenandoahNode::reloc() const {
18482 return 1;
18483}
18484
18485int compareAndSwapP_shenandoah_0Node::reloc() const {
18486 return 1;
18487}
18488
18489int compareAndSwapN_shenandoahNode::reloc() const {
18490 return 1;
18491}
18492
18493int compareAndSwapN_shenandoah_0Node::reloc() const {
18494 return 1;
18495}
18496
18497int compareAndExchangeN_shenandoahNode::reloc() const {
18498 return 1;
18499}
18500
18501int compareAndExchangeP_shenandoahNode::reloc() const {
18502 return 1;
18503}
18504
18505int zLoadPNode::reloc() const {
18506 return 1;
18507}
18508
18509int zCompareAndExchangePNode::reloc() const {
18510 return 1;
18511}
18512
18513int zCompareAndSwapPNode::reloc() const {
18514 return 1;
18515}
18516
18517int zCompareAndSwapP_0Node::reloc() const {
18518 return 1;
18519}
18520
18521int zXChgPNode::reloc() const {
18522 return 1;
18523}
18524
18525
18526void MoveF2VLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
18527 cbuf.set_insts_mark();
18528 // Start at oper_input_base() and count operands
18529 unsigned idx0 = 1;
18530 unsigned idx1 = 1; // src
18531 {
18532 C2_MacroAssembler _masm(&cbuf);
18533
18534#line 4828 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
18535
18536 ShouldNotReachHere()do { (*g_assert_poison) = 'X';; report_should_not_reach_here(
"/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 4829); ::breakpoint(); } while (0);
18537
18538#line 18538 "ad_x86.cpp"
18539 }
18540}
18541
18542void MoveF2LEGNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
18543 cbuf.set_insts_mark();
18544 // Start at oper_input_base() and count operands
18545 unsigned idx0 = 1;
18546 unsigned idx1 = 1; // src
18547 {
18548 C2_MacroAssembler _masm(&cbuf);
18549
18550#line 4838 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
18551
18552 ShouldNotReachHere()do { (*g_assert_poison) = 'X';; report_should_not_reach_here(
"/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 4839); ::breakpoint(); } while (0);
18553
18554#line 18554 "ad_x86.cpp"
18555 }
18556}
18557
18558void MoveVL2FNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
18559 cbuf.set_insts_mark();
18560 // Start at oper_input_base() and count operands
18561 unsigned idx0 = 1;
18562 unsigned idx1 = 1; // src
18563 {
18564 C2_MacroAssembler _masm(&cbuf);
18565
18566#line 4848 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
18567
18568 ShouldNotReachHere()do { (*g_assert_poison) = 'X';; report_should_not_reach_here(
"/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 4849); ::breakpoint(); } while (0);
18569
18570#line 18570 "ad_x86.cpp"
18571 }
18572}
18573
18574void MoveLEG2FNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
18575 cbuf.set_insts_mark();
18576 // Start at oper_input_base() and count operands
18577 unsigned idx0 = 1;
18578 unsigned idx1 = 1; // src
18579 {
18580 C2_MacroAssembler _masm(&cbuf);
18581
18582#line 4858 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
18583
18584 ShouldNotReachHere()do { (*g_assert_poison) = 'X';; report_should_not_reach_here(
"/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 4859); ::breakpoint(); } while (0);
18585
18586#line 18586 "ad_x86.cpp"
18587 }
18588}
18589
18590void MoveD2VLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
18591 cbuf.set_insts_mark();
18592 // Start at oper_input_base() and count operands
18593 unsigned idx0 = 1;
18594 unsigned idx1 = 1; // src
18595 {
18596 C2_MacroAssembler _masm(&cbuf);
18597
18598#line 4868 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
18599
18600 ShouldNotReachHere()do { (*g_assert_poison) = 'X';; report_should_not_reach_here(
"/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 4869); ::breakpoint(); } while (0);
18601
18602#line 18602 "ad_x86.cpp"
18603 }
18604}
18605
18606void MoveD2LEGNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
18607 cbuf.set_insts_mark();
18608 // Start at oper_input_base() and count operands
18609 unsigned idx0 = 1;
18610 unsigned idx1 = 1; // src
18611 {
18612 C2_MacroAssembler _masm(&cbuf);
18613
18614#line 4878 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
18615
18616 ShouldNotReachHere()do { (*g_assert_poison) = 'X';; report_should_not_reach_here(
"/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 4879); ::breakpoint(); } while (0);
18617
18618#line 18618 "ad_x86.cpp"
18619 }
18620}
18621
18622void MoveVL2DNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
18623 cbuf.set_insts_mark();
18624 // Start at oper_input_base() and count operands
18625 unsigned idx0 = 1;
18626 unsigned idx1 = 1; // src
18627 {
18628 C2_MacroAssembler _masm(&cbuf);
18629
18630#line 4888 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
18631
18632 ShouldNotReachHere()do { (*g_assert_poison) = 'X';; report_should_not_reach_here(
"/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 4889); ::breakpoint(); } while (0);
18633
18634#line 18634 "ad_x86.cpp"
18635 }
18636}
18637
18638void MoveLEG2DNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
18639 cbuf.set_insts_mark();
18640 // Start at oper_input_base() and count operands
18641 unsigned idx0 = 1;
18642 unsigned idx1 = 1; // src
18643 {
18644 C2_MacroAssembler _masm(&cbuf);
18645
18646#line 4898 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
18647
18648 ShouldNotReachHere()do { (*g_assert_poison) = 'X';; report_should_not_reach_here(
"/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 4899); ::breakpoint(); } while (0);
18649
18650#line 18650 "ad_x86.cpp"
18651 }
18652}
18653
18654void loadBNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
18655 cbuf.set_insts_mark();
18656 // Start at oper_input_base() and count operands
18657 unsigned idx0 = 2;
18658 unsigned idx1 = 2; // mem
18659 {
18660 C2_MacroAssembler _masm(&cbuf);
18661
18662#line 4915 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
18663
18664 ___masm. movsbl(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
18665
18666#line 18666 "ad_x86.cpp"
18667 }
18668}
18669
18670void loadB2LNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
18671 cbuf.set_insts_mark();
18672 // Start at oper_input_base() and count operands
18673 unsigned idx0 = 2;
18674 unsigned idx1 = 2; // mem
18675 {
18676 C2_MacroAssembler _masm(&cbuf);
18677
18678#line 4930 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
18679
18680 ___masm. movsbq(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
18681
18682#line 18682 "ad_x86.cpp"
18683 }
18684}
18685
18686void loadUBNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
18687 cbuf.set_insts_mark();
18688 // Start at oper_input_base() and count operands
18689 unsigned idx0 = 2;
18690 unsigned idx1 = 2; // mem
18691 {
18692 C2_MacroAssembler _masm(&cbuf);
18693
18694#line 4945 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
18695
18696 ___masm. movzbl(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
18697
18698#line 18698 "ad_x86.cpp"
18699 }
18700}
18701
18702void loadUB2LNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
18703 cbuf.set_insts_mark();
18704 // Start at oper_input_base() and count operands
18705 unsigned idx0 = 2;
18706 unsigned idx1 = 2; // mem
18707 {
18708 C2_MacroAssembler _masm(&cbuf);
18709
18710#line 4960 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
18711
18712 ___masm. movzbq(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
18713
18714#line 18714 "ad_x86.cpp"
18715 }
18716}
18717
18718void loadUB2L_immINode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
18719 cbuf.set_insts_mark();
18720 // Start at oper_input_base() and count operands
18721 unsigned idx0 = 2;
18722 unsigned idx1 = 2; // mem
18723 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask
18724 {
18725 C2_MacroAssembler _masm(&cbuf);
18726
18727#line 4974 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
18728
18729 Register Rdst = opnd_array(0)->as_Register(ra_,this)/* dst */;
18730 ___masm. movzbq(Rdst, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
18731 ___masm. andl(Rdst, opnd_array(2)->constant()& right_n_bits(8)((((8) >= BitsPerWord) ? 0 : (OneBit << (8))) - 1));
18732
18733#line 18733 "ad_x86.cpp"
18734 }
18735}
18736
18737void loadSNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
18738 cbuf.set_insts_mark();
18739 // Start at oper_input_base() and count operands
18740 unsigned idx0 = 2;
18741 unsigned idx1 = 2; // mem
18742 {
18743 C2_MacroAssembler _masm(&cbuf);
18744
18745#line 4990 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
18746
18747 ___masm. movswl(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
18748
18749#line 18749 "ad_x86.cpp"
18750 }
18751}
18752
18753void loadS2BNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
18754 cbuf.set_insts_mark();
18755 // Start at oper_input_base() and count operands
18756 unsigned idx0 = 2;
18757 unsigned idx1 = 2; // mem
18758 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // twentyfour
18759 {
18760 C2_MacroAssembler _masm(&cbuf);
18761
18762#line 5003 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
18763
18764 ___masm. movsbl(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
18765
18766#line 18766 "ad_x86.cpp"
18767 }
18768}
18769
18770void loadS2LNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
18771 cbuf.set_insts_mark();
18772 // Start at oper_input_base() and count operands
18773 unsigned idx0 = 2;
18774 unsigned idx1 = 2; // mem
18775 {
18776 C2_MacroAssembler _masm(&cbuf);
18777
18778#line 5017 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
18779
18780 ___masm. movswq(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
18781
18782#line 18782 "ad_x86.cpp"
18783 }
18784}
18785
18786void loadUSNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
18787 cbuf.set_insts_mark();
18788 // Start at oper_input_base() and count operands
18789 unsigned idx0 = 2;
18790 unsigned idx1 = 2; // mem
18791 {
18792 C2_MacroAssembler _masm(&cbuf);
18793
18794#line 5032 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
18795
18796 ___masm. movzwl(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
18797
18798#line 18798 "ad_x86.cpp"
18799 }
18800}
18801
18802void loadUS2BNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
18803 cbuf.set_insts_mark();
18804 // Start at oper_input_base() and count operands
18805 unsigned idx0 = 2;
18806 unsigned idx1 = 2; // mem
18807 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // twentyfour
18808 {
18809 C2_MacroAssembler _masm(&cbuf);
18810
18811#line 5045 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
18812
18813 ___masm. movsbl(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
18814
18815#line 18815 "ad_x86.cpp"
18816 }
18817}
18818
18819void loadUS2LNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
18820 cbuf.set_insts_mark();
18821 // Start at oper_input_base() and count operands
18822 unsigned idx0 = 2;
18823 unsigned idx1 = 2; // mem
18824 {
18825 C2_MacroAssembler _masm(&cbuf);
18826
18827#line 5059 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
18828
18829 ___masm. movzwq(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
18830
18831#line 18831 "ad_x86.cpp"
18832 }
18833}
18834
18835void loadUS2L_immI_255Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
18836 cbuf.set_insts_mark();
18837 // Start at oper_input_base() and count operands
18838 unsigned idx0 = 2;
18839 unsigned idx1 = 2; // mem
18840 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask
18841 {
18842 C2_MacroAssembler _masm(&cbuf);
18843
18844#line 5071 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
18845
18846 ___masm. movzbq(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
18847
18848#line 18848 "ad_x86.cpp"
18849 }
18850}
18851
18852void loadUS2L_immINode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
18853 cbuf.set_insts_mark();
18854 // Start at oper_input_base() and count operands
18855 unsigned idx0 = 2;
18856 unsigned idx1 = 2; // mem
18857 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask
18858 {
18859 C2_MacroAssembler _masm(&cbuf);
18860
18861#line 5084 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
18862
18863 Register Rdst = opnd_array(0)->as_Register(ra_,this)/* dst */;
18864 ___masm. movzwq(Rdst, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
18865 ___masm. andl(Rdst, opnd_array(2)->constant()& right_n_bits(16)((((16) >= BitsPerWord) ? 0 : (OneBit << (16))) - 1));
18866
18867#line 18867 "ad_x86.cpp"
18868 }
18869}
18870
18871void loadINode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
18872 cbuf.set_insts_mark();
18873 // Start at oper_input_base() and count operands
18874 unsigned idx0 = 2;
18875 unsigned idx1 = 2; // mem
18876 {
18877 C2_MacroAssembler _masm(&cbuf);
18878
18879#line 5100 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
18880
18881 ___masm. movl(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
18882
18883#line 18883 "ad_x86.cpp"
18884 }
18885}
18886
18887void loadI2BNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
18888 cbuf.set_insts_mark();
18889 // Start at oper_input_base() and count operands
18890 unsigned idx0 = 2;
18891 unsigned idx1 = 2; // mem
18892 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // twentyfour
18893 {
18894 C2_MacroAssembler _masm(&cbuf);
18895
18896#line 5113 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
18897
18898 ___masm. movsbl(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
18899
18900#line 18900 "ad_x86.cpp"
18901 }
18902}
18903
18904void loadI2UBNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
18905 cbuf.set_insts_mark();
18906 // Start at oper_input_base() and count operands
18907 unsigned idx0 = 2;
18908 unsigned idx1 = 2; // mem
18909 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask
18910 {
18911 C2_MacroAssembler _masm(&cbuf);
18912
18913#line 5125 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
18914
18915 ___masm. movzbl(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
18916
18917#line 18917 "ad_x86.cpp"
18918 }
18919}
18920
18921void loadI2SNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
18922 cbuf.set_insts_mark();
18923 // Start at oper_input_base() and count operands
18924 unsigned idx0 = 2;
18925 unsigned idx1 = 2; // mem
18926 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // sixteen
18927 {
18928 C2_MacroAssembler _masm(&cbuf);
18929
18930#line 5137 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
18931
18932 ___masm. movswl(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
18933
18934#line 18934 "ad_x86.cpp"
18935 }
18936}
18937
18938void loadI2USNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
18939 cbuf.set_insts_mark();
18940 // Start at oper_input_base() and count operands
18941 unsigned idx0 = 2;
18942 unsigned idx1 = 2; // mem
18943 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask
18944 {
18945 C2_MacroAssembler _masm(&cbuf);
18946
18947#line 5149 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
18948
18949 ___masm. movzwl(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
18950
18951#line 18951 "ad_x86.cpp"
18952 }
18953}
18954
18955void loadI2LNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
18956 cbuf.set_insts_mark();
18957 // Start at oper_input_base() and count operands
18958 unsigned idx0 = 2;
18959 unsigned idx1 = 2; // mem
18960 {
18961 C2_MacroAssembler _masm(&cbuf);
18962
18963#line 5163 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
18964
18965 ___masm. movslq(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
18966
18967#line 18967 "ad_x86.cpp"
18968 }
18969}
18970
18971void loadI2L_immI_255Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
18972 cbuf.set_insts_mark();
18973 // Start at oper_input_base() and count operands
18974 unsigned idx0 = 2;
18975 unsigned idx1 = 2; // mem
18976 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask
18977 {
18978 C2_MacroAssembler _masm(&cbuf);
18979
18980#line 5175 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
18981
18982 ___masm. movzbq(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
18983
18984#line 18984 "ad_x86.cpp"
18985 }
18986}
18987
18988void loadI2L_immI_65535Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
18989 cbuf.set_insts_mark();
18990 // Start at oper_input_base() and count operands
18991 unsigned idx0 = 2;
18992 unsigned idx1 = 2; // mem
18993 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask
18994 {
18995 C2_MacroAssembler _masm(&cbuf);
18996
18997#line 5186 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
18998
18999 ___masm. movzwq(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
19000
19001#line 19001 "ad_x86.cpp"
19002 }
19003}
19004
19005void loadI2L_immU31Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19006 cbuf.set_insts_mark();
19007 // Start at oper_input_base() and count operands
19008 unsigned idx0 = 2;
19009 unsigned idx1 = 2; // mem
19010 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask
19011 {
19012 C2_MacroAssembler _masm(&cbuf);
19013
19014#line 5199 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
19015
19016 Register Rdst = opnd_array(0)->as_Register(ra_,this)/* dst */;
19017 ___masm. movl(Rdst, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
19018 ___masm. andl(Rdst, opnd_array(2)->constant());
19019
19020#line 19020 "ad_x86.cpp"
19021 }
19022}
19023
19024void loadUI2LNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19025 cbuf.set_insts_mark();
19026 // Start at oper_input_base() and count operands
19027 unsigned idx0 = 2;
19028 unsigned idx1 = 2; // mem
19029 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask
19030 {
19031 C2_MacroAssembler _masm(&cbuf);
19032
19033#line 5215 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
19034
19035 ___masm. movl(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
19036
19037#line 19037 "ad_x86.cpp"
19038 }
19039}
19040
19041void loadLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19042 cbuf.set_insts_mark();
19043 // Start at oper_input_base() and count operands
19044 unsigned idx0 = 2;
19045 unsigned idx1 = 2; // mem
19046 {
19047 C2_MacroAssembler _masm(&cbuf);
19048
19049#line 5230 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
19050
19051 ___masm. movq(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
19052
19053#line 19053 "ad_x86.cpp"
19054 }
19055}
19056
19057void loadRangeNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19058 cbuf.set_insts_mark();
19059 // Start at oper_input_base() and count operands
19060 unsigned idx0 = 2;
19061 unsigned idx1 = 2; // mem
19062 {
19063 C2_MacroAssembler _masm(&cbuf);
19064
19065#line 5244 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
19066
19067 ___masm. movl(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
19068
19069#line 19069 "ad_x86.cpp"
19070 }
19071}
19072
19073void loadPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19074 cbuf.set_insts_mark();
19075 // Start at oper_input_base() and count operands
19076 unsigned idx0 = 2;
19077 unsigned idx1 = 2; // mem
19078 {
19079 C2_MacroAssembler _masm(&cbuf);
19080
19081#line 5258 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
19082
19083 ___masm. movq(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
19084
19085#line 19085 "ad_x86.cpp"
19086 }
19087}
19088
19089void loadNNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19090 cbuf.set_insts_mark();
19091 // Start at oper_input_base() and count operands
19092 unsigned idx0 = 2;
19093 unsigned idx1 = 2; // mem
19094 {
19095 C2_MacroAssembler _masm(&cbuf);
19096
19097#line 5271 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
19098
19099 ___masm. movl(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
19100
19101#line 19101 "ad_x86.cpp"
19102 }
19103}
19104
19105void loadKlassNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19106 cbuf.set_insts_mark();
19107 // Start at oper_input_base() and count operands
19108 unsigned idx0 = 2;
19109 unsigned idx1 = 2; // mem
19110 {
19111 C2_MacroAssembler _masm(&cbuf);
19112
19113#line 5285 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
19114
19115 ___masm. movq(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
19116
19117#line 19117 "ad_x86.cpp"
19118 }
19119}
19120
19121void loadNKlassNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19122 cbuf.set_insts_mark();
19123 // Start at oper_input_base() and count operands
19124 unsigned idx0 = 2;
19125 unsigned idx1 = 2; // mem
19126 {
19127 C2_MacroAssembler _masm(&cbuf);
19128
19129#line 5298 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
19130
19131 ___masm. movl(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
19132
19133#line 19133 "ad_x86.cpp"
19134 }
19135}
19136
19137void loadFNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19138 cbuf.set_insts_mark();
19139 // Start at oper_input_base() and count operands
19140 unsigned idx0 = 2;
19141 unsigned idx1 = 2; // mem
19142 {
19143 C2_MacroAssembler _masm(&cbuf);
19144
19145#line 5311 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
19146
19147 ___masm. movflt(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
19148
19149#line 19149 "ad_x86.cpp"
19150 }
19151}
19152
19153void loadD_partialNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19154 cbuf.set_insts_mark();
19155 // Start at oper_input_base() and count operands
19156 unsigned idx0 = 2;
19157 unsigned idx1 = 2; // mem
19158 {
19159 C2_MacroAssembler _masm(&cbuf);
19160
19161#line 5325 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
19162
19163 ___masm. movdbl(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
19164
19165#line 19165 "ad_x86.cpp"
19166 }
19167}
19168
19169void loadDNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19170 cbuf.set_insts_mark();
19171 // Start at oper_input_base() and count operands
19172 unsigned idx0 = 2;
19173 unsigned idx1 = 2; // mem
19174 {
19175 C2_MacroAssembler _masm(&cbuf);
19176
19177#line 5338 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
19178
19179 ___masm. movdbl(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
19180
19181#line 19181 "ad_x86.cpp"
19182 }
19183}
19184
19185void maxF_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19186 cbuf.set_insts_mark();
19187 // Start at oper_input_base() and count operands
19188 unsigned idx0 = 1;
19189 unsigned idx1 = 1; // a
19190 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // b
19191 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
19192 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // atmp
19193 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // btmp
19194 {
19195 C2_MacroAssembler _masm(&cbuf);
19196
19197#line 5364 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
19198
19199 int vector_len = Assembler::AVX_128bit;
19200 ___masm. vblendvps(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* btmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* b */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* a */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* b */, vector_len);
19201 ___masm. vblendvps(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* atmp */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* a */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* b */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* b */, vector_len);
19202 ___masm. vmaxss(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* atmp */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* btmp */);
19203 ___masm. vcmpps(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* btmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* atmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* atmp */, Assembler::_false, vector_len);
19204 ___masm. vblendvps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* atmp */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* btmp */, vector_len);
19205
19206#line 19206 "ad_x86.cpp"
19207 }
19208}
19209
19210void maxF_reduction_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19211 cbuf.set_insts_mark();
19212 // Start at oper_input_base() and count operands
19213 unsigned idx0 = 1;
19214 unsigned idx1 = 1; // a
19215 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // b
19216 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // xmmt
19217 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
19218 {
19219 C2_MacroAssembler _masm(&cbuf);
19220
19221#line 5381 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
19222
19223 emit_fp_min_max(_masm, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* a */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* b */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* xmmt */, opnd_array(4)->as_Register(ra_,this,idx4)/* tmp */,
19224 false /*min*/, true /*single*/);
19225
19226#line 19226 "ad_x86.cpp"
19227 }
19228}
19229
19230void maxD_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19231 cbuf.set_insts_mark();
19232 // Start at oper_input_base() and count operands
19233 unsigned idx0 = 1;
19234 unsigned idx1 = 1; // a
19235 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // b
19236 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
19237 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // atmp
19238 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // btmp
19239 {
19240 C2_MacroAssembler _masm(&cbuf);
19241
19242#line 5400 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
19243
19244 int vector_len = Assembler::AVX_128bit;
19245 ___masm. vblendvpd(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* btmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* b */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* a */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* b */, vector_len);
19246 ___masm. vblendvpd(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* atmp */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* a */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* b */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* b */, vector_len);
19247 ___masm. vmaxsd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* atmp */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* btmp */);
19248 ___masm. vcmppd(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* btmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* atmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* atmp */, Assembler::_false, vector_len);
19249 ___masm. vblendvpd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* atmp */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* btmp */, vector_len);
19250
19251#line 19251 "ad_x86.cpp"
19252 }
19253}
19254
19255void maxD_reduction_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19256 cbuf.set_insts_mark();
19257 // Start at oper_input_base() and count operands
19258 unsigned idx0 = 1;
19259 unsigned idx1 = 1; // a
19260 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // b
19261 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // xmmt
19262 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
19263 {
19264 C2_MacroAssembler _masm(&cbuf);
19265
19266#line 5417 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
19267
19268 emit_fp_min_max(_masm, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* a */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* b */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* xmmt */, opnd_array(4)->as_Register(ra_,this,idx4)/* tmp */,
19269 false /*min*/, false /*single*/);
19270
19271#line 19271 "ad_x86.cpp"
19272 }
19273}
19274
19275void minF_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19276 cbuf.set_insts_mark();
19277 // Start at oper_input_base() and count operands
19278 unsigned idx0 = 1;
19279 unsigned idx1 = 1; // a
19280 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // b
19281 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
19282 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // atmp
19283 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // btmp
19284 {
19285 C2_MacroAssembler _masm(&cbuf);
19286
19287#line 5436 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
19288
19289 int vector_len = Assembler::AVX_128bit;
19290 ___masm. vblendvps(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* atmp */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* a */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* b */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* a */, vector_len);
19291 ___masm. vblendvps(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* btmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* b */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* a */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* a */, vector_len);
19292 ___masm. vminss(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* atmp */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* btmp */);
19293 ___masm. vcmpps(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* btmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* atmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* atmp */, Assembler::_false, vector_len);
19294 ___masm. vblendvps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* atmp */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* btmp */, vector_len);
19295
19296#line 19296 "ad_x86.cpp"
19297 }
19298}
19299
19300void minF_reduction_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19301 cbuf.set_insts_mark();
19302 // Start at oper_input_base() and count operands
19303 unsigned idx0 = 1;
19304 unsigned idx1 = 1; // a
19305 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // b
19306 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // xmmt
19307 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
19308 {
19309 C2_MacroAssembler _masm(&cbuf);
19310
19311#line 5453 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
19312
19313 emit_fp_min_max(_masm, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* a */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* b */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* xmmt */, opnd_array(4)->as_Register(ra_,this,idx4)/* tmp */,
19314 true /*min*/, true /*single*/);
19315
19316#line 19316 "ad_x86.cpp"
19317 }
19318}
19319
19320void minD_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19321 cbuf.set_insts_mark();
19322 // Start at oper_input_base() and count operands
19323 unsigned idx0 = 1;
19324 unsigned idx1 = 1; // a
19325 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // b
19326 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
19327 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // atmp
19328 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // btmp
19329 {
19330 C2_MacroAssembler _masm(&cbuf);
19331
19332#line 5472 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
19333
19334 int vector_len = Assembler::AVX_128bit;
19335 ___masm. vblendvpd(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* atmp */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* a */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* b */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* a */, vector_len);
19336 ___masm. vblendvpd(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* btmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* b */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* a */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* a */, vector_len);
19337 ___masm. vminsd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* atmp */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* btmp */);
19338 ___masm. vcmppd(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* btmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* atmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* atmp */, Assembler::_false, vector_len);
19339 ___masm. vblendvpd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* atmp */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* btmp */, vector_len);
19340
19341#line 19341 "ad_x86.cpp"
19342 }
19343}
19344
19345void minD_reduction_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19346 cbuf.set_insts_mark();
19347 // Start at oper_input_base() and count operands
19348 unsigned idx0 = 1;
19349 unsigned idx1 = 1; // a
19350 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // b
19351 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // xmmt
19352 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
19353 {
19354 C2_MacroAssembler _masm(&cbuf);
19355
19356#line 5489 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
19357
19358 emit_fp_min_max(_masm, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* a */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* b */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* xmmt */, opnd_array(4)->as_Register(ra_,this,idx4)/* tmp */,
19359 true /*min*/, false /*single*/);
19360
19361#line 19361 "ad_x86.cpp"
19362 }
19363}
19364
19365void leaP8Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19366 cbuf.set_insts_mark();
19367 // Start at oper_input_base() and count operands
19368 unsigned idx0 = 2;
19369 unsigned idx1 = 2; // mem
19370 {
19371 C2_MacroAssembler _masm(&cbuf);
19372
19373#line 5503 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
19374
19375 ___masm. leaq(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
19376
19377#line 19377 "ad_x86.cpp"
19378 }
19379}
19380
19381void leaP32Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19382 cbuf.set_insts_mark();
19383 // Start at oper_input_base() and count operands
19384 unsigned idx0 = 2;
19385 unsigned idx1 = 2; // mem
19386 {
19387 C2_MacroAssembler _masm(&cbuf);
19388
19389#line 5515 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
19390
19391 ___masm. leaq(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
19392
19393#line 19393 "ad_x86.cpp"
19394 }
19395}
19396
19397void leaPIdxOffNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19398 cbuf.set_insts_mark();
19399 // Start at oper_input_base() and count operands
19400 unsigned idx0 = 2;
19401 unsigned idx1 = 2; // mem
19402 {
19403 C2_MacroAssembler _masm(&cbuf);
19404
19405#line 5527 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
19406
19407 ___masm. leaq(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
19408
19409#line 19409 "ad_x86.cpp"
19410 }
19411}
19412
19413void leaPIdxScaleNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19414 cbuf.set_insts_mark();
19415 // Start at oper_input_base() and count operands
19416 unsigned idx0 = 2;
19417 unsigned idx1 = 2; // mem
19418 {
19419 C2_MacroAssembler _masm(&cbuf);
19420
19421#line 5539 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
19422
19423 ___masm. leaq(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
19424
19425#line 19425 "ad_x86.cpp"
19426 }
19427}
19428
19429void leaPPosIdxScaleNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19430 cbuf.set_insts_mark();
19431 // Start at oper_input_base() and count operands
19432 unsigned idx0 = 2;
19433 unsigned idx1 = 2; // mem
19434 {
19435 C2_MacroAssembler _masm(&cbuf);
19436
19437#line 5551 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
19438
19439 ___masm. leaq(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
19440
19441#line 19441 "ad_x86.cpp"
19442 }
19443}
19444
19445void leaPIdxScaleOffNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19446 cbuf.set_insts_mark();
19447 // Start at oper_input_base() and count operands
19448 unsigned idx0 = 2;
19449 unsigned idx1 = 2; // mem
19450 {
19451 C2_MacroAssembler _masm(&cbuf);
19452
19453#line 5563 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
19454
19455 ___masm. leaq(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
19456
19457#line 19457 "ad_x86.cpp"
19458 }
19459}
19460
19461void leaPPosIdxOffNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19462 cbuf.set_insts_mark();
19463 // Start at oper_input_base() and count operands
19464 unsigned idx0 = 2;
19465 unsigned idx1 = 2; // mem
19466 {
19467 C2_MacroAssembler _masm(&cbuf);
19468
19469#line 5575 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
19470
19471 ___masm. leaq(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
19472
19473#line 19473 "ad_x86.cpp"
19474 }
19475}
19476
19477void leaPPosIdxScaleOffNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19478 cbuf.set_insts_mark();
19479 // Start at oper_input_base() and count operands
19480 unsigned idx0 = 2;
19481 unsigned idx1 = 2; // mem
19482 {
19483 C2_MacroAssembler _masm(&cbuf);
19484
19485#line 5587 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
19486
19487 ___masm. leaq(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
19488
19489#line 19489 "ad_x86.cpp"
19490 }
19491}
19492
19493void leaPCompressedOopOffsetNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19494 cbuf.set_insts_mark();
19495 // Start at oper_input_base() and count operands
19496 unsigned idx0 = 2;
19497 unsigned idx1 = 2; // mem
19498 {
19499 C2_MacroAssembler _masm(&cbuf);
19500
19501#line 5601 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
19502
19503 ___masm. leaq(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
19504
19505#line 19505 "ad_x86.cpp"
19506 }
19507}
19508
19509void leaP8NarrowNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19510 cbuf.set_insts_mark();
19511 // Start at oper_input_base() and count operands
19512 unsigned idx0 = 2;
19513 unsigned idx1 = 2; // mem
19514 {
19515 C2_MacroAssembler _masm(&cbuf);
19516
19517#line 5614 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
19518
19519 ___masm. leaq(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
19520
19521#line 19521 "ad_x86.cpp"
19522 }
19523}
19524
19525void leaP32NarrowNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19526 cbuf.set_insts_mark();
19527 // Start at oper_input_base() and count operands
19528 unsigned idx0 = 2;
19529 unsigned idx1 = 2; // mem
19530 {
19531 C2_MacroAssembler _masm(&cbuf);
19532
19533#line 5627 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
19534
19535 ___masm. leaq(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
19536
19537#line 19537 "ad_x86.cpp"
19538 }
19539}
19540
19541void leaPIdxOffNarrowNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19542 cbuf.set_insts_mark();
19543 // Start at oper_input_base() and count operands
19544 unsigned idx0 = 2;
19545 unsigned idx1 = 2; // mem
19546 {
19547 C2_MacroAssembler _masm(&cbuf);
19548
19549#line 5640 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
19550
19551 ___masm. leaq(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
19552
19553#line 19553 "ad_x86.cpp"
19554 }
19555}
19556
19557void leaPIdxScaleNarrowNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19558 cbuf.set_insts_mark();
19559 // Start at oper_input_base() and count operands
19560 unsigned idx0 = 2;
19561 unsigned idx1 = 2; // mem
19562 {
19563 C2_MacroAssembler _masm(&cbuf);
19564
19565#line 5653 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
19566
19567 ___masm. leaq(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
19568
19569#line 19569 "ad_x86.cpp"
19570 }
19571}
19572
19573void leaPIdxScaleOffNarrowNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19574 cbuf.set_insts_mark();
19575 // Start at oper_input_base() and count operands
19576 unsigned idx0 = 2;
19577 unsigned idx1 = 2; // mem
19578 {
19579 C2_MacroAssembler _masm(&cbuf);
19580
19581#line 5666 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
19582
19583 ___masm. leaq(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
19584
19585#line 19585 "ad_x86.cpp"
19586 }
19587}
19588
19589void leaPPosIdxOffNarrowNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19590 cbuf.set_insts_mark();
19591 // Start at oper_input_base() and count operands
19592 unsigned idx0 = 2;
19593 unsigned idx1 = 2; // mem
19594 {
19595 C2_MacroAssembler _masm(&cbuf);
19596
19597#line 5679 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
19598
19599 ___masm. leaq(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
19600
19601#line 19601 "ad_x86.cpp"
19602 }
19603}
19604
19605void leaPPosIdxScaleOffNarrowNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19606 cbuf.set_insts_mark();
19607 // Start at oper_input_base() and count operands
19608 unsigned idx0 = 2;
19609 unsigned idx1 = 2; // mem
19610 {
19611 C2_MacroAssembler _masm(&cbuf);
19612
19613#line 5692 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
19614
19615 ___masm. leaq(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
19616
19617#line 19617 "ad_x86.cpp"
19618 }
19619}
19620
19621void loadConINode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19622 cbuf.set_insts_mark();
19623 // Start at oper_input_base() and count operands
19624 unsigned idx0 = 1;
19625 unsigned idx1 = 1; // src
19626 {
19627 C2_MacroAssembler _masm(&cbuf);
19628
19629#line 5703 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
19630
19631 ___masm. movl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->constant());
19632
19633#line 19633 "ad_x86.cpp"
19634 }
19635}
19636
19637void loadConI0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19638 cbuf.set_insts_mark();
19639 // Start at oper_input_base() and count operands
19640 unsigned idx0 = 1;
19641 unsigned idx1 = 1; // src
19642 {
19643 C2_MacroAssembler _masm(&cbuf);
19644
19645#line 5716 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
19646
19647 ___masm. xorl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(0)->as_Register(ra_,this)/* dst */);
19648
19649#line 19649 "ad_x86.cpp"
19650 }
19651}
19652
19653void loadConLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19654 cbuf.set_insts_mark();
19655 // Start at oper_input_base() and count operands
19656 unsigned idx0 = 1;
19657 unsigned idx1 = 1; // src
19658 {
19659 C2_MacroAssembler _masm(&cbuf);
19660
19661#line 5728 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
19662
19663 ___masm. mov64(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->constantL());
19664
19665#line 19665 "ad_x86.cpp"
19666 }
19667}
19668
19669void loadConL0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19670 cbuf.set_insts_mark();
19671 // Start at oper_input_base() and count operands
19672 unsigned idx0 = 1;
19673 unsigned idx1 = 1; // src
19674 {
19675 C2_MacroAssembler _masm(&cbuf);
19676
19677#line 5741 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
19678
19679 ___masm. xorl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(0)->as_Register(ra_,this)/* dst */);
19680
19681#line 19681 "ad_x86.cpp"
19682 }
19683}
19684
19685void loadConUL32Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19686 cbuf.set_insts_mark();
19687 // Start at oper_input_base() and count operands
19688 unsigned idx0 = 1;
19689 unsigned idx1 = 1; // src
19690 {
19691 C2_MacroAssembler _masm(&cbuf);
19692
19693#line 5753 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
19694
19695 ___masm. movl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->constantL());
19696
19697#line 19697 "ad_x86.cpp"
19698 }
19699}
19700
19701void loadConL32Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19702 cbuf.set_insts_mark();
19703 // Start at oper_input_base() and count operands
19704 unsigned idx0 = 1;
19705 unsigned idx1 = 1; // src
19706 {
19707 C2_MacroAssembler _masm(&cbuf);
19708
19709#line 5765 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
19710
19711 ___masm. movq(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->constantL());
19712
19713#line 19713 "ad_x86.cpp"
19714 }
19715}
19716
19717void loadConPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19718 cbuf.set_insts_mark();
19719 // Start at oper_input_base() and count operands
19720 unsigned idx0 = 1;
19721 unsigned idx1 = 1; // con
19722 {
19723 C2_MacroAssembler _masm(&cbuf);
19724
19725#line 5775 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
19726
19727 ___masm. mov64(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->constant(), opnd_array(1)->constant_reloc(), RELOC_IMM64Assembler::imm_operand);
19728
19729#line 19729 "ad_x86.cpp"
19730 }
19731}
19732
19733void loadConP0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19734 cbuf.set_insts_mark();
19735 // Start at oper_input_base() and count operands
19736 unsigned idx0 = 1;
19737 unsigned idx1 = 1; // src
19738 {
19739 C2_MacroAssembler _masm(&cbuf);
19740
19741#line 5788 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
19742
19743 ___masm. xorl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(0)->as_Register(ra_,this)/* dst */);
19744
19745#line 19745 "ad_x86.cpp"
19746 }
19747}
19748
19749void loadConP31Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19750 cbuf.set_insts_mark();
19751 // Start at oper_input_base() and count operands
19752 unsigned idx0 = 1;
19753 unsigned idx1 = 1; // src
19754 {
19755 C2_MacroAssembler _masm(&cbuf);
19756
19757#line 5801 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
19758
19759 ___masm. movl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->constant());
19760
19761#line 19761 "ad_x86.cpp"
19762 }
19763}
19764
19765void loadConFNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19766 cbuf.set_insts_mark();
19767 // Start at oper_input_base() and count operands
19768 unsigned idx0 = 1;
19769 unsigned idx1 = 1; // con
19770 {
19771 C2_MacroAssembler _masm(&cbuf);
19772
19773#line 5811 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
19774
19775 ___masm. movflt(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, InternalAddress(___masm. code()->consts()->start() + constant_offset()));
19776
19777#line 19777 "ad_x86.cpp"
19778 }
19779}
19780
19781void loadConFNode::eval_constant(Compile* C) {
19782 {
19783
19784#line 5812 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
19785 _constant = C->output()->constant_table().add(this, opnd_array(1));
19786#line 19786 "ad_x86.cpp"
19787 }
19788}
19789void loadConN0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19790 cbuf.set_insts_mark();
19791 // Start at oper_input_base() and count operands
19792 unsigned idx0 = 1;
19793 unsigned idx1 = 1; // src
19794 {
19795 C2_MacroAssembler _masm(&cbuf);
19796
19797#line 5821 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
19798
19799 ___masm. xorq(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(0)->as_Register(ra_,this)/* dst */);
19800
19801#line 19801 "ad_x86.cpp"
19802 }
19803}
19804
19805void loadConNNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19806 cbuf.set_insts_mark();
19807 // Start at oper_input_base() and count operands
19808 unsigned idx0 = 1;
19809 unsigned idx1 = 1; // src
19810 {
19811 C2_MacroAssembler _masm(&cbuf);
19812
19813#line 5832 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
19814
19815 address con = (address)opnd_array(1)->constant();
19816 if (con == NULL__null) {
19817 ShouldNotReachHere()do { (*g_assert_poison) = 'X';; report_should_not_reach_here(
"/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 5835); ::breakpoint(); } while (0);
19818 } else {
19819 ___masm. set_narrow_oop(opnd_array(0)->as_Register(ra_,this)/* dst */, (jobject)opnd_array(1)->constant());
19820 }
19821
19822#line 19822 "ad_x86.cpp"
19823 }
19824}
19825
19826void loadConNKlassNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19827 cbuf.set_insts_mark();
19828 // Start at oper_input_base() and count operands
19829 unsigned idx0 = 1;
19830 unsigned idx1 = 1; // src
19831 {
19832 C2_MacroAssembler _masm(&cbuf);
19833
19834#line 5848 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
19835
19836 address con = (address)opnd_array(1)->constant();
19837 if (con == NULL__null) {
19838 ShouldNotReachHere()do { (*g_assert_poison) = 'X';; report_should_not_reach_here(
"/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 5851); ::breakpoint(); } while (0);
19839 } else {
19840 ___masm. set_narrow_klass(opnd_array(0)->as_Register(ra_,this)/* dst */, (Klass*)opnd_array(1)->constant());
19841 }
19842
19843#line 19843 "ad_x86.cpp"
19844 }
19845}
19846
19847void loadConF0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19848 cbuf.set_insts_mark();
19849 // Start at oper_input_base() and count operands
19850 unsigned idx0 = 1;
19851 unsigned idx1 = 1; // src
19852 {
19853 C2_MacroAssembler _masm(&cbuf);
19854
19855#line 5865 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
19856
19857 ___masm. xorps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
19858
19859#line 19859 "ad_x86.cpp"
19860 }
19861}
19862
19863void loadConDNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19864 cbuf.set_insts_mark();
19865 // Start at oper_input_base() and count operands
19866 unsigned idx0 = 1;
19867 unsigned idx1 = 1; // con
19868 {
19869 C2_MacroAssembler _masm(&cbuf);
19870
19871#line 5876 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
19872
19873 ___masm. movdbl(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, InternalAddress(___masm. code()->consts()->start() + constant_offset()));
19874
19875#line 19875 "ad_x86.cpp"
19876 }
19877}
19878
19879void loadConDNode::eval_constant(Compile* C) {
19880 {
19881
19882#line 5877 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
19883 _constant = C->output()->constant_table().add(this, opnd_array(1));
19884#line 19884 "ad_x86.cpp"
19885 }
19886}
19887void loadConD0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19888 cbuf.set_insts_mark();
19889 // Start at oper_input_base() and count operands
19890 unsigned idx0 = 1;
19891 unsigned idx1 = 1; // src
19892 {
19893 C2_MacroAssembler _masm(&cbuf);
19894
19895#line 5888 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
19896
19897 ___masm. xorpd (opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
19898
19899#line 19899 "ad_x86.cpp"
19900 }
19901}
19902
19903void loadSSINode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19904 cbuf.set_insts_mark();
19905 // Start at oper_input_base() and count operands
19906 unsigned idx0 = 1;
19907 unsigned idx1 = 1; // src
19908 {
19909
19910#line 2493 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
19911
19912 if (opnd_array(0)->reg(ra_,this)/* dst */ < 8) {
19913 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
19914 if (opnd_array(1)->index(ra_,this,idx1) >= 8) {
19915 emit_opcode(cbuf, Assembler::REX_X);
19916 }
19917 } else {
19918 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
19919 emit_opcode(cbuf, Assembler::REX_B);
19920 } else {
19921 emit_opcode(cbuf, Assembler::REX_XB);
19922 }
19923 }
19924 } else {
19925 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
19926 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
19927 emit_opcode(cbuf, Assembler::REX_R);
19928 } else {
19929 emit_opcode(cbuf, Assembler::REX_RX);
19930 }
19931 } else {
19932 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
19933 emit_opcode(cbuf, Assembler::REX_RB);
19934 } else {
19935 emit_opcode(cbuf, Assembler::REX_RXB);
19936 }
19937 }
19938 }
19939
19940#line 19940 "ad_x86.cpp"
19941 }
19942 {
19943
19944#line 1852 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
19945
19946 emit_opcode(cbuf, (0x8B /*primary()*/));
19947
19948#line 19948 "ad_x86.cpp"
19949 }
19950 {
19951
19952#line 2557 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
19953
19954 // High registers handle in encode_RegMem
19955 int reg = opnd_array(0)->reg(ra_,this)/* dst */;
19956 int base = opnd_array(1)->base(ra_,this,idx1);
19957 int index = opnd_array(1)->index(ra_,this,idx1);
19958 int scale = opnd_array(1)->scale();
19959 int disp = opnd_array(1)->disp(ra_,this,idx1);
19960 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
19961
19962 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
19963
19964#line 19964 "ad_x86.cpp"
19965 }
19966}
19967
19968void loadSSLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
19969 cbuf.set_insts_mark();
19970 // Start at oper_input_base() and count operands
19971 unsigned idx0 = 1;
19972 unsigned idx1 = 1; // src
19973 {
19974
19975#line 2524 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
19976
19977 if (opnd_array(0)->reg(ra_,this)/* dst */ < 8) {
19978 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
19979 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
19980 emit_opcode(cbuf, Assembler::REX_W);
19981 } else {
19982 emit_opcode(cbuf, Assembler::REX_WX);
19983 }
19984 } else {
19985 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
19986 emit_opcode(cbuf, Assembler::REX_WB);
19987 } else {
19988 emit_opcode(cbuf, Assembler::REX_WXB);
19989 }
19990 }
19991 } else {
19992 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
19993 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
19994 emit_opcode(cbuf, Assembler::REX_WR);
19995 } else {
19996 emit_opcode(cbuf, Assembler::REX_WRX);
19997 }
19998 } else {
19999 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
20000 emit_opcode(cbuf, Assembler::REX_WRB);
20001 } else {
20002 emit_opcode(cbuf, Assembler::REX_WRXB);
20003 }
20004 }
20005 }
20006
20007#line 20007 "ad_x86.cpp"
20008 }
20009 {
20010
20011#line 1852 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
20012
20013 emit_opcode(cbuf, (0x8B /*primary()*/));
20014
20015#line 20015 "ad_x86.cpp"
20016 }
20017 {
20018
20019#line 2557 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
20020
20021 // High registers handle in encode_RegMem
20022 int reg = opnd_array(0)->reg(ra_,this)/* dst */;
20023 int base = opnd_array(1)->base(ra_,this,idx1);
20024 int index = opnd_array(1)->index(ra_,this,idx1);
20025 int scale = opnd_array(1)->scale();
20026 int disp = opnd_array(1)->disp(ra_,this,idx1);
20027 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
20028
20029 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
20030
20031#line 20031 "ad_x86.cpp"
20032 }
20033}
20034
20035void loadSSPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
20036 cbuf.set_insts_mark();
20037 // Start at oper_input_base() and count operands
20038 unsigned idx0 = 1;
20039 unsigned idx1 = 1; // src
20040 {
20041
20042#line 2524 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
20043
20044 if (opnd_array(0)->reg(ra_,this)/* dst */ < 8) {
20045 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
20046 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
20047 emit_opcode(cbuf, Assembler::REX_W);
20048 } else {
20049 emit_opcode(cbuf, Assembler::REX_WX);
20050 }
20051 } else {
20052 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
20053 emit_opcode(cbuf, Assembler::REX_WB);
20054 } else {
20055 emit_opcode(cbuf, Assembler::REX_WXB);
20056 }
20057 }
20058 } else {
20059 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
20060 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
20061 emit_opcode(cbuf, Assembler::REX_WR);
20062 } else {
20063 emit_opcode(cbuf, Assembler::REX_WRX);
20064 }
20065 } else {
20066 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
20067 emit_opcode(cbuf, Assembler::REX_WRB);
20068 } else {
20069 emit_opcode(cbuf, Assembler::REX_WRXB);
20070 }
20071 }
20072 }
20073
20074#line 20074 "ad_x86.cpp"
20075 }
20076 {
20077
20078#line 1852 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
20079
20080 emit_opcode(cbuf, (0x8B /*primary()*/));
20081
20082#line 20082 "ad_x86.cpp"
20083 }
20084 {
20085
20086#line 2557 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
20087
20088 // High registers handle in encode_RegMem
20089 int reg = opnd_array(0)->reg(ra_,this)/* dst */;
20090 int base = opnd_array(1)->base(ra_,this,idx1);
20091 int index = opnd_array(1)->index(ra_,this,idx1);
20092 int scale = opnd_array(1)->scale();
20093 int disp = opnd_array(1)->disp(ra_,this,idx1);
20094 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
20095
20096 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
20097
20098#line 20098 "ad_x86.cpp"
20099 }
20100}
20101
20102void loadSSFNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
20103 cbuf.set_insts_mark();
20104 // Start at oper_input_base() and count operands
20105 unsigned idx0 = 1;
20106 unsigned idx1 = 1; // src
20107 {
20108 C2_MacroAssembler _masm(&cbuf);
20109
20110#line 5933 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
20111
20112 ___masm. movflt(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address(rsp, opnd_array(1)->disp(ra_,this,idx1)));
20113
20114#line 20114 "ad_x86.cpp"
20115 }
20116}
20117
20118void loadSSDNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
20119 cbuf.set_insts_mark();
20120 // Start at oper_input_base() and count operands
20121 unsigned idx0 = 1;
20122 unsigned idx1 = 1; // src
20123 {
20124 C2_MacroAssembler _masm(&cbuf);
20125
20126#line 5946 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
20127
20128 ___masm. movdbl(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address(rsp, opnd_array(1)->disp(ra_,this,idx1)));
20129
20130#line 20130 "ad_x86.cpp"
20131 }
20132}
20133
20134void prefetchAllocNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
20135 cbuf.set_insts_mark();
20136 // Start at oper_input_base() and count operands
20137 unsigned idx0 = 2;
20138 unsigned idx1 = 2; //
20139 {
20140 C2_MacroAssembler _masm(&cbuf);
20141
20142#line 5961 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
20143
20144 ___masm. prefetchw(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
20145
20146#line 20146 "ad_x86.cpp"
20147 }
20148}
20149
20150void prefetchAllocNTANode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
20151 cbuf.set_insts_mark();
20152 // Start at oper_input_base() and count operands
20153 unsigned idx0 = 2;
20154 unsigned idx1 = 2; //
20155 {
20156 C2_MacroAssembler _masm(&cbuf);
20157
20158#line 5973 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
20159
20160 ___masm. prefetchnta(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
20161
20162#line 20162 "ad_x86.cpp"
20163 }
20164}
20165
20166void prefetchAllocT0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
20167 cbuf.set_insts_mark();
20168 // Start at oper_input_base() and count operands
20169 unsigned idx0 = 2;
20170 unsigned idx1 = 2; //
20171 {
20172 C2_MacroAssembler _masm(&cbuf);
20173
20174#line 5985 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
20175
20176 ___masm. prefetcht0(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
20177
20178#line 20178 "ad_x86.cpp"
20179 }
20180}
20181
20182void prefetchAllocT2Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
20183 cbuf.set_insts_mark();
20184 // Start at oper_input_base() and count operands
20185 unsigned idx0 = 2;
20186 unsigned idx1 = 2; //
20187 {
20188 C2_MacroAssembler _masm(&cbuf);
20189
20190#line 5997 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
20191
20192 ___masm. prefetcht2(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
20193
20194#line 20194 "ad_x86.cpp"
20195 }
20196}
20197
20198void storeBNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
20199 cbuf.set_insts_mark();
20200 // Start at oper_input_base() and count operands
20201 unsigned idx0 = 2;
20202 unsigned idx1 = 2; // mem
20203 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
20204 {
20205 C2_MacroAssembler _masm(&cbuf);
20206
20207#line 6012 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
20208
20209 ___masm. movb(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_Register(ra_,this,idx2)/* src */);
20210
20211#line 20211 "ad_x86.cpp"
20212 }
20213}
20214
20215void storeCNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
20216 cbuf.set_insts_mark();
20217 // Start at oper_input_base() and count operands
20218 unsigned idx0 = 2;
20219 unsigned idx1 = 2; // mem
20220 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
20221 {
20222 C2_MacroAssembler _masm(&cbuf);
20223
20224#line 6025 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
20225
20226 ___masm. movw(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_Register(ra_,this,idx2)/* src */);
20227
20228#line 20228 "ad_x86.cpp"
20229 }
20230}
20231
20232void storeINode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
20233 cbuf.set_insts_mark();
20234 // Start at oper_input_base() and count operands
20235 unsigned idx0 = 2;
20236 unsigned idx1 = 2; // mem
20237 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
20238 {
20239 C2_MacroAssembler _masm(&cbuf);
20240
20241#line 6038 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
20242
20243 ___masm. movl(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_Register(ra_,this,idx2)/* src */);
20244
20245#line 20245 "ad_x86.cpp"
20246 }
20247}
20248
20249void storeLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
20250 cbuf.set_insts_mark();
20251 // Start at oper_input_base() and count operands
20252 unsigned idx0 = 2;
20253 unsigned idx1 = 2; // mem
20254 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
20255 {
20256 C2_MacroAssembler _masm(&cbuf);
20257
20258#line 6051 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
20259
20260 ___masm. movq(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_Register(ra_,this,idx2)/* src */);
20261
20262#line 20262 "ad_x86.cpp"
20263 }
20264}
20265
20266void storePNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
20267 cbuf.set_insts_mark();
20268 // Start at oper_input_base() and count operands
20269 unsigned idx0 = 2;
20270 unsigned idx1 = 2; // mem
20271 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
20272 {
20273 C2_MacroAssembler _masm(&cbuf);
20274
20275#line 6064 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
20276
20277 ___masm. movq(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_Register(ra_,this,idx2)/* src */);
20278
20279#line 20279 "ad_x86.cpp"
20280 }
20281}
20282
20283void storeImmP0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
20284 cbuf.set_insts_mark();
20285 // Start at oper_input_base() and count operands
20286 unsigned idx0 = 2;
20287 unsigned idx1 = 2; // mem
20288 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
20289 {
20290 C2_MacroAssembler _masm(&cbuf);
20291
20292#line 6077 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
20293
20294 ___masm. movq(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), r12);
20295
20296#line 20296 "ad_x86.cpp"
20297 }
20298}
20299
20300void storeImmPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
20301 cbuf.set_insts_mark();
20302 // Start at oper_input_base() and count operands
20303 unsigned idx0 = 2;
20304 unsigned idx1 = 2; // mem
20305 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
20306 {
20307 C2_MacroAssembler _masm(&cbuf);
20308
20309#line 6090 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
20310
20311 ___masm. movq(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->constant());
20312
20313#line 20313 "ad_x86.cpp"
20314 }
20315}
20316
20317void storeNNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
20318 cbuf.set_insts_mark();
20319 // Start at oper_input_base() and count operands
20320 unsigned idx0 = 2;
20321 unsigned idx1 = 2; // mem
20322 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
20323 {
20324 C2_MacroAssembler _masm(&cbuf);
20325
20326#line 6103 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
20327
20328 ___masm. movl(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_Register(ra_,this,idx2)/* src */);
20329
20330#line 20330 "ad_x86.cpp"
20331 }
20332}
20333
20334void storeNKlassNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
20335 cbuf.set_insts_mark();
20336 // Start at oper_input_base() and count operands
20337 unsigned idx0 = 2;
20338 unsigned idx1 = 2; // mem
20339 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
20340 {
20341 C2_MacroAssembler _masm(&cbuf);
20342
20343#line 6115 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
20344
20345 ___masm. movl(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_Register(ra_,this,idx2)/* src */);
20346
20347#line 20347 "ad_x86.cpp"
20348 }
20349}
20350
20351void storeImmN0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
20352 cbuf.set_insts_mark();
20353 // Start at oper_input_base() and count operands
20354 unsigned idx0 = 2;
20355 unsigned idx1 = 2; // mem
20356 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
20357 {
20358 C2_MacroAssembler _masm(&cbuf);
20359
20360#line 6128 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
20361
20362 ___masm. movl(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), r12);
20363
20364#line 20364 "ad_x86.cpp"
20365 }
20366}
20367
20368void storeImmNNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
20369 cbuf.set_insts_mark();
20370 // Start at oper_input_base() and count operands
20371 unsigned idx0 = 2;
20372 unsigned idx1 = 2; // mem
20373 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
20374 {
20375 C2_MacroAssembler _masm(&cbuf);
20376
20377#line 6140 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
20378
20379 address con = (address)opnd_array(2)->constant();
20380 if (con == NULL__null) {
20381 ___masm. movl(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), (int32_t)0);
20382 } else {
20383 ___masm. set_narrow_oop(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), (jobject)opnd_array(2)->constant());
20384 }
20385
20386#line 20386 "ad_x86.cpp"
20387 }
20388}
20389
20390void storeImmNKlassNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
20391 cbuf.set_insts_mark();
20392 // Start at oper_input_base() and count operands
20393 unsigned idx0 = 2;
20394 unsigned idx1 = 2; // mem
20395 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
20396 {
20397 C2_MacroAssembler _masm(&cbuf);
20398
20399#line 6157 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
20400
20401 ___masm. set_narrow_klass(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), (Klass*)opnd_array(2)->constant());
20402
20403#line 20403 "ad_x86.cpp"
20404 }
20405}
20406
20407void storeImmI0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
20408 cbuf.set_insts_mark();
20409 // Start at oper_input_base() and count operands
20410 unsigned idx0 = 2;
20411 unsigned idx1 = 2; // mem
20412 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
20413 {
20414 C2_MacroAssembler _masm(&cbuf);
20415
20416#line 6171 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
20417
20418 ___masm. movl(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), r12);
20419
20420#line 20420 "ad_x86.cpp"
20421 }
20422}
20423
20424void storeImmINode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
20425 cbuf.set_insts_mark();
20426 // Start at oper_input_base() and count operands
20427 unsigned idx0 = 2;
20428 unsigned idx1 = 2; // mem
20429 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
20430 {
20431 C2_MacroAssembler _masm(&cbuf);
20432
20433#line 6183 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
20434
20435 ___masm. movl(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->constant());
20436
20437#line 20437 "ad_x86.cpp"
20438 }
20439}
20440
20441void storeImmL0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
20442 cbuf.set_insts_mark();
20443 // Start at oper_input_base() and count operands
20444 unsigned idx0 = 2;
20445 unsigned idx1 = 2; // mem
20446 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
20447 {
20448 C2_MacroAssembler _masm(&cbuf);
20449
20450#line 6197 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
20451
20452 ___masm. movq(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), r12);
20453
20454#line 20454 "ad_x86.cpp"
20455 }
20456}
20457
20458void storeImmLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
20459 cbuf.set_insts_mark();
20460 // Start at oper_input_base() and count operands
20461 unsigned idx0 = 2;
20462 unsigned idx1 = 2; // mem
20463 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
20464 {
20465 C2_MacroAssembler _masm(&cbuf);
20466
20467#line 6209 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
20468
20469 ___masm. movq(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->constantL());
20470
20471#line 20471 "ad_x86.cpp"
20472 }
20473}
20474
20475void storeImmC0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
20476 cbuf.set_insts_mark();
20477 // Start at oper_input_base() and count operands
20478 unsigned idx0 = 2;
20479 unsigned idx1 = 2; // mem
20480 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
20481 {
20482 C2_MacroAssembler _masm(&cbuf);
20483
20484#line 6223 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
20485
20486 ___masm. movw(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), r12);
20487
20488#line 20488 "ad_x86.cpp"
20489 }
20490}
20491
20492void storeImmI16Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
20493 cbuf.set_insts_mark();
20494 // Start at oper_input_base() and count operands
20495 unsigned idx0 = 2;
20496 unsigned idx1 = 2; // mem
20497 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
20498 {
20499 C2_MacroAssembler _masm(&cbuf);
20500
20501#line 6236 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
20502
20503 ___masm. movw(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->constant());
20504
20505#line 20505 "ad_x86.cpp"
20506 }
20507}
20508
20509void storeImmB0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
20510 cbuf.set_insts_mark();
20511 // Start at oper_input_base() and count operands
20512 unsigned idx0 = 2;
20513 unsigned idx1 = 2; // mem
20514 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
20515 {
20516 C2_MacroAssembler _masm(&cbuf);
20517
20518#line 6250 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
20519
20520 ___masm. movb(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), r12);
20521
20522#line 20522 "ad_x86.cpp"
20523 }
20524}
20525
20526void storeImmBNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
20527 cbuf.set_insts_mark();
20528 // Start at oper_input_base() and count operands
20529 unsigned idx0 = 2;
20530 unsigned idx1 = 2; // mem
20531 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
20532 {
20533 C2_MacroAssembler _masm(&cbuf);
20534
20535#line 6262 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
20536
20537 ___masm. movb(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->constant());
20538
20539#line 20539 "ad_x86.cpp"
20540 }
20541}
20542
20543void storeImmCM0_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
20544 cbuf.set_insts_mark();
20545 // Start at oper_input_base() and count operands
20546 unsigned idx0 = 2;
20547 unsigned idx1 = 2; // mem
20548 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
20549 {
20550 C2_MacroAssembler _masm(&cbuf);
20551
20552#line 6276 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
20553
20554 ___masm. movb(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), r12);
20555
20556#line 20556 "ad_x86.cpp"
20557 }
20558}
20559
20560void storeImmCM0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
20561 cbuf.set_insts_mark();
20562 // Start at oper_input_base() and count operands
20563 unsigned idx0 = 2;
20564 unsigned idx1 = 2; // mem
20565 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
20566 {
20567 C2_MacroAssembler _masm(&cbuf);
20568
20569#line 6288 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
20570
20571 ___masm. movb(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->constant());
20572
20573#line 20573 "ad_x86.cpp"
20574 }
20575}
20576
20577void storeFNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
20578 cbuf.set_insts_mark();
20579 // Start at oper_input_base() and count operands
20580 unsigned idx0 = 2;
20581 unsigned idx1 = 2; // mem
20582 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
20583 {
20584 C2_MacroAssembler _masm(&cbuf);
20585
20586#line 6301 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
20587
20588 ___masm. movflt(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
20589
20590#line 20590 "ad_x86.cpp"
20591 }
20592}
20593
20594void storeF0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
20595 cbuf.set_insts_mark();
20596 // Start at oper_input_base() and count operands
20597 unsigned idx0 = 2;
20598 unsigned idx1 = 2; // mem
20599 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
20600 {
20601 C2_MacroAssembler _masm(&cbuf);
20602
20603#line 6315 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
20604
20605 ___masm. movl(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), r12);
20606
20607#line 20607 "ad_x86.cpp"
20608 }
20609}
20610
20611void storeF_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
20612 cbuf.set_insts_mark();
20613 // Start at oper_input_base() and count operands
20614 unsigned idx0 = 2;
20615 unsigned idx1 = 2; // mem
20616 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
20617 {
20618 C2_MacroAssembler _masm(&cbuf);
20619
20620#line 6327 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
20621
20622 ___masm. movl(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), jint_cast(opnd_array(2)->constantF()));
20623
20624#line 20624 "ad_x86.cpp"
20625 }
20626}
20627
20628void storeDNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
20629 cbuf.set_insts_mark();
20630 // Start at oper_input_base() and count operands
20631 unsigned idx0 = 2;
20632 unsigned idx1 = 2; // mem
20633 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
20634 {
20635 C2_MacroAssembler _masm(&cbuf);
20636
20637#line 6340 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
20638
20639 ___masm. movdbl(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
20640
20641#line 20641 "ad_x86.cpp"
20642 }
20643}
20644
20645void storeD0_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
20646 cbuf.set_insts_mark();
20647 // Start at oper_input_base() and count operands
20648 unsigned idx0 = 2;
20649 unsigned idx1 = 2; // mem
20650 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
20651 {
20652 C2_MacroAssembler _masm(&cbuf);
20653
20654#line 6354 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
20655
20656 ___masm. movq(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->constantD());
20657
20658#line 20658 "ad_x86.cpp"
20659 }
20660}
20661
20662void storeD0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
20663 cbuf.set_insts_mark();
20664 // Start at oper_input_base() and count operands
20665 unsigned idx0 = 2;
20666 unsigned idx1 = 2; // mem
20667 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
20668 {
20669 C2_MacroAssembler _masm(&cbuf);
20670
20671#line 6367 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
20672
20673 ___masm. movq(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), r12);
20674
20675#line 20675 "ad_x86.cpp"
20676 }
20677}
20678
20679void storeSSINode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
20680 cbuf.set_insts_mark();
20681 // Start at oper_input_base() and count operands
20682 unsigned idx0 = 1;
20683 unsigned idx1 = 1; // src
20684 {
20685
20686#line 2493 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
20687
20688 if (opnd_array(1)->reg(ra_,this,idx1)/* src */ < 8) {
20689 if (opnd_array(0)->base(ra_,this,idx0) < 8) {
20690 if (opnd_array(0)->index(ra_,this,idx0) >= 8) {
20691 emit_opcode(cbuf, Assembler::REX_X);
20692 }
20693 } else {
20694 if (opnd_array(0)->index(ra_,this,idx0) < 8) {
20695 emit_opcode(cbuf, Assembler::REX_B);
20696 } else {
20697 emit_opcode(cbuf, Assembler::REX_XB);
20698 }
20699 }
20700 } else {
20701 if (opnd_array(0)->base(ra_,this,idx0) < 8) {
20702 if (opnd_array(0)->index(ra_,this,idx0) < 8) {
20703 emit_opcode(cbuf, Assembler::REX_R);
20704 } else {
20705 emit_opcode(cbuf, Assembler::REX_RX);
20706 }
20707 } else {
20708 if (opnd_array(0)->index(ra_,this,idx0) < 8) {
20709 emit_opcode(cbuf, Assembler::REX_RB);
20710 } else {
20711 emit_opcode(cbuf, Assembler::REX_RXB);
20712 }
20713 }
20714 }
20715
20716#line 20716 "ad_x86.cpp"
20717 }
20718 {
20719
20720#line 1852 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
20721
20722 emit_opcode(cbuf, (0x89 /*primary()*/));
20723
20724#line 20724 "ad_x86.cpp"
20725 }
20726 {
20727
20728#line 2557 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
20729
20730 // High registers handle in encode_RegMem
20731 int reg = opnd_array(1)->reg(ra_,this,idx1)/* src */;
20732 int base = opnd_array(0)->base(ra_,this,idx0);
20733 int index = opnd_array(0)->index(ra_,this,idx0);
20734 int scale = opnd_array(0)->scale();
20735 int disp = opnd_array(0)->disp(ra_,this,0);
20736 relocInfo::relocType disp_reloc = opnd_array(0)->disp_reloc();
20737
20738 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
20739
20740#line 20740 "ad_x86.cpp"
20741 }
20742}
20743
20744void storeSSLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
20745 cbuf.set_insts_mark();
20746 // Start at oper_input_base() and count operands
20747 unsigned idx0 = 1;
20748 unsigned idx1 = 1; // src
20749 {
20750
20751#line 2524 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
20752
20753 if (opnd_array(1)->reg(ra_,this,idx1)/* src */ < 8) {
20754 if (opnd_array(0)->base(ra_,this,idx0) < 8) {
20755 if (opnd_array(0)->index(ra_,this,idx0) < 8) {
20756 emit_opcode(cbuf, Assembler::REX_W);
20757 } else {
20758 emit_opcode(cbuf, Assembler::REX_WX);
20759 }
20760 } else {
20761 if (opnd_array(0)->index(ra_,this,idx0) < 8) {
20762 emit_opcode(cbuf, Assembler::REX_WB);
20763 } else {
20764 emit_opcode(cbuf, Assembler::REX_WXB);
20765 }
20766 }
20767 } else {
20768 if (opnd_array(0)->base(ra_,this,idx0) < 8) {
20769 if (opnd_array(0)->index(ra_,this,idx0) < 8) {
20770 emit_opcode(cbuf, Assembler::REX_WR);
20771 } else {
20772 emit_opcode(cbuf, Assembler::REX_WRX);
20773 }
20774 } else {
20775 if (opnd_array(0)->index(ra_,this,idx0) < 8) {
20776 emit_opcode(cbuf, Assembler::REX_WRB);
20777 } else {
20778 emit_opcode(cbuf, Assembler::REX_WRXB);
20779 }
20780 }
20781 }
20782
20783#line 20783 "ad_x86.cpp"
20784 }
20785 {
20786
20787#line 1852 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
20788
20789 emit_opcode(cbuf, (0x89 /*primary()*/));
20790
20791#line 20791 "ad_x86.cpp"
20792 }
20793 {
20794
20795#line 2557 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
20796
20797 // High registers handle in encode_RegMem
20798 int reg = opnd_array(1)->reg(ra_,this,idx1)/* src */;
20799 int base = opnd_array(0)->base(ra_,this,idx0);
20800 int index = opnd_array(0)->index(ra_,this,idx0);
20801 int scale = opnd_array(0)->scale();
20802 int disp = opnd_array(0)->disp(ra_,this,0);
20803 relocInfo::relocType disp_reloc = opnd_array(0)->disp_reloc();
20804
20805 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
20806
20807#line 20807 "ad_x86.cpp"
20808 }
20809}
20810
20811void storeSSPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
20812 cbuf.set_insts_mark();
20813 // Start at oper_input_base() and count operands
20814 unsigned idx0 = 1;
20815 unsigned idx1 = 1; // src
20816 {
20817
20818#line 2524 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
20819
20820 if (opnd_array(1)->reg(ra_,this,idx1)/* src */ < 8) {
20821 if (opnd_array(0)->base(ra_,this,idx0) < 8) {
20822 if (opnd_array(0)->index(ra_,this,idx0) < 8) {
20823 emit_opcode(cbuf, Assembler::REX_W);
20824 } else {
20825 emit_opcode(cbuf, Assembler::REX_WX);
20826 }
20827 } else {
20828 if (opnd_array(0)->index(ra_,this,idx0) < 8) {
20829 emit_opcode(cbuf, Assembler::REX_WB);
20830 } else {
20831 emit_opcode(cbuf, Assembler::REX_WXB);
20832 }
20833 }
20834 } else {
20835 if (opnd_array(0)->base(ra_,this,idx0) < 8) {
20836 if (opnd_array(0)->index(ra_,this,idx0) < 8) {
20837 emit_opcode(cbuf, Assembler::REX_WR);
20838 } else {
20839 emit_opcode(cbuf, Assembler::REX_WRX);
20840 }
20841 } else {
20842 if (opnd_array(0)->index(ra_,this,idx0) < 8) {
20843 emit_opcode(cbuf, Assembler::REX_WRB);
20844 } else {
20845 emit_opcode(cbuf, Assembler::REX_WRXB);
20846 }
20847 }
20848 }
20849
20850#line 20850 "ad_x86.cpp"
20851 }
20852 {
20853
20854#line 1852 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
20855
20856 emit_opcode(cbuf, (0x89 /*primary()*/));
20857
20858#line 20858 "ad_x86.cpp"
20859 }
20860 {
20861
20862#line 2557 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
20863
20864 // High registers handle in encode_RegMem
20865 int reg = opnd_array(1)->reg(ra_,this,idx1)/* src */;
20866 int base = opnd_array(0)->base(ra_,this,idx0);
20867 int index = opnd_array(0)->index(ra_,this,idx0);
20868 int scale = opnd_array(0)->scale();
20869 int disp = opnd_array(0)->disp(ra_,this,0);
20870 relocInfo::relocType disp_reloc = opnd_array(0)->disp_reloc();
20871
20872 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
20873
20874#line 20874 "ad_x86.cpp"
20875 }
20876}
20877
20878void storeSSFNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
20879 cbuf.set_insts_mark();
20880 // Start at oper_input_base() and count operands
20881 unsigned idx0 = 1;
20882 unsigned idx1 = 1; // src
20883 {
20884 C2_MacroAssembler _masm(&cbuf);
20885
20886#line 6412 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
20887
20888 ___masm. movflt(Address(rsp, opnd_array(0)->disp(ra_,this,0)), opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
20889
20890#line 20890 "ad_x86.cpp"
20891 }
20892}
20893
20894void storeSSDNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
20895 cbuf.set_insts_mark();
20896 // Start at oper_input_base() and count operands
20897 unsigned idx0 = 1;
20898 unsigned idx1 = 1; // src
20899 {
20900 C2_MacroAssembler _masm(&cbuf);
20901
20902#line 6424 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
20903
20904 ___masm. movdbl(Address(rsp, opnd_array(0)->disp(ra_,this,0)), opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
20905
20906#line 20906 "ad_x86.cpp"
20907 }
20908}
20909
20910void cacheWBNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
20911 cbuf.set_insts_mark();
20912 // Start at oper_input_base() and count operands
20913 unsigned idx0 = 2;
20914 unsigned idx1 = 2; //
20915 {
20916 C2_MacroAssembler _masm(&cbuf);
20917
20918#line 6437 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
20919
20920 assert(opnd_array(1)->index_position() < 0, "should be")do { if (!(opnd_array(1)->index_position() < 0)) { (*g_assert_poison
) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 6438, "assert(" "opnd_array(1)->index_position() < 0"
") failed", "should be"); ::breakpoint(); } } while (0);
20921 assert(opnd_array(1)->disp(ra_,this,idx1)== 0, "should be")do { if (!(opnd_array(1)->disp(ra_,this,idx1)== 0)) { (*g_assert_poison
) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 6439, "assert(" "opnd_array(1)->disp(ra_,this,idx1)== 0"
") failed", "should be"); ::breakpoint(); } } while (0);
20922 ___masm. cache_wb(Address(as_Register(opnd_array(1)->base(ra_,this,idx1)), 0));
20923
20924#line 20924 "ad_x86.cpp"
20925 }
20926}
20927
20928void cacheWBPreSyncNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
20929 cbuf.set_insts_mark();
20930 // Start at oper_input_base() and count operands
20931 unsigned idx0 = 2;
20932 unsigned idx1 = 2; //
20933 {
20934 C2_MacroAssembler _masm(&cbuf);
20935
20936#line 6452 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
20937
20938 ___masm. cache_wbsync(true);
20939
20940#line 20940 "ad_x86.cpp"
20941 }
20942}
20943
20944void cacheWBPostSyncNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
20945 cbuf.set_insts_mark();
20946 // Start at oper_input_base() and count operands
20947 unsigned idx0 = 2;
20948 unsigned idx1 = 2; //
20949 {
20950 C2_MacroAssembler _masm(&cbuf);
20951
20952#line 6465 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
20953
20954 ___masm. cache_wbsync(false);
20955
20956#line 20956 "ad_x86.cpp"
20957 }
20958}
20959
20960void bytes_reverse_intNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
20961 cbuf.set_insts_mark();
20962 // Start at oper_input_base() and count operands
20963 unsigned idx0 = 1;
20964 unsigned idx1 = 1; // dst
20965 {
20966 C2_MacroAssembler _masm(&cbuf);
20967
20968#line 6476 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
20969
20970 ___masm. bswapl(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */);
20971
20972#line 20972 "ad_x86.cpp"
20973 }
20974}
20975
20976void bytes_reverse_longNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
20977 cbuf.set_insts_mark();
20978 // Start at oper_input_base() and count operands
20979 unsigned idx0 = 1;
20980 unsigned idx1 = 1; // dst
20981 {
20982 C2_MacroAssembler _masm(&cbuf);
20983
20984#line 6486 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
20985
20986 ___masm. bswapq(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */);
20987
20988#line 20988 "ad_x86.cpp"
20989 }
20990}
20991
20992void bytes_reverse_unsigned_shortNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
20993 cbuf.set_insts_mark();
20994 // Start at oper_input_base() and count operands
20995 unsigned idx0 = 1;
20996 unsigned idx1 = 1; // dst
20997 {
20998 C2_MacroAssembler _masm(&cbuf);
20999
21000#line 6498 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
21001
21002 ___masm. bswapl(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */);
21003 ___masm. shrl(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, 16);
21004
21005#line 21005 "ad_x86.cpp"
21006 }
21007}
21008
21009void bytes_reverse_shortNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21010 cbuf.set_insts_mark();
21011 // Start at oper_input_base() and count operands
21012 unsigned idx0 = 1;
21013 unsigned idx1 = 1; // dst
21014 {
21015 C2_MacroAssembler _masm(&cbuf);
21016
21017#line 6511 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
21018
21019 ___masm. bswapl(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */);
21020 ___masm. sarl(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, 16);
21021
21022#line 21022 "ad_x86.cpp"
21023 }
21024}
21025
21026void countLeadingZerosINode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21027 cbuf.set_insts_mark();
21028 // Start at oper_input_base() and count operands
21029 unsigned idx0 = 1;
21030 unsigned idx1 = 1; // src
21031 {
21032 C2_MacroAssembler _masm(&cbuf);
21033
21034#line 6526 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
21035
21036 ___masm. lzcntl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
21037
21038#line 21038 "ad_x86.cpp"
21039 }
21040}
21041
21042void countLeadingZerosI_bsrNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21043 cbuf.set_insts_mark();
21044 // Start at oper_input_base() and count operands
21045 unsigned idx0 = 1;
21046 unsigned idx1 = 1; // src
21047 {
21048 C2_MacroAssembler _masm(&cbuf);
21049
21050#line 6543 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
21051
21052 Register Rdst = opnd_array(0)->as_Register(ra_,this)/* dst */;
21053 Register Rsrc = opnd_array(1)->as_Register(ra_,this,idx1)/* src */;
21054 Label skip;
21055 ___masm. bsrl(Rdst, Rsrc);
21056 ___masm. jccb(Assembler::notZero, skip)jccb_0(Assembler::notZero, skip, "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 6548);
21057 ___masm. movl(Rdst, -1);
21058 ___masm. bind(skip);
21059 ___masm. negl(Rdst);
21060 ___masm. addl(Rdst, BitsPerInt - 1);
21061
21062#line 21062 "ad_x86.cpp"
21063 }
21064}
21065
21066void countLeadingZerosLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21067 cbuf.set_insts_mark();
21068 // Start at oper_input_base() and count operands
21069 unsigned idx0 = 1;
21070 unsigned idx1 = 1; // src
21071 {
21072 C2_MacroAssembler _masm(&cbuf);
21073
21074#line 6563 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
21075
21076 ___masm. lzcntq(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
21077
21078#line 21078 "ad_x86.cpp"
21079 }
21080}
21081
21082void countLeadingZerosL_bsrNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21083 cbuf.set_insts_mark();
21084 // Start at oper_input_base() and count operands
21085 unsigned idx0 = 1;
21086 unsigned idx1 = 1; // src
21087 {
21088 C2_MacroAssembler _masm(&cbuf);
21089
21090#line 6580 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
21091
21092 Register Rdst = opnd_array(0)->as_Register(ra_,this)/* dst */;
21093 Register Rsrc = opnd_array(1)->as_Register(ra_,this,idx1)/* src */;
21094 Label skip;
21095 ___masm. bsrq(Rdst, Rsrc);
21096 ___masm. jccb(Assembler::notZero, skip)jccb_0(Assembler::notZero, skip, "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 6585);
21097 ___masm. movl(Rdst, -1);
21098 ___masm. bind(skip);
21099 ___masm. negl(Rdst);
21100 ___masm. addl(Rdst, BitsPerLong - 1);
21101
21102#line 21102 "ad_x86.cpp"
21103 }
21104}
21105
21106void countTrailingZerosINode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21107 cbuf.set_insts_mark();
21108 // Start at oper_input_base() and count operands
21109 unsigned idx0 = 1;
21110 unsigned idx1 = 1; // src
21111 {
21112 C2_MacroAssembler _masm(&cbuf);
21113
21114#line 6600 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
21115
21116 ___masm. tzcntl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
21117
21118#line 21118 "ad_x86.cpp"
21119 }
21120}
21121
21122void countTrailingZerosI_bsfNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21123 cbuf.set_insts_mark();
21124 // Start at oper_input_base() and count operands
21125 unsigned idx0 = 1;
21126 unsigned idx1 = 1; // src
21127 {
21128 C2_MacroAssembler _masm(&cbuf);
21129
21130#line 6615 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
21131
21132 Register Rdst = opnd_array(0)->as_Register(ra_,this)/* dst */;
21133 Label done;
21134 ___masm. bsfl(Rdst, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
21135 ___masm. jccb(Assembler::notZero, done)jccb_0(Assembler::notZero, done, "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 6619);
21136 ___masm. movl(Rdst, BitsPerInt);
21137 ___masm. bind(done);
21138
21139#line 21139 "ad_x86.cpp"
21140 }
21141}
21142
21143void countTrailingZerosLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21144 cbuf.set_insts_mark();
21145 // Start at oper_input_base() and count operands
21146 unsigned idx0 = 1;
21147 unsigned idx1 = 1; // src
21148 {
21149 C2_MacroAssembler _masm(&cbuf);
21150
21151#line 6632 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
21152
21153 ___masm. tzcntq(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
21154
21155#line 21155 "ad_x86.cpp"
21156 }
21157}
21158
21159void countTrailingZerosL_bsfNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21160 cbuf.set_insts_mark();
21161 // Start at oper_input_base() and count operands
21162 unsigned idx0 = 1;
21163 unsigned idx1 = 1; // src
21164 {
21165 C2_MacroAssembler _masm(&cbuf);
21166
21167#line 6647 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
21168
21169 Register Rdst = opnd_array(0)->as_Register(ra_,this)/* dst */;
21170 Label done;
21171 ___masm. bsfq(Rdst, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
21172 ___masm. jccb(Assembler::notZero, done)jccb_0(Assembler::notZero, done, "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 6651);
21173 ___masm. movl(Rdst, BitsPerLong);
21174 ___masm. bind(done);
21175
21176#line 21176 "ad_x86.cpp"
21177 }
21178}
21179
21180void popCountINode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21181 cbuf.set_insts_mark();
21182 // Start at oper_input_base() and count operands
21183 unsigned idx0 = 1;
21184 unsigned idx1 = 1; // src
21185 {
21186 C2_MacroAssembler _masm(&cbuf);
21187
21188#line 6667 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
21189
21190 ___masm. popcntl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
21191
21192#line 21192 "ad_x86.cpp"
21193 }
21194}
21195
21196void popCountI_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21197 cbuf.set_insts_mark();
21198 // Start at oper_input_base() and count operands
21199 unsigned idx0 = 2;
21200 unsigned idx1 = 2; // mem
21201 {
21202 C2_MacroAssembler _masm(&cbuf);
21203
21204#line 6679 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
21205
21206 ___masm. popcntl(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
21207
21208#line 21208 "ad_x86.cpp"
21209 }
21210}
21211
21212void popCountLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21213 cbuf.set_insts_mark();
21214 // Start at oper_input_base() and count operands
21215 unsigned idx0 = 1;
21216 unsigned idx1 = 1; // src
21217 {
21218 C2_MacroAssembler _masm(&cbuf);
21219
21220#line 6692 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
21221
21222 ___masm. popcntq(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
21223
21224#line 21224 "ad_x86.cpp"
21225 }
21226}
21227
21228void popCountL_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21229 cbuf.set_insts_mark();
21230 // Start at oper_input_base() and count operands
21231 unsigned idx0 = 2;
21232 unsigned idx1 = 2; // mem
21233 {
21234 C2_MacroAssembler _masm(&cbuf);
21235
21236#line 6705 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
21237
21238 ___masm. popcntq(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
21239
21240#line 21240 "ad_x86.cpp"
21241 }
21242}
21243
21244void membar_acquireNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21245 cbuf.set_insts_mark();
21246 // Start at oper_input_base() and count operands
21247 unsigned idx0 = 1;
21248 unsigned idx1 = 1; //
21249 // User did not define which encode class to use.
21250}
21251
21252uint membar_acquireNode::size(PhaseRegAlloc *ra_) const {
21253 assert(VerifyOops || MachNode::size(ra_) <= 0, "bad fixed size")do { if (!(VerifyOops || MachNode::size(ra_) <= 0)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 21252, "assert(" "VerifyOops || MachNode::size(ra_) <= 0"
") failed", "bad fixed size"); ::breakpoint(); } } while (0);
21254 return (VerifyOops ? MachNode::size(ra_) : 0);
21255}
21256
21257void membar_acquire_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21258 cbuf.set_insts_mark();
21259 // Start at oper_input_base() and count operands
21260 unsigned idx0 = 1;
21261 unsigned idx1 = 1; //
21262 // User did not define which encode class to use.
21263}
21264
21265uint membar_acquire_0Node::size(PhaseRegAlloc *ra_) const {
21266 assert(VerifyOops || MachNode::size(ra_) <= 0, "bad fixed size")do { if (!(VerifyOops || MachNode::size(ra_) <= 0)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 21265, "assert(" "VerifyOops || MachNode::size(ra_) <= 0"
") failed", "bad fixed size"); ::breakpoint(); } } while (0);
21267 return (VerifyOops ? MachNode::size(ra_) : 0);
21268}
21269
21270void membar_acquire_lockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21271 cbuf.set_insts_mark();
21272 // Start at oper_input_base() and count operands
21273 unsigned idx0 = 1;
21274 unsigned idx1 = 1; //
21275 // User did not define which encode class to use.
21276}
21277
21278uint membar_acquire_lockNode::size(PhaseRegAlloc *ra_) const {
21279 assert(VerifyOops || MachNode::size(ra_) <= 0, "bad fixed size")do { if (!(VerifyOops || MachNode::size(ra_) <= 0)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 21278, "assert(" "VerifyOops || MachNode::size(ra_) <= 0"
") failed", "bad fixed size"); ::breakpoint(); } } while (0);
21280 return (VerifyOops ? MachNode::size(ra_) : 0);
21281}
21282
21283void membar_releaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21284 cbuf.set_insts_mark();
21285 // Start at oper_input_base() and count operands
21286 unsigned idx0 = 1;
21287 unsigned idx1 = 1; //
21288 // User did not define which encode class to use.
21289}
21290
21291uint membar_releaseNode::size(PhaseRegAlloc *ra_) const {
21292 assert(VerifyOops || MachNode::size(ra_) <= 0, "bad fixed size")do { if (!(VerifyOops || MachNode::size(ra_) <= 0)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 21291, "assert(" "VerifyOops || MachNode::size(ra_) <= 0"
") failed", "bad fixed size"); ::breakpoint(); } } while (0);
21293 return (VerifyOops ? MachNode::size(ra_) : 0);
21294}
21295
21296void membar_release_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21297 cbuf.set_insts_mark();
21298 // Start at oper_input_base() and count operands
21299 unsigned idx0 = 1;
21300 unsigned idx1 = 1; //
21301 // User did not define which encode class to use.
21302}
21303
21304uint membar_release_0Node::size(PhaseRegAlloc *ra_) const {
21305 assert(VerifyOops || MachNode::size(ra_) <= 0, "bad fixed size")do { if (!(VerifyOops || MachNode::size(ra_) <= 0)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 21304, "assert(" "VerifyOops || MachNode::size(ra_) <= 0"
") failed", "bad fixed size"); ::breakpoint(); } } while (0);
21306 return (VerifyOops ? MachNode::size(ra_) : 0);
21307}
21308
21309void membar_release_lockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21310 cbuf.set_insts_mark();
21311 // Start at oper_input_base() and count operands
21312 unsigned idx0 = 1;
21313 unsigned idx1 = 1; //
21314 // User did not define which encode class to use.
21315}
21316
21317uint membar_release_lockNode::size(PhaseRegAlloc *ra_) const {
21318 assert(VerifyOops || MachNode::size(ra_) <= 0, "bad fixed size")do { if (!(VerifyOops || MachNode::size(ra_) <= 0)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 21317, "assert(" "VerifyOops || MachNode::size(ra_) <= 0"
") failed", "bad fixed size"); ::breakpoint(); } } while (0);
21319 return (VerifyOops ? MachNode::size(ra_) : 0);
21320}
21321
21322void membar_volatileNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21323 cbuf.set_insts_mark();
21324 // Start at oper_input_base() and count operands
21325 unsigned idx0 = 1;
21326 unsigned idx1 = 1; //
21327 {
21328 C2_MacroAssembler _masm(&cbuf);
21329
21330#line 6770 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
21331
21332 ___masm. membar(Assembler::StoreLoad);
21333
21334#line 21334 "ad_x86.cpp"
21335 }
21336}
21337
21338void unnecessary_membar_volatileNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21339 cbuf.set_insts_mark();
21340 // Start at oper_input_base() and count operands
21341 unsigned idx0 = 1;
21342 unsigned idx1 = 1; //
21343 // User did not define which encode class to use.
21344}
21345
21346uint unnecessary_membar_volatileNode::size(PhaseRegAlloc *ra_) const {
21347 assert(VerifyOops || MachNode::size(ra_) <= 0, "bad fixed size")do { if (!(VerifyOops || MachNode::size(ra_) <= 0)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 21346, "assert(" "VerifyOops || MachNode::size(ra_) <= 0"
") failed", "bad fixed size"); ::breakpoint(); } } while (0);
21348 return (VerifyOops ? MachNode::size(ra_) : 0);
21349}
21350
21351void membar_storestoreNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21352 cbuf.set_insts_mark();
21353 // Start at oper_input_base() and count operands
21354 unsigned idx0 = 1;
21355 unsigned idx1 = 1; //
21356 // User did not define which encode class to use.
21357}
21358
21359uint membar_storestoreNode::size(PhaseRegAlloc *ra_) const {
21360 assert(VerifyOops || MachNode::size(ra_) <= 0, "bad fixed size")do { if (!(VerifyOops || MachNode::size(ra_) <= 0)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 21359, "assert(" "VerifyOops || MachNode::size(ra_) <= 0"
") failed", "bad fixed size"); ::breakpoint(); } } while (0);
21361 return (VerifyOops ? MachNode::size(ra_) : 0);
21362}
21363
21364void membar_storestore_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21365 cbuf.set_insts_mark();
21366 // Start at oper_input_base() and count operands
21367 unsigned idx0 = 1;
21368 unsigned idx1 = 1; //
21369 // User did not define which encode class to use.
21370}
21371
21372uint membar_storestore_0Node::size(PhaseRegAlloc *ra_) const {
21373 assert(VerifyOops || MachNode::size(ra_) <= 0, "bad fixed size")do { if (!(VerifyOops || MachNode::size(ra_) <= 0)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 21372, "assert(" "VerifyOops || MachNode::size(ra_) <= 0"
") failed", "bad fixed size"); ::breakpoint(); } } while (0);
21374 return (VerifyOops ? MachNode::size(ra_) : 0);
21375}
21376
21377void castX2PNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21378 cbuf.set_insts_mark();
21379 // Start at oper_input_base() and count operands
21380 unsigned idx0 = 1;
21381 unsigned idx1 = 1; // src
21382 {
21383 C2_MacroAssembler _masm(&cbuf);
21384
21385#line 6806 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
21386
21387 if (opnd_array(0)->reg(ra_,this)/* dst */!= opnd_array(1)->reg(ra_,this,idx1)/* src */) {
21388 ___masm. movptr(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
21389 }
21390
21391#line 21391 "ad_x86.cpp"
21392 }
21393}
21394
21395void castP2XNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21396 cbuf.set_insts_mark();
21397 // Start at oper_input_base() and count operands
21398 unsigned idx0 = 1;
21399 unsigned idx1 = 1; // src
21400 {
21401 C2_MacroAssembler _masm(&cbuf);
21402
21403#line 6819 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
21404
21405 if (opnd_array(0)->reg(ra_,this)/* dst */!= opnd_array(1)->reg(ra_,this,idx1)/* src */) {
21406 ___masm. movptr(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
21407 }
21408
21409#line 21409 "ad_x86.cpp"
21410 }
21411}
21412
21413void convP2INode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21414 cbuf.set_insts_mark();
21415 // Start at oper_input_base() and count operands
21416 unsigned idx0 = 1;
21417 unsigned idx1 = 1; // src
21418 {
21419 C2_MacroAssembler _masm(&cbuf);
21420
21421#line 6833 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
21422
21423 ___masm. movl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
21424
21425#line 21425 "ad_x86.cpp"
21426 }
21427}
21428
21429void convN2INode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21430 cbuf.set_insts_mark();
21431 // Start at oper_input_base() and count operands
21432 unsigned idx0 = 1;
21433 unsigned idx1 = 1; // src
21434 {
21435 C2_MacroAssembler _masm(&cbuf);
21436
21437#line 6847 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
21438
21439 ___masm. movl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
21440
21441#line 21441 "ad_x86.cpp"
21442 }
21443}
21444
21445void encodeHeapOopNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21446 cbuf.set_insts_mark();
21447 // Start at oper_input_base() and count operands
21448 unsigned idx0 = 1;
21449 unsigned idx1 = 1; // src
21450 {
21451 C2_MacroAssembler _masm(&cbuf);
21452
21453#line 6859 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
21454
21455 Register s = opnd_array(1)->as_Register(ra_,this,idx1)/* src */;
21456 Register d = opnd_array(0)->as_Register(ra_,this)/* dst */;
21457 if (s != d) {
21458 ___masm. movq(d, s);
21459 }
21460 ___masm. encode_heap_oop(d);
21461
21462#line 21462 "ad_x86.cpp"
21463 }
21464}
21465
21466void encodeHeapOop_not_nullNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21467 cbuf.set_insts_mark();
21468 // Start at oper_input_base() and count operands
21469 unsigned idx0 = 1;
21470 unsigned idx1 = 1; // src
21471 {
21472 C2_MacroAssembler _masm(&cbuf);
21473
21474#line 6875 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
21475
21476 ___masm. encode_heap_oop_not_null(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
21477
21478#line 21478 "ad_x86.cpp"
21479 }
21480}
21481
21482void decodeHeapOopNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21483 cbuf.set_insts_mark();
21484 // Start at oper_input_base() and count operands
21485 unsigned idx0 = 1;
21486 unsigned idx1 = 1; // src
21487 {
21488 C2_MacroAssembler _masm(&cbuf);
21489
21490#line 6887 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
21491
21492 Register s = opnd_array(1)->as_Register(ra_,this,idx1)/* src */;
21493 Register d = opnd_array(0)->as_Register(ra_,this)/* dst */;
21494 if (s != d) {
21495 ___masm. movq(d, s);
21496 }
21497 ___masm. decode_heap_oop(d);
21498
21499#line 21499 "ad_x86.cpp"
21500 }
21501}
21502
21503void decodeHeapOop_not_nullNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21504 cbuf.set_insts_mark();
21505 // Start at oper_input_base() and count operands
21506 unsigned idx0 = 1;
21507 unsigned idx1 = 1; // src
21508 {
21509 C2_MacroAssembler _masm(&cbuf);
21510
21511#line 6904 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
21512
21513 Register s = opnd_array(1)->as_Register(ra_,this,idx1)/* src */;
21514 Register d = opnd_array(0)->as_Register(ra_,this)/* dst */;
21515 if (s != d) {
21516 ___masm. decode_heap_oop_not_null(d, s);
21517 } else {
21518 ___masm. decode_heap_oop_not_null(d);
21519 }
21520
21521#line 21521 "ad_x86.cpp"
21522 }
21523}
21524
21525void encodeKlass_not_nullNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21526 cbuf.set_insts_mark();
21527 // Start at oper_input_base() and count operands
21528 unsigned idx0 = 1;
21529 unsigned idx1 = 1; // src
21530 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
21531 {
21532 C2_MacroAssembler _masm(&cbuf);
21533
21534#line 6920 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
21535
21536 ___masm. encode_and_move_klass_not_null(opnd_array(2)->as_Register(ra_,this,idx2)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
21537
21538#line 21538 "ad_x86.cpp"
21539 }
21540}
21541
21542void decodeKlass_not_nullNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21543 cbuf.set_insts_mark();
21544 // Start at oper_input_base() and count operands
21545 unsigned idx0 = 1;
21546 unsigned idx1 = 1; // src
21547 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
21548 {
21549 C2_MacroAssembler _masm(&cbuf);
21550
21551#line 6930 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
21552
21553 ___masm. decode_and_move_klass_not_null(opnd_array(2)->as_Register(ra_,this,idx2)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
21554
21555#line 21555 "ad_x86.cpp"
21556 }
21557}
21558
21559void jumpXtnd_offsetNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21560 cbuf.set_insts_mark();
21561 ra_->C->output()->constant_table().fill_jump_table(cbuf, (MachConstantNode*) this, _index2label);
21562 // Start at oper_input_base() and count operands
21563 unsigned idx0 = 1;
21564 unsigned idx1 = 1; // shift
21565 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dest
21566 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); //
21567 {
21568 C2_MacroAssembler _masm(&cbuf);
21569
21570#line 6947 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
21571
21572 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
21573 // to do that and the compiler is using that register as one it can allocate.
21574 // So we build it all by hand.
21575 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant);
21576 // ArrayAddress dispatch(table, index);
21577 Address dispatch(opnd_array(3)->as_Register(ra_,this,idx3)/* dest */, opnd_array(1)->as_Register(ra_,this,idx1)/* switch_val */, (Address::ScaleFactor) opnd_array(2)->constant());
21578 ___masm. lea(opnd_array(3)->as_Register(ra_,this,idx3)/* dest */, InternalAddress(___masm. code()->consts()->start() + constant_offset()));
21579 ___masm. jmp(dispatch);
21580
21581#line 21581 "ad_x86.cpp"
21582 }
21583}
21584
21585void jumpXtnd_offsetNode::eval_constant(Compile* C) {
21586 _constant = C->output()->constant_table().add_jump_table(this);
21587 // User did not define an encode section.
21588}
21589void jumpXtnd_addrNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21590 cbuf.set_insts_mark();
21591 ra_->C->output()->constant_table().fill_jump_table(cbuf, (MachConstantNode*) this, _index2label);
21592 // Start at oper_input_base() and count operands
21593 unsigned idx0 = 1;
21594 unsigned idx1 = 1; // shift
21595 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // offset
21596 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dest
21597 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); //
21598 {
21599 C2_MacroAssembler _masm(&cbuf);
21600
21601#line 6967 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
21602
21603 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
21604 // to do that and the compiler is using that register as one it can allocate.
21605 // So we build it all by hand.
21606 // Address index(noreg, switch_reg, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
21607 // ArrayAddress dispatch(table, index);
21608 Address dispatch(opnd_array(4)->as_Register(ra_,this,idx4)/* dest */, opnd_array(1)->as_Register(ra_,this,idx1)/* switch_val */, (Address::ScaleFactor) opnd_array(2)->constant(), (int) opnd_array(3)->constantL());
21609 ___masm. lea(opnd_array(4)->as_Register(ra_,this,idx4)/* dest */, InternalAddress(___masm. code()->consts()->start() + constant_offset()));
21610 ___masm. jmp(dispatch);
21611
21612#line 21612 "ad_x86.cpp"
21613 }
21614}
21615
21616void jumpXtnd_addrNode::eval_constant(Compile* C) {
21617 _constant = C->output()->constant_table().add_jump_table(this);
21618 // User did not define an encode section.
21619}
21620void jumpXtndNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21621 cbuf.set_insts_mark();
21622 ra_->C->output()->constant_table().fill_jump_table(cbuf, (MachConstantNode*) this, _index2label);
21623 // Start at oper_input_base() and count operands
21624 unsigned idx0 = 1;
21625 unsigned idx1 = 1; // dest
21626 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); //
21627 {
21628 C2_MacroAssembler _masm(&cbuf);
21629
21630#line 6987 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
21631
21632 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
21633 // to do that and the compiler is using that register as one it can allocate.
21634 // So we build it all by hand.
21635 // Address index(noreg, switch_reg, Address::times_1);
21636 // ArrayAddress dispatch(table, index);
21637 Address dispatch(opnd_array(2)->as_Register(ra_,this,idx2)/* dest */, opnd_array(1)->as_Register(ra_,this,idx1)/* switch_val */, Address::times_1);
21638 ___masm. lea(opnd_array(2)->as_Register(ra_,this,idx2)/* dest */, InternalAddress(___masm. code()->consts()->start() + constant_offset()));
21639 ___masm. jmp(dispatch);
21640
21641#line 21641 "ad_x86.cpp"
21642 }
21643}
21644
21645void jumpXtndNode::eval_constant(Compile* C) {
21646 _constant = C->output()->constant_table().add_jump_table(this);
21647 // User did not define an encode section.
21648}
21649void cmovI_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21650 cbuf.set_insts_mark();
21651 // Start at oper_input_base() and count operands
21652 unsigned idx0 = 1;
21653 unsigned idx1 = 1; // cop
21654 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
21655 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
21656 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src
21657 {
21658 C2_MacroAssembler _masm(&cbuf);
21659
21660#line 7007 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
21661
21662 ___masm. cmovl((Assembler::Condition)(opnd_array(1)->ccode()), opnd_array(3)->as_Register(ra_,this,idx3)/* dst */, opnd_array(4)->as_Register(ra_,this,idx4)/* src */);
21663
21664#line 21664 "ad_x86.cpp"
21665 }
21666}
21667
21668void cmovI_regUNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21669 cbuf.set_insts_mark();
21670 // Start at oper_input_base() and count operands
21671 unsigned idx0 = 1;
21672 unsigned idx1 = 1; // cop
21673 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
21674 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
21675 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src
21676 {
21677 C2_MacroAssembler _masm(&cbuf);
21678
21679#line 7018 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
21680
21681 ___masm. cmovl((Assembler::Condition)(opnd_array(1)->ccode()), opnd_array(3)->as_Register(ra_,this,idx3)/* dst */, opnd_array(4)->as_Register(ra_,this,idx4)/* src */);
21682
21683#line 21683 "ad_x86.cpp"
21684 }
21685}
21686
21687void cmovI_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21688 cbuf.set_insts_mark();
21689 // Start at oper_input_base() and count operands
21690 unsigned idx0 = 2;
21691 unsigned idx1 = 2; // cop
21692 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
21693 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
21694 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src
21695 {
21696 C2_MacroAssembler _masm(&cbuf);
21697
21698#line 7038 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
21699
21700 ___masm. cmovl((Assembler::Condition)(opnd_array(1)->ccode()), opnd_array(3)->as_Register(ra_,this,idx3)/* dst */, Address::make_raw(opnd_array(4)->base(ra_,this,idx4), opnd_array(4)->index(ra_,this,idx4), opnd_array(4)->scale(), opnd_array(4)->disp(ra_,this,idx4), opnd_array(4)->disp_reloc()));
21701
21702#line 21702 "ad_x86.cpp"
21703 }
21704}
21705
21706void cmovI_memUNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21707 cbuf.set_insts_mark();
21708 // Start at oper_input_base() and count operands
21709 unsigned idx0 = 2;
21710 unsigned idx1 = 2; // cop
21711 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
21712 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
21713 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src
21714 {
21715 C2_MacroAssembler _masm(&cbuf);
21716
21717#line 7051 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
21718
21719 ___masm. cmovl((Assembler::Condition)(opnd_array(1)->ccode()), opnd_array(3)->as_Register(ra_,this,idx3)/* dst */, Address::make_raw(opnd_array(4)->base(ra_,this,idx4), opnd_array(4)->index(ra_,this,idx4), opnd_array(4)->scale(), opnd_array(4)->disp(ra_,this,idx4), opnd_array(4)->disp_reloc()));
21720
21721#line 21721 "ad_x86.cpp"
21722 }
21723}
21724
21725void cmovN_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21726 cbuf.set_insts_mark();
21727 // Start at oper_input_base() and count operands
21728 unsigned idx0 = 1;
21729 unsigned idx1 = 1; // cop
21730 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
21731 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
21732 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src
21733 {
21734 C2_MacroAssembler _masm(&cbuf);
21735
21736#line 7072 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
21737
21738 ___masm. cmovl((Assembler::Condition)(opnd_array(1)->ccode()), opnd_array(3)->as_Register(ra_,this,idx3)/* dst */, opnd_array(4)->as_Register(ra_,this,idx4)/* src */);
21739
21740#line 21740 "ad_x86.cpp"
21741 }
21742}
21743
21744void cmovN_regUNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21745 cbuf.set_insts_mark();
21746 // Start at oper_input_base() and count operands
21747 unsigned idx0 = 1;
21748 unsigned idx1 = 1; // cop
21749 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
21750 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
21751 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src
21752 {
21753 C2_MacroAssembler _masm(&cbuf);
21754
21755#line 7085 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
21756
21757 ___masm. cmovl((Assembler::Condition)(opnd_array(1)->ccode()), opnd_array(3)->as_Register(ra_,this,idx3)/* dst */, opnd_array(4)->as_Register(ra_,this,idx4)/* src */);
21758
21759#line 21759 "ad_x86.cpp"
21760 }
21761}
21762
21763void cmovP_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21764 cbuf.set_insts_mark();
21765 // Start at oper_input_base() and count operands
21766 unsigned idx0 = 1;
21767 unsigned idx1 = 1; // cop
21768 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
21769 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
21770 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src
21771 {
21772 C2_MacroAssembler _masm(&cbuf);
21773
21774#line 7106 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
21775
21776 ___masm. cmovq((Assembler::Condition)(opnd_array(1)->ccode()), opnd_array(3)->as_Register(ra_,this,idx3)/* dst */, opnd_array(4)->as_Register(ra_,this,idx4)/* src */);
21777
21778#line 21778 "ad_x86.cpp"
21779 }
21780}
21781
21782void cmovP_regUNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21783 cbuf.set_insts_mark();
21784 // Start at oper_input_base() and count operands
21785 unsigned idx0 = 1;
21786 unsigned idx1 = 1; // cop
21787 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
21788 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
21789 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src
21790 {
21791 C2_MacroAssembler _masm(&cbuf);
21792
21793#line 7119 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
21794
21795 ___masm. cmovq((Assembler::Condition)(opnd_array(1)->ccode()), opnd_array(3)->as_Register(ra_,this,idx3)/* dst */, opnd_array(4)->as_Register(ra_,this,idx4)/* src */);
21796
21797#line 21797 "ad_x86.cpp"
21798 }
21799}
21800
21801void cmovL_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21802 cbuf.set_insts_mark();
21803 // Start at oper_input_base() and count operands
21804 unsigned idx0 = 1;
21805 unsigned idx1 = 1; // cop
21806 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
21807 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
21808 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src
21809 {
21810 C2_MacroAssembler _masm(&cbuf);
21811
21812#line 7166 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
21813
21814 ___masm. cmovq((Assembler::Condition)(opnd_array(1)->ccode()), opnd_array(3)->as_Register(ra_,this,idx3)/* dst */, opnd_array(4)->as_Register(ra_,this,idx4)/* src */);
21815
21816#line 21816 "ad_x86.cpp"
21817 }
21818}
21819
21820void cmovL_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21821 cbuf.set_insts_mark();
21822 // Start at oper_input_base() and count operands
21823 unsigned idx0 = 2;
21824 unsigned idx1 = 2; // cop
21825 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
21826 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
21827 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src
21828 {
21829 C2_MacroAssembler _masm(&cbuf);
21830
21831#line 7178 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
21832
21833 ___masm. cmovq((Assembler::Condition)(opnd_array(1)->ccode()), opnd_array(3)->as_Register(ra_,this,idx3)/* dst */, Address::make_raw(opnd_array(4)->base(ra_,this,idx4), opnd_array(4)->index(ra_,this,idx4), opnd_array(4)->scale(), opnd_array(4)->disp(ra_,this,idx4), opnd_array(4)->disp_reloc()));
21834
21835#line 21835 "ad_x86.cpp"
21836 }
21837}
21838
21839void cmovL_regUNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21840 cbuf.set_insts_mark();
21841 // Start at oper_input_base() and count operands
21842 unsigned idx0 = 1;
21843 unsigned idx1 = 1; // cop
21844 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
21845 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
21846 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src
21847 {
21848 C2_MacroAssembler _masm(&cbuf);
21849
21850#line 7190 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
21851
21852 ___masm. cmovq((Assembler::Condition)(opnd_array(1)->ccode()), opnd_array(3)->as_Register(ra_,this,idx3)/* dst */, opnd_array(4)->as_Register(ra_,this,idx4)/* src */);
21853
21854#line 21854 "ad_x86.cpp"
21855 }
21856}
21857
21858void cmovL_memUNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21859 cbuf.set_insts_mark();
21860 // Start at oper_input_base() and count operands
21861 unsigned idx0 = 2;
21862 unsigned idx1 = 2; // cop
21863 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
21864 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
21865 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src
21866 {
21867 C2_MacroAssembler _masm(&cbuf);
21868
21869#line 7210 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
21870
21871 ___masm. cmovq((Assembler::Condition)(opnd_array(1)->ccode()), opnd_array(3)->as_Register(ra_,this,idx3)/* dst */, Address::make_raw(opnd_array(4)->base(ra_,this,idx4), opnd_array(4)->index(ra_,this,idx4), opnd_array(4)->scale(), opnd_array(4)->disp(ra_,this,idx4), opnd_array(4)->disp_reloc()));
21872
21873#line 21873 "ad_x86.cpp"
21874 }
21875}
21876
21877void cmovF_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21878 cbuf.set_insts_mark();
21879 // Start at oper_input_base() and count operands
21880 unsigned idx0 = 1;
21881 unsigned idx1 = 1; // cop
21882 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
21883 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
21884 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src
21885 {
21886 C2_MacroAssembler _masm(&cbuf);
21887
21888#line 7232 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
21889
21890 Label Lskip;
21891 // Invert sense of branch from sense of CMOV
21892 ___masm. jccb((Assembler::Condition)(opnd_array(1)->ccode()^1), Lskip)jccb_0((Assembler::Condition)(opnd_array(1)->ccode()^1), Lskip
, "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 7235);
21893 ___masm. movflt(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* src */);
21894 ___masm. bind(Lskip);
21895
21896#line 21896 "ad_x86.cpp"
21897 }
21898}
21899
21900void cmovF_regUNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21901 cbuf.set_insts_mark();
21902 // Start at oper_input_base() and count operands
21903 unsigned idx0 = 1;
21904 unsigned idx1 = 1; // cop
21905 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
21906 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
21907 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src
21908 {
21909 C2_MacroAssembler _masm(&cbuf);
21910
21911#line 7262 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
21912
21913 Label Lskip;
21914 // Invert sense of branch from sense of CMOV
21915 ___masm. jccb((Assembler::Condition)(opnd_array(1)->ccode()^1), Lskip)jccb_0((Assembler::Condition)(opnd_array(1)->ccode()^1), Lskip
, "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 7265);
21916 ___masm. movflt(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* src */);
21917 ___masm. bind(Lskip);
21918
21919#line 21919 "ad_x86.cpp"
21920 }
21921}
21922
21923void cmovD_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21924 cbuf.set_insts_mark();
21925 // Start at oper_input_base() and count operands
21926 unsigned idx0 = 1;
21927 unsigned idx1 = 1; // cop
21928 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
21929 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
21930 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src
21931 {
21932 C2_MacroAssembler _masm(&cbuf);
21933
21934#line 7288 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
21935
21936 Label Lskip;
21937 // Invert sense of branch from sense of CMOV
21938 ___masm. jccb((Assembler::Condition)(opnd_array(1)->ccode()^1), Lskip)jccb_0((Assembler::Condition)(opnd_array(1)->ccode()^1), Lskip
, "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 7291);
21939 ___masm. movdbl(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* src */);
21940 ___masm. bind(Lskip);
21941
21942#line 21942 "ad_x86.cpp"
21943 }
21944}
21945
21946void cmovD_regUNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21947 cbuf.set_insts_mark();
21948 // Start at oper_input_base() and count operands
21949 unsigned idx0 = 1;
21950 unsigned idx1 = 1; // cop
21951 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
21952 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
21953 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src
21954 {
21955 C2_MacroAssembler _masm(&cbuf);
21956
21957#line 7306 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
21958
21959 Label Lskip;
21960 // Invert sense of branch from sense of CMOV
21961 ___masm. jccb((Assembler::Condition)(opnd_array(1)->ccode()^1), Lskip)jccb_0((Assembler::Condition)(opnd_array(1)->ccode()^1), Lskip
, "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 7309);
21962 ___masm. movdbl(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* src */);
21963 ___masm. bind(Lskip);
21964
21965#line 21965 "ad_x86.cpp"
21966 }
21967}
21968
21969void addI_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21970 cbuf.set_insts_mark();
21971 // Start at oper_input_base() and count operands
21972 unsigned idx0 = 1;
21973 unsigned idx1 = 1; // dst
21974 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
21975 {
21976 C2_MacroAssembler _masm(&cbuf);
21977
21978#line 7333 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
21979
21980 ___masm. addl(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, opnd_array(2)->as_Register(ra_,this,idx2)/* src */);
21981
21982#line 21982 "ad_x86.cpp"
21983 }
21984}
21985
21986void addI_rReg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
21987 cbuf.set_insts_mark();
21988 // Start at oper_input_base() and count operands
21989 unsigned idx0 = 1;
21990 unsigned idx1 = 1; // dst
21991 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
21992 {
21993 C2_MacroAssembler _masm(&cbuf);
21994
21995#line 7345 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
21996
21997 ___masm. addl(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, opnd_array(2)->constant());
21998
21999#line 21999 "ad_x86.cpp"
22000 }
22001}
22002
22003void addI_rReg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22004 cbuf.set_insts_mark();
22005 // Start at oper_input_base() and count operands
22006 unsigned idx0 = 2;
22007 unsigned idx1 = 2; // dst
22008 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
22009 {
22010 C2_MacroAssembler _masm(&cbuf);
22011
22012#line 7358 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
22013
22014 ___masm. addl(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
22015
22016#line 22016 "ad_x86.cpp"
22017 }
22018}
22019
22020void addI_rReg_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22021 cbuf.set_insts_mark();
22022 // Start at oper_input_base() and count operands
22023 unsigned idx0 = 2;
22024 unsigned idx1 = 2; // src
22025 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
22026 {
22027 C2_MacroAssembler _masm(&cbuf);
22028
22029#line 7358 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
22030
22031 ___masm. addl(opnd_array(2)->as_Register(ra_,this,idx2)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
22032
22033#line 22033 "ad_x86.cpp"
22034 }
22035}
22036
22037void addI_mem_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22038 cbuf.set_insts_mark();
22039 // Start at oper_input_base() and count operands
22040 unsigned idx0 = 2;
22041 unsigned idx1 = 2; // dst
22042 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
22043 {
22044 C2_MacroAssembler _masm(&cbuf);
22045
22046#line 7371 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
22047
22048 ___masm. addl(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_Register(ra_,this,idx2)/* src */);
22049
22050#line 22050 "ad_x86.cpp"
22051 }
22052}
22053
22054void addI_mem_rReg_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22055 cbuf.set_insts_mark();
22056 // Start at oper_input_base() and count operands
22057 unsigned idx0 = 2;
22058 unsigned idx1 = 2; // dst
22059 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
22060 {
22061 C2_MacroAssembler _masm(&cbuf);
22062
22063#line 7371 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
22064
22065 ___masm. addl(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_Register(ra_,this,idx2)/* src */);
22066
22067#line 22067 "ad_x86.cpp"
22068 }
22069}
22070
22071void addI_mem_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22072 cbuf.set_insts_mark();
22073 // Start at oper_input_base() and count operands
22074 unsigned idx0 = 2;
22075 unsigned idx1 = 2; // dst
22076 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
22077 {
22078 C2_MacroAssembler _masm(&cbuf);
22079
22080#line 7384 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
22081
22082 ___masm. addl(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->constant());
22083
22084#line 22084 "ad_x86.cpp"
22085 }
22086}
22087
22088void incI_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22089 cbuf.set_insts_mark();
22090 // Start at oper_input_base() and count operands
22091 unsigned idx0 = 1;
22092 unsigned idx1 = 1; // dst
22093 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
22094 {
22095 C2_MacroAssembler _masm(&cbuf);
22096
22097#line 7397 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
22098
22099 ___masm. incrementl(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */);
22100
22101#line 22101 "ad_x86.cpp"
22102 }
22103}
22104
22105void incI_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22106 cbuf.set_insts_mark();
22107 // Start at oper_input_base() and count operands
22108 unsigned idx0 = 2;
22109 unsigned idx1 = 2; // dst
22110 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
22111 {
22112 C2_MacroAssembler _masm(&cbuf);
22113
22114#line 7411 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
22115
22116 ___masm. incrementl(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
22117
22118#line 22118 "ad_x86.cpp"
22119 }
22120}
22121
22122void decI_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22123 cbuf.set_insts_mark();
22124 // Start at oper_input_base() and count operands
22125 unsigned idx0 = 1;
22126 unsigned idx1 = 1; // dst
22127 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
22128 {
22129 C2_MacroAssembler _masm(&cbuf);
22130
22131#line 7425 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
22132
22133 ___masm. decrementl(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */);
22134
22135#line 22135 "ad_x86.cpp"
22136 }
22137}
22138
22139void decI_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22140 cbuf.set_insts_mark();
22141 // Start at oper_input_base() and count operands
22142 unsigned idx0 = 2;
22143 unsigned idx1 = 2; // dst
22144 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
22145 {
22146 C2_MacroAssembler _masm(&cbuf);
22147
22148#line 7440 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
22149
22150 ___masm. decrementl(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
22151
22152#line 22152 "ad_x86.cpp"
22153 }
22154}
22155
22156void leaI_rReg_immINode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22157 cbuf.set_insts_mark();
22158 // Start at oper_input_base() and count operands
22159 unsigned idx0 = 1;
22160 unsigned idx1 = 1; // src0
22161 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src1
22162 {
22163 C2_MacroAssembler _masm(&cbuf);
22164
22165#line 7452 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
22166
22167 ___masm. leal(opnd_array(0)->as_Register(ra_,this)/* dst */, Address(opnd_array(1)->as_Register(ra_,this,idx1)/* src0 */, opnd_array(2)->constant()));
22168
22169#line 22169 "ad_x86.cpp"
22170 }
22171}
22172
22173void addL_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22174 cbuf.set_insts_mark();
22175 // Start at oper_input_base() and count operands
22176 unsigned idx0 = 1;
22177 unsigned idx1 = 1; // dst
22178 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
22179 {
22180 C2_MacroAssembler _masm(&cbuf);
22181
22182#line 7464 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
22183
22184 ___masm. addq(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, opnd_array(2)->as_Register(ra_,this,idx2)/* src */);
22185
22186#line 22186 "ad_x86.cpp"
22187 }
22188}
22189
22190void addL_rReg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22191 cbuf.set_insts_mark();
22192 // Start at oper_input_base() and count operands
22193 unsigned idx0 = 1;
22194 unsigned idx1 = 1; // dst
22195 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
22196 {
22197 C2_MacroAssembler _masm(&cbuf);
22198
22199#line 7476 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
22200
22201 ___masm. addq(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, opnd_array(2)->constantL());
22202
22203#line 22203 "ad_x86.cpp"
22204 }
22205}
22206
22207void addL_rReg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22208 cbuf.set_insts_mark();
22209 // Start at oper_input_base() and count operands
22210 unsigned idx0 = 2;
22211 unsigned idx1 = 2; // dst
22212 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
22213 {
22214 C2_MacroAssembler _masm(&cbuf);
22215
22216#line 7489 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
22217
22218 ___masm. addq(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
22219
22220#line 22220 "ad_x86.cpp"
22221 }
22222}
22223
22224void addL_rReg_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22225 cbuf.set_insts_mark();
22226 // Start at oper_input_base() and count operands
22227 unsigned idx0 = 2;
22228 unsigned idx1 = 2; // src
22229 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
22230 {
22231 C2_MacroAssembler _masm(&cbuf);
22232
22233#line 7489 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
22234
22235 ___masm. addq(opnd_array(2)->as_Register(ra_,this,idx2)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
22236
22237#line 22237 "ad_x86.cpp"
22238 }
22239}
22240
22241void addL_mem_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22242 cbuf.set_insts_mark();
22243 // Start at oper_input_base() and count operands
22244 unsigned idx0 = 2;
22245 unsigned idx1 = 2; // dst
22246 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
22247 {
22248 C2_MacroAssembler _masm(&cbuf);
22249
22250#line 7502 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
22251
22252 ___masm. addq(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_Register(ra_,this,idx2)/* src */);
22253
22254#line 22254 "ad_x86.cpp"
22255 }
22256}
22257
22258void addL_mem_rReg_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22259 cbuf.set_insts_mark();
22260 // Start at oper_input_base() and count operands
22261 unsigned idx0 = 2;
22262 unsigned idx1 = 2; // dst
22263 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
22264 {
22265 C2_MacroAssembler _masm(&cbuf);
22266
22267#line 7502 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
22268
22269 ___masm. addq(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_Register(ra_,this,idx2)/* src */);
22270
22271#line 22271 "ad_x86.cpp"
22272 }
22273}
22274
22275void addL_mem_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22276 cbuf.set_insts_mark();
22277 // Start at oper_input_base() and count operands
22278 unsigned idx0 = 2;
22279 unsigned idx1 = 2; // dst
22280 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
22281 {
22282 C2_MacroAssembler _masm(&cbuf);
22283
22284#line 7515 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
22285
22286 ___masm. addq(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->constantL());
22287
22288#line 22288 "ad_x86.cpp"
22289 }
22290}
22291
22292void incL_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22293 cbuf.set_insts_mark();
22294 // Start at oper_input_base() and count operands
22295 unsigned idx0 = 1;
22296 unsigned idx1 = 1; // dst
22297 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
22298 {
22299 C2_MacroAssembler _masm(&cbuf);
22300
22301#line 7528 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
22302
22303 ___masm. incrementq(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */);
22304
22305#line 22305 "ad_x86.cpp"
22306 }
22307}
22308
22309void incL_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22310 cbuf.set_insts_mark();
22311 // Start at oper_input_base() and count operands
22312 unsigned idx0 = 2;
22313 unsigned idx1 = 2; // dst
22314 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
22315 {
22316 C2_MacroAssembler _masm(&cbuf);
22317
22318#line 7542 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
22319
22320 ___masm. incrementq(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
22321
22322#line 22322 "ad_x86.cpp"
22323 }
22324}
22325
22326void decL_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22327 cbuf.set_insts_mark();
22328 // Start at oper_input_base() and count operands
22329 unsigned idx0 = 1;
22330 unsigned idx1 = 1; // dst
22331 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
22332 {
22333 C2_MacroAssembler _masm(&cbuf);
22334
22335#line 7556 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
22336
22337 ___masm. decrementq(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */);
22338
22339#line 22339 "ad_x86.cpp"
22340 }
22341}
22342
22343void decL_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22344 cbuf.set_insts_mark();
22345 // Start at oper_input_base() and count operands
22346 unsigned idx0 = 2;
22347 unsigned idx1 = 2; // dst
22348 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
22349 {
22350 C2_MacroAssembler _masm(&cbuf);
22351
22352#line 7571 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
22353
22354 ___masm. decrementq(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
22355
22356#line 22356 "ad_x86.cpp"
22357 }
22358}
22359
22360void leaL_rReg_immLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22361 cbuf.set_insts_mark();
22362 // Start at oper_input_base() and count operands
22363 unsigned idx0 = 1;
22364 unsigned idx1 = 1; // src0
22365 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src1
22366 {
22367 C2_MacroAssembler _masm(&cbuf);
22368
22369#line 7583 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
22370
22371 ___masm. leaq(opnd_array(0)->as_Register(ra_,this)/* dst */, Address(opnd_array(1)->as_Register(ra_,this,idx1)/* src0 */, opnd_array(2)->constantL()));
22372
22373#line 22373 "ad_x86.cpp"
22374 }
22375}
22376
22377void addP_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22378 cbuf.set_insts_mark();
22379 // Start at oper_input_base() and count operands
22380 unsigned idx0 = 2;
22381 unsigned idx1 = 2; // dst
22382 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
22383 {
22384 C2_MacroAssembler _masm(&cbuf);
22385
22386#line 7595 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
22387
22388 ___masm. addq(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, opnd_array(2)->as_Register(ra_,this,idx2)/* src */);
22389
22390#line 22390 "ad_x86.cpp"
22391 }
22392}
22393
22394void addP_rReg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22395 cbuf.set_insts_mark();
22396 // Start at oper_input_base() and count operands
22397 unsigned idx0 = 2;
22398 unsigned idx1 = 2; // dst
22399 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
22400 {
22401 C2_MacroAssembler _masm(&cbuf);
22402
22403#line 7607 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
22404
22405 ___masm. addq(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, opnd_array(2)->constantL());
22406
22407#line 22407 "ad_x86.cpp"
22408 }
22409}
22410
22411void leaP_rReg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22412 cbuf.set_insts_mark();
22413 // Start at oper_input_base() and count operands
22414 unsigned idx0 = 2;
22415 unsigned idx1 = 2; // src0
22416 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src1
22417 {
22418 C2_MacroAssembler _masm(&cbuf);
22419
22420#line 7621 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
22421
22422 ___masm. leaq(opnd_array(0)->as_Register(ra_,this)/* dst */, Address(opnd_array(1)->as_Register(ra_,this,idx1)/* src0 */, opnd_array(2)->constantL()));
22423
22424#line 22424 "ad_x86.cpp"
22425 }
22426}
22427
22428void checkCastPPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22429 cbuf.set_insts_mark();
22430 // Start at oper_input_base() and count operands
22431 unsigned idx0 = 1;
22432 unsigned idx1 = 1; // dst
22433 // User did not define which encode class to use.
22434}
22435
22436uint checkCastPPNode::size(PhaseRegAlloc *ra_) const {
22437 assert(VerifyOops || MachNode::size(ra_) <= 0, "bad fixed size")do { if (!(VerifyOops || MachNode::size(ra_) <= 0)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 22436, "assert(" "VerifyOops || MachNode::size(ra_) <= 0"
") failed", "bad fixed size"); ::breakpoint(); } } while (0);
22438 return (VerifyOops ? MachNode::size(ra_) : 0);
22439}
22440
22441void castPPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22442 cbuf.set_insts_mark();
22443 // Start at oper_input_base() and count operands
22444 unsigned idx0 = 1;
22445 unsigned idx1 = 1; // dst
22446 // User did not define which encode class to use.
22447}
22448
22449uint castPPNode::size(PhaseRegAlloc *ra_) const {
22450 assert(VerifyOops || MachNode::size(ra_) <= 0, "bad fixed size")do { if (!(VerifyOops || MachNode::size(ra_) <= 0)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 22449, "assert(" "VerifyOops || MachNode::size(ra_) <= 0"
") failed", "bad fixed size"); ::breakpoint(); } } while (0);
22451 return (VerifyOops ? MachNode::size(ra_) : 0);
22452}
22453
22454void castIINode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22455 cbuf.set_insts_mark();
22456 // Start at oper_input_base() and count operands
22457 unsigned idx0 = 1;
22458 unsigned idx1 = 1; // dst
22459 // User did not define which encode class to use.
22460}
22461
22462uint castIINode::size(PhaseRegAlloc *ra_) const {
22463 assert(VerifyOops || MachNode::size(ra_) <= 0, "bad fixed size")do { if (!(VerifyOops || MachNode::size(ra_) <= 0)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 22462, "assert(" "VerifyOops || MachNode::size(ra_) <= 0"
") failed", "bad fixed size"); ::breakpoint(); } } while (0);
22464 return (VerifyOops ? MachNode::size(ra_) : 0);
22465}
22466
22467void castLLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22468 cbuf.set_insts_mark();
22469 // Start at oper_input_base() and count operands
22470 unsigned idx0 = 1;
22471 unsigned idx1 = 1; // dst
22472 // User did not define which encode class to use.
22473}
22474
22475uint castLLNode::size(PhaseRegAlloc *ra_) const {
22476 assert(VerifyOops || MachNode::size(ra_) <= 0, "bad fixed size")do { if (!(VerifyOops || MachNode::size(ra_) <= 0)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 22475, "assert(" "VerifyOops || MachNode::size(ra_) <= 0"
") failed", "bad fixed size"); ::breakpoint(); } } while (0);
22477 return (VerifyOops ? MachNode::size(ra_) : 0);
22478}
22479
22480void castFFNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22481 cbuf.set_insts_mark();
22482 // Start at oper_input_base() and count operands
22483 unsigned idx0 = 1;
22484 unsigned idx1 = 1; // dst
22485 // User did not define which encode class to use.
22486}
22487
22488uint castFFNode::size(PhaseRegAlloc *ra_) const {
22489 assert(VerifyOops || MachNode::size(ra_) <= 0, "bad fixed size")do { if (!(VerifyOops || MachNode::size(ra_) <= 0)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 22488, "assert(" "VerifyOops || MachNode::size(ra_) <= 0"
") failed", "bad fixed size"); ::breakpoint(); } } while (0);
22490 return (VerifyOops ? MachNode::size(ra_) : 0);
22491}
22492
22493void castDDNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22494 cbuf.set_insts_mark();
22495 // Start at oper_input_base() and count operands
22496 unsigned idx0 = 1;
22497 unsigned idx1 = 1; // dst
22498 // User did not define which encode class to use.
22499}
22500
22501uint castDDNode::size(PhaseRegAlloc *ra_) const {
22502 assert(VerifyOops || MachNode::size(ra_) <= 0, "bad fixed size")do { if (!(VerifyOops || MachNode::size(ra_) <= 0)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 22501, "assert(" "VerifyOops || MachNode::size(ra_) <= 0"
") failed", "bad fixed size"); ::breakpoint(); } } while (0);
22503 return (VerifyOops ? MachNode::size(ra_) : 0);
22504}
22505
22506void loadPLockedNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22507 cbuf.set_insts_mark();
22508 // Start at oper_input_base() and count operands
22509 unsigned idx0 = 2;
22510 unsigned idx1 = 2; // mem
22511 {
22512 C2_MacroAssembler _masm(&cbuf);
22513
22514#line 7698 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
22515
22516 ___masm. movq(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
22517
22518#line 22518 "ad_x86.cpp"
22519 }
22520}
22521
22522void storePConditionalNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22523 cbuf.set_insts_mark();
22524 // Start at oper_input_base() and count operands
22525 unsigned idx0 = 2;
22526 unsigned idx1 = 2; // heap_top_ptr
22527 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
22528 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
22529 {
22530 C2_MacroAssembler _masm(&cbuf);
22531
22532#line 7717 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
22533
22534 ___masm. lock();
22535 ___masm. cmpxchgq(opnd_array(3)->as_Register(ra_,this,idx3)/* newval */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
22536
22537#line 22537 "ad_x86.cpp"
22538 }
22539}
22540
22541void storeIConditionalNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22542 cbuf.set_insts_mark();
22543 // Start at oper_input_base() and count operands
22544 unsigned idx0 = 2;
22545 unsigned idx1 = 2; // mem
22546 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
22547 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
22548 {
22549
22550#line 2350 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
22551
22552 emit_opcode(cbuf, 0xF0); // lock
22553
22554#line 22554 "ad_x86.cpp"
22555 }
22556 {
22557
22558#line 2493 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
22559
22560 if (opnd_array(3)->reg(ra_,this,idx3)/* newval */ < 8) {
22561 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
22562 if (opnd_array(1)->index(ra_,this,idx1) >= 8) {
22563 emit_opcode(cbuf, Assembler::REX_X);
22564 }
22565 } else {
22566 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
22567 emit_opcode(cbuf, Assembler::REX_B);
22568 } else {
22569 emit_opcode(cbuf, Assembler::REX_XB);
22570 }
22571 }
22572 } else {
22573 if (opnd_array(1)->base(ra_,this,idx1) < 8) {
22574 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
22575 emit_opcode(cbuf, Assembler::REX_R);
22576 } else {
22577 emit_opcode(cbuf, Assembler::REX_RX);
22578 }
22579 } else {
22580 if (opnd_array(1)->index(ra_,this,idx1) < 8) {
22581 emit_opcode(cbuf, Assembler::REX_RB);
22582 } else {
22583 emit_opcode(cbuf, Assembler::REX_RXB);
22584 }
22585 }
22586 }
22587
22588#line 22588 "ad_x86.cpp"
22589 }
22590 {
22591
22592#line 1852 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
22593
22594 emit_opcode(cbuf, (0x0F /*primary()*/));
22595
22596#line 22596 "ad_x86.cpp"
22597 }
22598 {
22599
22600#line 1858 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
22601
22602 emit_opcode(cbuf, (0xB1 /*secondary()*/));
22603
22604#line 22604 "ad_x86.cpp"
22605 }
22606 {
22607
22608#line 2557 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
22609
22610 // High registers handle in encode_RegMem
22611 int reg = opnd_array(3)->reg(ra_,this,idx3)/* newval */;
22612 int base = opnd_array(1)->base(ra_,this,idx1);
22613 int index = opnd_array(1)->index(ra_,this,idx1);
22614 int scale = opnd_array(1)->scale();
22615 int disp = opnd_array(1)->disp(ra_,this,idx1);
22616 relocInfo::relocType disp_reloc = opnd_array(1)->disp_reloc();
22617
22618 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
22619
22620#line 22620 "ad_x86.cpp"
22621 }
22622}
22623
22624void storeLConditionalNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22625 cbuf.set_insts_mark();
22626 // Start at oper_input_base() and count operands
22627 unsigned idx0 = 2;
22628 unsigned idx1 = 2; // mem
22629 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
22630 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
22631 {
22632 C2_MacroAssembler _masm(&cbuf);
22633
22634#line 7748 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
22635
22636 ___masm. lock();
22637 ___masm. cmpxchgq(opnd_array(3)->as_Register(ra_,this,idx3)/* newval */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
22638
22639#line 22639 "ad_x86.cpp"
22640 }
22641}
22642
22643void compareAndSwapPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22644 cbuf.set_insts_mark();
22645 // Start at oper_input_base() and count operands
22646 unsigned idx0 = 2;
22647 unsigned idx1 = 2; // mem_ptr
22648 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
22649 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
22650 {
22651 C2_MacroAssembler _masm(&cbuf);
22652
22653#line 7771 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
22654
22655 ___masm. lock();
22656 ___masm. cmpxchgq(opnd_array(3)->as_Register(ra_,this,idx3)/* newval */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
22657 ___masm. sete(opnd_array(0)->as_Register(ra_,this)/* res */);
22658 ___masm. movzbl(opnd_array(0)->as_Register(ra_,this)/* res */, opnd_array(0)->as_Register(ra_,this)/* res */);
22659
22660#line 22660 "ad_x86.cpp"
22661 }
22662}
22663
22664void compareAndSwapP_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22665 cbuf.set_insts_mark();
22666 // Start at oper_input_base() and count operands
22667 unsigned idx0 = 2;
22668 unsigned idx1 = 2; // mem_ptr
22669 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
22670 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
22671 {
22672 C2_MacroAssembler _masm(&cbuf);
22673
22674#line 7771 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
22675
22676 ___masm. lock();
22677 ___masm. cmpxchgq(opnd_array(3)->as_Register(ra_,this,idx3)/* newval */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
22678 ___masm. sete(opnd_array(0)->as_Register(ra_,this)/* res */);
22679 ___masm. movzbl(opnd_array(0)->as_Register(ra_,this)/* res */, opnd_array(0)->as_Register(ra_,this)/* res */);
22680
22681#line 22681 "ad_x86.cpp"
22682 }
22683}
22684
22685void compareAndSwapLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22686 cbuf.set_insts_mark();
22687 // Start at oper_input_base() and count operands
22688 unsigned idx0 = 2;
22689 unsigned idx1 = 2; // mem_ptr
22690 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
22691 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
22692 {
22693 C2_MacroAssembler _masm(&cbuf);
22694
22695#line 7794 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
22696
22697 ___masm. lock();
22698 ___masm. cmpxchgq(opnd_array(3)->as_Register(ra_,this,idx3)/* newval */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
22699 ___masm. sete(opnd_array(0)->as_Register(ra_,this)/* res */);
22700 ___masm. movzbl(opnd_array(0)->as_Register(ra_,this)/* res */, opnd_array(0)->as_Register(ra_,this)/* res */);
22701
22702#line 22702 "ad_x86.cpp"
22703 }
22704}
22705
22706void compareAndSwapL_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22707 cbuf.set_insts_mark();
22708 // Start at oper_input_base() and count operands
22709 unsigned idx0 = 2;
22710 unsigned idx1 = 2; // mem_ptr
22711 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
22712 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
22713 {
22714 C2_MacroAssembler _masm(&cbuf);
22715
22716#line 7794 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
22717
22718 ___masm. lock();
22719 ___masm. cmpxchgq(opnd_array(3)->as_Register(ra_,this,idx3)/* newval */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
22720 ___masm. sete(opnd_array(0)->as_Register(ra_,this)/* res */);
22721 ___masm. movzbl(opnd_array(0)->as_Register(ra_,this)/* res */, opnd_array(0)->as_Register(ra_,this)/* res */);
22722
22723#line 22723 "ad_x86.cpp"
22724 }
22725}
22726
22727void compareAndSwapINode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22728 cbuf.set_insts_mark();
22729 // Start at oper_input_base() and count operands
22730 unsigned idx0 = 2;
22731 unsigned idx1 = 2; // mem_ptr
22732 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
22733 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
22734 {
22735 C2_MacroAssembler _masm(&cbuf);
22736
22737#line 7816 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
22738
22739 ___masm. lock();
22740 ___masm. cmpxchgl(opnd_array(3)->as_Register(ra_,this,idx3)/* newval */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
22741 ___masm. sete(opnd_array(0)->as_Register(ra_,this)/* res */);
22742 ___masm. movzbl(opnd_array(0)->as_Register(ra_,this)/* res */, opnd_array(0)->as_Register(ra_,this)/* res */);
22743
22744#line 22744 "ad_x86.cpp"
22745 }
22746}
22747
22748void compareAndSwapI_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22749 cbuf.set_insts_mark();
22750 // Start at oper_input_base() and count operands
22751 unsigned idx0 = 2;
22752 unsigned idx1 = 2; // mem_ptr
22753 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
22754 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
22755 {
22756 C2_MacroAssembler _masm(&cbuf);
22757
22758#line 7816 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
22759
22760 ___masm. lock();
22761 ___masm. cmpxchgl(opnd_array(3)->as_Register(ra_,this,idx3)/* newval */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
22762 ___masm. sete(opnd_array(0)->as_Register(ra_,this)/* res */);
22763 ___masm. movzbl(opnd_array(0)->as_Register(ra_,this)/* res */, opnd_array(0)->as_Register(ra_,this)/* res */);
22764
22765#line 22765 "ad_x86.cpp"
22766 }
22767}
22768
22769void compareAndSwapBNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22770 cbuf.set_insts_mark();
22771 // Start at oper_input_base() and count operands
22772 unsigned idx0 = 2;
22773 unsigned idx1 = 2; // mem_ptr
22774 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
22775 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
22776 {
22777 C2_MacroAssembler _masm(&cbuf);
22778
22779#line 7838 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
22780
22781 ___masm. lock();
22782 ___masm. cmpxchgb(opnd_array(3)->as_Register(ra_,this,idx3)/* newval */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
22783 ___masm. sete(opnd_array(0)->as_Register(ra_,this)/* res */);
22784 ___masm. movzbl(opnd_array(0)->as_Register(ra_,this)/* res */, opnd_array(0)->as_Register(ra_,this)/* res */);
22785
22786#line 22786 "ad_x86.cpp"
22787 }
22788}
22789
22790void compareAndSwapB_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22791 cbuf.set_insts_mark();
22792 // Start at oper_input_base() and count operands
22793 unsigned idx0 = 2;
22794 unsigned idx1 = 2; // mem_ptr
22795 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
22796 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
22797 {
22798 C2_MacroAssembler _masm(&cbuf);
22799
22800#line 7838 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
22801
22802 ___masm. lock();
22803 ___masm. cmpxchgb(opnd_array(3)->as_Register(ra_,this,idx3)/* newval */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
22804 ___masm. sete(opnd_array(0)->as_Register(ra_,this)/* res */);
22805 ___masm. movzbl(opnd_array(0)->as_Register(ra_,this)/* res */, opnd_array(0)->as_Register(ra_,this)/* res */);
22806
22807#line 22807 "ad_x86.cpp"
22808 }
22809}
22810
22811void compareAndSwapSNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22812 cbuf.set_insts_mark();
22813 // Start at oper_input_base() and count operands
22814 unsigned idx0 = 2;
22815 unsigned idx1 = 2; // mem_ptr
22816 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
22817 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
22818 {
22819 C2_MacroAssembler _masm(&cbuf);
22820
22821#line 7860 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
22822
22823 ___masm. lock();
22824 ___masm. cmpxchgw(opnd_array(3)->as_Register(ra_,this,idx3)/* newval */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
22825 ___masm. sete(opnd_array(0)->as_Register(ra_,this)/* res */);
22826 ___masm. movzbl(opnd_array(0)->as_Register(ra_,this)/* res */, opnd_array(0)->as_Register(ra_,this)/* res */);
22827
22828#line 22828 "ad_x86.cpp"
22829 }
22830}
22831
22832void compareAndSwapS_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22833 cbuf.set_insts_mark();
22834 // Start at oper_input_base() and count operands
22835 unsigned idx0 = 2;
22836 unsigned idx1 = 2; // mem_ptr
22837 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
22838 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
22839 {
22840 C2_MacroAssembler _masm(&cbuf);
22841
22842#line 7860 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
22843
22844 ___masm. lock();
22845 ___masm. cmpxchgw(opnd_array(3)->as_Register(ra_,this,idx3)/* newval */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
22846 ___masm. sete(opnd_array(0)->as_Register(ra_,this)/* res */);
22847 ___masm. movzbl(opnd_array(0)->as_Register(ra_,this)/* res */, opnd_array(0)->as_Register(ra_,this)/* res */);
22848
22849#line 22849 "ad_x86.cpp"
22850 }
22851}
22852
22853void compareAndSwapNNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22854 cbuf.set_insts_mark();
22855 // Start at oper_input_base() and count operands
22856 unsigned idx0 = 2;
22857 unsigned idx1 = 2; // mem_ptr
22858 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
22859 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
22860 {
22861 C2_MacroAssembler _masm(&cbuf);
22862
22863#line 7881 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
22864
22865 ___masm. lock();
22866 ___masm. cmpxchgl(opnd_array(3)->as_Register(ra_,this,idx3)/* newval */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
22867 ___masm. sete(opnd_array(0)->as_Register(ra_,this)/* res */);
22868 ___masm. movzbl(opnd_array(0)->as_Register(ra_,this)/* res */, opnd_array(0)->as_Register(ra_,this)/* res */);
22869
22870#line 22870 "ad_x86.cpp"
22871 }
22872}
22873
22874void compareAndSwapN_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22875 cbuf.set_insts_mark();
22876 // Start at oper_input_base() and count operands
22877 unsigned idx0 = 2;
22878 unsigned idx1 = 2; // mem_ptr
22879 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
22880 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
22881 {
22882 C2_MacroAssembler _masm(&cbuf);
22883
22884#line 7881 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
22885
22886 ___masm. lock();
22887 ___masm. cmpxchgl(opnd_array(3)->as_Register(ra_,this,idx3)/* newval */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
22888 ___masm. sete(opnd_array(0)->as_Register(ra_,this)/* res */);
22889 ___masm. movzbl(opnd_array(0)->as_Register(ra_,this)/* res */, opnd_array(0)->as_Register(ra_,this)/* res */);
22890
22891#line 22891 "ad_x86.cpp"
22892 }
22893}
22894
22895void compareAndExchangeBNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22896 cbuf.set_insts_mark();
22897 // Start at oper_input_base() and count operands
22898 unsigned idx0 = 2;
22899 unsigned idx1 = 2; // mem_ptr
22900 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
22901 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
22902 {
22903 C2_MacroAssembler _masm(&cbuf);
22904
22905#line 7900 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
22906
22907 ___masm. lock();
22908 ___masm. cmpxchgb(opnd_array(3)->as_Register(ra_,this,idx3)/* newval */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
22909
22910#line 22910 "ad_x86.cpp"
22911 }
22912}
22913
22914void compareAndExchangeSNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22915 cbuf.set_insts_mark();
22916 // Start at oper_input_base() and count operands
22917 unsigned idx0 = 2;
22918 unsigned idx1 = 2; // mem_ptr
22919 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
22920 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
22921 {
22922 C2_MacroAssembler _masm(&cbuf);
22923
22924#line 7917 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
22925
22926 ___masm. lock();
22927 ___masm. cmpxchgw(opnd_array(3)->as_Register(ra_,this,idx3)/* newval */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
22928
22929#line 22929 "ad_x86.cpp"
22930 }
22931}
22932
22933void compareAndExchangeINode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22934 cbuf.set_insts_mark();
22935 // Start at oper_input_base() and count operands
22936 unsigned idx0 = 2;
22937 unsigned idx1 = 2; // mem_ptr
22938 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
22939 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
22940 {
22941 C2_MacroAssembler _masm(&cbuf);
22942
22943#line 7934 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
22944
22945 ___masm. lock();
22946 ___masm. cmpxchgl(opnd_array(3)->as_Register(ra_,this,idx3)/* newval */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
22947
22948#line 22948 "ad_x86.cpp"
22949 }
22950}
22951
22952void compareAndExchangeLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22953 cbuf.set_insts_mark();
22954 // Start at oper_input_base() and count operands
22955 unsigned idx0 = 2;
22956 unsigned idx1 = 2; // mem_ptr
22957 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
22958 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
22959 {
22960 C2_MacroAssembler _masm(&cbuf);
22961
22962#line 7952 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
22963
22964 ___masm. lock();
22965 ___masm. cmpxchgq(opnd_array(3)->as_Register(ra_,this,idx3)/* newval */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
22966
22967#line 22967 "ad_x86.cpp"
22968 }
22969}
22970
22971void compareAndExchangeNNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22972 cbuf.set_insts_mark();
22973 // Start at oper_input_base() and count operands
22974 unsigned idx0 = 2;
22975 unsigned idx1 = 2; // mem_ptr
22976 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
22977 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
22978 {
22979 C2_MacroAssembler _masm(&cbuf);
22980
22981#line 7968 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
22982
22983 ___masm. lock();
22984 ___masm. cmpxchgl(opnd_array(3)->as_Register(ra_,this,idx3)/* newval */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
22985
22986#line 22986 "ad_x86.cpp"
22987 }
22988}
22989
22990void compareAndExchangePNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
22991 cbuf.set_insts_mark();
22992 // Start at oper_input_base() and count operands
22993 unsigned idx0 = 2;
22994 unsigned idx1 = 2; // mem_ptr
22995 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
22996 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
22997 {
22998 C2_MacroAssembler _masm(&cbuf);
22999
23000#line 7986 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
23001
23002 ___masm. lock();
23003 ___masm. cmpxchgq(opnd_array(3)->as_Register(ra_,this,idx3)/* newval */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
23004
23005#line 23005 "ad_x86.cpp"
23006 }
23007}
23008
23009void xaddB_no_resNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23010 cbuf.set_insts_mark();
23011 // Start at oper_input_base() and count operands
23012 unsigned idx0 = 2;
23013 unsigned idx1 = 2; // mem
23014 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // add
23015 {
23016 C2_MacroAssembler _masm(&cbuf);
23017
23018#line 7998 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
23019
23020 ___masm. lock();
23021 ___masm. addb(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->constant());
23022
23023#line 23023 "ad_x86.cpp"
23024 }
23025}
23026
23027void xaddBNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23028 cbuf.set_insts_mark();
23029 // Start at oper_input_base() and count operands
23030 unsigned idx0 = 2;
23031 unsigned idx1 = 2; // mem
23032 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // newval
23033 {
23034 C2_MacroAssembler _masm(&cbuf);
23035
23036#line 8009 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
23037
23038 ___masm. lock();
23039 ___masm. xaddb(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_Register(ra_,this,idx2)/* newval */);
23040
23041#line 23041 "ad_x86.cpp"
23042 }
23043}
23044
23045void xaddS_no_resNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23046 cbuf.set_insts_mark();
23047 // Start at oper_input_base() and count operands
23048 unsigned idx0 = 2;
23049 unsigned idx1 = 2; // mem
23050 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // add
23051 {
23052 C2_MacroAssembler _masm(&cbuf);
23053
23054#line 8021 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
23055
23056 ___masm. lock();
23057 ___masm. addw(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->constant());
23058
23059#line 23059 "ad_x86.cpp"
23060 }
23061}
23062
23063void xaddSNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23064 cbuf.set_insts_mark();
23065 // Start at oper_input_base() and count operands
23066 unsigned idx0 = 2;
23067 unsigned idx1 = 2; // mem
23068 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // newval
23069 {
23070 C2_MacroAssembler _masm(&cbuf);
23071
23072#line 8032 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
23073
23074 ___masm. lock();
23075 ___masm. xaddw(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_Register(ra_,this,idx2)/* newval */);
23076
23077#line 23077 "ad_x86.cpp"
23078 }
23079}
23080
23081void xaddI_no_resNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23082 cbuf.set_insts_mark();
23083 // Start at oper_input_base() and count operands
23084 unsigned idx0 = 2;
23085 unsigned idx1 = 2; // mem
23086 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // add
23087 {
23088 C2_MacroAssembler _masm(&cbuf);
23089
23090#line 8044 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
23091
23092 ___masm. lock();
23093 ___masm. addl(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->constant());
23094
23095#line 23095 "ad_x86.cpp"
23096 }
23097}
23098
23099void xaddINode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23100 cbuf.set_insts_mark();
23101 // Start at oper_input_base() and count operands
23102 unsigned idx0 = 2;
23103 unsigned idx1 = 2; // mem
23104 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // newval
23105 {
23106 C2_MacroAssembler _masm(&cbuf);
23107
23108#line 8055 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
23109
23110 ___masm. lock();
23111 ___masm. xaddl(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_Register(ra_,this,idx2)/* newval */);
23112
23113#line 23113 "ad_x86.cpp"
23114 }
23115}
23116
23117void xaddL_no_resNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23118 cbuf.set_insts_mark();
23119 // Start at oper_input_base() and count operands
23120 unsigned idx0 = 2;
23121 unsigned idx1 = 2; // mem
23122 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // add
23123 {
23124 C2_MacroAssembler _masm(&cbuf);
23125
23126#line 8067 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
23127
23128 ___masm. lock();
23129 ___masm. addq(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->constantL());
23130
23131#line 23131 "ad_x86.cpp"
23132 }
23133}
23134
23135void xaddLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23136 cbuf.set_insts_mark();
23137 // Start at oper_input_base() and count operands
23138 unsigned idx0 = 2;
23139 unsigned idx1 = 2; // mem
23140 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // newval
23141 {
23142 C2_MacroAssembler _masm(&cbuf);
23143
23144#line 8078 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
23145
23146 ___masm. lock();
23147 ___masm. xaddq(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_Register(ra_,this,idx2)/* newval */);
23148
23149#line 23149 "ad_x86.cpp"
23150 }
23151}
23152
23153void xchgBNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23154 cbuf.set_insts_mark();
23155 // Start at oper_input_base() and count operands
23156 unsigned idx0 = 2;
23157 unsigned idx1 = 2; // mem
23158 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // newval
23159 {
23160 C2_MacroAssembler _masm(&cbuf);
23161
23162#line 8088 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
23163
23164 ___masm. xchgb(opnd_array(2)->as_Register(ra_,this,idx2)/* newval */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
23165
23166#line 23166 "ad_x86.cpp"
23167 }
23168}
23169
23170void xchgSNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23171 cbuf.set_insts_mark();
23172 // Start at oper_input_base() and count operands
23173 unsigned idx0 = 2;
23174 unsigned idx1 = 2; // mem
23175 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // newval
23176 {
23177 C2_MacroAssembler _masm(&cbuf);
23178
23179#line 8097 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
23180
23181 ___masm. xchgw(opnd_array(2)->as_Register(ra_,this,idx2)/* newval */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
23182
23183#line 23183 "ad_x86.cpp"
23184 }
23185}
23186
23187void xchgINode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23188 cbuf.set_insts_mark();
23189 // Start at oper_input_base() and count operands
23190 unsigned idx0 = 2;
23191 unsigned idx1 = 2; // mem
23192 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // newval
23193 {
23194 C2_MacroAssembler _masm(&cbuf);
23195
23196#line 8106 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
23197
23198 ___masm. xchgl(opnd_array(2)->as_Register(ra_,this,idx2)/* newval */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
23199
23200#line 23200 "ad_x86.cpp"
23201 }
23202}
23203
23204void xchgLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23205 cbuf.set_insts_mark();
23206 // Start at oper_input_base() and count operands
23207 unsigned idx0 = 2;
23208 unsigned idx1 = 2; // mem
23209 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // newval
23210 {
23211 C2_MacroAssembler _masm(&cbuf);
23212
23213#line 8115 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
23214
23215 ___masm. xchgq(opnd_array(2)->as_Register(ra_,this,idx2)/* newval */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
23216
23217#line 23217 "ad_x86.cpp"
23218 }
23219}
23220
23221void xchgPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23222 cbuf.set_insts_mark();
23223 // Start at oper_input_base() and count operands
23224 unsigned idx0 = 2;
23225 unsigned idx1 = 2; // mem
23226 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // newval
23227 {
23228 C2_MacroAssembler _masm(&cbuf);
23229
23230#line 8125 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
23231
23232 ___masm. xchgq(opnd_array(2)->as_Register(ra_,this,idx2)/* newval */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
23233
23234#line 23234 "ad_x86.cpp"
23235 }
23236}
23237
23238void xchgNNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23239 cbuf.set_insts_mark();
23240 // Start at oper_input_base() and count operands
23241 unsigned idx0 = 2;
23242 unsigned idx1 = 2; // mem
23243 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // newval
23244 {
23245 C2_MacroAssembler _masm(&cbuf);
23246
23247#line 8134 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
23248
23249 ___masm. xchgl(opnd_array(2)->as_Register(ra_,this,idx2)/* newval */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
23250
23251#line 23251 "ad_x86.cpp"
23252 }
23253}
23254
23255void absI_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23256 cbuf.set_insts_mark();
23257 // Start at oper_input_base() and count operands
23258 unsigned idx0 = 1;
23259 unsigned idx1 = 1; // src
23260 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
23261 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
23262 {
23263 C2_MacroAssembler _masm(&cbuf);
23264
23265#line 8153 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
23266
23267 ___masm. movl(opnd_array(3)->as_Register(ra_,this,idx3)/* tmp */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
23268 ___masm. sarl(opnd_array(3)->as_Register(ra_,this,idx3)/* tmp */, 31);
23269 ___masm. movl(opnd_array(2)->as_Register(ra_,this,idx2)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
23270 ___masm. xorl(opnd_array(2)->as_Register(ra_,this,idx2)/* dst */, opnd_array(3)->as_Register(ra_,this,idx3)/* tmp */);
23271 ___masm. subl(opnd_array(2)->as_Register(ra_,this,idx2)/* dst */, opnd_array(3)->as_Register(ra_,this,idx3)/* tmp */);
23272
23273#line 23273 "ad_x86.cpp"
23274 }
23275}
23276
23277void absL_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23278 cbuf.set_insts_mark();
23279 // Start at oper_input_base() and count operands
23280 unsigned idx0 = 1;
23281 unsigned idx1 = 1; // src
23282 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
23283 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
23284 {
23285 C2_MacroAssembler _masm(&cbuf);
23286
23287#line 8175 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
23288
23289 ___masm. movq(opnd_array(3)->as_Register(ra_,this,idx3)/* tmp */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
23290 ___masm. sarq(opnd_array(3)->as_Register(ra_,this,idx3)/* tmp */, 63);
23291 ___masm. movq(opnd_array(2)->as_Register(ra_,this,idx2)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
23292 ___masm. xorq(opnd_array(2)->as_Register(ra_,this,idx2)/* dst */, opnd_array(3)->as_Register(ra_,this,idx3)/* tmp */);
23293 ___masm. subq(opnd_array(2)->as_Register(ra_,this,idx2)/* dst */, opnd_array(3)->as_Register(ra_,this,idx3)/* tmp */);
23294
23295#line 23295 "ad_x86.cpp"
23296 }
23297}
23298
23299void subI_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23300 cbuf.set_insts_mark();
23301 // Start at oper_input_base() and count operands
23302 unsigned idx0 = 1;
23303 unsigned idx1 = 1; // dst
23304 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
23305 {
23306 C2_MacroAssembler _masm(&cbuf);
23307
23308#line 8195 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
23309
23310 ___masm. subl(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, opnd_array(2)->as_Register(ra_,this,idx2)/* src */);
23311
23312#line 23312 "ad_x86.cpp"
23313 }
23314}
23315
23316void subI_rReg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23317 cbuf.set_insts_mark();
23318 // Start at oper_input_base() and count operands
23319 unsigned idx0 = 1;
23320 unsigned idx1 = 1; // dst
23321 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
23322 {
23323 C2_MacroAssembler _masm(&cbuf);
23324
23325#line 8207 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
23326
23327 ___masm. subl(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, opnd_array(2)->constant());
23328
23329#line 23329 "ad_x86.cpp"
23330 }
23331}
23332
23333void subI_rReg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23334 cbuf.set_insts_mark();
23335 // Start at oper_input_base() and count operands
23336 unsigned idx0 = 2;
23337 unsigned idx1 = 2; // dst
23338 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
23339 {
23340 C2_MacroAssembler _masm(&cbuf);
23341
23342#line 8220 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
23343
23344 ___masm. subl(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
23345
23346#line 23346 "ad_x86.cpp"
23347 }
23348}
23349
23350void subI_mem_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23351 cbuf.set_insts_mark();
23352 // Start at oper_input_base() and count operands
23353 unsigned idx0 = 2;
23354 unsigned idx1 = 2; // dst
23355 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
23356 {
23357 C2_MacroAssembler _masm(&cbuf);
23358
23359#line 8233 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
23360
23361 ___masm. subl(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_Register(ra_,this,idx2)/* src */);
23362
23363#line 23363 "ad_x86.cpp"
23364 }
23365}
23366
23367void subI_mem_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23368 cbuf.set_insts_mark();
23369 // Start at oper_input_base() and count operands
23370 unsigned idx0 = 2;
23371 unsigned idx1 = 2; // dst
23372 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
23373 {
23374 C2_MacroAssembler _masm(&cbuf);
23375
23376#line 8246 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
23377
23378 ___masm. subl(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->constant());
23379
23380#line 23380 "ad_x86.cpp"
23381 }
23382}
23383
23384void subL_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23385 cbuf.set_insts_mark();
23386 // Start at oper_input_base() and count operands
23387 unsigned idx0 = 1;
23388 unsigned idx1 = 1; // dst
23389 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
23390 {
23391 C2_MacroAssembler _masm(&cbuf);
23392
23393#line 8258 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
23394
23395 ___masm. subq(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, opnd_array(2)->as_Register(ra_,this,idx2)/* src */);
23396
23397#line 23397 "ad_x86.cpp"
23398 }
23399}
23400
23401void subL_rReg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23402 cbuf.set_insts_mark();
23403 // Start at oper_input_base() and count operands
23404 unsigned idx0 = 1;
23405 unsigned idx1 = 1; // dst
23406 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
23407 {
23408 C2_MacroAssembler _masm(&cbuf);
23409
23410#line 8270 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
23411
23412 ___masm. subq(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, opnd_array(2)->constantL());
23413
23414#line 23414 "ad_x86.cpp"
23415 }
23416}
23417
23418void subL_rReg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23419 cbuf.set_insts_mark();
23420 // Start at oper_input_base() and count operands
23421 unsigned idx0 = 2;
23422 unsigned idx1 = 2; // dst
23423 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
23424 {
23425 C2_MacroAssembler _masm(&cbuf);
23426
23427#line 8283 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
23428
23429 ___masm. subq(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
23430
23431#line 23431 "ad_x86.cpp"
23432 }
23433}
23434
23435void subL_mem_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23436 cbuf.set_insts_mark();
23437 // Start at oper_input_base() and count operands
23438 unsigned idx0 = 2;
23439 unsigned idx1 = 2; // dst
23440 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
23441 {
23442 C2_MacroAssembler _masm(&cbuf);
23443
23444#line 8296 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
23445
23446 ___masm. subq(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_Register(ra_,this,idx2)/* src */);
23447
23448#line 23448 "ad_x86.cpp"
23449 }
23450}
23451
23452void subL_mem_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23453 cbuf.set_insts_mark();
23454 // Start at oper_input_base() and count operands
23455 unsigned idx0 = 2;
23456 unsigned idx1 = 2; // dst
23457 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
23458 {
23459 C2_MacroAssembler _masm(&cbuf);
23460
23461#line 8309 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
23462
23463 ___masm. subq(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->constantL());
23464
23465#line 23465 "ad_x86.cpp"
23466 }
23467}
23468
23469void subP_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23470 cbuf.set_insts_mark();
23471 // Start at oper_input_base() and count operands
23472 unsigned idx0 = 2;
23473 unsigned idx1 = 2; // dst
23474 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
23475 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // src
23476 {
23477
23478#line 2476 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
23479
23480 if (opnd_array(1)->reg(ra_,this,idx1)/* dst */ < 8) {
23481 if (opnd_array(3)->reg(ra_,this,idx3)/* src */ < 8) {
23482 emit_opcode(cbuf, Assembler::REX_W);
23483 } else {
23484 emit_opcode(cbuf, Assembler::REX_WB);
23485 }
23486 } else {
23487 if (opnd_array(3)->reg(ra_,this,idx3)/* src */ < 8) {
23488 emit_opcode(cbuf, Assembler::REX_WR);
23489 } else {
23490 emit_opcode(cbuf, Assembler::REX_WRB);
23491 }
23492 }
23493
23494#line 23494 "ad_x86.cpp"
23495 }
23496 {
23497
23498#line 1852 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
23499
23500 emit_opcode(cbuf, (0x2B /*primary()*/));
23501
23502#line 23502 "ad_x86.cpp"
23503 }
23504 {
23505
23506#line 1886 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
23507
23508 emit_rm(cbuf, 0x3, opnd_array(1)->reg(ra_,this,idx1)/* dst */ & 7, opnd_array(3)->reg(ra_,this,idx3)/* src */ & 7);
23509
23510#line 23510 "ad_x86.cpp"
23511 }
23512}
23513
23514void negI_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23515 cbuf.set_insts_mark();
23516 // Start at oper_input_base() and count operands
23517 unsigned idx0 = 1;
23518 unsigned idx1 = 1; // zero
23519 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
23520 {
23521 C2_MacroAssembler _masm(&cbuf);
23522
23523#line 8334 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
23524
23525 ___masm. negl(opnd_array(2)->as_Register(ra_,this,idx2)/* dst */);
23526
23527#line 23527 "ad_x86.cpp"
23528 }
23529}
23530
23531void negI_rReg_2Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23532 cbuf.set_insts_mark();
23533 // Start at oper_input_base() and count operands
23534 unsigned idx0 = 1;
23535 unsigned idx1 = 1; // dst
23536 {
23537 C2_MacroAssembler _masm(&cbuf);
23538
23539#line 8346 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
23540
23541 ___masm. negl(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */);
23542
23543#line 23543 "ad_x86.cpp"
23544 }
23545}
23546
23547void negI_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23548 cbuf.set_insts_mark();
23549 // Start at oper_input_base() and count operands
23550 unsigned idx0 = 2;
23551 unsigned idx1 = 2; // dst
23552 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
23553 {
23554 C2_MacroAssembler _masm(&cbuf);
23555
23556#line 8358 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
23557
23558 ___masm. negl(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
23559
23560#line 23560 "ad_x86.cpp"
23561 }
23562}
23563
23564void negL_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23565 cbuf.set_insts_mark();
23566 // Start at oper_input_base() and count operands
23567 unsigned idx0 = 1;
23568 unsigned idx1 = 1; // zero
23569 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
23570 {
23571 C2_MacroAssembler _masm(&cbuf);
23572
23573#line 8370 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
23574
23575 ___masm. negq(opnd_array(2)->as_Register(ra_,this,idx2)/* dst */);
23576
23577#line 23577 "ad_x86.cpp"
23578 }
23579}
23580
23581void negL_rReg_2Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23582 cbuf.set_insts_mark();
23583 // Start at oper_input_base() and count operands
23584 unsigned idx0 = 1;
23585 unsigned idx1 = 1; // dst
23586 {
23587 C2_MacroAssembler _masm(&cbuf);
23588
23589#line 8382 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
23590
23591 ___masm. negq(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */);
23592
23593#line 23593 "ad_x86.cpp"
23594 }
23595}
23596
23597void negL_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23598 cbuf.set_insts_mark();
23599 // Start at oper_input_base() and count operands
23600 unsigned idx0 = 2;
23601 unsigned idx1 = 2; // dst
23602 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
23603 {
23604 C2_MacroAssembler _masm(&cbuf);
23605
23606#line 8394 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
23607
23608 ___masm. negq(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
23609
23610#line 23610 "ad_x86.cpp"
23611 }
23612}
23613
23614void mulI_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23615 cbuf.set_insts_mark();
23616 // Start at oper_input_base() and count operands
23617 unsigned idx0 = 1;
23618 unsigned idx1 = 1; // dst
23619 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
23620 {
23621 C2_MacroAssembler _masm(&cbuf);
23622
23623#line 8411 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
23624
23625 ___masm. imull(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, opnd_array(2)->as_Register(ra_,this,idx2)/* src */);
23626
23627#line 23627 "ad_x86.cpp"
23628 }
23629}
23630
23631void mulI_rReg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23632 cbuf.set_insts_mark();
23633 // Start at oper_input_base() and count operands
23634 unsigned idx0 = 1;
23635 unsigned idx1 = 1; // src
23636 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // imm
23637 {
23638 C2_MacroAssembler _masm(&cbuf);
23639
23640#line 8424 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
23641
23642 ___masm. imull(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */, opnd_array(2)->constant());
23643
23644#line 23644 "ad_x86.cpp"
23645 }
23646}
23647
23648void mulI_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23649 cbuf.set_insts_mark();
23650 // Start at oper_input_base() and count operands
23651 unsigned idx0 = 2;
23652 unsigned idx1 = 2; // dst
23653 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
23654 {
23655 C2_MacroAssembler _masm(&cbuf);
23656
23657#line 8437 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
23658
23659 ___masm. imull(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
23660
23661#line 23661 "ad_x86.cpp"
23662 }
23663}
23664
23665void mulI_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23666 cbuf.set_insts_mark();
23667 // Start at oper_input_base() and count operands
23668 unsigned idx0 = 2;
23669 unsigned idx1 = 2; // src
23670 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
23671 {
23672 C2_MacroAssembler _masm(&cbuf);
23673
23674#line 8437 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
23675
23676 ___masm. imull(opnd_array(2)->as_Register(ra_,this,idx2)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
23677
23678#line 23678 "ad_x86.cpp"
23679 }
23680}
23681
23682void mulI_mem_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23683 cbuf.set_insts_mark();
23684 // Start at oper_input_base() and count operands
23685 unsigned idx0 = 2;
23686 unsigned idx1 = 2; // src
23687 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // imm
23688 {
23689 C2_MacroAssembler _masm(&cbuf);
23690
23691#line 8450 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
23692
23693 ___masm. imull(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->constant());
23694
23695#line 23695 "ad_x86.cpp"
23696 }
23697}
23698
23699void mulL_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23700 cbuf.set_insts_mark();
23701 // Start at oper_input_base() and count operands
23702 unsigned idx0 = 1;
23703 unsigned idx1 = 1; // dst
23704 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
23705 {
23706 C2_MacroAssembler _masm(&cbuf);
23707
23708#line 8473 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
23709
23710 ___masm. imulq(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, opnd_array(2)->as_Register(ra_,this,idx2)/* src */);
23711
23712#line 23712 "ad_x86.cpp"
23713 }
23714}
23715
23716void mulL_rReg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23717 cbuf.set_insts_mark();
23718 // Start at oper_input_base() and count operands
23719 unsigned idx0 = 1;
23720 unsigned idx1 = 1; // src
23721 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // imm
23722 {
23723 C2_MacroAssembler _masm(&cbuf);
23724
23725#line 8486 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
23726
23727 ___masm. imulq(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */, opnd_array(2)->constantL());
23728
23729#line 23729 "ad_x86.cpp"
23730 }
23731}
23732
23733void mulL_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23734 cbuf.set_insts_mark();
23735 // Start at oper_input_base() and count operands
23736 unsigned idx0 = 2;
23737 unsigned idx1 = 2; // dst
23738 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
23739 {
23740 C2_MacroAssembler _masm(&cbuf);
23741
23742#line 8499 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
23743
23744 ___masm. imulq(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
23745
23746#line 23746 "ad_x86.cpp"
23747 }
23748}
23749
23750void mulL_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23751 cbuf.set_insts_mark();
23752 // Start at oper_input_base() and count operands
23753 unsigned idx0 = 2;
23754 unsigned idx1 = 2; // src
23755 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
23756 {
23757 C2_MacroAssembler _masm(&cbuf);
23758
23759#line 8499 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
23760
23761 ___masm. imulq(opnd_array(2)->as_Register(ra_,this,idx2)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
23762
23763#line 23763 "ad_x86.cpp"
23764 }
23765}
23766
23767void mulL_mem_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23768 cbuf.set_insts_mark();
23769 // Start at oper_input_base() and count operands
23770 unsigned idx0 = 2;
23771 unsigned idx1 = 2; // src
23772 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // imm
23773 {
23774 C2_MacroAssembler _masm(&cbuf);
23775
23776#line 8512 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
23777
23778 ___masm. imulq(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->constantL());
23779
23780#line 23780 "ad_x86.cpp"
23781 }
23782}
23783
23784void mulHiL_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23785 cbuf.set_insts_mark();
23786 // Start at oper_input_base() and count operands
23787 unsigned idx0 = 1;
23788 unsigned idx1 = 1; // src
23789 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // rax
23790 {
23791 C2_MacroAssembler _masm(&cbuf);
23792
23793#line 8525 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
23794
23795 ___masm. imulq(opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
23796
23797#line 23797 "ad_x86.cpp"
23798 }
23799}
23800
23801void umulHiL_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23802 cbuf.set_insts_mark();
23803 // Start at oper_input_base() and count operands
23804 unsigned idx0 = 1;
23805 unsigned idx1 = 1; // src
23806 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // rax
23807 {
23808 C2_MacroAssembler _masm(&cbuf);
23809
23810#line 8538 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
23811
23812 ___masm. mulq(opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
23813
23814#line 23814 "ad_x86.cpp"
23815 }
23816}
23817
23818void divI_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23819 cbuf.set_insts_mark();
23820 // Start at oper_input_base() and count operands
23821 unsigned idx0 = 1;
23822 unsigned idx1 = 1; // rax
23823 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // div
23824 {
23825
23826#line 1897 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
23827
23828 // Full implementation of Java idiv and irem; checks for
23829 // special case as described in JVM spec., p.243 & p.271.
23830 //
23831 // normal case special case
23832 //
23833 // input : rax: dividend min_int
23834 // reg: divisor -1
23835 //
23836 // output: rax: quotient (= rax idiv reg) min_int
23837 // rdx: remainder (= rax irem reg) 0
23838 //
23839 // Code sequnce:
23840 //
23841 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax
23842 // 5: 75 07/08 jne e <normal>
23843 // 7: 33 d2 xor %edx,%edx
23844 // [div >= 8 -> offset + 1]
23845 // [REX_B]
23846 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div
23847 // c: 74 03/04 je 11 <done>
23848 // 000000000000000e <normal>:
23849 // e: 99 cltd
23850 // [div >= 8 -> offset + 1]
23851 // [REX_B]
23852 // f: f7 f9 idiv $div
23853 // 0000000000000011 <done>:
23854 MacroAssembler _masm(&cbuf);
23855 Label normal;
23856 Label done;
23857
23858 // cmp $0x80000000,%eax
23859 ___masm. cmp(as_Register(RAX_enc), 0x80000000);
23860
23861 // jne e <normal>
23862 ___masm. jccb(Assembler::notEqual, normal)jccb_0(Assembler::notEqual, normal, "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 1932);
23863
23864 // xor %edx,%edx
23865 ___masm. xorl(as_Register(RDX_enc), as_Register(RDX_enc));
23866
23867 // cmp $0xffffffffffffffff,%ecx
23868 ___masm. cmpl(opnd_array(2)->as_Register(ra_,this,idx2)/* div */, -1);
23869
23870 // je 11 <done>
23871 ___masm. jccb(Assembler::equal, done)jccb_0(Assembler::equal, done, "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 1941);
23872
23873 // <normal>
23874 // cltd
23875 ___masm. bind(normal);
23876 ___masm. cdql();
23877
23878 // idivl
23879 // <done>
23880 ___masm. idivl(opnd_array(2)->as_Register(ra_,this,idx2)/* div */);
23881 ___masm. bind(done);
23882
23883#line 23883 "ad_x86.cpp"
23884 }
23885}
23886
23887void divL_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23888 cbuf.set_insts_mark();
23889 // Start at oper_input_base() and count operands
23890 unsigned idx0 = 1;
23891 unsigned idx1 = 1; // rax
23892 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // div
23893 {
23894
23895#line 1955 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
23896
23897 // Full implementation of Java ldiv and lrem; checks for
23898 // special case as described in JVM spec., p.243 & p.271.
23899 //
23900 // normal case special case
23901 //
23902 // input : rax: dividend min_long
23903 // reg: divisor -1
23904 //
23905 // output: rax: quotient (= rax idiv reg) min_long
23906 // rdx: remainder (= rax irem reg) 0
23907 //
23908 // Code sequnce:
23909 //
23910 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx
23911 // 7: 00 00 80
23912 // a: 48 39 d0 cmp %rdx,%rax
23913 // d: 75 08 jne 17 <normal>
23914 // f: 33 d2 xor %edx,%edx
23915 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div
23916 // 15: 74 05 je 1c <done>
23917 // 0000000000000017 <normal>:
23918 // 17: 48 99 cqto
23919 // 19: 48 f7 f9 idiv $div
23920 // 000000000000001c <done>:
23921 MacroAssembler _masm(&cbuf);
23922 Label normal;
23923 Label done;
23924
23925 // mov $0x8000000000000000,%rdx
23926 ___masm. mov64(as_Register(RDX_enc), 0x8000000000000000);
23927
23928 // cmp %rdx,%rax
23929 ___masm. cmpq(as_Register(RAX_enc), as_Register(RDX_enc));
23930
23931 // jne 17 <normal>
23932 ___masm. jccb(Assembler::notEqual, normal)jccb_0(Assembler::notEqual, normal, "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 1991);
23933
23934 // xor %edx,%edx
23935 ___masm. xorl(as_Register(RDX_enc), as_Register(RDX_enc));
23936
23937 // cmp $0xffffffffffffffff,$div
23938 ___masm. cmpq(opnd_array(2)->as_Register(ra_,this,idx2)/* div */, -1);
23939
23940 // je 1e <done>
23941 ___masm. jccb(Assembler::equal, done)jccb_0(Assembler::equal, done, "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 2000);
23942
23943 // <normal>
23944 // cqto
23945 ___masm. bind(normal);
23946 ___masm. cdqq();
23947
23948 // idivq (note: must be emitted by the user of this rule)
23949 // <done>
23950 ___masm. idivq(opnd_array(2)->as_Register(ra_,this,idx2)/* div */);
23951 ___masm. bind(done);
23952
23953#line 23953 "ad_x86.cpp"
23954 }
23955}
23956
23957void divModI_rReg_divmodNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
23958 cbuf.set_insts_mark();
23959 // Start at oper_input_base() and count operands
23960 unsigned idx0 = 1;
23961 unsigned idx1 = 1; // div
23962 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // rdx
23963 {
23964
23965#line 1897 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
23966
23967 // Full implementation of Java idiv and irem; checks for
23968 // special case as described in JVM spec., p.243 & p.271.
23969 //
23970 // normal case special case
23971 //
23972 // input : rax: dividend min_int
23973 // reg: divisor -1
23974 //
23975 // output: rax: quotient (= rax idiv reg) min_int
23976 // rdx: remainder (= rax irem reg) 0
23977 //
23978 // Code sequnce:
23979 //
23980 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax
23981 // 5: 75 07/08 jne e <normal>
23982 // 7: 33 d2 xor %edx,%edx
23983 // [div >= 8 -> offset + 1]
23984 // [REX_B]
23985 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div
23986 // c: 74 03/04 je 11 <done>
23987 // 000000000000000e <normal>:
23988 // e: 99 cltd
23989 // [div >= 8 -> offset + 1]
23990 // [REX_B]
23991 // f: f7 f9 idiv $div
23992 // 0000000000000011 <done>:
23993 MacroAssembler _masm(&cbuf);
23994 Label normal;
23995 Label done;
23996
23997 // cmp $0x80000000,%eax
23998 ___masm. cmp(as_Register(RAX_enc), 0x80000000);
23999
24000 // jne e <normal>
24001 ___masm. jccb(Assembler::notEqual, normal)jccb_0(Assembler::notEqual, normal, "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 1932);
24002
24003 // xor %edx,%edx
24004 ___masm. xorl(as_Register(RDX_enc), as_Register(RDX_enc));
24005
24006 // cmp $0xffffffffffffffff,%ecx
24007 ___masm. cmpl(opnd_array(2)->as_Register(ra_,this,idx2)/* div */, -1);
24008
24009 // je 11 <done>
24010 ___masm. jccb(Assembler::equal, done)jccb_0(Assembler::equal, done, "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 1941);
24011
24012 // <normal>
24013 // cltd
24014 ___masm. bind(normal);
24015 ___masm. cdql();
24016
24017 // idivl
24018 // <done>
24019 ___masm. idivl(opnd_array(2)->as_Register(ra_,this,idx2)/* div */);
24020 ___masm. bind(done);
24021
24022#line 24022 "ad_x86.cpp"
24023 }
24024}
24025
24026void divModL_rReg_divmodNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24027 cbuf.set_insts_mark();
24028 // Start at oper_input_base() and count operands
24029 unsigned idx0 = 1;
24030 unsigned idx1 = 1; // div
24031 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // rdx
24032 {
24033
24034#line 1955 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
24035
24036 // Full implementation of Java ldiv and lrem; checks for
24037 // special case as described in JVM spec., p.243 & p.271.
24038 //
24039 // normal case special case
24040 //
24041 // input : rax: dividend min_long
24042 // reg: divisor -1
24043 //
24044 // output: rax: quotient (= rax idiv reg) min_long
24045 // rdx: remainder (= rax irem reg) 0
24046 //
24047 // Code sequnce:
24048 //
24049 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx
24050 // 7: 00 00 80
24051 // a: 48 39 d0 cmp %rdx,%rax
24052 // d: 75 08 jne 17 <normal>
24053 // f: 33 d2 xor %edx,%edx
24054 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div
24055 // 15: 74 05 je 1c <done>
24056 // 0000000000000017 <normal>:
24057 // 17: 48 99 cqto
24058 // 19: 48 f7 f9 idiv $div
24059 // 000000000000001c <done>:
24060 MacroAssembler _masm(&cbuf);
24061 Label normal;
24062 Label done;
24063
24064 // mov $0x8000000000000000,%rdx
24065 ___masm. mov64(as_Register(RDX_enc), 0x8000000000000000);
24066
24067 // cmp %rdx,%rax
24068 ___masm. cmpq(as_Register(RAX_enc), as_Register(RDX_enc));
24069
24070 // jne 17 <normal>
24071 ___masm. jccb(Assembler::notEqual, normal)jccb_0(Assembler::notEqual, normal, "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 1991);
24072
24073 // xor %edx,%edx
24074 ___masm. xorl(as_Register(RDX_enc), as_Register(RDX_enc));
24075
24076 // cmp $0xffffffffffffffff,$div
24077 ___masm. cmpq(opnd_array(2)->as_Register(ra_,this,idx2)/* div */, -1);
24078
24079 // je 1e <done>
24080 ___masm. jccb(Assembler::equal, done)jccb_0(Assembler::equal, done, "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 2000);
24081
24082 // <normal>
24083 // cqto
24084 ___masm. bind(normal);
24085 ___masm. cdqq();
24086
24087 // idivq (note: must be emitted by the user of this rule)
24088 // <done>
24089 ___masm. idivq(opnd_array(2)->as_Register(ra_,this,idx2)/* div */);
24090 ___masm. bind(done);
24091
24092#line 24092 "ad_x86.cpp"
24093 }
24094}
24095
24096void loadConL_0x6666666666666667Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24097 cbuf.set_insts_mark();
24098 // Start at oper_input_base() and count operands
24099 unsigned idx0 = 1;
24100 unsigned idx1 = 1; //
24101 {
24102
24103#line 2249 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
24104
24105 int dstenc = opnd_array(0)->reg(ra_,this)/* dst */;
24106 if (dstenc < 8) {
24107 emit_opcode(cbuf, Assembler::REX_W);
24108 } else {
24109 emit_opcode(cbuf, Assembler::REX_WB);
24110 dstenc -= 8;
24111 }
24112 emit_opcode(cbuf, 0xB8 | dstenc);
24113 emit_d64(cbuf, (0x6666666666666667));
24114
24115#line 24115 "ad_x86.cpp"
24116 }
24117}
24118
24119void mul_hiNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24120 cbuf.set_insts_mark();
24121 // Start at oper_input_base() and count operands
24122 unsigned idx0 = 1;
24123 unsigned idx1 = 1; // src
24124 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // rax
24125 {
24126 C2_MacroAssembler _masm(&cbuf);
24127
24128#line 8642 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
24129
24130 ___masm. imulq(opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
24131
24132#line 24132 "ad_x86.cpp"
24133 }
24134}
24135
24136void sarL_rReg_63Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24137 cbuf.set_insts_mark();
24138 // Start at oper_input_base() and count operands
24139 unsigned idx0 = 1;
24140 unsigned idx1 = 1; // cr
24141 {
24142 C2_MacroAssembler _masm(&cbuf);
24143
24144#line 8653 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
24145
24146 ___masm. sarq(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, 63);
24147
24148#line 24148 "ad_x86.cpp"
24149 }
24150}
24151
24152void sarL_rReg_2Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24153 cbuf.set_insts_mark();
24154 // Start at oper_input_base() and count operands
24155 unsigned idx0 = 1;
24156 unsigned idx1 = 1; // cr
24157 {
24158 C2_MacroAssembler _masm(&cbuf);
24159
24160#line 8664 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
24161
24162 ___masm. sarq(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, 2);
24163
24164#line 24164 "ad_x86.cpp"
24165 }
24166}
24167
24168void modI_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24169 cbuf.set_insts_mark();
24170 // Start at oper_input_base() and count operands
24171 unsigned idx0 = 1;
24172 unsigned idx1 = 1; // rax
24173 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // div
24174 {
24175
24176#line 1897 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
24177
24178 // Full implementation of Java idiv and irem; checks for
24179 // special case as described in JVM spec., p.243 & p.271.
24180 //
24181 // normal case special case
24182 //
24183 // input : rax: dividend min_int
24184 // reg: divisor -1
24185 //
24186 // output: rax: quotient (= rax idiv reg) min_int
24187 // rdx: remainder (= rax irem reg) 0
24188 //
24189 // Code sequnce:
24190 //
24191 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax
24192 // 5: 75 07/08 jne e <normal>
24193 // 7: 33 d2 xor %edx,%edx
24194 // [div >= 8 -> offset + 1]
24195 // [REX_B]
24196 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div
24197 // c: 74 03/04 je 11 <done>
24198 // 000000000000000e <normal>:
24199 // e: 99 cltd
24200 // [div >= 8 -> offset + 1]
24201 // [REX_B]
24202 // f: f7 f9 idiv $div
24203 // 0000000000000011 <done>:
24204 MacroAssembler _masm(&cbuf);
24205 Label normal;
24206 Label done;
24207
24208 // cmp $0x80000000,%eax
24209 ___masm. cmp(as_Register(RAX_enc), 0x80000000);
24210
24211 // jne e <normal>
24212 ___masm. jccb(Assembler::notEqual, normal)jccb_0(Assembler::notEqual, normal, "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 1932);
24213
24214 // xor %edx,%edx
24215 ___masm. xorl(as_Register(RDX_enc), as_Register(RDX_enc));
24216
24217 // cmp $0xffffffffffffffff,%ecx
24218 ___masm. cmpl(opnd_array(2)->as_Register(ra_,this,idx2)/* div */, -1);
24219
24220 // je 11 <done>
24221 ___masm. jccb(Assembler::equal, done)jccb_0(Assembler::equal, done, "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 1941);
24222
24223 // <normal>
24224 // cltd
24225 ___masm. bind(normal);
24226 ___masm. cdql();
24227
24228 // idivl
24229 // <done>
24230 ___masm. idivl(opnd_array(2)->as_Register(ra_,this,idx2)/* div */);
24231 ___masm. bind(done);
24232
24233#line 24233 "ad_x86.cpp"
24234 }
24235}
24236
24237void modL_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24238 cbuf.set_insts_mark();
24239 // Start at oper_input_base() and count operands
24240 unsigned idx0 = 1;
24241 unsigned idx1 = 1; // rax
24242 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // div
24243 {
24244
24245#line 1955 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
24246
24247 // Full implementation of Java ldiv and lrem; checks for
24248 // special case as described in JVM spec., p.243 & p.271.
24249 //
24250 // normal case special case
24251 //
24252 // input : rax: dividend min_long
24253 // reg: divisor -1
24254 //
24255 // output: rax: quotient (= rax idiv reg) min_long
24256 // rdx: remainder (= rax irem reg) 0
24257 //
24258 // Code sequnce:
24259 //
24260 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx
24261 // 7: 00 00 80
24262 // a: 48 39 d0 cmp %rdx,%rax
24263 // d: 75 08 jne 17 <normal>
24264 // f: 33 d2 xor %edx,%edx
24265 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div
24266 // 15: 74 05 je 1c <done>
24267 // 0000000000000017 <normal>:
24268 // 17: 48 99 cqto
24269 // 19: 48 f7 f9 idiv $div
24270 // 000000000000001c <done>:
24271 MacroAssembler _masm(&cbuf);
24272 Label normal;
24273 Label done;
24274
24275 // mov $0x8000000000000000,%rdx
24276 ___masm. mov64(as_Register(RDX_enc), 0x8000000000000000);
24277
24278 // cmp %rdx,%rax
24279 ___masm. cmpq(as_Register(RAX_enc), as_Register(RDX_enc));
24280
24281 // jne 17 <normal>
24282 ___masm. jccb(Assembler::notEqual, normal)jccb_0(Assembler::notEqual, normal, "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 1991);
24283
24284 // xor %edx,%edx
24285 ___masm. xorl(as_Register(RDX_enc), as_Register(RDX_enc));
24286
24287 // cmp $0xffffffffffffffff,$div
24288 ___masm. cmpq(opnd_array(2)->as_Register(ra_,this,idx2)/* div */, -1);
24289
24290 // je 1e <done>
24291 ___masm. jccb(Assembler::equal, done)jccb_0(Assembler::equal, done, "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 2000);
24292
24293 // <normal>
24294 // cqto
24295 ___masm. bind(normal);
24296 ___masm. cdqq();
24297
24298 // idivq (note: must be emitted by the user of this rule)
24299 // <done>
24300 ___masm. idivq(opnd_array(2)->as_Register(ra_,this,idx2)/* div */);
24301 ___masm. bind(done);
24302
24303#line 24303 "ad_x86.cpp"
24304 }
24305}
24306
24307void salI_rReg_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24308 cbuf.set_insts_mark();
24309 // Start at oper_input_base() and count operands
24310 unsigned idx0 = 1;
24311 unsigned idx1 = 1; // dst
24312 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
24313 {
24314 C2_MacroAssembler _masm(&cbuf);
24315
24316#line 8735 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
24317
24318 ___masm. sall(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, opnd_array(2)->constant());
24319
24320#line 24320 "ad_x86.cpp"
24321 }
24322}
24323
24324void salI_mem_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24325 cbuf.set_insts_mark();
24326 // Start at oper_input_base() and count operands
24327 unsigned idx0 = 2;
24328 unsigned idx1 = 2; // dst
24329 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
24330 {
24331 C2_MacroAssembler _masm(&cbuf);
24332
24333#line 8748 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
24334
24335 ___masm. sall(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->constant());
24336
24337#line 24337 "ad_x86.cpp"
24338 }
24339}
24340
24341void salI_rReg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24342 cbuf.set_insts_mark();
24343 // Start at oper_input_base() and count operands
24344 unsigned idx0 = 1;
24345 unsigned idx1 = 1; // dst
24346 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
24347 {
24348 C2_MacroAssembler _masm(&cbuf);
24349
24350#line 8761 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
24351
24352 ___masm. sall(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, opnd_array(2)->constant());
24353
24354#line 24354 "ad_x86.cpp"
24355 }
24356}
24357
24358void salI_mem_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24359 cbuf.set_insts_mark();
24360 // Start at oper_input_base() and count operands
24361 unsigned idx0 = 2;
24362 unsigned idx1 = 2; // dst
24363 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
24364 {
24365 C2_MacroAssembler _masm(&cbuf);
24366
24367#line 8774 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
24368
24369 ___masm. sall(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->constant());
24370
24371#line 24371 "ad_x86.cpp"
24372 }
24373}
24374
24375void salI_rReg_CLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24376 cbuf.set_insts_mark();
24377 // Start at oper_input_base() and count operands
24378 unsigned idx0 = 1;
24379 unsigned idx1 = 1; // dst
24380 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
24381 {
24382 C2_MacroAssembler _masm(&cbuf);
24383
24384#line 8787 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
24385
24386 ___masm. sall(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */);
24387
24388#line 24388 "ad_x86.cpp"
24389 }
24390}
24391
24392void salI_mem_CLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24393 cbuf.set_insts_mark();
24394 // Start at oper_input_base() and count operands
24395 unsigned idx0 = 2;
24396 unsigned idx1 = 2; // dst
24397 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
24398 {
24399 C2_MacroAssembler _masm(&cbuf);
24400
24401#line 8800 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
24402
24403 ___masm. sall(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
24404
24405#line 24405 "ad_x86.cpp"
24406 }
24407}
24408
24409void sarI_rReg_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24410 cbuf.set_insts_mark();
24411 // Start at oper_input_base() and count operands
24412 unsigned idx0 = 1;
24413 unsigned idx1 = 1; // dst
24414 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
24415 {
24416 C2_MacroAssembler _masm(&cbuf);
24417
24418#line 8813 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
24419
24420 ___masm. sarl(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, opnd_array(2)->constant());
24421
24422#line 24422 "ad_x86.cpp"
24423 }
24424}
24425
24426void sarI_mem_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24427 cbuf.set_insts_mark();
24428 // Start at oper_input_base() and count operands
24429 unsigned idx0 = 2;
24430 unsigned idx1 = 2; // dst
24431 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
24432 {
24433 C2_MacroAssembler _masm(&cbuf);
24434
24435#line 8826 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
24436
24437 ___masm. sarl(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->constant());
24438
24439#line 24439 "ad_x86.cpp"
24440 }
24441}
24442
24443void sarI_rReg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24444 cbuf.set_insts_mark();
24445 // Start at oper_input_base() and count operands
24446 unsigned idx0 = 1;
24447 unsigned idx1 = 1; // dst
24448 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
24449 {
24450 C2_MacroAssembler _masm(&cbuf);
24451
24452#line 8839 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
24453
24454 ___masm. sarl(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, opnd_array(2)->constant());
24455
24456#line 24456 "ad_x86.cpp"
24457 }
24458}
24459
24460void sarI_mem_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24461 cbuf.set_insts_mark();
24462 // Start at oper_input_base() and count operands
24463 unsigned idx0 = 2;
24464 unsigned idx1 = 2; // dst
24465 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
24466 {
24467 C2_MacroAssembler _masm(&cbuf);
24468
24469#line 8852 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
24470
24471 ___masm. sarl(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->constant());
24472
24473#line 24473 "ad_x86.cpp"
24474 }
24475}
24476
24477void sarI_rReg_CLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24478 cbuf.set_insts_mark();
24479 // Start at oper_input_base() and count operands
24480 unsigned idx0 = 1;
24481 unsigned idx1 = 1; // dst
24482 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
24483 {
24484 C2_MacroAssembler _masm(&cbuf);
24485
24486#line 8864 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
24487
24488 ___masm. sarl(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */);
24489
24490#line 24490 "ad_x86.cpp"
24491 }
24492}
24493
24494void sarI_mem_CLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24495 cbuf.set_insts_mark();
24496 // Start at oper_input_base() and count operands
24497 unsigned idx0 = 2;
24498 unsigned idx1 = 2; // dst
24499 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
24500 {
24501 C2_MacroAssembler _masm(&cbuf);
24502
24503#line 8877 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
24504
24505 ___masm. sarl(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
24506
24507#line 24507 "ad_x86.cpp"
24508 }
24509}
24510
24511void shrI_rReg_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24512 cbuf.set_insts_mark();
24513 // Start at oper_input_base() and count operands
24514 unsigned idx0 = 1;
24515 unsigned idx1 = 1; // dst
24516 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
24517 {
24518 C2_MacroAssembler _masm(&cbuf);
24519
24520#line 8890 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
24521
24522 ___masm. shrl(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, opnd_array(2)->constant());
24523
24524#line 24524 "ad_x86.cpp"
24525 }
24526}
24527
24528void shrI_mem_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24529 cbuf.set_insts_mark();
24530 // Start at oper_input_base() and count operands
24531 unsigned idx0 = 2;
24532 unsigned idx1 = 2; // dst
24533 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
24534 {
24535 C2_MacroAssembler _masm(&cbuf);
24536
24537#line 8903 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
24538
24539 ___masm. shrl(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->constant());
24540
24541#line 24541 "ad_x86.cpp"
24542 }
24543}
24544
24545void shrI_rReg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24546 cbuf.set_insts_mark();
24547 // Start at oper_input_base() and count operands
24548 unsigned idx0 = 1;
24549 unsigned idx1 = 1; // dst
24550 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
24551 {
24552 C2_MacroAssembler _masm(&cbuf);
24553
24554#line 8916 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
24555
24556 ___masm. shrl(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, opnd_array(2)->constant());
24557
24558#line 24558 "ad_x86.cpp"
24559 }
24560}
24561
24562void shrI_mem_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24563 cbuf.set_insts_mark();
24564 // Start at oper_input_base() and count operands
24565 unsigned idx0 = 2;
24566 unsigned idx1 = 2; // dst
24567 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
24568 {
24569 C2_MacroAssembler _masm(&cbuf);
24570
24571#line 8929 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
24572
24573 ___masm. shrl(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->constant());
24574
24575#line 24575 "ad_x86.cpp"
24576 }
24577}
24578
24579void shrI_rReg_CLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24580 cbuf.set_insts_mark();
24581 // Start at oper_input_base() and count operands
24582 unsigned idx0 = 1;
24583 unsigned idx1 = 1; // dst
24584 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
24585 {
24586 C2_MacroAssembler _masm(&cbuf);
24587
24588#line 8942 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
24589
24590 ___masm. shrl(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */);
24591
24592#line 24592 "ad_x86.cpp"
24593 }
24594}
24595
24596void shrI_mem_CLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24597 cbuf.set_insts_mark();
24598 // Start at oper_input_base() and count operands
24599 unsigned idx0 = 2;
24600 unsigned idx1 = 2; // dst
24601 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
24602 {
24603 C2_MacroAssembler _masm(&cbuf);
24604
24605#line 8955 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
24606
24607 ___masm. shrl(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
24608
24609#line 24609 "ad_x86.cpp"
24610 }
24611}
24612
24613void salL_rReg_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24614 cbuf.set_insts_mark();
24615 // Start at oper_input_base() and count operands
24616 unsigned idx0 = 1;
24617 unsigned idx1 = 1; // dst
24618 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
24619 {
24620 C2_MacroAssembler _masm(&cbuf);
24621
24622#line 8969 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
24623
24624 ___masm. salq(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, opnd_array(2)->constant());
24625
24626#line 24626 "ad_x86.cpp"
24627 }
24628}
24629
24630void salL_mem_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24631 cbuf.set_insts_mark();
24632 // Start at oper_input_base() and count operands
24633 unsigned idx0 = 2;
24634 unsigned idx1 = 2; // dst
24635 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
24636 {
24637 C2_MacroAssembler _masm(&cbuf);
24638
24639#line 8982 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
24640
24641 ___masm. salq(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->constant());
24642
24643#line 24643 "ad_x86.cpp"
24644 }
24645}
24646
24647void salL_rReg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24648 cbuf.set_insts_mark();
24649 // Start at oper_input_base() and count operands
24650 unsigned idx0 = 1;
24651 unsigned idx1 = 1; // dst
24652 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
24653 {
24654 C2_MacroAssembler _masm(&cbuf);
24655
24656#line 8995 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
24657
24658 ___masm. salq(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, opnd_array(2)->constant());
24659
24660#line 24660 "ad_x86.cpp"
24661 }
24662}
24663
24664void salL_mem_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24665 cbuf.set_insts_mark();
24666 // Start at oper_input_base() and count operands
24667 unsigned idx0 = 2;
24668 unsigned idx1 = 2; // dst
24669 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
24670 {
24671 C2_MacroAssembler _masm(&cbuf);
24672
24673#line 9008 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
24674
24675 ___masm. salq(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->constant());
24676
24677#line 24677 "ad_x86.cpp"
24678 }
24679}
24680
24681void salL_rReg_CLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24682 cbuf.set_insts_mark();
24683 // Start at oper_input_base() and count operands
24684 unsigned idx0 = 1;
24685 unsigned idx1 = 1; // dst
24686 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
24687 {
24688 C2_MacroAssembler _masm(&cbuf);
24689
24690#line 9021 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
24691
24692 ___masm. salq(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */);
24693
24694#line 24694 "ad_x86.cpp"
24695 }
24696}
24697
24698void salL_mem_CLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24699 cbuf.set_insts_mark();
24700 // Start at oper_input_base() and count operands
24701 unsigned idx0 = 2;
24702 unsigned idx1 = 2; // dst
24703 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
24704 {
24705 C2_MacroAssembler _masm(&cbuf);
24706
24707#line 9034 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
24708
24709 ___masm. salq(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
24710
24711#line 24711 "ad_x86.cpp"
24712 }
24713}
24714
24715void sarL_rReg_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24716 cbuf.set_insts_mark();
24717 // Start at oper_input_base() and count operands
24718 unsigned idx0 = 1;
24719 unsigned idx1 = 1; // dst
24720 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
24721 {
24722 C2_MacroAssembler _masm(&cbuf);
24723
24724#line 9047 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
24725
24726 ___masm. sarq(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, opnd_array(2)->constant());
24727
24728#line 24728 "ad_x86.cpp"
24729 }
24730}
24731
24732void sarL_mem_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24733 cbuf.set_insts_mark();
24734 // Start at oper_input_base() and count operands
24735 unsigned idx0 = 2;
24736 unsigned idx1 = 2; // dst
24737 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
24738 {
24739 C2_MacroAssembler _masm(&cbuf);
24740
24741#line 9060 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
24742
24743 ___masm. sarq(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->constant());
24744
24745#line 24745 "ad_x86.cpp"
24746 }
24747}
24748
24749void sarL_rReg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24750 cbuf.set_insts_mark();
24751 // Start at oper_input_base() and count operands
24752 unsigned idx0 = 1;
24753 unsigned idx1 = 1; // dst
24754 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
24755 {
24756 C2_MacroAssembler _masm(&cbuf);
24757
24758#line 9073 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
24759
24760 ___masm. sarq(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, (unsigned char)(opnd_array(2)->constant()& 0x3F));
24761
24762#line 24762 "ad_x86.cpp"
24763 }
24764}
24765
24766void sarL_mem_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24767 cbuf.set_insts_mark();
24768 // Start at oper_input_base() and count operands
24769 unsigned idx0 = 2;
24770 unsigned idx1 = 2; // dst
24771 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
24772 {
24773 C2_MacroAssembler _masm(&cbuf);
24774
24775#line 9086 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
24776
24777 ___masm. sarq(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), (unsigned char)(opnd_array(2)->constant()& 0x3F));
24778
24779#line 24779 "ad_x86.cpp"
24780 }
24781}
24782
24783void sarL_rReg_CLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24784 cbuf.set_insts_mark();
24785 // Start at oper_input_base() and count operands
24786 unsigned idx0 = 1;
24787 unsigned idx1 = 1; // dst
24788 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
24789 {
24790 C2_MacroAssembler _masm(&cbuf);
24791
24792#line 9099 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
24793
24794 ___masm. sarq(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */);
24795
24796#line 24796 "ad_x86.cpp"
24797 }
24798}
24799
24800void sarL_mem_CLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24801 cbuf.set_insts_mark();
24802 // Start at oper_input_base() and count operands
24803 unsigned idx0 = 2;
24804 unsigned idx1 = 2; // dst
24805 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
24806 {
24807 C2_MacroAssembler _masm(&cbuf);
24808
24809#line 9112 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
24810
24811 ___masm. sarq(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
24812
24813#line 24813 "ad_x86.cpp"
24814 }
24815}
24816
24817void shrL_rReg_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24818 cbuf.set_insts_mark();
24819 // Start at oper_input_base() and count operands
24820 unsigned idx0 = 1;
24821 unsigned idx1 = 1; // dst
24822 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
24823 {
24824 C2_MacroAssembler _masm(&cbuf);
24825
24826#line 9125 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
24827
24828 ___masm. shrq(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, opnd_array(2)->constant());
24829
24830#line 24830 "ad_x86.cpp"
24831 }
24832}
24833
24834void shrL_mem_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24835 cbuf.set_insts_mark();
24836 // Start at oper_input_base() and count operands
24837 unsigned idx0 = 2;
24838 unsigned idx1 = 2; // dst
24839 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
24840 {
24841 C2_MacroAssembler _masm(&cbuf);
24842
24843#line 9138 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
24844
24845 ___masm. shrq(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->constant());
24846
24847#line 24847 "ad_x86.cpp"
24848 }
24849}
24850
24851void shrL_rReg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24852 cbuf.set_insts_mark();
24853 // Start at oper_input_base() and count operands
24854 unsigned idx0 = 1;
24855 unsigned idx1 = 1; // dst
24856 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
24857 {
24858 C2_MacroAssembler _masm(&cbuf);
24859
24860#line 9151 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
24861
24862 ___masm. shrq(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, opnd_array(2)->constant());
24863
24864#line 24864 "ad_x86.cpp"
24865 }
24866}
24867
24868void shrL_mem_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24869 cbuf.set_insts_mark();
24870 // Start at oper_input_base() and count operands
24871 unsigned idx0 = 2;
24872 unsigned idx1 = 2; // dst
24873 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
24874 {
24875 C2_MacroAssembler _masm(&cbuf);
24876
24877#line 9164 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
24878
24879 ___masm. shrq(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->constant());
24880
24881#line 24881 "ad_x86.cpp"
24882 }
24883}
24884
24885void shrL_rReg_CLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24886 cbuf.set_insts_mark();
24887 // Start at oper_input_base() and count operands
24888 unsigned idx0 = 1;
24889 unsigned idx1 = 1; // dst
24890 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
24891 {
24892 C2_MacroAssembler _masm(&cbuf);
24893
24894#line 9177 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
24895
24896 ___masm. shrq(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */);
24897
24898#line 24898 "ad_x86.cpp"
24899 }
24900}
24901
24902void shrL_mem_CLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24903 cbuf.set_insts_mark();
24904 // Start at oper_input_base() and count operands
24905 unsigned idx0 = 2;
24906 unsigned idx1 = 2; // dst
24907 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
24908 {
24909 C2_MacroAssembler _masm(&cbuf);
24910
24911#line 9190 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
24912
24913 ___masm. shrq(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
24914
24915#line 24915 "ad_x86.cpp"
24916 }
24917}
24918
24919void i2bNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24920 cbuf.set_insts_mark();
24921 // Start at oper_input_base() and count operands
24922 unsigned idx0 = 1;
24923 unsigned idx1 = 1; // src
24924 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // twentyfour
24925 {
24926 C2_MacroAssembler _masm(&cbuf);
24927
24928#line 9203 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
24929
24930 ___masm. movsbl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
24931
24932#line 24932 "ad_x86.cpp"
24933 }
24934}
24935
24936void i2sNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24937 cbuf.set_insts_mark();
24938 // Start at oper_input_base() and count operands
24939 unsigned idx0 = 1;
24940 unsigned idx1 = 1; // src
24941 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // sixteen
24942 {
24943 C2_MacroAssembler _masm(&cbuf);
24944
24945#line 9216 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
24946
24947 ___masm. movswl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
24948
24949#line 24949 "ad_x86.cpp"
24950 }
24951}
24952
24953void rolI_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24954 cbuf.set_insts_mark();
24955 // Start at oper_input_base() and count operands
24956 unsigned idx0 = 1;
24957 unsigned idx1 = 1; // dst
24958 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
24959 {
24960 C2_MacroAssembler _masm(&cbuf);
24961
24962#line 9231 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
24963
24964 ___masm. roll(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, opnd_array(2)->constant());
24965
24966#line 24966 "ad_x86.cpp"
24967 }
24968}
24969
24970void rolI_rReg_VarNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24971 cbuf.set_insts_mark();
24972 // Start at oper_input_base() and count operands
24973 unsigned idx0 = 1;
24974 unsigned idx1 = 1; // dst
24975 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
24976 {
24977 C2_MacroAssembler _masm(&cbuf);
24978
24979#line 9244 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
24980
24981 ___masm. roll(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */);
24982
24983#line 24983 "ad_x86.cpp"
24984 }
24985}
24986
24987void rorI_immI8_legacyNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
24988 cbuf.set_insts_mark();
24989 // Start at oper_input_base() and count operands
24990 unsigned idx0 = 1;
24991 unsigned idx1 = 1; // dst
24992 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
24993 {
24994 C2_MacroAssembler _masm(&cbuf);
24995
24996#line 9257 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
24997
24998 ___masm. rorl(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, opnd_array(2)->constant());
24999
25000#line 25000 "ad_x86.cpp"
25001 }
25002}
25003
25004void rorI_immI8Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25005 cbuf.set_insts_mark();
25006 // Start at oper_input_base() and count operands
25007 unsigned idx0 = 1;
25008 unsigned idx1 = 1; // dst
25009 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
25010 {
25011 C2_MacroAssembler _masm(&cbuf);
25012
25013#line 9269 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
25014
25015 ___masm. rorxd(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, opnd_array(2)->constant());
25016
25017#line 25017 "ad_x86.cpp"
25018 }
25019}
25020
25021void rorI_rReg_VarNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25022 cbuf.set_insts_mark();
25023 // Start at oper_input_base() and count operands
25024 unsigned idx0 = 1;
25025 unsigned idx1 = 1; // dst
25026 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
25027 {
25028 C2_MacroAssembler _masm(&cbuf);
25029
25030#line 9282 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
25031
25032 ___masm. rorl(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */);
25033
25034#line 25034 "ad_x86.cpp"
25035 }
25036}
25037
25038void rolL_immI8Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25039 cbuf.set_insts_mark();
25040 // Start at oper_input_base() and count operands
25041 unsigned idx0 = 1;
25042 unsigned idx1 = 1; // dst
25043 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
25044 {
25045 C2_MacroAssembler _masm(&cbuf);
25046
25047#line 9296 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
25048
25049 ___masm. rolq(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, opnd_array(2)->constant());
25050
25051#line 25051 "ad_x86.cpp"
25052 }
25053}
25054
25055void rolL_rReg_VarNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25056 cbuf.set_insts_mark();
25057 // Start at oper_input_base() and count operands
25058 unsigned idx0 = 1;
25059 unsigned idx1 = 1; // dst
25060 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
25061 {
25062 C2_MacroAssembler _masm(&cbuf);
25063
25064#line 9309 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
25065
25066 ___masm. rolq(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */);
25067
25068#line 25068 "ad_x86.cpp"
25069 }
25070}
25071
25072void rorL_immI8_legacyNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25073 cbuf.set_insts_mark();
25074 // Start at oper_input_base() and count operands
25075 unsigned idx0 = 1;
25076 unsigned idx1 = 1; // dst
25077 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
25078 {
25079 C2_MacroAssembler _masm(&cbuf);
25080
25081#line 9323 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
25082
25083 ___masm. rorq(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, opnd_array(2)->constant());
25084
25085#line 25085 "ad_x86.cpp"
25086 }
25087}
25088
25089void rorL_immI8Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25090 cbuf.set_insts_mark();
25091 // Start at oper_input_base() and count operands
25092 unsigned idx0 = 1;
25093 unsigned idx1 = 1; // dst
25094 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
25095 {
25096 C2_MacroAssembler _masm(&cbuf);
25097
25098#line 9336 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
25099
25100 ___masm. rorxq(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, opnd_array(2)->constant());
25101
25102#line 25102 "ad_x86.cpp"
25103 }
25104}
25105
25106void rorL_rReg_VarNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25107 cbuf.set_insts_mark();
25108 // Start at oper_input_base() and count operands
25109 unsigned idx0 = 1;
25110 unsigned idx1 = 1; // dst
25111 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
25112 {
25113 C2_MacroAssembler _masm(&cbuf);
25114
25115#line 9349 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
25116
25117 ___masm. rorq(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */);
25118
25119#line 25119 "ad_x86.cpp"
25120 }
25121}
25122
25123void andI_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25124 cbuf.set_insts_mark();
25125 // Start at oper_input_base() and count operands
25126 unsigned idx0 = 1;
25127 unsigned idx1 = 1; // dst
25128 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
25129 {
25130 C2_MacroAssembler _masm(&cbuf);
25131
25132#line 9368 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
25133
25134 ___masm. andl(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, opnd_array(2)->as_Register(ra_,this,idx2)/* src */);
25135
25136#line 25136 "ad_x86.cpp"
25137 }
25138}
25139
25140void andI_rReg_imm255Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25141 cbuf.set_insts_mark();
25142 // Start at oper_input_base() and count operands
25143 unsigned idx0 = 1;
25144 unsigned idx1 = 1; // dst
25145 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
25146 {
25147 C2_MacroAssembler _masm(&cbuf);
25148
25149#line 9380 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
25150
25151 ___masm. movzbl(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* dst */);
25152
25153#line 25153 "ad_x86.cpp"
25154 }
25155}
25156
25157void andI2L_rReg_imm255Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25158 cbuf.set_insts_mark();
25159 // Start at oper_input_base() and count operands
25160 unsigned idx0 = 1;
25161 unsigned idx1 = 1; // src
25162 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask
25163 {
25164 C2_MacroAssembler _masm(&cbuf);
25165
25166#line 9392 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
25167
25168 ___masm. movzbl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
25169
25170#line 25170 "ad_x86.cpp"
25171 }
25172}
25173
25174void andI_rReg_imm65535Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25175 cbuf.set_insts_mark();
25176 // Start at oper_input_base() and count operands
25177 unsigned idx0 = 1;
25178 unsigned idx1 = 1; // dst
25179 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
25180 {
25181 C2_MacroAssembler _masm(&cbuf);
25182
25183#line 9404 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
25184
25185 ___masm. movzwl(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* dst */);
25186
25187#line 25187 "ad_x86.cpp"
25188 }
25189}
25190
25191void andI2L_rReg_imm65535Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25192 cbuf.set_insts_mark();
25193 // Start at oper_input_base() and count operands
25194 unsigned idx0 = 1;
25195 unsigned idx1 = 1; // src
25196 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask
25197 {
25198 C2_MacroAssembler _masm(&cbuf);
25199
25200#line 9416 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
25201
25202 ___masm. movzwl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
25203
25204#line 25204 "ad_x86.cpp"
25205 }
25206}
25207
25208void convI2LAndI_reg_immIbitmaskNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25209 cbuf.set_insts_mark();
25210 // Start at oper_input_base() and count operands
25211 unsigned idx0 = 1;
25212 unsigned idx1 = 1; // src
25213 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask
25214 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
25215 {
25216 C2_MacroAssembler _masm(&cbuf);
25217
25218#line 9430 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
25219
25220 ___masm. movl(opnd_array(3)->as_Register(ra_,this,idx3)/* tmp */, exact_log2(opnd_array(2)->constant()+ 1));
25221 ___masm. bzhiq(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */, opnd_array(3)->as_Register(ra_,this,idx3)/* tmp */);
25222
25223#line 25223 "ad_x86.cpp"
25224 }
25225}
25226
25227void andI_rReg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25228 cbuf.set_insts_mark();
25229 // Start at oper_input_base() and count operands
25230 unsigned idx0 = 1;
25231 unsigned idx1 = 1; // dst
25232 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
25233 {
25234 C2_MacroAssembler _masm(&cbuf);
25235
25236#line 9444 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
25237
25238 ___masm. andl(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, opnd_array(2)->constant());
25239
25240#line 25240 "ad_x86.cpp"
25241 }
25242}
25243
25244void andI_rReg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25245 cbuf.set_insts_mark();
25246 // Start at oper_input_base() and count operands
25247 unsigned idx0 = 2;
25248 unsigned idx1 = 2; // dst
25249 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
25250 {
25251 C2_MacroAssembler _masm(&cbuf);
25252
25253#line 9458 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
25254
25255 ___masm. andl(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
25256
25257#line 25257 "ad_x86.cpp"
25258 }
25259}
25260
25261void andI_rReg_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25262 cbuf.set_insts_mark();
25263 // Start at oper_input_base() and count operands
25264 unsigned idx0 = 2;
25265 unsigned idx1 = 2; // src
25266 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
25267 {
25268 C2_MacroAssembler _masm(&cbuf);
25269
25270#line 9458 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
25271
25272 ___masm. andl(opnd_array(2)->as_Register(ra_,this,idx2)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
25273
25274#line 25274 "ad_x86.cpp"
25275 }
25276}
25277
25278void andB_mem_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25279 cbuf.set_insts_mark();
25280 // Start at oper_input_base() and count operands
25281 unsigned idx0 = 2;
25282 unsigned idx1 = 2; // dst
25283 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
25284 {
25285 C2_MacroAssembler _masm(&cbuf);
25286
25287#line 9472 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
25288
25289 ___masm. andb(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_Register(ra_,this,idx2)/* src */);
25290
25291#line 25291 "ad_x86.cpp"
25292 }
25293}
25294
25295void andB_mem_rReg_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25296 cbuf.set_insts_mark();
25297 // Start at oper_input_base() and count operands
25298 unsigned idx0 = 2;
25299 unsigned idx1 = 2; // dst
25300 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
25301 {
25302 C2_MacroAssembler _masm(&cbuf);
25303
25304#line 9472 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
25305
25306 ___masm. andb(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_Register(ra_,this,idx2)/* src */);
25307
25308#line 25308 "ad_x86.cpp"
25309 }
25310}
25311
25312void andI_mem_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25313 cbuf.set_insts_mark();
25314 // Start at oper_input_base() and count operands
25315 unsigned idx0 = 2;
25316 unsigned idx1 = 2; // dst
25317 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
25318 {
25319 C2_MacroAssembler _masm(&cbuf);
25320
25321#line 9485 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
25322
25323 ___masm. andl(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_Register(ra_,this,idx2)/* src */);
25324
25325#line 25325 "ad_x86.cpp"
25326 }
25327}
25328
25329void andI_mem_rReg_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25330 cbuf.set_insts_mark();
25331 // Start at oper_input_base() and count operands
25332 unsigned idx0 = 2;
25333 unsigned idx1 = 2; // dst
25334 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
25335 {
25336 C2_MacroAssembler _masm(&cbuf);
25337
25338#line 9485 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
25339
25340 ___masm. andl(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_Register(ra_,this,idx2)/* src */);
25341
25342#line 25342 "ad_x86.cpp"
25343 }
25344}
25345
25346void andI_mem_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25347 cbuf.set_insts_mark();
25348 // Start at oper_input_base() and count operands
25349 unsigned idx0 = 2;
25350 unsigned idx1 = 2; // dst
25351 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
25352 {
25353 C2_MacroAssembler _masm(&cbuf);
25354
25355#line 9499 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
25356
25357 ___masm. andl(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->constant());
25358
25359#line 25359 "ad_x86.cpp"
25360 }
25361}
25362
25363void andnI_rReg_rReg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25364 cbuf.set_insts_mark();
25365 // Start at oper_input_base() and count operands
25366 unsigned idx0 = 2;
25367 unsigned idx1 = 2; // src1
25368 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1
25369 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // src2
25370 {
25371 C2_MacroAssembler _masm(&cbuf);
25372
25373#line 9514 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
25374
25375 ___masm. andnl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */, Address::make_raw(opnd_array(3)->base(ra_,this,idx3), opnd_array(3)->index(ra_,this,idx3), opnd_array(3)->scale(), opnd_array(3)->disp(ra_,this,idx3), opnd_array(3)->disp_reloc()));
25376
25377#line 25377 "ad_x86.cpp"
25378 }
25379}
25380
25381void andnI_rReg_rReg_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25382 cbuf.set_insts_mark();
25383 // Start at oper_input_base() and count operands
25384 unsigned idx0 = 2;
25385 unsigned idx1 = 2; // src2
25386 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src1
25387 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // minus_1
25388 {
25389 C2_MacroAssembler _masm(&cbuf);
25390
25391#line 9514 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
25392
25393 ___masm. andnl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(2)->as_Register(ra_,this,idx2)/* src1 */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
25394
25395#line 25395 "ad_x86.cpp"
25396 }
25397}
25398
25399void andnI_rReg_rReg_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25400 cbuf.set_insts_mark();
25401 // Start at oper_input_base() and count operands
25402 unsigned idx0 = 1;
25403 unsigned idx1 = 1; // src1
25404 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1
25405 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // src2
25406 {
25407 C2_MacroAssembler _masm(&cbuf);
25408
25409#line 9527 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
25410
25411 ___masm. andnl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */, opnd_array(3)->as_Register(ra_,this,idx3)/* src2 */);
25412
25413#line 25413 "ad_x86.cpp"
25414 }
25415}
25416
25417void andnI_rReg_rReg_rReg_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25418 cbuf.set_insts_mark();
25419 // Start at oper_input_base() and count operands
25420 unsigned idx0 = 1;
25421 unsigned idx1 = 1; // src2
25422 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src1
25423 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // minus_1
25424 {
25425 C2_MacroAssembler _masm(&cbuf);
25426
25427#line 9527 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
25428
25429 ___masm. andnl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(2)->as_Register(ra_,this,idx2)/* src1 */, opnd_array(1)->as_Register(ra_,this,idx1)/* src2 */);
25430
25431#line 25431 "ad_x86.cpp"
25432 }
25433}
25434
25435void blsiI_rReg_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25436 cbuf.set_insts_mark();
25437 // Start at oper_input_base() and count operands
25438 unsigned idx0 = 1;
25439 unsigned idx1 = 1; // imm_zero
25440 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
25441 {
25442 C2_MacroAssembler _masm(&cbuf);
25443
25444#line 9540 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
25445
25446 ___masm. blsil(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(2)->as_Register(ra_,this,idx2)/* src */);
25447
25448#line 25448 "ad_x86.cpp"
25449 }
25450}
25451
25452void blsiI_rReg_rReg_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25453 cbuf.set_insts_mark();
25454 // Start at oper_input_base() and count operands
25455 unsigned idx0 = 1;
25456 unsigned idx1 = 1; // src
25457 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // imm_zero
25458 {
25459 C2_MacroAssembler _masm(&cbuf);
25460
25461#line 9540 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
25462
25463 ___masm. blsil(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
25464
25465#line 25465 "ad_x86.cpp"
25466 }
25467}
25468
25469void blsiI_rReg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25470 cbuf.set_insts_mark();
25471 // Start at oper_input_base() and count operands
25472 unsigned idx0 = 2;
25473 unsigned idx1 = 2; // imm_zero
25474 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
25475 {
25476 C2_MacroAssembler _masm(&cbuf);
25477
25478#line 9554 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
25479
25480 ___masm. blsil(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
25481
25482#line 25482 "ad_x86.cpp"
25483 }
25484}
25485
25486void blsiI_rReg_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25487 cbuf.set_insts_mark();
25488 // Start at oper_input_base() and count operands
25489 unsigned idx0 = 2;
25490 unsigned idx1 = 2; // src
25491 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // imm_zero
25492 {
25493 C2_MacroAssembler _masm(&cbuf);
25494
25495#line 9554 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
25496
25497 ___masm. blsil(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
25498
25499#line 25499 "ad_x86.cpp"
25500 }
25501}
25502
25503void blsmskI_rReg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25504 cbuf.set_insts_mark();
25505 // Start at oper_input_base() and count operands
25506 unsigned idx0 = 2;
25507 unsigned idx1 = 2; // src
25508 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1
25509 {
25510 C2_MacroAssembler _masm(&cbuf);
25511
25512#line 9569 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
25513
25514 ___masm. blsmskl(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
25515
25516#line 25516 "ad_x86.cpp"
25517 }
25518}
25519
25520void blsmskI_rReg_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25521 cbuf.set_insts_mark();
25522 // Start at oper_input_base() and count operands
25523 unsigned idx0 = 2;
25524 unsigned idx1 = 2; // src
25525 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1
25526 {
25527 C2_MacroAssembler _masm(&cbuf);
25528
25529#line 9569 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
25530
25531 ___masm. blsmskl(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
25532
25533#line 25533 "ad_x86.cpp"
25534 }
25535}
25536
25537void blsmskI_rReg_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25538 cbuf.set_insts_mark();
25539 // Start at oper_input_base() and count operands
25540 unsigned idx0 = 1;
25541 unsigned idx1 = 1; // src
25542 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1
25543 {
25544 C2_MacroAssembler _masm(&cbuf);
25545
25546#line 9583 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
25547
25548 ___masm. blsmskl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
25549
25550#line 25550 "ad_x86.cpp"
25551 }
25552}
25553
25554void blsmskI_rReg_rReg_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25555 cbuf.set_insts_mark();
25556 // Start at oper_input_base() and count operands
25557 unsigned idx0 = 1;
25558 unsigned idx1 = 1; // src
25559 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1
25560 {
25561 C2_MacroAssembler _masm(&cbuf);
25562
25563#line 9583 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
25564
25565 ___masm. blsmskl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
25566
25567#line 25567 "ad_x86.cpp"
25568 }
25569}
25570
25571void blsrI_rReg_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25572 cbuf.set_insts_mark();
25573 // Start at oper_input_base() and count operands
25574 unsigned idx0 = 1;
25575 unsigned idx1 = 1; // src
25576 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1
25577 {
25578 C2_MacroAssembler _masm(&cbuf);
25579
25580#line 9598 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
25581
25582 ___masm. blsrl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
25583
25584#line 25584 "ad_x86.cpp"
25585 }
25586}
25587
25588void blsrI_rReg_rReg_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25589 cbuf.set_insts_mark();
25590 // Start at oper_input_base() and count operands
25591 unsigned idx0 = 1;
25592 unsigned idx1 = 1; // src
25593 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1
25594 {
25595 C2_MacroAssembler _masm(&cbuf);
25596
25597#line 9598 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
25598
25599 ___masm. blsrl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
25600
25601#line 25601 "ad_x86.cpp"
25602 }
25603}
25604
25605void blsrI_rReg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25606 cbuf.set_insts_mark();
25607 // Start at oper_input_base() and count operands
25608 unsigned idx0 = 2;
25609 unsigned idx1 = 2; // src
25610 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1
25611 {
25612 C2_MacroAssembler _masm(&cbuf);
25613
25614#line 9614 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
25615
25616 ___masm. blsrl(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
25617
25618#line 25618 "ad_x86.cpp"
25619 }
25620}
25621
25622void blsrI_rReg_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25623 cbuf.set_insts_mark();
25624 // Start at oper_input_base() and count operands
25625 unsigned idx0 = 2;
25626 unsigned idx1 = 2; // src
25627 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1
25628 {
25629 C2_MacroAssembler _masm(&cbuf);
25630
25631#line 9614 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
25632
25633 ___masm. blsrl(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
25634
25635#line 25635 "ad_x86.cpp"
25636 }
25637}
25638
25639void orI_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25640 cbuf.set_insts_mark();
25641 // Start at oper_input_base() and count operands
25642 unsigned idx0 = 1;
25643 unsigned idx1 = 1; // dst
25644 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
25645 {
25646 C2_MacroAssembler _masm(&cbuf);
25647
25648#line 9629 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
25649
25650 ___masm. orl(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, opnd_array(2)->as_Register(ra_,this,idx2)/* src */);
25651
25652#line 25652 "ad_x86.cpp"
25653 }
25654}
25655
25656void orI_rReg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25657 cbuf.set_insts_mark();
25658 // Start at oper_input_base() and count operands
25659 unsigned idx0 = 1;
25660 unsigned idx1 = 1; // dst
25661 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
25662 {
25663 C2_MacroAssembler _masm(&cbuf);
25664
25665#line 9642 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
25666
25667 ___masm. orl(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, opnd_array(2)->constant());
25668
25669#line 25669 "ad_x86.cpp"
25670 }
25671}
25672
25673void orI_rReg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25674 cbuf.set_insts_mark();
25675 // Start at oper_input_base() and count operands
25676 unsigned idx0 = 2;
25677 unsigned idx1 = 2; // dst
25678 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
25679 {
25680 C2_MacroAssembler _masm(&cbuf);
25681
25682#line 9656 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
25683
25684 ___masm. orl(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
25685
25686#line 25686 "ad_x86.cpp"
25687 }
25688}
25689
25690void orI_rReg_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25691 cbuf.set_insts_mark();
25692 // Start at oper_input_base() and count operands
25693 unsigned idx0 = 2;
25694 unsigned idx1 = 2; // src
25695 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
25696 {
25697 C2_MacroAssembler _masm(&cbuf);
25698
25699#line 9656 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
25700
25701 ___masm. orl(opnd_array(2)->as_Register(ra_,this,idx2)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
25702
25703#line 25703 "ad_x86.cpp"
25704 }
25705}
25706
25707void orB_mem_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25708 cbuf.set_insts_mark();
25709 // Start at oper_input_base() and count operands
25710 unsigned idx0 = 2;
25711 unsigned idx1 = 2; // dst
25712 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
25713 {
25714 C2_MacroAssembler _masm(&cbuf);
25715
25716#line 9670 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
25717
25718 ___masm. orb(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_Register(ra_,this,idx2)/* src */);
25719
25720#line 25720 "ad_x86.cpp"
25721 }
25722}
25723
25724void orB_mem_rReg_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25725 cbuf.set_insts_mark();
25726 // Start at oper_input_base() and count operands
25727 unsigned idx0 = 2;
25728 unsigned idx1 = 2; // dst
25729 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
25730 {
25731 C2_MacroAssembler _masm(&cbuf);
25732
25733#line 9670 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
25734
25735 ___masm. orb(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_Register(ra_,this,idx2)/* src */);
25736
25737#line 25737 "ad_x86.cpp"
25738 }
25739}
25740
25741void orI_mem_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25742 cbuf.set_insts_mark();
25743 // Start at oper_input_base() and count operands
25744 unsigned idx0 = 2;
25745 unsigned idx1 = 2; // dst
25746 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
25747 {
25748 C2_MacroAssembler _masm(&cbuf);
25749
25750#line 9683 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
25751
25752 ___masm. orl(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_Register(ra_,this,idx2)/* src */);
25753
25754#line 25754 "ad_x86.cpp"
25755 }
25756}
25757
25758void orI_mem_rReg_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25759 cbuf.set_insts_mark();
25760 // Start at oper_input_base() and count operands
25761 unsigned idx0 = 2;
25762 unsigned idx1 = 2; // dst
25763 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
25764 {
25765 C2_MacroAssembler _masm(&cbuf);
25766
25767#line 9683 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
25768
25769 ___masm. orl(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_Register(ra_,this,idx2)/* src */);
25770
25771#line 25771 "ad_x86.cpp"
25772 }
25773}
25774
25775void orI_mem_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25776 cbuf.set_insts_mark();
25777 // Start at oper_input_base() and count operands
25778 unsigned idx0 = 2;
25779 unsigned idx1 = 2; // dst
25780 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
25781 {
25782 C2_MacroAssembler _masm(&cbuf);
25783
25784#line 9697 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
25785
25786 ___masm. orl(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->constant());
25787
25788#line 25788 "ad_x86.cpp"
25789 }
25790}
25791
25792void xorI_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25793 cbuf.set_insts_mark();
25794 // Start at oper_input_base() and count operands
25795 unsigned idx0 = 1;
25796 unsigned idx1 = 1; // dst
25797 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
25798 {
25799 C2_MacroAssembler _masm(&cbuf);
25800
25801#line 9711 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
25802
25803 ___masm. xorl(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, opnd_array(2)->as_Register(ra_,this,idx2)/* src */);
25804
25805#line 25805 "ad_x86.cpp"
25806 }
25807}
25808
25809void xorI_rReg_im1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25810 cbuf.set_insts_mark();
25811 // Start at oper_input_base() and count operands
25812 unsigned idx0 = 1;
25813 unsigned idx1 = 1; // dst
25814 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // imm
25815 {
25816 C2_MacroAssembler _masm(&cbuf);
25817
25818#line 9722 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
25819
25820 ___masm. notl(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */);
25821
25822#line 25822 "ad_x86.cpp"
25823 }
25824}
25825
25826void xorI_rReg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25827 cbuf.set_insts_mark();
25828 // Start at oper_input_base() and count operands
25829 unsigned idx0 = 1;
25830 unsigned idx1 = 1; // dst
25831 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
25832 {
25833 C2_MacroAssembler _masm(&cbuf);
25834
25835#line 9735 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
25836
25837 ___masm. xorl(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, opnd_array(2)->constant());
25838
25839#line 25839 "ad_x86.cpp"
25840 }
25841}
25842
25843void xorI_rReg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25844 cbuf.set_insts_mark();
25845 // Start at oper_input_base() and count operands
25846 unsigned idx0 = 2;
25847 unsigned idx1 = 2; // dst
25848 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
25849 {
25850 C2_MacroAssembler _masm(&cbuf);
25851
25852#line 9749 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
25853
25854 ___masm. xorl(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
25855
25856#line 25856 "ad_x86.cpp"
25857 }
25858}
25859
25860void xorI_rReg_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25861 cbuf.set_insts_mark();
25862 // Start at oper_input_base() and count operands
25863 unsigned idx0 = 2;
25864 unsigned idx1 = 2; // src
25865 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
25866 {
25867 C2_MacroAssembler _masm(&cbuf);
25868
25869#line 9749 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
25870
25871 ___masm. xorl(opnd_array(2)->as_Register(ra_,this,idx2)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
25872
25873#line 25873 "ad_x86.cpp"
25874 }
25875}
25876
25877void xorB_mem_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25878 cbuf.set_insts_mark();
25879 // Start at oper_input_base() and count operands
25880 unsigned idx0 = 2;
25881 unsigned idx1 = 2; // dst
25882 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
25883 {
25884 C2_MacroAssembler _masm(&cbuf);
25885
25886#line 9763 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
25887
25888 ___masm. xorb(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_Register(ra_,this,idx2)/* src */);
25889
25890#line 25890 "ad_x86.cpp"
25891 }
25892}
25893
25894void xorB_mem_rReg_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25895 cbuf.set_insts_mark();
25896 // Start at oper_input_base() and count operands
25897 unsigned idx0 = 2;
25898 unsigned idx1 = 2; // dst
25899 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
25900 {
25901 C2_MacroAssembler _masm(&cbuf);
25902
25903#line 9763 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
25904
25905 ___masm. xorb(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_Register(ra_,this,idx2)/* src */);
25906
25907#line 25907 "ad_x86.cpp"
25908 }
25909}
25910
25911void xorI_mem_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25912 cbuf.set_insts_mark();
25913 // Start at oper_input_base() and count operands
25914 unsigned idx0 = 2;
25915 unsigned idx1 = 2; // dst
25916 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
25917 {
25918 C2_MacroAssembler _masm(&cbuf);
25919
25920#line 9776 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
25921
25922 ___masm. xorl(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_Register(ra_,this,idx2)/* src */);
25923
25924#line 25924 "ad_x86.cpp"
25925 }
25926}
25927
25928void xorI_mem_rReg_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25929 cbuf.set_insts_mark();
25930 // Start at oper_input_base() and count operands
25931 unsigned idx0 = 2;
25932 unsigned idx1 = 2; // dst
25933 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
25934 {
25935 C2_MacroAssembler _masm(&cbuf);
25936
25937#line 9776 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
25938
25939 ___masm. xorl(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_Register(ra_,this,idx2)/* src */);
25940
25941#line 25941 "ad_x86.cpp"
25942 }
25943}
25944
25945void xorI_mem_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25946 cbuf.set_insts_mark();
25947 // Start at oper_input_base() and count operands
25948 unsigned idx0 = 2;
25949 unsigned idx1 = 2; // dst
25950 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
25951 {
25952 C2_MacroAssembler _masm(&cbuf);
25953
25954#line 9790 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
25955
25956 ___masm. xorl(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->constant());
25957
25958#line 25958 "ad_x86.cpp"
25959 }
25960}
25961
25962void andL_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25963 cbuf.set_insts_mark();
25964 // Start at oper_input_base() and count operands
25965 unsigned idx0 = 1;
25966 unsigned idx1 = 1; // dst
25967 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
25968 {
25969 C2_MacroAssembler _masm(&cbuf);
25970
25971#line 9807 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
25972
25973 ___masm. andq(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, opnd_array(2)->as_Register(ra_,this,idx2)/* src */);
25974
25975#line 25975 "ad_x86.cpp"
25976 }
25977}
25978
25979void andL_rReg_imm255Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25980 cbuf.set_insts_mark();
25981 // Start at oper_input_base() and count operands
25982 unsigned idx0 = 1;
25983 unsigned idx1 = 1; // dst
25984 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
25985 {
25986 C2_MacroAssembler _masm(&cbuf);
25987
25988#line 9819 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
25989
25990 ___masm. movzbq(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* dst */);
25991
25992#line 25992 "ad_x86.cpp"
25993 }
25994}
25995
25996void andL_rReg_imm65535Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
25997 cbuf.set_insts_mark();
25998 // Start at oper_input_base() and count operands
25999 unsigned idx0 = 1;
26000 unsigned idx1 = 1; // dst
26001 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
26002 {
26003 C2_MacroAssembler _masm(&cbuf);
26004
26005#line 9831 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
26006
26007 ___masm. movzwq(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* dst */);
26008
26009#line 26009 "ad_x86.cpp"
26010 }
26011}
26012
26013void andL_rReg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26014 cbuf.set_insts_mark();
26015 // Start at oper_input_base() and count operands
26016 unsigned idx0 = 1;
26017 unsigned idx1 = 1; // dst
26018 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
26019 {
26020 C2_MacroAssembler _masm(&cbuf);
26021
26022#line 9844 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
26023
26024 ___masm. andq(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, opnd_array(2)->constantL());
26025
26026#line 26026 "ad_x86.cpp"
26027 }
26028}
26029
26030void andL_rReg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26031 cbuf.set_insts_mark();
26032 // Start at oper_input_base() and count operands
26033 unsigned idx0 = 2;
26034 unsigned idx1 = 2; // dst
26035 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
26036 {
26037 C2_MacroAssembler _masm(&cbuf);
26038
26039#line 9858 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
26040
26041 ___masm. andq(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
26042
26043#line 26043 "ad_x86.cpp"
26044 }
26045}
26046
26047void andL_rReg_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26048 cbuf.set_insts_mark();
26049 // Start at oper_input_base() and count operands
26050 unsigned idx0 = 2;
26051 unsigned idx1 = 2; // src
26052 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
26053 {
26054 C2_MacroAssembler _masm(&cbuf);
26055
26056#line 9858 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
26057
26058 ___masm. andq(opnd_array(2)->as_Register(ra_,this,idx2)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
26059
26060#line 26060 "ad_x86.cpp"
26061 }
26062}
26063
26064void andL_mem_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26065 cbuf.set_insts_mark();
26066 // Start at oper_input_base() and count operands
26067 unsigned idx0 = 2;
26068 unsigned idx1 = 2; // dst
26069 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
26070 {
26071 C2_MacroAssembler _masm(&cbuf);
26072
26073#line 9872 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
26074
26075 ___masm. andq(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_Register(ra_,this,idx2)/* src */);
26076
26077#line 26077 "ad_x86.cpp"
26078 }
26079}
26080
26081void andL_mem_rReg_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26082 cbuf.set_insts_mark();
26083 // Start at oper_input_base() and count operands
26084 unsigned idx0 = 2;
26085 unsigned idx1 = 2; // dst
26086 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
26087 {
26088 C2_MacroAssembler _masm(&cbuf);
26089
26090#line 9872 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
26091
26092 ___masm. andq(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_Register(ra_,this,idx2)/* src */);
26093
26094#line 26094 "ad_x86.cpp"
26095 }
26096}
26097
26098void andL_mem_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26099 cbuf.set_insts_mark();
26100 // Start at oper_input_base() and count operands
26101 unsigned idx0 = 2;
26102 unsigned idx1 = 2; // dst
26103 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
26104 {
26105 C2_MacroAssembler _masm(&cbuf);
26106
26107#line 9886 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
26108
26109 ___masm. andq(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->constantL());
26110
26111#line 26111 "ad_x86.cpp"
26112 }
26113}
26114
26115void btrL_mem_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26116 cbuf.set_insts_mark();
26117 // Start at oper_input_base() and count operands
26118 unsigned idx0 = 2;
26119 unsigned idx1 = 2; // dst
26120 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
26121 {
26122 C2_MacroAssembler _masm(&cbuf);
26123
26124#line 9903 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
26125
26126 ___masm. btrq(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), log2i_exact((julong)~opnd_array(2)->constantL()));
26127
26128#line 26128 "ad_x86.cpp"
26129 }
26130}
26131
26132void andnL_rReg_rReg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26133 cbuf.set_insts_mark();
26134 // Start at oper_input_base() and count operands
26135 unsigned idx0 = 2;
26136 unsigned idx1 = 2; // src1
26137 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1
26138 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // src2
26139 {
26140 C2_MacroAssembler _masm(&cbuf);
26141
26142#line 9918 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
26143
26144 ___masm. andnq(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */, Address::make_raw(opnd_array(3)->base(ra_,this,idx3), opnd_array(3)->index(ra_,this,idx3), opnd_array(3)->scale(), opnd_array(3)->disp(ra_,this,idx3), opnd_array(3)->disp_reloc()));
26145
26146#line 26146 "ad_x86.cpp"
26147 }
26148}
26149
26150void andnL_rReg_rReg_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26151 cbuf.set_insts_mark();
26152 // Start at oper_input_base() and count operands
26153 unsigned idx0 = 2;
26154 unsigned idx1 = 2; // src2
26155 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src1
26156 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // minus_1
26157 {
26158 C2_MacroAssembler _masm(&cbuf);
26159
26160#line 9918 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
26161
26162 ___masm. andnq(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(2)->as_Register(ra_,this,idx2)/* src1 */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
26163
26164#line 26164 "ad_x86.cpp"
26165 }
26166}
26167
26168void andnL_rReg_rReg_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26169 cbuf.set_insts_mark();
26170 // Start at oper_input_base() and count operands
26171 unsigned idx0 = 1;
26172 unsigned idx1 = 1; // src1
26173 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1
26174 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // src2
26175 {
26176 C2_MacroAssembler _masm(&cbuf);
26177
26178#line 9931 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
26179
26180 ___masm. andnq(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */, opnd_array(3)->as_Register(ra_,this,idx3)/* src2 */);
26181
26182#line 26182 "ad_x86.cpp"
26183 }
26184}
26185
26186void andnL_rReg_rReg_rReg_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26187 cbuf.set_insts_mark();
26188 // Start at oper_input_base() and count operands
26189 unsigned idx0 = 1;
26190 unsigned idx1 = 1; // src2
26191 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src1
26192 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // minus_1
26193 {
26194 C2_MacroAssembler _masm(&cbuf);
26195
26196#line 9931 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
26197
26198 ___masm. andnq(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(2)->as_Register(ra_,this,idx2)/* src1 */, opnd_array(1)->as_Register(ra_,this,idx1)/* src2 */);
26199
26200#line 26200 "ad_x86.cpp"
26201 }
26202}
26203
26204void blsiL_rReg_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26205 cbuf.set_insts_mark();
26206 // Start at oper_input_base() and count operands
26207 unsigned idx0 = 1;
26208 unsigned idx1 = 1; // imm_zero
26209 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
26210 {
26211 C2_MacroAssembler _masm(&cbuf);
26212
26213#line 9944 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
26214
26215 ___masm. blsiq(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(2)->as_Register(ra_,this,idx2)/* src */);
26216
26217#line 26217 "ad_x86.cpp"
26218 }
26219}
26220
26221void blsiL_rReg_rReg_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26222 cbuf.set_insts_mark();
26223 // Start at oper_input_base() and count operands
26224 unsigned idx0 = 1;
26225 unsigned idx1 = 1; // src
26226 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // imm_zero
26227 {
26228 C2_MacroAssembler _masm(&cbuf);
26229
26230#line 9944 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
26231
26232 ___masm. blsiq(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
26233
26234#line 26234 "ad_x86.cpp"
26235 }
26236}
26237
26238void blsiL_rReg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26239 cbuf.set_insts_mark();
26240 // Start at oper_input_base() and count operands
26241 unsigned idx0 = 2;
26242 unsigned idx1 = 2; // imm_zero
26243 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
26244 {
26245 C2_MacroAssembler _masm(&cbuf);
26246
26247#line 9958 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
26248
26249 ___masm. blsiq(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
26250
26251#line 26251 "ad_x86.cpp"
26252 }
26253}
26254
26255void blsiL_rReg_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26256 cbuf.set_insts_mark();
26257 // Start at oper_input_base() and count operands
26258 unsigned idx0 = 2;
26259 unsigned idx1 = 2; // src
26260 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // imm_zero
26261 {
26262 C2_MacroAssembler _masm(&cbuf);
26263
26264#line 9958 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
26265
26266 ___masm. blsiq(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
26267
26268#line 26268 "ad_x86.cpp"
26269 }
26270}
26271
26272void blsmskL_rReg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26273 cbuf.set_insts_mark();
26274 // Start at oper_input_base() and count operands
26275 unsigned idx0 = 2;
26276 unsigned idx1 = 2; // src
26277 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1
26278 {
26279 C2_MacroAssembler _masm(&cbuf);
26280
26281#line 9973 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
26282
26283 ___masm. blsmskq(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
26284
26285#line 26285 "ad_x86.cpp"
26286 }
26287}
26288
26289void blsmskL_rReg_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26290 cbuf.set_insts_mark();
26291 // Start at oper_input_base() and count operands
26292 unsigned idx0 = 2;
26293 unsigned idx1 = 2; // src
26294 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1
26295 {
26296 C2_MacroAssembler _masm(&cbuf);
26297
26298#line 9973 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
26299
26300 ___masm. blsmskq(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
26301
26302#line 26302 "ad_x86.cpp"
26303 }
26304}
26305
26306void blsmskL_rReg_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26307 cbuf.set_insts_mark();
26308 // Start at oper_input_base() and count operands
26309 unsigned idx0 = 1;
26310 unsigned idx1 = 1; // src
26311 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1
26312 {
26313 C2_MacroAssembler _masm(&cbuf);
26314
26315#line 9987 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
26316
26317 ___masm. blsmskq(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
26318
26319#line 26319 "ad_x86.cpp"
26320 }
26321}
26322
26323void blsmskL_rReg_rReg_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26324 cbuf.set_insts_mark();
26325 // Start at oper_input_base() and count operands
26326 unsigned idx0 = 1;
26327 unsigned idx1 = 1; // src
26328 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1
26329 {
26330 C2_MacroAssembler _masm(&cbuf);
26331
26332#line 9987 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
26333
26334 ___masm. blsmskq(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
26335
26336#line 26336 "ad_x86.cpp"
26337 }
26338}
26339
26340void blsrL_rReg_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26341 cbuf.set_insts_mark();
26342 // Start at oper_input_base() and count operands
26343 unsigned idx0 = 1;
26344 unsigned idx1 = 1; // src
26345 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1
26346 {
26347 C2_MacroAssembler _masm(&cbuf);
26348
26349#line 10002 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
26350
26351 ___masm. blsrq(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
26352
26353#line 26353 "ad_x86.cpp"
26354 }
26355}
26356
26357void blsrL_rReg_rReg_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26358 cbuf.set_insts_mark();
26359 // Start at oper_input_base() and count operands
26360 unsigned idx0 = 1;
26361 unsigned idx1 = 1; // src
26362 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1
26363 {
26364 C2_MacroAssembler _masm(&cbuf);
26365
26366#line 10002 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
26367
26368 ___masm. blsrq(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
26369
26370#line 26370 "ad_x86.cpp"
26371 }
26372}
26373
26374void blsrL_rReg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26375 cbuf.set_insts_mark();
26376 // Start at oper_input_base() and count operands
26377 unsigned idx0 = 2;
26378 unsigned idx1 = 2; // src
26379 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1
26380 {
26381 C2_MacroAssembler _masm(&cbuf);
26382
26383#line 10018 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
26384
26385 ___masm. blsrq(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
26386
26387#line 26387 "ad_x86.cpp"
26388 }
26389}
26390
26391void blsrL_rReg_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26392 cbuf.set_insts_mark();
26393 // Start at oper_input_base() and count operands
26394 unsigned idx0 = 2;
26395 unsigned idx1 = 2; // src
26396 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // minus_1
26397 {
26398 C2_MacroAssembler _masm(&cbuf);
26399
26400#line 10018 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
26401
26402 ___masm. blsrq(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
26403
26404#line 26404 "ad_x86.cpp"
26405 }
26406}
26407
26408void orL_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26409 cbuf.set_insts_mark();
26410 // Start at oper_input_base() and count operands
26411 unsigned idx0 = 1;
26412 unsigned idx1 = 1; // dst
26413 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
26414 {
26415 C2_MacroAssembler _masm(&cbuf);
26416
26417#line 10033 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
26418
26419 ___masm. orq(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, opnd_array(2)->as_Register(ra_,this,idx2)/* src */);
26420
26421#line 26421 "ad_x86.cpp"
26422 }
26423}
26424
26425void orL_rReg_castP2XNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26426 cbuf.set_insts_mark();
26427 // Start at oper_input_base() and count operands
26428 unsigned idx0 = 1;
26429 unsigned idx1 = 1; // dst
26430 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
26431 {
26432 C2_MacroAssembler _masm(&cbuf);
26433
26434#line 10045 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
26435
26436 ___masm. orq(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, opnd_array(2)->as_Register(ra_,this,idx2)/* src */);
26437
26438#line 26438 "ad_x86.cpp"
26439 }
26440}
26441
26442void orL_rReg_castP2X_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26443 cbuf.set_insts_mark();
26444 // Start at oper_input_base() and count operands
26445 unsigned idx0 = 1;
26446 unsigned idx1 = 1; // src
26447 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
26448 {
26449 C2_MacroAssembler _masm(&cbuf);
26450
26451#line 10045 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
26452
26453 ___masm. orq(opnd_array(2)->as_Register(ra_,this,idx2)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
26454
26455#line 26455 "ad_x86.cpp"
26456 }
26457}
26458
26459void orL_rReg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26460 cbuf.set_insts_mark();
26461 // Start at oper_input_base() and count operands
26462 unsigned idx0 = 1;
26463 unsigned idx1 = 1; // dst
26464 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
26465 {
26466 C2_MacroAssembler _masm(&cbuf);
26467
26468#line 10059 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
26469
26470 ___masm. orq(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, opnd_array(2)->constantL());
26471
26472#line 26472 "ad_x86.cpp"
26473 }
26474}
26475
26476void orL_rReg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26477 cbuf.set_insts_mark();
26478 // Start at oper_input_base() and count operands
26479 unsigned idx0 = 2;
26480 unsigned idx1 = 2; // dst
26481 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
26482 {
26483 C2_MacroAssembler _masm(&cbuf);
26484
26485#line 10073 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
26486
26487 ___masm. orq(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
26488
26489#line 26489 "ad_x86.cpp"
26490 }
26491}
26492
26493void orL_rReg_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26494 cbuf.set_insts_mark();
26495 // Start at oper_input_base() and count operands
26496 unsigned idx0 = 2;
26497 unsigned idx1 = 2; // src
26498 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
26499 {
26500 C2_MacroAssembler _masm(&cbuf);
26501
26502#line 10073 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
26503
26504 ___masm. orq(opnd_array(2)->as_Register(ra_,this,idx2)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
26505
26506#line 26506 "ad_x86.cpp"
26507 }
26508}
26509
26510void orL_mem_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26511 cbuf.set_insts_mark();
26512 // Start at oper_input_base() and count operands
26513 unsigned idx0 = 2;
26514 unsigned idx1 = 2; // dst
26515 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
26516 {
26517 C2_MacroAssembler _masm(&cbuf);
26518
26519#line 10087 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
26520
26521 ___masm. orq(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_Register(ra_,this,idx2)/* src */);
26522
26523#line 26523 "ad_x86.cpp"
26524 }
26525}
26526
26527void orL_mem_rReg_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26528 cbuf.set_insts_mark();
26529 // Start at oper_input_base() and count operands
26530 unsigned idx0 = 2;
26531 unsigned idx1 = 2; // dst
26532 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
26533 {
26534 C2_MacroAssembler _masm(&cbuf);
26535
26536#line 10087 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
26537
26538 ___masm. orq(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_Register(ra_,this,idx2)/* src */);
26539
26540#line 26540 "ad_x86.cpp"
26541 }
26542}
26543
26544void orL_mem_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26545 cbuf.set_insts_mark();
26546 // Start at oper_input_base() and count operands
26547 unsigned idx0 = 2;
26548 unsigned idx1 = 2; // dst
26549 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
26550 {
26551 C2_MacroAssembler _masm(&cbuf);
26552
26553#line 10101 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
26554
26555 ___masm. orq(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->constantL());
26556
26557#line 26557 "ad_x86.cpp"
26558 }
26559}
26560
26561void btsL_mem_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26562 cbuf.set_insts_mark();
26563 // Start at oper_input_base() and count operands
26564 unsigned idx0 = 2;
26565 unsigned idx1 = 2; // dst
26566 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
26567 {
26568 C2_MacroAssembler _masm(&cbuf);
26569
26570#line 10118 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
26571
26572 ___masm. btsq(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), log2i_exact((julong)opnd_array(2)->constantL()));
26573
26574#line 26574 "ad_x86.cpp"
26575 }
26576}
26577
26578void xorL_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26579 cbuf.set_insts_mark();
26580 // Start at oper_input_base() and count operands
26581 unsigned idx0 = 1;
26582 unsigned idx1 = 1; // dst
26583 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
26584 {
26585 C2_MacroAssembler _masm(&cbuf);
26586
26587#line 10132 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
26588
26589 ___masm. xorq(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, opnd_array(2)->as_Register(ra_,this,idx2)/* src */);
26590
26591#line 26591 "ad_x86.cpp"
26592 }
26593}
26594
26595void xorL_rReg_im1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26596 cbuf.set_insts_mark();
26597 // Start at oper_input_base() and count operands
26598 unsigned idx0 = 1;
26599 unsigned idx1 = 1; // dst
26600 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // imm
26601 {
26602 C2_MacroAssembler _masm(&cbuf);
26603
26604#line 10143 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
26605
26606 ___masm. notq(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */);
26607
26608#line 26608 "ad_x86.cpp"
26609 }
26610}
26611
26612void xorL_rReg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26613 cbuf.set_insts_mark();
26614 // Start at oper_input_base() and count operands
26615 unsigned idx0 = 1;
26616 unsigned idx1 = 1; // dst
26617 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
26618 {
26619 C2_MacroAssembler _masm(&cbuf);
26620
26621#line 10156 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
26622
26623 ___masm. xorq(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, opnd_array(2)->constantL());
26624
26625#line 26625 "ad_x86.cpp"
26626 }
26627}
26628
26629void xorL_rReg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26630 cbuf.set_insts_mark();
26631 // Start at oper_input_base() and count operands
26632 unsigned idx0 = 2;
26633 unsigned idx1 = 2; // dst
26634 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
26635 {
26636 C2_MacroAssembler _masm(&cbuf);
26637
26638#line 10170 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
26639
26640 ___masm. xorq(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
26641
26642#line 26642 "ad_x86.cpp"
26643 }
26644}
26645
26646void xorL_rReg_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26647 cbuf.set_insts_mark();
26648 // Start at oper_input_base() and count operands
26649 unsigned idx0 = 2;
26650 unsigned idx1 = 2; // src
26651 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
26652 {
26653 C2_MacroAssembler _masm(&cbuf);
26654
26655#line 10170 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
26656
26657 ___masm. xorq(opnd_array(2)->as_Register(ra_,this,idx2)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
26658
26659#line 26659 "ad_x86.cpp"
26660 }
26661}
26662
26663void xorL_mem_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26664 cbuf.set_insts_mark();
26665 // Start at oper_input_base() and count operands
26666 unsigned idx0 = 2;
26667 unsigned idx1 = 2; // dst
26668 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
26669 {
26670 C2_MacroAssembler _masm(&cbuf);
26671
26672#line 10184 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
26673
26674 ___masm. xorq(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_Register(ra_,this,idx2)/* src */);
26675
26676#line 26676 "ad_x86.cpp"
26677 }
26678}
26679
26680void xorL_mem_rReg_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26681 cbuf.set_insts_mark();
26682 // Start at oper_input_base() and count operands
26683 unsigned idx0 = 2;
26684 unsigned idx1 = 2; // dst
26685 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
26686 {
26687 C2_MacroAssembler _masm(&cbuf);
26688
26689#line 10184 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
26690
26691 ___masm. xorq(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_Register(ra_,this,idx2)/* src */);
26692
26693#line 26693 "ad_x86.cpp"
26694 }
26695}
26696
26697void xorL_mem_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26698 cbuf.set_insts_mark();
26699 // Start at oper_input_base() and count operands
26700 unsigned idx0 = 2;
26701 unsigned idx1 = 2; // dst
26702 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
26703 {
26704 C2_MacroAssembler _masm(&cbuf);
26705
26706#line 10198 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
26707
26708 ___masm. xorq(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->constantL());
26709
26710#line 26710 "ad_x86.cpp"
26711 }
26712}
26713
26714void convI2BNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26715 cbuf.set_insts_mark();
26716 // Start at oper_input_base() and count operands
26717 unsigned idx0 = 1;
26718 unsigned idx1 = 1; // src
26719 {
26720 C2_MacroAssembler _masm(&cbuf);
26721
26722#line 10213 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
26723
26724 ___masm. testl(opnd_array(1)->as_Register(ra_,this,idx1)/* src */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
26725 ___masm. set_byte_if_not_zero(opnd_array(0)->as_Register(ra_,this)/* dst */);
26726 ___masm. movzbl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(0)->as_Register(ra_,this)/* dst */);
26727
26728#line 26728 "ad_x86.cpp"
26729 }
26730}
26731
26732void convP2BNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26733 cbuf.set_insts_mark();
26734 // Start at oper_input_base() and count operands
26735 unsigned idx0 = 1;
26736 unsigned idx1 = 1; // src
26737 {
26738 C2_MacroAssembler _masm(&cbuf);
26739
26740#line 10230 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
26741
26742 ___masm. testq(opnd_array(1)->as_Register(ra_,this,idx1)/* src */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
26743 ___masm. set_byte_if_not_zero(opnd_array(0)->as_Register(ra_,this)/* dst */);
26744 ___masm. movzbl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(0)->as_Register(ra_,this)/* dst */);
26745
26746#line 26746 "ad_x86.cpp"
26747 }
26748}
26749
26750void cmpLTMaskNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26751 cbuf.set_insts_mark();
26752 // Start at oper_input_base() and count operands
26753 unsigned idx0 = 1;
26754 unsigned idx1 = 1; // p
26755 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // q
26756 {
26757 C2_MacroAssembler _masm(&cbuf);
26758
26759#line 10248 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
26760
26761 ___masm. cmpl(opnd_array(1)->as_Register(ra_,this,idx1)/* p */, opnd_array(2)->as_Register(ra_,this,idx2)/* q */);
26762 ___masm. setl(opnd_array(0)->as_Register(ra_,this)/* dst */);
26763 ___masm. movzbl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(0)->as_Register(ra_,this)/* dst */);
26764 ___masm. negl(opnd_array(0)->as_Register(ra_,this)/* dst */);
26765
26766#line 26766 "ad_x86.cpp"
26767 }
26768}
26769
26770void cmpLTMask0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26771 cbuf.set_insts_mark();
26772 // Start at oper_input_base() and count operands
26773 unsigned idx0 = 1;
26774 unsigned idx1 = 1; // dst
26775 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
26776 {
26777 C2_MacroAssembler _masm(&cbuf);
26778
26779#line 10264 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
26780
26781 ___masm. sarl(opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, 31);
26782
26783#line 26783 "ad_x86.cpp"
26784 }
26785}
26786
26787void cadd_cmpLTMaskNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26788 cbuf.set_insts_mark();
26789 // Start at oper_input_base() and count operands
26790 unsigned idx0 = 1;
26791 unsigned idx1 = 1; // p
26792 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // q
26793 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // y
26794 {
26795 C2_MacroAssembler _masm(&cbuf);
26796
26797#line 10280 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
26798
26799 Register Rp = opnd_array(1)->as_Register(ra_,this,idx1)/* p */;
26800 Register Rq = opnd_array(2)->as_Register(ra_,this,idx2)/* q */;
26801 Register Ry = opnd_array(3)->as_Register(ra_,this,idx3)/* y */;
26802 Label done;
26803 ___masm. subl(Rp, Rq);
26804 ___masm. jccb(Assembler::greaterEqual, done)jccb_0(Assembler::greaterEqual, done, "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 10286);
26805 ___masm. addl(Rp, Ry);
26806 ___masm. bind(done);
26807
26808#line 26808 "ad_x86.cpp"
26809 }
26810}
26811
26812void cadd_cmpLTMask_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26813 cbuf.set_insts_mark();
26814 // Start at oper_input_base() and count operands
26815 unsigned idx0 = 1;
26816 unsigned idx1 = 1; // p
26817 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // q
26818 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // y
26819 {
26820 C2_MacroAssembler _masm(&cbuf);
26821
26822#line 10280 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
26823
26824 Register Rp = opnd_array(1)->as_Register(ra_,this,idx1)/* p */;
26825 Register Rq = opnd_array(2)->as_Register(ra_,this,idx2)/* q */;
26826 Register Ry = opnd_array(3)->as_Register(ra_,this,idx3)/* y */;
26827 Label done;
26828 ___masm. subl(Rp, Rq);
26829 ___masm. jccb(Assembler::greaterEqual, done)jccb_0(Assembler::greaterEqual, done, "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 10286);
26830 ___masm. addl(Rp, Ry);
26831 ___masm. bind(done);
26832
26833#line 26833 "ad_x86.cpp"
26834 }
26835}
26836
26837void cadd_cmpLTMask_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26838 cbuf.set_insts_mark();
26839 // Start at oper_input_base() and count operands
26840 unsigned idx0 = 1;
26841 unsigned idx1 = 1; // y
26842 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // p
26843 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // q
26844 {
26845 C2_MacroAssembler _masm(&cbuf);
26846
26847#line 10280 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
26848
26849 Register Rp = opnd_array(2)->as_Register(ra_,this,idx2)/* p */;
26850 Register Rq = opnd_array(3)->as_Register(ra_,this,idx3)/* q */;
26851 Register Ry = opnd_array(1)->as_Register(ra_,this,idx1)/* y */;
26852 Label done;
26853 ___masm. subl(Rp, Rq);
26854 ___masm. jccb(Assembler::greaterEqual, done)jccb_0(Assembler::greaterEqual, done, "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 10286);
26855 ___masm. addl(Rp, Ry);
26856 ___masm. bind(done);
26857
26858#line 26858 "ad_x86.cpp"
26859 }
26860}
26861
26862void cadd_cmpLTMask_2Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26863 cbuf.set_insts_mark();
26864 // Start at oper_input_base() and count operands
26865 unsigned idx0 = 1;
26866 unsigned idx1 = 1; // p
26867 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // q
26868 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // y
26869 {
26870 C2_MacroAssembler _masm(&cbuf);
26871
26872#line 10280 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
26873
26874 Register Rp = opnd_array(1)->as_Register(ra_,this,idx1)/* p */;
26875 Register Rq = opnd_array(2)->as_Register(ra_,this,idx2)/* q */;
26876 Register Ry = opnd_array(3)->as_Register(ra_,this,idx3)/* y */;
26877 Label done;
26878 ___masm. subl(Rp, Rq);
26879 ___masm. jccb(Assembler::greaterEqual, done)jccb_0(Assembler::greaterEqual, done, "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 10286);
26880 ___masm. addl(Rp, Ry);
26881 ___masm. bind(done);
26882
26883#line 26883 "ad_x86.cpp"
26884 }
26885}
26886
26887void and_cmpLTMaskNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26888 cbuf.set_insts_mark();
26889 // Start at oper_input_base() and count operands
26890 unsigned idx0 = 1;
26891 unsigned idx1 = 1; // p
26892 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // q
26893 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // y
26894 {
26895 C2_MacroAssembler _masm(&cbuf);
26896
26897#line 10305 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
26898
26899 Register Rp = opnd_array(1)->as_Register(ra_,this,idx1)/* p */;
26900 Register Rq = opnd_array(2)->as_Register(ra_,this,idx2)/* q */;
26901 Register Ry = opnd_array(3)->as_Register(ra_,this,idx3)/* y */;
26902 Label done;
26903 ___masm. cmpl(Rp, Rq);
26904 ___masm. jccb(Assembler::less, done)jccb_0(Assembler::less, done, "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 10311);
26905 ___masm. xorl(Ry, Ry);
26906 ___masm. bind(done);
26907
26908#line 26908 "ad_x86.cpp"
26909 }
26910}
26911
26912void and_cmpLTMask_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26913 cbuf.set_insts_mark();
26914 // Start at oper_input_base() and count operands
26915 unsigned idx0 = 1;
26916 unsigned idx1 = 1; // y
26917 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // p
26918 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // q
26919 {
26920 C2_MacroAssembler _masm(&cbuf);
26921
26922#line 10305 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
26923
26924 Register Rp = opnd_array(2)->as_Register(ra_,this,idx2)/* p */;
26925 Register Rq = opnd_array(3)->as_Register(ra_,this,idx3)/* q */;
26926 Register Ry = opnd_array(1)->as_Register(ra_,this,idx1)/* y */;
26927 Label done;
26928 ___masm. cmpl(Rp, Rq);
26929 ___masm. jccb(Assembler::less, done)jccb_0(Assembler::less, done, "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 10311);
26930 ___masm. xorl(Ry, Ry);
26931 ___masm. bind(done);
26932
26933#line 26933 "ad_x86.cpp"
26934 }
26935}
26936
26937void cmpF_cc_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26938 cbuf.set_insts_mark();
26939 // Start at oper_input_base() and count operands
26940 unsigned idx0 = 1;
26941 unsigned idx1 = 1; // src1
26942 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
26943 {
26944 C2_MacroAssembler _masm(&cbuf);
26945
26946#line 10332 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
26947
26948 ___masm. ucomiss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
26949 emit_cmpfp_fixup(_masm);
26950
26951#line 26951 "ad_x86.cpp"
26952 }
26953}
26954
26955void cmpF_cc_reg_CFNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26956 cbuf.set_insts_mark();
26957 // Start at oper_input_base() and count operands
26958 unsigned idx0 = 1;
26959 unsigned idx1 = 1; // src1
26960 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
26961 {
26962 C2_MacroAssembler _masm(&cbuf);
26963
26964#line 10344 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
26965
26966 ___masm. ucomiss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
26967
26968#line 26968 "ad_x86.cpp"
26969 }
26970}
26971
26972void cmpF_cc_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26973 cbuf.set_insts_mark();
26974 // Start at oper_input_base() and count operands
26975 unsigned idx0 = 2;
26976 unsigned idx1 = 2; // src1
26977 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
26978 {
26979 C2_MacroAssembler _masm(&cbuf);
26980
26981#line 10361 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
26982
26983 ___masm. ucomiss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
26984 emit_cmpfp_fixup(_masm);
26985
26986#line 26986 "ad_x86.cpp"
26987 }
26988}
26989
26990void cmpF_cc_memCFNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
26991 cbuf.set_insts_mark();
26992 // Start at oper_input_base() and count operands
26993 unsigned idx0 = 2;
26994 unsigned idx1 = 2; // src1
26995 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
26996 {
26997 C2_MacroAssembler _masm(&cbuf);
26998
26999#line 10373 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
27000
27001 ___masm. ucomiss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
27002
27003#line 27003 "ad_x86.cpp"
27004 }
27005}
27006
27007void cmpF_cc_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
27008 cbuf.set_insts_mark();
27009 // Start at oper_input_base() and count operands
27010 unsigned idx0 = 1;
27011 unsigned idx1 = 1; // src
27012 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
27013 {
27014 C2_MacroAssembler _masm(&cbuf);
27015
27016#line 10389 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
27017
27018 ___masm. ucomiss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, InternalAddress(___masm. code()->consts()->start() + constant_offset()));
27019 emit_cmpfp_fixup(_masm);
27020
27021#line 27021 "ad_x86.cpp"
27022 }
27023}
27024
27025void cmpF_cc_immNode::eval_constant(Compile* C) {
27026 {
27027
27028#line 10390 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
27029 _constant = C->output()->constant_table().add(this, opnd_array(2));
27030#line 27030 "ad_x86.cpp"
27031 }
27032}
27033void cmpF_cc_immCFNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
27034 cbuf.set_insts_mark();
27035 // Start at oper_input_base() and count operands
27036 unsigned idx0 = 1;
27037 unsigned idx1 = 1; // src
27038 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
27039 {
27040 C2_MacroAssembler _masm(&cbuf);
27041
27042#line 10400 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
27043
27044 ___masm. ucomiss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, InternalAddress(___masm. code()->consts()->start() + constant_offset()));
27045
27046#line 27046 "ad_x86.cpp"
27047 }
27048}
27049
27050void cmpF_cc_immCFNode::eval_constant(Compile* C) {
27051 {
27052
27053#line 10401 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
27054 _constant = C->output()->constant_table().add(this, opnd_array(2));
27055#line 27055 "ad_x86.cpp"
27056 }
27057}
27058void cmpD_cc_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
27059 cbuf.set_insts_mark();
27060 // Start at oper_input_base() and count operands
27061 unsigned idx0 = 1;
27062 unsigned idx1 = 1; // src1
27063 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
27064 {
27065 C2_MacroAssembler _masm(&cbuf);
27066
27067#line 10417 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
27068
27069 ___masm. ucomisd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
27070 emit_cmpfp_fixup(_masm);
27071
27072#line 27072 "ad_x86.cpp"
27073 }
27074}
27075
27076void cmpD_cc_reg_CFNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
27077 cbuf.set_insts_mark();
27078 // Start at oper_input_base() and count operands
27079 unsigned idx0 = 1;
27080 unsigned idx1 = 1; // src1
27081 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
27082 {
27083 C2_MacroAssembler _masm(&cbuf);
27084
27085#line 10429 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
27086
27087 ___masm. ucomisd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
27088
27089#line 27089 "ad_x86.cpp"
27090 }
27091}
27092
27093void cmpD_cc_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
27094 cbuf.set_insts_mark();
27095 // Start at oper_input_base() and count operands
27096 unsigned idx0 = 2;
27097 unsigned idx1 = 2; // src1
27098 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
27099 {
27100 C2_MacroAssembler _masm(&cbuf);
27101
27102#line 10446 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
27103
27104 ___masm. ucomisd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
27105 emit_cmpfp_fixup(_masm);
27106
27107#line 27107 "ad_x86.cpp"
27108 }
27109}
27110
27111void cmpD_cc_memCFNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
27112 cbuf.set_insts_mark();
27113 // Start at oper_input_base() and count operands
27114 unsigned idx0 = 2;
27115 unsigned idx1 = 2; // src1
27116 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
27117 {
27118 C2_MacroAssembler _masm(&cbuf);
27119
27120#line 10458 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
27121
27122 ___masm. ucomisd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
27123
27124#line 27124 "ad_x86.cpp"
27125 }
27126}
27127
27128void cmpD_cc_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
27129 cbuf.set_insts_mark();
27130 // Start at oper_input_base() and count operands
27131 unsigned idx0 = 1;
27132 unsigned idx1 = 1; // src
27133 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
Value stored to 'idx2' during its initialization is never read
27134 {
27135 C2_MacroAssembler _masm(&cbuf);
27136
27137#line 10474 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
27138
27139 ___masm. ucomisd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, InternalAddress(___masm. code()->consts()->start() + constant_offset()));
27140 emit_cmpfp_fixup(_masm);
27141
27142#line 27142 "ad_x86.cpp"
27143 }
27144}
27145
27146void cmpD_cc_immNode::eval_constant(Compile* C) {
27147 {
27148
27149#line 10475 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
27150 _constant = C->output()->constant_table().add(this, opnd_array(2));
27151#line 27151 "ad_x86.cpp"
27152 }
27153}
27154void cmpD_cc_immCFNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
27155 cbuf.set_insts_mark();
27156 // Start at oper_input_base() and count operands
27157 unsigned idx0 = 1;
27158 unsigned idx1 = 1; // src
27159 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
27160 {
27161 C2_MacroAssembler _masm(&cbuf);
27162
27163#line 10485 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
27164
27165 ___masm. ucomisd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, InternalAddress(___masm. code()->consts()->start() + constant_offset()));
27166
27167#line 27167 "ad_x86.cpp"
27168 }
27169}
27170
27171void cmpD_cc_immCFNode::eval_constant(Compile* C) {
27172 {
27173
27174#line 10486 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
27175 _constant = C->output()->constant_table().add(this, opnd_array(2));
27176#line 27176 "ad_x86.cpp"
27177 }
27178}
27179void cmpF_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
27180 cbuf.set_insts_mark();
27181 // Start at oper_input_base() and count operands
27182 unsigned idx0 = 1;
27183 unsigned idx1 = 1; // src1
27184 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
27185 {
27186 C2_MacroAssembler _masm(&cbuf);
27187
27188#line 10505 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
27189
27190 ___masm. ucomiss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
27191 emit_cmpfp3(_masm, opnd_array(0)->as_Register(ra_,this)/* dst */);
27192
27193#line 27193 "ad_x86.cpp"
27194 }
27195}
27196
27197void cmpF_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
27198 cbuf.set_insts_mark();
27199 // Start at oper_input_base() and count operands
27200 unsigned idx0 = 2;
27201 unsigned idx1 = 2; // src1
27202 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
27203 {
27204 C2_MacroAssembler _masm(&cbuf);
27205
27206#line 10526 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
27207
27208 ___masm. ucomiss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
27209 emit_cmpfp3(_masm, opnd_array(0)->as_Register(ra_,this)/* dst */);
27210
27211#line 27211 "ad_x86.cpp"
27212 }
27213}
27214
27215void cmpF_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
27216 cbuf.set_insts_mark();
27217 // Start at oper_input_base() and count operands
27218 unsigned idx0 = 1;
27219 unsigned idx1 = 1; // src
27220 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
27221 {
27222 C2_MacroAssembler _masm(&cbuf);
27223
27224#line 10546 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
27225
27226 ___masm. ucomiss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, InternalAddress(___masm. code()->consts()->start() + constant_offset()));
27227 emit_cmpfp3(_masm, opnd_array(0)->as_Register(ra_,this)/* dst */);
27228
27229#line 27229 "ad_x86.cpp"
27230 }
27231}
27232
27233void cmpF_immNode::eval_constant(Compile* C) {
27234 {
27235
27236#line 10547 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
27237 _constant = C->output()->constant_table().add(this, opnd_array(2));
27238#line 27238 "ad_x86.cpp"
27239 }
27240}
27241void cmpD_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
27242 cbuf.set_insts_mark();
27243 // Start at oper_input_base() and count operands
27244 unsigned idx0 = 1;
27245 unsigned idx1 = 1; // src1
27246 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
27247 {
27248 C2_MacroAssembler _masm(&cbuf);
27249
27250#line 10567 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
27251
27252 ___masm. ucomisd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
27253 emit_cmpfp3(_masm, opnd_array(0)->as_Register(ra_,this)/* dst */);
27254
27255#line 27255 "ad_x86.cpp"
27256 }
27257}
27258
27259void cmpD_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
27260 cbuf.set_insts_mark();
27261 // Start at oper_input_base() and count operands
27262 unsigned idx0 = 2;
27263 unsigned idx1 = 2; // src1
27264 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
27265 {
27266 C2_MacroAssembler _masm(&cbuf);
27267
27268#line 10588 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
27269
27270 ___masm. ucomisd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
27271 emit_cmpfp3(_masm, opnd_array(0)->as_Register(ra_,this)/* dst */);
27272
27273#line 27273 "ad_x86.cpp"
27274 }
27275}
27276
27277void cmpD_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
27278 cbuf.set_insts_mark();
27279 // Start at oper_input_base() and count operands
27280 unsigned idx0 = 1;
27281 unsigned idx1 = 1; // src
27282 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
27283 {
27284 C2_MacroAssembler _masm(&cbuf);
27285
27286#line 10608 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
27287
27288 ___masm. ucomisd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, InternalAddress(___masm. code()->consts()->start() + constant_offset()));
27289 emit_cmpfp3(_masm, opnd_array(0)->as_Register(ra_,this)/* dst */);
27290
27291#line 27291 "ad_x86.cpp"
27292 }
27293}
27294
27295void cmpD_immNode::eval_constant(Compile* C) {
27296 {
27297
27298#line 10609 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
27299 _constant = C->output()->constant_table().add(this, opnd_array(2));
27300#line 27300 "ad_x86.cpp"
27301 }
27302}
27303void convF2D_reg_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
27304 cbuf.set_insts_mark();
27305 // Start at oper_input_base() and count operands
27306 unsigned idx0 = 1;
27307 unsigned idx1 = 1; // src
27308 {
27309 C2_MacroAssembler _masm(&cbuf);
27310
27311#line 10622 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
27312
27313 ___masm. cvtss2sd (opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
27314
27315#line 27315 "ad_x86.cpp"
27316 }
27317}
27318
27319void convF2D_reg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
27320 cbuf.set_insts_mark();
27321 // Start at oper_input_base() and count operands
27322 unsigned idx0 = 2;
27323 unsigned idx1 = 2; // src
27324 {
27325 C2_MacroAssembler _masm(&cbuf);
27326
27327#line 10633 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
27328
27329 ___masm. cvtss2sd (opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
27330
27331#line 27331 "ad_x86.cpp"
27332 }
27333}
27334
27335void convD2F_reg_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
27336 cbuf.set_insts_mark();
27337 // Start at oper_input_base() and count operands
27338 unsigned idx0 = 1;
27339 unsigned idx1 = 1; // src
27340 {
27341 C2_MacroAssembler _masm(&cbuf);
27342
27343#line 10644 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
27344
27345 ___masm. cvtsd2ss (opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
27346
27347#line 27347 "ad_x86.cpp"
27348 }
27349}
27350
27351void convD2F_reg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
27352 cbuf.set_insts_mark();
27353 // Start at oper_input_base() and count operands
27354 unsigned idx0 = 2;
27355 unsigned idx1 = 2; // src
27356 {
27357 C2_MacroAssembler _masm(&cbuf);
27358
27359#line 10655 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
27360
27361 ___masm. cvtsd2ss (opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
27362
27363#line 27363 "ad_x86.cpp"
27364 }
27365}
27366
27367void convF2I_reg_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
27368 cbuf.set_insts_mark();
27369 // Start at oper_input_base() and count operands
27370 unsigned idx0 = 1;
27371 unsigned idx1 = 1; // src
27372 {
27373 C2_MacroAssembler _masm(&cbuf);
27374
27375#line 10667 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
27376
27377 ___masm. convert_f2i(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
27378
27379#line 27379 "ad_x86.cpp"
27380 }
27381}
27382
27383void convF2L_reg_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
27384 cbuf.set_insts_mark();
27385 // Start at oper_input_base() and count operands
27386 unsigned idx0 = 1;
27387 unsigned idx1 = 1; // src
27388 {
27389 C2_MacroAssembler _masm(&cbuf);
27390
27391#line 10678 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
27392
27393 ___masm. convert_f2l(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
27394
27395#line 27395 "ad_x86.cpp"
27396 }
27397}
27398
27399void convD2I_reg_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
27400 cbuf.set_insts_mark();
27401 // Start at oper_input_base() and count operands
27402 unsigned idx0 = 1;
27403 unsigned idx1 = 1; // src
27404 {
27405 C2_MacroAssembler _masm(&cbuf);
27406
27407#line 10689 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
27408
27409 ___masm. convert_d2i(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
27410
27411#line 27411 "ad_x86.cpp"
27412 }
27413}
27414
27415void convD2L_reg_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
27416 cbuf.set_insts_mark();
27417 // Start at oper_input_base() and count operands
27418 unsigned idx0 = 1;
27419 unsigned idx1 = 1; // src
27420 {
27421 C2_MacroAssembler _masm(&cbuf);
27422
27423#line 10700 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
27424
27425 ___masm. convert_d2l(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
27426
27427#line 27427 "ad_x86.cpp"
27428 }
27429}
27430
27431void convI2F_reg_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
27432 cbuf.set_insts_mark();
27433 // Start at oper_input_base() and count operands
27434 unsigned idx0 = 1;
27435 unsigned idx1 = 1; // src
27436 {
27437 C2_MacroAssembler _masm(&cbuf);
27438
27439#line 10712 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
27440
27441 ___masm. cvtsi2ssl (opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
27442
27443#line 27443 "ad_x86.cpp"
27444 }
27445}
27446
27447void convI2F_reg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
27448 cbuf.set_insts_mark();
27449 // Start at oper_input_base() and count operands
27450 unsigned idx0 = 2;
27451 unsigned idx1 = 2; // src
27452 {
27453 C2_MacroAssembler _masm(&cbuf);
27454
27455#line 10723 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
27456
27457 ___masm. cvtsi2ssl (opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
27458
27459#line 27459 "ad_x86.cpp"
27460 }
27461}
27462
27463void convI2D_reg_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
27464 cbuf.set_insts_mark();
27465 // Start at oper_input_base() and count operands
27466 unsigned idx0 = 1;
27467 unsigned idx1 = 1; // src
27468 {
27469 C2_MacroAssembler _masm(&cbuf);
27470
27471#line 10735 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
27472
27473 ___masm. cvtsi2sdl (opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
27474
27475#line 27475 "ad_x86.cpp"
27476 }
27477}
27478
27479void convI2D_reg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
27480 cbuf.set_insts_mark();
27481 // Start at oper_input_base() and count operands
27482 unsigned idx0 = 2;
27483 unsigned idx1 = 2; // src
27484 {
27485 C2_MacroAssembler _masm(&cbuf);
27486
27487#line 10746 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
27488
27489 ___masm. cvtsi2sdl (opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
27490
27491#line 27491 "ad_x86.cpp"
27492 }
27493}
27494
27495void convXI2F_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
27496 cbuf.set_insts_mark();
27497 // Start at oper_input_base() and count operands
27498 unsigned idx0 = 1;
27499 unsigned idx1 = 1; // src
27500 {
27501 C2_MacroAssembler _masm(&cbuf);
27502
27503#line 10759 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
27504
27505 ___masm. movdl(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
27506 ___masm. cvtdq2ps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
27507
27508#line 27508 "ad_x86.cpp"
27509 }
27510}
27511
27512void convXI2D_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
27513 cbuf.set_insts_mark();
27514 // Start at oper_input_base() and count operands
27515 unsigned idx0 = 1;
27516 unsigned idx1 = 1; // src
27517 {
27518 C2_MacroAssembler _masm(&cbuf);
27519
27520#line 10773 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
27521
27522 ___masm. movdl(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
27523 ___masm. cvtdq2pd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
27524
27525#line 27525 "ad_x86.cpp"
27526 }
27527}
27528
27529void convL2F_reg_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
27530 cbuf.set_insts_mark();
27531 // Start at oper_input_base() and count operands
27532 unsigned idx0 = 1;
27533 unsigned idx1 = 1; // src
27534 {
27535 C2_MacroAssembler _masm(&cbuf);
27536
27537#line 10785 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
27538
27539 ___masm. cvtsi2ssq (opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
27540
27541#line 27541 "ad_x86.cpp"
27542 }
27543}
27544
27545void convL2F_reg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
27546 cbuf.set_insts_mark();
27547 // Start at oper_input_base() and count operands
27548 unsigned idx0 = 2;
27549 unsigned idx1 = 2; // src
27550 {
27551 C2_MacroAssembler _masm(&cbuf);
27552
27553#line 10796 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
27554
27555 ___masm. cvtsi2ssq (opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
27556
27557#line 27557 "ad_x86.cpp"
27558 }
27559}
27560
27561void convL2D_reg_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
27562 cbuf.set_insts_mark();
27563 // Start at oper_input_base() and count operands
27564 unsigned idx0 = 1;
27565 unsigned idx1 = 1; // src
27566 {
27567 C2_MacroAssembler _masm(&cbuf);
27568
27569#line 10807 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
27570
27571 ___masm. cvtsi2sdq (opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
27572
27573#line 27573 "ad_x86.cpp"
27574 }
27575}
27576
27577void convL2D_reg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
27578 cbuf.set_insts_mark();
27579 // Start at oper_input_base() and count operands
27580 unsigned idx0 = 2;
27581 unsigned idx1 = 2; // src
27582 {
27583 C2_MacroAssembler _masm(&cbuf);
27584
27585#line 10818 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
27586
27587 ___masm. cvtsi2sdq (opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
27588
27589#line 27589 "ad_x86.cpp"
27590 }
27591}
27592
27593void convI2L_reg_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
27594 cbuf.set_insts_mark();
27595 // Start at oper_input_base() and count operands
27596 unsigned idx0 = 1;
27597 unsigned idx1 = 1; // src
27598 {
27599 C2_MacroAssembler _masm(&cbuf);
27600
27601#line 10830 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
27602
27603 ___masm. movslq(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
27604
27605#line 27605 "ad_x86.cpp"
27606 }
27607}
27608
27609void convI2L_reg_reg_zexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
27610 cbuf.set_insts_mark();
27611 // Start at oper_input_base() and count operands
27612 unsigned idx0 = 1;
27613 unsigned idx1 = 1; // src
27614 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask
27615 {
27616 C2_MacroAssembler _masm(&cbuf);
27617
27618#line 10859 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
27619
27620 if (opnd_array(0)->reg(ra_,this)/* dst */!= opnd_array(1)->reg(ra_,this,idx1)/* src */) {
27621 ___masm. movl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
27622 }
27623
27624#line 27624 "ad_x86.cpp"
27625 }
27626}
27627
27628void convI2L_reg_mem_zexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
27629 cbuf.set_insts_mark();
27630 // Start at oper_input_base() and count operands
27631 unsigned idx0 = 2;
27632 unsigned idx1 = 2; // src
27633 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask
27634 {
27635 C2_MacroAssembler _masm(&cbuf);
27636
27637#line 10873 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
27638
27639 ___masm. movl(opnd_array(0)->as_Register(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
27640
27641#line 27641 "ad_x86.cpp"
27642 }
27643}
27644
27645void zerox_long_reg_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
27646 cbuf.set_insts_mark();
27647 // Start at oper_input_base() and count operands
27648 unsigned idx0 = 1;
27649 unsigned idx1 = 1; // src
27650 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask
27651 {
27652 C2_MacroAssembler _masm(&cbuf);
27653
27654#line 10884 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
27655
27656 ___masm. movl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
27657
27658#line 27658 "ad_x86.cpp"
27659 }
27660}
27661
27662void convL2I_reg_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
27663 cbuf.set_insts_mark();
27664 // Start at oper_input_base() and count operands
27665 unsigned idx0 = 1;
27666 unsigned idx1 = 1; // src
27667 {
27668 C2_MacroAssembler _masm(&cbuf);
27669
27670#line 10895 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
27671
27672 ___masm. movl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
27673
27674#line 27674 "ad_x86.cpp"
27675 }
27676}
27677
27678void MoveF2I_stack_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
27679 cbuf.set_insts_mark();
27680 // Start at oper_input_base() and count operands
27681 unsigned idx0 = 1;
27682 unsigned idx1 = 1; // src
27683 {
27684 C2_MacroAssembler _masm(&cbuf);
27685
27686#line 10908 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
27687
27688 ___masm. movl(opnd_array(0)->as_Register(ra_,this)/* dst */, Address(rsp, opnd_array(1)->disp(ra_,this,idx1)));
27689
27690#line 27690 "ad_x86.cpp"
27691 }
27692}
27693
27694void MoveI2F_stack_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
27695 cbuf.set_insts_mark();
27696 // Start at oper_input_base() and count operands
27697 unsigned idx0 = 1;
27698 unsigned idx1 = 1; // src
27699 {
27700 C2_MacroAssembler _masm(&cbuf);
27701
27702#line 10920 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
27703
27704 ___masm. movflt(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address(rsp, opnd_array(1)->disp(ra_,this,idx1)));
27705
27706#line 27706 "ad_x86.cpp"
27707 }
27708}
27709
27710void MoveD2L_stack_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
27711 cbuf.set_insts_mark();
27712 // Start at oper_input_base() and count operands
27713 unsigned idx0 = 1;
27714 unsigned idx1 = 1; // src
27715 {
27716 C2_MacroAssembler _masm(&cbuf);
27717
27718#line 10932 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
27719
27720 ___masm. movq(opnd_array(0)->as_Register(ra_,this)/* dst */, Address(rsp, opnd_array(1)->disp(ra_,this,idx1)));
27721
27722#line 27722 "ad_x86.cpp"
27723 }
27724}
27725
27726void MoveL2D_stack_reg_partialNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
27727 cbuf.set_insts_mark();
27728 // Start at oper_input_base() and count operands
27729 unsigned idx0 = 1;
27730 unsigned idx1 = 1; // src
27731 {
27732 C2_MacroAssembler _masm(&cbuf);
27733
27734#line 10945 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
27735
27736 ___masm. movdbl(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address(rsp, opnd_array(1)->disp(ra_,this,idx1)));
27737
27738#line 27738 "ad_x86.cpp"
27739 }
27740}
27741
27742void MoveL2D_stack_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
27743 cbuf.set_insts_mark();
27744 // Start at oper_input_base() and count operands
27745 unsigned idx0 = 1;
27746 unsigned idx1 = 1; // src
27747 {
27748 C2_MacroAssembler _masm(&cbuf);
27749
27750#line 10958 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
27751
27752 ___masm. movdbl(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address(rsp, opnd_array(1)->disp(ra_,this,idx1)));
27753
27754#line 27754 "ad_x86.cpp"
27755 }
27756}
27757
27758void MoveF2I_reg_stackNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
27759 cbuf.set_insts_mark();
27760 // Start at oper_input_base() and count operands
27761 unsigned idx0 = 1;
27762 unsigned idx1 = 1; // src
27763 {
27764 C2_MacroAssembler _masm(&cbuf);
27765
27766#line 10971 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
27767
27768 ___masm. movflt(Address(rsp, opnd_array(0)->disp(ra_,this,0)), opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
27769
27770#line 27770 "ad_x86.cpp"
27771 }
27772}
27773
27774void MoveI2F_reg_stackNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
27775 cbuf.set_insts_mark();
27776 // Start at oper_input_base() and count operands
27777 unsigned idx0 = 1;
27778 unsigned idx1 = 1; // src
27779 {
27780 C2_MacroAssembler _masm(&cbuf);
27781
27782#line 10983 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
27783
27784 ___masm. movl(Address(rsp, opnd_array(0)->disp(ra_,this,0)), opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
27785
27786#line 27786 "ad_x86.cpp"
27787 }
27788}
27789
27790void MoveD2L_reg_stackNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
27791 cbuf.set_insts_mark();
27792 // Start at oper_input_base() and count operands
27793 unsigned idx0 = 1;
27794 unsigned idx1 = 1; // src
27795 {
27796 C2_MacroAssembler _masm(&cbuf);
27797
27798#line 10995 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
27799
27800 ___masm. movdbl(Address(rsp, opnd_array(0)->disp(ra_,this,0)), opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
27801
27802#line 27802 "ad_x86.cpp"
27803 }
27804}
27805
27806void MoveL2D_reg_stackNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
27807 cbuf.set_insts_mark();
27808 // Start at oper_input_base() and count operands
27809 unsigned idx0 = 1;
27810 unsigned idx1 = 1; // src
27811 {
27812 C2_MacroAssembler _masm(&cbuf);
27813
27814#line 11007 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
27815
27816 ___masm. movq(Address(rsp, opnd_array(0)->disp(ra_,this,0)), opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
27817
27818#line 27818 "ad_x86.cpp"
27819 }
27820}
27821
27822void MoveF2I_reg_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
27823 cbuf.set_insts_mark();
27824 // Start at oper_input_base() and count operands
27825 unsigned idx0 = 1;
27826 unsigned idx1 = 1; // src
27827 {
27828 C2_MacroAssembler _masm(&cbuf);
27829
27830#line 11018 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
27831
27832 ___masm. movdl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
27833
27834#line 27834 "ad_x86.cpp"
27835 }
27836}
27837
27838void MoveD2L_reg_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
27839 cbuf.set_insts_mark();
27840 // Start at oper_input_base() and count operands
27841 unsigned idx0 = 1;
27842 unsigned idx1 = 1; // src
27843 {
27844 C2_MacroAssembler _masm(&cbuf);
27845
27846#line 11029 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
27847
27848 ___masm. movdq(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
27849
27850#line 27850 "ad_x86.cpp"
27851 }
27852}
27853
27854void MoveI2F_reg_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
27855 cbuf.set_insts_mark();
27856 // Start at oper_input_base() and count operands
27857 unsigned idx0 = 1;
27858 unsigned idx1 = 1; // src
27859 {
27860 C2_MacroAssembler _masm(&cbuf);
27861
27862#line 11040 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
27863
27864 ___masm. movdl(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
27865
27866#line 27866 "ad_x86.cpp"
27867 }
27868}
27869
27870void MoveL2D_reg_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
27871 cbuf.set_insts_mark();
27872 // Start at oper_input_base() and count operands
27873 unsigned idx0 = 1;
27874 unsigned idx1 = 1; // src
27875 {
27876 C2_MacroAssembler _masm(&cbuf);
27877
27878#line 11051 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
27879
27880 ___masm. movdq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
27881
27882#line 27882 "ad_x86.cpp"
27883 }
27884}
27885
27886void rep_stosNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
27887 cbuf.set_insts_mark();
27888 // Start at oper_input_base() and count operands
27889 unsigned idx0 = 2;
27890 unsigned idx1 = 2; // cnt
27891 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // base
27892 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
27893 {
27894 C2_MacroAssembler _masm(&cbuf);
27895
27896#line 11111 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
27897
27898 ___masm. clear_mem(opnd_array(2)->as_Register(ra_,this,idx2)/* base */, opnd_array(1)->as_Register(ra_,this,idx1)/* cnt */, as_Register(RAX_enc),
27899 opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, false, knoreg);
27900
27901#line 27901 "ad_x86.cpp"
27902 }
27903}
27904
27905void rep_stos_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
27906 cbuf.set_insts_mark();
27907 // Start at oper_input_base() and count operands
27908 unsigned idx0 = 2;
27909 unsigned idx1 = 2; // cnt
27910 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // base
27911 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
27912 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // ktmp
27913 {
27914 C2_MacroAssembler _masm(&cbuf);
27915
27916#line 11172 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
27917
27918 ___masm. clear_mem(opnd_array(2)->as_Register(ra_,this,idx2)/* base */, opnd_array(1)->as_Register(ra_,this,idx1)/* cnt */, as_Register(RAX_enc),
27919 opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, false, opnd_array(4)->as_KRegister(ra_,this,idx4)/* ktmp */);
27920
27921#line 27921 "ad_x86.cpp"
27922 }
27923}
27924
27925void rep_stos_largeNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
27926 cbuf.set_insts_mark();
27927 // Start at oper_input_base() and count operands
27928 unsigned idx0 = 2;
27929 unsigned idx1 = 2; // cnt
27930 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // base
27931 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
27932 {
27933 C2_MacroAssembler _masm(&cbuf);
27934
27935#line 11223 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
27936
27937 ___masm. clear_mem(opnd_array(2)->as_Register(ra_,this,idx2)/* base */, opnd_array(1)->as_Register(ra_,this,idx1)/* cnt */, as_Register(RAX_enc),
27938 opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, true, knoreg);
27939
27940#line 27940 "ad_x86.cpp"
27941 }
27942}
27943
27944void rep_stos_large_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
27945 cbuf.set_insts_mark();
27946 // Start at oper_input_base() and count operands
27947 unsigned idx0 = 2;
27948 unsigned idx1 = 2; // cnt
27949 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // base
27950 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
27951 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // ktmp
27952 {
27953 C2_MacroAssembler _masm(&cbuf);
27954
27955#line 11274 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
27956
27957 ___masm. clear_mem(opnd_array(2)->as_Register(ra_,this,idx2)/* base */, opnd_array(1)->as_Register(ra_,this,idx1)/* cnt */, as_Register(RAX_enc),
27958 opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, true, opnd_array(4)->as_KRegister(ra_,this,idx4)/* ktmp */);
27959
27960#line 27960 "ad_x86.cpp"
27961 }
27962}
27963
27964void rep_stos_imNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
27965 cbuf.set_insts_mark();
27966 // Start at oper_input_base() and count operands
27967 unsigned idx0 = 2;
27968 unsigned idx1 = 2; // cnt
27969 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // base
27970 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
27971 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // zero
27972 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // ktmp
27973 {
27974 C2_MacroAssembler _masm(&cbuf);
27975
27976#line 11290 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
27977
27978 ___masm. clear_mem(opnd_array(2)->as_Register(ra_,this,idx2)/* base */, opnd_array(1)->constantL(), opnd_array(4)->as_Register(ra_,this,idx4)/* zero */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(5)->as_KRegister(ra_,this,idx5)/* ktmp */);
27979
27980#line 27980 "ad_x86.cpp"
27981 }
27982}
27983
27984void string_compareLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
27985 cbuf.set_insts_mark();
27986 // Start at oper_input_base() and count operands
27987 unsigned idx0 = 2;
27988 unsigned idx1 = 2; // str1
27989 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cnt1
27990 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // str2
27991 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // cnt2
27992 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp1
27993 {
27994 C2_MacroAssembler _masm(&cbuf);
27995
27996#line 11304 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
27997
27998 ___masm. string_compare(opnd_array(1)->as_Register(ra_,this,idx1)/* str1 */, opnd_array(3)->as_Register(ra_,this,idx3)/* str2 */,
27999 opnd_array(2)->as_Register(ra_,this,idx2)/* cnt1 */, opnd_array(4)->as_Register(ra_,this,idx4)/* cnt2 */, opnd_array(0)->as_Register(ra_,this)/* result */,
28000 opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp1 */, StrIntrinsicNode::LL, knoreg);
28001
28002#line 28002 "ad_x86.cpp"
28003 }
28004}
28005
28006void string_compareL_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
28007 cbuf.set_insts_mark();
28008 // Start at oper_input_base() and count operands
28009 unsigned idx0 = 2;
28010 unsigned idx1 = 2; // str1
28011 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cnt1
28012 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // str2
28013 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // cnt2
28014 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp1
28015 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // ktmp
28016 {
28017 C2_MacroAssembler _masm(&cbuf);
28018
28019#line 11320 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
28020
28021 ___masm. string_compare(opnd_array(1)->as_Register(ra_,this,idx1)/* str1 */, opnd_array(3)->as_Register(ra_,this,idx3)/* str2 */,
28022 opnd_array(2)->as_Register(ra_,this,idx2)/* cnt1 */, opnd_array(4)->as_Register(ra_,this,idx4)/* cnt2 */, opnd_array(0)->as_Register(ra_,this)/* result */,
28023 opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp1 */, StrIntrinsicNode::LL, opnd_array(6)->as_KRegister(ra_,this,idx6)/* ktmp */);
28024
28025#line 28025 "ad_x86.cpp"
28026 }
28027}
28028
28029void string_compareUNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
28030 cbuf.set_insts_mark();
28031 // Start at oper_input_base() and count operands
28032 unsigned idx0 = 2;
28033 unsigned idx1 = 2; // str1
28034 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cnt1
28035 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // str2
28036 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // cnt2
28037 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp1
28038 {
28039 C2_MacroAssembler _masm(&cbuf);
28040
28041#line 11336 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
28042
28043 ___masm. string_compare(opnd_array(1)->as_Register(ra_,this,idx1)/* str1 */, opnd_array(3)->as_Register(ra_,this,idx3)/* str2 */,
28044 opnd_array(2)->as_Register(ra_,this,idx2)/* cnt1 */, opnd_array(4)->as_Register(ra_,this,idx4)/* cnt2 */, opnd_array(0)->as_Register(ra_,this)/* result */,
28045 opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp1 */, StrIntrinsicNode::UU, knoreg);
28046
28047#line 28047 "ad_x86.cpp"
28048 }
28049}
28050
28051void string_compareU_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
28052 cbuf.set_insts_mark();
28053 // Start at oper_input_base() and count operands
28054 unsigned idx0 = 2;
28055 unsigned idx1 = 2; // str1
28056 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cnt1
28057 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // str2
28058 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // cnt2
28059 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp1
28060 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // ktmp
28061 {
28062 C2_MacroAssembler _masm(&cbuf);
28063
28064#line 11352 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
28065
28066 ___masm. string_compare(opnd_array(1)->as_Register(ra_,this,idx1)/* str1 */, opnd_array(3)->as_Register(ra_,this,idx3)/* str2 */,
28067 opnd_array(2)->as_Register(ra_,this,idx2)/* cnt1 */, opnd_array(4)->as_Register(ra_,this,idx4)/* cnt2 */, opnd_array(0)->as_Register(ra_,this)/* result */,
28068 opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp1 */, StrIntrinsicNode::UU, opnd_array(6)->as_KRegister(ra_,this,idx6)/* ktmp */);
28069
28070#line 28070 "ad_x86.cpp"
28071 }
28072}
28073
28074void string_compareLUNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
28075 cbuf.set_insts_mark();
28076 // Start at oper_input_base() and count operands
28077 unsigned idx0 = 2;
28078 unsigned idx1 = 2; // str1
28079 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cnt1
28080 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // str2
28081 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // cnt2
28082 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp1
28083 {
28084 C2_MacroAssembler _masm(&cbuf);
28085
28086#line 11368 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
28087
28088 ___masm. string_compare(opnd_array(1)->as_Register(ra_,this,idx1)/* str1 */, opnd_array(3)->as_Register(ra_,this,idx3)/* str2 */,
28089 opnd_array(2)->as_Register(ra_,this,idx2)/* cnt1 */, opnd_array(4)->as_Register(ra_,this,idx4)/* cnt2 */, opnd_array(0)->as_Register(ra_,this)/* result */,
28090 opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp1 */, StrIntrinsicNode::LU, knoreg);
28091
28092#line 28092 "ad_x86.cpp"
28093 }
28094}
28095
28096void string_compareLU_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
28097 cbuf.set_insts_mark();
28098 // Start at oper_input_base() and count operands
28099 unsigned idx0 = 2;
28100 unsigned idx1 = 2; // str1
28101 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cnt1
28102 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // str2
28103 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // cnt2
28104 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp1
28105 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // ktmp
28106 {
28107 C2_MacroAssembler _masm(&cbuf);
28108
28109#line 11384 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
28110
28111 ___masm. string_compare(opnd_array(1)->as_Register(ra_,this,idx1)/* str1 */, opnd_array(3)->as_Register(ra_,this,idx3)/* str2 */,
28112 opnd_array(2)->as_Register(ra_,this,idx2)/* cnt1 */, opnd_array(4)->as_Register(ra_,this,idx4)/* cnt2 */, opnd_array(0)->as_Register(ra_,this)/* result */,
28113 opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp1 */, StrIntrinsicNode::LU, opnd_array(6)->as_KRegister(ra_,this,idx6)/* ktmp */);
28114
28115#line 28115 "ad_x86.cpp"
28116 }
28117}
28118
28119void string_compareULNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
28120 cbuf.set_insts_mark();
28121 // Start at oper_input_base() and count operands
28122 unsigned idx0 = 2;
28123 unsigned idx1 = 2; // str1
28124 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cnt1
28125 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // str2
28126 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // cnt2
28127 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp1
28128 {
28129 C2_MacroAssembler _masm(&cbuf);
28130
28131#line 11400 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
28132
28133 ___masm. string_compare(opnd_array(3)->as_Register(ra_,this,idx3)/* str2 */, opnd_array(1)->as_Register(ra_,this,idx1)/* str1 */,
28134 opnd_array(4)->as_Register(ra_,this,idx4)/* cnt2 */, opnd_array(2)->as_Register(ra_,this,idx2)/* cnt1 */, opnd_array(0)->as_Register(ra_,this)/* result */,
28135 opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp1 */, StrIntrinsicNode::UL, knoreg);
28136
28137#line 28137 "ad_x86.cpp"
28138 }
28139}
28140
28141void string_compareUL_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
28142 cbuf.set_insts_mark();
28143 // Start at oper_input_base() and count operands
28144 unsigned idx0 = 2;
28145 unsigned idx1 = 2; // str1
28146 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cnt1
28147 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // str2
28148 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // cnt2
28149 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp1
28150 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // ktmp
28151 {
28152 C2_MacroAssembler _masm(&cbuf);
28153
28154#line 11416 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
28155
28156 ___masm. string_compare(opnd_array(3)->as_Register(ra_,this,idx3)/* str2 */, opnd_array(1)->as_Register(ra_,this,idx1)/* str1 */,
28157 opnd_array(4)->as_Register(ra_,this,idx4)/* cnt2 */, opnd_array(2)->as_Register(ra_,this,idx2)/* cnt1 */, opnd_array(0)->as_Register(ra_,this)/* result */,
28158 opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp1 */, StrIntrinsicNode::UL, opnd_array(6)->as_KRegister(ra_,this,idx6)/* ktmp */);
28159
28160#line 28160 "ad_x86.cpp"
28161 }
28162}
28163
28164void string_indexof_conLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
28165 cbuf.set_insts_mark();
28166 // Start at oper_input_base() and count operands
28167 unsigned idx0 = 2;
28168 unsigned idx1 = 2; // str1
28169 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cnt1
28170 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // str2
28171 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // int_cnt2
28172 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp_vec
28173 {
28174 C2_MacroAssembler _masm(&cbuf);
28175
28176#line 11433 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
28177
28178 int icnt2 = (int)opnd_array(4)->constant();
28179 if (icnt2 >= 16) {
28180 // IndexOf for constant substrings with size >= 16 elements
28181 // which don't need to be loaded through stack.
28182 ___masm. string_indexofC8(opnd_array(1)->as_Register(ra_,this,idx1)/* str1 */, opnd_array(3)->as_Register(ra_,this,idx3)/* str2 */,
28183 opnd_array(2)->as_Register(ra_,this,idx2)/* cnt1 */, as_Register(RAX_enc),
28184 icnt2, opnd_array(0)->as_Register(ra_,this)/* result */,
28185 opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp_vec */, as_Register(RCX_enc), StrIntrinsicNode::LL);
28186 } else {
28187 // Small strings are loaded through stack if they cross page boundary.
28188 ___masm. string_indexof(opnd_array(1)->as_Register(ra_,this,idx1)/* str1 */, opnd_array(3)->as_Register(ra_,this,idx3)/* str2 */,
28189 opnd_array(2)->as_Register(ra_,this,idx2)/* cnt1 */, as_Register(RAX_enc),
28190 icnt2, opnd_array(0)->as_Register(ra_,this)/* result */,
28191 opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp_vec */, as_Register(RCX_enc), StrIntrinsicNode::LL);
28192 }
28193
28194#line 28194 "ad_x86.cpp"
28195 }
28196}
28197
28198void string_indexof_conUNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
28199 cbuf.set_insts_mark();
28200 // Start at oper_input_base() and count operands
28201 unsigned idx0 = 2;
28202 unsigned idx1 = 2; // str1
28203 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cnt1
28204 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // str2
28205 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // int_cnt2
28206 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp_vec
28207 {
28208 C2_MacroAssembler _masm(&cbuf);
28209
28210#line 11462 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
28211
28212 int icnt2 = (int)opnd_array(4)->constant();
28213 if (icnt2 >= 8) {
28214 // IndexOf for constant substrings with size >= 8 elements
28215 // which don't need to be loaded through stack.
28216 ___masm. string_indexofC8(opnd_array(1)->as_Register(ra_,this,idx1)/* str1 */, opnd_array(3)->as_Register(ra_,this,idx3)/* str2 */,
28217 opnd_array(2)->as_Register(ra_,this,idx2)/* cnt1 */, as_Register(RAX_enc),
28218 icnt2, opnd_array(0)->as_Register(ra_,this)/* result */,
28219 opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp_vec */, as_Register(RCX_enc), StrIntrinsicNode::UU);
28220 } else {
28221 // Small strings are loaded through stack if they cross page boundary.
28222 ___masm. string_indexof(opnd_array(1)->as_Register(ra_,this,idx1)/* str1 */, opnd_array(3)->as_Register(ra_,this,idx3)/* str2 */,
28223 opnd_array(2)->as_Register(ra_,this,idx2)/* cnt1 */, as_Register(RAX_enc),
28224 icnt2, opnd_array(0)->as_Register(ra_,this)/* result */,
28225 opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp_vec */, as_Register(RCX_enc), StrIntrinsicNode::UU);
28226 }
28227
28228#line 28228 "ad_x86.cpp"
28229 }
28230}
28231
28232void string_indexof_conULNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
28233 cbuf.set_insts_mark();
28234 // Start at oper_input_base() and count operands
28235 unsigned idx0 = 2;
28236 unsigned idx1 = 2; // str1
28237 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cnt1
28238 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // str2
28239 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // int_cnt2
28240 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp_vec
28241 {
28242 C2_MacroAssembler _masm(&cbuf);
28243
28244#line 11491 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
28245
28246 int icnt2 = (int)opnd_array(4)->constant();
28247 if (icnt2 >= 8) {
28248 // IndexOf for constant substrings with size >= 8 elements
28249 // which don't need to be loaded through stack.
28250 ___masm. string_indexofC8(opnd_array(1)->as_Register(ra_,this,idx1)/* str1 */, opnd_array(3)->as_Register(ra_,this,idx3)/* str2 */,
28251 opnd_array(2)->as_Register(ra_,this,idx2)/* cnt1 */, as_Register(RAX_enc),
28252 icnt2, opnd_array(0)->as_Register(ra_,this)/* result */,
28253 opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp_vec */, as_Register(RCX_enc), StrIntrinsicNode::UL);
28254 } else {
28255 // Small strings are loaded through stack if they cross page boundary.
28256 ___masm. string_indexof(opnd_array(1)->as_Register(ra_,this,idx1)/* str1 */, opnd_array(3)->as_Register(ra_,this,idx3)/* str2 */,
28257 opnd_array(2)->as_Register(ra_,this,idx2)/* cnt1 */, as_Register(RAX_enc),
28258 icnt2, opnd_array(0)->as_Register(ra_,this)/* result */,
28259 opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp_vec */, as_Register(RCX_enc), StrIntrinsicNode::UL);
28260 }
28261
28262#line 28262 "ad_x86.cpp"
28263 }
28264}
28265
28266void string_indexofLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
28267 cbuf.set_insts_mark();
28268 // Start at oper_input_base() and count operands
28269 unsigned idx0 = 2;
28270 unsigned idx1 = 2; // str1
28271 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cnt1
28272 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // str2
28273 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // cnt2
28274 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp_vec
28275 {
28276 C2_MacroAssembler _masm(&cbuf);
28277
28278#line 11519 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
28279
28280 ___masm. string_indexof(opnd_array(1)->as_Register(ra_,this,idx1)/* str1 */, opnd_array(3)->as_Register(ra_,this,idx3)/* str2 */,
28281 opnd_array(2)->as_Register(ra_,this,idx2)/* cnt1 */, opnd_array(4)->as_Register(ra_,this,idx4)/* cnt2 */,
28282 (-1), opnd_array(0)->as_Register(ra_,this)/* result */,
28283 opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp_vec */, as_Register(RCX_enc), StrIntrinsicNode::LL);
28284
28285#line 28285 "ad_x86.cpp"
28286 }
28287}
28288
28289void string_indexofUNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
28290 cbuf.set_insts_mark();
28291 // Start at oper_input_base() and count operands
28292 unsigned idx0 = 2;
28293 unsigned idx1 = 2; // str1
28294 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cnt1
28295 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // str2
28296 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // cnt2
28297 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp_vec
28298 {
28299 C2_MacroAssembler _masm(&cbuf);
28300
28301#line 11536 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
28302
28303 ___masm. string_indexof(opnd_array(1)->as_Register(ra_,this,idx1)/* str1 */, opnd_array(3)->as_Register(ra_,this,idx3)/* str2 */,
28304 opnd_array(2)->as_Register(ra_,this,idx2)/* cnt1 */, opnd_array(4)->as_Register(ra_,this,idx4)/* cnt2 */,
28305 (-1), opnd_array(0)->as_Register(ra_,this)/* result */,
28306 opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp_vec */, as_Register(RCX_enc), StrIntrinsicNode::UU);
28307
28308#line 28308 "ad_x86.cpp"
28309 }
28310}
28311
28312void string_indexofULNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
28313 cbuf.set_insts_mark();
28314 // Start at oper_input_base() and count operands
28315 unsigned idx0 = 2;
28316 unsigned idx1 = 2; // str1
28317 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cnt1
28318 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // str2
28319 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // cnt2
28320 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp_vec
28321 {
28322 C2_MacroAssembler _masm(&cbuf);
28323
28324#line 11553 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
28325
28326 ___masm. string_indexof(opnd_array(1)->as_Register(ra_,this,idx1)/* str1 */, opnd_array(3)->as_Register(ra_,this,idx3)/* str2 */,
28327 opnd_array(2)->as_Register(ra_,this,idx2)/* cnt1 */, opnd_array(4)->as_Register(ra_,this,idx4)/* cnt2 */,
28328 (-1), opnd_array(0)->as_Register(ra_,this)/* result */,
28329 opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp_vec */, as_Register(RCX_enc), StrIntrinsicNode::UL);
28330
28331#line 28331 "ad_x86.cpp"
28332 }
28333}
28334
28335void string_indexof_charNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
28336 cbuf.set_insts_mark();
28337 // Start at oper_input_base() and count operands
28338 unsigned idx0 = 2;
28339 unsigned idx1 = 2; // str1
28340 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cnt1
28341 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // ch
28342 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp_vec1
28343 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp_vec2
28344 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // tmp_vec3
28345 unsigned idx7 = idx6 + opnd_array(6)->num_edges(); // tmp
28346 {
28347 C2_MacroAssembler _masm(&cbuf);
28348
28349#line 11569 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
28350
28351 ___masm. string_indexof_char(opnd_array(1)->as_Register(ra_,this,idx1)/* str1 */, opnd_array(2)->as_Register(ra_,this,idx2)/* cnt1 */, opnd_array(3)->as_Register(ra_,this,idx3)/* ch */, opnd_array(0)->as_Register(ra_,this)/* result */,
28352 opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp_vec1 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp_vec2 */, opnd_array(6)->as_XMMRegister(ra_,this,idx6)/* tmp_vec3 */, opnd_array(7)->as_Register(ra_,this,idx7)/* tmp */);
28353
28354#line 28354 "ad_x86.cpp"
28355 }
28356}
28357
28358void stringL_indexof_charNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
28359 cbuf.set_insts_mark();
28360 // Start at oper_input_base() and count operands
28361 unsigned idx0 = 2;
28362 unsigned idx1 = 2; // str1
28363 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cnt1
28364 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // ch
28365 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp_vec1
28366 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp_vec2
28367 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // tmp_vec3
28368 unsigned idx7 = idx6 + opnd_array(6)->num_edges(); // tmp
28369 {
28370 C2_MacroAssembler _masm(&cbuf);
28371
28372#line 11583 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
28373
28374 ___masm. stringL_indexof_char(opnd_array(1)->as_Register(ra_,this,idx1)/* str1 */, opnd_array(2)->as_Register(ra_,this,idx2)/* cnt1 */, opnd_array(3)->as_Register(ra_,this,idx3)/* ch */, opnd_array(0)->as_Register(ra_,this)/* result */,
28375 opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp_vec1 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp_vec2 */, opnd_array(6)->as_XMMRegister(ra_,this,idx6)/* tmp_vec3 */, opnd_array(7)->as_Register(ra_,this,idx7)/* tmp */);
28376
28377#line 28377 "ad_x86.cpp"
28378 }
28379}
28380
28381void string_equalsNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
28382 cbuf.set_insts_mark();
28383 // Start at oper_input_base() and count operands
28384 unsigned idx0 = 2;
28385 unsigned idx1 = 2; // str1
28386 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // str2
28387 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // cnt
28388 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
28389 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
28390 {
28391 C2_MacroAssembler _masm(&cbuf);
28392
28393#line 11599 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
28394
28395 ___masm. arrays_equals(false, opnd_array(1)->as_Register(ra_,this,idx1)/* str1 */, opnd_array(2)->as_Register(ra_,this,idx2)/* str2 */,
28396 opnd_array(3)->as_Register(ra_,this,idx3)/* cnt */, opnd_array(0)->as_Register(ra_,this)/* result */, as_Register(RBX_enc),
28397 opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, false /* char */, knoreg);
28398
28399#line 28399 "ad_x86.cpp"
28400 }
28401}
28402
28403void string_equals_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
28404 cbuf.set_insts_mark();
28405 // Start at oper_input_base() and count operands
28406 unsigned idx0 = 2;
28407 unsigned idx1 = 2; // str1
28408 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // str2
28409 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // cnt
28410 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
28411 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
28412 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // ktmp
28413 {
28414 C2_MacroAssembler _masm(&cbuf);
28415
28416#line 11615 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
28417
28418 ___masm. arrays_equals(false, opnd_array(1)->as_Register(ra_,this,idx1)/* str1 */, opnd_array(2)->as_Register(ra_,this,idx2)/* str2 */,
28419 opnd_array(3)->as_Register(ra_,this,idx3)/* cnt */, opnd_array(0)->as_Register(ra_,this)/* result */, as_Register(RBX_enc),
28420 opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, false /* char */, opnd_array(6)->as_KRegister(ra_,this,idx6)/* ktmp */);
28421
28422#line 28422 "ad_x86.cpp"
28423 }
28424}
28425
28426void array_equalsBNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
28427 cbuf.set_insts_mark();
28428 // Start at oper_input_base() and count operands
28429 unsigned idx0 = 2;
28430 unsigned idx1 = 2; // ary1
28431 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // ary2
28432 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp1
28433 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
28434 {
28435 C2_MacroAssembler _masm(&cbuf);
28436
28437#line 11632 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
28438
28439 ___masm. arrays_equals(true, opnd_array(1)->as_Register(ra_,this,idx1)/* ary1 */, opnd_array(2)->as_Register(ra_,this,idx2)/* ary2 */,
28440 as_Register(RCX_enc), opnd_array(0)->as_Register(ra_,this)/* result */, as_Register(RBX_enc),
28441 opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, false /* char */, knoreg);
28442
28443#line 28443 "ad_x86.cpp"
28444 }
28445}
28446
28447void array_equalsB_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
28448 cbuf.set_insts_mark();
28449 // Start at oper_input_base() and count operands
28450 unsigned idx0 = 2;
28451 unsigned idx1 = 2; // ary1
28452 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // ary2
28453 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp1
28454 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
28455 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // ktmp
28456 {
28457 C2_MacroAssembler _masm(&cbuf);
28458
28459#line 11648 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
28460
28461 ___masm. arrays_equals(true, opnd_array(1)->as_Register(ra_,this,idx1)/* ary1 */, opnd_array(2)->as_Register(ra_,this,idx2)/* ary2 */,
28462 as_Register(RCX_enc), opnd_array(0)->as_Register(ra_,this)/* result */, as_Register(RBX_enc),
28463 opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, false /* char */, opnd_array(5)->as_KRegister(ra_,this,idx5)/* ktmp */);
28464
28465#line 28465 "ad_x86.cpp"
28466 }
28467}
28468
28469void array_equalsCNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
28470 cbuf.set_insts_mark();
28471 // Start at oper_input_base() and count operands
28472 unsigned idx0 = 2;
28473 unsigned idx1 = 2; // ary1
28474 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // ary2
28475 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp1
28476 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
28477 {
28478 C2_MacroAssembler _masm(&cbuf);
28479
28480#line 11664 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
28481
28482 ___masm. arrays_equals(true, opnd_array(1)->as_Register(ra_,this,idx1)/* ary1 */, opnd_array(2)->as_Register(ra_,this,idx2)/* ary2 */,
28483 as_Register(RCX_enc), opnd_array(0)->as_Register(ra_,this)/* result */, as_Register(RBX_enc),
28484 opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, true /* char */, knoreg);
28485
28486#line 28486 "ad_x86.cpp"
28487 }
28488}
28489
28490void array_equalsC_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
28491 cbuf.set_insts_mark();
28492 // Start at oper_input_base() and count operands
28493 unsigned idx0 = 2;
28494 unsigned idx1 = 2; // ary1
28495 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // ary2
28496 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp1
28497 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
28498 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // ktmp
28499 {
28500 C2_MacroAssembler _masm(&cbuf);
28501
28502#line 11680 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
28503
28504 ___masm. arrays_equals(true, opnd_array(1)->as_Register(ra_,this,idx1)/* ary1 */, opnd_array(2)->as_Register(ra_,this,idx2)/* ary2 */,
28505 as_Register(RCX_enc), opnd_array(0)->as_Register(ra_,this)/* result */, as_Register(RBX_enc),
28506 opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, true /* char */, opnd_array(5)->as_KRegister(ra_,this,idx5)/* ktmp */);
28507
28508#line 28508 "ad_x86.cpp"
28509 }
28510}
28511
28512void has_negativesNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
28513 cbuf.set_insts_mark();
28514 // Start at oper_input_base() and count operands
28515 unsigned idx0 = 2;
28516 unsigned idx1 = 2; // ary1
28517 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // len
28518 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp1
28519 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
28520 {
28521 C2_MacroAssembler _masm(&cbuf);
28522
28523#line 11696 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
28524
28525 ___masm. has_negatives(opnd_array(1)->as_Register(ra_,this,idx1)/* ary1 */, opnd_array(2)->as_Register(ra_,this,idx2)/* len */,
28526 opnd_array(0)->as_Register(ra_,this)/* result */, as_Register(RBX_enc),
28527 opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, knoreg, knoreg);
28528
28529#line 28529 "ad_x86.cpp"
28530 }
28531}
28532
28533void has_negatives_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
28534 cbuf.set_insts_mark();
28535 // Start at oper_input_base() and count operands
28536 unsigned idx0 = 2;
28537 unsigned idx1 = 2; // ary1
28538 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // len
28539 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp1
28540 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
28541 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // ktmp1
28542 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // ktmp2
28543 {
28544 C2_MacroAssembler _masm(&cbuf);
28545
28546#line 11712 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
28547
28548 ___masm. has_negatives(opnd_array(1)->as_Register(ra_,this,idx1)/* ary1 */, opnd_array(2)->as_Register(ra_,this,idx2)/* len */,
28549 opnd_array(0)->as_Register(ra_,this)/* result */, as_Register(RBX_enc),
28550 opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(5)->as_KRegister(ra_,this,idx5)/* ktmp1 */, opnd_array(6)->as_KRegister(ra_,this,idx6)/* ktmp2 */);
28551
28552#line 28552 "ad_x86.cpp"
28553 }
28554}
28555
28556void string_compressNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
28557 cbuf.set_insts_mark();
28558 // Start at oper_input_base() and count operands
28559 unsigned idx0 = 2;
28560 unsigned idx1 = 2; // src
28561 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
28562 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // len
28563 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
28564 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
28565 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // tmp3
28566 unsigned idx7 = idx6 + opnd_array(6)->num_edges(); // tmp4
28567 {
28568 C2_MacroAssembler _masm(&cbuf);
28569
28570#line 11729 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
28571
28572 ___masm. char_array_compress(opnd_array(1)->as_Register(ra_,this,idx1)/* src */, opnd_array(2)->as_Register(ra_,this,idx2)/* dst */, opnd_array(3)->as_Register(ra_,this,idx3)/* len */,
28573 opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(6)->as_XMMRegister(ra_,this,idx6)/* tmp3 */,
28574 opnd_array(7)->as_XMMRegister(ra_,this,idx7)/* tmp4 */, as_Register(RCX_enc), opnd_array(0)->as_Register(ra_,this)/* result */,
28575 knoreg, knoreg);
28576
28577#line 28577 "ad_x86.cpp"
28578 }
28579}
28580
28581void string_compress_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
28582 cbuf.set_insts_mark();
28583 // Start at oper_input_base() and count operands
28584 unsigned idx0 = 2;
28585 unsigned idx1 = 2; // src
28586 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
28587 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // len
28588 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
28589 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
28590 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // tmp3
28591 unsigned idx7 = idx6 + opnd_array(6)->num_edges(); // tmp4
28592 unsigned idx8 = idx7 + opnd_array(7)->num_edges(); // ktmp1
28593 unsigned idx9 = idx8 + opnd_array(8)->num_edges(); // ktmp2
28594 {
28595 C2_MacroAssembler _masm(&cbuf);
28596
28597#line 11746 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
28598
28599 ___masm. char_array_compress(opnd_array(1)->as_Register(ra_,this,idx1)/* src */, opnd_array(2)->as_Register(ra_,this,idx2)/* dst */, opnd_array(3)->as_Register(ra_,this,idx3)/* len */,
28600 opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(6)->as_XMMRegister(ra_,this,idx6)/* tmp3 */,
28601 opnd_array(7)->as_XMMRegister(ra_,this,idx7)/* tmp4 */, as_Register(RCX_enc), opnd_array(0)->as_Register(ra_,this)/* result */,
28602 opnd_array(8)->as_KRegister(ra_,this,idx8)/* ktmp1 */, opnd_array(9)->as_KRegister(ra_,this,idx9)/* ktmp2 */);
28603
28604#line 28604 "ad_x86.cpp"
28605 }
28606}
28607
28608void string_inflateNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
28609 cbuf.set_insts_mark();
28610 // Start at oper_input_base() and count operands
28611 unsigned idx0 = 2;
28612 unsigned idx1 = 2; // src
28613 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
28614 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // len
28615 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
28616 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
28617 {
28618 C2_MacroAssembler _masm(&cbuf);
28619
28620#line 11762 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
28621
28622 ___masm. byte_array_inflate(opnd_array(1)->as_Register(ra_,this,idx1)/* src */, opnd_array(2)->as_Register(ra_,this,idx2)/* dst */, opnd_array(3)->as_Register(ra_,this,idx3)/* len */,
28623 opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(5)->as_Register(ra_,this,idx5)/* tmp2 */, knoreg);
28624
28625#line 28625 "ad_x86.cpp"
28626 }
28627}
28628
28629void string_inflate_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
28630 cbuf.set_insts_mark();
28631 // Start at oper_input_base() and count operands
28632 unsigned idx0 = 2;
28633 unsigned idx1 = 2; // src
28634 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
28635 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // len
28636 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
28637 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // ktmp
28638 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // tmp2
28639 {
28640 C2_MacroAssembler _masm(&cbuf);
28641
28642#line 11776 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
28643
28644 ___masm. byte_array_inflate(opnd_array(1)->as_Register(ra_,this,idx1)/* src */, opnd_array(2)->as_Register(ra_,this,idx2)/* dst */, opnd_array(3)->as_Register(ra_,this,idx3)/* len */,
28645 opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(6)->as_Register(ra_,this,idx6)/* tmp2 */, opnd_array(5)->as_KRegister(ra_,this,idx5)/* ktmp */);
28646
28647#line 28647 "ad_x86.cpp"
28648 }
28649}
28650
28651void encode_iso_arrayNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
28652 cbuf.set_insts_mark();
28653 // Start at oper_input_base() and count operands
28654 unsigned idx0 = 2;
28655 unsigned idx1 = 2; // src
28656 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
28657 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // len
28658 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
28659 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
28660 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // tmp3
28661 unsigned idx7 = idx6 + opnd_array(6)->num_edges(); // tmp4
28662 {
28663 C2_MacroAssembler _masm(&cbuf);
28664
28665#line 11792 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
28666
28667 ___masm. encode_iso_array(opnd_array(1)->as_Register(ra_,this,idx1)/* src */, opnd_array(2)->as_Register(ra_,this,idx2)/* dst */, opnd_array(3)->as_Register(ra_,this,idx3)/* len */,
28668 opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(6)->as_XMMRegister(ra_,this,idx6)/* tmp3 */,
28669 opnd_array(7)->as_XMMRegister(ra_,this,idx7)/* tmp4 */, as_Register(RCX_enc), opnd_array(0)->as_Register(ra_,this)/* result */, false);
28670
28671#line 28671 "ad_x86.cpp"
28672 }
28673}
28674
28675void encode_ascii_arrayNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
28676 cbuf.set_insts_mark();
28677 // Start at oper_input_base() and count operands
28678 unsigned idx0 = 2;
28679 unsigned idx1 = 2; // src
28680 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
28681 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // len
28682 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
28683 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
28684 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // tmp3
28685 unsigned idx7 = idx6 + opnd_array(6)->num_edges(); // tmp4
28686 {
28687 C2_MacroAssembler _masm(&cbuf);
28688
28689#line 11809 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
28690
28691 ___masm. encode_iso_array(opnd_array(1)->as_Register(ra_,this,idx1)/* src */, opnd_array(2)->as_Register(ra_,this,idx2)/* dst */, opnd_array(3)->as_Register(ra_,this,idx3)/* len */,
28692 opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(6)->as_XMMRegister(ra_,this,idx6)/* tmp3 */,
28693 opnd_array(7)->as_XMMRegister(ra_,this,idx7)/* tmp4 */, as_Register(RCX_enc), opnd_array(0)->as_Register(ra_,this)/* result */, true);
28694
28695#line 28695 "ad_x86.cpp"
28696 }
28697}
28698
28699void overflowAddI_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
28700 cbuf.set_insts_mark();
28701 // Start at oper_input_base() and count operands
28702 unsigned idx0 = 1;
28703 unsigned idx1 = 1; // op1
28704 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
28705 {
28706 C2_MacroAssembler _masm(&cbuf);
28707
28708#line 11826 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
28709
28710 ___masm. addl(opnd_array(1)->as_Register(ra_,this,idx1)/* op1 */, opnd_array(2)->as_Register(ra_,this,idx2)/* op2 */);
28711
28712#line 28712 "ad_x86.cpp"
28713 }
28714}
28715
28716void overflowAddI_rReg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
28717 cbuf.set_insts_mark();
28718 // Start at oper_input_base() and count operands
28719 unsigned idx0 = 1;
28720 unsigned idx1 = 1; // op1
28721 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
28722 {
28723 C2_MacroAssembler _masm(&cbuf);
28724
28725#line 11839 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
28726
28727 ___masm. addl(opnd_array(1)->as_Register(ra_,this,idx1)/* op1 */, opnd_array(2)->constant());
28728
28729#line 28729 "ad_x86.cpp"
28730 }
28731}
28732
28733void overflowAddL_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
28734 cbuf.set_insts_mark();
28735 // Start at oper_input_base() and count operands
28736 unsigned idx0 = 1;
28737 unsigned idx1 = 1; // op1
28738 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
28739 {
28740 C2_MacroAssembler _masm(&cbuf);
28741
28742#line 11851 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
28743
28744 ___masm. addq(opnd_array(1)->as_Register(ra_,this,idx1)/* op1 */, opnd_array(2)->as_Register(ra_,this,idx2)/* op2 */);
28745
28746#line 28746 "ad_x86.cpp"
28747 }
28748}
28749
28750void overflowAddL_rReg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
28751 cbuf.set_insts_mark();
28752 // Start at oper_input_base() and count operands
28753 unsigned idx0 = 1;
28754 unsigned idx1 = 1; // op1
28755 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
28756 {
28757 C2_MacroAssembler _masm(&cbuf);
28758
28759#line 11863 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
28760
28761 ___masm. addq(opnd_array(1)->as_Register(ra_,this,idx1)/* op1 */, opnd_array(2)->constantL());
28762
28763#line 28763 "ad_x86.cpp"
28764 }
28765}
28766
28767void overflowSubI_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
28768 cbuf.set_insts_mark();
28769 // Start at oper_input_base() and count operands
28770 unsigned idx0 = 1;
28771 unsigned idx1 = 1; // op1
28772 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
28773 {
28774 C2_MacroAssembler _masm(&cbuf);
28775
28776#line 11874 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
28777
28778 ___masm. cmpl(opnd_array(1)->as_Register(ra_,this,idx1)/* op1 */, opnd_array(2)->as_Register(ra_,this,idx2)/* op2 */);
28779
28780#line 28780 "ad_x86.cpp"
28781 }
28782}
28783
28784void overflowSubI_rReg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
28785 cbuf.set_insts_mark();
28786 // Start at oper_input_base() and count operands
28787 unsigned idx0 = 1;
28788 unsigned idx1 = 1; // op1
28789 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
28790 {
28791 C2_MacroAssembler _masm(&cbuf);
28792
28793#line 11885 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
28794
28795 ___masm. cmpl(opnd_array(1)->as_Register(ra_,this,idx1)/* op1 */, opnd_array(2)->constant());
28796
28797#line 28797 "ad_x86.cpp"
28798 }
28799}
28800
28801void overflowSubL_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
28802 cbuf.set_insts_mark();
28803 // Start at oper_input_base() and count operands
28804 unsigned idx0 = 1;
28805 unsigned idx1 = 1; // op1
28806 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
28807 {
28808 C2_MacroAssembler _masm(&cbuf);
28809
28810#line 11896 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
28811
28812 ___masm. cmpq(opnd_array(1)->as_Register(ra_,this,idx1)/* op1 */, opnd_array(2)->as_Register(ra_,this,idx2)/* op2 */);
28813
28814#line 28814 "ad_x86.cpp"
28815 }
28816}
28817
28818void overflowSubL_rReg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
28819 cbuf.set_insts_mark();
28820 // Start at oper_input_base() and count operands
28821 unsigned idx0 = 1;
28822 unsigned idx1 = 1; // op1
28823 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
28824 {
28825 C2_MacroAssembler _masm(&cbuf);
28826
28827#line 11907 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
28828
28829 ___masm. cmpq(opnd_array(1)->as_Register(ra_,this,idx1)/* op1 */, opnd_array(2)->constantL());
28830
28831#line 28831 "ad_x86.cpp"
28832 }
28833}
28834
28835void overflowNegI_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
28836 cbuf.set_insts_mark();
28837 // Start at oper_input_base() and count operands
28838 unsigned idx0 = 1;
28839 unsigned idx1 = 1; // zero
28840 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
28841 {
28842 C2_MacroAssembler _masm(&cbuf);
28843
28844#line 11919 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
28845
28846 ___masm. negl(opnd_array(2)->as_Register(ra_,this,idx2)/* op2 */);
28847
28848#line 28848 "ad_x86.cpp"
28849 }
28850}
28851
28852void overflowNegL_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
28853 cbuf.set_insts_mark();
28854 // Start at oper_input_base() and count operands
28855 unsigned idx0 = 1;
28856 unsigned idx1 = 1; // zero
28857 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
28858 {
28859 C2_MacroAssembler _masm(&cbuf);
28860
28861#line 11931 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
28862
28863 ___masm. negq(opnd_array(2)->as_Register(ra_,this,idx2)/* op2 */);
28864
28865#line 28865 "ad_x86.cpp"
28866 }
28867}
28868
28869void overflowMulI_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
28870 cbuf.set_insts_mark();
28871 // Start at oper_input_base() and count operands
28872 unsigned idx0 = 1;
28873 unsigned idx1 = 1; // op1
28874 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
28875 {
28876 C2_MacroAssembler _masm(&cbuf);
28877
28878#line 11943 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
28879
28880 ___masm. imull(opnd_array(1)->as_Register(ra_,this,idx1)/* op1 */, opnd_array(2)->as_Register(ra_,this,idx2)/* op2 */);
28881
28882#line 28882 "ad_x86.cpp"
28883 }
28884}
28885
28886void overflowMulI_rReg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
28887 cbuf.set_insts_mark();
28888 // Start at oper_input_base() and count operands
28889 unsigned idx0 = 1;
28890 unsigned idx1 = 1; // op1
28891 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
28892 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
28893 {
28894 C2_MacroAssembler _masm(&cbuf);
28895
28896#line 11955 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
28897
28898 ___masm. imull(opnd_array(3)->as_Register(ra_,this,idx3)/* tmp */, opnd_array(1)->as_Register(ra_,this,idx1)/* op1 */, opnd_array(2)->constant());
28899
28900#line 28900 "ad_x86.cpp"
28901 }
28902}
28903
28904void overflowMulL_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
28905 cbuf.set_insts_mark();
28906 // Start at oper_input_base() and count operands
28907 unsigned idx0 = 1;
28908 unsigned idx1 = 1; // op1
28909 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
28910 {
28911 C2_MacroAssembler _masm(&cbuf);
28912
28913#line 11967 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
28914
28915 ___masm. imulq(opnd_array(1)->as_Register(ra_,this,idx1)/* op1 */, opnd_array(2)->as_Register(ra_,this,idx2)/* op2 */);
28916
28917#line 28917 "ad_x86.cpp"
28918 }
28919}
28920
28921void overflowMulL_rReg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
28922 cbuf.set_insts_mark();
28923 // Start at oper_input_base() and count operands
28924 unsigned idx0 = 1;
28925 unsigned idx1 = 1; // op1
28926 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
28927 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
28928 {
28929 C2_MacroAssembler _masm(&cbuf);
28930
28931#line 11979 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
28932
28933 ___masm. imulq(opnd_array(3)->as_Register(ra_,this,idx3)/* tmp */, opnd_array(1)->as_Register(ra_,this,idx1)/* op1 */, opnd_array(2)->constantL());
28934
28935#line 28935 "ad_x86.cpp"
28936 }
28937}
28938
28939void compI_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
28940 cbuf.set_insts_mark();
28941 // Start at oper_input_base() and count operands
28942 unsigned idx0 = 1;
28943 unsigned idx1 = 1; // op1
28944 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
28945 {
28946 C2_MacroAssembler _masm(&cbuf);
28947
28948#line 11996 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
28949
28950 ___masm. cmpl(opnd_array(1)->as_Register(ra_,this,idx1)/* op1 */, opnd_array(2)->as_Register(ra_,this,idx2)/* op2 */);
28951
28952#line 28952 "ad_x86.cpp"
28953 }
28954}
28955
28956void compI_rReg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
28957 cbuf.set_insts_mark();
28958 // Start at oper_input_base() and count operands
28959 unsigned idx0 = 1;
28960 unsigned idx1 = 1; // op1
28961 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
28962 {
28963 C2_MacroAssembler _masm(&cbuf);
28964
28965#line 12007 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
28966
28967 ___masm. cmpl(opnd_array(1)->as_Register(ra_,this,idx1)/* op1 */, opnd_array(2)->constant());
28968
28969#line 28969 "ad_x86.cpp"
28970 }
28971}
28972
28973void compI_rReg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
28974 cbuf.set_insts_mark();
28975 // Start at oper_input_base() and count operands
28976 unsigned idx0 = 2;
28977 unsigned idx1 = 2; // op1
28978 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
28979 {
28980 C2_MacroAssembler _masm(&cbuf);
28981
28982#line 12019 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
28983
28984 ___masm. cmpl(opnd_array(1)->as_Register(ra_,this,idx1)/* op1 */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
28985
28986#line 28986 "ad_x86.cpp"
28987 }
28988}
28989
28990void testI_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
28991 cbuf.set_insts_mark();
28992 // Start at oper_input_base() and count operands
28993 unsigned idx0 = 1;
28994 unsigned idx1 = 1; // src
28995 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
28996 {
28997 C2_MacroAssembler _masm(&cbuf);
28998
28999#line 12030 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
29000
29001 ___masm. testl(opnd_array(1)->as_Register(ra_,this,idx1)/* src */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
29002
29003#line 29003 "ad_x86.cpp"
29004 }
29005}
29006
29007void testI_reg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29008 cbuf.set_insts_mark();
29009 // Start at oper_input_base() and count operands
29010 unsigned idx0 = 1;
29011 unsigned idx1 = 1; // src
29012 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
29013 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // zero
29014 {
29015 C2_MacroAssembler _masm(&cbuf);
29016
29017#line 12041 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
29018
29019 ___masm. testl(opnd_array(1)->as_Register(ra_,this,idx1)/* src */, opnd_array(2)->constant());
29020
29021#line 29021 "ad_x86.cpp"
29022 }
29023}
29024
29025void testI_reg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29026 cbuf.set_insts_mark();
29027 // Start at oper_input_base() and count operands
29028 unsigned idx0 = 2;
29029 unsigned idx1 = 2; // src
29030 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
29031 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // zero
29032 {
29033 C2_MacroAssembler _masm(&cbuf);
29034
29035#line 12052 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
29036
29037 ___masm. testl(opnd_array(1)->as_Register(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
29038
29039#line 29039 "ad_x86.cpp"
29040 }
29041}
29042
29043void testI_reg_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29044 cbuf.set_insts_mark();
29045 // Start at oper_input_base() and count operands
29046 unsigned idx0 = 2;
29047 unsigned idx1 = 2; // mem
29048 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
29049 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // zero
29050 {
29051 C2_MacroAssembler _masm(&cbuf);
29052
29053#line 12052 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
29054
29055 ___masm. testl(opnd_array(2)->as_Register(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
29056
29057#line 29057 "ad_x86.cpp"
29058 }
29059}
29060
29061void compU_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29062 cbuf.set_insts_mark();
29063 // Start at oper_input_base() and count operands
29064 unsigned idx0 = 1;
29065 unsigned idx1 = 1; // op1
29066 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
29067 {
29068 C2_MacroAssembler _masm(&cbuf);
29069
29070#line 12065 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
29071
29072 ___masm. cmpl(opnd_array(1)->as_Register(ra_,this,idx1)/* op1 */, opnd_array(2)->as_Register(ra_,this,idx2)/* op2 */);
29073
29074#line 29074 "ad_x86.cpp"
29075 }
29076}
29077
29078void compU_rReg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29079 cbuf.set_insts_mark();
29080 // Start at oper_input_base() and count operands
29081 unsigned idx0 = 1;
29082 unsigned idx1 = 1; // op1
29083 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
29084 {
29085 C2_MacroAssembler _masm(&cbuf);
29086
29087#line 12076 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
29088
29089 ___masm. cmpl(opnd_array(1)->as_Register(ra_,this,idx1)/* op1 */, opnd_array(2)->constant());
29090
29091#line 29091 "ad_x86.cpp"
29092 }
29093}
29094
29095void compU_rReg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29096 cbuf.set_insts_mark();
29097 // Start at oper_input_base() and count operands
29098 unsigned idx0 = 2;
29099 unsigned idx1 = 2; // op1
29100 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
29101 {
29102 C2_MacroAssembler _masm(&cbuf);
29103
29104#line 12088 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
29105
29106 ___masm. cmpl(opnd_array(1)->as_Register(ra_,this,idx1)/* op1 */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
29107
29108#line 29108 "ad_x86.cpp"
29109 }
29110}
29111
29112void testU_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29113 cbuf.set_insts_mark();
29114 // Start at oper_input_base() and count operands
29115 unsigned idx0 = 1;
29116 unsigned idx1 = 1; // src
29117 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
29118 {
29119 C2_MacroAssembler _masm(&cbuf);
29120
29121#line 12110 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
29122
29123 ___masm. testl(opnd_array(1)->as_Register(ra_,this,idx1)/* src */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
29124
29125#line 29125 "ad_x86.cpp"
29126 }
29127}
29128
29129void compP_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29130 cbuf.set_insts_mark();
29131 // Start at oper_input_base() and count operands
29132 unsigned idx0 = 1;
29133 unsigned idx1 = 1; // op1
29134 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
29135 {
29136 C2_MacroAssembler _masm(&cbuf);
29137
29138#line 12121 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
29139
29140 ___masm. cmpq(opnd_array(1)->as_Register(ra_,this,idx1)/* op1 */, opnd_array(2)->as_Register(ra_,this,idx2)/* op2 */);
29141
29142#line 29142 "ad_x86.cpp"
29143 }
29144}
29145
29146void compP_rReg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29147 cbuf.set_insts_mark();
29148 // Start at oper_input_base() and count operands
29149 unsigned idx0 = 2;
29150 unsigned idx1 = 2; // op1
29151 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
29152 {
29153 C2_MacroAssembler _masm(&cbuf);
29154
29155#line 12134 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
29156
29157 ___masm. cmpq(opnd_array(1)->as_Register(ra_,this,idx1)/* op1 */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
29158
29159#line 29159 "ad_x86.cpp"
29160 }
29161}
29162
29163void compP_mem_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29164 cbuf.set_insts_mark();
29165 // Start at oper_input_base() and count operands
29166 unsigned idx0 = 2;
29167 unsigned idx1 = 2; // op1
29168 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
29169 {
29170 C2_MacroAssembler _masm(&cbuf);
29171
29172#line 12162 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
29173
29174 ___masm. cmpq(opnd_array(1)->as_Register(ra_,this,idx1)/* op1 */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
29175
29176#line 29176 "ad_x86.cpp"
29177 }
29178}
29179
29180void testP_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29181 cbuf.set_insts_mark();
29182 // Start at oper_input_base() and count operands
29183 unsigned idx0 = 1;
29184 unsigned idx1 = 1; // src
29185 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
29186 {
29187 C2_MacroAssembler _masm(&cbuf);
29188
29189#line 12175 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
29190
29191 ___masm. testq(opnd_array(1)->as_Register(ra_,this,idx1)/* src */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
29192
29193#line 29193 "ad_x86.cpp"
29194 }
29195}
29196
29197void testP_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29198 cbuf.set_insts_mark();
29199 // Start at oper_input_base() and count operands
29200 unsigned idx0 = 2;
29201 unsigned idx1 = 2; // op
29202 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
29203 {
29204 C2_MacroAssembler _masm(&cbuf);
29205
29206#line 12191 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
29207
29208 ___masm. testq(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), 0xFFFFFFFF);
29209
29210#line 29210 "ad_x86.cpp"
29211 }
29212}
29213
29214void testP_mem_reg0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29215 cbuf.set_insts_mark();
29216 // Start at oper_input_base() and count operands
29217 unsigned idx0 = 2;
29218 unsigned idx1 = 2; // mem
29219 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
29220 {
29221 C2_MacroAssembler _masm(&cbuf);
29222
29223#line 12204 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
29224
29225 ___masm. cmpq(r12, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
29226
29227#line 29227 "ad_x86.cpp"
29228 }
29229}
29230
29231void compN_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29232 cbuf.set_insts_mark();
29233 // Start at oper_input_base() and count operands
29234 unsigned idx0 = 1;
29235 unsigned idx1 = 1; // op1
29236 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
29237 {
29238 C2_MacroAssembler _masm(&cbuf);
29239
29240#line 12215 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
29241___masm. cmpl(opnd_array(1)->as_Register(ra_,this,idx1)/* op1 */, opnd_array(2)->as_Register(ra_,this,idx2)/* op2 */);
29242#line 29242 "ad_x86.cpp"
29243 }
29244}
29245
29246void compN_rReg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29247 cbuf.set_insts_mark();
29248 // Start at oper_input_base() and count operands
29249 unsigned idx0 = 2;
29250 unsigned idx1 = 2; // src
29251 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
29252 {
29253 C2_MacroAssembler _masm(&cbuf);
29254
29255#line 12224 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
29256
29257 ___masm. cmpl(opnd_array(1)->as_Register(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
29258
29259#line 29259 "ad_x86.cpp"
29260 }
29261}
29262
29263void compN_rReg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29264 cbuf.set_insts_mark();
29265 // Start at oper_input_base() and count operands
29266 unsigned idx0 = 1;
29267 unsigned idx1 = 1; // op1
29268 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
29269 {
29270 C2_MacroAssembler _masm(&cbuf);
29271
29272#line 12234 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
29273
29274 ___masm. cmp_narrow_oop(opnd_array(1)->as_Register(ra_,this,idx1)/* op1 */, (jobject)opnd_array(2)->constant());
29275
29276#line 29276 "ad_x86.cpp"
29277 }
29278}
29279
29280void compN_mem_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29281 cbuf.set_insts_mark();
29282 // Start at oper_input_base() and count operands
29283 unsigned idx0 = 2;
29284 unsigned idx1 = 2; // src
29285 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
29286 {
29287 C2_MacroAssembler _masm(&cbuf);
29288
29289#line 12245 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
29290
29291 ___masm. cmp_narrow_oop(Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), (jobject)opnd_array(1)->constant());
29292
29293#line 29293 "ad_x86.cpp"
29294 }
29295}
29296
29297void compN_rReg_imm_klassNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29298 cbuf.set_insts_mark();
29299 // Start at oper_input_base() and count operands
29300 unsigned idx0 = 1;
29301 unsigned idx1 = 1; // op1
29302 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
29303 {
29304 C2_MacroAssembler _masm(&cbuf);
29305
29306#line 12255 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
29307
29308 ___masm. cmp_narrow_klass(opnd_array(1)->as_Register(ra_,this,idx1)/* op1 */, (Klass*)opnd_array(2)->constant());
29309
29310#line 29310 "ad_x86.cpp"
29311 }
29312}
29313
29314void compN_mem_imm_klassNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29315 cbuf.set_insts_mark();
29316 // Start at oper_input_base() and count operands
29317 unsigned idx0 = 2;
29318 unsigned idx1 = 2; // src
29319 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
29320 {
29321 C2_MacroAssembler _masm(&cbuf);
29322
29323#line 12266 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
29324
29325 ___masm. cmp_narrow_klass(Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), (Klass*)opnd_array(1)->constant());
29326
29327#line 29327 "ad_x86.cpp"
29328 }
29329}
29330
29331void testN_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29332 cbuf.set_insts_mark();
29333 // Start at oper_input_base() and count operands
29334 unsigned idx0 = 1;
29335 unsigned idx1 = 1; // src
29336 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
29337 {
29338 C2_MacroAssembler _masm(&cbuf);
29339
29340#line 12276 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
29341___masm. testl(opnd_array(1)->as_Register(ra_,this,idx1)/* src */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
29342#line 29342 "ad_x86.cpp"
29343 }
29344}
29345
29346void testN_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29347 cbuf.set_insts_mark();
29348 // Start at oper_input_base() and count operands
29349 unsigned idx0 = 2;
29350 unsigned idx1 = 2; // mem
29351 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
29352 {
29353 C2_MacroAssembler _masm(&cbuf);
29354
29355#line 12287 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
29356
29357 ___masm. cmpl(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), (int)0xFFFFFFFF);
29358
29359#line 29359 "ad_x86.cpp"
29360 }
29361}
29362
29363void testN_mem_reg0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29364 cbuf.set_insts_mark();
29365 // Start at oper_input_base() and count operands
29366 unsigned idx0 = 2;
29367 unsigned idx1 = 2; // mem
29368 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
29369 {
29370 C2_MacroAssembler _masm(&cbuf);
29371
29372#line 12299 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
29373
29374 ___masm. cmpl(r12, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
29375
29376#line 29376 "ad_x86.cpp"
29377 }
29378}
29379
29380void compL_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29381 cbuf.set_insts_mark();
29382 // Start at oper_input_base() and count operands
29383 unsigned idx0 = 1;
29384 unsigned idx1 = 1; // op1
29385 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
29386 {
29387 C2_MacroAssembler _masm(&cbuf);
29388
29389#line 12313 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
29390
29391 ___masm. cmpq(opnd_array(1)->as_Register(ra_,this,idx1)/* op1 */, opnd_array(2)->as_Register(ra_,this,idx2)/* op2 */);
29392
29393#line 29393 "ad_x86.cpp"
29394 }
29395}
29396
29397void compL_rReg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29398 cbuf.set_insts_mark();
29399 // Start at oper_input_base() and count operands
29400 unsigned idx0 = 1;
29401 unsigned idx1 = 1; // op1
29402 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
29403 {
29404 C2_MacroAssembler _masm(&cbuf);
29405
29406#line 12324 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
29407
29408 ___masm. cmpq(opnd_array(1)->as_Register(ra_,this,idx1)/* op1 */, opnd_array(2)->constantL());
29409
29410#line 29410 "ad_x86.cpp"
29411 }
29412}
29413
29414void compL_rReg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29415 cbuf.set_insts_mark();
29416 // Start at oper_input_base() and count operands
29417 unsigned idx0 = 2;
29418 unsigned idx1 = 2; // op1
29419 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
29420 {
29421 C2_MacroAssembler _masm(&cbuf);
29422
29423#line 12335 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
29424
29425 ___masm. cmpq(opnd_array(1)->as_Register(ra_,this,idx1)/* op1 */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
29426
29427#line 29427 "ad_x86.cpp"
29428 }
29429}
29430
29431void testL_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29432 cbuf.set_insts_mark();
29433 // Start at oper_input_base() and count operands
29434 unsigned idx0 = 1;
29435 unsigned idx1 = 1; // src
29436 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
29437 {
29438 C2_MacroAssembler _masm(&cbuf);
29439
29440#line 12346 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
29441
29442 ___masm. testq(opnd_array(1)->as_Register(ra_,this,idx1)/* src */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
29443
29444#line 29444 "ad_x86.cpp"
29445 }
29446}
29447
29448void testL_reg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29449 cbuf.set_insts_mark();
29450 // Start at oper_input_base() and count operands
29451 unsigned idx0 = 1;
29452 unsigned idx1 = 1; // src
29453 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
29454 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // zero
29455 {
29456 C2_MacroAssembler _masm(&cbuf);
29457
29458#line 12357 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
29459
29460 ___masm. testq(opnd_array(1)->as_Register(ra_,this,idx1)/* src */, opnd_array(2)->constantL());
29461
29462#line 29462 "ad_x86.cpp"
29463 }
29464}
29465
29466void testL_reg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29467 cbuf.set_insts_mark();
29468 // Start at oper_input_base() and count operands
29469 unsigned idx0 = 2;
29470 unsigned idx1 = 2; // src
29471 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
29472 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // zero
29473 {
29474 C2_MacroAssembler _masm(&cbuf);
29475
29476#line 12368 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
29477
29478 ___masm. testq(opnd_array(1)->as_Register(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
29479
29480#line 29480 "ad_x86.cpp"
29481 }
29482}
29483
29484void testL_reg_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29485 cbuf.set_insts_mark();
29486 // Start at oper_input_base() and count operands
29487 unsigned idx0 = 2;
29488 unsigned idx1 = 2; // mem
29489 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
29490 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // zero
29491 {
29492 C2_MacroAssembler _masm(&cbuf);
29493
29494#line 12368 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
29495
29496 ___masm. testq(opnd_array(2)->as_Register(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
29497
29498#line 29498 "ad_x86.cpp"
29499 }
29500}
29501
29502void testL_reg_mem2Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29503 cbuf.set_insts_mark();
29504 // Start at oper_input_base() and count operands
29505 unsigned idx0 = 2;
29506 unsigned idx1 = 2; // src
29507 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
29508 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // zero
29509 {
29510 C2_MacroAssembler _masm(&cbuf);
29511
29512#line 12379 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
29513
29514 ___masm. testq(opnd_array(1)->as_Register(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
29515
29516#line 29516 "ad_x86.cpp"
29517 }
29518}
29519
29520void testL_reg_mem2_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29521 cbuf.set_insts_mark();
29522 // Start at oper_input_base() and count operands
29523 unsigned idx0 = 2;
29524 unsigned idx1 = 2; // mem
29525 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
29526 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // zero
29527 {
29528 C2_MacroAssembler _masm(&cbuf);
29529
29530#line 12379 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
29531
29532 ___masm. testq(opnd_array(2)->as_Register(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
29533
29534#line 29534 "ad_x86.cpp"
29535 }
29536}
29537
29538void cmpL3_reg_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29539 cbuf.set_insts_mark();
29540 // Start at oper_input_base() and count operands
29541 unsigned idx0 = 1;
29542 unsigned idx1 = 1; // src1
29543 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
29544 {
29545 C2_MacroAssembler _masm(&cbuf);
29546
29547#line 12399 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
29548
29549 Label done;
29550 ___masm. cmpq(opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */, opnd_array(2)->as_Register(ra_,this,idx2)/* src2 */);
29551 ___masm. movl(opnd_array(0)->as_Register(ra_,this)/* dst */, -1);
29552 ___masm. jccb(Assembler::less, done)jccb_0(Assembler::less, done, "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 12403);
29553 ___masm. setne(opnd_array(0)->as_Register(ra_,this)/* dst */);
29554 ___masm. movzbl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(0)->as_Register(ra_,this)/* dst */);
29555 ___masm. bind(done);
29556
29557#line 29557 "ad_x86.cpp"
29558 }
29559}
29560
29561void compUL_rRegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29562 cbuf.set_insts_mark();
29563 // Start at oper_input_base() and count operands
29564 unsigned idx0 = 1;
29565 unsigned idx1 = 1; // op1
29566 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
29567 {
29568 C2_MacroAssembler _masm(&cbuf);
29569
29570#line 12418 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
29571
29572 ___masm. cmpq(opnd_array(1)->as_Register(ra_,this,idx1)/* op1 */, opnd_array(2)->as_Register(ra_,this,idx2)/* op2 */);
29573
29574#line 29574 "ad_x86.cpp"
29575 }
29576}
29577
29578void compUL_rReg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29579 cbuf.set_insts_mark();
29580 // Start at oper_input_base() and count operands
29581 unsigned idx0 = 1;
29582 unsigned idx1 = 1; // op1
29583 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
29584 {
29585 C2_MacroAssembler _masm(&cbuf);
29586
29587#line 12429 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
29588
29589 ___masm. cmpq(opnd_array(1)->as_Register(ra_,this,idx1)/* op1 */, opnd_array(2)->constantL());
29590
29591#line 29591 "ad_x86.cpp"
29592 }
29593}
29594
29595void compUL_rReg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29596 cbuf.set_insts_mark();
29597 // Start at oper_input_base() and count operands
29598 unsigned idx0 = 2;
29599 unsigned idx1 = 2; // op1
29600 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // op2
29601 {
29602 C2_MacroAssembler _masm(&cbuf);
29603
29604#line 12440 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
29605
29606 ___masm. cmpq(opnd_array(1)->as_Register(ra_,this,idx1)/* op1 */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
29607
29608#line 29608 "ad_x86.cpp"
29609 }
29610}
29611
29612void testUL_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29613 cbuf.set_insts_mark();
29614 // Start at oper_input_base() and count operands
29615 unsigned idx0 = 1;
29616 unsigned idx1 = 1; // src
29617 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
29618 {
29619 C2_MacroAssembler _masm(&cbuf);
29620
29621#line 12451 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
29622
29623 ___masm. testq(opnd_array(1)->as_Register(ra_,this,idx1)/* src */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
29624
29625#line 29625 "ad_x86.cpp"
29626 }
29627}
29628
29629void compB_mem_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29630 cbuf.set_insts_mark();
29631 // Start at oper_input_base() and count operands
29632 unsigned idx0 = 2;
29633 unsigned idx1 = 2; // mem
29634 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // imm
29635 {
29636 C2_MacroAssembler _masm(&cbuf);
29637
29638#line 12463 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
29639___masm. cmpb(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->constant());
29640#line 29640 "ad_x86.cpp"
29641 }
29642}
29643
29644void testUB_mem_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29645 cbuf.set_insts_mark();
29646 // Start at oper_input_base() and count operands
29647 unsigned idx0 = 2;
29648 unsigned idx1 = 2; // mem
29649 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // imm
29650 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // zero
29651 {
29652 C2_MacroAssembler _masm(&cbuf);
29653
29654#line 12473 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
29655___masm. testb(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->constant());
29656#line 29656 "ad_x86.cpp"
29657 }
29658}
29659
29660void testB_mem_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29661 cbuf.set_insts_mark();
29662 // Start at oper_input_base() and count operands
29663 unsigned idx0 = 2;
29664 unsigned idx1 = 2; // mem
29665 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // imm
29666 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // zero
29667 {
29668 C2_MacroAssembler _masm(&cbuf);
29669
29670#line 12483 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
29671___masm. testb(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->constant());
29672#line 29672 "ad_x86.cpp"
29673 }
29674}
29675
29676void cmovI_reg_gNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29677 cbuf.set_insts_mark();
29678 // Start at oper_input_base() and count operands
29679 unsigned idx0 = 1;
29680 unsigned idx1 = 1; // src
29681 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
29682 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); //
29683 {
29684 C2_MacroAssembler _masm(&cbuf);
29685
29686#line 12495 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
29687
29688 ___masm. cmovl(Assembler::greater, opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, opnd_array(2)->as_Register(ra_,this,idx2)/* src */);
29689
29690#line 29690 "ad_x86.cpp"
29691 }
29692}
29693
29694void cmovI_reg_lNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29695 cbuf.set_insts_mark();
29696 // Start at oper_input_base() and count operands
29697 unsigned idx0 = 1;
29698 unsigned idx1 = 1; // src
29699 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cr
29700 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); //
29701 {
29702 C2_MacroAssembler _masm(&cbuf);
29703
29704#line 12519 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
29705
29706 ___masm. cmovl(Assembler::less, opnd_array(1)->as_Register(ra_,this,idx1)/* dst */, opnd_array(2)->as_Register(ra_,this,idx2)/* src */);
29707
29708#line 29708 "ad_x86.cpp"
29709 }
29710}
29711
29712void jmpDirNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29713 cbuf.set_insts_mark();
29714 // Start at oper_input_base() and count operands
29715 unsigned idx0 = 1;
29716 unsigned idx1 = 1; //
29717 {
29718 C2_MacroAssembler _masm(&cbuf);
29719
29720#line 12550 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
29721
29722 Label* L = opnd_array(1)->label();
29723 ___masm. jmp(*L, false); // Always long jump
29724
29725#line 29725 "ad_x86.cpp"
29726 }
29727}
29728
29729uint jmpDirNode::size(PhaseRegAlloc *ra_) const {
29730 assert(VerifyOops || MachNode::size(ra_) <= 5, "bad fixed size")do { if (!(VerifyOops || MachNode::size(ra_) <= 5)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 29729, "assert(" "VerifyOops || MachNode::size(ra_) <= 5"
") failed", "bad fixed size"); ::breakpoint(); } } while (0);
29731 return (VerifyOops ? MachNode::size(ra_) : 5);
29732}
29733
29734void jmpConNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29735 cbuf.set_insts_mark();
29736 // Start at oper_input_base() and count operands
29737 unsigned idx0 = 1;
29738 unsigned idx1 = 1; // cr
29739 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // labl
29740 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); //
29741 {
29742 C2_MacroAssembler _masm(&cbuf);
29743
29744#line 12566 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
29745
29746 Label* L = opnd_array(3)->label();
29747 ___masm. jcc((Assembler::Condition)(opnd_array(1)->ccode()), *L, false); // Always long jump
29748
29749#line 29749 "ad_x86.cpp"
29750 }
29751}
29752
29753uint jmpConNode::size(PhaseRegAlloc *ra_) const {
29754 assert(VerifyOops || MachNode::size(ra_) <= 6, "bad fixed size")do { if (!(VerifyOops || MachNode::size(ra_) <= 6)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 29753, "assert(" "VerifyOops || MachNode::size(ra_) <= 6"
") failed", "bad fixed size"); ::breakpoint(); } } while (0);
29755 return (VerifyOops ? MachNode::size(ra_) : 6);
29756}
29757
29758void jmpLoopEndNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29759 cbuf.set_insts_mark();
29760 // Start at oper_input_base() and count operands
29761 unsigned idx0 = 1;
29762 unsigned idx1 = 1; // cr
29763 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // labl
29764 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); //
29765 {
29766 C2_MacroAssembler _masm(&cbuf);
29767
29768#line 12583 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
29769
29770 Label* L = opnd_array(3)->label();
29771 ___masm. jcc((Assembler::Condition)(opnd_array(1)->ccode()), *L, false); // Always long jump
29772
29773#line 29773 "ad_x86.cpp"
29774 }
29775}
29776
29777uint jmpLoopEndNode::size(PhaseRegAlloc *ra_) const {
29778 assert(VerifyOops || MachNode::size(ra_) <= 6, "bad fixed size")do { if (!(VerifyOops || MachNode::size(ra_) <= 6)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 29777, "assert(" "VerifyOops || MachNode::size(ra_) <= 6"
") failed", "bad fixed size"); ::breakpoint(); } } while (0);
29779 return (VerifyOops ? MachNode::size(ra_) : 6);
29780}
29781
29782void jmpLoopEndUNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29783 cbuf.set_insts_mark();
29784 // Start at oper_input_base() and count operands
29785 unsigned idx0 = 1;
29786 unsigned idx1 = 1; // cmp
29787 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // labl
29788 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); //
29789 {
29790 C2_MacroAssembler _masm(&cbuf);
29791
29792#line 12599 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
29793
29794 Label* L = opnd_array(3)->label();
29795 ___masm. jcc((Assembler::Condition)(opnd_array(1)->ccode()), *L, false); // Always long jump
29796
29797#line 29797 "ad_x86.cpp"
29798 }
29799}
29800
29801uint jmpLoopEndUNode::size(PhaseRegAlloc *ra_) const {
29802 assert(VerifyOops || MachNode::size(ra_) <= 6, "bad fixed size")do { if (!(VerifyOops || MachNode::size(ra_) <= 6)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 29801, "assert(" "VerifyOops || MachNode::size(ra_) <= 6"
") failed", "bad fixed size"); ::breakpoint(); } } while (0);
29803 return (VerifyOops ? MachNode::size(ra_) : 6);
29804}
29805
29806void jmpLoopEndUCFNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29807 cbuf.set_insts_mark();
29808 // Start at oper_input_base() and count operands
29809 unsigned idx0 = 1;
29810 unsigned idx1 = 1; // cmp
29811 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // labl
29812 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); //
29813 {
29814 C2_MacroAssembler _masm(&cbuf);
29815
29816#line 12614 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
29817
29818 Label* L = opnd_array(3)->label();
29819 ___masm. jcc((Assembler::Condition)(opnd_array(1)->ccode()), *L, false); // Always long jump
29820
29821#line 29821 "ad_x86.cpp"
29822 }
29823}
29824
29825uint jmpLoopEndUCFNode::size(PhaseRegAlloc *ra_) const {
29826 assert(VerifyOops || MachNode::size(ra_) <= 6, "bad fixed size")do { if (!(VerifyOops || MachNode::size(ra_) <= 6)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 29825, "assert(" "VerifyOops || MachNode::size(ra_) <= 6"
") failed", "bad fixed size"); ::breakpoint(); } } while (0);
29827 return (VerifyOops ? MachNode::size(ra_) : 6);
29828}
29829
29830void jmpLoopEnd_and_restoreMaskNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29831 cbuf.set_insts_mark();
29832 // Start at oper_input_base() and count operands
29833 unsigned idx0 = 1;
29834 unsigned idx1 = 1; // cr
29835 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // ktmp
29836 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // labl
29837 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); //
29838 {
29839 C2_MacroAssembler _masm(&cbuf);
29840
29841#line 12635 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
29842
29843 Label* L = opnd_array(4)->label();
29844 ___masm. jcc((Assembler::Condition)(opnd_array(1)->ccode()), *L, false); // Always long jump
29845 ___masm. restorevectmask(opnd_array(3)->as_KRegister(ra_,this,idx3)/* ktmp */);
29846
29847#line 29847 "ad_x86.cpp"
29848 }
29849}
29850
29851uint jmpLoopEnd_and_restoreMaskNode::size(PhaseRegAlloc *ra_) const {
29852 assert(VerifyOops || MachNode::size(ra_) <= 10, "bad fixed size")do { if (!(VerifyOops || MachNode::size(ra_) <= 10)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 29851, "assert(" "VerifyOops || MachNode::size(ra_) <= 10"
") failed", "bad fixed size"); ::breakpoint(); } } while (0);
29853 return (VerifyOops ? MachNode::size(ra_) : 10);
29854}
29855
29856void jmpLoopEndU_and_restoreMaskNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29857 cbuf.set_insts_mark();
29858 // Start at oper_input_base() and count operands
29859 unsigned idx0 = 1;
29860 unsigned idx1 = 1; // cmp
29861 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // ktmp
29862 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // labl
29863 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); //
29864 {
29865 C2_MacroAssembler _masm(&cbuf);
29866
29867#line 12655 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
29868
29869 Label* L = opnd_array(4)->label();
29870 ___masm. jcc((Assembler::Condition)(opnd_array(1)->ccode()), *L, false); // Always long jump
29871 ___masm. restorevectmask(opnd_array(3)->as_KRegister(ra_,this,idx3)/* ktmp */);
29872
29873#line 29873 "ad_x86.cpp"
29874 }
29875}
29876
29877uint jmpLoopEndU_and_restoreMaskNode::size(PhaseRegAlloc *ra_) const {
29878 assert(VerifyOops || MachNode::size(ra_) <= 10, "bad fixed size")do { if (!(VerifyOops || MachNode::size(ra_) <= 10)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 29877, "assert(" "VerifyOops || MachNode::size(ra_) <= 10"
") failed", "bad fixed size"); ::breakpoint(); } } while (0);
29879 return (VerifyOops ? MachNode::size(ra_) : 10);
29880}
29881
29882void jmpLoopEndUCF_and_restoreMaskNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29883 cbuf.set_insts_mark();
29884 // Start at oper_input_base() and count operands
29885 unsigned idx0 = 1;
29886 unsigned idx1 = 1; // cmp
29887 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // ktmp
29888 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // labl
29889 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); //
29890 {
29891 C2_MacroAssembler _masm(&cbuf);
29892
29893#line 12674 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
29894
29895 Label* L = opnd_array(4)->label();
29896 ___masm. jcc((Assembler::Condition)(opnd_array(1)->ccode()), *L, false); // Always long jump
29897 ___masm. restorevectmask(opnd_array(3)->as_KRegister(ra_,this,idx3)/* ktmp */);
29898
29899#line 29899 "ad_x86.cpp"
29900 }
29901}
29902
29903uint jmpLoopEndUCF_and_restoreMaskNode::size(PhaseRegAlloc *ra_) const {
29904 assert(VerifyOops || MachNode::size(ra_) <= 10, "bad fixed size")do { if (!(VerifyOops || MachNode::size(ra_) <= 10)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 29903, "assert(" "VerifyOops || MachNode::size(ra_) <= 10"
") failed", "bad fixed size"); ::breakpoint(); } } while (0);
29905 return (VerifyOops ? MachNode::size(ra_) : 10);
29906}
29907
29908void jmpConUNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29909 cbuf.set_insts_mark();
29910 // Start at oper_input_base() and count operands
29911 unsigned idx0 = 1;
29912 unsigned idx1 = 1; // cmp
29913 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // labl
29914 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); //
29915 {
29916 C2_MacroAssembler _masm(&cbuf);
29917
29918#line 12690 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
29919
29920 Label* L = opnd_array(3)->label();
29921 ___masm. jcc((Assembler::Condition)(opnd_array(1)->ccode()), *L, false); // Always long jump
29922
29923#line 29923 "ad_x86.cpp"
29924 }
29925}
29926
29927uint jmpConUNode::size(PhaseRegAlloc *ra_) const {
29928 assert(VerifyOops || MachNode::size(ra_) <= 6, "bad fixed size")do { if (!(VerifyOops || MachNode::size(ra_) <= 6)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 29927, "assert(" "VerifyOops || MachNode::size(ra_) <= 6"
") failed", "bad fixed size"); ::breakpoint(); } } while (0);
29929 return (VerifyOops ? MachNode::size(ra_) : 6);
29930}
29931
29932void jmpConUCFNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29933 cbuf.set_insts_mark();
29934 // Start at oper_input_base() and count operands
29935 unsigned idx0 = 1;
29936 unsigned idx1 = 1; // cmp
29937 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // labl
29938 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); //
29939 {
29940 C2_MacroAssembler _masm(&cbuf);
29941
29942#line 12704 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
29943
29944 Label* L = opnd_array(3)->label();
29945 ___masm. jcc((Assembler::Condition)(opnd_array(1)->ccode()), *L, false); // Always long jump
29946
29947#line 29947 "ad_x86.cpp"
29948 }
29949}
29950
29951uint jmpConUCFNode::size(PhaseRegAlloc *ra_) const {
29952 assert(VerifyOops || MachNode::size(ra_) <= 6, "bad fixed size")do { if (!(VerifyOops || MachNode::size(ra_) <= 6)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 29951, "assert(" "VerifyOops || MachNode::size(ra_) <= 6"
") failed", "bad fixed size"); ::breakpoint(); } } while (0);
29953 return (VerifyOops ? MachNode::size(ra_) : 6);
29954}
29955
29956void jmpConUCF2Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29957 cbuf.set_insts_mark();
29958 // Start at oper_input_base() and count operands
29959 unsigned idx0 = 1;
29960 unsigned idx1 = 1; // cmp
29961 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // labl
29962 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); //
29963 {
29964 C2_MacroAssembler _masm(&cbuf);
29965
29966#line 12726 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
29967
29968 Label* l = opnd_array(3)->label();
29969 if (opnd_array(1)->ccode()== Assembler::notEqual) {
29970 ___masm. jcc(Assembler::parity, *l, false);
29971 ___masm. jcc(Assembler::notEqual, *l, false);
29972 } else if (opnd_array(1)->ccode()== Assembler::equal) {
29973 Label done;
29974 ___masm. jccb(Assembler::parity, done)jccb_0(Assembler::parity, done, "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 12733);
29975 ___masm. jcc(Assembler::equal, *l, false);
29976 ___masm. bind(done);
29977 } else {
29978 ShouldNotReachHere()do { (*g_assert_poison) = 'X';; report_should_not_reach_here(
"/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 12737); ::breakpoint(); } while (0);
29979 }
29980
29981#line 29981 "ad_x86.cpp"
29982 }
29983}
29984
29985void partialSubtypeCheckNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
29986 cbuf.set_insts_mark();
29987 // Start at oper_input_base() and count operands
29988 unsigned idx0 = 1;
29989 unsigned idx1 = 1; // sub
29990 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // super
29991 {
29992
29993#line 2105 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
29994
29995 Register Rrdi = as_Register(RDI_enc); // result register
29996 Register Rrax = as_Register(RAX_enc); // super class
29997 Register Rrcx = as_Register(RCX_enc); // killed
29998 Register Rrsi = as_Register(RSI_enc); // sub class
29999 Label miss;
30000 const bool set_cond_codes = true;
30001
30002 MacroAssembler _masm(&cbuf);
30003 ___masm. check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi,
30004 NULL__null, &miss,
30005 /*set_cond_codes:*/ true);
30006 if ((0x1 /*primary()*/)) {
30007 ___masm. xorptr(Rrdi, Rrdi);
30008 }
30009 ___masm. bind(miss);
30010
30011#line 30011 "ad_x86.cpp"
30012 }
30013}
30014
30015void partialSubtypeCheck_vs_ZeroNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
30016 cbuf.set_insts_mark();
30017 // Start at oper_input_base() and count operands
30018 unsigned idx0 = 1;
30019 unsigned idx1 = 1; // sub
30020 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // super
30021 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // zero
30022 {
30023
30024#line 2105 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
30025
30026 Register Rrdi = as_Register(RDI_enc); // result register
30027 Register Rrax = as_Register(RAX_enc); // super class
30028 Register Rrcx = as_Register(RCX_enc); // killed
30029 Register Rrsi = as_Register(RSI_enc); // sub class
30030 Label miss;
30031 const bool set_cond_codes = true;
30032
30033 MacroAssembler _masm(&cbuf);
30034 ___masm. check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi,
30035 NULL__null, &miss,
30036 /*set_cond_codes:*/ true);
30037 if ((0x0 /*primary()*/)) {
30038 ___masm. xorptr(Rrdi, Rrdi);
30039 }
30040 ___masm. bind(miss);
30041
30042#line 30042 "ad_x86.cpp"
30043 }
30044}
30045
30046void jmpDir_shortNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
30047 cbuf.set_insts_mark();
30048 // Start at oper_input_base() and count operands
30049 unsigned idx0 = 1;
30050 unsigned idx1 = 1; //
30051 {
30052 C2_MacroAssembler _masm(&cbuf);
30053
30054#line 12814 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
30055
30056 Label* L = opnd_array(1)->label();
30057 ___masm. jmpb(*L)jmpb_0(*L, "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 12816);
30058
30059#line 30059 "ad_x86.cpp"
30060 }
30061}
30062
30063uint jmpDir_shortNode::size(PhaseRegAlloc *ra_) const {
30064 assert(VerifyOops || MachNode::size(ra_) <= 2, "bad fixed size")do { if (!(VerifyOops || MachNode::size(ra_) <= 2)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 30063, "assert(" "VerifyOops || MachNode::size(ra_) <= 2"
") failed", "bad fixed size"); ::breakpoint(); } } while (0);
30065 return (VerifyOops ? MachNode::size(ra_) : 2);
30066}
30067
30068void jmpCon_shortNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
30069 cbuf.set_insts_mark();
30070 // Start at oper_input_base() and count operands
30071 unsigned idx0 = 1;
30072 unsigned idx1 = 1; // cr
30073 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // labl
30074 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); //
30075 {
30076 C2_MacroAssembler _masm(&cbuf);
30077
30078#line 12830 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
30079
30080 Label* L = opnd_array(3)->label();
30081 ___masm. jccb((Assembler::Condition)(opnd_array(1)->ccode()), *L)jccb_0((Assembler::Condition)(opnd_array(1)->ccode()), *L,
"/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 12832);
30082
30083#line 30083 "ad_x86.cpp"
30084 }
30085}
30086
30087uint jmpCon_shortNode::size(PhaseRegAlloc *ra_) const {
30088 assert(VerifyOops || MachNode::size(ra_) <= 2, "bad fixed size")do { if (!(VerifyOops || MachNode::size(ra_) <= 2)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 30087, "assert(" "VerifyOops || MachNode::size(ra_) <= 2"
") failed", "bad fixed size"); ::breakpoint(); } } while (0);
30089 return (VerifyOops ? MachNode::size(ra_) : 2);
30090}
30091
30092void jmpLoopEnd_shortNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
30093 cbuf.set_insts_mark();
30094 // Start at oper_input_base() and count operands
30095 unsigned idx0 = 1;
30096 unsigned idx1 = 1; // cr
30097 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // labl
30098 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); //
30099 {
30100 C2_MacroAssembler _masm(&cbuf);
30101
30102#line 12846 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
30103
30104 Label* L = opnd_array(3)->label();
30105 ___masm. jccb((Assembler::Condition)(opnd_array(1)->ccode()), *L)jccb_0((Assembler::Condition)(opnd_array(1)->ccode()), *L,
"/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 12848);
30106
30107#line 30107 "ad_x86.cpp"
30108 }
30109}
30110
30111uint jmpLoopEnd_shortNode::size(PhaseRegAlloc *ra_) const {
30112 assert(VerifyOops || MachNode::size(ra_) <= 2, "bad fixed size")do { if (!(VerifyOops || MachNode::size(ra_) <= 2)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 30111, "assert(" "VerifyOops || MachNode::size(ra_) <= 2"
") failed", "bad fixed size"); ::breakpoint(); } } while (0);
30113 return (VerifyOops ? MachNode::size(ra_) : 2);
30114}
30115
30116void jmpLoopEndU_shortNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
30117 cbuf.set_insts_mark();
30118 // Start at oper_input_base() and count operands
30119 unsigned idx0 = 1;
30120 unsigned idx1 = 1; // cmp
30121 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // labl
30122 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); //
30123 {
30124 C2_MacroAssembler _masm(&cbuf);
30125
30126#line 12862 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
30127
30128 Label* L = opnd_array(3)->label();
30129 ___masm. jccb((Assembler::Condition)(opnd_array(1)->ccode()), *L)jccb_0((Assembler::Condition)(opnd_array(1)->ccode()), *L,
"/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 12864);
30130
30131#line 30131 "ad_x86.cpp"
30132 }
30133}
30134
30135uint jmpLoopEndU_shortNode::size(PhaseRegAlloc *ra_) const {
30136 assert(VerifyOops || MachNode::size(ra_) <= 2, "bad fixed size")do { if (!(VerifyOops || MachNode::size(ra_) <= 2)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 30135, "assert(" "VerifyOops || MachNode::size(ra_) <= 2"
") failed", "bad fixed size"); ::breakpoint(); } } while (0);
30137 return (VerifyOops ? MachNode::size(ra_) : 2);
30138}
30139
30140void jmpLoopEndUCF_shortNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
30141 cbuf.set_insts_mark();
30142 // Start at oper_input_base() and count operands
30143 unsigned idx0 = 1;
30144 unsigned idx1 = 1; // cmp
30145 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // labl
30146 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); //
30147 {
30148 C2_MacroAssembler _masm(&cbuf);
30149
30150#line 12877 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
30151
30152 Label* L = opnd_array(3)->label();
30153 ___masm. jccb((Assembler::Condition)(opnd_array(1)->ccode()), *L)jccb_0((Assembler::Condition)(opnd_array(1)->ccode()), *L,
"/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 12879);
30154
30155#line 30155 "ad_x86.cpp"
30156 }
30157}
30158
30159uint jmpLoopEndUCF_shortNode::size(PhaseRegAlloc *ra_) const {
30160 assert(VerifyOops || MachNode::size(ra_) <= 2, "bad fixed size")do { if (!(VerifyOops || MachNode::size(ra_) <= 2)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 30159, "assert(" "VerifyOops || MachNode::size(ra_) <= 2"
") failed", "bad fixed size"); ::breakpoint(); } } while (0);
30161 return (VerifyOops ? MachNode::size(ra_) : 2);
30162}
30163
30164void jmpConU_shortNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
30165 cbuf.set_insts_mark();
30166 // Start at oper_input_base() and count operands
30167 unsigned idx0 = 1;
30168 unsigned idx1 = 1; // cmp
30169 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // labl
30170 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); //
30171 {
30172 C2_MacroAssembler _masm(&cbuf);
30173
30174#line 12893 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
30175
30176 Label* L = opnd_array(3)->label();
30177 ___masm. jccb((Assembler::Condition)(opnd_array(1)->ccode()), *L)jccb_0((Assembler::Condition)(opnd_array(1)->ccode()), *L,
"/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 12895);
30178
30179#line 30179 "ad_x86.cpp"
30180 }
30181}
30182
30183uint jmpConU_shortNode::size(PhaseRegAlloc *ra_) const {
30184 assert(VerifyOops || MachNode::size(ra_) <= 2, "bad fixed size")do { if (!(VerifyOops || MachNode::size(ra_) <= 2)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 30183, "assert(" "VerifyOops || MachNode::size(ra_) <= 2"
") failed", "bad fixed size"); ::breakpoint(); } } while (0);
30185 return (VerifyOops ? MachNode::size(ra_) : 2);
30186}
30187
30188void jmpConUCF_shortNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
30189 cbuf.set_insts_mark();
30190 // Start at oper_input_base() and count operands
30191 unsigned idx0 = 1;
30192 unsigned idx1 = 1; // cmp
30193 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // labl
30194 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); //
30195 {
30196 C2_MacroAssembler _masm(&cbuf);
30197
30198#line 12908 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
30199
30200 Label* L = opnd_array(3)->label();
30201 ___masm. jccb((Assembler::Condition)(opnd_array(1)->ccode()), *L)jccb_0((Assembler::Condition)(opnd_array(1)->ccode()), *L,
"/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 12910);
30202
30203#line 30203 "ad_x86.cpp"
30204 }
30205}
30206
30207uint jmpConUCF_shortNode::size(PhaseRegAlloc *ra_) const {
30208 assert(VerifyOops || MachNode::size(ra_) <= 2, "bad fixed size")do { if (!(VerifyOops || MachNode::size(ra_) <= 2)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 30207, "assert(" "VerifyOops || MachNode::size(ra_) <= 2"
") failed", "bad fixed size"); ::breakpoint(); } } while (0);
30209 return (VerifyOops ? MachNode::size(ra_) : 2);
30210}
30211
30212void jmpConUCF2_shortNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
30213 cbuf.set_insts_mark();
30214 // Start at oper_input_base() and count operands
30215 unsigned idx0 = 1;
30216 unsigned idx1 = 1; // cmp
30217 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // labl
30218 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); //
30219 {
30220 C2_MacroAssembler _masm(&cbuf);
30221
30222#line 12932 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
30223
30224 Label* l = opnd_array(3)->label();
30225 if (opnd_array(1)->ccode()== Assembler::notEqual) {
30226 ___masm. jccb(Assembler::parity, *l)jccb_0(Assembler::parity, *l, "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 12935);
30227 ___masm. jccb(Assembler::notEqual, *l)jccb_0(Assembler::notEqual, *l, "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 12936);
30228 } else if (opnd_array(1)->ccode()== Assembler::equal) {
30229 Label done;
30230 ___masm. jccb(Assembler::parity, done)jccb_0(Assembler::parity, done, "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 12939);
30231 ___masm. jccb(Assembler::equal, *l)jccb_0(Assembler::equal, *l, "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 12940);
30232 ___masm. bind(done);
30233 } else {
30234 ShouldNotReachHere()do { (*g_assert_poison) = 'X';; report_should_not_reach_here(
"/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 12943); ::breakpoint(); } while (0);
30235 }
30236
30237#line 30237 "ad_x86.cpp"
30238 }
30239}
30240
30241uint jmpConUCF2_shortNode::size(PhaseRegAlloc *ra_) const {
30242 assert(VerifyOops || MachNode::size(ra_) <= 4, "bad fixed size")do { if (!(VerifyOops || MachNode::size(ra_) <= 4)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 30241, "assert(" "VerifyOops || MachNode::size(ra_) <= 4"
") failed", "bad fixed size"); ::breakpoint(); } } while (0);
30243 return (VerifyOops ? MachNode::size(ra_) : 4);
30244}
30245
30246void cmpFastLockRTMNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
30247 cbuf.set_insts_mark();
30248 // Start at oper_input_base() and count operands
30249 unsigned idx0 = 1;
30250 unsigned idx1 = 1; // object
30251 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // box
30252 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
30253 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // scr
30254 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // cx1
30255 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // cx2
30256 {
30257 C2_MacroAssembler _masm(&cbuf);
30258
30259#line 12959 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
30260
30261 ___masm. fast_lock(opnd_array(1)->as_Register(ra_,this,idx1)/* object */, opnd_array(2)->as_Register(ra_,this,idx2)/* box */, opnd_array(3)->as_Register(ra_,this,idx3)/* tmp */,
30262 opnd_array(4)->as_Register(ra_,this,idx4)/* scr */, opnd_array(5)->as_Register(ra_,this,idx5)/* cx1 */, opnd_array(6)->as_Register(ra_,this,idx6)/* cx2 */,
30263 _rtm_counters, _stack_rtm_counters,
30264 ((Method*)(ra_->C->method()->constant_encoding()))->method_data(),
30265 true, ra_->C->profile_rtm());
30266
30267#line 30267 "ad_x86.cpp"
30268 }
30269}
30270
30271void cmpFastLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
30272 cbuf.set_insts_mark();
30273 // Start at oper_input_base() and count operands
30274 unsigned idx0 = 1;
30275 unsigned idx1 = 1; // object
30276 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // box
30277 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
30278 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // scr
30279 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // cx1
30280 {
30281 C2_MacroAssembler _masm(&cbuf);
30282
30283#line 12975 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
30284
30285 ___masm. fast_lock(opnd_array(1)->as_Register(ra_,this,idx1)/* object */, opnd_array(2)->as_Register(ra_,this,idx2)/* box */, opnd_array(3)->as_Register(ra_,this,idx3)/* tmp */,
30286 opnd_array(4)->as_Register(ra_,this,idx4)/* scr */, opnd_array(5)->as_Register(ra_,this,idx5)/* cx1 */, noreg, NULL__null, NULL__null, NULL__null, false, false);
30287
30288#line 30288 "ad_x86.cpp"
30289 }
30290}
30291
30292void cmpFastUnlockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
30293 cbuf.set_insts_mark();
30294 // Start at oper_input_base() and count operands
30295 unsigned idx0 = 1;
30296 unsigned idx1 = 1; // object
30297 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // box
30298 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
30299 {
30300 C2_MacroAssembler _masm(&cbuf);
30301
30302#line 12987 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
30303
30304 ___masm. fast_unlock(opnd_array(1)->as_Register(ra_,this,idx1)/* object */, opnd_array(2)->as_Register(ra_,this,idx2)/* box */, opnd_array(3)->as_Register(ra_,this,idx3)/* tmp */, ra_->C->use_rtm());
30305
30306#line 30306 "ad_x86.cpp"
30307 }
30308}
30309
30310void safePoint_poll_tlsNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
30311 cbuf.set_insts_mark();
30312 // Start at oper_input_base() and count operands
30313 unsigned idx0 = 5;
30314 unsigned idx1 = 5; // cr
30315 {
30316 C2_MacroAssembler _masm(&cbuf);
30317
30318#line 13005 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
30319
30320 ___masm. relocate(relocInfo::poll_type);
30321 address pre_pc = ___masm. pc();
30322 ___masm. testl(rax, Address(opnd_array(1)->as_Register(ra_,this,idx1)/* poll */, 0));
30323 assert(nativeInstruction_at(pre_pc)->is_safepoint_poll(), "must emit test %%eax [reg]")do { if (!(nativeInstruction_at(pre_pc)->is_safepoint_poll
())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 13009, "assert(" "nativeInstruction_at(pre_pc)->is_safepoint_poll()"
") failed", "must emit test %%eax [reg]"); ::breakpoint(); }
} while (0);
30324
30325#line 30325 "ad_x86.cpp"
30326 }
30327}
30328
30329uint safePoint_poll_tlsNode::size(PhaseRegAlloc *ra_) const {
30330 assert(VerifyOops || MachNode::size(ra_) <= 4, "bad fixed size")do { if (!(VerifyOops || MachNode::size(ra_) <= 4)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 30329, "assert(" "VerifyOops || MachNode::size(ra_) <= 4"
") failed", "bad fixed size"); ::breakpoint(); } } while (0);
30331 return (VerifyOops ? MachNode::size(ra_) : 4);
30332}
30333
30334void CallStaticJavaDirectNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
30335 cbuf.set_insts_mark();
30336 // Start at oper_input_base() and count operands
30337 unsigned idx0 = 1;
30338 unsigned idx1 = 1; //
30339 {
30340
30341#line 2123 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
30342
30343 debug_only(int off0 = cbuf.insts_size())int off0 = cbuf.insts_size();
30344 if (generate_vzeroupper(Compile::current())) {
30345 // Clear upper bits of YMM registers to avoid AVX <-> SSE transition penalty
30346 // Clear upper bits of YMM registers when current compiled code uses
30347 // wide vectors to avoid AVX <-> SSE transition penalty during call.
30348 MacroAssembler _masm(&cbuf);
30349 ___masm. vzeroupper();
30350 }
30351 debug_only(int off1 = cbuf.insts_size())int off1 = cbuf.insts_size();
30352 assert(off1 - off0 == clear_avx_size(), "correct size prediction")do { if (!(off1 - off0 == clear_avx_size())) { (*g_assert_poison
) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 2133, "assert(" "off1 - off0 == clear_avx_size()" ") failed"
, "correct size prediction"); ::breakpoint(); } } while (0);
30353
30354#line 30354 "ad_x86.cpp"
30355 }
30356 {
30357
30358#line 2157 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
30359
30360 // JAVA STATIC CALL
30361 // CALL to fixup routine. Fixup routine uses ScopeDesc info to
30362 // determine who we intended to call.
30363 cbuf.set_insts_mark();
30364 emit_d8(cbuf, (0xE8 /*primary()*/));
30365
30366 if (!_method) {
30367 emit_d32_reloc(cbuf, (int) (opnd_array(1)->method() - ((intptr_t) cbuf.insts_end()) - 4),
30368 runtime_call_Relocation::spec(),
30369 RELOC_DISP32Assembler::disp32_operand);
30370 } else {
30371 int method_index = resolved_method_index(cbuf);
30372 RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
30373 : static_call_Relocation::spec(method_index);
30374 emit_d32_reloc(cbuf, (int) (opnd_array(1)->method() - ((intptr_t) cbuf.insts_end()) - 4),
30375 rspec, RELOC_DISP32Assembler::disp32_operand);
30376 // Emit stubs for static call.
30377 address mark = cbuf.insts_mark();
30378 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf, mark);
30379 if (stub == NULL__null) {
30380 ciEnv::current()->record_failure("CodeCache is full");
30381 return;
30382 }
30383 }
30384
30385#line 30385 "ad_x86.cpp"
30386 }
30387 {
30388
30389#line 2588 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
30390
30391 if (VerifyStackAtCalls) {
30392 // Check that stack depth is unchanged: find majik cookie on stack
30393 int framesize = ra_->reg2offset_unchecked(OptoReg::add(ra_->_matcher._old_SP, -3*VMRegImpl::slots_per_word));
30394 C2_MacroAssembler _masm(&cbuf);
30395 Label L;
30396 ___masm. cmpptr(Address(rsp, framesize), (int32_t)0xbadb100d);
30397 ___masm. jccb(Assembler::equal, L)jccb_0(Assembler::equal, L, "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 2595);
30398 // Die if stack mismatch
30399 ___masm. int3();
30400 ___masm. bind(L);
30401 }
30402
30403#line 30403 "ad_x86.cpp"
30404 }
30405}
30406
30407void CallDynamicJavaDirectNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
30408 cbuf.set_insts_mark();
30409 // Start at oper_input_base() and count operands
30410 unsigned idx0 = 1;
30411 unsigned idx1 = 1; //
30412 {
30413
30414#line 2123 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
30415
30416 debug_only(int off0 = cbuf.insts_size())int off0 = cbuf.insts_size();
30417 if (generate_vzeroupper(Compile::current())) {
30418 // Clear upper bits of YMM registers to avoid AVX <-> SSE transition penalty
30419 // Clear upper bits of YMM registers when current compiled code uses
30420 // wide vectors to avoid AVX <-> SSE transition penalty during call.
30421 MacroAssembler _masm(&cbuf);
30422 ___masm. vzeroupper();
30423 }
30424 debug_only(int off1 = cbuf.insts_size())int off1 = cbuf.insts_size();
30425 assert(off1 - off0 == clear_avx_size(), "correct size prediction")do { if (!(off1 - off0 == clear_avx_size())) { (*g_assert_poison
) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 2133, "assert(" "off1 - off0 == clear_avx_size()" ") failed"
, "correct size prediction"); ::breakpoint(); } } while (0);
30426
30427#line 30427 "ad_x86.cpp"
30428 }
30429 {
30430
30431#line 2184 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
30432
30433 MacroAssembler _masm(&cbuf);
30434 ___masm. ic_call((address)opnd_array(1)->method(), resolved_method_index(cbuf));
30435
30436#line 30436 "ad_x86.cpp"
30437 }
30438 {
30439
30440#line 2588 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
30441
30442 if (VerifyStackAtCalls) {
30443 // Check that stack depth is unchanged: find majik cookie on stack
30444 int framesize = ra_->reg2offset_unchecked(OptoReg::add(ra_->_matcher._old_SP, -3*VMRegImpl::slots_per_word));
30445 C2_MacroAssembler _masm(&cbuf);
30446 Label L;
30447 ___masm. cmpptr(Address(rsp, framesize), (int32_t)0xbadb100d);
30448 ___masm. jccb(Assembler::equal, L)jccb_0(Assembler::equal, L, "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 2595);
30449 // Die if stack mismatch
30450 ___masm. int3();
30451 ___masm. bind(L);
30452 }
30453
30454#line 30454 "ad_x86.cpp"
30455 }
30456}
30457
30458void CallRuntimeDirectNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
30459 cbuf.set_insts_mark();
30460 // Start at oper_input_base() and count operands
30461 unsigned idx0 = 1;
30462 unsigned idx1 = 1; //
30463 {
30464
30465#line 2123 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
30466
30467 debug_only(int off0 = cbuf.insts_size())int off0 = cbuf.insts_size();
30468 if (generate_vzeroupper(Compile::current())) {
30469 // Clear upper bits of YMM registers to avoid AVX <-> SSE transition penalty
30470 // Clear upper bits of YMM registers when current compiled code uses
30471 // wide vectors to avoid AVX <-> SSE transition penalty during call.
30472 MacroAssembler _masm(&cbuf);
30473 ___masm. vzeroupper();
30474 }
30475 debug_only(int off1 = cbuf.insts_size())int off1 = cbuf.insts_size();
30476 assert(off1 - off0 == clear_avx_size(), "correct size prediction")do { if (!(off1 - off0 == clear_avx_size())) { (*g_assert_poison
) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 2133, "assert(" "off1 - off0 == clear_avx_size()" ") failed"
, "correct size prediction"); ::breakpoint(); } } while (0);
30477
30478#line 30478 "ad_x86.cpp"
30479 }
30480 {
30481
30482#line 2136 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
30483
30484 // No relocation needed
30485 MacroAssembler _masm(&cbuf);
30486 ___masm. mov64(r10, (int64_t) opnd_array(1)->method());
30487 ___masm. call(r10);
30488
30489#line 30489 "ad_x86.cpp"
30490 }
30491}
30492
30493void CallLeafDirectNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
30494 cbuf.set_insts_mark();
30495 // Start at oper_input_base() and count operands
30496 unsigned idx0 = 1;
30497 unsigned idx1 = 1; //
30498 {
30499
30500#line 2123 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
30501
30502 debug_only(int off0 = cbuf.insts_size())int off0 = cbuf.insts_size();
30503 if (generate_vzeroupper(Compile::current())) {
30504 // Clear upper bits of YMM registers to avoid AVX <-> SSE transition penalty
30505 // Clear upper bits of YMM registers when current compiled code uses
30506 // wide vectors to avoid AVX <-> SSE transition penalty during call.
30507 MacroAssembler _masm(&cbuf);
30508 ___masm. vzeroupper();
30509 }
30510 debug_only(int off1 = cbuf.insts_size())int off1 = cbuf.insts_size();
30511 assert(off1 - off0 == clear_avx_size(), "correct size prediction")do { if (!(off1 - off0 == clear_avx_size())) { (*g_assert_poison
) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 2133, "assert(" "off1 - off0 == clear_avx_size()" ") failed"
, "correct size prediction"); ::breakpoint(); } } while (0);
30512
30513#line 30513 "ad_x86.cpp"
30514 }
30515 {
30516
30517#line 2136 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
30518
30519 // No relocation needed
30520 MacroAssembler _masm(&cbuf);
30521 ___masm. mov64(r10, (int64_t) opnd_array(1)->method());
30522 ___masm. call(r10);
30523
30524#line 30524 "ad_x86.cpp"
30525 }
30526}
30527
30528void CallLeafDirectVectorNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
30529 cbuf.set_insts_mark();
30530 // Start at oper_input_base() and count operands
30531 unsigned idx0 = 1;
30532 unsigned idx1 = 1; //
30533 {
30534
30535#line 2136 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
30536
30537 // No relocation needed
30538 MacroAssembler _masm(&cbuf);
30539 ___masm. mov64(r10, (int64_t) opnd_array(1)->method());
30540 ___masm. call(r10);
30541
30542#line 30542 "ad_x86.cpp"
30543 }
30544}
30545
30546void CallNativeDirectNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
30547 cbuf.set_insts_mark();
30548 // Start at oper_input_base() and count operands
30549 unsigned idx0 = 1;
30550 unsigned idx1 = 1; //
30551 {
30552
30553#line 2123 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
30554
30555 debug_only(int off0 = cbuf.insts_size())int off0 = cbuf.insts_size();
30556 if (generate_vzeroupper(Compile::current())) {
30557 // Clear upper bits of YMM registers to avoid AVX <-> SSE transition penalty
30558 // Clear upper bits of YMM registers when current compiled code uses
30559 // wide vectors to avoid AVX <-> SSE transition penalty during call.
30560 MacroAssembler _masm(&cbuf);
30561 ___masm. vzeroupper();
30562 }
30563 debug_only(int off1 = cbuf.insts_size())int off1 = cbuf.insts_size();
30564 assert(off1 - off0 == clear_avx_size(), "correct size prediction")do { if (!(off1 - off0 == clear_avx_size())) { (*g_assert_poison
) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 2133, "assert(" "off1 - off0 == clear_avx_size()" ") failed"
, "correct size prediction"); ::breakpoint(); } } while (0);
30565
30566#line 30566 "ad_x86.cpp"
30567 }
30568 {
30569
30570#line 2136 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
30571
30572 // No relocation needed
30573 MacroAssembler _masm(&cbuf);
30574 ___masm. mov64(r10, (int64_t) opnd_array(1)->method());
30575 ___masm. call(r10);
30576
30577#line 30577 "ad_x86.cpp"
30578 }
30579}
30580
30581void CallLeafNoFPDirectNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
30582 cbuf.set_insts_mark();
30583 // Start at oper_input_base() and count operands
30584 unsigned idx0 = 1;
30585 unsigned idx1 = 1; //
30586 {
30587
30588#line 2123 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
30589
30590 debug_only(int off0 = cbuf.insts_size())int off0 = cbuf.insts_size();
30591 if (generate_vzeroupper(Compile::current())) {
30592 // Clear upper bits of YMM registers to avoid AVX <-> SSE transition penalty
30593 // Clear upper bits of YMM registers when current compiled code uses
30594 // wide vectors to avoid AVX <-> SSE transition penalty during call.
30595 MacroAssembler _masm(&cbuf);
30596 ___masm. vzeroupper();
30597 }
30598 debug_only(int off1 = cbuf.insts_size())int off1 = cbuf.insts_size();
30599 assert(off1 - off0 == clear_avx_size(), "correct size prediction")do { if (!(off1 - off0 == clear_avx_size())) { (*g_assert_poison
) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 2133, "assert(" "off1 - off0 == clear_avx_size()" ") failed"
, "correct size prediction"); ::breakpoint(); } } while (0);
30600
30601#line 30601 "ad_x86.cpp"
30602 }
30603 {
30604
30605#line 2136 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
30606
30607 // No relocation needed
30608 MacroAssembler _masm(&cbuf);
30609 ___masm. mov64(r10, (int64_t) opnd_array(1)->method());
30610 ___masm. call(r10);
30611
30612#line 30612 "ad_x86.cpp"
30613 }
30614}
30615
30616void RetNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
30617 cbuf.set_insts_mark();
30618 // Start at oper_input_base() and count operands
30619 unsigned idx0 = 5;
30620 unsigned idx1 = 5; //
30621 {
30622 C2_MacroAssembler _masm(&cbuf);
30623
30624#line 13116 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
30625
30626 ___masm. ret(0);
30627
30628#line 30628 "ad_x86.cpp"
30629 }
30630}
30631
30632void TailCalljmpIndNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
30633 cbuf.set_insts_mark();
30634 // Start at oper_input_base() and count operands
30635 unsigned idx0 = 5;
30636 unsigned idx1 = 5; // method_ptr
30637 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); //
30638 {
30639 C2_MacroAssembler _masm(&cbuf);
30640
30641#line 13132 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
30642
30643 ___masm. jmp(opnd_array(1)->as_Register(ra_,this,idx1)/* jump_target */);
30644
30645#line 30645 "ad_x86.cpp"
30646 }
30647}
30648
30649void tailjmpIndNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
30650 cbuf.set_insts_mark();
30651 // Start at oper_input_base() and count operands
30652 unsigned idx0 = 5;
30653 unsigned idx1 = 5; // ex_oop
30654 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); //
30655 {
30656 C2_MacroAssembler _masm(&cbuf);
30657
30658#line 13147 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
30659
30660 ___masm. popq(as_Register(RDX_enc));
30661 ___masm. jmp(opnd_array(1)->as_Register(ra_,this,idx1)/* jump_target */);
30662
30663#line 30663 "ad_x86.cpp"
30664 }
30665}
30666
30667void CreateExceptionNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
30668 cbuf.set_insts_mark();
30669 // Start at oper_input_base() and count operands
30670 unsigned idx0 = 1;
30671 unsigned idx1 = 1; //
30672 // User did not define which encode class to use.
30673}
30674
30675uint CreateExceptionNode::size(PhaseRegAlloc *ra_) const {
30676 assert(VerifyOops || MachNode::size(ra_) <= 0, "bad fixed size")do { if (!(VerifyOops || MachNode::size(ra_) <= 0)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 30675, "assert(" "VerifyOops || MachNode::size(ra_) <= 0"
") failed", "bad fixed size"); ::breakpoint(); } } while (0);
30677 return (VerifyOops ? MachNode::size(ra_) : 0);
30678}
30679
30680void RethrowExceptionNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
30681 cbuf.set_insts_mark();
30682 // Start at oper_input_base() and count operands
30683 unsigned idx0 = 5;
30684 unsigned idx1 = 5; //
30685 {
30686
30687#line 2723 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
30688
30689 cbuf.set_insts_mark();
30690 emit_opcode(cbuf, 0xE9); // jmp entry
30691 emit_d32_reloc(cbuf,
30692 (int) (OptoRuntime::rethrow_stub() - cbuf.insts_end() - 4),
30693 runtime_call_Relocation::spec(),
30694 RELOC_DISP32Assembler::disp32_operand);
30695
30696#line 30696 "ad_x86.cpp"
30697 }
30698}
30699
30700void tlsLoadPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
30701 cbuf.set_insts_mark();
30702 // Start at oper_input_base() and count operands
30703 unsigned idx0 = 1;
30704 unsigned idx1 = 1; //
30705 // User did not define which encode class to use.
30706}
30707
30708uint tlsLoadPNode::size(PhaseRegAlloc *ra_) const {
30709 assert(VerifyOops || MachNode::size(ra_) <= 0, "bad fixed size")do { if (!(VerifyOops || MachNode::size(ra_) <= 0)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 30708, "assert(" "VerifyOops || MachNode::size(ra_) <= 0"
") failed", "bad fixed size"); ::breakpoint(); } } while (0);
30710 return (VerifyOops ? MachNode::size(ra_) : 0);
30711}
30712
30713void ShouldNotReachHereNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
30714 cbuf.set_insts_mark();
30715 // Start at oper_input_base() and count operands
30716 unsigned idx0 = 5;
30717 unsigned idx1 = 5; //
30718 {
30719 C2_MacroAssembler _masm(&cbuf);
30720
30721#line 2769 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
30722
30723 if (is_reachable()) {
30724 ___masm. stop(_halt_reason);
30725 }
30726
30727#line 30727 "ad_x86.cpp"
30728 }
30729}
30730
30731void setMaskNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
30732 cbuf.set_insts_mark();
30733 // Start at oper_input_base() and count operands
30734 unsigned idx0 = 1;
30735 unsigned idx1 = 1; // src
30736 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
30737 {
30738 C2_MacroAssembler _masm(&cbuf);
30739
30740#line 2788 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
30741
30742 ___masm. setvectmask(opnd_array(2)->as_Register(ra_,this,idx2)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */, as_KRegister(K1_enc));
30743
30744#line 30744 "ad_x86.cpp"
30745 }
30746}
30747
30748void addF_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
30749 cbuf.set_insts_mark();
30750 // Start at oper_input_base() and count operands
30751 unsigned idx0 = 1;
30752 unsigned idx1 = 1; // dst
30753 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
30754 {
30755 C2_MacroAssembler _masm(&cbuf);
30756
30757#line 2802 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
30758
30759 ___masm. addss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
30760
30761#line 30761 "ad_x86.cpp"
30762 }
30763}
30764
30765void addF_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
30766 cbuf.set_insts_mark();
30767 // Start at oper_input_base() and count operands
30768 unsigned idx0 = 2;
30769 unsigned idx1 = 2; // dst
30770 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
30771 {
30772 C2_MacroAssembler _masm(&cbuf);
30773
30774#line 2814 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
30775
30776 ___masm. addss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
30777
30778#line 30778 "ad_x86.cpp"
30779 }
30780}
30781
30782void addF_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
30783 cbuf.set_insts_mark();
30784 // Start at oper_input_base() and count operands
30785 unsigned idx0 = 2;
30786 unsigned idx1 = 2; // src
30787 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
30788 {
30789 C2_MacroAssembler _masm(&cbuf);
30790
30791#line 2814 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
30792
30793 ___masm. addss(opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
30794
30795#line 30795 "ad_x86.cpp"
30796 }
30797}
30798
30799void addF_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
30800 cbuf.set_insts_mark();
30801 // Start at oper_input_base() and count operands
30802 unsigned idx0 = 1;
30803 unsigned idx1 = 1; // dst
30804 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
30805 {
30806 C2_MacroAssembler _masm(&cbuf);
30807
30808#line 2825 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
30809
30810 ___masm. addss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, InternalAddress(___masm. code()->consts()->start() + constant_offset()));
30811
30812#line 30812 "ad_x86.cpp"
30813 }
30814}
30815
30816void addF_immNode::eval_constant(Compile* C) {
30817 {
30818
30819#line 2826 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
30820 _constant = C->output()->constant_table().add(this, opnd_array(2));
30821#line 30821 "ad_x86.cpp"
30822 }
30823}
30824void addF_reg_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
30825 cbuf.set_insts_mark();
30826 // Start at oper_input_base() and count operands
30827 unsigned idx0 = 1;
30828 unsigned idx1 = 1; // src1
30829 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
30830 {
30831 C2_MacroAssembler _masm(&cbuf);
30832
30833#line 2837 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
30834
30835 ___masm. vaddss(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
30836
30837#line 30837 "ad_x86.cpp"
30838 }
30839}
30840
30841void addF_reg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
30842 cbuf.set_insts_mark();
30843 // Start at oper_input_base() and count operands
30844 unsigned idx0 = 2;
30845 unsigned idx1 = 2; // src1
30846 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
30847 {
30848 C2_MacroAssembler _masm(&cbuf);
30849
30850#line 2849 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
30851
30852 ___masm. vaddss(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
30853
30854#line 30854 "ad_x86.cpp"
30855 }
30856}
30857
30858void addF_reg_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
30859 cbuf.set_insts_mark();
30860 // Start at oper_input_base() and count operands
30861 unsigned idx0 = 2;
30862 unsigned idx1 = 2; // src2
30863 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src1
30864 {
30865 C2_MacroAssembler _masm(&cbuf);
30866
30867#line 2849 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
30868
30869 ___masm. vaddss(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src1 */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
30870
30871#line 30871 "ad_x86.cpp"
30872 }
30873}
30874
30875void addF_reg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
30876 cbuf.set_insts_mark();
30877 // Start at oper_input_base() and count operands
30878 unsigned idx0 = 1;
30879 unsigned idx1 = 1; // src
30880 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
30881 {
30882 C2_MacroAssembler _masm(&cbuf);
30883
30884#line 2861 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
30885
30886 ___masm. vaddss(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, InternalAddress(___masm. code()->consts()->start() + constant_offset()));
30887
30888#line 30888 "ad_x86.cpp"
30889 }
30890}
30891
30892void addF_reg_immNode::eval_constant(Compile* C) {
30893 {
30894
30895#line 2862 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
30896 _constant = C->output()->constant_table().add(this, opnd_array(2));
30897#line 30897 "ad_x86.cpp"
30898 }
30899}
30900void addD_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
30901 cbuf.set_insts_mark();
30902 // Start at oper_input_base() and count operands
30903 unsigned idx0 = 1;
30904 unsigned idx1 = 1; // dst
30905 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
30906 {
30907 C2_MacroAssembler _masm(&cbuf);
30908
30909#line 2873 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
30910
30911 ___masm. addsd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
30912
30913#line 30913 "ad_x86.cpp"
30914 }
30915}
30916
30917void addD_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
30918 cbuf.set_insts_mark();
30919 // Start at oper_input_base() and count operands
30920 unsigned idx0 = 2;
30921 unsigned idx1 = 2; // dst
30922 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
30923 {
30924 C2_MacroAssembler _masm(&cbuf);
30925
30926#line 2885 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
30927
30928 ___masm. addsd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
30929
30930#line 30930 "ad_x86.cpp"
30931 }
30932}
30933
30934void addD_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
30935 cbuf.set_insts_mark();
30936 // Start at oper_input_base() and count operands
30937 unsigned idx0 = 2;
30938 unsigned idx1 = 2; // src
30939 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
30940 {
30941 C2_MacroAssembler _masm(&cbuf);
30942
30943#line 2885 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
30944
30945 ___masm. addsd(opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
30946
30947#line 30947 "ad_x86.cpp"
30948 }
30949}
30950
30951void addD_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
30952 cbuf.set_insts_mark();
30953 // Start at oper_input_base() and count operands
30954 unsigned idx0 = 1;
30955 unsigned idx1 = 1; // dst
30956 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
30957 {
30958 C2_MacroAssembler _masm(&cbuf);
30959
30960#line 2896 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
30961
30962 ___masm. addsd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, InternalAddress(___masm. code()->consts()->start() + constant_offset()));
30963
30964#line 30964 "ad_x86.cpp"
30965 }
30966}
30967
30968void addD_immNode::eval_constant(Compile* C) {
30969 {
30970
30971#line 2897 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
30972 _constant = C->output()->constant_table().add(this, opnd_array(2));
30973#line 30973 "ad_x86.cpp"
30974 }
30975}
30976void addD_reg_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
30977 cbuf.set_insts_mark();
30978 // Start at oper_input_base() and count operands
30979 unsigned idx0 = 1;
30980 unsigned idx1 = 1; // src1
30981 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
30982 {
30983 C2_MacroAssembler _masm(&cbuf);
30984
30985#line 2908 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
30986
30987 ___masm. vaddsd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
30988
30989#line 30989 "ad_x86.cpp"
30990 }
30991}
30992
30993void addD_reg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
30994 cbuf.set_insts_mark();
30995 // Start at oper_input_base() and count operands
30996 unsigned idx0 = 2;
30997 unsigned idx1 = 2; // src1
30998 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
30999 {
31000 C2_MacroAssembler _masm(&cbuf);
31001
31002#line 2920 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31003
31004 ___masm. vaddsd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
31005
31006#line 31006 "ad_x86.cpp"
31007 }
31008}
31009
31010void addD_reg_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31011 cbuf.set_insts_mark();
31012 // Start at oper_input_base() and count operands
31013 unsigned idx0 = 2;
31014 unsigned idx1 = 2; // src2
31015 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src1
31016 {
31017 C2_MacroAssembler _masm(&cbuf);
31018
31019#line 2920 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31020
31021 ___masm. vaddsd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src1 */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
31022
31023#line 31023 "ad_x86.cpp"
31024 }
31025}
31026
31027void addD_reg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31028 cbuf.set_insts_mark();
31029 // Start at oper_input_base() and count operands
31030 unsigned idx0 = 1;
31031 unsigned idx1 = 1; // src
31032 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
31033 {
31034 C2_MacroAssembler _masm(&cbuf);
31035
31036#line 2932 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31037
31038 ___masm. vaddsd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, InternalAddress(___masm. code()->consts()->start() + constant_offset()));
31039
31040#line 31040 "ad_x86.cpp"
31041 }
31042}
31043
31044void addD_reg_immNode::eval_constant(Compile* C) {
31045 {
31046
31047#line 2933 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31048 _constant = C->output()->constant_table().add(this, opnd_array(2));
31049#line 31049 "ad_x86.cpp"
31050 }
31051}
31052void subF_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31053 cbuf.set_insts_mark();
31054 // Start at oper_input_base() and count operands
31055 unsigned idx0 = 1;
31056 unsigned idx1 = 1; // dst
31057 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
31058 {
31059 C2_MacroAssembler _masm(&cbuf);
31060
31061#line 2944 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31062
31063 ___masm. subss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
31064
31065#line 31065 "ad_x86.cpp"
31066 }
31067}
31068
31069void subF_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31070 cbuf.set_insts_mark();
31071 // Start at oper_input_base() and count operands
31072 unsigned idx0 = 2;
31073 unsigned idx1 = 2; // dst
31074 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
31075 {
31076 C2_MacroAssembler _masm(&cbuf);
31077
31078#line 2956 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31079
31080 ___masm. subss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
31081
31082#line 31082 "ad_x86.cpp"
31083 }
31084}
31085
31086void subF_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31087 cbuf.set_insts_mark();
31088 // Start at oper_input_base() and count operands
31089 unsigned idx0 = 1;
31090 unsigned idx1 = 1; // dst
31091 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
31092 {
31093 C2_MacroAssembler _masm(&cbuf);
31094
31095#line 2967 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31096
31097 ___masm. subss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, InternalAddress(___masm. code()->consts()->start() + constant_offset()));
31098
31099#line 31099 "ad_x86.cpp"
31100 }
31101}
31102
31103void subF_immNode::eval_constant(Compile* C) {
31104 {
31105
31106#line 2968 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31107 _constant = C->output()->constant_table().add(this, opnd_array(2));
31108#line 31108 "ad_x86.cpp"
31109 }
31110}
31111void subF_reg_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31112 cbuf.set_insts_mark();
31113 // Start at oper_input_base() and count operands
31114 unsigned idx0 = 1;
31115 unsigned idx1 = 1; // src1
31116 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
31117 {
31118 C2_MacroAssembler _masm(&cbuf);
31119
31120#line 2979 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31121
31122 ___masm. vsubss(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
31123
31124#line 31124 "ad_x86.cpp"
31125 }
31126}
31127
31128void subF_reg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31129 cbuf.set_insts_mark();
31130 // Start at oper_input_base() and count operands
31131 unsigned idx0 = 2;
31132 unsigned idx1 = 2; // src1
31133 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
31134 {
31135 C2_MacroAssembler _masm(&cbuf);
31136
31137#line 2991 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31138
31139 ___masm. vsubss(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
31140
31141#line 31141 "ad_x86.cpp"
31142 }
31143}
31144
31145void subF_reg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31146 cbuf.set_insts_mark();
31147 // Start at oper_input_base() and count operands
31148 unsigned idx0 = 1;
31149 unsigned idx1 = 1; // src
31150 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
31151 {
31152 C2_MacroAssembler _masm(&cbuf);
31153
31154#line 3003 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31155
31156 ___masm. vsubss(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, InternalAddress(___masm. code()->consts()->start() + constant_offset()));
31157
31158#line 31158 "ad_x86.cpp"
31159 }
31160}
31161
31162void subF_reg_immNode::eval_constant(Compile* C) {
31163 {
31164
31165#line 3004 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31166 _constant = C->output()->constant_table().add(this, opnd_array(2));
31167#line 31167 "ad_x86.cpp"
31168 }
31169}
31170void subD_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31171 cbuf.set_insts_mark();
31172 // Start at oper_input_base() and count operands
31173 unsigned idx0 = 1;
31174 unsigned idx1 = 1; // dst
31175 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
31176 {
31177 C2_MacroAssembler _masm(&cbuf);
31178
31179#line 3015 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31180
31181 ___masm. subsd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
31182
31183#line 31183 "ad_x86.cpp"
31184 }
31185}
31186
31187void subD_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31188 cbuf.set_insts_mark();
31189 // Start at oper_input_base() and count operands
31190 unsigned idx0 = 2;
31191 unsigned idx1 = 2; // dst
31192 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
31193 {
31194 C2_MacroAssembler _masm(&cbuf);
31195
31196#line 3027 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31197
31198 ___masm. subsd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
31199
31200#line 31200 "ad_x86.cpp"
31201 }
31202}
31203
31204void subD_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31205 cbuf.set_insts_mark();
31206 // Start at oper_input_base() and count operands
31207 unsigned idx0 = 1;
31208 unsigned idx1 = 1; // dst
31209 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
31210 {
31211 C2_MacroAssembler _masm(&cbuf);
31212
31213#line 3038 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31214
31215 ___masm. subsd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, InternalAddress(___masm. code()->consts()->start() + constant_offset()));
31216
31217#line 31217 "ad_x86.cpp"
31218 }
31219}
31220
31221void subD_immNode::eval_constant(Compile* C) {
31222 {
31223
31224#line 3039 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31225 _constant = C->output()->constant_table().add(this, opnd_array(2));
31226#line 31226 "ad_x86.cpp"
31227 }
31228}
31229void subD_reg_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31230 cbuf.set_insts_mark();
31231 // Start at oper_input_base() and count operands
31232 unsigned idx0 = 1;
31233 unsigned idx1 = 1; // src1
31234 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
31235 {
31236 C2_MacroAssembler _masm(&cbuf);
31237
31238#line 3050 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31239
31240 ___masm. vsubsd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
31241
31242#line 31242 "ad_x86.cpp"
31243 }
31244}
31245
31246void subD_reg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31247 cbuf.set_insts_mark();
31248 // Start at oper_input_base() and count operands
31249 unsigned idx0 = 2;
31250 unsigned idx1 = 2; // src1
31251 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
31252 {
31253 C2_MacroAssembler _masm(&cbuf);
31254
31255#line 3062 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31256
31257 ___masm. vsubsd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
31258
31259#line 31259 "ad_x86.cpp"
31260 }
31261}
31262
31263void subD_reg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31264 cbuf.set_insts_mark();
31265 // Start at oper_input_base() and count operands
31266 unsigned idx0 = 1;
31267 unsigned idx1 = 1; // src
31268 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
31269 {
31270 C2_MacroAssembler _masm(&cbuf);
31271
31272#line 3074 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31273
31274 ___masm. vsubsd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, InternalAddress(___masm. code()->consts()->start() + constant_offset()));
31275
31276#line 31276 "ad_x86.cpp"
31277 }
31278}
31279
31280void subD_reg_immNode::eval_constant(Compile* C) {
31281 {
31282
31283#line 3075 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31284 _constant = C->output()->constant_table().add(this, opnd_array(2));
31285#line 31285 "ad_x86.cpp"
31286 }
31287}
31288void mulF_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31289 cbuf.set_insts_mark();
31290 // Start at oper_input_base() and count operands
31291 unsigned idx0 = 1;
31292 unsigned idx1 = 1; // dst
31293 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
31294 {
31295 C2_MacroAssembler _masm(&cbuf);
31296
31297#line 3086 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31298
31299 ___masm. mulss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
31300
31301#line 31301 "ad_x86.cpp"
31302 }
31303}
31304
31305void mulF_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31306 cbuf.set_insts_mark();
31307 // Start at oper_input_base() and count operands
31308 unsigned idx0 = 2;
31309 unsigned idx1 = 2; // dst
31310 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
31311 {
31312 C2_MacroAssembler _masm(&cbuf);
31313
31314#line 3098 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31315
31316 ___masm. mulss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
31317
31318#line 31318 "ad_x86.cpp"
31319 }
31320}
31321
31322void mulF_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31323 cbuf.set_insts_mark();
31324 // Start at oper_input_base() and count operands
31325 unsigned idx0 = 2;
31326 unsigned idx1 = 2; // src
31327 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
31328 {
31329 C2_MacroAssembler _masm(&cbuf);
31330
31331#line 3098 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31332
31333 ___masm. mulss(opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
31334
31335#line 31335 "ad_x86.cpp"
31336 }
31337}
31338
31339void mulF_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31340 cbuf.set_insts_mark();
31341 // Start at oper_input_base() and count operands
31342 unsigned idx0 = 1;
31343 unsigned idx1 = 1; // dst
31344 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
31345 {
31346 C2_MacroAssembler _masm(&cbuf);
31347
31348#line 3109 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31349
31350 ___masm. mulss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, InternalAddress(___masm. code()->consts()->start() + constant_offset()));
31351
31352#line 31352 "ad_x86.cpp"
31353 }
31354}
31355
31356void mulF_immNode::eval_constant(Compile* C) {
31357 {
31358
31359#line 3110 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31360 _constant = C->output()->constant_table().add(this, opnd_array(2));
31361#line 31361 "ad_x86.cpp"
31362 }
31363}
31364void mulF_reg_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31365 cbuf.set_insts_mark();
31366 // Start at oper_input_base() and count operands
31367 unsigned idx0 = 1;
31368 unsigned idx1 = 1; // src1
31369 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
31370 {
31371 C2_MacroAssembler _masm(&cbuf);
31372
31373#line 3121 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31374
31375 ___masm. vmulss(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
31376
31377#line 31377 "ad_x86.cpp"
31378 }
31379}
31380
31381void mulF_reg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31382 cbuf.set_insts_mark();
31383 // Start at oper_input_base() and count operands
31384 unsigned idx0 = 2;
31385 unsigned idx1 = 2; // src1
31386 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
31387 {
31388 C2_MacroAssembler _masm(&cbuf);
31389
31390#line 3133 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31391
31392 ___masm. vmulss(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
31393
31394#line 31394 "ad_x86.cpp"
31395 }
31396}
31397
31398void mulF_reg_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31399 cbuf.set_insts_mark();
31400 // Start at oper_input_base() and count operands
31401 unsigned idx0 = 2;
31402 unsigned idx1 = 2; // src2
31403 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src1
31404 {
31405 C2_MacroAssembler _masm(&cbuf);
31406
31407#line 3133 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31408
31409 ___masm. vmulss(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src1 */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
31410
31411#line 31411 "ad_x86.cpp"
31412 }
31413}
31414
31415void mulF_reg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31416 cbuf.set_insts_mark();
31417 // Start at oper_input_base() and count operands
31418 unsigned idx0 = 1;
31419 unsigned idx1 = 1; // src
31420 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
31421 {
31422 C2_MacroAssembler _masm(&cbuf);
31423
31424#line 3145 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31425
31426 ___masm. vmulss(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, InternalAddress(___masm. code()->consts()->start() + constant_offset()));
31427
31428#line 31428 "ad_x86.cpp"
31429 }
31430}
31431
31432void mulF_reg_immNode::eval_constant(Compile* C) {
31433 {
31434
31435#line 3146 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31436 _constant = C->output()->constant_table().add(this, opnd_array(2));
31437#line 31437 "ad_x86.cpp"
31438 }
31439}
31440void mulD_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31441 cbuf.set_insts_mark();
31442 // Start at oper_input_base() and count operands
31443 unsigned idx0 = 1;
31444 unsigned idx1 = 1; // dst
31445 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
31446 {
31447 C2_MacroAssembler _masm(&cbuf);
31448
31449#line 3157 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31450
31451 ___masm. mulsd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
31452
31453#line 31453 "ad_x86.cpp"
31454 }
31455}
31456
31457void mulD_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31458 cbuf.set_insts_mark();
31459 // Start at oper_input_base() and count operands
31460 unsigned idx0 = 2;
31461 unsigned idx1 = 2; // dst
31462 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
31463 {
31464 C2_MacroAssembler _masm(&cbuf);
31465
31466#line 3169 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31467
31468 ___masm. mulsd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
31469
31470#line 31470 "ad_x86.cpp"
31471 }
31472}
31473
31474void mulD_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31475 cbuf.set_insts_mark();
31476 // Start at oper_input_base() and count operands
31477 unsigned idx0 = 2;
31478 unsigned idx1 = 2; // src
31479 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
31480 {
31481 C2_MacroAssembler _masm(&cbuf);
31482
31483#line 3169 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31484
31485 ___masm. mulsd(opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
31486
31487#line 31487 "ad_x86.cpp"
31488 }
31489}
31490
31491void mulD_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31492 cbuf.set_insts_mark();
31493 // Start at oper_input_base() and count operands
31494 unsigned idx0 = 1;
31495 unsigned idx1 = 1; // dst
31496 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
31497 {
31498 C2_MacroAssembler _masm(&cbuf);
31499
31500#line 3180 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31501
31502 ___masm. mulsd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, InternalAddress(___masm. code()->consts()->start() + constant_offset()));
31503
31504#line 31504 "ad_x86.cpp"
31505 }
31506}
31507
31508void mulD_immNode::eval_constant(Compile* C) {
31509 {
31510
31511#line 3181 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31512 _constant = C->output()->constant_table().add(this, opnd_array(2));
31513#line 31513 "ad_x86.cpp"
31514 }
31515}
31516void mulD_reg_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31517 cbuf.set_insts_mark();
31518 // Start at oper_input_base() and count operands
31519 unsigned idx0 = 1;
31520 unsigned idx1 = 1; // src1
31521 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
31522 {
31523 C2_MacroAssembler _masm(&cbuf);
31524
31525#line 3192 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31526
31527 ___masm. vmulsd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
31528
31529#line 31529 "ad_x86.cpp"
31530 }
31531}
31532
31533void mulD_reg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31534 cbuf.set_insts_mark();
31535 // Start at oper_input_base() and count operands
31536 unsigned idx0 = 2;
31537 unsigned idx1 = 2; // src1
31538 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
31539 {
31540 C2_MacroAssembler _masm(&cbuf);
31541
31542#line 3204 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31543
31544 ___masm. vmulsd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
31545
31546#line 31546 "ad_x86.cpp"
31547 }
31548}
31549
31550void mulD_reg_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31551 cbuf.set_insts_mark();
31552 // Start at oper_input_base() and count operands
31553 unsigned idx0 = 2;
31554 unsigned idx1 = 2; // src2
31555 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src1
31556 {
31557 C2_MacroAssembler _masm(&cbuf);
31558
31559#line 3204 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31560
31561 ___masm. vmulsd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src1 */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
31562
31563#line 31563 "ad_x86.cpp"
31564 }
31565}
31566
31567void mulD_reg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31568 cbuf.set_insts_mark();
31569 // Start at oper_input_base() and count operands
31570 unsigned idx0 = 1;
31571 unsigned idx1 = 1; // src
31572 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
31573 {
31574 C2_MacroAssembler _masm(&cbuf);
31575
31576#line 3216 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31577
31578 ___masm. vmulsd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, InternalAddress(___masm. code()->consts()->start() + constant_offset()));
31579
31580#line 31580 "ad_x86.cpp"
31581 }
31582}
31583
31584void mulD_reg_immNode::eval_constant(Compile* C) {
31585 {
31586
31587#line 3217 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31588 _constant = C->output()->constant_table().add(this, opnd_array(2));
31589#line 31589 "ad_x86.cpp"
31590 }
31591}
31592void divF_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31593 cbuf.set_insts_mark();
31594 // Start at oper_input_base() and count operands
31595 unsigned idx0 = 1;
31596 unsigned idx1 = 1; // dst
31597 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
31598 {
31599 C2_MacroAssembler _masm(&cbuf);
31600
31601#line 3228 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31602
31603 ___masm. divss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
31604
31605#line 31605 "ad_x86.cpp"
31606 }
31607}
31608
31609void divF_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31610 cbuf.set_insts_mark();
31611 // Start at oper_input_base() and count operands
31612 unsigned idx0 = 2;
31613 unsigned idx1 = 2; // dst
31614 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
31615 {
31616 C2_MacroAssembler _masm(&cbuf);
31617
31618#line 3240 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31619
31620 ___masm. divss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
31621
31622#line 31622 "ad_x86.cpp"
31623 }
31624}
31625
31626void divF_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31627 cbuf.set_insts_mark();
31628 // Start at oper_input_base() and count operands
31629 unsigned idx0 = 1;
31630 unsigned idx1 = 1; // dst
31631 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
31632 {
31633 C2_MacroAssembler _masm(&cbuf);
31634
31635#line 3251 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31636
31637 ___masm. divss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, InternalAddress(___masm. code()->consts()->start() + constant_offset()));
31638
31639#line 31639 "ad_x86.cpp"
31640 }
31641}
31642
31643void divF_immNode::eval_constant(Compile* C) {
31644 {
31645
31646#line 3252 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31647 _constant = C->output()->constant_table().add(this, opnd_array(2));
31648#line 31648 "ad_x86.cpp"
31649 }
31650}
31651void divF_reg_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31652 cbuf.set_insts_mark();
31653 // Start at oper_input_base() and count operands
31654 unsigned idx0 = 1;
31655 unsigned idx1 = 1; // src1
31656 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
31657 {
31658 C2_MacroAssembler _masm(&cbuf);
31659
31660#line 3263 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31661
31662 ___masm. vdivss(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
31663
31664#line 31664 "ad_x86.cpp"
31665 }
31666}
31667
31668void divF_reg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31669 cbuf.set_insts_mark();
31670 // Start at oper_input_base() and count operands
31671 unsigned idx0 = 2;
31672 unsigned idx1 = 2; // src1
31673 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
31674 {
31675 C2_MacroAssembler _masm(&cbuf);
31676
31677#line 3275 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31678
31679 ___masm. vdivss(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
31680
31681#line 31681 "ad_x86.cpp"
31682 }
31683}
31684
31685void divF_reg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31686 cbuf.set_insts_mark();
31687 // Start at oper_input_base() and count operands
31688 unsigned idx0 = 1;
31689 unsigned idx1 = 1; // src
31690 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
31691 {
31692 C2_MacroAssembler _masm(&cbuf);
31693
31694#line 3287 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31695
31696 ___masm. vdivss(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, InternalAddress(___masm. code()->consts()->start() + constant_offset()));
31697
31698#line 31698 "ad_x86.cpp"
31699 }
31700}
31701
31702void divF_reg_immNode::eval_constant(Compile* C) {
31703 {
31704
31705#line 3288 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31706 _constant = C->output()->constant_table().add(this, opnd_array(2));
31707#line 31707 "ad_x86.cpp"
31708 }
31709}
31710void divD_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31711 cbuf.set_insts_mark();
31712 // Start at oper_input_base() and count operands
31713 unsigned idx0 = 1;
31714 unsigned idx1 = 1; // dst
31715 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
31716 {
31717 C2_MacroAssembler _masm(&cbuf);
31718
31719#line 3299 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31720
31721 ___masm. divsd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
31722
31723#line 31723 "ad_x86.cpp"
31724 }
31725}
31726
31727void divD_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31728 cbuf.set_insts_mark();
31729 // Start at oper_input_base() and count operands
31730 unsigned idx0 = 2;
31731 unsigned idx1 = 2; // dst
31732 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
31733 {
31734 C2_MacroAssembler _masm(&cbuf);
31735
31736#line 3311 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31737
31738 ___masm. divsd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
31739
31740#line 31740 "ad_x86.cpp"
31741 }
31742}
31743
31744void divD_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31745 cbuf.set_insts_mark();
31746 // Start at oper_input_base() and count operands
31747 unsigned idx0 = 1;
31748 unsigned idx1 = 1; // dst
31749 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
31750 {
31751 C2_MacroAssembler _masm(&cbuf);
31752
31753#line 3322 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31754
31755 ___masm. divsd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, InternalAddress(___masm. code()->consts()->start() + constant_offset()));
31756
31757#line 31757 "ad_x86.cpp"
31758 }
31759}
31760
31761void divD_immNode::eval_constant(Compile* C) {
31762 {
31763
31764#line 3323 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31765 _constant = C->output()->constant_table().add(this, opnd_array(2));
31766#line 31766 "ad_x86.cpp"
31767 }
31768}
31769void divD_reg_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31770 cbuf.set_insts_mark();
31771 // Start at oper_input_base() and count operands
31772 unsigned idx0 = 1;
31773 unsigned idx1 = 1; // src1
31774 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
31775 {
31776 C2_MacroAssembler _masm(&cbuf);
31777
31778#line 3334 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31779
31780 ___masm. vdivsd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
31781
31782#line 31782 "ad_x86.cpp"
31783 }
31784}
31785
31786void divD_reg_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31787 cbuf.set_insts_mark();
31788 // Start at oper_input_base() and count operands
31789 unsigned idx0 = 2;
31790 unsigned idx1 = 2; // src1
31791 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
31792 {
31793 C2_MacroAssembler _masm(&cbuf);
31794
31795#line 3346 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31796
31797 ___masm. vdivsd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()));
31798
31799#line 31799 "ad_x86.cpp"
31800 }
31801}
31802
31803void divD_reg_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31804 cbuf.set_insts_mark();
31805 // Start at oper_input_base() and count operands
31806 unsigned idx0 = 1;
31807 unsigned idx1 = 1; // src
31808 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // con
31809 {
31810 C2_MacroAssembler _masm(&cbuf);
31811
31812#line 3358 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31813
31814 ___masm. vdivsd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, InternalAddress(___masm. code()->consts()->start() + constant_offset()));
31815
31816#line 31816 "ad_x86.cpp"
31817 }
31818}
31819
31820void divD_reg_immNode::eval_constant(Compile* C) {
31821 {
31822
31823#line 3359 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31824 _constant = C->output()->constant_table().add(this, opnd_array(2));
31825#line 31825 "ad_x86.cpp"
31826 }
31827}
31828void absF_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31829 cbuf.set_insts_mark();
31830 // Start at oper_input_base() and count operands
31831 unsigned idx0 = 1;
31832 unsigned idx1 = 1; // dst
31833 {
31834 C2_MacroAssembler _masm(&cbuf);
31835
31836#line 3369 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31837
31838 ___masm. andps(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, ExternalAddress(float_signmask()));
31839
31840#line 31840 "ad_x86.cpp"
31841 }
31842}
31843
31844void absF_reg_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31845 cbuf.set_insts_mark();
31846 // Start at oper_input_base() and count operands
31847 unsigned idx0 = 1;
31848 unsigned idx1 = 1; // src
31849 {
31850 C2_MacroAssembler _masm(&cbuf);
31851
31852#line 3380 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31853
31854 int vlen_enc = Assembler::AVX_128bit;
31855 ___masm. vandps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */,
31856 ExternalAddress(float_signmask()), vlen_enc);
31857
31858#line 31858 "ad_x86.cpp"
31859 }
31860}
31861
31862void absD_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31863 cbuf.set_insts_mark();
31864 // Start at oper_input_base() and count operands
31865 unsigned idx0 = 1;
31866 unsigned idx1 = 1; // dst
31867 {
31868 C2_MacroAssembler _masm(&cbuf);
31869
31870#line 3394 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31871
31872 ___masm. andpd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, ExternalAddress(double_signmask()));
31873
31874#line 31874 "ad_x86.cpp"
31875 }
31876}
31877
31878void absD_reg_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31879 cbuf.set_insts_mark();
31880 // Start at oper_input_base() and count operands
31881 unsigned idx0 = 1;
31882 unsigned idx1 = 1; // src
31883 {
31884 C2_MacroAssembler _masm(&cbuf);
31885
31886#line 3406 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31887
31888 int vlen_enc = Assembler::AVX_128bit;
31889 ___masm. vandpd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */,
31890 ExternalAddress(double_signmask()), vlen_enc);
31891
31892#line 31892 "ad_x86.cpp"
31893 }
31894}
31895
31896void negF_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31897 cbuf.set_insts_mark();
31898 // Start at oper_input_base() and count operands
31899 unsigned idx0 = 1;
31900 unsigned idx1 = 1; // dst
31901 {
31902 C2_MacroAssembler _masm(&cbuf);
31903
31904#line 3419 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31905
31906 ___masm. xorps(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, ExternalAddress(float_signflip()));
31907
31908#line 31908 "ad_x86.cpp"
31909 }
31910}
31911
31912void negF_reg_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31913 cbuf.set_insts_mark();
31914 // Start at oper_input_base() and count operands
31915 unsigned idx0 = 1;
31916 unsigned idx1 = 1; // src
31917 {
31918 C2_MacroAssembler _masm(&cbuf);
31919
31920#line 3430 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31921
31922 ___masm. vnegatess(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */,
31923 ExternalAddress(float_signflip()));
31924
31925#line 31925 "ad_x86.cpp"
31926 }
31927}
31928
31929void negD_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31930 cbuf.set_insts_mark();
31931 // Start at oper_input_base() and count operands
31932 unsigned idx0 = 1;
31933 unsigned idx1 = 1; // dst
31934 {
31935 C2_MacroAssembler _masm(&cbuf);
31936
31937#line 3443 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31938
31939 ___masm. xorpd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, ExternalAddress(double_signflip()));
31940
31941#line 31941 "ad_x86.cpp"
31942 }
31943}
31944
31945void negD_reg_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31946 cbuf.set_insts_mark();
31947 // Start at oper_input_base() and count operands
31948 unsigned idx0 = 1;
31949 unsigned idx1 = 1; // src
31950 {
31951 C2_MacroAssembler _masm(&cbuf);
31952
31953#line 3455 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31954
31955 ___masm. vnegatesd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */,
31956 ExternalAddress(double_signflip()));
31957
31958#line 31958 "ad_x86.cpp"
31959 }
31960}
31961
31962void sqrtF_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31963 cbuf.set_insts_mark();
31964 // Start at oper_input_base() and count operands
31965 unsigned idx0 = 1;
31966 unsigned idx1 = 1; // dst
31967 {
31968 C2_MacroAssembler _masm(&cbuf);
31969
31970#line 3468 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31971
31972 ___masm. sqrtss(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */);
31973
31974#line 31974 "ad_x86.cpp"
31975 }
31976}
31977
31978void sqrtD_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31979 cbuf.set_insts_mark();
31980 // Start at oper_input_base() and count operands
31981 unsigned idx0 = 1;
31982 unsigned idx1 = 1; // dst
31983 {
31984 C2_MacroAssembler _masm(&cbuf);
31985
31986#line 3480 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
31987
31988 ___masm. sqrtsd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */);
31989
31990#line 31990 "ad_x86.cpp"
31991 }
31992}
31993
31994void reinterpret_maskNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
31995 cbuf.set_insts_mark();
31996 // Start at oper_input_base() and count operands
31997 unsigned idx0 = 1;
31998 unsigned idx1 = 1; // dst
31999 {
32000 C2_MacroAssembler _masm(&cbuf);
32001
32002#line 3494 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
32003
32004 // empty
32005
32006#line 32006 "ad_x86.cpp"
32007 }
32008}
32009
32010void reinterpret_mask_W2BNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
32011 cbuf.set_insts_mark();
32012 // Start at oper_input_base() and count operands
32013 unsigned idx0 = 1;
32014 unsigned idx1 = 1; // src
32015 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // xtmp
32016 {
32017 C2_MacroAssembler _masm(&cbuf);
32018
32019#line 3509 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
32020
32021 int src_sz = Matcher::vector_length(this, opnd_array(1))*type2aelembytes(T_SHORT);
32022 int dst_sz = Matcher::vector_length(this)*type2aelembytes(T_BYTE);
32023 assert(src_sz == dst_sz , "src and dst size mismatch")do { if (!(src_sz == dst_sz)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
3512, "assert(" "src_sz == dst_sz" ") failed", "src and dst size mismatch"
); ::breakpoint(); } } while (0);
32024 int vlen_enc = vector_length_encoding(src_sz);
32025 ___masm. evpmovm2w(opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* xtmp */, opnd_array(1)->as_KRegister(ra_,this,idx1)/* src */, vlen_enc);
32026 ___masm. evpmovb2m(opnd_array(0)->as_KRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* xtmp */, vlen_enc);
32027
32028#line 32028 "ad_x86.cpp"
32029 }
32030}
32031
32032void reinterpret_mask_D2BNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
32033 cbuf.set_insts_mark();
32034 // Start at oper_input_base() and count operands
32035 unsigned idx0 = 1;
32036 unsigned idx1 = 1; // src
32037 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // xtmp
32038 {
32039 C2_MacroAssembler _masm(&cbuf);
32040
32041#line 3530 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
32042
32043 int src_sz = Matcher::vector_length(this, opnd_array(1))*type2aelembytes(T_INT);
32044 int dst_sz = Matcher::vector_length(this)*type2aelembytes(T_BYTE);
32045 assert(src_sz == dst_sz , "src and dst size mismatch")do { if (!(src_sz == dst_sz)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
3533, "assert(" "src_sz == dst_sz" ") failed", "src and dst size mismatch"
); ::breakpoint(); } } while (0);
32046 int vlen_enc = vector_length_encoding(src_sz);
32047 ___masm. evpmovm2d(opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* xtmp */, opnd_array(1)->as_KRegister(ra_,this,idx1)/* src */, vlen_enc);
32048 ___masm. evpmovb2m(opnd_array(0)->as_KRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* xtmp */, vlen_enc);
32049
32050#line 32050 "ad_x86.cpp"
32051 }
32052}
32053
32054void reinterpret_mask_Q2BNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
32055 cbuf.set_insts_mark();
32056 // Start at oper_input_base() and count operands
32057 unsigned idx0 = 1;
32058 unsigned idx1 = 1; // src
32059 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // xtmp
32060 {
32061 C2_MacroAssembler _masm(&cbuf);
32062
32063#line 3551 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
32064
32065 int src_sz = Matcher::vector_length(this, opnd_array(1))*type2aelembytes(T_LONG);
32066 int dst_sz = Matcher::vector_length(this)*type2aelembytes(T_BYTE);
32067 assert(src_sz == dst_sz , "src and dst size mismatch")do { if (!(src_sz == dst_sz)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
3554, "assert(" "src_sz == dst_sz" ") failed", "src and dst size mismatch"
); ::breakpoint(); } } while (0);
32068 int vlen_enc = vector_length_encoding(src_sz);
32069 ___masm. evpmovm2q(opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* xtmp */, opnd_array(1)->as_KRegister(ra_,this,idx1)/* src */, vlen_enc);
32070 ___masm. evpmovb2m(opnd_array(0)->as_KRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* xtmp */, vlen_enc);
32071
32072#line 32072 "ad_x86.cpp"
32073 }
32074}
32075
32076void reinterpretNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
32077 cbuf.set_insts_mark();
32078 // Start at oper_input_base() and count operands
32079 unsigned idx0 = 1;
32080 unsigned idx1 = 1; // dst
32081 {
32082 C2_MacroAssembler _masm(&cbuf);
32083
32084#line 3568 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
32085
32086 // empty
32087
32088#line 32088 "ad_x86.cpp"
32089 }
32090}
32091
32092void reinterpret_expandNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
32093 cbuf.set_insts_mark();
32094 // Start at oper_input_base() and count operands
32095 unsigned idx0 = 1;
32096 unsigned idx1 = 1; // src
32097 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
32098 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // scratch
32099 {
32100 C2_MacroAssembler _masm(&cbuf);
32101
32102#line 3581 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
32103
32104 assert(Matcher::vector_length_in_bytes(this) <= 16, "required")do { if (!(Matcher::vector_length_in_bytes(this) <= 16)) {
(*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 3582, "assert(" "Matcher::vector_length_in_bytes(this) <= 16"
") failed", "required"); ::breakpoint(); } } while (0);
32105 assert(Matcher::vector_length_in_bytes(this, opnd_array(1)) <= 8, "required")do { if (!(Matcher::vector_length_in_bytes(this, opnd_array(1
)) <= 8)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 3583, "assert(" "Matcher::vector_length_in_bytes(this, opnd_array(1)) <= 8"
") failed", "required"); ::breakpoint(); } } while (0);
32106
32107 int src_vlen_in_bytes = Matcher::vector_length_in_bytes(this, opnd_array(1));
32108 if (src_vlen_in_bytes == 4) {
32109 ___masm. movdqu(opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* dst */, ExternalAddress(vector_32_bit_mask()), opnd_array(3)->as_Register(ra_,this,idx3)/* scratch */);
32110 } else {
32111 assert(src_vlen_in_bytes == 8, "")do { if (!(src_vlen_in_bytes == 8)) { (*g_assert_poison) = 'X'
;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 3589, "assert(" "src_vlen_in_bytes == 8" ") failed", ""); ::
breakpoint(); } } while (0);
32112 ___masm. movdqu(opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* dst */, ExternalAddress(vector_64_bit_mask()), opnd_array(3)->as_Register(ra_,this,idx3)/* scratch */);
32113 }
32114 ___masm. pand(opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
32115
32116#line 32116 "ad_x86.cpp"
32117 }
32118}
32119
32120void vreinterpret_expand4Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
32121 cbuf.set_insts_mark();
32122 // Start at oper_input_base() and count operands
32123 unsigned idx0 = 1;
32124 unsigned idx1 = 1; // src
32125 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // scratch
32126 {
32127 C2_MacroAssembler _masm(&cbuf);
32128
32129#line 3606 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
32130
32131 ___masm. vpand(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, ExternalAddress(vector_32_bit_mask()), 0, opnd_array(2)->as_Register(ra_,this,idx2)/* scratch */);
32132
32133#line 32133 "ad_x86.cpp"
32134 }
32135}
32136
32137void vreinterpret_expandNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
32138 cbuf.set_insts_mark();
32139 // Start at oper_input_base() and count operands
32140 unsigned idx0 = 1;
32141 unsigned idx1 = 1; // src
32142 {
32143 C2_MacroAssembler _masm(&cbuf);
32144
32145#line 3621 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
32146
32147 switch (Matcher::vector_length_in_bytes(this, opnd_array(1))) {
32148 case 8: ___masm. movq (opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */); break;
32149 case 16: ___masm. movdqu (opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */); break;
32150 case 32: ___masm. vmovdqu(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */); break;
32151 default: ShouldNotReachHere()do { (*g_assert_poison) = 'X';; report_should_not_reach_here(
"/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad", 3626
); ::breakpoint(); } while (0);
32152 }
32153
32154#line 32154 "ad_x86.cpp"
32155 }
32156}
32157
32158void reinterpret_shrinkNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
32159 cbuf.set_insts_mark();
32160 // Start at oper_input_base() and count operands
32161 unsigned idx0 = 1;
32162 unsigned idx1 = 1; // src
32163 {
32164 C2_MacroAssembler _masm(&cbuf);
32165
32166#line 3638 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
32167
32168 switch (Matcher::vector_length_in_bytes(this)) {
32169 case 4: ___masm. movfltz(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */); break;
32170 case 8: ___masm. movq (opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */); break;
32171 case 16: ___masm. movdqu (opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */); break;
32172 case 32: ___masm. vmovdqu(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */); break;
32173 default: ShouldNotReachHere()do { (*g_assert_poison) = 'X';; report_should_not_reach_here(
"/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad", 3644
); ::breakpoint(); } while (0);
32174 }
32175
32176#line 32176 "ad_x86.cpp"
32177 }
32178}
32179
32180void roundD_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
32181 cbuf.set_insts_mark();
32182 // Start at oper_input_base() and count operands
32183 unsigned idx0 = 1;
32184 unsigned idx1 = 1; // src
32185 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // rmode
32186 {
32187 C2_MacroAssembler _masm(&cbuf);
32188
32189#line 3657 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
32190
32191 assert(UseSSE >= 4, "required")do { if (!(UseSSE >= 4)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
3658, "assert(" "UseSSE >= 4" ") failed", "required"); ::
breakpoint(); } } while (0);
32192 ___masm. roundsd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->constant());
32193
32194#line 32194 "ad_x86.cpp"
32195 }
32196}
32197
32198void roundD_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
32199 cbuf.set_insts_mark();
32200 // Start at oper_input_base() and count operands
32201 unsigned idx0 = 2;
32202 unsigned idx1 = 2; // src
32203 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // rmode
32204 {
32205 C2_MacroAssembler _masm(&cbuf);
32206
32207#line 3668 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
32208
32209 assert(UseSSE >= 4, "required")do { if (!(UseSSE >= 4)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
3669, "assert(" "UseSSE >= 4" ") failed", "required"); ::
breakpoint(); } } while (0);
32210 ___masm. roundsd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->constant());
32211
32212#line 32212 "ad_x86.cpp"
32213 }
32214}
32215
32216void roundD_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
32217 cbuf.set_insts_mark();
32218 // Start at oper_input_base() and count operands
32219 unsigned idx0 = 1;
32220 unsigned idx1 = 1; // con
32221 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // rmode
32222 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // scratch_reg
32223 {
32224 C2_MacroAssembler _masm(&cbuf);
32225
32226#line 3680 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
32227
32228 assert(UseSSE >= 4, "required")do { if (!(UseSSE >= 4)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
3681, "assert(" "UseSSE >= 4" ") failed", "required"); ::
breakpoint(); } } while (0);
32229 ___masm. roundsd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, InternalAddress(___masm. code()->consts()->start() + constant_offset()), opnd_array(2)->constant(), opnd_array(3)->as_Register(ra_,this,idx3)/* scratch_reg */);
32230
32231#line 32231 "ad_x86.cpp"
32232 }
32233}
32234
32235void roundD_immNode::eval_constant(Compile* C) {
32236 {
32237
32238#line 3682 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
32239 _constant = C->output()->constant_table().add(this, opnd_array(1));
32240#line 32240 "ad_x86.cpp"
32241 }
32242}
32243void vroundD_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
32244 cbuf.set_insts_mark();
32245 // Start at oper_input_base() and count operands
32246 unsigned idx0 = 1;
32247 unsigned idx1 = 1; // src
32248 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // rmode
32249 {
32250 C2_MacroAssembler _masm(&cbuf);
32251
32252#line 3691 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
32253
32254 assert(UseAVX > 0, "required")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
3692, "assert(" "UseAVX > 0" ") failed", "required"); ::breakpoint
(); } } while (0);
32255 int vlen_enc = vector_length_encoding(this);
32256 ___masm. vroundpd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->constant(), vlen_enc);
32257
32258#line 32258 "ad_x86.cpp"
32259 }
32260}
32261
32262void vround8D_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
32263 cbuf.set_insts_mark();
32264 // Start at oper_input_base() and count operands
32265 unsigned idx0 = 1;
32266 unsigned idx1 = 1; // src
32267 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // rmode
32268 {
32269 C2_MacroAssembler _masm(&cbuf);
32270
32271#line 3703 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
32272
32273 assert(UseAVX > 2, "required")do { if (!(UseAVX > 2)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
3704, "assert(" "UseAVX > 2" ") failed", "required"); ::breakpoint
(); } } while (0);
32274 ___masm. vrndscalepd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->constant(), Assembler::AVX_512bit);
32275
32276#line 32276 "ad_x86.cpp"
32277 }
32278}
32279
32280void vroundD_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
32281 cbuf.set_insts_mark();
32282 // Start at oper_input_base() and count operands
32283 unsigned idx0 = 2;
32284 unsigned idx1 = 2; // mem
32285 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // rmode
32286 {
32287 C2_MacroAssembler _masm(&cbuf);
32288
32289#line 3714 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
32290
32291 assert(UseAVX > 0, "required")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
3715, "assert(" "UseAVX > 0" ") failed", "required"); ::breakpoint
(); } } while (0);
32292 int vlen_enc = vector_length_encoding(this);
32293 ___masm. vroundpd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->constant(), vlen_enc);
32294
32295#line 32295 "ad_x86.cpp"
32296 }
32297}
32298
32299void vround8D_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
32300 cbuf.set_insts_mark();
32301 // Start at oper_input_base() and count operands
32302 unsigned idx0 = 2;
32303 unsigned idx1 = 2; // mem
32304 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // rmode
32305 {
32306 C2_MacroAssembler _masm(&cbuf);
32307
32308#line 3726 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
32309
32310 assert(UseAVX > 2, "required")do { if (!(UseAVX > 2)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
3727, "assert(" "UseAVX > 2" ") failed", "required"); ::breakpoint
(); } } while (0);
32311 ___masm. vrndscalepd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->constant(), Assembler::AVX_512bit);
32312
32313#line 32313 "ad_x86.cpp"
32314 }
32315}
32316
32317void onspinwaitNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
32318 cbuf.set_insts_mark();
32319 // Start at oper_input_base() and count operands
32320 unsigned idx0 = 1;
32321 unsigned idx1 = 1; //
32322 {
32323 C2_MacroAssembler _masm(&cbuf);
32324
32325#line 3742 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
32326
32327 ___masm. pause();
32328
32329#line 32329 "ad_x86.cpp"
32330 }
32331}
32332
32333void fmaD_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
32334 cbuf.set_insts_mark();
32335 // Start at oper_input_base() and count operands
32336 unsigned idx0 = 1;
32337 unsigned idx1 = 1; // c
32338 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // a
32339 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // b
32340 {
32341 C2_MacroAssembler _masm(&cbuf);
32342
32343#line 3754 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
32344
32345 ___masm. fmad(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* c */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* a */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* b */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* c */);
32346
32347#line 32347 "ad_x86.cpp"
32348 }
32349}
32350
32351void fmaF_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
32352 cbuf.set_insts_mark();
32353 // Start at oper_input_base() and count operands
32354 unsigned idx0 = 1;
32355 unsigned idx1 = 1; // c
32356 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // a
32357 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // b
32358 {
32359 C2_MacroAssembler _masm(&cbuf);
32360
32361#line 3766 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
32362
32363 ___masm. fmaf(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* c */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* a */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* b */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* c */);
32364
32365#line 32365 "ad_x86.cpp"
32366 }
32367}
32368
32369void MoveVec2LegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
32370 cbuf.set_insts_mark();
32371 // Start at oper_input_base() and count operands
32372 unsigned idx0 = 1;
32373 unsigned idx1 = 1; // src
32374 {
32375 C2_MacroAssembler _masm(&cbuf);
32376
32377#line 3778 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
32378
32379 ShouldNotReachHere()do { (*g_assert_poison) = 'X';; report_should_not_reach_here(
"/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad", 3779
); ::breakpoint(); } while (0);
32380
32381#line 32381 "ad_x86.cpp"
32382 }
32383}
32384
32385void MoveLeg2VecNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
32386 cbuf.set_insts_mark();
32387 // Start at oper_input_base() and count operands
32388 unsigned idx0 = 1;
32389 unsigned idx1 = 1; // src
32390 {
32391 C2_MacroAssembler _masm(&cbuf);
32392
32393#line 3787 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
32394
32395 ShouldNotReachHere()do { (*g_assert_poison) = 'X';; report_should_not_reach_here(
"/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad", 3788
); ::breakpoint(); } while (0);
32396
32397#line 32397 "ad_x86.cpp"
32398 }
32399}
32400
32401void loadVNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
32402 cbuf.set_insts_mark();
32403 // Start at oper_input_base() and count operands
32404 unsigned idx0 = 2;
32405 unsigned idx1 = 2; // mem
32406 {
32407 C2_MacroAssembler _masm(&cbuf);
32408
32409#line 3800 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
32410
32411 switch (Matcher::vector_length_in_bytes(this)) {
32412 case 4: ___masm. movdl (opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc())); break;
32413 case 8: ___masm. movq (opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc())); break;
32414 case 16: ___masm. movdqu (opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc())); break;
32415 case 32: ___masm. vmovdqu (opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc())); break;
32416 case 64: ___masm. evmovdqul(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), Assembler::AVX_512bit); break;
32417 default: ShouldNotReachHere()do { (*g_assert_poison) = 'X';; report_should_not_reach_here(
"/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad", 3807
); ::breakpoint(); } while (0);
32418 }
32419
32420#line 32420 "ad_x86.cpp"
32421 }
32422}
32423
32424void storeVNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
32425 cbuf.set_insts_mark();
32426 // Start at oper_input_base() and count operands
32427 unsigned idx0 = 2;
32428 unsigned idx1 = 2; // mem
32429 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
32430 {
32431 C2_MacroAssembler _masm(&cbuf);
32432
32433#line 3818 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
32434
32435 switch (Matcher::vector_length_in_bytes(this, opnd_array(2))) {
32436 case 4: ___masm. movdl (Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */); break;
32437 case 8: ___masm. movq (Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */); break;
32438 case 16: ___masm. movdqu (Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */); break;
32439 case 32: ___masm. vmovdqu (Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */); break;
32440 case 64: ___masm. evmovdqul(Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Assembler::AVX_512bit); break;
32441 default: ShouldNotReachHere()do { (*g_assert_poison) = 'X';; report_should_not_reach_here(
"/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad", 3825
); ::breakpoint(); } while (0);
32442 }
32443
32444#line 32444 "ad_x86.cpp"
32445 }
32446}
32447
32448void gatherNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
32449 cbuf.set_insts_mark();
32450 // Start at oper_input_base() and count operands
32451 unsigned idx0 = 2;
32452 unsigned idx1 = 2; // mem
32453 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // idx
32454 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
32455 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
32456 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // mask
32457 {
32458 C2_MacroAssembler _masm(&cbuf);
32459
32460#line 3840 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
32461
32462 assert(UseAVX >= 2, "sanity")do { if (!(UseAVX >= 2)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
3841, "assert(" "UseAVX >= 2" ") failed", "sanity"); ::breakpoint
(); } } while (0);
32463
32464 int vlen_enc = vector_length_encoding(this);
32465 BasicType elem_bt = Matcher::vector_element_basic_type(this);
32466
32467 assert(Matcher::vector_length_in_bytes(this) >= 16, "sanity")do { if (!(Matcher::vector_length_in_bytes(this) >= 16)) {
(*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 3846, "assert(" "Matcher::vector_length_in_bytes(this) >= 16"
") failed", "sanity"); ::breakpoint(); } } while (0);
32468 assert(!is_subword_type(elem_bt), "sanity")do { if (!(!is_subword_type(elem_bt))) { (*g_assert_poison) =
'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 3847, "assert(" "!is_subword_type(elem_bt)" ") failed", "sanity"
); ::breakpoint(); } } while (0); // T_INT, T_LONG, T_FLOAT, T_DOUBLE
32469
32470 if (vlen_enc == Assembler::AVX_128bit) {
32471 ___masm. movdqu(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* mask */, ExternalAddress(vector_all_bits_set()));
32472 } else {
32473 ___masm. vmovdqu(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* mask */, ExternalAddress(vector_all_bits_set()));
32474 }
32475 ___masm. lea(opnd_array(4)->as_Register(ra_,this,idx4)/* tmp */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
32476 ___masm. vgather(elem_bt, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_Register(ra_,this,idx4)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* idx */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* mask */, vlen_enc);
32477
32478#line 32478 "ad_x86.cpp"
32479 }
32480}
32481
32482void evgatherNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
32483 cbuf.set_insts_mark();
32484 // Start at oper_input_base() and count operands
32485 unsigned idx0 = 2;
32486 unsigned idx1 = 2; // mem
32487 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // idx
32488 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
32489 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
32490 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // ktmp
32491 {
32492 C2_MacroAssembler _masm(&cbuf);
32493
32494#line 3865 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
32495
32496 assert(UseAVX > 2, "sanity")do { if (!(UseAVX > 2)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
3866, "assert(" "UseAVX > 2" ") failed", "sanity"); ::breakpoint
(); } } while (0);
32497
32498 int vlen_enc = vector_length_encoding(this);
32499 BasicType elem_bt = Matcher::vector_element_basic_type(this);
32500
32501 assert(!is_subword_type(elem_bt), "sanity")do { if (!(!is_subword_type(elem_bt))) { (*g_assert_poison) =
'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 3871, "assert(" "!is_subword_type(elem_bt)" ") failed", "sanity"
); ::breakpoint(); } } while (0); // T_INT, T_LONG, T_FLOAT, T_DOUBLE
32502
32503 ___masm. kmovwl(opnd_array(5)->as_KRegister(ra_,this,idx5)/* ktmp */, ExternalAddress(vector_all_bits_set()), opnd_array(4)->as_Register(ra_,this,idx4)/* tmp */);
32504 ___masm. lea(opnd_array(4)->as_Register(ra_,this,idx4)/* tmp */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
32505 ___masm. evgather(elem_bt, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(5)->as_KRegister(ra_,this,idx5)/* ktmp */, opnd_array(4)->as_Register(ra_,this,idx4)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* idx */, vlen_enc);
32506
32507#line 32507 "ad_x86.cpp"
32508 }
32509}
32510
32511void evgather_maskedNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
32512 cbuf.set_insts_mark();
32513 // Start at oper_input_base() and count operands
32514 unsigned idx0 = 2;
32515 unsigned idx1 = 2; // mem
32516 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // idx
32517 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
32518 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // dst
32519 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // ktmp
32520 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // tmp
32521 {
32522 C2_MacroAssembler _masm(&cbuf);
32523
32524#line 3884 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
32525
32526 assert(UseAVX > 2, "sanity")do { if (!(UseAVX > 2)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
3885, "assert(" "UseAVX > 2" ") failed", "sanity"); ::breakpoint
(); } } while (0);
32527 int vlen_enc = vector_length_encoding(this);
32528 BasicType elem_bt = Matcher::vector_element_basic_type(this);
32529 assert(!is_subword_type(elem_bt), "sanity")do { if (!(!is_subword_type(elem_bt))) { (*g_assert_poison) =
'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 3888, "assert(" "!is_subword_type(elem_bt)" ") failed", "sanity"
); ::breakpoint(); } } while (0); // T_INT, T_LONG, T_FLOAT, T_DOUBLE
32530 // Note: Since gather instruction partially updates the opmask register used
32531 // for predication hense moving mask operand to a temporary.
32532 ___masm. kmovwl(opnd_array(5)->as_KRegister(ra_,this,idx5)/* ktmp */, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */);
32533 ___masm. vpxor(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* dst */, vlen_enc);
32534 ___masm. lea(opnd_array(6)->as_Register(ra_,this,idx6)/* tmp */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
32535 ___masm. evgather(elem_bt, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* dst */, opnd_array(5)->as_KRegister(ra_,this,idx5)/* ktmp */, opnd_array(6)->as_Register(ra_,this,idx6)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* idx */, vlen_enc);
32536
32537#line 32537 "ad_x86.cpp"
32538 }
32539}
32540
32541void scatterNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
32542 cbuf.set_insts_mark();
32543 // Start at oper_input_base() and count operands
32544 unsigned idx0 = 2;
32545 unsigned idx1 = 2; // mem
32546 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
32547 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // idx
32548 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
32549 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // ktmp
32550 {
32551 C2_MacroAssembler _masm(&cbuf);
32552
32553#line 3907 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
32554
32555 int vlen_enc = vector_length_encoding(this, opnd_array(2));
32556 BasicType elem_bt = Matcher::vector_element_basic_type(this, opnd_array(2));
32557
32558 assert(Matcher::vector_length_in_bytes(this, opnd_array(2)) >= 16, "sanity")do { if (!(Matcher::vector_length_in_bytes(this, opnd_array(2
)) >= 16)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 3911, "assert(" "Matcher::vector_length_in_bytes(this, opnd_array(2)) >= 16"
") failed", "sanity"); ::breakpoint(); } } while (0);
32559 assert(!is_subword_type(elem_bt), "sanity")do { if (!(!is_subword_type(elem_bt))) { (*g_assert_poison) =
'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 3912, "assert(" "!is_subword_type(elem_bt)" ") failed", "sanity"
); ::breakpoint(); } } while (0); // T_INT, T_LONG, T_FLOAT, T_DOUBLE
32560
32561 ___masm. kmovwl(opnd_array(5)->as_KRegister(ra_,this,idx5)/* ktmp */, ExternalAddress(vector_all_bits_set()), opnd_array(4)->as_Register(ra_,this,idx4)/* tmp */);
32562 ___masm. lea(opnd_array(4)->as_Register(ra_,this,idx4)/* tmp */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
32563 ___masm. evscatter(elem_bt, opnd_array(4)->as_Register(ra_,this,idx4)/* tmp */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* idx */, opnd_array(5)->as_KRegister(ra_,this,idx5)/* ktmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, vlen_enc);
32564
32565#line 32565 "ad_x86.cpp"
32566 }
32567}
32568
32569void scatter_maskedNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
32570 cbuf.set_insts_mark();
32571 // Start at oper_input_base() and count operands
32572 unsigned idx0 = 2;
32573 unsigned idx1 = 2; // mem
32574 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
32575 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // idx
32576 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // mask
32577 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // ktmp
32578 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // tmp
32579 {
32580 C2_MacroAssembler _masm(&cbuf);
32581
32582#line 3925 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
32583
32584 int vlen_enc = vector_length_encoding(this, opnd_array(2));
32585 BasicType elem_bt = Matcher::vector_element_basic_type(this, opnd_array(2));
32586 assert(Matcher::vector_length_in_bytes(this, opnd_array(2)) >= 16, "sanity")do { if (!(Matcher::vector_length_in_bytes(this, opnd_array(2
)) >= 16)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 3928, "assert(" "Matcher::vector_length_in_bytes(this, opnd_array(2)) >= 16"
") failed", "sanity"); ::breakpoint(); } } while (0);
32587 assert(!is_subword_type(elem_bt), "sanity")do { if (!(!is_subword_type(elem_bt))) { (*g_assert_poison) =
'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 3929, "assert(" "!is_subword_type(elem_bt)" ") failed", "sanity"
); ::breakpoint(); } } while (0); // T_INT, T_LONG, T_FLOAT, T_DOUBLE
32588 // Note: Since scatter instruction partially updates the opmask register used
32589 // for predication hense moving mask operand to a temporary.
32590 ___masm. kmovwl(opnd_array(5)->as_KRegister(ra_,this,idx5)/* ktmp */, opnd_array(4)->as_KRegister(ra_,this,idx4)/* mask */);
32591 ___masm. lea(opnd_array(6)->as_Register(ra_,this,idx6)/* tmp */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
32592 ___masm. evscatter(elem_bt, opnd_array(6)->as_Register(ra_,this,idx6)/* tmp */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* idx */, opnd_array(5)->as_KRegister(ra_,this,idx5)/* ktmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, vlen_enc);
32593
32594#line 32594 "ad_x86.cpp"
32595 }
32596}
32597
32598void ReplB_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
32599 cbuf.set_insts_mark();
32600 // Start at oper_input_base() and count operands
32601 unsigned idx0 = 1;
32602 unsigned idx1 = 1; // src
32603 {
32604 C2_MacroAssembler _masm(&cbuf);
32605
32606#line 3945 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
32607
32608 uint vlen = Matcher::vector_length(this);
32609 if (vlen == 64 || VM_Version::supports_avx512vlbw()) { // AVX512VL for <512bit operands
32610 assert(VM_Version::supports_avx512bw(), "required")do { if (!(VM_Version::supports_avx512bw())) { (*g_assert_poison
) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 3948, "assert(" "VM_Version::supports_avx512bw()" ") failed"
, "required"); ::breakpoint(); } } while (0); // 512-bit byte vectors assume AVX512BW
32611 int vlen_enc = vector_length_encoding(this);
32612 ___masm. evpbroadcastb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */, vlen_enc);
32613 } else if (VM_Version::supports_avx2()) {
32614 int vlen_enc = vector_length_encoding(this);
32615 ___masm. movdl(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
32616 ___masm. vpbroadcastb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, vlen_enc);
32617 } else {
32618 ___masm. movdl(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
32619 ___masm. punpcklbw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
32620 ___masm. pshuflw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, 0x00);
32621 if (vlen >= 16) {
32622 ___masm. punpcklqdq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
32623 if (vlen >= 32) {
32624 assert(vlen == 32, "sanity")do { if (!(vlen == 32)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
3962, "assert(" "vlen == 32" ") failed", "sanity"); ::breakpoint
(); } } while (0);
32625 ___masm. vinserti128_high(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
32626 }
32627 }
32628 }
32629
32630#line 32630 "ad_x86.cpp"
32631 }
32632}
32633
32634void ReplB_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
32635 cbuf.set_insts_mark();
32636 // Start at oper_input_base() and count operands
32637 unsigned idx0 = 2;
32638 unsigned idx1 = 2; // mem
32639 {
32640 C2_MacroAssembler _masm(&cbuf);
32641
32642#line 3975 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
32643
32644 int vlen_enc = vector_length_encoding(this);
32645 ___masm. vpbroadcastb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vlen_enc);
32646
32647#line 32647 "ad_x86.cpp"
32648 }
32649}
32650
32651void ReplB_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
32652 cbuf.set_insts_mark();
32653 // Start at oper_input_base() and count operands
32654 unsigned idx0 = 1;
32655 unsigned idx1 = 1; // con
32656 {
32657 C2_MacroAssembler _masm(&cbuf);
32658
32659#line 3985 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
32660
32661 uint vlen = Matcher::vector_length(this);
32662 InternalAddress const_addr = InternalAddress(___masm. code()->consts()->start() + constant_offset());
32663 if (vlen == 4) {
32664 ___masm. movdl(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, const_addr);
32665 } else {
32666 ___masm. movq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, const_addr);
32667 if (vlen >= 16) {
32668 if (VM_Version::supports_avx2()) {
32669 int vlen_enc = vector_length_encoding(this);
32670 ___masm. vpbroadcastq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, vlen_enc);
32671 } else {
32672 assert(vlen == 16, "sanity")do { if (!(vlen == 16)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
3997, "assert(" "vlen == 16" ") failed", "sanity"); ::breakpoint
(); } } while (0);
32673 ___masm. punpcklqdq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
32674 }
32675 }
32676 }
32677
32678#line 32678 "ad_x86.cpp"
32679 }
32680}
32681
32682void ReplB_immNode::eval_constant(Compile* C) {
32683 {
32684
32685#line 3987 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
32686 _constant = C->output()->constant_table().add(this, replicate8_imm(opnd_array(1)->constant(), 1));
32687#line 32687 "ad_x86.cpp"
32688 }
32689}
32690void ReplB_zeroNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
32691 cbuf.set_insts_mark();
32692 // Start at oper_input_base() and count operands
32693 unsigned idx0 = 1;
32694 unsigned idx1 = 1; // zero
32695 {
32696 C2_MacroAssembler _masm(&cbuf);
32697
32698#line 4010 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
32699
32700 uint vlen = Matcher::vector_length(this);
32701 if (vlen <= 16) {
32702 ___masm. pxor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
32703 } else {
32704 // Use vpxor since AVX512F does not have 512bit vxorpd (requires AVX512DQ).
32705 int vlen_enc = vector_length_encoding(this);
32706 ___masm. vpxor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, vlen_enc);
32707 }
32708
32709#line 32709 "ad_x86.cpp"
32710 }
32711}
32712
32713void ReplS_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
32714 cbuf.set_insts_mark();
32715 // Start at oper_input_base() and count operands
32716 unsigned idx0 = 1;
32717 unsigned idx1 = 1; // src
32718 {
32719 C2_MacroAssembler _masm(&cbuf);
32720
32721#line 4028 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
32722
32723 uint vlen = Matcher::vector_length(this);
32724 if (vlen == 32 || VM_Version::supports_avx512vlbw()) { // AVX512VL for <512bit operands
32725 assert(VM_Version::supports_avx512bw(), "required")do { if (!(VM_Version::supports_avx512bw())) { (*g_assert_poison
) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 4031, "assert(" "VM_Version::supports_avx512bw()" ") failed"
, "required"); ::breakpoint(); } } while (0); // 512-bit short vectors assume AVX512BW
32726 int vlen_enc = vector_length_encoding(this);
32727 ___masm. evpbroadcastw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */, vlen_enc);
32728 } else if (VM_Version::supports_avx2()) {
32729 int vlen_enc = vector_length_encoding(this);
32730 ___masm. movdl(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
32731 ___masm. vpbroadcastw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, vlen_enc);
32732 } else {
32733 ___masm. movdl(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
32734 ___masm. pshuflw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, 0x00);
32735 if (vlen >= 8) {
32736 ___masm. punpcklqdq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
32737 if (vlen >= 16) {
32738 assert(vlen == 16, "sanity")do { if (!(vlen == 16)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
4044, "assert(" "vlen == 16" ") failed", "sanity"); ::breakpoint
(); } } while (0);
32739 ___masm. vinserti128_high(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
32740 }
32741 }
32742 }
32743
32744#line 32744 "ad_x86.cpp"
32745 }
32746}
32747
32748void ReplS_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
32749 cbuf.set_insts_mark();
32750 // Start at oper_input_base() and count operands
32751 unsigned idx0 = 2;
32752 unsigned idx1 = 2; // mem
32753 {
32754 C2_MacroAssembler _masm(&cbuf);
32755
32756#line 4057 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
32757
32758 int vlen_enc = vector_length_encoding(this);
32759 ___masm. vpbroadcastw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vlen_enc);
32760
32761#line 32761 "ad_x86.cpp"
32762 }
32763}
32764
32765void ReplS_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
32766 cbuf.set_insts_mark();
32767 // Start at oper_input_base() and count operands
32768 unsigned idx0 = 1;
32769 unsigned idx1 = 1; // con
32770 {
32771 C2_MacroAssembler _masm(&cbuf);
32772
32773#line 4067 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
32774
32775 uint vlen = Matcher::vector_length(this);
32776 InternalAddress const_addr = InternalAddress(___masm. code()->consts()->start() + constant_offset());
32777 if (vlen == 2) {
32778 ___masm. movdl(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, const_addr);
32779 } else {
32780 ___masm. movq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, const_addr);
32781 if (vlen >= 8) {
32782 if (VM_Version::supports_avx2()) {
32783 int vlen_enc = vector_length_encoding(this);
32784 ___masm. vpbroadcastw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, vlen_enc);
32785 } else {
32786 assert(vlen == 8, "sanity")do { if (!(vlen == 8)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
4079, "assert(" "vlen == 8" ") failed", "sanity"); ::breakpoint
(); } } while (0);
32787 ___masm. punpcklqdq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
32788 }
32789 }
32790 }
32791
32792#line 32792 "ad_x86.cpp"
32793 }
32794}
32795
32796void ReplS_immNode::eval_constant(Compile* C) {
32797 {
32798
32799#line 4069 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
32800 _constant = C->output()->constant_table().add(this, replicate8_imm(opnd_array(1)->constant(), 2));
32801#line 32801 "ad_x86.cpp"
32802 }
32803}
32804void ReplS_zeroNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
32805 cbuf.set_insts_mark();
32806 // Start at oper_input_base() and count operands
32807 unsigned idx0 = 1;
32808 unsigned idx1 = 1; // zero
32809 {
32810 C2_MacroAssembler _masm(&cbuf);
32811
32812#line 4091 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
32813
32814 uint vlen = Matcher::vector_length(this);
32815 if (vlen <= 8) {
32816 ___masm. pxor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
32817 } else {
32818 int vlen_enc = vector_length_encoding(this);
32819 ___masm. vpxor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, vlen_enc);
32820 }
32821
32822#line 32822 "ad_x86.cpp"
32823 }
32824}
32825
32826void ReplI_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
32827 cbuf.set_insts_mark();
32828 // Start at oper_input_base() and count operands
32829 unsigned idx0 = 1;
32830 unsigned idx1 = 1; // src
32831 {
32832 C2_MacroAssembler _masm(&cbuf);
32833
32834#line 4108 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
32835
32836 uint vlen = Matcher::vector_length(this);
32837 if (vlen == 16 || VM_Version::supports_avx512vl()) { // AVX512VL for <512bit operands
32838 int vlen_enc = vector_length_encoding(this);
32839 ___masm. evpbroadcastd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */, vlen_enc);
32840 } else if (VM_Version::supports_avx2()) {
32841 int vlen_enc = vector_length_encoding(this);
32842 ___masm. movdl(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
32843 ___masm. vpbroadcastd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, vlen_enc);
32844 } else {
32845 ___masm. movdl(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
32846 ___masm. pshufd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, 0x00);
32847 if (vlen >= 8) {
32848 assert(vlen == 8, "sanity")do { if (!(vlen == 8)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
4121, "assert(" "vlen == 8" ") failed", "sanity"); ::breakpoint
(); } } while (0);
32849 ___masm. vinserti128_high(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
32850 }
32851 }
32852
32853#line 32853 "ad_x86.cpp"
32854 }
32855}
32856
32857void ReplI_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
32858 cbuf.set_insts_mark();
32859 // Start at oper_input_base() and count operands
32860 unsigned idx0 = 2;
32861 unsigned idx1 = 2; // mem
32862 {
32863 C2_MacroAssembler _masm(&cbuf);
32864
32865#line 4132 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
32866
32867 uint vlen = Matcher::vector_length(this);
32868 if (vlen <= 4) {
32869 ___masm. movdl(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
32870 ___masm. pshufd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, 0x00);
32871 } else {
32872 assert(VM_Version::supports_avx2(), "sanity")do { if (!(VM_Version::supports_avx2())) { (*g_assert_poison)
= 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 4138, "assert(" "VM_Version::supports_avx2()" ") failed", "sanity"
); ::breakpoint(); } } while (0);
32873 int vlen_enc = vector_length_encoding(this);
32874 ___masm. vpbroadcastd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vlen_enc);
32875 }
32876
32877#line 32877 "ad_x86.cpp"
32878 }
32879}
32880
32881void ReplI_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
32882 cbuf.set_insts_mark();
32883 // Start at oper_input_base() and count operands
32884 unsigned idx0 = 1;
32885 unsigned idx1 = 1; // con
32886 {
32887 C2_MacroAssembler _masm(&cbuf);
32888
32889#line 4149 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
32890
32891 uint vlen = Matcher::vector_length(this);
32892 InternalAddress const_addr = InternalAddress(___masm. code()->consts()->start() + constant_offset());
32893 if (vlen <= 4) {
32894 ___masm. movq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, const_addr);
32895 if (vlen == 4) {
32896 ___masm. punpcklqdq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
32897 }
32898 } else {
32899 assert(VM_Version::supports_avx2(), "sanity")do { if (!(VM_Version::supports_avx2())) { (*g_assert_poison)
= 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 4158, "assert(" "VM_Version::supports_avx2()" ") failed", "sanity"
); ::breakpoint(); } } while (0);
32900 int vlen_enc = vector_length_encoding(this);
32901 ___masm. movq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, const_addr);
32902 ___masm. vpbroadcastd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, vlen_enc);
32903 }
32904
32905#line 32905 "ad_x86.cpp"
32906 }
32907}
32908
32909void ReplI_immNode::eval_constant(Compile* C) {
32910 {
32911
32912#line 4151 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
32913 _constant = C->output()->constant_table().add(this, replicate8_imm(opnd_array(1)->constant(), 4));
32914#line 32914 "ad_x86.cpp"
32915 }
32916}
32917void ReplI_zeroNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
32918 cbuf.set_insts_mark();
32919 // Start at oper_input_base() and count operands
32920 unsigned idx0 = 1;
32921 unsigned idx1 = 1; // zero
32922 {
32923 C2_MacroAssembler _masm(&cbuf);
32924
32925#line 4171 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
32926
32927 uint vlen = Matcher::vector_length(this);
32928 if (vlen <= 4) {
32929 ___masm. pxor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
32930 } else {
32931 int vlen_enc = vector_length_encoding(this);
32932 ___masm. vpxor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, vlen_enc);
32933 }
32934
32935#line 32935 "ad_x86.cpp"
32936 }
32937}
32938
32939void ReplI_M1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
32940 cbuf.set_insts_mark();
32941 // Start at oper_input_base() and count operands
32942 unsigned idx0 = 1;
32943 unsigned idx1 = 1; // con
32944 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
32945 {
32946 C2_MacroAssembler _masm(&cbuf);
32947
32948#line 4190 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
32949
32950 int vector_len = vector_length_encoding(this);
32951 ___masm. vallones(opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* dst */, vector_len);
32952
32953#line 32953 "ad_x86.cpp"
32954 }
32955}
32956
32957void ReplI_M1_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
32958 cbuf.set_insts_mark();
32959 // Start at oper_input_base() and count operands
32960 unsigned idx0 = 1;
32961 unsigned idx1 = 1; // con
32962 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
32963 {
32964 C2_MacroAssembler _masm(&cbuf);
32965
32966#line 4190 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
32967
32968 int vector_len = vector_length_encoding(this);
32969 ___masm. vallones(opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* dst */, vector_len);
32970
32971#line 32971 "ad_x86.cpp"
32972 }
32973}
32974
32975void ReplI_M1_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
32976 cbuf.set_insts_mark();
32977 // Start at oper_input_base() and count operands
32978 unsigned idx0 = 1;
32979 unsigned idx1 = 1; // con
32980 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
32981 {
32982 C2_MacroAssembler _masm(&cbuf);
32983
32984#line 4190 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
32985
32986 int vector_len = vector_length_encoding(this);
32987 ___masm. vallones(opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* dst */, vector_len);
32988
32989#line 32989 "ad_x86.cpp"
32990 }
32991}
32992
32993void ReplL_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
32994 cbuf.set_insts_mark();
32995 // Start at oper_input_base() and count operands
32996 unsigned idx0 = 1;
32997 unsigned idx1 = 1; // src
32998 {
32999 C2_MacroAssembler _masm(&cbuf);
33000
33001#line 4204 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
33002
33003 uint vlen = Matcher::vector_length(this);
33004 if (vlen == 2) {
33005 ___masm. movdq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
33006 ___masm. punpcklqdq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
33007 } else if (vlen == 8 || VM_Version::supports_avx512vl()) { // AVX512VL for <512bit operands
33008 int vlen_enc = vector_length_encoding(this);
33009 ___masm. evpbroadcastq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */, vlen_enc);
33010 } else if (VM_Version::supports_avx2()) {
33011 assert(vlen == 4, "sanity")do { if (!(vlen == 4)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
4213, "assert(" "vlen == 4" ") failed", "sanity"); ::breakpoint
(); } } while (0);
33012 int vlen_enc = vector_length_encoding(this);
33013 ___masm. movdq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
33014 ___masm. vpbroadcastq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, vlen_enc);
33015 } else {
33016 assert(vlen == 4, "sanity")do { if (!(vlen == 4)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
4218, "assert(" "vlen == 4" ") failed", "sanity"); ::breakpoint
(); } } while (0);
33017 ___masm. movdq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
33018 ___masm. punpcklqdq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
33019 ___masm. vinserti128_high(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
33020 }
33021
33022#line 33022 "ad_x86.cpp"
33023 }
33024}
33025
33026void ReplL_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33027 cbuf.set_insts_mark();
33028 // Start at oper_input_base() and count operands
33029 unsigned idx0 = 2;
33030 unsigned idx1 = 2; // mem
33031 {
33032 C2_MacroAssembler _masm(&cbuf);
33033
33034#line 4285 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
33035
33036 uint vlen = Matcher::vector_length(this);
33037 if (vlen == 2) {
33038 ___masm. movq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
33039 ___masm. punpcklqdq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
33040 } else {
33041 assert(VM_Version::supports_avx2(), "sanity")do { if (!(VM_Version::supports_avx2())) { (*g_assert_poison)
= 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 4291, "assert(" "VM_Version::supports_avx2()" ") failed", "sanity"
); ::breakpoint(); } } while (0);
33042 int vlen_enc = vector_length_encoding(this);
33043 ___masm. vpbroadcastq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vlen_enc);
33044 }
33045
33046#line 33046 "ad_x86.cpp"
33047 }
33048}
33049
33050void ReplL_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33051 cbuf.set_insts_mark();
33052 // Start at oper_input_base() and count operands
33053 unsigned idx0 = 1;
33054 unsigned idx1 = 1; // con
33055 {
33056 C2_MacroAssembler _masm(&cbuf);
33057
33058#line 4303 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
33059
33060 uint vlen = Matcher::vector_length(this);
33061 InternalAddress const_addr = InternalAddress(___masm. code()->consts()->start() + constant_offset());
33062 if (vlen == 2) {
33063 ___masm. movq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, const_addr);
33064 ___masm. punpcklqdq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
33065 } else {
33066 assert(VM_Version::supports_avx2(), "sanity")do { if (!(VM_Version::supports_avx2())) { (*g_assert_poison)
= 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 4310, "assert(" "VM_Version::supports_avx2()" ") failed", "sanity"
); ::breakpoint(); } } while (0);
33067 int vlen_enc = vector_length_encoding(this);
33068 ___masm. movq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, const_addr);
33069 ___masm. vpbroadcastq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, vlen_enc);
33070 }
33071
33072#line 33072 "ad_x86.cpp"
33073 }
33074}
33075
33076void ReplL_immNode::eval_constant(Compile* C) {
33077 {
33078
33079#line 4305 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
33080 _constant = C->output()->constant_table().add(this, opnd_array(1));
33081#line 33081 "ad_x86.cpp"
33082 }
33083}
33084void ReplL_zeroNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33085 cbuf.set_insts_mark();
33086 // Start at oper_input_base() and count operands
33087 unsigned idx0 = 1;
33088 unsigned idx1 = 1; // zero
33089 {
33090 C2_MacroAssembler _masm(&cbuf);
33091
33092#line 4322 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
33093
33094 int vlen = Matcher::vector_length(this);
33095 if (vlen == 2) {
33096 ___masm. pxor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
33097 } else {
33098 int vlen_enc = vector_length_encoding(this);
33099 ___masm. vpxor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, vlen_enc);
33100 }
33101
33102#line 33102 "ad_x86.cpp"
33103 }
33104}
33105
33106void ReplL_M1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33107 cbuf.set_insts_mark();
33108 // Start at oper_input_base() and count operands
33109 unsigned idx0 = 1;
33110 unsigned idx1 = 1; // con
33111 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
33112 {
33113 C2_MacroAssembler _masm(&cbuf);
33114
33115#line 4339 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
33116
33117 int vector_len = vector_length_encoding(this);
33118 ___masm. vallones(opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* dst */, vector_len);
33119
33120#line 33120 "ad_x86.cpp"
33121 }
33122}
33123
33124void ReplF_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33125 cbuf.set_insts_mark();
33126 // Start at oper_input_base() and count operands
33127 unsigned idx0 = 1;
33128 unsigned idx1 = 1; // src
33129 {
33130 C2_MacroAssembler _masm(&cbuf);
33131
33132#line 4351 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
33133
33134 uint vlen = Matcher::vector_length(this);
33135 if (vlen <= 4) {
33136 ___masm. pshufd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, 0x00);
33137 } else if (VM_Version::supports_avx2()) {
33138 int vlen_enc = vector_length_encoding(this);
33139 ___masm. vbroadcastss(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vlen_enc); // reg-to-reg variant requires AVX2
33140 } else {
33141 assert(vlen == 8, "sanity")do { if (!(vlen == 8)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
4359, "assert(" "vlen == 8" ") failed", "sanity"); ::breakpoint
(); } } while (0);
33142 ___masm. pshufd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, 0x00);
33143 ___masm. vinsertf128_high(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
33144 }
33145
33146#line 33146 "ad_x86.cpp"
33147 }
33148}
33149
33150void ReplF_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33151 cbuf.set_insts_mark();
33152 // Start at oper_input_base() and count operands
33153 unsigned idx0 = 2;
33154 unsigned idx1 = 2; // mem
33155 {
33156 C2_MacroAssembler _masm(&cbuf);
33157
33158#line 4370 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
33159
33160 uint vlen = Matcher::vector_length(this);
33161 if (vlen <= 4) {
33162 ___masm. movdl(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
33163 ___masm. pshufd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, 0x00);
33164 } else {
33165 assert(VM_Version::supports_avx(), "sanity")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) =
'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 4376, "assert(" "VM_Version::supports_avx()" ") failed", "sanity"
); ::breakpoint(); } } while (0);
33166 int vlen_enc = vector_length_encoding(this);
33167 ___masm. vbroadcastss(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vlen_enc);
33168 }
33169
33170#line 33170 "ad_x86.cpp"
33171 }
33172}
33173
33174void ReplF_zeroNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33175 cbuf.set_insts_mark();
33176 // Start at oper_input_base() and count operands
33177 unsigned idx0 = 1;
33178 unsigned idx1 = 1; // zero
33179 {
33180 C2_MacroAssembler _masm(&cbuf);
33181
33182#line 4387 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
33183
33184 uint vlen = Matcher::vector_length(this);
33185 if (vlen <= 4) {
33186 ___masm. xorps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
33187 } else {
33188 int vlen_enc = vector_length_encoding(this);
33189 ___masm. vpxor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */,opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, vlen_enc); // 512bit vxorps requires AVX512DQ
33190 }
33191
33192#line 33192 "ad_x86.cpp"
33193 }
33194}
33195
33196void ReplD_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33197 cbuf.set_insts_mark();
33198 // Start at oper_input_base() and count operands
33199 unsigned idx0 = 1;
33200 unsigned idx1 = 1; // src
33201 {
33202 C2_MacroAssembler _masm(&cbuf);
33203
33204#line 4405 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
33205
33206 uint vlen = Matcher::vector_length(this);
33207 if (vlen == 2) {
33208 ___masm. pshufd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, 0x44);
33209 } else if (VM_Version::supports_avx2()) {
33210 int vlen_enc = vector_length_encoding(this);
33211 ___masm. vbroadcastsd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vlen_enc); // reg-to-reg variant requires AVX2
33212 } else {
33213 assert(vlen == 4, "sanity")do { if (!(vlen == 4)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
4413, "assert(" "vlen == 4" ") failed", "sanity"); ::breakpoint
(); } } while (0);
33214 ___masm. pshufd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, 0x44);
33215 ___masm. vinsertf128_high(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
33216 }
33217
33218#line 33218 "ad_x86.cpp"
33219 }
33220}
33221
33222void ReplD_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33223 cbuf.set_insts_mark();
33224 // Start at oper_input_base() and count operands
33225 unsigned idx0 = 2;
33226 unsigned idx1 = 2; // mem
33227 {
33228 C2_MacroAssembler _masm(&cbuf);
33229
33230#line 4424 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
33231
33232 uint vlen = Matcher::vector_length(this);
33233 if (vlen == 2) {
33234 ___masm. movq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
33235 ___masm. pshufd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, 0x44);
33236 } else {
33237 assert(VM_Version::supports_avx(), "sanity")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) =
'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 4430, "assert(" "VM_Version::supports_avx()" ") failed", "sanity"
); ::breakpoint(); } } while (0);
33238 int vlen_enc = vector_length_encoding(this);
33239 ___masm. vbroadcastsd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vlen_enc);
33240 }
33241
33242#line 33242 "ad_x86.cpp"
33243 }
33244}
33245
33246void ReplD_zeroNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33247 cbuf.set_insts_mark();
33248 // Start at oper_input_base() and count operands
33249 unsigned idx0 = 1;
33250 unsigned idx1 = 1; // zero
33251 {
33252 C2_MacroAssembler _masm(&cbuf);
33253
33254#line 4441 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
33255
33256 uint vlen = Matcher::vector_length(this);
33257 if (vlen == 2) {
33258 ___masm. xorpd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */);
33259 } else {
33260 int vlen_enc = vector_length_encoding(this);
33261 ___masm. vpxor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, vlen_enc); // 512bit vxorps requires AVX512DQ
33262 }
33263
33264#line 33264 "ad_x86.cpp"
33265 }
33266}
33267
33268void insertNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33269 cbuf.set_insts_mark();
33270 // Start at oper_input_base() and count operands
33271 unsigned idx0 = 1;
33272 unsigned idx1 = 1; // dst
33273 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // val
33274 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // idx
33275 {
33276 C2_MacroAssembler _masm(&cbuf);
33277
33278#line 4459 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
33279
33280 assert(UseSSE >= 4, "required")do { if (!(UseSSE >= 4)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
4460, "assert(" "UseSSE >= 4" ") failed", "required"); ::
breakpoint(); } } while (0);
33281 assert(Matcher::vector_length_in_bytes(this) >= 8, "required")do { if (!(Matcher::vector_length_in_bytes(this) >= 8)) { (
*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 4461, "assert(" "Matcher::vector_length_in_bytes(this) >= 8"
") failed", "required"); ::breakpoint(); } } while (0);
33282
33283 BasicType elem_bt = Matcher::vector_element_basic_type(this);
33284
33285 assert(is_integral_type(elem_bt), "")do { if (!(is_integral_type(elem_bt))) { (*g_assert_poison) =
'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 4465, "assert(" "is_integral_type(elem_bt)" ") failed", "")
; ::breakpoint(); } } while (0);
33286 assert(opnd_array(3)->constant()< (int)Matcher::vector_length(this), "out of bounds")do { if (!(opnd_array(3)->constant()< (int)Matcher::vector_length
(this))) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 4466, "assert(" "opnd_array(3)->constant()< (int)Matcher::vector_length(this)"
") failed", "out of bounds"); ::breakpoint(); } } while (0);
33287
33288 ___masm. insert(elem_bt, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_Register(ra_,this,idx2)/* val */, opnd_array(3)->constant());
33289
33290#line 33290 "ad_x86.cpp"
33291 }
33292}
33293
33294void insert32Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33295 cbuf.set_insts_mark();
33296 // Start at oper_input_base() and count operands
33297 unsigned idx0 = 1;
33298 unsigned idx1 = 1; // src
33299 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // val
33300 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // idx
33301 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp
33302 {
33303 C2_MacroAssembler _masm(&cbuf);
33304
33305#line 4478 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
33306
33307 int vlen_enc = Assembler::AVX_256bit;
33308 BasicType elem_bt = Matcher::vector_element_basic_type(this);
33309 int elem_per_lane = 16/type2aelembytes(elem_bt);
33310 int log2epr = log2(elem_per_lane);
33311
33312 assert(is_integral_type(elem_bt), "sanity")do { if (!(is_integral_type(elem_bt))) { (*g_assert_poison) =
'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 4484, "assert(" "is_integral_type(elem_bt)" ") failed", "sanity"
); ::breakpoint(); } } while (0);
33313 assert(opnd_array(3)->constant()< (int)Matcher::vector_length(this), "out of bounds")do { if (!(opnd_array(3)->constant()< (int)Matcher::vector_length
(this))) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 4485, "assert(" "opnd_array(3)->constant()< (int)Matcher::vector_length(this)"
") failed", "out of bounds"); ::breakpoint(); } } while (0);
33314
33315 uint x_idx = opnd_array(3)->constant()& right_n_bits(log2epr)((((log2epr) >= BitsPerWord) ? 0 : (OneBit << (log2epr
))) - 1);
33316 uint y_idx = (opnd_array(3)->constant()>> log2epr) & 1;
33317 ___masm. vextracti128(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, y_idx);
33318 ___masm. vinsert(elem_bt, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp */, opnd_array(2)->as_Register(ra_,this,idx2)/* val */, x_idx);
33319 ___masm. vinserti128(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp */, y_idx);
33320
33321#line 33321 "ad_x86.cpp"
33322 }
33323}
33324
33325void insert64Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33326 cbuf.set_insts_mark();
33327 // Start at oper_input_base() and count operands
33328 unsigned idx0 = 1;
33329 unsigned idx1 = 1; // src
33330 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // val
33331 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // idx
33332 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp
33333 {
33334 C2_MacroAssembler _masm(&cbuf);
33335
33336#line 4501 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
33337
33338 assert(UseAVX > 2, "sanity")do { if (!(UseAVX > 2)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
4502, "assert(" "UseAVX > 2" ") failed", "sanity"); ::breakpoint
(); } } while (0);
33339
33340 BasicType elem_bt = Matcher::vector_element_basic_type(this);
33341 int elem_per_lane = 16/type2aelembytes(elem_bt);
33342 int log2epr = log2(elem_per_lane);
33343
33344 assert(is_integral_type(elem_bt), "")do { if (!(is_integral_type(elem_bt))) { (*g_assert_poison) =
'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 4508, "assert(" "is_integral_type(elem_bt)" ") failed", "")
; ::breakpoint(); } } while (0);
33345 assert(opnd_array(3)->constant()< (int)Matcher::vector_length(this), "out of bounds")do { if (!(opnd_array(3)->constant()< (int)Matcher::vector_length
(this))) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 4509, "assert(" "opnd_array(3)->constant()< (int)Matcher::vector_length(this)"
") failed", "out of bounds"); ::breakpoint(); } } while (0);
33346
33347 uint x_idx = opnd_array(3)->constant()& right_n_bits(log2epr)((((log2epr) >= BitsPerWord) ? 0 : (OneBit << (log2epr
))) - 1);
33348 uint y_idx = (opnd_array(3)->constant()>> log2epr) & 3;
33349 ___masm. vextracti32x4(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, y_idx);
33350 ___masm. vinsert(elem_bt, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp */, opnd_array(2)->as_Register(ra_,this,idx2)/* val */, x_idx);
33351 ___masm. vinserti32x4(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp */, y_idx);
33352
33353#line 33353 "ad_x86.cpp"
33354 }
33355}
33356
33357void insert2LNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33358 cbuf.set_insts_mark();
33359 // Start at oper_input_base() and count operands
33360 unsigned idx0 = 1;
33361 unsigned idx1 = 1; // dst
33362 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // val
33363 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // idx
33364 {
33365 C2_MacroAssembler _masm(&cbuf);
33366
33367#line 4525 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
33368
33369 assert(UseSSE >= 4, "required")do { if (!(UseSSE >= 4)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
4526, "assert(" "UseSSE >= 4" ") failed", "required"); ::
breakpoint(); } } while (0);
33370 assert(Matcher::vector_element_basic_type(this) == T_LONG, "")do { if (!(Matcher::vector_element_basic_type(this) == T_LONG
)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 4527, "assert(" "Matcher::vector_element_basic_type(this) == T_LONG"
") failed", ""); ::breakpoint(); } } while (0);
33371 assert(opnd_array(3)->constant()< (int)Matcher::vector_length(this), "out of bounds")do { if (!(opnd_array(3)->constant()< (int)Matcher::vector_length
(this))) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 4528, "assert(" "opnd_array(3)->constant()< (int)Matcher::vector_length(this)"
") failed", "out of bounds"); ::breakpoint(); } } while (0);
33372
33373 ___masm. pinsrq(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_Register(ra_,this,idx2)/* val */, opnd_array(3)->constant());
33374
33375#line 33375 "ad_x86.cpp"
33376 }
33377}
33378
33379void insert4LNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33380 cbuf.set_insts_mark();
33381 // Start at oper_input_base() and count operands
33382 unsigned idx0 = 1;
33383 unsigned idx1 = 1; // src
33384 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // val
33385 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // idx
33386 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp
33387 {
33388 C2_MacroAssembler _masm(&cbuf);
33389
33390#line 4540 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
33391
33392 assert(Matcher::vector_element_basic_type(this) == T_LONG, "")do { if (!(Matcher::vector_element_basic_type(this) == T_LONG
)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 4541, "assert(" "Matcher::vector_element_basic_type(this) == T_LONG"
") failed", ""); ::breakpoint(); } } while (0);
33393 assert(opnd_array(3)->constant()< (int)Matcher::vector_length(this), "out of bounds")do { if (!(opnd_array(3)->constant()< (int)Matcher::vector_length
(this))) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 4542, "assert(" "opnd_array(3)->constant()< (int)Matcher::vector_length(this)"
") failed", "out of bounds"); ::breakpoint(); } } while (0);
33394
33395 uint x_idx = opnd_array(3)->constant()& right_n_bits(1)((((1) >= BitsPerWord) ? 0 : (OneBit << (1))) - 1);
33396 uint y_idx = (opnd_array(3)->constant()>> 1) & 1;
33397 int vlen_enc = Assembler::AVX_256bit;
33398 ___masm. vextracti128(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, y_idx);
33399 ___masm. vpinsrq(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp */, opnd_array(2)->as_Register(ra_,this,idx2)/* val */, x_idx);
33400 ___masm. vinserti128(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp */, y_idx);
33401
33402#line 33402 "ad_x86.cpp"
33403 }
33404}
33405
33406void insert8LNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33407 cbuf.set_insts_mark();
33408 // Start at oper_input_base() and count operands
33409 unsigned idx0 = 1;
33410 unsigned idx1 = 1; // src
33411 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // val
33412 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // idx
33413 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp
33414 {
33415 C2_MacroAssembler _masm(&cbuf);
33416
33417#line 4559 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
33418
33419 assert(Matcher::vector_element_basic_type(this) == T_LONG, "sanity")do { if (!(Matcher::vector_element_basic_type(this) == T_LONG
)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 4560, "assert(" "Matcher::vector_element_basic_type(this) == T_LONG"
") failed", "sanity"); ::breakpoint(); } } while (0);
33420 assert(opnd_array(3)->constant()< (int)Matcher::vector_length(this), "out of bounds")do { if (!(opnd_array(3)->constant()< (int)Matcher::vector_length
(this))) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 4561, "assert(" "opnd_array(3)->constant()< (int)Matcher::vector_length(this)"
") failed", "out of bounds"); ::breakpoint(); } } while (0);
33421
33422 uint x_idx = opnd_array(3)->constant()& right_n_bits(1)((((1) >= BitsPerWord) ? 0 : (OneBit << (1))) - 1);
33423 uint y_idx = (opnd_array(3)->constant()>> 1) & 3;
33424 ___masm. vextracti32x4(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, y_idx);
33425 ___masm. vpinsrq(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp */, opnd_array(2)->as_Register(ra_,this,idx2)/* val */, x_idx);
33426 ___masm. vinserti32x4(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp */, y_idx);
33427
33428#line 33428 "ad_x86.cpp"
33429 }
33430}
33431
33432void insertFNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33433 cbuf.set_insts_mark();
33434 // Start at oper_input_base() and count operands
33435 unsigned idx0 = 1;
33436 unsigned idx1 = 1; // dst
33437 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // val
33438 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // idx
33439 {
33440 C2_MacroAssembler _masm(&cbuf);
33441
33442#line 4577 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
33443
33444 assert(UseSSE >= 4, "sanity")do { if (!(UseSSE >= 4)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
4578, "assert(" "UseSSE >= 4" ") failed", "sanity"); ::breakpoint
(); } } while (0);
33445
33446 assert(Matcher::vector_element_basic_type(this) == T_FLOAT, "sanity")do { if (!(Matcher::vector_element_basic_type(this) == T_FLOAT
)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 4580, "assert(" "Matcher::vector_element_basic_type(this) == T_FLOAT"
") failed", "sanity"); ::breakpoint(); } } while (0);
33447 assert(opnd_array(3)->constant()< (int)Matcher::vector_length(this), "out of bounds")do { if (!(opnd_array(3)->constant()< (int)Matcher::vector_length
(this))) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 4581, "assert(" "opnd_array(3)->constant()< (int)Matcher::vector_length(this)"
") failed", "out of bounds"); ::breakpoint(); } } while (0);
33448
33449 ___masm. insertps(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* val */, opnd_array(3)->constant());
33450
33451#line 33451 "ad_x86.cpp"
33452 }
33453}
33454
33455void vinsertFNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33456 cbuf.set_insts_mark();
33457 // Start at oper_input_base() and count operands
33458 unsigned idx0 = 1;
33459 unsigned idx1 = 1; // src
33460 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // val
33461 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // idx
33462 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp
33463 {
33464 C2_MacroAssembler _masm(&cbuf);
33465
33466#line 4593 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
33467
33468 assert(Matcher::vector_element_basic_type(this) == T_FLOAT, "sanity")do { if (!(Matcher::vector_element_basic_type(this) == T_FLOAT
)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 4594, "assert(" "Matcher::vector_element_basic_type(this) == T_FLOAT"
") failed", "sanity"); ::breakpoint(); } } while (0);
33469 assert(opnd_array(3)->constant()< (int)Matcher::vector_length(this), "out of bounds")do { if (!(opnd_array(3)->constant()< (int)Matcher::vector_length
(this))) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 4595, "assert(" "opnd_array(3)->constant()< (int)Matcher::vector_length(this)"
") failed", "out of bounds"); ::breakpoint(); } } while (0);
33470
33471 int vlen = Matcher::vector_length(this);
33472 uint x_idx = opnd_array(3)->constant()& right_n_bits(2)((((2) >= BitsPerWord) ? 0 : (OneBit << (2))) - 1);
33473 if (vlen == 8) {
33474 uint y_idx = (opnd_array(3)->constant()>> 2) & 1;
33475 int vlen_enc = Assembler::AVX_256bit;
33476 ___masm. vextracti128(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, y_idx);
33477 ___masm. vinsertps(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* val */, x_idx);
33478 ___masm. vinserti128(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp */, y_idx);
33479 } else {
33480 assert(vlen == 16, "sanity")do { if (!(vlen == 16)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
4606, "assert(" "vlen == 16" ") failed", "sanity"); ::breakpoint
(); } } while (0);
33481 uint y_idx = (opnd_array(3)->constant()>> 2) & 3;
33482 ___masm. vextracti32x4(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, y_idx);
33483 ___masm. vinsertps(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* val */, x_idx);
33484 ___masm. vinserti32x4(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp */, y_idx);
33485 }
33486
33487#line 33487 "ad_x86.cpp"
33488 }
33489}
33490
33491void insert2DNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33492 cbuf.set_insts_mark();
33493 // Start at oper_input_base() and count operands
33494 unsigned idx0 = 1;
33495 unsigned idx1 = 1; // dst
33496 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // val
33497 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // idx
33498 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
33499 {
33500 C2_MacroAssembler _masm(&cbuf);
33501
33502#line 4622 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
33503
33504 assert(UseSSE >= 4, "sanity")do { if (!(UseSSE >= 4)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
4623, "assert(" "UseSSE >= 4" ") failed", "sanity"); ::breakpoint
(); } } while (0);
33505 assert(Matcher::vector_element_basic_type(this) == T_DOUBLE, "sanity")do { if (!(Matcher::vector_element_basic_type(this) == T_DOUBLE
)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 4624, "assert(" "Matcher::vector_element_basic_type(this) == T_DOUBLE"
") failed", "sanity"); ::breakpoint(); } } while (0);
33506 assert(opnd_array(3)->constant()< (int)Matcher::vector_length(this), "out of bounds")do { if (!(opnd_array(3)->constant()< (int)Matcher::vector_length
(this))) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 4625, "assert(" "opnd_array(3)->constant()< (int)Matcher::vector_length(this)"
") failed", "out of bounds"); ::breakpoint(); } } while (0);
33507
33508 ___masm. movq(opnd_array(4)->as_Register(ra_,this,idx4)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* val */);
33509 ___masm. pinsrq(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(4)->as_Register(ra_,this,idx4)/* tmp */, opnd_array(3)->constant());
33510
33511#line 33511 "ad_x86.cpp"
33512 }
33513}
33514
33515void insert4DNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33516 cbuf.set_insts_mark();
33517 // Start at oper_input_base() and count operands
33518 unsigned idx0 = 1;
33519 unsigned idx1 = 1; // src
33520 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // val
33521 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // idx
33522 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
33523 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // vtmp
33524 {
33525 C2_MacroAssembler _masm(&cbuf);
33526
33527#line 4638 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
33528
33529 assert(Matcher::vector_element_basic_type(this) == T_DOUBLE, "sanity")do { if (!(Matcher::vector_element_basic_type(this) == T_DOUBLE
)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 4639, "assert(" "Matcher::vector_element_basic_type(this) == T_DOUBLE"
") failed", "sanity"); ::breakpoint(); } } while (0);
33530 assert(opnd_array(3)->constant()< (int)Matcher::vector_length(this), "out of bounds")do { if (!(opnd_array(3)->constant()< (int)Matcher::vector_length
(this))) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 4640, "assert(" "opnd_array(3)->constant()< (int)Matcher::vector_length(this)"
") failed", "out of bounds"); ::breakpoint(); } } while (0);
33531
33532 uint x_idx = opnd_array(3)->constant()& right_n_bits(1)((((1) >= BitsPerWord) ? 0 : (OneBit << (1))) - 1);
33533 uint y_idx = (opnd_array(3)->constant()>> 1) & 1;
33534 int vlen_enc = Assembler::AVX_256bit;
33535 ___masm. movq(opnd_array(4)->as_Register(ra_,this,idx4)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* val */);
33536 ___masm. vextracti128(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, y_idx);
33537 ___masm. vpinsrq(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp */, opnd_array(4)->as_Register(ra_,this,idx4)/* tmp */, x_idx);
33538 ___masm. vinserti128(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp */, y_idx);
33539
33540#line 33540 "ad_x86.cpp"
33541 }
33542}
33543
33544void insert8DNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33545 cbuf.set_insts_mark();
33546 // Start at oper_input_base() and count operands
33547 unsigned idx0 = 1;
33548 unsigned idx1 = 1; // src
33549 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // val
33550 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // idx
33551 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
33552 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // vtmp
33553 {
33554 C2_MacroAssembler _masm(&cbuf);
33555
33556#line 4658 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
33557
33558 assert(Matcher::vector_element_basic_type(this) == T_DOUBLE, "sanity")do { if (!(Matcher::vector_element_basic_type(this) == T_DOUBLE
)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 4659, "assert(" "Matcher::vector_element_basic_type(this) == T_DOUBLE"
") failed", "sanity"); ::breakpoint(); } } while (0);
33559 assert(opnd_array(3)->constant()< (int)Matcher::vector_length(this), "out of bounds")do { if (!(opnd_array(3)->constant()< (int)Matcher::vector_length
(this))) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 4660, "assert(" "opnd_array(3)->constant()< (int)Matcher::vector_length(this)"
") failed", "out of bounds"); ::breakpoint(); } } while (0);
33560
33561 uint x_idx = opnd_array(3)->constant()& right_n_bits(1)((((1) >= BitsPerWord) ? 0 : (OneBit << (1))) - 1);
33562 uint y_idx = (opnd_array(3)->constant()>> 1) & 3;
33563 ___masm. movq(opnd_array(4)->as_Register(ra_,this,idx4)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* val */);
33564 ___masm. vextracti32x4(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, y_idx);
33565 ___masm. vpinsrq(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp */, opnd_array(4)->as_Register(ra_,this,idx4)/* tmp */, x_idx);
33566 ___masm. vinserti32x4(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp */, y_idx);
33567
33568#line 33568 "ad_x86.cpp"
33569 }
33570}
33571
33572void reductionINode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33573 cbuf.set_insts_mark();
33574 // Start at oper_input_base() and count operands
33575 unsigned idx0 = 1;
33576 unsigned idx1 = 1; // src1
33577 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
33578 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1
33579 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2
33580 {
33581 C2_MacroAssembler _masm(&cbuf);
33582
33583#line 4688 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
33584
33585 int opcode = this->ideal_Opcode();
33586 int vlen = Matcher::vector_length(this, opnd_array(2));
33587 ___masm. reduceI(opcode, vlen, opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp2 */);
33588
33589#line 33589 "ad_x86.cpp"
33590 }
33591}
33592
33593void reductionI_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33594 cbuf.set_insts_mark();
33595 // Start at oper_input_base() and count operands
33596 unsigned idx0 = 1;
33597 unsigned idx1 = 1; // src1
33598 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
33599 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1
33600 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2
33601 {
33602 C2_MacroAssembler _masm(&cbuf);
33603
33604#line 4688 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
33605
33606 int opcode = this->ideal_Opcode();
33607 int vlen = Matcher::vector_length(this, opnd_array(2));
33608 ___masm. reduceI(opcode, vlen, opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp2 */);
33609
33610#line 33610 "ad_x86.cpp"
33611 }
33612}
33613
33614void reductionI_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33615 cbuf.set_insts_mark();
33616 // Start at oper_input_base() and count operands
33617 unsigned idx0 = 1;
33618 unsigned idx1 = 1; // src1
33619 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
33620 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1
33621 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2
33622 {
33623 C2_MacroAssembler _masm(&cbuf);
33624
33625#line 4688 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
33626
33627 int opcode = this->ideal_Opcode();
33628 int vlen = Matcher::vector_length(this, opnd_array(2));
33629 ___masm. reduceI(opcode, vlen, opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp2 */);
33630
33631#line 33631 "ad_x86.cpp"
33632 }
33633}
33634
33635void reductionI_2Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33636 cbuf.set_insts_mark();
33637 // Start at oper_input_base() and count operands
33638 unsigned idx0 = 1;
33639 unsigned idx1 = 1; // src1
33640 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
33641 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1
33642 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2
33643 {
33644 C2_MacroAssembler _masm(&cbuf);
33645
33646#line 4688 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
33647
33648 int opcode = this->ideal_Opcode();
33649 int vlen = Matcher::vector_length(this, opnd_array(2));
33650 ___masm. reduceI(opcode, vlen, opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp2 */);
33651
33652#line 33652 "ad_x86.cpp"
33653 }
33654}
33655
33656void reductionI_3Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33657 cbuf.set_insts_mark();
33658 // Start at oper_input_base() and count operands
33659 unsigned idx0 = 1;
33660 unsigned idx1 = 1; // src1
33661 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
33662 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1
33663 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2
33664 {
33665 C2_MacroAssembler _masm(&cbuf);
33666
33667#line 4688 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
33668
33669 int opcode = this->ideal_Opcode();
33670 int vlen = Matcher::vector_length(this, opnd_array(2));
33671 ___masm. reduceI(opcode, vlen, opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp2 */);
33672
33673#line 33673 "ad_x86.cpp"
33674 }
33675}
33676
33677void reductionI_4Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33678 cbuf.set_insts_mark();
33679 // Start at oper_input_base() and count operands
33680 unsigned idx0 = 1;
33681 unsigned idx1 = 1; // src1
33682 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
33683 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1
33684 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2
33685 {
33686 C2_MacroAssembler _masm(&cbuf);
33687
33688#line 4688 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
33689
33690 int opcode = this->ideal_Opcode();
33691 int vlen = Matcher::vector_length(this, opnd_array(2));
33692 ___masm. reduceI(opcode, vlen, opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp2 */);
33693
33694#line 33694 "ad_x86.cpp"
33695 }
33696}
33697
33698void reductionI_5Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33699 cbuf.set_insts_mark();
33700 // Start at oper_input_base() and count operands
33701 unsigned idx0 = 1;
33702 unsigned idx1 = 1; // src1
33703 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
33704 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1
33705 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2
33706 {
33707 C2_MacroAssembler _masm(&cbuf);
33708
33709#line 4688 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
33710
33711 int opcode = this->ideal_Opcode();
33712 int vlen = Matcher::vector_length(this, opnd_array(2));
33713 ___masm. reduceI(opcode, vlen, opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp2 */);
33714
33715#line 33715 "ad_x86.cpp"
33716 }
33717}
33718
33719void reductionLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33720 cbuf.set_insts_mark();
33721 // Start at oper_input_base() and count operands
33722 unsigned idx0 = 1;
33723 unsigned idx1 = 1; // src1
33724 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
33725 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1
33726 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2
33727 {
33728 C2_MacroAssembler _masm(&cbuf);
33729
33730#line 4710 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
33731
33732 int opcode = this->ideal_Opcode();
33733 int vlen = Matcher::vector_length(this, opnd_array(2));
33734 ___masm. reduceL(opcode, vlen, opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp2 */);
33735
33736#line 33736 "ad_x86.cpp"
33737 }
33738}
33739
33740void reductionL_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33741 cbuf.set_insts_mark();
33742 // Start at oper_input_base() and count operands
33743 unsigned idx0 = 1;
33744 unsigned idx1 = 1; // src1
33745 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
33746 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1
33747 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2
33748 {
33749 C2_MacroAssembler _masm(&cbuf);
33750
33751#line 4710 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
33752
33753 int opcode = this->ideal_Opcode();
33754 int vlen = Matcher::vector_length(this, opnd_array(2));
33755 ___masm. reduceL(opcode, vlen, opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp2 */);
33756
33757#line 33757 "ad_x86.cpp"
33758 }
33759}
33760
33761void reductionL_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33762 cbuf.set_insts_mark();
33763 // Start at oper_input_base() and count operands
33764 unsigned idx0 = 1;
33765 unsigned idx1 = 1; // src1
33766 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
33767 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1
33768 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2
33769 {
33770 C2_MacroAssembler _masm(&cbuf);
33771
33772#line 4710 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
33773
33774 int opcode = this->ideal_Opcode();
33775 int vlen = Matcher::vector_length(this, opnd_array(2));
33776 ___masm. reduceL(opcode, vlen, opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp2 */);
33777
33778#line 33778 "ad_x86.cpp"
33779 }
33780}
33781
33782void reductionL_2Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33783 cbuf.set_insts_mark();
33784 // Start at oper_input_base() and count operands
33785 unsigned idx0 = 1;
33786 unsigned idx1 = 1; // src1
33787 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
33788 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1
33789 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2
33790 {
33791 C2_MacroAssembler _masm(&cbuf);
33792
33793#line 4710 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
33794
33795 int opcode = this->ideal_Opcode();
33796 int vlen = Matcher::vector_length(this, opnd_array(2));
33797 ___masm. reduceL(opcode, vlen, opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp2 */);
33798
33799#line 33799 "ad_x86.cpp"
33800 }
33801}
33802
33803void reductionL_3Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33804 cbuf.set_insts_mark();
33805 // Start at oper_input_base() and count operands
33806 unsigned idx0 = 1;
33807 unsigned idx1 = 1; // src1
33808 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
33809 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1
33810 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2
33811 {
33812 C2_MacroAssembler _masm(&cbuf);
33813
33814#line 4710 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
33815
33816 int opcode = this->ideal_Opcode();
33817 int vlen = Matcher::vector_length(this, opnd_array(2));
33818 ___masm. reduceL(opcode, vlen, opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp2 */);
33819
33820#line 33820 "ad_x86.cpp"
33821 }
33822}
33823
33824void reductionL_4Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33825 cbuf.set_insts_mark();
33826 // Start at oper_input_base() and count operands
33827 unsigned idx0 = 1;
33828 unsigned idx1 = 1; // src1
33829 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
33830 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1
33831 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2
33832 {
33833 C2_MacroAssembler _masm(&cbuf);
33834
33835#line 4710 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
33836
33837 int opcode = this->ideal_Opcode();
33838 int vlen = Matcher::vector_length(this, opnd_array(2));
33839 ___masm. reduceL(opcode, vlen, opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp2 */);
33840
33841#line 33841 "ad_x86.cpp"
33842 }
33843}
33844
33845void reductionL_5Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33846 cbuf.set_insts_mark();
33847 // Start at oper_input_base() and count operands
33848 unsigned idx0 = 1;
33849 unsigned idx1 = 1; // src1
33850 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
33851 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1
33852 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2
33853 {
33854 C2_MacroAssembler _masm(&cbuf);
33855
33856#line 4710 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
33857
33858 int opcode = this->ideal_Opcode();
33859 int vlen = Matcher::vector_length(this, opnd_array(2));
33860 ___masm. reduceL(opcode, vlen, opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp2 */);
33861
33862#line 33862 "ad_x86.cpp"
33863 }
33864}
33865
33866void reductionL_avx512dqNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33867 cbuf.set_insts_mark();
33868 // Start at oper_input_base() and count operands
33869 unsigned idx0 = 1;
33870 unsigned idx1 = 1; // src1
33871 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
33872 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1
33873 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2
33874 {
33875 C2_MacroAssembler _masm(&cbuf);
33876
33877#line 4729 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
33878
33879 int opcode = this->ideal_Opcode();
33880 int vlen = Matcher::vector_length(this, opnd_array(2));
33881 ___masm. reduceL(opcode, vlen, opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp2 */);
33882
33883#line 33883 "ad_x86.cpp"
33884 }
33885}
33886
33887void reductionL_avx512dq_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33888 cbuf.set_insts_mark();
33889 // Start at oper_input_base() and count operands
33890 unsigned idx0 = 1;
33891 unsigned idx1 = 1; // src1
33892 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
33893 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1
33894 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2
33895 {
33896 C2_MacroAssembler _masm(&cbuf);
33897
33898#line 4729 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
33899
33900 int opcode = this->ideal_Opcode();
33901 int vlen = Matcher::vector_length(this, opnd_array(2));
33902 ___masm. reduceL(opcode, vlen, opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp2 */);
33903
33904#line 33904 "ad_x86.cpp"
33905 }
33906}
33907
33908void reductionL_avx512dq_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33909 cbuf.set_insts_mark();
33910 // Start at oper_input_base() and count operands
33911 unsigned idx0 = 1;
33912 unsigned idx1 = 1; // src1
33913 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
33914 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1
33915 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2
33916 {
33917 C2_MacroAssembler _masm(&cbuf);
33918
33919#line 4729 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
33920
33921 int opcode = this->ideal_Opcode();
33922 int vlen = Matcher::vector_length(this, opnd_array(2));
33923 ___masm. reduceL(opcode, vlen, opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp2 */);
33924
33925#line 33925 "ad_x86.cpp"
33926 }
33927}
33928
33929void reductionL_avx512dq_2Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33930 cbuf.set_insts_mark();
33931 // Start at oper_input_base() and count operands
33932 unsigned idx0 = 1;
33933 unsigned idx1 = 1; // src1
33934 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
33935 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1
33936 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2
33937 {
33938 C2_MacroAssembler _masm(&cbuf);
33939
33940#line 4729 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
33941
33942 int opcode = this->ideal_Opcode();
33943 int vlen = Matcher::vector_length(this, opnd_array(2));
33944 ___masm. reduceL(opcode, vlen, opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp2 */);
33945
33946#line 33946 "ad_x86.cpp"
33947 }
33948}
33949
33950void reductionL_avx512dq_3Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33951 cbuf.set_insts_mark();
33952 // Start at oper_input_base() and count operands
33953 unsigned idx0 = 1;
33954 unsigned idx1 = 1; // src1
33955 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
33956 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1
33957 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2
33958 {
33959 C2_MacroAssembler _masm(&cbuf);
33960
33961#line 4729 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
33962
33963 int opcode = this->ideal_Opcode();
33964 int vlen = Matcher::vector_length(this, opnd_array(2));
33965 ___masm. reduceL(opcode, vlen, opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp2 */);
33966
33967#line 33967 "ad_x86.cpp"
33968 }
33969}
33970
33971void reductionL_avx512dq_4Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33972 cbuf.set_insts_mark();
33973 // Start at oper_input_base() and count operands
33974 unsigned idx0 = 1;
33975 unsigned idx1 = 1; // src1
33976 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
33977 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1
33978 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2
33979 {
33980 C2_MacroAssembler _masm(&cbuf);
33981
33982#line 4729 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
33983
33984 int opcode = this->ideal_Opcode();
33985 int vlen = Matcher::vector_length(this, opnd_array(2));
33986 ___masm. reduceL(opcode, vlen, opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp2 */);
33987
33988#line 33988 "ad_x86.cpp"
33989 }
33990}
33991
33992void reductionL_avx512dq_5Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
33993 cbuf.set_insts_mark();
33994 // Start at oper_input_base() and count operands
33995 unsigned idx0 = 1;
33996 unsigned idx1 = 1; // src1
33997 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
33998 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1
33999 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2
34000 {
34001 C2_MacroAssembler _masm(&cbuf);
34002
34003#line 4729 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
34004
34005 int opcode = this->ideal_Opcode();
34006 int vlen = Matcher::vector_length(this, opnd_array(2));
34007 ___masm. reduceL(opcode, vlen, opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp2 */);
34008
34009#line 34009 "ad_x86.cpp"
34010 }
34011}
34012
34013void reductionF128Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34014 cbuf.set_insts_mark();
34015 // Start at oper_input_base() and count operands
34016 unsigned idx0 = 1;
34017 unsigned idx1 = 1; // dst
34018 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
34019 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp
34020 {
34021 C2_MacroAssembler _masm(&cbuf);
34022
34023#line 4746 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
34024
34025 int opcode = this->ideal_Opcode();
34026 int vlen = Matcher::vector_length(this, opnd_array(2));
34027 ___masm. reduce_fp(opcode, vlen, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp */);
34028
34029#line 34029 "ad_x86.cpp"
34030 }
34031}
34032
34033void reductionF128_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34034 cbuf.set_insts_mark();
34035 // Start at oper_input_base() and count operands
34036 unsigned idx0 = 1;
34037 unsigned idx1 = 1; // dst
34038 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
34039 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp
34040 {
34041 C2_MacroAssembler _masm(&cbuf);
34042
34043#line 4746 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
34044
34045 int opcode = this->ideal_Opcode();
34046 int vlen = Matcher::vector_length(this, opnd_array(2));
34047 ___masm. reduce_fp(opcode, vlen, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp */);
34048
34049#line 34049 "ad_x86.cpp"
34050 }
34051}
34052
34053void reduction8FNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34054 cbuf.set_insts_mark();
34055 // Start at oper_input_base() and count operands
34056 unsigned idx0 = 1;
34057 unsigned idx1 = 1; // dst
34058 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
34059 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1
34060 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2
34061 {
34062 C2_MacroAssembler _masm(&cbuf);
34063
34064#line 4760 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
34065
34066 int opcode = this->ideal_Opcode();
34067 int vlen = Matcher::vector_length(this, opnd_array(2));
34068 ___masm. reduce_fp(opcode, vlen, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp2 */);
34069
34070#line 34070 "ad_x86.cpp"
34071 }
34072}
34073
34074void reduction8F_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34075 cbuf.set_insts_mark();
34076 // Start at oper_input_base() and count operands
34077 unsigned idx0 = 1;
34078 unsigned idx1 = 1; // dst
34079 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
34080 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1
34081 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2
34082 {
34083 C2_MacroAssembler _masm(&cbuf);
34084
34085#line 4760 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
34086
34087 int opcode = this->ideal_Opcode();
34088 int vlen = Matcher::vector_length(this, opnd_array(2));
34089 ___masm. reduce_fp(opcode, vlen, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp2 */);
34090
34091#line 34091 "ad_x86.cpp"
34092 }
34093}
34094
34095void reduction16FNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34096 cbuf.set_insts_mark();
34097 // Start at oper_input_base() and count operands
34098 unsigned idx0 = 1;
34099 unsigned idx1 = 1; // dst
34100 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
34101 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1
34102 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2
34103 {
34104 C2_MacroAssembler _masm(&cbuf);
34105
34106#line 4774 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
34107
34108 int opcode = this->ideal_Opcode();
34109 int vlen = Matcher::vector_length(this, opnd_array(2));
34110 ___masm. reduce_fp(opcode, vlen, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp2 */);
34111
34112#line 34112 "ad_x86.cpp"
34113 }
34114}
34115
34116void reduction16F_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34117 cbuf.set_insts_mark();
34118 // Start at oper_input_base() and count operands
34119 unsigned idx0 = 1;
34120 unsigned idx1 = 1; // dst
34121 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
34122 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1
34123 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2
34124 {
34125 C2_MacroAssembler _masm(&cbuf);
34126
34127#line 4774 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
34128
34129 int opcode = this->ideal_Opcode();
34130 int vlen = Matcher::vector_length(this, opnd_array(2));
34131 ___masm. reduce_fp(opcode, vlen, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp2 */);
34132
34133#line 34133 "ad_x86.cpp"
34134 }
34135}
34136
34137void reduction2DNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34138 cbuf.set_insts_mark();
34139 // Start at oper_input_base() and count operands
34140 unsigned idx0 = 1;
34141 unsigned idx1 = 1; // dst
34142 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
34143 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp
34144 {
34145 C2_MacroAssembler _masm(&cbuf);
34146
34147#line 4790 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
34148
34149 int opcode = this->ideal_Opcode();
34150 int vlen = Matcher::vector_length(this, opnd_array(2));
34151 ___masm. reduce_fp(opcode, vlen, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp */);
34152
34153#line 34153 "ad_x86.cpp"
34154 }
34155}
34156
34157void reduction2D_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34158 cbuf.set_insts_mark();
34159 // Start at oper_input_base() and count operands
34160 unsigned idx0 = 1;
34161 unsigned idx1 = 1; // dst
34162 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
34163 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp
34164 {
34165 C2_MacroAssembler _masm(&cbuf);
34166
34167#line 4790 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
34168
34169 int opcode = this->ideal_Opcode();
34170 int vlen = Matcher::vector_length(this, opnd_array(2));
34171 ___masm. reduce_fp(opcode, vlen, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp */);
34172
34173#line 34173 "ad_x86.cpp"
34174 }
34175}
34176
34177void reduction4DNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34178 cbuf.set_insts_mark();
34179 // Start at oper_input_base() and count operands
34180 unsigned idx0 = 1;
34181 unsigned idx1 = 1; // dst
34182 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
34183 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1
34184 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2
34185 {
34186 C2_MacroAssembler _masm(&cbuf);
34187
34188#line 4804 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
34189
34190 int opcode = this->ideal_Opcode();
34191 int vlen = Matcher::vector_length(this, opnd_array(2));
34192 ___masm. reduce_fp(opcode, vlen, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp2 */);
34193
34194#line 34194 "ad_x86.cpp"
34195 }
34196}
34197
34198void reduction4D_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34199 cbuf.set_insts_mark();
34200 // Start at oper_input_base() and count operands
34201 unsigned idx0 = 1;
34202 unsigned idx1 = 1; // dst
34203 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
34204 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1
34205 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2
34206 {
34207 C2_MacroAssembler _masm(&cbuf);
34208
34209#line 4804 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
34210
34211 int opcode = this->ideal_Opcode();
34212 int vlen = Matcher::vector_length(this, opnd_array(2));
34213 ___masm. reduce_fp(opcode, vlen, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp2 */);
34214
34215#line 34215 "ad_x86.cpp"
34216 }
34217}
34218
34219void reduction8DNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34220 cbuf.set_insts_mark();
34221 // Start at oper_input_base() and count operands
34222 unsigned idx0 = 1;
34223 unsigned idx1 = 1; // dst
34224 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
34225 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1
34226 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2
34227 {
34228 C2_MacroAssembler _masm(&cbuf);
34229
34230#line 4818 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
34231
34232 int opcode = this->ideal_Opcode();
34233 int vlen = Matcher::vector_length(this, opnd_array(2));
34234 ___masm. reduce_fp(opcode, vlen, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp2 */);
34235
34236#line 34236 "ad_x86.cpp"
34237 }
34238}
34239
34240void reduction8D_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34241 cbuf.set_insts_mark();
34242 // Start at oper_input_base() and count operands
34243 unsigned idx0 = 1;
34244 unsigned idx1 = 1; // dst
34245 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
34246 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1
34247 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2
34248 {
34249 C2_MacroAssembler _masm(&cbuf);
34250
34251#line 4818 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
34252
34253 int opcode = this->ideal_Opcode();
34254 int vlen = Matcher::vector_length(this, opnd_array(2));
34255 ___masm. reduce_fp(opcode, vlen, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp2 */);
34256
34257#line 34257 "ad_x86.cpp"
34258 }
34259}
34260
34261void reductionBNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34262 cbuf.set_insts_mark();
34263 // Start at oper_input_base() and count operands
34264 unsigned idx0 = 1;
34265 unsigned idx1 = 1; // src1
34266 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
34267 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1
34268 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2
34269 {
34270 C2_MacroAssembler _masm(&cbuf);
34271
34272#line 4839 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
34273
34274 int opcode = this->ideal_Opcode();
34275 int vlen = Matcher::vector_length(this, opnd_array(2));
34276 ___masm. reduceB(opcode, vlen, opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp2 */);
34277
34278#line 34278 "ad_x86.cpp"
34279 }
34280}
34281
34282void reductionB_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34283 cbuf.set_insts_mark();
34284 // Start at oper_input_base() and count operands
34285 unsigned idx0 = 1;
34286 unsigned idx1 = 1; // src1
34287 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
34288 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1
34289 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2
34290 {
34291 C2_MacroAssembler _masm(&cbuf);
34292
34293#line 4839 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
34294
34295 int opcode = this->ideal_Opcode();
34296 int vlen = Matcher::vector_length(this, opnd_array(2));
34297 ___masm. reduceB(opcode, vlen, opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp2 */);
34298
34299#line 34299 "ad_x86.cpp"
34300 }
34301}
34302
34303void reductionB_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34304 cbuf.set_insts_mark();
34305 // Start at oper_input_base() and count operands
34306 unsigned idx0 = 1;
34307 unsigned idx1 = 1; // src1
34308 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
34309 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1
34310 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2
34311 {
34312 C2_MacroAssembler _masm(&cbuf);
34313
34314#line 4839 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
34315
34316 int opcode = this->ideal_Opcode();
34317 int vlen = Matcher::vector_length(this, opnd_array(2));
34318 ___masm. reduceB(opcode, vlen, opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp2 */);
34319
34320#line 34320 "ad_x86.cpp"
34321 }
34322}
34323
34324void reductionB_2Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34325 cbuf.set_insts_mark();
34326 // Start at oper_input_base() and count operands
34327 unsigned idx0 = 1;
34328 unsigned idx1 = 1; // src1
34329 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
34330 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1
34331 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2
34332 {
34333 C2_MacroAssembler _masm(&cbuf);
34334
34335#line 4839 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
34336
34337 int opcode = this->ideal_Opcode();
34338 int vlen = Matcher::vector_length(this, opnd_array(2));
34339 ___masm. reduceB(opcode, vlen, opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp2 */);
34340
34341#line 34341 "ad_x86.cpp"
34342 }
34343}
34344
34345void reductionB_3Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34346 cbuf.set_insts_mark();
34347 // Start at oper_input_base() and count operands
34348 unsigned idx0 = 1;
34349 unsigned idx1 = 1; // src1
34350 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
34351 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1
34352 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2
34353 {
34354 C2_MacroAssembler _masm(&cbuf);
34355
34356#line 4839 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
34357
34358 int opcode = this->ideal_Opcode();
34359 int vlen = Matcher::vector_length(this, opnd_array(2));
34360 ___masm. reduceB(opcode, vlen, opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp2 */);
34361
34362#line 34362 "ad_x86.cpp"
34363 }
34364}
34365
34366void reductionB_4Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34367 cbuf.set_insts_mark();
34368 // Start at oper_input_base() and count operands
34369 unsigned idx0 = 1;
34370 unsigned idx1 = 1; // src1
34371 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
34372 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1
34373 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2
34374 {
34375 C2_MacroAssembler _masm(&cbuf);
34376
34377#line 4839 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
34378
34379 int opcode = this->ideal_Opcode();
34380 int vlen = Matcher::vector_length(this, opnd_array(2));
34381 ___masm. reduceB(opcode, vlen, opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp2 */);
34382
34383#line 34383 "ad_x86.cpp"
34384 }
34385}
34386
34387void reductionB_avx512bwNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34388 cbuf.set_insts_mark();
34389 // Start at oper_input_base() and count operands
34390 unsigned idx0 = 1;
34391 unsigned idx1 = 1; // src1
34392 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
34393 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1
34394 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2
34395 {
34396 C2_MacroAssembler _masm(&cbuf);
34397
34398#line 4857 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
34399
34400 int opcode = this->ideal_Opcode();
34401 int vlen = Matcher::vector_length(this, opnd_array(2));
34402 ___masm. reduceB(opcode, vlen, opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp2 */);
34403
34404#line 34404 "ad_x86.cpp"
34405 }
34406}
34407
34408void reductionB_avx512bw_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34409 cbuf.set_insts_mark();
34410 // Start at oper_input_base() and count operands
34411 unsigned idx0 = 1;
34412 unsigned idx1 = 1; // src1
34413 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
34414 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1
34415 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2
34416 {
34417 C2_MacroAssembler _masm(&cbuf);
34418
34419#line 4857 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
34420
34421 int opcode = this->ideal_Opcode();
34422 int vlen = Matcher::vector_length(this, opnd_array(2));
34423 ___masm. reduceB(opcode, vlen, opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp2 */);
34424
34425#line 34425 "ad_x86.cpp"
34426 }
34427}
34428
34429void reductionB_avx512bw_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34430 cbuf.set_insts_mark();
34431 // Start at oper_input_base() and count operands
34432 unsigned idx0 = 1;
34433 unsigned idx1 = 1; // src1
34434 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
34435 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1
34436 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2
34437 {
34438 C2_MacroAssembler _masm(&cbuf);
34439
34440#line 4857 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
34441
34442 int opcode = this->ideal_Opcode();
34443 int vlen = Matcher::vector_length(this, opnd_array(2));
34444 ___masm. reduceB(opcode, vlen, opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp2 */);
34445
34446#line 34446 "ad_x86.cpp"
34447 }
34448}
34449
34450void reductionB_avx512bw_2Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34451 cbuf.set_insts_mark();
34452 // Start at oper_input_base() and count operands
34453 unsigned idx0 = 1;
34454 unsigned idx1 = 1; // src1
34455 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
34456 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1
34457 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2
34458 {
34459 C2_MacroAssembler _masm(&cbuf);
34460
34461#line 4857 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
34462
34463 int opcode = this->ideal_Opcode();
34464 int vlen = Matcher::vector_length(this, opnd_array(2));
34465 ___masm. reduceB(opcode, vlen, opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp2 */);
34466
34467#line 34467 "ad_x86.cpp"
34468 }
34469}
34470
34471void reductionB_avx512bw_3Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34472 cbuf.set_insts_mark();
34473 // Start at oper_input_base() and count operands
34474 unsigned idx0 = 1;
34475 unsigned idx1 = 1; // src1
34476 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
34477 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1
34478 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2
34479 {
34480 C2_MacroAssembler _masm(&cbuf);
34481
34482#line 4857 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
34483
34484 int opcode = this->ideal_Opcode();
34485 int vlen = Matcher::vector_length(this, opnd_array(2));
34486 ___masm. reduceB(opcode, vlen, opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp2 */);
34487
34488#line 34488 "ad_x86.cpp"
34489 }
34490}
34491
34492void reductionB_avx512bw_4Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34493 cbuf.set_insts_mark();
34494 // Start at oper_input_base() and count operands
34495 unsigned idx0 = 1;
34496 unsigned idx1 = 1; // src1
34497 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
34498 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1
34499 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2
34500 {
34501 C2_MacroAssembler _masm(&cbuf);
34502
34503#line 4857 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
34504
34505 int opcode = this->ideal_Opcode();
34506 int vlen = Matcher::vector_length(this, opnd_array(2));
34507 ___masm. reduceB(opcode, vlen, opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp2 */);
34508
34509#line 34509 "ad_x86.cpp"
34510 }
34511}
34512
34513void reductionSNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34514 cbuf.set_insts_mark();
34515 // Start at oper_input_base() and count operands
34516 unsigned idx0 = 1;
34517 unsigned idx1 = 1; // src1
34518 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
34519 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1
34520 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2
34521 {
34522 C2_MacroAssembler _masm(&cbuf);
34523
34524#line 4879 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
34525
34526 int opcode = this->ideal_Opcode();
34527 int vlen = Matcher::vector_length(this, opnd_array(2));
34528 ___masm. reduceS(opcode, vlen, opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp2 */);
34529
34530#line 34530 "ad_x86.cpp"
34531 }
34532}
34533
34534void reductionS_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34535 cbuf.set_insts_mark();
34536 // Start at oper_input_base() and count operands
34537 unsigned idx0 = 1;
34538 unsigned idx1 = 1; // src1
34539 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
34540 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1
34541 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2
34542 {
34543 C2_MacroAssembler _masm(&cbuf);
34544
34545#line 4879 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
34546
34547 int opcode = this->ideal_Opcode();
34548 int vlen = Matcher::vector_length(this, opnd_array(2));
34549 ___masm. reduceS(opcode, vlen, opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp2 */);
34550
34551#line 34551 "ad_x86.cpp"
34552 }
34553}
34554
34555void reductionS_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34556 cbuf.set_insts_mark();
34557 // Start at oper_input_base() and count operands
34558 unsigned idx0 = 1;
34559 unsigned idx1 = 1; // src1
34560 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
34561 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1
34562 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2
34563 {
34564 C2_MacroAssembler _masm(&cbuf);
34565
34566#line 4879 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
34567
34568 int opcode = this->ideal_Opcode();
34569 int vlen = Matcher::vector_length(this, opnd_array(2));
34570 ___masm. reduceS(opcode, vlen, opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp2 */);
34571
34572#line 34572 "ad_x86.cpp"
34573 }
34574}
34575
34576void reductionS_2Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34577 cbuf.set_insts_mark();
34578 // Start at oper_input_base() and count operands
34579 unsigned idx0 = 1;
34580 unsigned idx1 = 1; // src1
34581 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
34582 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1
34583 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2
34584 {
34585 C2_MacroAssembler _masm(&cbuf);
34586
34587#line 4879 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
34588
34589 int opcode = this->ideal_Opcode();
34590 int vlen = Matcher::vector_length(this, opnd_array(2));
34591 ___masm. reduceS(opcode, vlen, opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp2 */);
34592
34593#line 34593 "ad_x86.cpp"
34594 }
34595}
34596
34597void reductionS_3Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34598 cbuf.set_insts_mark();
34599 // Start at oper_input_base() and count operands
34600 unsigned idx0 = 1;
34601 unsigned idx1 = 1; // src1
34602 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
34603 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1
34604 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2
34605 {
34606 C2_MacroAssembler _masm(&cbuf);
34607
34608#line 4879 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
34609
34610 int opcode = this->ideal_Opcode();
34611 int vlen = Matcher::vector_length(this, opnd_array(2));
34612 ___masm. reduceS(opcode, vlen, opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp2 */);
34613
34614#line 34614 "ad_x86.cpp"
34615 }
34616}
34617
34618void reductionS_4Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34619 cbuf.set_insts_mark();
34620 // Start at oper_input_base() and count operands
34621 unsigned idx0 = 1;
34622 unsigned idx1 = 1; // src1
34623 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
34624 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1
34625 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2
34626 {
34627 C2_MacroAssembler _masm(&cbuf);
34628
34629#line 4879 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
34630
34631 int opcode = this->ideal_Opcode();
34632 int vlen = Matcher::vector_length(this, opnd_array(2));
34633 ___masm. reduceS(opcode, vlen, opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp2 */);
34634
34635#line 34635 "ad_x86.cpp"
34636 }
34637}
34638
34639void reductionS_5Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34640 cbuf.set_insts_mark();
34641 // Start at oper_input_base() and count operands
34642 unsigned idx0 = 1;
34643 unsigned idx1 = 1; // src1
34644 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
34645 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1
34646 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2
34647 {
34648 C2_MacroAssembler _masm(&cbuf);
34649
34650#line 4879 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
34651
34652 int opcode = this->ideal_Opcode();
34653 int vlen = Matcher::vector_length(this, opnd_array(2));
34654 ___masm. reduceS(opcode, vlen, opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp2 */);
34655
34656#line 34656 "ad_x86.cpp"
34657 }
34658}
34659
34660void mul_reductionBNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34661 cbuf.set_insts_mark();
34662 // Start at oper_input_base() and count operands
34663 unsigned idx0 = 1;
34664 unsigned idx1 = 1; // src1
34665 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
34666 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
34667 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp1
34668 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // vtmp2
34669 {
34670 C2_MacroAssembler _masm(&cbuf);
34671
34672#line 4895 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
34673
34674 int opcode = this->ideal_Opcode();
34675 int vlen = Matcher::vector_length(this, opnd_array(2));
34676 ___masm. mulreduceB(opcode, vlen, opnd_array(3)->as_Register(ra_,this,idx3)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */);
34677
34678#line 34678 "ad_x86.cpp"
34679 }
34680}
34681
34682void mul_reduction64BNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34683 cbuf.set_insts_mark();
34684 // Start at oper_input_base() and count operands
34685 unsigned idx0 = 1;
34686 unsigned idx1 = 1; // src1
34687 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
34688 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
34689 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp1
34690 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // vtmp2
34691 {
34692 C2_MacroAssembler _masm(&cbuf);
34693
34694#line 4909 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
34695
34696 int opcode = this->ideal_Opcode();
34697 int vlen = Matcher::vector_length(this, opnd_array(2));
34698 ___masm. mulreduceB(opcode, vlen, opnd_array(3)->as_Register(ra_,this,idx3)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */);
34699
34700#line 34700 "ad_x86.cpp"
34701 }
34702}
34703
34704void minmax_reduction2FNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34705 cbuf.set_insts_mark();
34706 // Start at oper_input_base() and count operands
34707 unsigned idx0 = 1;
34708 unsigned idx1 = 1; // src1
34709 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
34710 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
34711 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
34712 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // atmp
34713 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // btmp
34714 unsigned idx7 = idx6 + opnd_array(6)->num_edges(); // xmm_1
34715 {
34716 C2_MacroAssembler _masm(&cbuf);
34717
34718#line 4929 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
34719
34720 assert(UseAVX > 0, "sanity")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
4930, "assert(" "UseAVX > 0" ") failed", "sanity"); ::breakpoint
(); } } while (0);
34721
34722 int opcode = this->ideal_Opcode();
34723 int vlen = Matcher::vector_length(this, opnd_array(2));
34724 ___masm. reduceFloatMinMax(opcode, vlen, false, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */,
34725 opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* atmp */, opnd_array(6)->as_XMMRegister(ra_,this,idx6)/* btmp */, opnd_array(7)->as_XMMRegister(ra_,this,idx7)/* xmm_1 */);
34726
34727#line 34727 "ad_x86.cpp"
34728 }
34729}
34730
34731void minmax_reduction2F_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34732 cbuf.set_insts_mark();
34733 // Start at oper_input_base() and count operands
34734 unsigned idx0 = 1;
34735 unsigned idx1 = 1; // src1
34736 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
34737 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
34738 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
34739 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // atmp
34740 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // btmp
34741 unsigned idx7 = idx6 + opnd_array(6)->num_edges(); // xmm_1
34742 {
34743 C2_MacroAssembler _masm(&cbuf);
34744
34745#line 4929 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
34746
34747 assert(UseAVX > 0, "sanity")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
4930, "assert(" "UseAVX > 0" ") failed", "sanity"); ::breakpoint
(); } } while (0);
34748
34749 int opcode = this->ideal_Opcode();
34750 int vlen = Matcher::vector_length(this, opnd_array(2));
34751 ___masm. reduceFloatMinMax(opcode, vlen, false, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */,
34752 opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* atmp */, opnd_array(6)->as_XMMRegister(ra_,this,idx6)/* btmp */, opnd_array(7)->as_XMMRegister(ra_,this,idx7)/* xmm_1 */);
34753
34754#line 34754 "ad_x86.cpp"
34755 }
34756}
34757
34758void minmax_reductionFNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34759 cbuf.set_insts_mark();
34760 // Start at oper_input_base() and count operands
34761 unsigned idx0 = 1;
34762 unsigned idx1 = 1; // src1
34763 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
34764 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
34765 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
34766 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // atmp
34767 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // btmp
34768 unsigned idx7 = idx6 + opnd_array(6)->num_edges(); // xmm_0
34769 unsigned idx8 = idx7 + opnd_array(7)->num_edges(); // xmm_1
34770 {
34771 C2_MacroAssembler _masm(&cbuf);
34772
34773#line 4950 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
34774
34775 assert(UseAVX > 0, "sanity")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
4951, "assert(" "UseAVX > 0" ") failed", "sanity"); ::breakpoint
(); } } while (0);
34776
34777 int opcode = this->ideal_Opcode();
34778 int vlen = Matcher::vector_length(this, opnd_array(2));
34779 ___masm. reduceFloatMinMax(opcode, vlen, false, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */,
34780 opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* atmp */, opnd_array(6)->as_XMMRegister(ra_,this,idx6)/* btmp */, opnd_array(7)->as_XMMRegister(ra_,this,idx7)/* xmm_0 */, opnd_array(8)->as_XMMRegister(ra_,this,idx8)/* xmm_1 */);
34781
34782#line 34782 "ad_x86.cpp"
34783 }
34784}
34785
34786void minmax_reductionF_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34787 cbuf.set_insts_mark();
34788 // Start at oper_input_base() and count operands
34789 unsigned idx0 = 1;
34790 unsigned idx1 = 1; // src1
34791 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
34792 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
34793 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
34794 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // atmp
34795 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // btmp
34796 unsigned idx7 = idx6 + opnd_array(6)->num_edges(); // xmm_0
34797 unsigned idx8 = idx7 + opnd_array(7)->num_edges(); // xmm_1
34798 {
34799 C2_MacroAssembler _masm(&cbuf);
34800
34801#line 4950 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
34802
34803 assert(UseAVX > 0, "sanity")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
4951, "assert(" "UseAVX > 0" ") failed", "sanity"); ::breakpoint
(); } } while (0);
34804
34805 int opcode = this->ideal_Opcode();
34806 int vlen = Matcher::vector_length(this, opnd_array(2));
34807 ___masm. reduceFloatMinMax(opcode, vlen, false, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */,
34808 opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* atmp */, opnd_array(6)->as_XMMRegister(ra_,this,idx6)/* btmp */, opnd_array(7)->as_XMMRegister(ra_,this,idx7)/* xmm_0 */, opnd_array(8)->as_XMMRegister(ra_,this,idx8)/* xmm_1 */);
34809
34810#line 34810 "ad_x86.cpp"
34811 }
34812}
34813
34814void minmax_reduction2F_avNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34815 cbuf.set_insts_mark();
34816 // Start at oper_input_base() and count operands
34817 unsigned idx0 = 1;
34818 unsigned idx1 = 1; // dst
34819 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
34820 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
34821 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // atmp
34822 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // btmp
34823 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // xmm_1
34824 {
34825 C2_MacroAssembler _masm(&cbuf);
34826
34827#line 4969 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
34828
34829 assert(UseAVX > 0, "sanity")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
4970, "assert(" "UseAVX > 0" ") failed", "sanity"); ::breakpoint
(); } } while (0);
34830
34831 int opcode = this->ideal_Opcode();
34832 int vlen = Matcher::vector_length(this, opnd_array(2));
34833 ___masm. reduceFloatMinMax(opcode, vlen, true, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */,
34834 opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* atmp */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* btmp */, opnd_array(6)->as_XMMRegister(ra_,this,idx6)/* xmm_1 */);
34835
34836#line 34836 "ad_x86.cpp"
34837 }
34838}
34839
34840void minmax_reduction2F_av_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34841 cbuf.set_insts_mark();
34842 // Start at oper_input_base() and count operands
34843 unsigned idx0 = 1;
34844 unsigned idx1 = 1; // dst
34845 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
34846 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
34847 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // atmp
34848 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // btmp
34849 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // xmm_1
34850 {
34851 C2_MacroAssembler _masm(&cbuf);
34852
34853#line 4969 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
34854
34855 assert(UseAVX > 0, "sanity")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
4970, "assert(" "UseAVX > 0" ") failed", "sanity"); ::breakpoint
(); } } while (0);
34856
34857 int opcode = this->ideal_Opcode();
34858 int vlen = Matcher::vector_length(this, opnd_array(2));
34859 ___masm. reduceFloatMinMax(opcode, vlen, true, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */,
34860 opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* atmp */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* btmp */, opnd_array(6)->as_XMMRegister(ra_,this,idx6)/* xmm_1 */);
34861
34862#line 34862 "ad_x86.cpp"
34863 }
34864}
34865
34866void minmax_reductionF_avNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34867 cbuf.set_insts_mark();
34868 // Start at oper_input_base() and count operands
34869 unsigned idx0 = 1;
34870 unsigned idx1 = 1; // dst
34871 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
34872 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
34873 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // atmp
34874 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // btmp
34875 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // xmm_0
34876 unsigned idx7 = idx6 + opnd_array(6)->num_edges(); // xmm_1
34877 {
34878 C2_MacroAssembler _masm(&cbuf);
34879
34880#line 4989 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
34881
34882 assert(UseAVX > 0, "sanity")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
4990, "assert(" "UseAVX > 0" ") failed", "sanity"); ::breakpoint
(); } } while (0);
34883
34884 int opcode = this->ideal_Opcode();
34885 int vlen = Matcher::vector_length(this, opnd_array(2));
34886 ___masm. reduceFloatMinMax(opcode, vlen, true, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */,
34887 opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* atmp */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* btmp */, opnd_array(6)->as_XMMRegister(ra_,this,idx6)/* xmm_0 */, opnd_array(7)->as_XMMRegister(ra_,this,idx7)/* xmm_1 */);
34888
34889#line 34889 "ad_x86.cpp"
34890 }
34891}
34892
34893void minmax_reductionF_av_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34894 cbuf.set_insts_mark();
34895 // Start at oper_input_base() and count operands
34896 unsigned idx0 = 1;
34897 unsigned idx1 = 1; // dst
34898 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
34899 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
34900 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // atmp
34901 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // btmp
34902 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // xmm_0
34903 unsigned idx7 = idx6 + opnd_array(6)->num_edges(); // xmm_1
34904 {
34905 C2_MacroAssembler _masm(&cbuf);
34906
34907#line 4989 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
34908
34909 assert(UseAVX > 0, "sanity")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
4990, "assert(" "UseAVX > 0" ") failed", "sanity"); ::breakpoint
(); } } while (0);
34910
34911 int opcode = this->ideal_Opcode();
34912 int vlen = Matcher::vector_length(this, opnd_array(2));
34913 ___masm. reduceFloatMinMax(opcode, vlen, true, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */,
34914 opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* atmp */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* btmp */, opnd_array(6)->as_XMMRegister(ra_,this,idx6)/* xmm_0 */, opnd_array(7)->as_XMMRegister(ra_,this,idx7)/* xmm_1 */);
34915
34916#line 34916 "ad_x86.cpp"
34917 }
34918}
34919
34920void minmax_reduction2DNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34921 cbuf.set_insts_mark();
34922 // Start at oper_input_base() and count operands
34923 unsigned idx0 = 1;
34924 unsigned idx1 = 1; // src1
34925 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
34926 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
34927 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
34928 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
34929 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // tmp3
34930 unsigned idx7 = idx6 + opnd_array(6)->num_edges(); // tmp4
34931 {
34932 C2_MacroAssembler _masm(&cbuf);
34933
34934#line 5013 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
34935
34936 assert(UseAVX > 0, "sanity")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
5014, "assert(" "UseAVX > 0" ") failed", "sanity"); ::breakpoint
(); } } while (0);
34937
34938 int opcode = this->ideal_Opcode();
34939 int vlen = Matcher::vector_length(this, opnd_array(2));
34940 ___masm. reduceDoubleMinMax(opcode, vlen, false, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */,
34941 opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(6)->as_XMMRegister(ra_,this,idx6)/* tmp3 */, opnd_array(7)->as_XMMRegister(ra_,this,idx7)/* tmp4 */);
34942
34943#line 34943 "ad_x86.cpp"
34944 }
34945}
34946
34947void minmax_reduction2D_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34948 cbuf.set_insts_mark();
34949 // Start at oper_input_base() and count operands
34950 unsigned idx0 = 1;
34951 unsigned idx1 = 1; // src1
34952 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
34953 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
34954 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
34955 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
34956 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // tmp3
34957 unsigned idx7 = idx6 + opnd_array(6)->num_edges(); // tmp4
34958 {
34959 C2_MacroAssembler _masm(&cbuf);
34960
34961#line 5013 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
34962
34963 assert(UseAVX > 0, "sanity")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
5014, "assert(" "UseAVX > 0" ") failed", "sanity"); ::breakpoint
(); } } while (0);
34964
34965 int opcode = this->ideal_Opcode();
34966 int vlen = Matcher::vector_length(this, opnd_array(2));
34967 ___masm. reduceDoubleMinMax(opcode, vlen, false, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */,
34968 opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(6)->as_XMMRegister(ra_,this,idx6)/* tmp3 */, opnd_array(7)->as_XMMRegister(ra_,this,idx7)/* tmp4 */);
34969
34970#line 34970 "ad_x86.cpp"
34971 }
34972}
34973
34974void minmax_reductionDNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
34975 cbuf.set_insts_mark();
34976 // Start at oper_input_base() and count operands
34977 unsigned idx0 = 1;
34978 unsigned idx1 = 1; // src1
34979 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
34980 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
34981 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
34982 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
34983 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // tmp3
34984 unsigned idx7 = idx6 + opnd_array(6)->num_edges(); // tmp4
34985 unsigned idx8 = idx7 + opnd_array(7)->num_edges(); // tmp5
34986 {
34987 C2_MacroAssembler _masm(&cbuf);
34988
34989#line 5035 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
34990
34991 assert(UseAVX > 0, "sanity")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
5036, "assert(" "UseAVX > 0" ") failed", "sanity"); ::breakpoint
(); } } while (0);
34992
34993 int opcode = this->ideal_Opcode();
34994 int vlen = Matcher::vector_length(this, opnd_array(2));
34995 ___masm. reduceDoubleMinMax(opcode, vlen, false, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */,
34996 opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(6)->as_XMMRegister(ra_,this,idx6)/* tmp3 */, opnd_array(7)->as_XMMRegister(ra_,this,idx7)/* tmp4 */, opnd_array(8)->as_XMMRegister(ra_,this,idx8)/* tmp5 */);
34997
34998#line 34998 "ad_x86.cpp"
34999 }
35000}
35001
35002void minmax_reductionD_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35003 cbuf.set_insts_mark();
35004 // Start at oper_input_base() and count operands
35005 unsigned idx0 = 1;
35006 unsigned idx1 = 1; // src1
35007 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
35008 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
35009 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
35010 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
35011 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // tmp3
35012 unsigned idx7 = idx6 + opnd_array(6)->num_edges(); // tmp4
35013 unsigned idx8 = idx7 + opnd_array(7)->num_edges(); // tmp5
35014 {
35015 C2_MacroAssembler _masm(&cbuf);
35016
35017#line 5035 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
35018
35019 assert(UseAVX > 0, "sanity")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
5036, "assert(" "UseAVX > 0" ") failed", "sanity"); ::breakpoint
(); } } while (0);
35020
35021 int opcode = this->ideal_Opcode();
35022 int vlen = Matcher::vector_length(this, opnd_array(2));
35023 ___masm. reduceDoubleMinMax(opcode, vlen, false, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */,
35024 opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(6)->as_XMMRegister(ra_,this,idx6)/* tmp3 */, opnd_array(7)->as_XMMRegister(ra_,this,idx7)/* tmp4 */, opnd_array(8)->as_XMMRegister(ra_,this,idx8)/* tmp5 */);
35025
35026#line 35026 "ad_x86.cpp"
35027 }
35028}
35029
35030void minmax_reduction2D_avNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35031 cbuf.set_insts_mark();
35032 // Start at oper_input_base() and count operands
35033 unsigned idx0 = 1;
35034 unsigned idx1 = 1; // dst
35035 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
35036 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp1
35037 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
35038 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp3
35039 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // tmp4
35040 {
35041 C2_MacroAssembler _masm(&cbuf);
35042
35043#line 5056 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
35044
35045 assert(UseAVX > 0, "sanity")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
5057, "assert(" "UseAVX > 0" ") failed", "sanity"); ::breakpoint
(); } } while (0);
35046
35047 int opcode = this->ideal_Opcode();
35048 int vlen = Matcher::vector_length(this, opnd_array(2));
35049 ___masm. reduceDoubleMinMax(opcode, vlen, true, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */,
35050 opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp3 */, opnd_array(6)->as_XMMRegister(ra_,this,idx6)/* tmp4 */);
35051
35052#line 35052 "ad_x86.cpp"
35053 }
35054}
35055
35056void minmax_reduction2D_av_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35057 cbuf.set_insts_mark();
35058 // Start at oper_input_base() and count operands
35059 unsigned idx0 = 1;
35060 unsigned idx1 = 1; // dst
35061 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
35062 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp1
35063 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
35064 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp3
35065 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // tmp4
35066 {
35067 C2_MacroAssembler _masm(&cbuf);
35068
35069#line 5056 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
35070
35071 assert(UseAVX > 0, "sanity")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
5057, "assert(" "UseAVX > 0" ") failed", "sanity"); ::breakpoint
(); } } while (0);
35072
35073 int opcode = this->ideal_Opcode();
35074 int vlen = Matcher::vector_length(this, opnd_array(2));
35075 ___masm. reduceDoubleMinMax(opcode, vlen, true, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */,
35076 opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp3 */, opnd_array(6)->as_XMMRegister(ra_,this,idx6)/* tmp4 */);
35077
35078#line 35078 "ad_x86.cpp"
35079 }
35080}
35081
35082void minmax_reductionD_avNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35083 cbuf.set_insts_mark();
35084 // Start at oper_input_base() and count operands
35085 unsigned idx0 = 1;
35086 unsigned idx1 = 1; // dst
35087 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
35088 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp1
35089 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
35090 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp3
35091 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // tmp4
35092 unsigned idx7 = idx6 + opnd_array(6)->num_edges(); // tmp5
35093 {
35094 C2_MacroAssembler _masm(&cbuf);
35095
35096#line 5076 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
35097
35098 assert(UseAVX > 0, "sanity")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
5077, "assert(" "UseAVX > 0" ") failed", "sanity"); ::breakpoint
(); } } while (0);
35099
35100 int opcode = this->ideal_Opcode();
35101 int vlen = Matcher::vector_length(this, opnd_array(2));
35102 ___masm. reduceDoubleMinMax(opcode, vlen, true, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */,
35103 opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp3 */, opnd_array(6)->as_XMMRegister(ra_,this,idx6)/* tmp4 */, opnd_array(7)->as_XMMRegister(ra_,this,idx7)/* tmp5 */);
35104
35105#line 35105 "ad_x86.cpp"
35106 }
35107}
35108
35109void minmax_reductionD_av_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35110 cbuf.set_insts_mark();
35111 // Start at oper_input_base() and count operands
35112 unsigned idx0 = 1;
35113 unsigned idx1 = 1; // dst
35114 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
35115 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp1
35116 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
35117 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp3
35118 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // tmp4
35119 unsigned idx7 = idx6 + opnd_array(6)->num_edges(); // tmp5
35120 {
35121 C2_MacroAssembler _masm(&cbuf);
35122
35123#line 5076 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
35124
35125 assert(UseAVX > 0, "sanity")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
5077, "assert(" "UseAVX > 0" ") failed", "sanity"); ::breakpoint
(); } } while (0);
35126
35127 int opcode = this->ideal_Opcode();
35128 int vlen = Matcher::vector_length(this, opnd_array(2));
35129 ___masm. reduceDoubleMinMax(opcode, vlen, true, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */,
35130 opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp2 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp3 */, opnd_array(6)->as_XMMRegister(ra_,this,idx6)/* tmp4 */, opnd_array(7)->as_XMMRegister(ra_,this,idx7)/* tmp5 */);
35131
35132#line 35132 "ad_x86.cpp"
35133 }
35134}
35135
35136void vaddBNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35137 cbuf.set_insts_mark();
35138 // Start at oper_input_base() and count operands
35139 unsigned idx0 = 1;
35140 unsigned idx1 = 1; // dst
35141 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
35142 {
35143 C2_MacroAssembler _masm(&cbuf);
35144
35145#line 5096 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
35146
35147 ___masm. paddb(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
35148
35149#line 35149 "ad_x86.cpp"
35150 }
35151}
35152
35153void vaddB_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35154 cbuf.set_insts_mark();
35155 // Start at oper_input_base() and count operands
35156 unsigned idx0 = 1;
35157 unsigned idx1 = 1; // src1
35158 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
35159 {
35160 C2_MacroAssembler _masm(&cbuf);
35161
35162#line 5106 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
35163
35164 int vlen_enc = vector_length_encoding(this);
35165 ___masm. vpaddb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vlen_enc);
35166
35167#line 35167 "ad_x86.cpp"
35168 }
35169}
35170
35171void vaddB_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35172 cbuf.set_insts_mark();
35173 // Start at oper_input_base() and count operands
35174 unsigned idx0 = 2;
35175 unsigned idx1 = 2; // src
35176 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
35177 {
35178 C2_MacroAssembler _masm(&cbuf);
35179
35180#line 5118 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
35181
35182 int vlen_enc = vector_length_encoding(this);
35183 ___masm. vpaddb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vlen_enc);
35184
35185#line 35185 "ad_x86.cpp"
35186 }
35187}
35188
35189void vaddB_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35190 cbuf.set_insts_mark();
35191 // Start at oper_input_base() and count operands
35192 unsigned idx0 = 2;
35193 unsigned idx1 = 2; // mem
35194 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
35195 {
35196 C2_MacroAssembler _masm(&cbuf);
35197
35198#line 5118 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
35199
35200 int vlen_enc = vector_length_encoding(this);
35201 ___masm. vpaddb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vlen_enc);
35202
35203#line 35203 "ad_x86.cpp"
35204 }
35205}
35206
35207void vaddSNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35208 cbuf.set_insts_mark();
35209 // Start at oper_input_base() and count operands
35210 unsigned idx0 = 1;
35211 unsigned idx1 = 1; // dst
35212 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
35213 {
35214 C2_MacroAssembler _masm(&cbuf);
35215
35216#line 5130 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
35217
35218 ___masm. paddw(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
35219
35220#line 35220 "ad_x86.cpp"
35221 }
35222}
35223
35224void vaddS_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35225 cbuf.set_insts_mark();
35226 // Start at oper_input_base() and count operands
35227 unsigned idx0 = 1;
35228 unsigned idx1 = 1; // src1
35229 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
35230 {
35231 C2_MacroAssembler _masm(&cbuf);
35232
35233#line 5140 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
35234
35235 int vlen_enc = vector_length_encoding(this);
35236 ___masm. vpaddw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vlen_enc);
35237
35238#line 35238 "ad_x86.cpp"
35239 }
35240}
35241
35242void vaddS_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35243 cbuf.set_insts_mark();
35244 // Start at oper_input_base() and count operands
35245 unsigned idx0 = 2;
35246 unsigned idx1 = 2; // src
35247 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
35248 {
35249 C2_MacroAssembler _masm(&cbuf);
35250
35251#line 5152 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
35252
35253 int vlen_enc = vector_length_encoding(this);
35254 ___masm. vpaddw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vlen_enc);
35255
35256#line 35256 "ad_x86.cpp"
35257 }
35258}
35259
35260void vaddS_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35261 cbuf.set_insts_mark();
35262 // Start at oper_input_base() and count operands
35263 unsigned idx0 = 2;
35264 unsigned idx1 = 2; // mem
35265 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
35266 {
35267 C2_MacroAssembler _masm(&cbuf);
35268
35269#line 5152 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
35270
35271 int vlen_enc = vector_length_encoding(this);
35272 ___masm. vpaddw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vlen_enc);
35273
35274#line 35274 "ad_x86.cpp"
35275 }
35276}
35277
35278void vaddINode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35279 cbuf.set_insts_mark();
35280 // Start at oper_input_base() and count operands
35281 unsigned idx0 = 1;
35282 unsigned idx1 = 1; // dst
35283 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
35284 {
35285 C2_MacroAssembler _masm(&cbuf);
35286
35287#line 5164 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
35288
35289 ___masm. paddd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
35290
35291#line 35291 "ad_x86.cpp"
35292 }
35293}
35294
35295void vaddI_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35296 cbuf.set_insts_mark();
35297 // Start at oper_input_base() and count operands
35298 unsigned idx0 = 1;
35299 unsigned idx1 = 1; // src1
35300 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
35301 {
35302 C2_MacroAssembler _masm(&cbuf);
35303
35304#line 5174 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
35305
35306 int vlen_enc = vector_length_encoding(this);
35307 ___masm. vpaddd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vlen_enc);
35308
35309#line 35309 "ad_x86.cpp"
35310 }
35311}
35312
35313void vaddI_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35314 cbuf.set_insts_mark();
35315 // Start at oper_input_base() and count operands
35316 unsigned idx0 = 2;
35317 unsigned idx1 = 2; // src
35318 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
35319 {
35320 C2_MacroAssembler _masm(&cbuf);
35321
35322#line 5187 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
35323
35324 int vlen_enc = vector_length_encoding(this);
35325 ___masm. vpaddd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vlen_enc);
35326
35327#line 35327 "ad_x86.cpp"
35328 }
35329}
35330
35331void vaddI_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35332 cbuf.set_insts_mark();
35333 // Start at oper_input_base() and count operands
35334 unsigned idx0 = 2;
35335 unsigned idx1 = 2; // mem
35336 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
35337 {
35338 C2_MacroAssembler _masm(&cbuf);
35339
35340#line 5187 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
35341
35342 int vlen_enc = vector_length_encoding(this);
35343 ___masm. vpaddd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vlen_enc);
35344
35345#line 35345 "ad_x86.cpp"
35346 }
35347}
35348
35349void vaddLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35350 cbuf.set_insts_mark();
35351 // Start at oper_input_base() and count operands
35352 unsigned idx0 = 1;
35353 unsigned idx1 = 1; // dst
35354 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
35355 {
35356 C2_MacroAssembler _masm(&cbuf);
35357
35358#line 5199 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
35359
35360 ___masm. paddq(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
35361
35362#line 35362 "ad_x86.cpp"
35363 }
35364}
35365
35366void vaddL_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35367 cbuf.set_insts_mark();
35368 // Start at oper_input_base() and count operands
35369 unsigned idx0 = 1;
35370 unsigned idx1 = 1; // src1
35371 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
35372 {
35373 C2_MacroAssembler _masm(&cbuf);
35374
35375#line 5209 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
35376
35377 int vlen_enc = vector_length_encoding(this);
35378 ___masm. vpaddq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vlen_enc);
35379
35380#line 35380 "ad_x86.cpp"
35381 }
35382}
35383
35384void vaddL_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35385 cbuf.set_insts_mark();
35386 // Start at oper_input_base() and count operands
35387 unsigned idx0 = 2;
35388 unsigned idx1 = 2; // src
35389 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
35390 {
35391 C2_MacroAssembler _masm(&cbuf);
35392
35393#line 5221 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
35394
35395 int vlen_enc = vector_length_encoding(this);
35396 ___masm. vpaddq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vlen_enc);
35397
35398#line 35398 "ad_x86.cpp"
35399 }
35400}
35401
35402void vaddL_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35403 cbuf.set_insts_mark();
35404 // Start at oper_input_base() and count operands
35405 unsigned idx0 = 2;
35406 unsigned idx1 = 2; // mem
35407 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
35408 {
35409 C2_MacroAssembler _masm(&cbuf);
35410
35411#line 5221 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
35412
35413 int vlen_enc = vector_length_encoding(this);
35414 ___masm. vpaddq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vlen_enc);
35415
35416#line 35416 "ad_x86.cpp"
35417 }
35418}
35419
35420void vaddFNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35421 cbuf.set_insts_mark();
35422 // Start at oper_input_base() and count operands
35423 unsigned idx0 = 1;
35424 unsigned idx1 = 1; // dst
35425 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
35426 {
35427 C2_MacroAssembler _masm(&cbuf);
35428
35429#line 5233 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
35430
35431 ___masm. addps(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
35432
35433#line 35433 "ad_x86.cpp"
35434 }
35435}
35436
35437void vaddF_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35438 cbuf.set_insts_mark();
35439 // Start at oper_input_base() and count operands
35440 unsigned idx0 = 1;
35441 unsigned idx1 = 1; // src1
35442 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
35443 {
35444 C2_MacroAssembler _masm(&cbuf);
35445
35446#line 5243 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
35447
35448 int vlen_enc = vector_length_encoding(this);
35449 ___masm. vaddps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vlen_enc);
35450
35451#line 35451 "ad_x86.cpp"
35452 }
35453}
35454
35455void vaddF_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35456 cbuf.set_insts_mark();
35457 // Start at oper_input_base() and count operands
35458 unsigned idx0 = 2;
35459 unsigned idx1 = 2; // src
35460 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
35461 {
35462 C2_MacroAssembler _masm(&cbuf);
35463
35464#line 5255 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
35465
35466 int vlen_enc = vector_length_encoding(this);
35467 ___masm. vaddps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vlen_enc);
35468
35469#line 35469 "ad_x86.cpp"
35470 }
35471}
35472
35473void vaddF_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35474 cbuf.set_insts_mark();
35475 // Start at oper_input_base() and count operands
35476 unsigned idx0 = 2;
35477 unsigned idx1 = 2; // mem
35478 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
35479 {
35480 C2_MacroAssembler _masm(&cbuf);
35481
35482#line 5255 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
35483
35484 int vlen_enc = vector_length_encoding(this);
35485 ___masm. vaddps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vlen_enc);
35486
35487#line 35487 "ad_x86.cpp"
35488 }
35489}
35490
35491void vaddDNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35492 cbuf.set_insts_mark();
35493 // Start at oper_input_base() and count operands
35494 unsigned idx0 = 1;
35495 unsigned idx1 = 1; // dst
35496 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
35497 {
35498 C2_MacroAssembler _masm(&cbuf);
35499
35500#line 5267 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
35501
35502 ___masm. addpd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
35503
35504#line 35504 "ad_x86.cpp"
35505 }
35506}
35507
35508void vaddD_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35509 cbuf.set_insts_mark();
35510 // Start at oper_input_base() and count operands
35511 unsigned idx0 = 1;
35512 unsigned idx1 = 1; // src1
35513 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
35514 {
35515 C2_MacroAssembler _masm(&cbuf);
35516
35517#line 5277 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
35518
35519 int vlen_enc = vector_length_encoding(this);
35520 ___masm. vaddpd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vlen_enc);
35521
35522#line 35522 "ad_x86.cpp"
35523 }
35524}
35525
35526void vaddD_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35527 cbuf.set_insts_mark();
35528 // Start at oper_input_base() and count operands
35529 unsigned idx0 = 2;
35530 unsigned idx1 = 2; // src
35531 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
35532 {
35533 C2_MacroAssembler _masm(&cbuf);
35534
35535#line 5289 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
35536
35537 int vlen_enc = vector_length_encoding(this);
35538 ___masm. vaddpd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vlen_enc);
35539
35540#line 35540 "ad_x86.cpp"
35541 }
35542}
35543
35544void vaddD_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35545 cbuf.set_insts_mark();
35546 // Start at oper_input_base() and count operands
35547 unsigned idx0 = 2;
35548 unsigned idx1 = 2; // mem
35549 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
35550 {
35551 C2_MacroAssembler _masm(&cbuf);
35552
35553#line 5289 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
35554
35555 int vlen_enc = vector_length_encoding(this);
35556 ___masm. vaddpd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vlen_enc);
35557
35558#line 35558 "ad_x86.cpp"
35559 }
35560}
35561
35562void vsubBNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35563 cbuf.set_insts_mark();
35564 // Start at oper_input_base() and count operands
35565 unsigned idx0 = 1;
35566 unsigned idx1 = 1; // dst
35567 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
35568 {
35569 C2_MacroAssembler _masm(&cbuf);
35570
35571#line 5303 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
35572
35573 ___masm. psubb(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
35574
35575#line 35575 "ad_x86.cpp"
35576 }
35577}
35578
35579void vsubB_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35580 cbuf.set_insts_mark();
35581 // Start at oper_input_base() and count operands
35582 unsigned idx0 = 1;
35583 unsigned idx1 = 1; // src1
35584 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
35585 {
35586 C2_MacroAssembler _masm(&cbuf);
35587
35588#line 5313 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
35589
35590 int vlen_enc = vector_length_encoding(this);
35591 ___masm. vpsubb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vlen_enc);
35592
35593#line 35593 "ad_x86.cpp"
35594 }
35595}
35596
35597void vsubB_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35598 cbuf.set_insts_mark();
35599 // Start at oper_input_base() and count operands
35600 unsigned idx0 = 2;
35601 unsigned idx1 = 2; // src
35602 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
35603 {
35604 C2_MacroAssembler _masm(&cbuf);
35605
35606#line 5325 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
35607
35608 int vlen_enc = vector_length_encoding(this);
35609 ___masm. vpsubb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vlen_enc);
35610
35611#line 35611 "ad_x86.cpp"
35612 }
35613}
35614
35615void vsubSNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35616 cbuf.set_insts_mark();
35617 // Start at oper_input_base() and count operands
35618 unsigned idx0 = 1;
35619 unsigned idx1 = 1; // dst
35620 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
35621 {
35622 C2_MacroAssembler _masm(&cbuf);
35623
35624#line 5337 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
35625
35626 ___masm. psubw(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
35627
35628#line 35628 "ad_x86.cpp"
35629 }
35630}
35631
35632void vsubS_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35633 cbuf.set_insts_mark();
35634 // Start at oper_input_base() and count operands
35635 unsigned idx0 = 1;
35636 unsigned idx1 = 1; // src1
35637 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
35638 {
35639 C2_MacroAssembler _masm(&cbuf);
35640
35641#line 5348 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
35642
35643 int vlen_enc = vector_length_encoding(this);
35644 ___masm. vpsubw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vlen_enc);
35645
35646#line 35646 "ad_x86.cpp"
35647 }
35648}
35649
35650void vsubS_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35651 cbuf.set_insts_mark();
35652 // Start at oper_input_base() and count operands
35653 unsigned idx0 = 2;
35654 unsigned idx1 = 2; // src
35655 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
35656 {
35657 C2_MacroAssembler _masm(&cbuf);
35658
35659#line 5360 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
35660
35661 int vlen_enc = vector_length_encoding(this);
35662 ___masm. vpsubw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vlen_enc);
35663
35664#line 35664 "ad_x86.cpp"
35665 }
35666}
35667
35668void vsubINode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35669 cbuf.set_insts_mark();
35670 // Start at oper_input_base() and count operands
35671 unsigned idx0 = 1;
35672 unsigned idx1 = 1; // dst
35673 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
35674 {
35675 C2_MacroAssembler _masm(&cbuf);
35676
35677#line 5372 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
35678
35679 ___masm. psubd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
35680
35681#line 35681 "ad_x86.cpp"
35682 }
35683}
35684
35685void vsubI_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35686 cbuf.set_insts_mark();
35687 // Start at oper_input_base() and count operands
35688 unsigned idx0 = 1;
35689 unsigned idx1 = 1; // src1
35690 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
35691 {
35692 C2_MacroAssembler _masm(&cbuf);
35693
35694#line 5382 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
35695
35696 int vlen_enc = vector_length_encoding(this);
35697 ___masm. vpsubd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vlen_enc);
35698
35699#line 35699 "ad_x86.cpp"
35700 }
35701}
35702
35703void vsubI_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35704 cbuf.set_insts_mark();
35705 // Start at oper_input_base() and count operands
35706 unsigned idx0 = 2;
35707 unsigned idx1 = 2; // src
35708 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
35709 {
35710 C2_MacroAssembler _masm(&cbuf);
35711
35712#line 5394 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
35713
35714 int vlen_enc = vector_length_encoding(this);
35715 ___masm. vpsubd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vlen_enc);
35716
35717#line 35717 "ad_x86.cpp"
35718 }
35719}
35720
35721void vsubLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35722 cbuf.set_insts_mark();
35723 // Start at oper_input_base() and count operands
35724 unsigned idx0 = 1;
35725 unsigned idx1 = 1; // dst
35726 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
35727 {
35728 C2_MacroAssembler _masm(&cbuf);
35729
35730#line 5406 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
35731
35732 ___masm. psubq(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
35733
35734#line 35734 "ad_x86.cpp"
35735 }
35736}
35737
35738void vsubL_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35739 cbuf.set_insts_mark();
35740 // Start at oper_input_base() and count operands
35741 unsigned idx0 = 1;
35742 unsigned idx1 = 1; // src1
35743 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
35744 {
35745 C2_MacroAssembler _masm(&cbuf);
35746
35747#line 5416 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
35748
35749 int vlen_enc = vector_length_encoding(this);
35750 ___masm. vpsubq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vlen_enc);
35751
35752#line 35752 "ad_x86.cpp"
35753 }
35754}
35755
35756void vsubL_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35757 cbuf.set_insts_mark();
35758 // Start at oper_input_base() and count operands
35759 unsigned idx0 = 2;
35760 unsigned idx1 = 2; // src
35761 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
35762 {
35763 C2_MacroAssembler _masm(&cbuf);
35764
35765#line 5429 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
35766
35767 int vlen_enc = vector_length_encoding(this);
35768 ___masm. vpsubq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vlen_enc);
35769
35770#line 35770 "ad_x86.cpp"
35771 }
35772}
35773
35774void vsubFNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35775 cbuf.set_insts_mark();
35776 // Start at oper_input_base() and count operands
35777 unsigned idx0 = 1;
35778 unsigned idx1 = 1; // dst
35779 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
35780 {
35781 C2_MacroAssembler _masm(&cbuf);
35782
35783#line 5441 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
35784
35785 ___masm. subps(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
35786
35787#line 35787 "ad_x86.cpp"
35788 }
35789}
35790
35791void vsubF_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35792 cbuf.set_insts_mark();
35793 // Start at oper_input_base() and count operands
35794 unsigned idx0 = 1;
35795 unsigned idx1 = 1; // src1
35796 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
35797 {
35798 C2_MacroAssembler _masm(&cbuf);
35799
35800#line 5451 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
35801
35802 int vlen_enc = vector_length_encoding(this);
35803 ___masm. vsubps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vlen_enc);
35804
35805#line 35805 "ad_x86.cpp"
35806 }
35807}
35808
35809void vsubF_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35810 cbuf.set_insts_mark();
35811 // Start at oper_input_base() and count operands
35812 unsigned idx0 = 2;
35813 unsigned idx1 = 2; // src
35814 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
35815 {
35816 C2_MacroAssembler _masm(&cbuf);
35817
35818#line 5463 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
35819
35820 int vlen_enc = vector_length_encoding(this);
35821 ___masm. vsubps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vlen_enc);
35822
35823#line 35823 "ad_x86.cpp"
35824 }
35825}
35826
35827void vsubDNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35828 cbuf.set_insts_mark();
35829 // Start at oper_input_base() and count operands
35830 unsigned idx0 = 1;
35831 unsigned idx1 = 1; // dst
35832 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
35833 {
35834 C2_MacroAssembler _masm(&cbuf);
35835
35836#line 5475 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
35837
35838 ___masm. subpd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
35839
35840#line 35840 "ad_x86.cpp"
35841 }
35842}
35843
35844void vsubD_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35845 cbuf.set_insts_mark();
35846 // Start at oper_input_base() and count operands
35847 unsigned idx0 = 1;
35848 unsigned idx1 = 1; // src1
35849 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
35850 {
35851 C2_MacroAssembler _masm(&cbuf);
35852
35853#line 5485 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
35854
35855 int vlen_enc = vector_length_encoding(this);
35856 ___masm. vsubpd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vlen_enc);
35857
35858#line 35858 "ad_x86.cpp"
35859 }
35860}
35861
35862void vsubD_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35863 cbuf.set_insts_mark();
35864 // Start at oper_input_base() and count operands
35865 unsigned idx0 = 2;
35866 unsigned idx1 = 2; // src
35867 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
35868 {
35869 C2_MacroAssembler _masm(&cbuf);
35870
35871#line 5497 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
35872
35873 int vlen_enc = vector_length_encoding(this);
35874 ___masm. vsubpd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vlen_enc);
35875
35876#line 35876 "ad_x86.cpp"
35877 }
35878}
35879
35880void mulB_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35881 cbuf.set_insts_mark();
35882 // Start at oper_input_base() and count operands
35883 unsigned idx0 = 1;
35884 unsigned idx1 = 1; // src1
35885 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
35886 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
35887 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
35888 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch
35889 {
35890 C2_MacroAssembler _masm(&cbuf);
35891
35892#line 5513 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
35893
35894 assert(UseSSE > 3, "required")do { if (!(UseSSE > 3)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
5514, "assert(" "UseSSE > 3" ") failed", "required"); ::breakpoint
(); } } while (0);
35895 ___masm. pmovsxbw(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */);
35896 ___masm. pmovsxbw(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
35897 ___masm. pmullw(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */);
35898 ___masm. movdqu(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, ExternalAddress(vector_short_to_byte_mask()), opnd_array(5)->as_Register(ra_,this,idx5)/* scratch */);
35899 ___masm. pand(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */);
35900 ___masm. packuswb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */);
35901
35902#line 35902 "ad_x86.cpp"
35903 }
35904}
35905
35906void mul16B_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35907 cbuf.set_insts_mark();
35908 // Start at oper_input_base() and count operands
35909 unsigned idx0 = 1;
35910 unsigned idx1 = 1; // src1
35911 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
35912 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
35913 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
35914 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
35915 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // scratch
35916 {
35917 C2_MacroAssembler _masm(&cbuf);
35918
35919#line 5530 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
35920
35921 assert(UseSSE > 3, "required")do { if (!(UseSSE > 3)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
5531, "assert(" "UseSSE > 3" ") failed", "required"); ::breakpoint
(); } } while (0);
35922 ___masm. pmovsxbw(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */);
35923 ___masm. pmovsxbw(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
35924 ___masm. pmullw(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */);
35925 ___masm. pshufd(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, 0xEE);
35926 ___masm. pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 0xEE);
35927 ___masm. pmovsxbw(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */);
35928 ___masm. pmovsxbw(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */);
35929 ___masm. pmullw(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */);
35930 ___masm. movdqu(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, ExternalAddress(vector_short_to_byte_mask()), opnd_array(6)->as_Register(ra_,this,idx6)/* scratch */);
35931 ___masm. pand(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */);
35932 ___masm. pand(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */);
35933 ___masm. packuswb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */);
35934
35935#line 35935 "ad_x86.cpp"
35936 }
35937}
35938
35939void vmul16B_reg_avxNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35940 cbuf.set_insts_mark();
35941 // Start at oper_input_base() and count operands
35942 unsigned idx0 = 1;
35943 unsigned idx1 = 1; // src1
35944 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
35945 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
35946 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
35947 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch
35948 {
35949 C2_MacroAssembler _masm(&cbuf);
35950
35951#line 5553 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
35952
35953 int vlen_enc = Assembler::AVX_256bit;
35954 ___masm. vpmovsxbw(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, vlen_enc);
35955 ___masm. vpmovsxbw(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vlen_enc);
35956 ___masm. vpmullw(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, vlen_enc);
35957 ___masm. vmovdqu(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, ExternalAddress(vector_short_to_byte_mask()), opnd_array(5)->as_Register(ra_,this,idx5)/* scratch */);
35958 ___masm. vpand(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, vlen_enc);
35959 ___masm. vextracti128_high(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */);
35960 ___masm. vpackuswb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, 0);
35961
35962#line 35962 "ad_x86.cpp"
35963 }
35964}
35965
35966void vmul32B_reg_avxNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
35967 cbuf.set_insts_mark();
35968 // Start at oper_input_base() and count operands
35969 unsigned idx0 = 1;
35970 unsigned idx1 = 1; // src1
35971 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
35972 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
35973 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
35974 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
35975 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // scratch
35976 {
35977 C2_MacroAssembler _masm(&cbuf);
35978
35979#line 5571 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
35980
35981 assert(UseAVX > 1, "required")do { if (!(UseAVX > 1)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
5572, "assert(" "UseAVX > 1" ") failed", "required"); ::breakpoint
(); } } while (0);
35982 int vlen_enc = Assembler::AVX_256bit;
35983 ___masm. vextracti128_high(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */);
35984 ___masm. vextracti128_high(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
35985 ___masm. vpmovsxbw(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, vlen_enc);
35986 ___masm. vpmovsxbw(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, vlen_enc);
35987 ___masm. vpmullw(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, vlen_enc);
35988 ___masm. vpmovsxbw(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, vlen_enc);
35989 ___masm. vpmovsxbw(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vlen_enc);
35990 ___masm. vpmullw(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, vlen_enc);
35991 ___masm. vmovdqu(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, ExternalAddress(vector_short_to_byte_mask()), opnd_array(6)->as_Register(ra_,this,idx6)/* scratch */);
35992 ___masm. vpbroadcastd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, vlen_enc);
35993 ___masm. vpand(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, vlen_enc);
35994 ___masm. vpand(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, vlen_enc);
35995 ___masm. vpackuswb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, vlen_enc);
35996 ___masm. vpermq(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, 0xD8, vlen_enc);
35997
35998#line 35998 "ad_x86.cpp"
35999 }
36000}
36001
36002void vmul64B_reg_avxNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36003 cbuf.set_insts_mark();
36004 // Start at oper_input_base() and count operands
36005 unsigned idx0 = 1;
36006 unsigned idx1 = 1; // src1
36007 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
36008 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
36009 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
36010 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
36011 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // scratch
36012 {
36013 C2_MacroAssembler _masm(&cbuf);
36014
36015#line 5597 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
36016
36017 assert(UseAVX > 2, "required")do { if (!(UseAVX > 2)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
5598, "assert(" "UseAVX > 2" ") failed", "required"); ::breakpoint
(); } } while (0);
36018 int vlen_enc = Assembler::AVX_512bit;
36019 ___masm. vextracti64x4_high(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */);
36020 ___masm. vextracti64x4_high(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
36021 ___masm. vpmovsxbw(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, vlen_enc);
36022 ___masm. vpmovsxbw(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, vlen_enc);
36023 ___masm. vpmullw(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, vlen_enc);
36024 ___masm. vpmovsxbw(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, vlen_enc);
36025 ___masm. vpmovsxbw(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vlen_enc);
36026 ___masm. vpmullw(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, vlen_enc);
36027 ___masm. vmovdqu(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, ExternalAddress(vector_short_to_byte_mask()), opnd_array(6)->as_Register(ra_,this,idx6)/* scratch */);
36028 ___masm. vpbroadcastd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, vlen_enc);
36029 ___masm. vpand(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, vlen_enc);
36030 ___masm. vpand(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, vlen_enc);
36031 ___masm. vpackuswb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, vlen_enc);
36032 ___masm. evmovdquq(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, ExternalAddress(vector_byte_perm_mask()), vlen_enc, opnd_array(6)->as_Register(ra_,this,idx6)/* scratch */);
36033 ___masm. vpermq(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, vlen_enc);
36034
36035#line 36035 "ad_x86.cpp"
36036 }
36037}
36038
36039void vmulSNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36040 cbuf.set_insts_mark();
36041 // Start at oper_input_base() and count operands
36042 unsigned idx0 = 1;
36043 unsigned idx1 = 1; // dst
36044 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
36045 {
36046 C2_MacroAssembler _masm(&cbuf);
36047
36048#line 5624 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
36049
36050 ___masm. pmullw(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
36051
36052#line 36052 "ad_x86.cpp"
36053 }
36054}
36055
36056void vmulS_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36057 cbuf.set_insts_mark();
36058 // Start at oper_input_base() and count operands
36059 unsigned idx0 = 1;
36060 unsigned idx1 = 1; // src1
36061 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
36062 {
36063 C2_MacroAssembler _masm(&cbuf);
36064
36065#line 5634 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
36066
36067 int vlen_enc = vector_length_encoding(this);
36068 ___masm. vpmullw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vlen_enc);
36069
36070#line 36070 "ad_x86.cpp"
36071 }
36072}
36073
36074void vmulS_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36075 cbuf.set_insts_mark();
36076 // Start at oper_input_base() and count operands
36077 unsigned idx0 = 2;
36078 unsigned idx1 = 2; // src
36079 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
36080 {
36081 C2_MacroAssembler _masm(&cbuf);
36082
36083#line 5646 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
36084
36085 int vlen_enc = vector_length_encoding(this);
36086 ___masm. vpmullw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vlen_enc);
36087
36088#line 36088 "ad_x86.cpp"
36089 }
36090}
36091
36092void vmulS_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36093 cbuf.set_insts_mark();
36094 // Start at oper_input_base() and count operands
36095 unsigned idx0 = 2;
36096 unsigned idx1 = 2; // mem
36097 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
36098 {
36099 C2_MacroAssembler _masm(&cbuf);
36100
36101#line 5646 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
36102
36103 int vlen_enc = vector_length_encoding(this);
36104 ___masm. vpmullw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vlen_enc);
36105
36106#line 36106 "ad_x86.cpp"
36107 }
36108}
36109
36110void vmulINode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36111 cbuf.set_insts_mark();
36112 // Start at oper_input_base() and count operands
36113 unsigned idx0 = 1;
36114 unsigned idx1 = 1; // dst
36115 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
36116 {
36117 C2_MacroAssembler _masm(&cbuf);
36118
36119#line 5658 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
36120
36121 assert(UseSSE > 3, "required")do { if (!(UseSSE > 3)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
5659, "assert(" "UseSSE > 3" ") failed", "required"); ::breakpoint
(); } } while (0);
36122 ___masm. pmulld(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
36123
36124#line 36124 "ad_x86.cpp"
36125 }
36126}
36127
36128void vmulI_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36129 cbuf.set_insts_mark();
36130 // Start at oper_input_base() and count operands
36131 unsigned idx0 = 1;
36132 unsigned idx1 = 1; // src1
36133 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
36134 {
36135 C2_MacroAssembler _masm(&cbuf);
36136
36137#line 5669 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
36138
36139 int vlen_enc = vector_length_encoding(this);
36140 ___masm. vpmulld(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vlen_enc);
36141
36142#line 36142 "ad_x86.cpp"
36143 }
36144}
36145
36146void vmulI_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36147 cbuf.set_insts_mark();
36148 // Start at oper_input_base() and count operands
36149 unsigned idx0 = 2;
36150 unsigned idx1 = 2; // src
36151 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
36152 {
36153 C2_MacroAssembler _masm(&cbuf);
36154
36155#line 5681 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
36156
36157 int vlen_enc = vector_length_encoding(this);
36158 ___masm. vpmulld(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vlen_enc);
36159
36160#line 36160 "ad_x86.cpp"
36161 }
36162}
36163
36164void vmulI_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36165 cbuf.set_insts_mark();
36166 // Start at oper_input_base() and count operands
36167 unsigned idx0 = 2;
36168 unsigned idx1 = 2; // mem
36169 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
36170 {
36171 C2_MacroAssembler _masm(&cbuf);
36172
36173#line 5681 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
36174
36175 int vlen_enc = vector_length_encoding(this);
36176 ___masm. vpmulld(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vlen_enc);
36177
36178#line 36178 "ad_x86.cpp"
36179 }
36180}
36181
36182void vmulL_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36183 cbuf.set_insts_mark();
36184 // Start at oper_input_base() and count operands
36185 unsigned idx0 = 1;
36186 unsigned idx1 = 1; // src1
36187 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
36188 {
36189 C2_MacroAssembler _masm(&cbuf);
36190
36191#line 5693 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
36192
36193 assert(UseAVX > 2, "required")do { if (!(UseAVX > 2)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
5694, "assert(" "UseAVX > 2" ") failed", "required"); ::breakpoint
(); } } while (0);
36194 int vlen_enc = vector_length_encoding(this);
36195 ___masm. vpmullq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vlen_enc);
36196
36197#line 36197 "ad_x86.cpp"
36198 }
36199}
36200
36201void vmulL_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36202 cbuf.set_insts_mark();
36203 // Start at oper_input_base() and count operands
36204 unsigned idx0 = 2;
36205 unsigned idx1 = 2; // src
36206 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
36207 {
36208 C2_MacroAssembler _masm(&cbuf);
36209
36210#line 5706 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
36211
36212 assert(UseAVX > 2, "required")do { if (!(UseAVX > 2)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
5707, "assert(" "UseAVX > 2" ") failed", "required"); ::breakpoint
(); } } while (0);
36213 int vlen_enc = vector_length_encoding(this);
36214 ___masm. vpmullq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vlen_enc);
36215
36216#line 36216 "ad_x86.cpp"
36217 }
36218}
36219
36220void vmulL_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36221 cbuf.set_insts_mark();
36222 // Start at oper_input_base() and count operands
36223 unsigned idx0 = 2;
36224 unsigned idx1 = 2; // mem
36225 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
36226 {
36227 C2_MacroAssembler _masm(&cbuf);
36228
36229#line 5706 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
36230
36231 assert(UseAVX > 2, "required")do { if (!(UseAVX > 2)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
5707, "assert(" "UseAVX > 2" ") failed", "required"); ::breakpoint
(); } } while (0);
36232 int vlen_enc = vector_length_encoding(this);
36233 ___masm. vpmullq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vlen_enc);
36234
36235#line 36235 "ad_x86.cpp"
36236 }
36237}
36238
36239void mul2L_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36240 cbuf.set_insts_mark();
36241 // Start at oper_input_base() and count operands
36242 unsigned idx0 = 1;
36243 unsigned idx1 = 1; // dst
36244 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
36245 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
36246 {
36247 C2_MacroAssembler _masm(&cbuf);
36248
36249#line 5726 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
36250
36251 assert(VM_Version::supports_sse4_1(), "required")do { if (!(VM_Version::supports_sse4_1())) { (*g_assert_poison
) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 5727, "assert(" "VM_Version::supports_sse4_1()" ") failed",
"required"); ::breakpoint(); } } while (0);
36252 int vlen_enc = Assembler::AVX_128bit;
36253 ___masm. pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 177);
36254 ___masm. pmulld(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */);
36255 ___masm. phaddd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
36256 ___masm. pmovzxdq(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
36257 ___masm. psllq(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, 32);
36258 ___masm. pmuludq(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */);
36259 ___masm. paddq(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
36260
36261#line 36261 "ad_x86.cpp"
36262 }
36263}
36264
36265void vmul4L_reg_avxNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36266 cbuf.set_insts_mark();
36267 // Start at oper_input_base() and count operands
36268 unsigned idx0 = 1;
36269 unsigned idx1 = 1; // src1
36270 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
36271 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
36272 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
36273 {
36274 C2_MacroAssembler _masm(&cbuf);
36275
36276#line 5751 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
36277
36278 int vlen_enc = Assembler::AVX_256bit;
36279 ___masm. vpshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, 177, vlen_enc);
36280 ___masm. vpmulld(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, vlen_enc);
36281 ___masm. vextracti128_high(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
36282 ___masm. vphaddd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, vlen_enc);
36283 ___masm. vpmovzxdq(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, vlen_enc);
36284 ___masm. vpsllq(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, 32, vlen_enc);
36285 ___masm. vpmuludq(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vlen_enc);
36286 ___masm. vpaddq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, vlen_enc);
36287
36288#line 36288 "ad_x86.cpp"
36289 }
36290}
36291
36292void vmulFNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36293 cbuf.set_insts_mark();
36294 // Start at oper_input_base() and count operands
36295 unsigned idx0 = 1;
36296 unsigned idx1 = 1; // dst
36297 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
36298 {
36299 C2_MacroAssembler _masm(&cbuf);
36300
36301#line 5770 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
36302
36303 ___masm. mulps(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
36304
36305#line 36305 "ad_x86.cpp"
36306 }
36307}
36308
36309void vmulF_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36310 cbuf.set_insts_mark();
36311 // Start at oper_input_base() and count operands
36312 unsigned idx0 = 1;
36313 unsigned idx1 = 1; // src1
36314 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
36315 {
36316 C2_MacroAssembler _masm(&cbuf);
36317
36318#line 5780 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
36319
36320 int vlen_enc = vector_length_encoding(this);
36321 ___masm. vmulps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vlen_enc);
36322
36323#line 36323 "ad_x86.cpp"
36324 }
36325}
36326
36327void vmulF_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36328 cbuf.set_insts_mark();
36329 // Start at oper_input_base() and count operands
36330 unsigned idx0 = 2;
36331 unsigned idx1 = 2; // src
36332 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
36333 {
36334 C2_MacroAssembler _masm(&cbuf);
36335
36336#line 5792 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
36337
36338 int vlen_enc = vector_length_encoding(this);
36339 ___masm. vmulps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vlen_enc);
36340
36341#line 36341 "ad_x86.cpp"
36342 }
36343}
36344
36345void vmulF_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36346 cbuf.set_insts_mark();
36347 // Start at oper_input_base() and count operands
36348 unsigned idx0 = 2;
36349 unsigned idx1 = 2; // mem
36350 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
36351 {
36352 C2_MacroAssembler _masm(&cbuf);
36353
36354#line 5792 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
36355
36356 int vlen_enc = vector_length_encoding(this);
36357 ___masm. vmulps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vlen_enc);
36358
36359#line 36359 "ad_x86.cpp"
36360 }
36361}
36362
36363void vmulDNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36364 cbuf.set_insts_mark();
36365 // Start at oper_input_base() and count operands
36366 unsigned idx0 = 1;
36367 unsigned idx1 = 1; // dst
36368 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
36369 {
36370 C2_MacroAssembler _masm(&cbuf);
36371
36372#line 5804 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
36373
36374 ___masm. mulpd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
36375
36376#line 36376 "ad_x86.cpp"
36377 }
36378}
36379
36380void vmulD_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36381 cbuf.set_insts_mark();
36382 // Start at oper_input_base() and count operands
36383 unsigned idx0 = 1;
36384 unsigned idx1 = 1; // src1
36385 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
36386 {
36387 C2_MacroAssembler _masm(&cbuf);
36388
36389#line 5814 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
36390
36391 int vlen_enc = vector_length_encoding(this);
36392 ___masm. vmulpd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vlen_enc);
36393
36394#line 36394 "ad_x86.cpp"
36395 }
36396}
36397
36398void vmulD_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36399 cbuf.set_insts_mark();
36400 // Start at oper_input_base() and count operands
36401 unsigned idx0 = 2;
36402 unsigned idx1 = 2; // src
36403 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
36404 {
36405 C2_MacroAssembler _masm(&cbuf);
36406
36407#line 5826 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
36408
36409 int vlen_enc = vector_length_encoding(this);
36410 ___masm. vmulpd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vlen_enc);
36411
36412#line 36412 "ad_x86.cpp"
36413 }
36414}
36415
36416void vmulD_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36417 cbuf.set_insts_mark();
36418 // Start at oper_input_base() and count operands
36419 unsigned idx0 = 2;
36420 unsigned idx1 = 2; // mem
36421 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
36422 {
36423 C2_MacroAssembler _masm(&cbuf);
36424
36425#line 5826 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
36426
36427 int vlen_enc = vector_length_encoding(this);
36428 ___masm. vmulpd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vlen_enc);
36429
36430#line 36430 "ad_x86.cpp"
36431 }
36432}
36433
36434void vcmov8F_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36435 cbuf.set_insts_mark();
36436 // Start at oper_input_base() and count operands
36437 unsigned idx0 = 1;
36438 unsigned idx1 = 1; // copnd
36439 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cop
36440 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // src1
36441 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src2
36442 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // dst
36443 {
36444 C2_MacroAssembler _masm(&cbuf);
36445
36446#line 5840 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
36447
36448 assert(UseAVX > 0, "required")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
5841, "assert(" "UseAVX > 0" ") failed", "required"); ::breakpoint
(); } } while (0);
36449
36450 int vlen_enc = Assembler::AVX_256bit;
36451 int cond = (Assembler::Condition)(opnd_array(1)->ccode());
36452 ___masm. vcmpps(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* src1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* src2 */, cond, vlen_enc);
36453 ___masm. vblendvps(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* src1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* src2 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* dst */, vlen_enc);
36454
36455#line 36455 "ad_x86.cpp"
36456 }
36457}
36458
36459void vcmov4D_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36460 cbuf.set_insts_mark();
36461 // Start at oper_input_base() and count operands
36462 unsigned idx0 = 1;
36463 unsigned idx1 = 1; // copnd
36464 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cop
36465 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // src1
36466 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // src2
36467 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // dst
36468 {
36469 C2_MacroAssembler _masm(&cbuf);
36470
36471#line 5858 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
36472
36473 assert(UseAVX > 0, "required")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
5859, "assert(" "UseAVX > 0" ") failed", "required"); ::breakpoint
(); } } while (0);
36474
36475 int vlen_enc = Assembler::AVX_256bit;
36476 int cond = (Assembler::Condition)(opnd_array(1)->ccode());
36477 ___masm. vcmppd(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* src1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* src2 */, cond, vlen_enc);
36478 ___masm. vblendvpd(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* src1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* src2 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* dst */, vlen_enc);
36479
36480#line 36480 "ad_x86.cpp"
36481 }
36482}
36483
36484void vdivFNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36485 cbuf.set_insts_mark();
36486 // Start at oper_input_base() and count operands
36487 unsigned idx0 = 1;
36488 unsigned idx1 = 1; // dst
36489 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
36490 {
36491 C2_MacroAssembler _masm(&cbuf);
36492
36493#line 5876 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
36494
36495 ___masm. divps(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
36496
36497#line 36497 "ad_x86.cpp"
36498 }
36499}
36500
36501void vdivF_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36502 cbuf.set_insts_mark();
36503 // Start at oper_input_base() and count operands
36504 unsigned idx0 = 1;
36505 unsigned idx1 = 1; // src1
36506 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
36507 {
36508 C2_MacroAssembler _masm(&cbuf);
36509
36510#line 5886 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
36511
36512 int vlen_enc = vector_length_encoding(this);
36513 ___masm. vdivps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vlen_enc);
36514
36515#line 36515 "ad_x86.cpp"
36516 }
36517}
36518
36519void vdivF_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36520 cbuf.set_insts_mark();
36521 // Start at oper_input_base() and count operands
36522 unsigned idx0 = 2;
36523 unsigned idx1 = 2; // src
36524 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
36525 {
36526 C2_MacroAssembler _masm(&cbuf);
36527
36528#line 5898 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
36529
36530 int vlen_enc = vector_length_encoding(this);
36531 ___masm. vdivps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vlen_enc);
36532
36533#line 36533 "ad_x86.cpp"
36534 }
36535}
36536
36537void vdivDNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36538 cbuf.set_insts_mark();
36539 // Start at oper_input_base() and count operands
36540 unsigned idx0 = 1;
36541 unsigned idx1 = 1; // dst
36542 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
36543 {
36544 C2_MacroAssembler _masm(&cbuf);
36545
36546#line 5910 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
36547
36548 ___masm. divpd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
36549
36550#line 36550 "ad_x86.cpp"
36551 }
36552}
36553
36554void vdivD_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36555 cbuf.set_insts_mark();
36556 // Start at oper_input_base() and count operands
36557 unsigned idx0 = 1;
36558 unsigned idx1 = 1; // src1
36559 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
36560 {
36561 C2_MacroAssembler _masm(&cbuf);
36562
36563#line 5920 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
36564
36565 int vlen_enc = vector_length_encoding(this);
36566 ___masm. vdivpd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vlen_enc);
36567
36568#line 36568 "ad_x86.cpp"
36569 }
36570}
36571
36572void vdivD_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36573 cbuf.set_insts_mark();
36574 // Start at oper_input_base() and count operands
36575 unsigned idx0 = 2;
36576 unsigned idx1 = 2; // src
36577 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
36578 {
36579 C2_MacroAssembler _masm(&cbuf);
36580
36581#line 5932 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
36582
36583 int vlen_enc = vector_length_encoding(this);
36584 ___masm. vdivpd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vlen_enc);
36585
36586#line 36586 "ad_x86.cpp"
36587 }
36588}
36589
36590void minmax_reg_sseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36591 cbuf.set_insts_mark();
36592 // Start at oper_input_base() and count operands
36593 unsigned idx0 = 1;
36594 unsigned idx1 = 1; // dst
36595 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
36596 {
36597 C2_MacroAssembler _masm(&cbuf);
36598
36599#line 5948 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
36600
36601 assert(UseSSE >= 4, "required")do { if (!(UseSSE >= 4)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
5949, "assert(" "UseSSE >= 4" ") failed", "required"); ::
breakpoint(); } } while (0);
36602
36603 int opcode = this->ideal_Opcode();
36604 BasicType elem_bt = Matcher::vector_element_basic_type(this);
36605 ___masm. pminmax(opcode, elem_bt, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
36606
36607#line 36607 "ad_x86.cpp"
36608 }
36609}
36610
36611void minmax_reg_sse_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36612 cbuf.set_insts_mark();
36613 // Start at oper_input_base() and count operands
36614 unsigned idx0 = 1;
36615 unsigned idx1 = 1; // dst
36616 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
36617 {
36618 C2_MacroAssembler _masm(&cbuf);
36619
36620#line 5948 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
36621
36622 assert(UseSSE >= 4, "required")do { if (!(UseSSE >= 4)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
5949, "assert(" "UseSSE >= 4" ") failed", "required"); ::
breakpoint(); } } while (0);
36623
36624 int opcode = this->ideal_Opcode();
36625 BasicType elem_bt = Matcher::vector_element_basic_type(this);
36626 ___masm. pminmax(opcode, elem_bt, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
36627
36628#line 36628 "ad_x86.cpp"
36629 }
36630}
36631
36632void vminmax_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36633 cbuf.set_insts_mark();
36634 // Start at oper_input_base() and count operands
36635 unsigned idx0 = 1;
36636 unsigned idx1 = 1; // src1
36637 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
36638 {
36639 C2_MacroAssembler _masm(&cbuf);
36640
36641#line 5964 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
36642
36643 int opcode = this->ideal_Opcode();
36644 int vlen_enc = vector_length_encoding(this);
36645 BasicType elem_bt = Matcher::vector_element_basic_type(this);
36646
36647 ___masm. vpminmax(opcode, elem_bt, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vlen_enc);
36648
36649#line 36649 "ad_x86.cpp"
36650 }
36651}
36652
36653void vminmax_reg_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36654 cbuf.set_insts_mark();
36655 // Start at oper_input_base() and count operands
36656 unsigned idx0 = 1;
36657 unsigned idx1 = 1; // src1
36658 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
36659 {
36660 C2_MacroAssembler _masm(&cbuf);
36661
36662#line 5964 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
36663
36664 int opcode = this->ideal_Opcode();
36665 int vlen_enc = vector_length_encoding(this);
36666 BasicType elem_bt = Matcher::vector_element_basic_type(this);
36667
36668 ___masm. vpminmax(opcode, elem_bt, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vlen_enc);
36669
36670#line 36670 "ad_x86.cpp"
36671 }
36672}
36673
36674void minmaxL_reg_sseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36675 cbuf.set_insts_mark();
36676 // Start at oper_input_base() and count operands
36677 unsigned idx0 = 1;
36678 unsigned idx1 = 1; // dst
36679 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
36680 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
36681 {
36682 C2_MacroAssembler _masm(&cbuf);
36683
36684#line 5982 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
36685
36686 assert(UseSSE >= 4, "required")do { if (!(UseSSE >= 4)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
5983, "assert(" "UseSSE >= 4" ") failed", "required"); ::
breakpoint(); } } while (0);
36687
36688 int opcode = this->ideal_Opcode();
36689 BasicType elem_bt = Matcher::vector_element_basic_type(this);
36690 assert(elem_bt == T_LONG, "sanity")do { if (!(elem_bt == T_LONG)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
5987, "assert(" "elem_bt == T_LONG" ") failed", "sanity"); ::
breakpoint(); } } while (0);
36691
36692 ___masm. pminmax(opcode, elem_bt, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
36693
36694#line 36694 "ad_x86.cpp"
36695 }
36696}
36697
36698void minmaxL_reg_sse_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36699 cbuf.set_insts_mark();
36700 // Start at oper_input_base() and count operands
36701 unsigned idx0 = 1;
36702 unsigned idx1 = 1; // src
36703 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
36704 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
36705 {
36706 C2_MacroAssembler _masm(&cbuf);
36707
36708#line 5982 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
36709
36710 assert(UseSSE >= 4, "required")do { if (!(UseSSE >= 4)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
5983, "assert(" "UseSSE >= 4" ") failed", "required"); ::
breakpoint(); } } while (0);
36711
36712 int opcode = this->ideal_Opcode();
36713 BasicType elem_bt = Matcher::vector_element_basic_type(this);
36714 assert(elem_bt == T_LONG, "sanity")do { if (!(elem_bt == T_LONG)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
5987, "assert(" "elem_bt == T_LONG" ") failed", "sanity"); ::
breakpoint(); } } while (0);
36715
36716 ___masm. pminmax(opcode, elem_bt, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */);
36717
36718#line 36718 "ad_x86.cpp"
36719 }
36720}
36721
36722void vminmaxL_reg_avxNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36723 cbuf.set_insts_mark();
36724 // Start at oper_input_base() and count operands
36725 unsigned idx0 = 1;
36726 unsigned idx1 = 1; // src1
36727 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
36728 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
36729 {
36730 C2_MacroAssembler _masm(&cbuf);
36731
36732#line 6001 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
36733
36734 int vlen_enc = vector_length_encoding(this);
36735 int opcode = this->ideal_Opcode();
36736 BasicType elem_bt = Matcher::vector_element_basic_type(this);
36737 assert(elem_bt == T_LONG, "sanity")do { if (!(elem_bt == T_LONG)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6005, "assert(" "elem_bt == T_LONG" ") failed", "sanity"); ::
breakpoint(); } } while (0);
36738
36739 ___masm. vpminmax(opcode, elem_bt, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vlen_enc);
36740
36741#line 36741 "ad_x86.cpp"
36742 }
36743}
36744
36745void vminmaxL_reg_avx_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36746 cbuf.set_insts_mark();
36747 // Start at oper_input_base() and count operands
36748 unsigned idx0 = 1;
36749 unsigned idx1 = 1; // src1
36750 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
36751 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
36752 {
36753 C2_MacroAssembler _masm(&cbuf);
36754
36755#line 6001 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
36756
36757 int vlen_enc = vector_length_encoding(this);
36758 int opcode = this->ideal_Opcode();
36759 BasicType elem_bt = Matcher::vector_element_basic_type(this);
36760 assert(elem_bt == T_LONG, "sanity")do { if (!(elem_bt == T_LONG)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6005, "assert(" "elem_bt == T_LONG" ") failed", "sanity"); ::
breakpoint(); } } while (0);
36761
36762 ___masm. vpminmax(opcode, elem_bt, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vlen_enc);
36763
36764#line 36764 "ad_x86.cpp"
36765 }
36766}
36767
36768void vminmaxL_reg_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36769 cbuf.set_insts_mark();
36770 // Start at oper_input_base() and count operands
36771 unsigned idx0 = 1;
36772 unsigned idx1 = 1; // src1
36773 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
36774 {
36775 C2_MacroAssembler _masm(&cbuf);
36776
36777#line 6018 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
36778
36779 assert(UseAVX > 2, "required")do { if (!(UseAVX > 2)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6019, "assert(" "UseAVX > 2" ") failed", "required"); ::breakpoint
(); } } while (0);
36780
36781 int vlen_enc = vector_length_encoding(this);
36782 int opcode = this->ideal_Opcode();
36783 BasicType elem_bt = Matcher::vector_element_basic_type(this);
36784 assert(elem_bt == T_LONG, "sanity")do { if (!(elem_bt == T_LONG)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6024, "assert(" "elem_bt == T_LONG" ") failed", "sanity"); ::
breakpoint(); } } while (0);
36785
36786 ___masm. vpminmax(opcode, elem_bt, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vlen_enc);
36787
36788#line 36788 "ad_x86.cpp"
36789 }
36790}
36791
36792void vminmaxL_reg_evex_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36793 cbuf.set_insts_mark();
36794 // Start at oper_input_base() and count operands
36795 unsigned idx0 = 1;
36796 unsigned idx1 = 1; // src1
36797 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
36798 {
36799 C2_MacroAssembler _masm(&cbuf);
36800
36801#line 6018 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
36802
36803 assert(UseAVX > 2, "required")do { if (!(UseAVX > 2)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6019, "assert(" "UseAVX > 2" ") failed", "required"); ::breakpoint
(); } } while (0);
36804
36805 int vlen_enc = vector_length_encoding(this);
36806 int opcode = this->ideal_Opcode();
36807 BasicType elem_bt = Matcher::vector_element_basic_type(this);
36808 assert(elem_bt == T_LONG, "sanity")do { if (!(elem_bt == T_LONG)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6024, "assert(" "elem_bt == T_LONG" ") failed", "sanity"); ::
breakpoint(); } } while (0);
36809
36810 ___masm. vpminmax(opcode, elem_bt, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vlen_enc);
36811
36812#line 36812 "ad_x86.cpp"
36813 }
36814}
36815
36816void minmaxFP_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36817 cbuf.set_insts_mark();
36818 // Start at oper_input_base() and count operands
36819 unsigned idx0 = 1;
36820 unsigned idx1 = 1; // a
36821 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // b
36822 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
36823 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // atmp
36824 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // btmp
36825 {
36826 C2_MacroAssembler _masm(&cbuf);
36827
36828#line 6040 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
36829
36830 assert(UseAVX > 0, "required")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6041, "assert(" "UseAVX > 0" ") failed", "required"); ::breakpoint
(); } } while (0);
36831
36832 int opcode = this->ideal_Opcode();
36833 int vlen_enc = vector_length_encoding(this);
36834 BasicType elem_bt = Matcher::vector_element_basic_type(this);
36835
36836 ___masm. vminmax_fp(opcode, elem_bt,
36837 opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* a */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* b */,
36838 opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* atmp */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* btmp */, vlen_enc);
36839
36840#line 36840 "ad_x86.cpp"
36841 }
36842}
36843
36844void minmaxFP_reg_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36845 cbuf.set_insts_mark();
36846 // Start at oper_input_base() and count operands
36847 unsigned idx0 = 1;
36848 unsigned idx1 = 1; // a
36849 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // b
36850 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
36851 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // atmp
36852 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // btmp
36853 {
36854 C2_MacroAssembler _masm(&cbuf);
36855
36856#line 6040 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
36857
36858 assert(UseAVX > 0, "required")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6041, "assert(" "UseAVX > 0" ") failed", "required"); ::breakpoint
(); } } while (0);
36859
36860 int opcode = this->ideal_Opcode();
36861 int vlen_enc = vector_length_encoding(this);
36862 BasicType elem_bt = Matcher::vector_element_basic_type(this);
36863
36864 ___masm. vminmax_fp(opcode, elem_bt,
36865 opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* a */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* b */,
36866 opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* atmp */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* btmp */, vlen_enc);
36867
36868#line 36868 "ad_x86.cpp"
36869 }
36870}
36871
36872void evminmaxFP_reg_eavxNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36873 cbuf.set_insts_mark();
36874 // Start at oper_input_base() and count operands
36875 unsigned idx0 = 1;
36876 unsigned idx1 = 1; // a
36877 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // b
36878 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
36879 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // atmp
36880 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // btmp
36881 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // ktmp
36882 {
36883 C2_MacroAssembler _masm(&cbuf);
36884
36885#line 6061 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
36886
36887 assert(UseAVX > 2, "required")do { if (!(UseAVX > 2)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6062, "assert(" "UseAVX > 2" ") failed", "required"); ::breakpoint
(); } } while (0);
36888
36889 int opcode = this->ideal_Opcode();
36890 int vlen_enc = vector_length_encoding(this);
36891 BasicType elem_bt = Matcher::vector_element_basic_type(this);
36892
36893 ___masm. evminmax_fp(opcode, elem_bt,
36894 opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* a */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* b */,
36895 opnd_array(6)->as_KRegister(ra_,this,idx6)/* ktmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* atmp */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* btmp */, vlen_enc);
36896
36897#line 36897 "ad_x86.cpp"
36898 }
36899}
36900
36901void evminmaxFP_reg_eavx_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36902 cbuf.set_insts_mark();
36903 // Start at oper_input_base() and count operands
36904 unsigned idx0 = 1;
36905 unsigned idx1 = 1; // a
36906 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // b
36907 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
36908 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // atmp
36909 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // btmp
36910 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // ktmp
36911 {
36912 C2_MacroAssembler _masm(&cbuf);
36913
36914#line 6061 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
36915
36916 assert(UseAVX > 2, "required")do { if (!(UseAVX > 2)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6062, "assert(" "UseAVX > 2" ") failed", "required"); ::breakpoint
(); } } while (0);
36917
36918 int opcode = this->ideal_Opcode();
36919 int vlen_enc = vector_length_encoding(this);
36920 BasicType elem_bt = Matcher::vector_element_basic_type(this);
36921
36922 ___masm. evminmax_fp(opcode, elem_bt,
36923 opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* a */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* b */,
36924 opnd_array(6)->as_KRegister(ra_,this,idx6)/* ktmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* atmp */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* btmp */, vlen_enc);
36925
36926#line 36926 "ad_x86.cpp"
36927 }
36928}
36929
36930void signumF_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36931 cbuf.set_insts_mark();
36932 // Start at oper_input_base() and count operands
36933 unsigned idx0 = 1;
36934 unsigned idx1 = 1; // dst
36935 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
36936 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // one
36937 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // scratch
36938 {
36939 C2_MacroAssembler _masm(&cbuf);
36940
36941#line 6081 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
36942
36943 int opcode = this->ideal_Opcode();
36944 ___masm. signum_fp(opcode, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* zero */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* one */, opnd_array(4)->as_Register(ra_,this,idx4)/* scratch */);
36945
36946#line 36946 "ad_x86.cpp"
36947 }
36948}
36949
36950void signumD_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36951 cbuf.set_insts_mark();
36952 // Start at oper_input_base() and count operands
36953 unsigned idx0 = 1;
36954 unsigned idx1 = 1; // dst
36955 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // zero
36956 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // one
36957 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // scratch
36958 {
36959 C2_MacroAssembler _masm(&cbuf);
36960
36961#line 6092 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
36962
36963 int opcode = this->ideal_Opcode();
36964 ___masm. signum_fp(opcode, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* zero */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* one */, opnd_array(4)->as_Register(ra_,this,idx4)/* scratch */);
36965
36966#line 36966 "ad_x86.cpp"
36967 }
36968}
36969
36970void copySignF_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36971 cbuf.set_insts_mark();
36972 // Start at oper_input_base() and count operands
36973 unsigned idx0 = 1;
36974 unsigned idx1 = 1; // dst
36975 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
36976 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp1
36977 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp2
36978 {
36979 C2_MacroAssembler _masm(&cbuf);
36980
36981#line 6124 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
36982
36983 ___masm. movl(opnd_array(4)->as_Register(ra_,this,idx4)/* tmp2 */, 0x7FFFFFFF);
36984 ___masm. movdl(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp1 */, opnd_array(4)->as_Register(ra_,this,idx4)/* tmp2 */);
36985 ___masm. vpternlogd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, 0xE4, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* tmp1 */, Assembler::AVX_128bit);
36986
36987#line 36987 "ad_x86.cpp"
36988 }
36989}
36990
36991void copySignD_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
36992 cbuf.set_insts_mark();
36993 // Start at oper_input_base() and count operands
36994 unsigned idx0 = 1;
36995 unsigned idx1 = 1; // dst
36996 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
36997 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // zero
36998 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
36999 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
37000 {
37001 C2_MacroAssembler _masm(&cbuf);
37002
37003#line 6137 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
37004
37005 ___masm. mov64(opnd_array(5)->as_Register(ra_,this,idx5)/* tmp2 */, 0x7FFFFFFFFFFFFFFF);
37006 ___masm. movq(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(5)->as_Register(ra_,this,idx5)/* tmp2 */);
37007 ___masm. vpternlogq(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, 0xE4, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, Assembler::AVX_128bit);
37008
37009#line 37009 "ad_x86.cpp"
37010 }
37011}
37012
37013void vsqrtF_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
37014 cbuf.set_insts_mark();
37015 // Start at oper_input_base() and count operands
37016 unsigned idx0 = 1;
37017 unsigned idx1 = 1; // src
37018 {
37019 C2_MacroAssembler _masm(&cbuf);
37020
37021#line 6152 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
37022
37023 assert(UseAVX > 0, "required")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6153, "assert(" "UseAVX > 0" ") failed", "required"); ::breakpoint
(); } } while (0);
37024 int vlen_enc = vector_length_encoding(this);
37025 ___masm. vsqrtps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vlen_enc);
37026
37027#line 37027 "ad_x86.cpp"
37028 }
37029}
37030
37031void vsqrtF_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
37032 cbuf.set_insts_mark();
37033 // Start at oper_input_base() and count operands
37034 unsigned idx0 = 2;
37035 unsigned idx1 = 2; // mem
37036 {
37037 C2_MacroAssembler _masm(&cbuf);
37038
37039#line 6165 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
37040
37041 assert(UseAVX > 0, "required")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6166, "assert(" "UseAVX > 0" ") failed", "required"); ::breakpoint
(); } } while (0);
37042 int vlen_enc = vector_length_encoding(this);
37043 ___masm. vsqrtps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vlen_enc);
37044
37045#line 37045 "ad_x86.cpp"
37046 }
37047}
37048
37049void vsqrtD_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
37050 cbuf.set_insts_mark();
37051 // Start at oper_input_base() and count operands
37052 unsigned idx0 = 1;
37053 unsigned idx1 = 1; // src
37054 {
37055 C2_MacroAssembler _masm(&cbuf);
37056
37057#line 6178 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
37058
37059 assert(UseAVX > 0, "required")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6179, "assert(" "UseAVX > 0" ") failed", "required"); ::breakpoint
(); } } while (0);
37060 int vlen_enc = vector_length_encoding(this);
37061 ___masm. vsqrtpd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vlen_enc);
37062
37063#line 37063 "ad_x86.cpp"
37064 }
37065}
37066
37067void vsqrtD_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
37068 cbuf.set_insts_mark();
37069 // Start at oper_input_base() and count operands
37070 unsigned idx0 = 2;
37071 unsigned idx1 = 2; // mem
37072 {
37073 C2_MacroAssembler _masm(&cbuf);
37074
37075#line 6191 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
37076
37077 assert(UseAVX > 0, "required")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6192, "assert(" "UseAVX > 0" ") failed", "required"); ::breakpoint
(); } } while (0);
37078 int vlen_enc = vector_length_encoding(this);
37079 ___masm. vsqrtpd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vlen_enc);
37080
37081#line 37081 "ad_x86.cpp"
37082 }
37083}
37084
37085void vshiftcntNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
37086 cbuf.set_insts_mark();
37087 // Start at oper_input_base() and count operands
37088 unsigned idx0 = 1;
37089 unsigned idx1 = 1; // cnt
37090 {
37091 C2_MacroAssembler _masm(&cbuf);
37092
37093#line 6207 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
37094
37095 ___masm. movdl(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* cnt */);
37096
37097#line 37097 "ad_x86.cpp"
37098 }
37099}
37100
37101void vshiftcnt_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
37102 cbuf.set_insts_mark();
37103 // Start at oper_input_base() and count operands
37104 unsigned idx0 = 1;
37105 unsigned idx1 = 1; // cnt
37106 {
37107 C2_MacroAssembler _masm(&cbuf);
37108
37109#line 6207 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
37110
37111 ___masm. movdl(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* cnt */);
37112
37113#line 37113 "ad_x86.cpp"
37114 }
37115}
37116
37117void vshiftBNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
37118 cbuf.set_insts_mark();
37119 // Start at oper_input_base() and count operands
37120 unsigned idx0 = 1;
37121 unsigned idx1 = 1; // src
37122 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
37123 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
37124 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
37125 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch
37126 {
37127 C2_MacroAssembler _masm(&cbuf);
37128
37129#line 6221 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
37130
37131 assert(UseSSE > 3, "required")do { if (!(UseSSE > 3)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6222, "assert(" "UseSSE > 3" ") failed", "required"); ::breakpoint
(); } } while (0);
37132 int opcode = this->ideal_Opcode();
37133 bool sign = (opcode != Op_URShiftVB);
37134 ___masm. vextendbw(sign, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
37135 ___masm. vshiftw(opcode, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
37136 ___masm. movdqu(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, ExternalAddress(vector_short_to_byte_mask()), opnd_array(5)->as_Register(ra_,this,idx5)/* scratch */);
37137 ___masm. pand(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */);
37138 ___masm. packuswb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */);
37139
37140#line 37140 "ad_x86.cpp"
37141 }
37142}
37143
37144void vshiftB_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
37145 cbuf.set_insts_mark();
37146 // Start at oper_input_base() and count operands
37147 unsigned idx0 = 1;
37148 unsigned idx1 = 1; // src
37149 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
37150 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
37151 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
37152 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch
37153 {
37154 C2_MacroAssembler _masm(&cbuf);
37155
37156#line 6221 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
37157
37158 assert(UseSSE > 3, "required")do { if (!(UseSSE > 3)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6222, "assert(" "UseSSE > 3" ") failed", "required"); ::breakpoint
(); } } while (0);
37159 int opcode = this->ideal_Opcode();
37160 bool sign = (opcode != Op_URShiftVB);
37161 ___masm. vextendbw(sign, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
37162 ___masm. vshiftw(opcode, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
37163 ___masm. movdqu(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, ExternalAddress(vector_short_to_byte_mask()), opnd_array(5)->as_Register(ra_,this,idx5)/* scratch */);
37164 ___masm. pand(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */);
37165 ___masm. packuswb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */);
37166
37167#line 37167 "ad_x86.cpp"
37168 }
37169}
37170
37171void vshiftB_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
37172 cbuf.set_insts_mark();
37173 // Start at oper_input_base() and count operands
37174 unsigned idx0 = 1;
37175 unsigned idx1 = 1; // src
37176 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
37177 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
37178 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
37179 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch
37180 {
37181 C2_MacroAssembler _masm(&cbuf);
37182
37183#line 6221 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
37184
37185 assert(UseSSE > 3, "required")do { if (!(UseSSE > 3)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6222, "assert(" "UseSSE > 3" ") failed", "required"); ::breakpoint
(); } } while (0);
37186 int opcode = this->ideal_Opcode();
37187 bool sign = (opcode != Op_URShiftVB);
37188 ___masm. vextendbw(sign, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
37189 ___masm. vshiftw(opcode, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
37190 ___masm. movdqu(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, ExternalAddress(vector_short_to_byte_mask()), opnd_array(5)->as_Register(ra_,this,idx5)/* scratch */);
37191 ___masm. pand(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */);
37192 ___masm. packuswb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */);
37193
37194#line 37194 "ad_x86.cpp"
37195 }
37196}
37197
37198void vshift16BNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
37199 cbuf.set_insts_mark();
37200 // Start at oper_input_base() and count operands
37201 unsigned idx0 = 1;
37202 unsigned idx1 = 1; // src
37203 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
37204 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
37205 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
37206 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
37207 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // scratch
37208 {
37209 C2_MacroAssembler _masm(&cbuf);
37210
37211#line 6242 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
37212
37213 assert(UseSSE > 3, "required")do { if (!(UseSSE > 3)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6243, "assert(" "UseSSE > 3" ") failed", "required"); ::breakpoint
(); } } while (0);
37214 int opcode = this->ideal_Opcode();
37215 bool sign = (opcode != Op_URShiftVB);
37216 ___masm. vextendbw(sign, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
37217 ___masm. vshiftw(opcode, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
37218 ___masm. pshufd(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, 0xE);
37219 ___masm. vextendbw(sign, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */);
37220 ___masm. vshiftw(opcode, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
37221 ___masm. movdqu(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, ExternalAddress(vector_short_to_byte_mask()), opnd_array(6)->as_Register(ra_,this,idx6)/* scratch */);
37222 ___masm. pand(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */);
37223 ___masm. pand(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */);
37224 ___masm. packuswb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */);
37225
37226#line 37226 "ad_x86.cpp"
37227 }
37228}
37229
37230void vshift16B_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
37231 cbuf.set_insts_mark();
37232 // Start at oper_input_base() and count operands
37233 unsigned idx0 = 1;
37234 unsigned idx1 = 1; // src
37235 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
37236 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
37237 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
37238 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
37239 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // scratch
37240 {
37241 C2_MacroAssembler _masm(&cbuf);
37242
37243#line 6242 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
37244
37245 assert(UseSSE > 3, "required")do { if (!(UseSSE > 3)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6243, "assert(" "UseSSE > 3" ") failed", "required"); ::breakpoint
(); } } while (0);
37246 int opcode = this->ideal_Opcode();
37247 bool sign = (opcode != Op_URShiftVB);
37248 ___masm. vextendbw(sign, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
37249 ___masm. vshiftw(opcode, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
37250 ___masm. pshufd(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, 0xE);
37251 ___masm. vextendbw(sign, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */);
37252 ___masm. vshiftw(opcode, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
37253 ___masm. movdqu(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, ExternalAddress(vector_short_to_byte_mask()), opnd_array(6)->as_Register(ra_,this,idx6)/* scratch */);
37254 ___masm. pand(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */);
37255 ___masm. pand(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */);
37256 ___masm. packuswb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */);
37257
37258#line 37258 "ad_x86.cpp"
37259 }
37260}
37261
37262void vshift16B_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
37263 cbuf.set_insts_mark();
37264 // Start at oper_input_base() and count operands
37265 unsigned idx0 = 1;
37266 unsigned idx1 = 1; // src
37267 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
37268 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
37269 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
37270 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
37271 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // scratch
37272 {
37273 C2_MacroAssembler _masm(&cbuf);
37274
37275#line 6242 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
37276
37277 assert(UseSSE > 3, "required")do { if (!(UseSSE > 3)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6243, "assert(" "UseSSE > 3" ") failed", "required"); ::breakpoint
(); } } while (0);
37278 int opcode = this->ideal_Opcode();
37279 bool sign = (opcode != Op_URShiftVB);
37280 ___masm. vextendbw(sign, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
37281 ___masm. vshiftw(opcode, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
37282 ___masm. pshufd(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, 0xE);
37283 ___masm. vextendbw(sign, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */);
37284 ___masm. vshiftw(opcode, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
37285 ___masm. movdqu(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, ExternalAddress(vector_short_to_byte_mask()), opnd_array(6)->as_Register(ra_,this,idx6)/* scratch */);
37286 ___masm. pand(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */);
37287 ___masm. pand(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */);
37288 ___masm. packuswb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */);
37289
37290#line 37290 "ad_x86.cpp"
37291 }
37292}
37293
37294void vshift16B_avxNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
37295 cbuf.set_insts_mark();
37296 // Start at oper_input_base() and count operands
37297 unsigned idx0 = 1;
37298 unsigned idx1 = 1; // src
37299 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
37300 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
37301 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
37302 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch
37303 {
37304 C2_MacroAssembler _masm(&cbuf);
37305
37306#line 6267 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
37307
37308 int opcode = this->ideal_Opcode();
37309 bool sign = (opcode != Op_URShiftVB);
37310 int vlen_enc = Assembler::AVX_256bit;
37311 ___masm. vextendbw(sign, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vlen_enc);
37312 ___masm. vshiftw(opcode, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vlen_enc);
37313 ___masm. vpand(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, ExternalAddress(vector_short_to_byte_mask()), vlen_enc, opnd_array(5)->as_Register(ra_,this,idx5)/* scratch */);
37314 ___masm. vextracti128_high(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */);
37315 ___masm. vpackuswb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, 0);
37316
37317#line 37317 "ad_x86.cpp"
37318 }
37319}
37320
37321void vshift16B_avx_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
37322 cbuf.set_insts_mark();
37323 // Start at oper_input_base() and count operands
37324 unsigned idx0 = 1;
37325 unsigned idx1 = 1; // src
37326 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
37327 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
37328 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
37329 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch
37330 {
37331 C2_MacroAssembler _masm(&cbuf);
37332
37333#line 6267 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
37334
37335 int opcode = this->ideal_Opcode();
37336 bool sign = (opcode != Op_URShiftVB);
37337 int vlen_enc = Assembler::AVX_256bit;
37338 ___masm. vextendbw(sign, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vlen_enc);
37339 ___masm. vshiftw(opcode, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vlen_enc);
37340 ___masm. vpand(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, ExternalAddress(vector_short_to_byte_mask()), vlen_enc, opnd_array(5)->as_Register(ra_,this,idx5)/* scratch */);
37341 ___masm. vextracti128_high(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */);
37342 ___masm. vpackuswb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, 0);
37343
37344#line 37344 "ad_x86.cpp"
37345 }
37346}
37347
37348void vshift16B_avx_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
37349 cbuf.set_insts_mark();
37350 // Start at oper_input_base() and count operands
37351 unsigned idx0 = 1;
37352 unsigned idx1 = 1; // src
37353 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
37354 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
37355 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
37356 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch
37357 {
37358 C2_MacroAssembler _masm(&cbuf);
37359
37360#line 6267 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
37361
37362 int opcode = this->ideal_Opcode();
37363 bool sign = (opcode != Op_URShiftVB);
37364 int vlen_enc = Assembler::AVX_256bit;
37365 ___masm. vextendbw(sign, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vlen_enc);
37366 ___masm. vshiftw(opcode, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vlen_enc);
37367 ___masm. vpand(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, ExternalAddress(vector_short_to_byte_mask()), vlen_enc, opnd_array(5)->as_Register(ra_,this,idx5)/* scratch */);
37368 ___masm. vextracti128_high(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */);
37369 ___masm. vpackuswb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, 0);
37370
37371#line 37371 "ad_x86.cpp"
37372 }
37373}
37374
37375void vshift32B_avxNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
37376 cbuf.set_insts_mark();
37377 // Start at oper_input_base() and count operands
37378 unsigned idx0 = 1;
37379 unsigned idx1 = 1; // src
37380 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
37381 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
37382 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
37383 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch
37384 {
37385 C2_MacroAssembler _masm(&cbuf);
37386
37387#line 6287 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
37388
37389 assert(UseAVX > 1, "required")do { if (!(UseAVX > 1)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6288, "assert(" "UseAVX > 1" ") failed", "required"); ::breakpoint
(); } } while (0);
37390 int opcode = this->ideal_Opcode();
37391 bool sign = (opcode != Op_URShiftVB);
37392 int vlen_enc = Assembler::AVX_256bit;
37393 ___masm. vextracti128_high(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
37394 ___masm. vextendbw(sign, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, vlen_enc);
37395 ___masm. vextendbw(sign, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vlen_enc);
37396 ___masm. vshiftw(opcode, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vlen_enc);
37397 ___masm. vshiftw(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vlen_enc);
37398 ___masm. vpand(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, ExternalAddress(vector_short_to_byte_mask()), vlen_enc, opnd_array(5)->as_Register(ra_,this,idx5)/* scratch */);
37399 ___masm. vpand(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, ExternalAddress(vector_short_to_byte_mask()), vlen_enc, opnd_array(5)->as_Register(ra_,this,idx5)/* scratch */);
37400 ___masm. vpackuswb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, vlen_enc);
37401 ___masm. vpermq(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, 0xD8, vlen_enc);
37402
37403#line 37403 "ad_x86.cpp"
37404 }
37405}
37406
37407void vshift32B_avx_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
37408 cbuf.set_insts_mark();
37409 // Start at oper_input_base() and count operands
37410 unsigned idx0 = 1;
37411 unsigned idx1 = 1; // src
37412 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
37413 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
37414 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
37415 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch
37416 {
37417 C2_MacroAssembler _masm(&cbuf);
37418
37419#line 6287 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
37420
37421 assert(UseAVX > 1, "required")do { if (!(UseAVX > 1)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6288, "assert(" "UseAVX > 1" ") failed", "required"); ::breakpoint
(); } } while (0);
37422 int opcode = this->ideal_Opcode();
37423 bool sign = (opcode != Op_URShiftVB);
37424 int vlen_enc = Assembler::AVX_256bit;
37425 ___masm. vextracti128_high(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
37426 ___masm. vextendbw(sign, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, vlen_enc);
37427 ___masm. vextendbw(sign, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vlen_enc);
37428 ___masm. vshiftw(opcode, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vlen_enc);
37429 ___masm. vshiftw(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vlen_enc);
37430 ___masm. vpand(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, ExternalAddress(vector_short_to_byte_mask()), vlen_enc, opnd_array(5)->as_Register(ra_,this,idx5)/* scratch */);
37431 ___masm. vpand(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, ExternalAddress(vector_short_to_byte_mask()), vlen_enc, opnd_array(5)->as_Register(ra_,this,idx5)/* scratch */);
37432 ___masm. vpackuswb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, vlen_enc);
37433 ___masm. vpermq(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, 0xD8, vlen_enc);
37434
37435#line 37435 "ad_x86.cpp"
37436 }
37437}
37438
37439void vshift32B_avx_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
37440 cbuf.set_insts_mark();
37441 // Start at oper_input_base() and count operands
37442 unsigned idx0 = 1;
37443 unsigned idx1 = 1; // src
37444 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
37445 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
37446 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
37447 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch
37448 {
37449 C2_MacroAssembler _masm(&cbuf);
37450
37451#line 6287 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
37452
37453 assert(UseAVX > 1, "required")do { if (!(UseAVX > 1)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6288, "assert(" "UseAVX > 1" ") failed", "required"); ::breakpoint
(); } } while (0);
37454 int opcode = this->ideal_Opcode();
37455 bool sign = (opcode != Op_URShiftVB);
37456 int vlen_enc = Assembler::AVX_256bit;
37457 ___masm. vextracti128_high(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
37458 ___masm. vextendbw(sign, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, vlen_enc);
37459 ___masm. vextendbw(sign, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vlen_enc);
37460 ___masm. vshiftw(opcode, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vlen_enc);
37461 ___masm. vshiftw(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vlen_enc);
37462 ___masm. vpand(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, ExternalAddress(vector_short_to_byte_mask()), vlen_enc, opnd_array(5)->as_Register(ra_,this,idx5)/* scratch */);
37463 ___masm. vpand(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, ExternalAddress(vector_short_to_byte_mask()), vlen_enc, opnd_array(5)->as_Register(ra_,this,idx5)/* scratch */);
37464 ___masm. vpackuswb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, vlen_enc);
37465 ___masm. vpermq(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, 0xD8, vlen_enc);
37466
37467#line 37467 "ad_x86.cpp"
37468 }
37469}
37470
37471void vshift64B_avxNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
37472 cbuf.set_insts_mark();
37473 // Start at oper_input_base() and count operands
37474 unsigned idx0 = 1;
37475 unsigned idx1 = 1; // src
37476 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
37477 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
37478 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
37479 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
37480 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // scratch
37481 {
37482 C2_MacroAssembler _masm(&cbuf);
37483
37484#line 6312 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
37485
37486 assert(UseAVX > 2, "required")do { if (!(UseAVX > 2)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6313, "assert(" "UseAVX > 2" ") failed", "required"); ::breakpoint
(); } } while (0);
37487 int opcode = this->ideal_Opcode();
37488 bool sign = (opcode != Op_URShiftVB);
37489 int vlen_enc = Assembler::AVX_512bit;
37490 ___masm. vextracti64x4(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, 1);
37491 ___masm. vextendbw(sign, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, vlen_enc);
37492 ___masm. vextendbw(sign, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vlen_enc);
37493 ___masm. vshiftw(opcode, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vlen_enc);
37494 ___masm. vshiftw(opcode, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vlen_enc);
37495 ___masm. vmovdqu(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, ExternalAddress(vector_short_to_byte_mask()), opnd_array(6)->as_Register(ra_,this,idx6)/* scratch */);
37496 ___masm. vpbroadcastd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, vlen_enc);
37497 ___masm. vpand(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, vlen_enc);
37498 ___masm. vpand(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, vlen_enc);
37499 ___masm. vpackuswb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, vlen_enc);
37500 ___masm. evmovdquq(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, ExternalAddress(vector_byte_perm_mask()), vlen_enc, opnd_array(6)->as_Register(ra_,this,idx6)/* scratch */);
37501 ___masm. vpermq(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, vlen_enc);
37502
37503#line 37503 "ad_x86.cpp"
37504 }
37505}
37506
37507void vshift64B_avx_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
37508 cbuf.set_insts_mark();
37509 // Start at oper_input_base() and count operands
37510 unsigned idx0 = 1;
37511 unsigned idx1 = 1; // src
37512 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
37513 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
37514 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
37515 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
37516 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // scratch
37517 {
37518 C2_MacroAssembler _masm(&cbuf);
37519
37520#line 6312 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
37521
37522 assert(UseAVX > 2, "required")do { if (!(UseAVX > 2)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6313, "assert(" "UseAVX > 2" ") failed", "required"); ::breakpoint
(); } } while (0);
37523 int opcode = this->ideal_Opcode();
37524 bool sign = (opcode != Op_URShiftVB);
37525 int vlen_enc = Assembler::AVX_512bit;
37526 ___masm. vextracti64x4(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, 1);
37527 ___masm. vextendbw(sign, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, vlen_enc);
37528 ___masm. vextendbw(sign, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vlen_enc);
37529 ___masm. vshiftw(opcode, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vlen_enc);
37530 ___masm. vshiftw(opcode, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vlen_enc);
37531 ___masm. vmovdqu(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, ExternalAddress(vector_short_to_byte_mask()), opnd_array(6)->as_Register(ra_,this,idx6)/* scratch */);
37532 ___masm. vpbroadcastd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, vlen_enc);
37533 ___masm. vpand(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, vlen_enc);
37534 ___masm. vpand(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, vlen_enc);
37535 ___masm. vpackuswb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, vlen_enc);
37536 ___masm. evmovdquq(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, ExternalAddress(vector_byte_perm_mask()), vlen_enc, opnd_array(6)->as_Register(ra_,this,idx6)/* scratch */);
37537 ___masm. vpermq(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, vlen_enc);
37538
37539#line 37539 "ad_x86.cpp"
37540 }
37541}
37542
37543void vshift64B_avx_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
37544 cbuf.set_insts_mark();
37545 // Start at oper_input_base() and count operands
37546 unsigned idx0 = 1;
37547 unsigned idx1 = 1; // src
37548 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
37549 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
37550 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
37551 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
37552 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // scratch
37553 {
37554 C2_MacroAssembler _masm(&cbuf);
37555
37556#line 6312 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
37557
37558 assert(UseAVX > 2, "required")do { if (!(UseAVX > 2)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6313, "assert(" "UseAVX > 2" ") failed", "required"); ::breakpoint
(); } } while (0);
37559 int opcode = this->ideal_Opcode();
37560 bool sign = (opcode != Op_URShiftVB);
37561 int vlen_enc = Assembler::AVX_512bit;
37562 ___masm. vextracti64x4(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, 1);
37563 ___masm. vextendbw(sign, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, vlen_enc);
37564 ___masm. vextendbw(sign, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vlen_enc);
37565 ___masm. vshiftw(opcode, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vlen_enc);
37566 ___masm. vshiftw(opcode, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vlen_enc);
37567 ___masm. vmovdqu(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, ExternalAddress(vector_short_to_byte_mask()), opnd_array(6)->as_Register(ra_,this,idx6)/* scratch */);
37568 ___masm. vpbroadcastd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, vlen_enc);
37569 ___masm. vpand(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, vlen_enc);
37570 ___masm. vpand(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, vlen_enc);
37571 ___masm. vpackuswb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp1 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, vlen_enc);
37572 ___masm. evmovdquq(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, ExternalAddress(vector_byte_perm_mask()), vlen_enc, opnd_array(6)->as_Register(ra_,this,idx6)/* scratch */);
37573 ___masm. vpermq(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* tmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, vlen_enc);
37574
37575#line 37575 "ad_x86.cpp"
37576 }
37577}
37578
37579void vshiftSNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
37580 cbuf.set_insts_mark();
37581 // Start at oper_input_base() and count operands
37582 unsigned idx0 = 1;
37583 unsigned idx1 = 1; // src
37584 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
37585 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
37586 {
37587 C2_MacroAssembler _masm(&cbuf);
37588
37589#line 6345 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
37590
37591 int opcode = this->ideal_Opcode();
37592 if (UseAVX > 0) {
37593 int vlen_enc = vector_length_encoding(this);
37594 ___masm. vshiftw(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vlen_enc);
37595 } else {
37596 int vlen = Matcher::vector_length(this);
37597 if (vlen == 2) {
37598 ___masm. movflt(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
37599 ___masm. vshiftw(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
37600 } else if (vlen == 4) {
37601 ___masm. movdbl(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
37602 ___masm. vshiftw(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
37603 } else {
37604 assert (vlen == 8, "sanity")do { if (!(vlen == 8)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6359, "assert(" "vlen == 8" ") failed", "sanity"); ::breakpoint
(); } } while (0);
37605 ___masm. movdqu(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
37606 ___masm. vshiftw(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
37607 }
37608 }
37609
37610#line 37610 "ad_x86.cpp"
37611 }
37612}
37613
37614void vshiftS_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
37615 cbuf.set_insts_mark();
37616 // Start at oper_input_base() and count operands
37617 unsigned idx0 = 1;
37618 unsigned idx1 = 1; // src
37619 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
37620 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
37621 {
37622 C2_MacroAssembler _masm(&cbuf);
37623
37624#line 6345 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
37625
37626 int opcode = this->ideal_Opcode();
37627 if (UseAVX > 0) {
37628 int vlen_enc = vector_length_encoding(this);
37629 ___masm. vshiftw(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vlen_enc);
37630 } else {
37631 int vlen = Matcher::vector_length(this);
37632 if (vlen == 2) {
37633 ___masm. movflt(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
37634 ___masm. vshiftw(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
37635 } else if (vlen == 4) {
37636 ___masm. movdbl(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
37637 ___masm. vshiftw(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
37638 } else {
37639 assert (vlen == 8, "sanity")do { if (!(vlen == 8)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6359, "assert(" "vlen == 8" ") failed", "sanity"); ::breakpoint
(); } } while (0);
37640 ___masm. movdqu(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
37641 ___masm. vshiftw(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
37642 }
37643 }
37644
37645#line 37645 "ad_x86.cpp"
37646 }
37647}
37648
37649void vshiftS_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
37650 cbuf.set_insts_mark();
37651 // Start at oper_input_base() and count operands
37652 unsigned idx0 = 1;
37653 unsigned idx1 = 1; // src
37654 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
37655 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
37656 {
37657 C2_MacroAssembler _masm(&cbuf);
37658
37659#line 6345 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
37660
37661 int opcode = this->ideal_Opcode();
37662 if (UseAVX > 0) {
37663 int vlen_enc = vector_length_encoding(this);
37664 ___masm. vshiftw(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vlen_enc);
37665 } else {
37666 int vlen = Matcher::vector_length(this);
37667 if (vlen == 2) {
37668 ___masm. movflt(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
37669 ___masm. vshiftw(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
37670 } else if (vlen == 4) {
37671 ___masm. movdbl(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
37672 ___masm. vshiftw(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
37673 } else {
37674 assert (vlen == 8, "sanity")do { if (!(vlen == 8)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6359, "assert(" "vlen == 8" ") failed", "sanity"); ::breakpoint
(); } } while (0);
37675 ___masm. movdqu(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
37676 ___masm. vshiftw(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
37677 }
37678 }
37679
37680#line 37680 "ad_x86.cpp"
37681 }
37682}
37683
37684void vshiftINode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
37685 cbuf.set_insts_mark();
37686 // Start at oper_input_base() and count operands
37687 unsigned idx0 = 1;
37688 unsigned idx1 = 1; // src
37689 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
37690 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
37691 {
37692 C2_MacroAssembler _masm(&cbuf);
37693
37694#line 6376 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
37695
37696 int opcode = this->ideal_Opcode();
37697 if (UseAVX > 0) {
37698 int vlen_enc = vector_length_encoding(this);
37699 ___masm. vshiftd(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vlen_enc);
37700 } else {
37701 int vlen = Matcher::vector_length(this);
37702 if (vlen == 2) {
37703 ___masm. movdbl(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
37704 ___masm. vshiftd(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
37705 } else {
37706 assert(vlen == 4, "sanity")do { if (!(vlen == 4)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6387, "assert(" "vlen == 4" ") failed", "sanity"); ::breakpoint
(); } } while (0);
37707 ___masm. movdqu(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
37708 ___masm. vshiftd(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
37709 }
37710 }
37711
37712#line 37712 "ad_x86.cpp"
37713 }
37714}
37715
37716void vshiftI_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
37717 cbuf.set_insts_mark();
37718 // Start at oper_input_base() and count operands
37719 unsigned idx0 = 1;
37720 unsigned idx1 = 1; // src
37721 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
37722 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
37723 {
37724 C2_MacroAssembler _masm(&cbuf);
37725
37726#line 6376 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
37727
37728 int opcode = this->ideal_Opcode();
37729 if (UseAVX > 0) {
37730 int vlen_enc = vector_length_encoding(this);
37731 ___masm. vshiftd(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vlen_enc);
37732 } else {
37733 int vlen = Matcher::vector_length(this);
37734 if (vlen == 2) {
37735 ___masm. movdbl(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
37736 ___masm. vshiftd(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
37737 } else {
37738 assert(vlen == 4, "sanity")do { if (!(vlen == 4)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6387, "assert(" "vlen == 4" ") failed", "sanity"); ::breakpoint
(); } } while (0);
37739 ___masm. movdqu(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
37740 ___masm. vshiftd(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
37741 }
37742 }
37743
37744#line 37744 "ad_x86.cpp"
37745 }
37746}
37747
37748void vshiftI_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
37749 cbuf.set_insts_mark();
37750 // Start at oper_input_base() and count operands
37751 unsigned idx0 = 1;
37752 unsigned idx1 = 1; // src
37753 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
37754 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
37755 {
37756 C2_MacroAssembler _masm(&cbuf);
37757
37758#line 6376 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
37759
37760 int opcode = this->ideal_Opcode();
37761 if (UseAVX > 0) {
37762 int vlen_enc = vector_length_encoding(this);
37763 ___masm. vshiftd(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vlen_enc);
37764 } else {
37765 int vlen = Matcher::vector_length(this);
37766 if (vlen == 2) {
37767 ___masm. movdbl(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
37768 ___masm. vshiftd(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
37769 } else {
37770 assert(vlen == 4, "sanity")do { if (!(vlen == 4)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6387, "assert(" "vlen == 4" ") failed", "sanity"); ::breakpoint
(); } } while (0);
37771 ___masm. movdqu(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
37772 ___masm. vshiftd(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
37773 }
37774 }
37775
37776#line 37776 "ad_x86.cpp"
37777 }
37778}
37779
37780void vshiftI_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
37781 cbuf.set_insts_mark();
37782 // Start at oper_input_base() and count operands
37783 unsigned idx0 = 1;
37784 unsigned idx1 = 1; // src
37785 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
37786 {
37787 C2_MacroAssembler _masm(&cbuf);
37788
37789#line 6402 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
37790
37791 int opcode = this->ideal_Opcode();
37792 if (UseAVX > 0) {
37793 int vector_len = vector_length_encoding(this);
37794 ___masm. vshiftd_imm(opcode, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->constant(), vector_len);
37795 } else {
37796 int vlen = Matcher::vector_length(this);
37797 if (vlen == 2) {
37798 ___masm. movdbl(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
37799 ___masm. vshiftd_imm(opcode, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->constant());
37800 } else {
37801 assert(vlen == 4, "sanity")do { if (!(vlen == 4)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6413, "assert(" "vlen == 4" ") failed", "sanity"); ::breakpoint
(); } } while (0);
37802 ___masm. movdqu(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
37803 ___masm. vshiftd_imm(opcode, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->constant());
37804 }
37805 }
37806
37807#line 37807 "ad_x86.cpp"
37808 }
37809}
37810
37811void vshiftI_imm_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
37812 cbuf.set_insts_mark();
37813 // Start at oper_input_base() and count operands
37814 unsigned idx0 = 1;
37815 unsigned idx1 = 1; // src
37816 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
37817 {
37818 C2_MacroAssembler _masm(&cbuf);
37819
37820#line 6402 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
37821
37822 int opcode = this->ideal_Opcode();
37823 if (UseAVX > 0) {
37824 int vector_len = vector_length_encoding(this);
37825 ___masm. vshiftd_imm(opcode, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->constant(), vector_len);
37826 } else {
37827 int vlen = Matcher::vector_length(this);
37828 if (vlen == 2) {
37829 ___masm. movdbl(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
37830 ___masm. vshiftd_imm(opcode, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->constant());
37831 } else {
37832 assert(vlen == 4, "sanity")do { if (!(vlen == 4)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6413, "assert(" "vlen == 4" ") failed", "sanity"); ::breakpoint
(); } } while (0);
37833 ___masm. movdqu(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
37834 ___masm. vshiftd_imm(opcode, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->constant());
37835 }
37836 }
37837
37838#line 37838 "ad_x86.cpp"
37839 }
37840}
37841
37842void vshiftI_imm_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
37843 cbuf.set_insts_mark();
37844 // Start at oper_input_base() and count operands
37845 unsigned idx0 = 1;
37846 unsigned idx1 = 1; // src
37847 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
37848 {
37849 C2_MacroAssembler _masm(&cbuf);
37850
37851#line 6402 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
37852
37853 int opcode = this->ideal_Opcode();
37854 if (UseAVX > 0) {
37855 int vector_len = vector_length_encoding(this);
37856 ___masm. vshiftd_imm(opcode, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->constant(), vector_len);
37857 } else {
37858 int vlen = Matcher::vector_length(this);
37859 if (vlen == 2) {
37860 ___masm. movdbl(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
37861 ___masm. vshiftd_imm(opcode, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->constant());
37862 } else {
37863 assert(vlen == 4, "sanity")do { if (!(vlen == 4)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6413, "assert(" "vlen == 4" ") failed", "sanity"); ::breakpoint
(); } } while (0);
37864 ___masm. movdqu(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
37865 ___masm. vshiftd_imm(opcode, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->constant());
37866 }
37867 }
37868
37869#line 37869 "ad_x86.cpp"
37870 }
37871}
37872
37873void vshiftLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
37874 cbuf.set_insts_mark();
37875 // Start at oper_input_base() and count operands
37876 unsigned idx0 = 1;
37877 unsigned idx1 = 1; // src
37878 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
37879 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
37880 {
37881 C2_MacroAssembler _masm(&cbuf);
37882
37883#line 6429 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
37884
37885 int opcode = this->ideal_Opcode();
37886 if (UseAVX > 0) {
37887 int vlen_enc = vector_length_encoding(this);
37888 ___masm. vshiftq(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vlen_enc);
37889 } else {
37890 assert(Matcher::vector_length(this) == 2, "")do { if (!(Matcher::vector_length(this) == 2)) { (*g_assert_poison
) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 6435, "assert(" "Matcher::vector_length(this) == 2" ") failed"
, ""); ::breakpoint(); } } while (0);
37891 ___masm. movdqu(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
37892 ___masm. vshiftq(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
37893 }
37894
37895#line 37895 "ad_x86.cpp"
37896 }
37897}
37898
37899void vshiftL_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
37900 cbuf.set_insts_mark();
37901 // Start at oper_input_base() and count operands
37902 unsigned idx0 = 1;
37903 unsigned idx1 = 1; // src
37904 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
37905 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
37906 {
37907 C2_MacroAssembler _masm(&cbuf);
37908
37909#line 6429 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
37910
37911 int opcode = this->ideal_Opcode();
37912 if (UseAVX > 0) {
37913 int vlen_enc = vector_length_encoding(this);
37914 ___masm. vshiftq(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vlen_enc);
37915 } else {
37916 assert(Matcher::vector_length(this) == 2, "")do { if (!(Matcher::vector_length(this) == 2)) { (*g_assert_poison
) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 6435, "assert(" "Matcher::vector_length(this) == 2" ") failed"
, ""); ::breakpoint(); } } while (0);
37917 ___masm. movdqu(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
37918 ___masm. vshiftq(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
37919 }
37920
37921#line 37921 "ad_x86.cpp"
37922 }
37923}
37924
37925void vshiftL_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
37926 cbuf.set_insts_mark();
37927 // Start at oper_input_base() and count operands
37928 unsigned idx0 = 1;
37929 unsigned idx1 = 1; // src
37930 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
37931 {
37932 C2_MacroAssembler _masm(&cbuf);
37933
37934#line 6448 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
37935
37936 int opcode = this->ideal_Opcode();
37937 if (UseAVX > 0) {
37938 int vector_len = vector_length_encoding(this);
37939 ___masm. vshiftq_imm(opcode, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->constant(), vector_len);
37940 } else {
37941 assert(Matcher::vector_length(this) == 2, "")do { if (!(Matcher::vector_length(this) == 2)) { (*g_assert_poison
) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 6454, "assert(" "Matcher::vector_length(this) == 2" ") failed"
, ""); ::breakpoint(); } } while (0);
37942 ___masm. movdqu(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
37943 ___masm. vshiftq_imm(opcode, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->constant());
37944 }
37945
37946#line 37946 "ad_x86.cpp"
37947 }
37948}
37949
37950void vshiftL_imm_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
37951 cbuf.set_insts_mark();
37952 // Start at oper_input_base() and count operands
37953 unsigned idx0 = 1;
37954 unsigned idx1 = 1; // src
37955 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
37956 {
37957 C2_MacroAssembler _masm(&cbuf);
37958
37959#line 6448 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
37960
37961 int opcode = this->ideal_Opcode();
37962 if (UseAVX > 0) {
37963 int vector_len = vector_length_encoding(this);
37964 ___masm. vshiftq_imm(opcode, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->constant(), vector_len);
37965 } else {
37966 assert(Matcher::vector_length(this) == 2, "")do { if (!(Matcher::vector_length(this) == 2)) { (*g_assert_poison
) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 6454, "assert(" "Matcher::vector_length(this) == 2" ") failed"
, ""); ::breakpoint(); } } while (0);
37967 ___masm. movdqu(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
37968 ___masm. vshiftq_imm(opcode, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->constant());
37969 }
37970
37971#line 37971 "ad_x86.cpp"
37972 }
37973}
37974
37975void vshiftL_arith_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
37976 cbuf.set_insts_mark();
37977 // Start at oper_input_base() and count operands
37978 unsigned idx0 = 1;
37979 unsigned idx1 = 1; // src
37980 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
37981 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
37982 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
37983 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch
37984 {
37985 C2_MacroAssembler _masm(&cbuf);
37986
37987#line 6469 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
37988
37989 uint vlen = Matcher::vector_length(this);
37990 if (vlen == 2) {
37991 assert(UseSSE >= 2, "required")do { if (!(UseSSE >= 2)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6472, "assert(" "UseSSE >= 2" ") failed", "required"); ::
breakpoint(); } } while (0);
37992 ___masm. movdqu(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
37993 ___masm. psrlq(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
37994 ___masm. movdqu(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, ExternalAddress(vector_long_sign_mask()), opnd_array(5)->as_Register(ra_,this,idx5)/* scratch */);
37995 ___masm. psrlq(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
37996 ___masm. pxor(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */);
37997 ___masm. psubq(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */);
37998 } else {
37999 assert(vlen == 4, "sanity")do { if (!(vlen == 4)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6480, "assert(" "vlen == 4" ") failed", "sanity"); ::breakpoint
(); } } while (0);
38000 assert(UseAVX > 1, "required")do { if (!(UseAVX > 1)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6481, "assert(" "UseAVX > 1" ") failed", "required"); ::breakpoint
(); } } while (0);
38001 int vlen_enc = Assembler::AVX_256bit;
38002 ___masm. vpsrlq(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vlen_enc);
38003 ___masm. vmovdqu(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, ExternalAddress(vector_long_sign_mask()), opnd_array(5)->as_Register(ra_,this,idx5)/* scratch */);
38004 ___masm. vpsrlq(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vlen_enc);
38005 ___masm. vpxor(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, vlen_enc);
38006 ___masm. vpsubq(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, vlen_enc);
38007 }
38008
38009#line 38009 "ad_x86.cpp"
38010 }
38011}
38012
38013void vshiftL_arith_reg_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38014 cbuf.set_insts_mark();
38015 // Start at oper_input_base() and count operands
38016 unsigned idx0 = 1;
38017 unsigned idx1 = 1; // src
38018 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
38019 {
38020 C2_MacroAssembler _masm(&cbuf);
38021
38022#line 6497 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
38023
38024 int vlen_enc = vector_length_encoding(this);
38025 ___masm. evpsraq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vlen_enc);
38026
38027#line 38027 "ad_x86.cpp"
38028 }
38029}
38030
38031void vshift8B_var_nobwNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38032 cbuf.set_insts_mark();
38033 // Start at oper_input_base() and count operands
38034 unsigned idx0 = 1;
38035 unsigned idx1 = 1; // src
38036 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
38037 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
38038 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp
38039 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch
38040 {
38041 C2_MacroAssembler _masm(&cbuf);
38042
38043#line 6515 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
38044
38045 assert(UseAVX >= 2, "required")do { if (!(UseAVX >= 2)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6516, "assert(" "UseAVX >= 2" ") failed", "required"); ::
breakpoint(); } } while (0);
38046
38047 int opcode = this->ideal_Opcode();
38048 int vlen_enc = Assembler::AVX_128bit;
38049 ___masm. varshiftbw(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vlen_enc, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp */, opnd_array(5)->as_Register(ra_,this,idx5)/* scratch */);
38050 ___masm. vpackuswb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, 0);
38051
38052#line 38052 "ad_x86.cpp"
38053 }
38054}
38055
38056void vshift8B_var_nobw_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38057 cbuf.set_insts_mark();
38058 // Start at oper_input_base() and count operands
38059 unsigned idx0 = 1;
38060 unsigned idx1 = 1; // src
38061 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
38062 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
38063 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp
38064 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch
38065 {
38066 C2_MacroAssembler _masm(&cbuf);
38067
38068#line 6515 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
38069
38070 assert(UseAVX >= 2, "required")do { if (!(UseAVX >= 2)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6516, "assert(" "UseAVX >= 2" ") failed", "required"); ::
breakpoint(); } } while (0);
38071
38072 int opcode = this->ideal_Opcode();
38073 int vlen_enc = Assembler::AVX_128bit;
38074 ___masm. varshiftbw(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vlen_enc, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp */, opnd_array(5)->as_Register(ra_,this,idx5)/* scratch */);
38075 ___masm. vpackuswb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, 0);
38076
38077#line 38077 "ad_x86.cpp"
38078 }
38079}
38080
38081void vshift8B_var_nobw_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38082 cbuf.set_insts_mark();
38083 // Start at oper_input_base() and count operands
38084 unsigned idx0 = 1;
38085 unsigned idx1 = 1; // src
38086 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
38087 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
38088 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp
38089 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch
38090 {
38091 C2_MacroAssembler _masm(&cbuf);
38092
38093#line 6515 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
38094
38095 assert(UseAVX >= 2, "required")do { if (!(UseAVX >= 2)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6516, "assert(" "UseAVX >= 2" ") failed", "required"); ::
breakpoint(); } } while (0);
38096
38097 int opcode = this->ideal_Opcode();
38098 int vlen_enc = Assembler::AVX_128bit;
38099 ___masm. varshiftbw(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vlen_enc, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp */, opnd_array(5)->as_Register(ra_,this,idx5)/* scratch */);
38100 ___masm. vpackuswb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, 0);
38101
38102#line 38102 "ad_x86.cpp"
38103 }
38104}
38105
38106void vshift16B_var_nobwNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38107 cbuf.set_insts_mark();
38108 // Start at oper_input_base() and count operands
38109 unsigned idx0 = 1;
38110 unsigned idx1 = 1; // src
38111 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
38112 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
38113 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp1
38114 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // vtmp2
38115 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // scratch
38116 {
38117 C2_MacroAssembler _masm(&cbuf);
38118
38119#line 6535 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
38120
38121 assert(UseAVX >= 2, "required")do { if (!(UseAVX >= 2)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6536, "assert(" "UseAVX >= 2" ") failed", "required"); ::
breakpoint(); } } while (0);
38122
38123 int opcode = this->ideal_Opcode();
38124 int vlen_enc = Assembler::AVX_128bit;
38125 // Shift lower half and get word result in dst
38126 ___masm. varshiftbw(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vlen_enc, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(6)->as_Register(ra_,this,idx6)/* scratch */);
38127
38128 // Shift upper half and get word result in vtmp1
38129 ___masm. vpshufd(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, 0xE, 0);
38130 ___masm. vpshufd(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, 0xE, 0);
38131 ___masm. varshiftbw(opcode, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, vlen_enc, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, opnd_array(6)->as_Register(ra_,this,idx6)/* scratch */);
38132
38133 // Merge and down convert the two word results to byte in dst
38134 ___masm. vpackuswb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, 0);
38135
38136#line 38136 "ad_x86.cpp"
38137 }
38138}
38139
38140void vshift16B_var_nobw_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38141 cbuf.set_insts_mark();
38142 // Start at oper_input_base() and count operands
38143 unsigned idx0 = 1;
38144 unsigned idx1 = 1; // src
38145 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
38146 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
38147 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp1
38148 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // vtmp2
38149 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // scratch
38150 {
38151 C2_MacroAssembler _masm(&cbuf);
38152
38153#line 6535 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
38154
38155 assert(UseAVX >= 2, "required")do { if (!(UseAVX >= 2)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6536, "assert(" "UseAVX >= 2" ") failed", "required"); ::
breakpoint(); } } while (0);
38156
38157 int opcode = this->ideal_Opcode();
38158 int vlen_enc = Assembler::AVX_128bit;
38159 // Shift lower half and get word result in dst
38160 ___masm. varshiftbw(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vlen_enc, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(6)->as_Register(ra_,this,idx6)/* scratch */);
38161
38162 // Shift upper half and get word result in vtmp1
38163 ___masm. vpshufd(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, 0xE, 0);
38164 ___masm. vpshufd(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, 0xE, 0);
38165 ___masm. varshiftbw(opcode, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, vlen_enc, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, opnd_array(6)->as_Register(ra_,this,idx6)/* scratch */);
38166
38167 // Merge and down convert the two word results to byte in dst
38168 ___masm. vpackuswb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, 0);
38169
38170#line 38170 "ad_x86.cpp"
38171 }
38172}
38173
38174void vshift16B_var_nobw_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38175 cbuf.set_insts_mark();
38176 // Start at oper_input_base() and count operands
38177 unsigned idx0 = 1;
38178 unsigned idx1 = 1; // src
38179 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
38180 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
38181 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp1
38182 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // vtmp2
38183 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // scratch
38184 {
38185 C2_MacroAssembler _masm(&cbuf);
38186
38187#line 6535 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
38188
38189 assert(UseAVX >= 2, "required")do { if (!(UseAVX >= 2)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6536, "assert(" "UseAVX >= 2" ") failed", "required"); ::
breakpoint(); } } while (0);
38190
38191 int opcode = this->ideal_Opcode();
38192 int vlen_enc = Assembler::AVX_128bit;
38193 // Shift lower half and get word result in dst
38194 ___masm. varshiftbw(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vlen_enc, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(6)->as_Register(ra_,this,idx6)/* scratch */);
38195
38196 // Shift upper half and get word result in vtmp1
38197 ___masm. vpshufd(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, 0xE, 0);
38198 ___masm. vpshufd(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, 0xE, 0);
38199 ___masm. varshiftbw(opcode, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, vlen_enc, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, opnd_array(6)->as_Register(ra_,this,idx6)/* scratch */);
38200
38201 // Merge and down convert the two word results to byte in dst
38202 ___masm. vpackuswb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, 0);
38203
38204#line 38204 "ad_x86.cpp"
38205 }
38206}
38207
38208void vshift32B_var_nobwNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38209 cbuf.set_insts_mark();
38210 // Start at oper_input_base() and count operands
38211 unsigned idx0 = 1;
38212 unsigned idx1 = 1; // src
38213 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
38214 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
38215 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp1
38216 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // vtmp2
38217 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // vtmp3
38218 unsigned idx7 = idx6 + opnd_array(6)->num_edges(); // vtmp4
38219 unsigned idx8 = idx7 + opnd_array(7)->num_edges(); // scratch
38220 {
38221 C2_MacroAssembler _masm(&cbuf);
38222
38223#line 6563 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
38224
38225 assert(UseAVX >= 2, "required")do { if (!(UseAVX >= 2)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6564, "assert(" "UseAVX >= 2" ") failed", "required"); ::
breakpoint(); } } while (0);
38226
38227 int opcode = this->ideal_Opcode();
38228 int vlen_enc = Assembler::AVX_128bit;
38229 // Process lower 128 bits and get result in dst
38230 ___masm. varshiftbw(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vlen_enc, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(8)->as_Register(ra_,this,idx8)/* scratch */);
38231 ___masm. vpshufd(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, 0xE, 0);
38232 ___masm. vpshufd(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, 0xE, 0);
38233 ___masm. varshiftbw(opcode, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, vlen_enc, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, opnd_array(8)->as_Register(ra_,this,idx8)/* scratch */);
38234 ___masm. vpackuswb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, 0);
38235
38236 // Process higher 128 bits and get result in vtmp3
38237 ___masm. vextracti128_high(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
38238 ___masm. vextracti128_high(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
38239 ___masm. varshiftbw(opcode, opnd_array(6)->as_XMMRegister(ra_,this,idx6)/* vtmp3 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, vlen_enc, opnd_array(7)->as_XMMRegister(ra_,this,idx7)/* vtmp4 */, opnd_array(8)->as_Register(ra_,this,idx8)/* scratch */);
38240 ___masm. vpshufd(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, 0xE, 0);
38241 ___masm. vpshufd(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, 0xE, 0);
38242 ___masm. varshiftbw(opcode, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, vlen_enc, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, opnd_array(8)->as_Register(ra_,this,idx8)/* scratch */);
38243 ___masm. vpackuswb(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(6)->as_XMMRegister(ra_,this,idx6)/* vtmp3 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, 0);
38244
38245 // Merge the two results in dst
38246 ___masm. vinserti128(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, 0x1);
38247
38248#line 38248 "ad_x86.cpp"
38249 }
38250}
38251
38252void vshift32B_var_nobw_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38253 cbuf.set_insts_mark();
38254 // Start at oper_input_base() and count operands
38255 unsigned idx0 = 1;
38256 unsigned idx1 = 1; // src
38257 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
38258 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
38259 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp1
38260 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // vtmp2
38261 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // vtmp3
38262 unsigned idx7 = idx6 + opnd_array(6)->num_edges(); // vtmp4
38263 unsigned idx8 = idx7 + opnd_array(7)->num_edges(); // scratch
38264 {
38265 C2_MacroAssembler _masm(&cbuf);
38266
38267#line 6563 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
38268
38269 assert(UseAVX >= 2, "required")do { if (!(UseAVX >= 2)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6564, "assert(" "UseAVX >= 2" ") failed", "required"); ::
breakpoint(); } } while (0);
38270
38271 int opcode = this->ideal_Opcode();
38272 int vlen_enc = Assembler::AVX_128bit;
38273 // Process lower 128 bits and get result in dst
38274 ___masm. varshiftbw(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vlen_enc, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(8)->as_Register(ra_,this,idx8)/* scratch */);
38275 ___masm. vpshufd(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, 0xE, 0);
38276 ___masm. vpshufd(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, 0xE, 0);
38277 ___masm. varshiftbw(opcode, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, vlen_enc, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, opnd_array(8)->as_Register(ra_,this,idx8)/* scratch */);
38278 ___masm. vpackuswb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, 0);
38279
38280 // Process higher 128 bits and get result in vtmp3
38281 ___masm. vextracti128_high(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
38282 ___masm. vextracti128_high(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
38283 ___masm. varshiftbw(opcode, opnd_array(6)->as_XMMRegister(ra_,this,idx6)/* vtmp3 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, vlen_enc, opnd_array(7)->as_XMMRegister(ra_,this,idx7)/* vtmp4 */, opnd_array(8)->as_Register(ra_,this,idx8)/* scratch */);
38284 ___masm. vpshufd(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, 0xE, 0);
38285 ___masm. vpshufd(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, 0xE, 0);
38286 ___masm. varshiftbw(opcode, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, vlen_enc, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, opnd_array(8)->as_Register(ra_,this,idx8)/* scratch */);
38287 ___masm. vpackuswb(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(6)->as_XMMRegister(ra_,this,idx6)/* vtmp3 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, 0);
38288
38289 // Merge the two results in dst
38290 ___masm. vinserti128(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, 0x1);
38291
38292#line 38292 "ad_x86.cpp"
38293 }
38294}
38295
38296void vshift32B_var_nobw_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38297 cbuf.set_insts_mark();
38298 // Start at oper_input_base() and count operands
38299 unsigned idx0 = 1;
38300 unsigned idx1 = 1; // src
38301 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
38302 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
38303 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp1
38304 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // vtmp2
38305 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // vtmp3
38306 unsigned idx7 = idx6 + opnd_array(6)->num_edges(); // vtmp4
38307 unsigned idx8 = idx7 + opnd_array(7)->num_edges(); // scratch
38308 {
38309 C2_MacroAssembler _masm(&cbuf);
38310
38311#line 6563 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
38312
38313 assert(UseAVX >= 2, "required")do { if (!(UseAVX >= 2)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6564, "assert(" "UseAVX >= 2" ") failed", "required"); ::
breakpoint(); } } while (0);
38314
38315 int opcode = this->ideal_Opcode();
38316 int vlen_enc = Assembler::AVX_128bit;
38317 // Process lower 128 bits and get result in dst
38318 ___masm. varshiftbw(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vlen_enc, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(8)->as_Register(ra_,this,idx8)/* scratch */);
38319 ___masm. vpshufd(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, 0xE, 0);
38320 ___masm. vpshufd(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, 0xE, 0);
38321 ___masm. varshiftbw(opcode, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, vlen_enc, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, opnd_array(8)->as_Register(ra_,this,idx8)/* scratch */);
38322 ___masm. vpackuswb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, 0);
38323
38324 // Process higher 128 bits and get result in vtmp3
38325 ___masm. vextracti128_high(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
38326 ___masm. vextracti128_high(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
38327 ___masm. varshiftbw(opcode, opnd_array(6)->as_XMMRegister(ra_,this,idx6)/* vtmp3 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, vlen_enc, opnd_array(7)->as_XMMRegister(ra_,this,idx7)/* vtmp4 */, opnd_array(8)->as_Register(ra_,this,idx8)/* scratch */);
38328 ___masm. vpshufd(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, 0xE, 0);
38329 ___masm. vpshufd(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, 0xE, 0);
38330 ___masm. varshiftbw(opcode, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, vlen_enc, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, opnd_array(8)->as_Register(ra_,this,idx8)/* scratch */);
38331 ___masm. vpackuswb(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(6)->as_XMMRegister(ra_,this,idx6)/* vtmp3 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, 0);
38332
38333 // Merge the two results in dst
38334 ___masm. vinserti128(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, 0x1);
38335
38336#line 38336 "ad_x86.cpp"
38337 }
38338}
38339
38340void vshiftB_var_evex_bwNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38341 cbuf.set_insts_mark();
38342 // Start at oper_input_base() and count operands
38343 unsigned idx0 = 1;
38344 unsigned idx1 = 1; // src
38345 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
38346 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
38347 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp
38348 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch
38349 {
38350 C2_MacroAssembler _masm(&cbuf);
38351
38352#line 6599 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
38353
38354 assert(UseAVX > 2, "required")do { if (!(UseAVX > 2)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6600, "assert(" "UseAVX > 2" ") failed", "required"); ::breakpoint
(); } } while (0);
38355
38356 int opcode = this->ideal_Opcode();
38357 int vlen_enc = vector_length_encoding(this);
38358 ___masm. evarshiftb(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vlen_enc, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp */, opnd_array(5)->as_Register(ra_,this,idx5)/* scratch */);
38359
38360#line 38360 "ad_x86.cpp"
38361 }
38362}
38363
38364void vshiftB_var_evex_bw_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38365 cbuf.set_insts_mark();
38366 // Start at oper_input_base() and count operands
38367 unsigned idx0 = 1;
38368 unsigned idx1 = 1; // src
38369 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
38370 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
38371 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp
38372 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch
38373 {
38374 C2_MacroAssembler _masm(&cbuf);
38375
38376#line 6599 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
38377
38378 assert(UseAVX > 2, "required")do { if (!(UseAVX > 2)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6600, "assert(" "UseAVX > 2" ") failed", "required"); ::breakpoint
(); } } while (0);
38379
38380 int opcode = this->ideal_Opcode();
38381 int vlen_enc = vector_length_encoding(this);
38382 ___masm. evarshiftb(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vlen_enc, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp */, opnd_array(5)->as_Register(ra_,this,idx5)/* scratch */);
38383
38384#line 38384 "ad_x86.cpp"
38385 }
38386}
38387
38388void vshiftB_var_evex_bw_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38389 cbuf.set_insts_mark();
38390 // Start at oper_input_base() and count operands
38391 unsigned idx0 = 1;
38392 unsigned idx1 = 1; // src
38393 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
38394 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
38395 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp
38396 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch
38397 {
38398 C2_MacroAssembler _masm(&cbuf);
38399
38400#line 6599 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
38401
38402 assert(UseAVX > 2, "required")do { if (!(UseAVX > 2)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6600, "assert(" "UseAVX > 2" ") failed", "required"); ::breakpoint
(); } } while (0);
38403
38404 int opcode = this->ideal_Opcode();
38405 int vlen_enc = vector_length_encoding(this);
38406 ___masm. evarshiftb(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vlen_enc, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp */, opnd_array(5)->as_Register(ra_,this,idx5)/* scratch */);
38407
38408#line 38408 "ad_x86.cpp"
38409 }
38410}
38411
38412void vshift64B_var_evex_bwNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38413 cbuf.set_insts_mark();
38414 // Start at oper_input_base() and count operands
38415 unsigned idx0 = 1;
38416 unsigned idx1 = 1; // src
38417 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
38418 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
38419 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp1
38420 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // vtmp2
38421 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // scratch
38422 {
38423 C2_MacroAssembler _masm(&cbuf);
38424
38425#line 6618 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
38426
38427 assert(UseAVX > 2, "required")do { if (!(UseAVX > 2)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6619, "assert(" "UseAVX > 2" ") failed", "required"); ::breakpoint
(); } } while (0);
38428
38429 int opcode = this->ideal_Opcode();
38430 int vlen_enc = Assembler::AVX_256bit;
38431 ___masm. evarshiftb(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vlen_enc, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(6)->as_Register(ra_,this,idx6)/* scratch */);
38432 ___masm. vextracti64x4_high(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
38433 ___masm. vextracti64x4_high(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
38434 ___masm. evarshiftb(opcode, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, vlen_enc, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, opnd_array(6)->as_Register(ra_,this,idx6)/* scratch */);
38435 ___masm. vinserti64x4(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, 0x1);
38436
38437#line 38437 "ad_x86.cpp"
38438 }
38439}
38440
38441void vshift64B_var_evex_bw_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38442 cbuf.set_insts_mark();
38443 // Start at oper_input_base() and count operands
38444 unsigned idx0 = 1;
38445 unsigned idx1 = 1; // src
38446 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
38447 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
38448 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp1
38449 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // vtmp2
38450 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // scratch
38451 {
38452 C2_MacroAssembler _masm(&cbuf);
38453
38454#line 6618 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
38455
38456 assert(UseAVX > 2, "required")do { if (!(UseAVX > 2)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6619, "assert(" "UseAVX > 2" ") failed", "required"); ::breakpoint
(); } } while (0);
38457
38458 int opcode = this->ideal_Opcode();
38459 int vlen_enc = Assembler::AVX_256bit;
38460 ___masm. evarshiftb(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vlen_enc, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(6)->as_Register(ra_,this,idx6)/* scratch */);
38461 ___masm. vextracti64x4_high(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
38462 ___masm. vextracti64x4_high(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
38463 ___masm. evarshiftb(opcode, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, vlen_enc, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, opnd_array(6)->as_Register(ra_,this,idx6)/* scratch */);
38464 ___masm. vinserti64x4(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, 0x1);
38465
38466#line 38466 "ad_x86.cpp"
38467 }
38468}
38469
38470void vshift64B_var_evex_bw_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38471 cbuf.set_insts_mark();
38472 // Start at oper_input_base() and count operands
38473 unsigned idx0 = 1;
38474 unsigned idx1 = 1; // src
38475 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
38476 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
38477 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp1
38478 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // vtmp2
38479 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // scratch
38480 {
38481 C2_MacroAssembler _masm(&cbuf);
38482
38483#line 6618 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
38484
38485 assert(UseAVX > 2, "required")do { if (!(UseAVX > 2)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6619, "assert(" "UseAVX > 2" ") failed", "required"); ::breakpoint
(); } } while (0);
38486
38487 int opcode = this->ideal_Opcode();
38488 int vlen_enc = Assembler::AVX_256bit;
38489 ___masm. evarshiftb(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vlen_enc, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(6)->as_Register(ra_,this,idx6)/* scratch */);
38490 ___masm. vextracti64x4_high(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
38491 ___masm. vextracti64x4_high(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
38492 ___masm. evarshiftb(opcode, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, vlen_enc, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, opnd_array(6)->as_Register(ra_,this,idx6)/* scratch */);
38493 ___masm. vinserti64x4(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, 0x1);
38494
38495#line 38495 "ad_x86.cpp"
38496 }
38497}
38498
38499void vshift8S_var_nobwNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38500 cbuf.set_insts_mark();
38501 // Start at oper_input_base() and count operands
38502 unsigned idx0 = 1;
38503 unsigned idx1 = 1; // src
38504 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
38505 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
38506 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp
38507 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch
38508 {
38509 C2_MacroAssembler _masm(&cbuf);
38510
38511#line 6642 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
38512
38513 assert(UseAVX >= 2, "required")do { if (!(UseAVX >= 2)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6643, "assert(" "UseAVX >= 2" ") failed", "required"); ::
breakpoint(); } } while (0);
38514
38515 int opcode = this->ideal_Opcode();
38516 bool sign = (opcode != Op_URShiftVS);
38517 int vlen_enc = Assembler::AVX_256bit;
38518 ___masm. vextendwd(sign, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, 1);
38519 ___masm. vpmovzxwd(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, 1);
38520 ___masm. varshiftd(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp */, vlen_enc);
38521 ___masm. vpand(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, ExternalAddress(vector_int_to_short_mask()), vlen_enc, opnd_array(5)->as_Register(ra_,this,idx5)/* scratch */);
38522 ___masm. vextracti128_high(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */);
38523 ___masm. vpackusdw(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp */, 0);
38524
38525#line 38525 "ad_x86.cpp"
38526 }
38527}
38528
38529void vshift8S_var_nobw_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38530 cbuf.set_insts_mark();
38531 // Start at oper_input_base() and count operands
38532 unsigned idx0 = 1;
38533 unsigned idx1 = 1; // src
38534 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
38535 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
38536 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp
38537 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch
38538 {
38539 C2_MacroAssembler _masm(&cbuf);
38540
38541#line 6642 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
38542
38543 assert(UseAVX >= 2, "required")do { if (!(UseAVX >= 2)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6643, "assert(" "UseAVX >= 2" ") failed", "required"); ::
breakpoint(); } } while (0);
38544
38545 int opcode = this->ideal_Opcode();
38546 bool sign = (opcode != Op_URShiftVS);
38547 int vlen_enc = Assembler::AVX_256bit;
38548 ___masm. vextendwd(sign, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, 1);
38549 ___masm. vpmovzxwd(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, 1);
38550 ___masm. varshiftd(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp */, vlen_enc);
38551 ___masm. vpand(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, ExternalAddress(vector_int_to_short_mask()), vlen_enc, opnd_array(5)->as_Register(ra_,this,idx5)/* scratch */);
38552 ___masm. vextracti128_high(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */);
38553 ___masm. vpackusdw(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp */, 0);
38554
38555#line 38555 "ad_x86.cpp"
38556 }
38557}
38558
38559void vshift8S_var_nobw_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38560 cbuf.set_insts_mark();
38561 // Start at oper_input_base() and count operands
38562 unsigned idx0 = 1;
38563 unsigned idx1 = 1; // src
38564 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
38565 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
38566 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp
38567 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch
38568 {
38569 C2_MacroAssembler _masm(&cbuf);
38570
38571#line 6642 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
38572
38573 assert(UseAVX >= 2, "required")do { if (!(UseAVX >= 2)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6643, "assert(" "UseAVX >= 2" ") failed", "required"); ::
breakpoint(); } } while (0);
38574
38575 int opcode = this->ideal_Opcode();
38576 bool sign = (opcode != Op_URShiftVS);
38577 int vlen_enc = Assembler::AVX_256bit;
38578 ___masm. vextendwd(sign, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, 1);
38579 ___masm. vpmovzxwd(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, 1);
38580 ___masm. varshiftd(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp */, vlen_enc);
38581 ___masm. vpand(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, ExternalAddress(vector_int_to_short_mask()), vlen_enc, opnd_array(5)->as_Register(ra_,this,idx5)/* scratch */);
38582 ___masm. vextracti128_high(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */);
38583 ___masm. vpackusdw(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp */, 0);
38584
38585#line 38585 "ad_x86.cpp"
38586 }
38587}
38588
38589void vshift16S_var_nobwNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38590 cbuf.set_insts_mark();
38591 // Start at oper_input_base() and count operands
38592 unsigned idx0 = 1;
38593 unsigned idx1 = 1; // src
38594 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
38595 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
38596 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp1
38597 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // vtmp2
38598 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // scratch
38599 {
38600 C2_MacroAssembler _masm(&cbuf);
38601
38602#line 6667 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
38603
38604 assert(UseAVX >= 2, "required")do { if (!(UseAVX >= 2)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6668, "assert(" "UseAVX >= 2" ") failed", "required"); ::
breakpoint(); } } while (0);
38605
38606 int opcode = this->ideal_Opcode();
38607 bool sign = (opcode != Op_URShiftVS);
38608 int vlen_enc = Assembler::AVX_256bit;
38609 // Shift lower half, with result in vtmp2 usign vtmp1 as TEMP
38610 ___masm. vextendwd(sign, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vlen_enc);
38611 ___masm. vpmovzxwd(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vlen_enc);
38612 ___masm. varshiftd(opcode, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, vlen_enc);
38613 ___masm. vpand(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, ExternalAddress(vector_int_to_short_mask()), vlen_enc, opnd_array(6)->as_Register(ra_,this,idx6)/* scratch */);
38614
38615 // Shift upper half, with result in dst usign vtmp1 as TEMP
38616 ___masm. vextracti128_high(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
38617 ___masm. vextracti128_high(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
38618 ___masm. vextendwd(sign, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, vlen_enc);
38619 ___masm. vpmovzxwd(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, vlen_enc);
38620 ___masm. varshiftd(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, vlen_enc);
38621 ___masm. vpand(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, ExternalAddress(vector_int_to_short_mask()), vlen_enc, opnd_array(6)->as_Register(ra_,this,idx6)/* scratch */);
38622
38623 // Merge lower and upper half result into dst
38624 ___masm. vpackusdw(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, vlen_enc);
38625 ___masm. vpermq(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, 0xD8, vlen_enc);
38626
38627#line 38627 "ad_x86.cpp"
38628 }
38629}
38630
38631void vshift16S_var_nobw_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38632 cbuf.set_insts_mark();
38633 // Start at oper_input_base() and count operands
38634 unsigned idx0 = 1;
38635 unsigned idx1 = 1; // src
38636 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
38637 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
38638 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp1
38639 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // vtmp2
38640 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // scratch
38641 {
38642 C2_MacroAssembler _masm(&cbuf);
38643
38644#line 6667 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
38645
38646 assert(UseAVX >= 2, "required")do { if (!(UseAVX >= 2)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6668, "assert(" "UseAVX >= 2" ") failed", "required"); ::
breakpoint(); } } while (0);
38647
38648 int opcode = this->ideal_Opcode();
38649 bool sign = (opcode != Op_URShiftVS);
38650 int vlen_enc = Assembler::AVX_256bit;
38651 // Shift lower half, with result in vtmp2 usign vtmp1 as TEMP
38652 ___masm. vextendwd(sign, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vlen_enc);
38653 ___masm. vpmovzxwd(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vlen_enc);
38654 ___masm. varshiftd(opcode, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, vlen_enc);
38655 ___masm. vpand(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, ExternalAddress(vector_int_to_short_mask()), vlen_enc, opnd_array(6)->as_Register(ra_,this,idx6)/* scratch */);
38656
38657 // Shift upper half, with result in dst usign vtmp1 as TEMP
38658 ___masm. vextracti128_high(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
38659 ___masm. vextracti128_high(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
38660 ___masm. vextendwd(sign, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, vlen_enc);
38661 ___masm. vpmovzxwd(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, vlen_enc);
38662 ___masm. varshiftd(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, vlen_enc);
38663 ___masm. vpand(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, ExternalAddress(vector_int_to_short_mask()), vlen_enc, opnd_array(6)->as_Register(ra_,this,idx6)/* scratch */);
38664
38665 // Merge lower and upper half result into dst
38666 ___masm. vpackusdw(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, vlen_enc);
38667 ___masm. vpermq(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, 0xD8, vlen_enc);
38668
38669#line 38669 "ad_x86.cpp"
38670 }
38671}
38672
38673void vshift16S_var_nobw_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38674 cbuf.set_insts_mark();
38675 // Start at oper_input_base() and count operands
38676 unsigned idx0 = 1;
38677 unsigned idx1 = 1; // src
38678 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
38679 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
38680 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp1
38681 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // vtmp2
38682 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // scratch
38683 {
38684 C2_MacroAssembler _masm(&cbuf);
38685
38686#line 6667 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
38687
38688 assert(UseAVX >= 2, "required")do { if (!(UseAVX >= 2)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6668, "assert(" "UseAVX >= 2" ") failed", "required"); ::
breakpoint(); } } while (0);
38689
38690 int opcode = this->ideal_Opcode();
38691 bool sign = (opcode != Op_URShiftVS);
38692 int vlen_enc = Assembler::AVX_256bit;
38693 // Shift lower half, with result in vtmp2 usign vtmp1 as TEMP
38694 ___masm. vextendwd(sign, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vlen_enc);
38695 ___masm. vpmovzxwd(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vlen_enc);
38696 ___masm. varshiftd(opcode, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, vlen_enc);
38697 ___masm. vpand(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, ExternalAddress(vector_int_to_short_mask()), vlen_enc, opnd_array(6)->as_Register(ra_,this,idx6)/* scratch */);
38698
38699 // Shift upper half, with result in dst usign vtmp1 as TEMP
38700 ___masm. vextracti128_high(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
38701 ___masm. vextracti128_high(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */);
38702 ___masm. vextendwd(sign, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, vlen_enc);
38703 ___masm. vpmovzxwd(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, vlen_enc);
38704 ___masm. varshiftd(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, vlen_enc);
38705 ___masm. vpand(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, ExternalAddress(vector_int_to_short_mask()), vlen_enc, opnd_array(6)->as_Register(ra_,this,idx6)/* scratch */);
38706
38707 // Merge lower and upper half result into dst
38708 ___masm. vpackusdw(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, vlen_enc);
38709 ___masm. vpermq(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, 0xD8, vlen_enc);
38710
38711#line 38711 "ad_x86.cpp"
38712 }
38713}
38714
38715void vshift16S_var_evex_bwNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38716 cbuf.set_insts_mark();
38717 // Start at oper_input_base() and count operands
38718 unsigned idx0 = 1;
38719 unsigned idx1 = 1; // src
38720 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
38721 {
38722 C2_MacroAssembler _masm(&cbuf);
38723
38724#line 6701 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
38725
38726 assert(UseAVX > 2, "required")do { if (!(UseAVX > 2)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6702, "assert(" "UseAVX > 2" ") failed", "required"); ::breakpoint
(); } } while (0);
38727
38728 int opcode = this->ideal_Opcode();
38729 int vlen_enc = vector_length_encoding(this);
38730 if (!VM_Version::supports_avx512vl()) {
38731 vlen_enc = Assembler::AVX_512bit;
38732 }
38733 ___masm. varshiftw(opcode, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vlen_enc);
38734
38735#line 38735 "ad_x86.cpp"
38736 }
38737}
38738
38739void vshift16S_var_evex_bw_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38740 cbuf.set_insts_mark();
38741 // Start at oper_input_base() and count operands
38742 unsigned idx0 = 1;
38743 unsigned idx1 = 1; // src
38744 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
38745 {
38746 C2_MacroAssembler _masm(&cbuf);
38747
38748#line 6701 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
38749
38750 assert(UseAVX > 2, "required")do { if (!(UseAVX > 2)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6702, "assert(" "UseAVX > 2" ") failed", "required"); ::breakpoint
(); } } while (0);
38751
38752 int opcode = this->ideal_Opcode();
38753 int vlen_enc = vector_length_encoding(this);
38754 if (!VM_Version::supports_avx512vl()) {
38755 vlen_enc = Assembler::AVX_512bit;
38756 }
38757 ___masm. varshiftw(opcode, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vlen_enc);
38758
38759#line 38759 "ad_x86.cpp"
38760 }
38761}
38762
38763void vshift16S_var_evex_bw_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38764 cbuf.set_insts_mark();
38765 // Start at oper_input_base() and count operands
38766 unsigned idx0 = 1;
38767 unsigned idx1 = 1; // src
38768 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
38769 {
38770 C2_MacroAssembler _masm(&cbuf);
38771
38772#line 6701 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
38773
38774 assert(UseAVX > 2, "required")do { if (!(UseAVX > 2)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6702, "assert(" "UseAVX > 2" ") failed", "required"); ::breakpoint
(); } } while (0);
38775
38776 int opcode = this->ideal_Opcode();
38777 int vlen_enc = vector_length_encoding(this);
38778 if (!VM_Version::supports_avx512vl()) {
38779 vlen_enc = Assembler::AVX_512bit;
38780 }
38781 ___masm. varshiftw(opcode, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vlen_enc);
38782
38783#line 38783 "ad_x86.cpp"
38784 }
38785}
38786
38787void vshiftI_varNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38788 cbuf.set_insts_mark();
38789 // Start at oper_input_base() and count operands
38790 unsigned idx0 = 1;
38791 unsigned idx1 = 1; // src
38792 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
38793 {
38794 C2_MacroAssembler _masm(&cbuf);
38795
38796#line 6721 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
38797
38798 assert(UseAVX >= 2, "required")do { if (!(UseAVX >= 2)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6722, "assert(" "UseAVX >= 2" ") failed", "required"); ::
breakpoint(); } } while (0);
38799
38800 int opcode = this->ideal_Opcode();
38801 int vlen_enc = vector_length_encoding(this);
38802 ___masm. varshiftd(opcode, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vlen_enc);
38803
38804#line 38804 "ad_x86.cpp"
38805 }
38806}
38807
38808void vshiftI_var_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38809 cbuf.set_insts_mark();
38810 // Start at oper_input_base() and count operands
38811 unsigned idx0 = 1;
38812 unsigned idx1 = 1; // src
38813 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
38814 {
38815 C2_MacroAssembler _masm(&cbuf);
38816
38817#line 6721 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
38818
38819 assert(UseAVX >= 2, "required")do { if (!(UseAVX >= 2)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6722, "assert(" "UseAVX >= 2" ") failed", "required"); ::
breakpoint(); } } while (0);
38820
38821 int opcode = this->ideal_Opcode();
38822 int vlen_enc = vector_length_encoding(this);
38823 ___masm. varshiftd(opcode, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vlen_enc);
38824
38825#line 38825 "ad_x86.cpp"
38826 }
38827}
38828
38829void vshiftI_var_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38830 cbuf.set_insts_mark();
38831 // Start at oper_input_base() and count operands
38832 unsigned idx0 = 1;
38833 unsigned idx1 = 1; // src
38834 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
38835 {
38836 C2_MacroAssembler _masm(&cbuf);
38837
38838#line 6721 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
38839
38840 assert(UseAVX >= 2, "required")do { if (!(UseAVX >= 2)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6722, "assert(" "UseAVX >= 2" ") failed", "required"); ::
breakpoint(); } } while (0);
38841
38842 int opcode = this->ideal_Opcode();
38843 int vlen_enc = vector_length_encoding(this);
38844 ___masm. varshiftd(opcode, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vlen_enc);
38845
38846#line 38846 "ad_x86.cpp"
38847 }
38848}
38849
38850void vshiftL_varNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38851 cbuf.set_insts_mark();
38852 // Start at oper_input_base() and count operands
38853 unsigned idx0 = 1;
38854 unsigned idx1 = 1; // src
38855 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
38856 {
38857 C2_MacroAssembler _masm(&cbuf);
38858
38859#line 6737 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
38860
38861 assert(UseAVX >= 2, "required")do { if (!(UseAVX >= 2)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6738, "assert(" "UseAVX >= 2" ") failed", "required"); ::
breakpoint(); } } while (0);
38862
38863 int opcode = this->ideal_Opcode();
38864 int vlen_enc = vector_length_encoding(this);
38865 ___masm. varshiftq(opcode, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vlen_enc);
38866
38867#line 38867 "ad_x86.cpp"
38868 }
38869}
38870
38871void vshiftL_var_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38872 cbuf.set_insts_mark();
38873 // Start at oper_input_base() and count operands
38874 unsigned idx0 = 1;
38875 unsigned idx1 = 1; // src
38876 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
38877 {
38878 C2_MacroAssembler _masm(&cbuf);
38879
38880#line 6737 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
38881
38882 assert(UseAVX >= 2, "required")do { if (!(UseAVX >= 2)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6738, "assert(" "UseAVX >= 2" ") failed", "required"); ::
breakpoint(); } } while (0);
38883
38884 int opcode = this->ideal_Opcode();
38885 int vlen_enc = vector_length_encoding(this);
38886 ___masm. varshiftq(opcode, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vlen_enc);
38887
38888#line 38888 "ad_x86.cpp"
38889 }
38890}
38891
38892void vshiftL_arith_varNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38893 cbuf.set_insts_mark();
38894 // Start at oper_input_base() and count operands
38895 unsigned idx0 = 1;
38896 unsigned idx1 = 1; // src
38897 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
38898 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
38899 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp
38900 {
38901 C2_MacroAssembler _masm(&cbuf);
38902
38903#line 6755 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
38904
38905 int opcode = this->ideal_Opcode();
38906 int vlen_enc = vector_length_encoding(this);
38907 ___masm. varshiftq(opcode, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vlen_enc,
38908 opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp */);
38909
38910#line 38910 "ad_x86.cpp"
38911 }
38912}
38913
38914void vshiftL_arith_var_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38915 cbuf.set_insts_mark();
38916 // Start at oper_input_base() and count operands
38917 unsigned idx0 = 1;
38918 unsigned idx1 = 1; // src
38919 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
38920 {
38921 C2_MacroAssembler _masm(&cbuf);
38922
38923#line 6769 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
38924
38925 int opcode = this->ideal_Opcode();
38926 int vlen_enc = vector_length_encoding(this);
38927 ___masm. varshiftq(opcode, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vlen_enc);
38928
38929#line 38929 "ad_x86.cpp"
38930 }
38931}
38932
38933void vandNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38934 cbuf.set_insts_mark();
38935 // Start at oper_input_base() and count operands
38936 unsigned idx0 = 1;
38937 unsigned idx1 = 1; // dst
38938 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
38939 {
38940 C2_MacroAssembler _masm(&cbuf);
38941
38942#line 6783 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
38943
38944 ___masm. pand(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
38945
38946#line 38946 "ad_x86.cpp"
38947 }
38948}
38949
38950void vand_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38951 cbuf.set_insts_mark();
38952 // Start at oper_input_base() and count operands
38953 unsigned idx0 = 1;
38954 unsigned idx1 = 1; // src1
38955 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
38956 {
38957 C2_MacroAssembler _masm(&cbuf);
38958
38959#line 6793 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
38960
38961 int vlen_enc = vector_length_encoding(this);
38962 ___masm. vpand(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vlen_enc);
38963
38964#line 38964 "ad_x86.cpp"
38965 }
38966}
38967
38968void vand_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38969 cbuf.set_insts_mark();
38970 // Start at oper_input_base() and count operands
38971 unsigned idx0 = 2;
38972 unsigned idx1 = 2; // src
38973 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
38974 {
38975 C2_MacroAssembler _masm(&cbuf);
38976
38977#line 6805 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
38978
38979 int vlen_enc = vector_length_encoding(this);
38980 ___masm. vpand(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vlen_enc);
38981
38982#line 38982 "ad_x86.cpp"
38983 }
38984}
38985
38986void vand_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
38987 cbuf.set_insts_mark();
38988 // Start at oper_input_base() and count operands
38989 unsigned idx0 = 2;
38990 unsigned idx1 = 2; // mem
38991 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
38992 {
38993 C2_MacroAssembler _masm(&cbuf);
38994
38995#line 6805 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
38996
38997 int vlen_enc = vector_length_encoding(this);
38998 ___masm. vpand(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vlen_enc);
38999
39000#line 39000 "ad_x86.cpp"
39001 }
39002}
39003
39004void vorNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39005 cbuf.set_insts_mark();
39006 // Start at oper_input_base() and count operands
39007 unsigned idx0 = 1;
39008 unsigned idx1 = 1; // dst
39009 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
39010 {
39011 C2_MacroAssembler _masm(&cbuf);
39012
39013#line 6818 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
39014
39015 ___masm. por(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
39016
39017#line 39017 "ad_x86.cpp"
39018 }
39019}
39020
39021void vor_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39022 cbuf.set_insts_mark();
39023 // Start at oper_input_base() and count operands
39024 unsigned idx0 = 1;
39025 unsigned idx1 = 1; // src1
39026 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
39027 {
39028 C2_MacroAssembler _masm(&cbuf);
39029
39030#line 6828 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
39031
39032 int vlen_enc = vector_length_encoding(this);
39033 ___masm. vpor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vlen_enc);
39034
39035#line 39035 "ad_x86.cpp"
39036 }
39037}
39038
39039void vor_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39040 cbuf.set_insts_mark();
39041 // Start at oper_input_base() and count operands
39042 unsigned idx0 = 2;
39043 unsigned idx1 = 2; // src
39044 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
39045 {
39046 C2_MacroAssembler _masm(&cbuf);
39047
39048#line 6840 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
39049
39050 int vlen_enc = vector_length_encoding(this);
39051 ___masm. vpor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vlen_enc);
39052
39053#line 39053 "ad_x86.cpp"
39054 }
39055}
39056
39057void vor_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39058 cbuf.set_insts_mark();
39059 // Start at oper_input_base() and count operands
39060 unsigned idx0 = 2;
39061 unsigned idx1 = 2; // mem
39062 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
39063 {
39064 C2_MacroAssembler _masm(&cbuf);
39065
39066#line 6840 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
39067
39068 int vlen_enc = vector_length_encoding(this);
39069 ___masm. vpor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vlen_enc);
39070
39071#line 39071 "ad_x86.cpp"
39072 }
39073}
39074
39075void vxorNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39076 cbuf.set_insts_mark();
39077 // Start at oper_input_base() and count operands
39078 unsigned idx0 = 1;
39079 unsigned idx1 = 1; // dst
39080 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
39081 {
39082 C2_MacroAssembler _masm(&cbuf);
39083
39084#line 6853 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
39085
39086 ___masm. pxor(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */);
39087
39088#line 39088 "ad_x86.cpp"
39089 }
39090}
39091
39092void vxor_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39093 cbuf.set_insts_mark();
39094 // Start at oper_input_base() and count operands
39095 unsigned idx0 = 1;
39096 unsigned idx1 = 1; // src1
39097 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
39098 {
39099 C2_MacroAssembler _masm(&cbuf);
39100
39101#line 6863 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
39102
39103 int vlen_enc = vector_length_encoding(this);
39104 ___masm. vpxor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vlen_enc);
39105
39106#line 39106 "ad_x86.cpp"
39107 }
39108}
39109
39110void vxor_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39111 cbuf.set_insts_mark();
39112 // Start at oper_input_base() and count operands
39113 unsigned idx0 = 2;
39114 unsigned idx1 = 2; // src
39115 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mem
39116 {
39117 C2_MacroAssembler _masm(&cbuf);
39118
39119#line 6875 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
39120
39121 int vlen_enc = vector_length_encoding(this);
39122 ___masm. vpxor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), vlen_enc);
39123
39124#line 39124 "ad_x86.cpp"
39125 }
39126}
39127
39128void vxor_mem_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39129 cbuf.set_insts_mark();
39130 // Start at oper_input_base() and count operands
39131 unsigned idx0 = 2;
39132 unsigned idx1 = 2; // mem
39133 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
39134 {
39135 C2_MacroAssembler _masm(&cbuf);
39136
39137#line 6875 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
39138
39139 int vlen_enc = vector_length_encoding(this);
39140 ___masm. vpxor(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vlen_enc);
39141
39142#line 39142 "ad_x86.cpp"
39143 }
39144}
39145
39146void vcastBtoXNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39147 cbuf.set_insts_mark();
39148 // Start at oper_input_base() and count operands
39149 unsigned idx0 = 1;
39150 unsigned idx1 = 1; // src
39151 {
39152 C2_MacroAssembler _masm(&cbuf);
39153
39154#line 6887 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
39155
39156 assert(UseAVX > 0, "required")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6888, "assert(" "UseAVX > 0" ") failed", "required"); ::breakpoint
(); } } while (0);
39157
39158 BasicType to_elem_bt = Matcher::vector_element_basic_type(this);
39159 int vlen_enc = vector_length_encoding(this);
39160 switch (to_elem_bt) {
39161 case T_SHORT:
39162 ___masm. vpmovsxbw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vlen_enc);
39163 break;
39164 case T_INT:
39165 ___masm. vpmovsxbd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vlen_enc);
39166 break;
39167 case T_FLOAT:
39168 ___masm. vpmovsxbd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vlen_enc);
39169 ___masm. vcvtdq2ps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, vlen_enc);
39170 break;
39171 case T_LONG:
39172 ___masm. vpmovsxbq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vlen_enc);
39173 break;
39174 case T_DOUBLE:
39175 ___masm. vpmovsxbd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vlen_enc);
39176 ___masm. vcvtdq2pd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, vlen_enc);
39177 break;
39178
39179 default: assert(false, "%s", type2name(to_elem_bt))do { if (!(false)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6911, "assert(" "false" ") failed", "%s", type2name(to_elem_bt
)); ::breakpoint(); } } while (0);
39180 }
39181
39182#line 39182 "ad_x86.cpp"
39183 }
39184}
39185
39186void castStoXNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39187 cbuf.set_insts_mark();
39188 // Start at oper_input_base() and count operands
39189 unsigned idx0 = 1;
39190 unsigned idx1 = 1; // src
39191 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // scratch
39192 {
39193 C2_MacroAssembler _masm(&cbuf);
39194
39195#line 6924 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
39196
39197 assert(UseAVX > 0, "required")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6925, "assert(" "UseAVX > 0" ") failed", "required"); ::breakpoint
(); } } while (0);
39198
39199 ___masm. vpand(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, ExternalAddress(vector_short_to_byte_mask()), 0, opnd_array(2)->as_Register(ra_,this,idx2)/* scratch */);
39200 ___masm. vpackuswb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, 0);
39201
39202#line 39202 "ad_x86.cpp"
39203 }
39204}
39205
39206void vcastStoXNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39207 cbuf.set_insts_mark();
39208 // Start at oper_input_base() and count operands
39209 unsigned idx0 = 1;
39210 unsigned idx1 = 1; // src
39211 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
39212 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp
39213 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // scratch
39214 {
39215 C2_MacroAssembler _masm(&cbuf);
39216
39217#line 6940 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
39218
39219 assert(UseAVX > 0, "required")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6941, "assert(" "UseAVX > 0" ") failed", "required"); ::breakpoint
(); } } while (0);
39220
39221 int vlen_enc = vector_length_encoding(Matcher::vector_length_in_bytes(this, opnd_array(1)));
39222 ___masm. vpand(opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, ExternalAddress(vector_short_to_byte_mask()), vlen_enc, opnd_array(4)->as_Register(ra_,this,idx4)/* scratch */);
39223 ___masm. vextracti128(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* dst */, 0x1);
39224 ___masm. vpackuswb(opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp */, 0);
39225
39226#line 39226 "ad_x86.cpp"
39227 }
39228}
39229
39230void vcastStoX_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39231 cbuf.set_insts_mark();
39232 // Start at oper_input_base() and count operands
39233 unsigned idx0 = 1;
39234 unsigned idx1 = 1; // src
39235 {
39236 C2_MacroAssembler _masm(&cbuf);
39237
39238#line 6956 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
39239
39240 BasicType to_elem_bt = Matcher::vector_element_basic_type(this);
39241 int src_vlen_enc = vector_length_encoding(this, opnd_array(1));
39242 int vlen_enc = vector_length_encoding(this);
39243 switch (to_elem_bt) {
39244 case T_BYTE:
39245 if (!VM_Version::supports_avx512vl()) {
39246 vlen_enc = Assembler::AVX_512bit;
39247 }
39248 ___masm. evpmovwb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, src_vlen_enc);
39249 break;
39250 case T_INT:
39251 ___masm. vpmovsxwd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vlen_enc);
39252 break;
39253 case T_FLOAT:
39254 ___masm. vpmovsxwd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vlen_enc);
39255 ___masm. vcvtdq2ps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, vlen_enc);
39256 break;
39257 case T_LONG:
39258 ___masm. vpmovsxwq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vlen_enc);
39259 break;
39260 case T_DOUBLE:
39261 ___masm. vpmovsxwd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vlen_enc);
39262 ___masm. vcvtdq2pd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, vlen_enc);
39263 break;
39264 default:
39265 ShouldNotReachHere()do { (*g_assert_poison) = 'X';; report_should_not_reach_here(
"/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad", 6982
); ::breakpoint(); } while (0);
39266 }
39267
39268#line 39268 "ad_x86.cpp"
39269 }
39270}
39271
39272void castItoXNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39273 cbuf.set_insts_mark();
39274 // Start at oper_input_base() and count operands
39275 unsigned idx0 = 1;
39276 unsigned idx1 = 1; // src
39277 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // scratch
39278 {
39279 C2_MacroAssembler _masm(&cbuf);
39280
39281#line 6995 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
39282
39283 assert(UseAVX > 0, "required")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
6996, "assert(" "UseAVX > 0" ") failed", "required"); ::breakpoint
(); } } while (0);
39284
39285 BasicType to_elem_bt = Matcher::vector_element_basic_type(this);
39286 int vlen_enc = vector_length_encoding(this, opnd_array(1));
39287
39288 if (to_elem_bt == T_BYTE) {
39289 ___masm. vpand(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, ExternalAddress(vector_int_to_byte_mask()), vlen_enc, opnd_array(2)->as_Register(ra_,this,idx2)/* scratch */);
39290 ___masm. vpackusdw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, vlen_enc);
39291 ___masm. vpackuswb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, vlen_enc);
39292 } else {
39293 assert(to_elem_bt == T_SHORT, "%s", type2name(to_elem_bt))do { if (!(to_elem_bt == T_SHORT)) { (*g_assert_poison) = 'X'
;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 7006, "assert(" "to_elem_bt == T_SHORT" ") failed", "%s", type2name
(to_elem_bt)); ::breakpoint(); } } while (0);
39294 ___masm. vpand(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, ExternalAddress(vector_int_to_short_mask()), vlen_enc, opnd_array(2)->as_Register(ra_,this,idx2)/* scratch */);
39295 ___masm. vpackusdw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, vlen_enc);
39296 }
39297
39298#line 39298 "ad_x86.cpp"
39299 }
39300}
39301
39302void vcastItoXNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39303 cbuf.set_insts_mark();
39304 // Start at oper_input_base() and count operands
39305 unsigned idx0 = 1;
39306 unsigned idx1 = 1; // src
39307 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
39308 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp
39309 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // scratch
39310 {
39311 C2_MacroAssembler _masm(&cbuf);
39312
39313#line 7021 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
39314
39315 assert(UseAVX > 0, "required")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
7022, "assert(" "UseAVX > 0" ") failed", "required"); ::breakpoint
(); } } while (0);
39316
39317 BasicType to_elem_bt = Matcher::vector_element_basic_type(this);
39318 int vlen_enc = vector_length_encoding(this, opnd_array(1));
39319
39320 if (to_elem_bt == T_BYTE) {
39321 ___masm. vpand(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, ExternalAddress(vector_int_to_byte_mask()), vlen_enc, opnd_array(4)->as_Register(ra_,this,idx4)/* scratch */);
39322 ___masm. vextracti128(opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp */, 0x1);
39323 ___masm. vpackusdw(opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* dst */, vlen_enc);
39324 ___masm. vpackuswb(opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* dst */, Assembler::AVX_128bit);
39325 } else {
39326 assert(to_elem_bt == T_SHORT, "%s", type2name(to_elem_bt))do { if (!(to_elem_bt == T_SHORT)) { (*g_assert_poison) = 'X'
;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 7033, "assert(" "to_elem_bt == T_SHORT" ") failed", "%s", type2name
(to_elem_bt)); ::breakpoint(); } } while (0);
39327 ___masm. vpand(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, ExternalAddress(vector_int_to_short_mask()), vlen_enc, opnd_array(4)->as_Register(ra_,this,idx4)/* scratch */);
39328 ___masm. vextracti128(opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp */, 0x1);
39329 ___masm. vpackusdw(opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* dst */, vlen_enc);
39330 }
39331
39332#line 39332 "ad_x86.cpp"
39333 }
39334}
39335
39336void vcastItoX_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39337 cbuf.set_insts_mark();
39338 // Start at oper_input_base() and count operands
39339 unsigned idx0 = 1;
39340 unsigned idx1 = 1; // src
39341 {
39342 C2_MacroAssembler _masm(&cbuf);
39343
39344#line 7047 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
39345
39346 assert(UseAVX > 0, "required")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
7048, "assert(" "UseAVX > 0" ") failed", "required"); ::breakpoint
(); } } while (0);
39347
39348 BasicType dst_elem_bt = Matcher::vector_element_basic_type(this);
39349 int src_vlen_enc = vector_length_encoding(this, opnd_array(1));
39350 int dst_vlen_enc = vector_length_encoding(this);
39351 switch (dst_elem_bt) {
39352 case T_BYTE:
39353 if (!VM_Version::supports_avx512vl()) {
39354 src_vlen_enc = Assembler::AVX_512bit;
39355 }
39356 ___masm. evpmovdb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, src_vlen_enc);
39357 break;
39358 case T_SHORT:
39359 if (!VM_Version::supports_avx512vl()) {
39360 src_vlen_enc = Assembler::AVX_512bit;
39361 }
39362 ___masm. evpmovdw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, src_vlen_enc);
39363 break;
39364 case T_FLOAT:
39365 ___masm. vcvtdq2ps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, dst_vlen_enc);
39366 break;
39367 case T_LONG:
39368 ___masm. vpmovsxdq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, dst_vlen_enc);
39369 break;
39370 case T_DOUBLE:
39371 ___masm. vcvtdq2pd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, dst_vlen_enc);
39372 break;
39373 default:
39374 ShouldNotReachHere()do { (*g_assert_poison) = 'X';; report_should_not_reach_here(
"/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad", 7076
); ::breakpoint(); } while (0);
39375 }
39376
39377#line 39377 "ad_x86.cpp"
39378 }
39379}
39380
39381void vcastLtoBSNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39382 cbuf.set_insts_mark();
39383 // Start at oper_input_base() and count operands
39384 unsigned idx0 = 1;
39385 unsigned idx1 = 1; // src
39386 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // scratch
39387 {
39388 C2_MacroAssembler _masm(&cbuf);
39389
39390#line 7088 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
39391
39392 assert(UseAVX > 0, "required")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
7089, "assert(" "UseAVX > 0" ") failed", "required"); ::breakpoint
(); } } while (0);
39393
39394 int vlen = Matcher::vector_length_in_bytes(this, opnd_array(1));
39395 BasicType to_elem_bt = Matcher::vector_element_basic_type(this);
39396 AddressLiteral mask_addr = (to_elem_bt == T_BYTE) ? ExternalAddress(vector_int_to_byte_mask())
39397 : ExternalAddress(vector_int_to_short_mask());
39398 if (vlen <= 16) {
39399 ___masm. vpshufd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, 8, Assembler::AVX_128bit);
39400 ___masm. vpand(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, mask_addr, Assembler::AVX_128bit, opnd_array(2)->as_Register(ra_,this,idx2)/* scratch */);
39401 ___masm. vpackusdw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Assembler::AVX_128bit);
39402 } else {
39403 assert(vlen <= 32, "required")do { if (!(vlen <= 32)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
7100, "assert(" "vlen <= 32" ") failed", "required"); ::breakpoint
(); } } while (0);
39404 ___masm. vpermilps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, 8, Assembler::AVX_256bit);
39405 ___masm. vpermpd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, 8, Assembler::AVX_256bit);
39406 ___masm. vpand(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, mask_addr, Assembler::AVX_128bit, opnd_array(2)->as_Register(ra_,this,idx2)/* scratch */);
39407 ___masm. vpackusdw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Assembler::AVX_128bit);
39408 }
39409 if (to_elem_bt == T_BYTE) {
39410 ___masm. vpackuswb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Assembler::AVX_128bit);
39411 }
39412
39413#line 39413 "ad_x86.cpp"
39414 }
39415}
39416
39417void vcastLtoX_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39418 cbuf.set_insts_mark();
39419 // Start at oper_input_base() and count operands
39420 unsigned idx0 = 1;
39421 unsigned idx1 = 1; // src
39422 {
39423 C2_MacroAssembler _masm(&cbuf);
39424
39425#line 7120 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
39426
39427 BasicType to_elem_bt = Matcher::vector_element_basic_type(this);
39428 int vlen = Matcher::vector_length_in_bytes(this, opnd_array(1));
39429 int vlen_enc = vector_length_encoding(this, opnd_array(1));
39430 switch (to_elem_bt) {
39431 case T_BYTE:
39432 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
39433 vlen_enc = Assembler::AVX_512bit;
39434 }
39435 ___masm. evpmovqb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vlen_enc);
39436 break;
39437 case T_SHORT:
39438 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
39439 vlen_enc = Assembler::AVX_512bit;
39440 }
39441 ___masm. evpmovqw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vlen_enc);
39442 break;
39443 case T_INT:
39444 if (vlen == 8) {
39445 if (opnd_array(0)->as_XMMRegister(ra_,this)/* dst */!= opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */) {
39446 ___masm. movflt(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
39447 }
39448 } else if (vlen == 16) {
39449 ___masm. pshufd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, 8);
39450 } else if (vlen == 32) {
39451 if (UseAVX > 2) {
39452 if (!VM_Version::supports_avx512vl()) {
39453 vlen_enc = Assembler::AVX_512bit;
39454 }
39455 ___masm. evpmovqd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vlen_enc);
39456 } else {
39457 ___masm. vpermilps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, 8, vlen_enc);
39458 ___masm. vpermpd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, 8, vlen_enc);
39459 }
39460 } else { // vlen == 64
39461 ___masm. evpmovqd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vlen_enc);
39462 }
39463 break;
39464 case T_FLOAT:
39465 assert(UseAVX > 2 && VM_Version::supports_avx512dq(), "required")do { if (!(UseAVX > 2 && VM_Version::supports_avx512dq
())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 7159, "assert(" "UseAVX > 2 && VM_Version::supports_avx512dq()"
") failed", "required"); ::breakpoint(); } } while (0);
39466 ___masm. evcvtqq2ps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vlen_enc);
39467 break;
39468 case T_DOUBLE:
39469 assert(UseAVX > 2 && VM_Version::supports_avx512dq(), "required")do { if (!(UseAVX > 2 && VM_Version::supports_avx512dq
())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 7163, "assert(" "UseAVX > 2 && VM_Version::supports_avx512dq()"
") failed", "required"); ::breakpoint(); } } while (0);
39470 ___masm. evcvtqq2pd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vlen_enc);
39471 break;
39472
39473 default: assert(false, "%s", type2name(to_elem_bt))do { if (!(false)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
7167, "assert(" "false" ") failed", "%s", type2name(to_elem_bt
)); ::breakpoint(); } } while (0);
39474 }
39475
39476#line 39476 "ad_x86.cpp"
39477 }
39478}
39479
39480void vcastFtoD_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39481 cbuf.set_insts_mark();
39482 // Start at oper_input_base() and count operands
39483 unsigned idx0 = 1;
39484 unsigned idx1 = 1; // src
39485 {
39486 C2_MacroAssembler _masm(&cbuf);
39487
39488#line 7177 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
39489
39490 int vlen_enc = vector_length_encoding(this);
39491 ___masm. vcvtps2pd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vlen_enc);
39492
39493#line 39493 "ad_x86.cpp"
39494 }
39495}
39496
39497void vcastFtoI_reg_avxNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39498 cbuf.set_insts_mark();
39499 // Start at oper_input_base() and count operands
39500 unsigned idx0 = 1;
39501 unsigned idx1 = 1; // src
39502 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
39503 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // xtmp1
39504 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // xtmp2
39505 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // xtmp3
39506 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // xtmp4
39507 unsigned idx7 = idx6 + opnd_array(6)->num_edges(); // scratch
39508 {
39509 C2_MacroAssembler _masm(&cbuf);
39510
39511#line 7191 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
39512
39513 int vlen_enc = vector_length_encoding(this);
39514 ___masm. vector_castF2I_avx(opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* xtmp1 */,
39515 opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* xtmp2 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* xtmp3 */, opnd_array(6)->as_XMMRegister(ra_,this,idx6)/* xtmp4 */,
39516 ExternalAddress(vector_float_signflip()), opnd_array(7)->as_Register(ra_,this,idx7)/* scratch */, vlen_enc);
39517
39518#line 39518 "ad_x86.cpp"
39519 }
39520}
39521
39522void vcastFtoI_reg_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39523 cbuf.set_insts_mark();
39524 // Start at oper_input_base() and count operands
39525 unsigned idx0 = 1;
39526 unsigned idx1 = 1; // src
39527 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
39528 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // xtmp1
39529 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // xtmp2
39530 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // ktmp1
39531 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // ktmp2
39532 unsigned idx7 = idx6 + opnd_array(6)->num_edges(); // scratch
39533 {
39534 C2_MacroAssembler _masm(&cbuf);
39535
39536#line 7207 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
39537
39538 int vlen_enc = vector_length_encoding(this);
39539 ___masm. vector_castF2I_evex(opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* xtmp1 */,
39540 opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* xtmp2 */, opnd_array(5)->as_KRegister(ra_,this,idx5)/* ktmp1 */, opnd_array(6)->as_KRegister(ra_,this,idx6)/* ktmp2 */,
39541 ExternalAddress(vector_float_signflip()), opnd_array(7)->as_Register(ra_,this,idx7)/* scratch */, vlen_enc);
39542
39543#line 39543 "ad_x86.cpp"
39544 }
39545}
39546
39547void vcastDtoF_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39548 cbuf.set_insts_mark();
39549 // Start at oper_input_base() and count operands
39550 unsigned idx0 = 1;
39551 unsigned idx1 = 1; // src
39552 {
39553 C2_MacroAssembler _masm(&cbuf);
39554
39555#line 7220 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
39556
39557 int vlen_enc = vector_length_encoding(this, opnd_array(1));
39558 ___masm. vcvtpd2ps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vlen_enc);
39559
39560#line 39560 "ad_x86.cpp"
39561 }
39562}
39563
39564void vcastDtoL_reg_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39565 cbuf.set_insts_mark();
39566 // Start at oper_input_base() and count operands
39567 unsigned idx0 = 1;
39568 unsigned idx1 = 1; // src
39569 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
39570 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // xtmp1
39571 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // xtmp2
39572 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // ktmp1
39573 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // ktmp2
39574 unsigned idx7 = idx6 + opnd_array(6)->num_edges(); // scratch
39575 {
39576 C2_MacroAssembler _masm(&cbuf);
39577
39578#line 7232 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
39579
39580 int vlen_enc = vector_length_encoding(this);
39581 ___masm. vector_castD2L_evex(opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* xtmp1 */,
39582 opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* xtmp2 */, opnd_array(5)->as_KRegister(ra_,this,idx5)/* ktmp1 */, opnd_array(6)->as_KRegister(ra_,this,idx6)/* ktmp2 */,
39583 ExternalAddress(vector_double_signflip()), opnd_array(7)->as_Register(ra_,this,idx7)/* scratch */, vlen_enc);
39584
39585#line 39585 "ad_x86.cpp"
39586 }
39587}
39588
39589void vcmpFDNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39590 cbuf.set_insts_mark();
39591 // Start at oper_input_base() and count operands
39592 unsigned idx0 = 1;
39593 unsigned idx1 = 1; // src1
39594 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
39595 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // cond
39596 {
39597 C2_MacroAssembler _masm(&cbuf);
39598
39599#line 7250 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
39600
39601 int vlen_enc = vector_length_encoding(this, opnd_array(1));
39602 Assembler::ComparisonPredicateFP cmp = booltest_pred_to_comparison_pred_fp(opnd_array(3)->constant());
39603 if (Matcher::vector_element_basic_type(this, opnd_array(1)) == T_FLOAT) {
39604 ___masm. vcmpps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, cmp, vlen_enc);
39605 } else {
39606 ___masm. vcmppd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, cmp, vlen_enc);
39607 }
39608
39609#line 39609 "ad_x86.cpp"
39610 }
39611}
39612
39613void evcmpFD64Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39614 cbuf.set_insts_mark();
39615 // Start at oper_input_base() and count operands
39616 unsigned idx0 = 1;
39617 unsigned idx1 = 1; // src1
39618 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
39619 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // cond
39620 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // scratch
39621 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // ktmp
39622 {
39623 C2_MacroAssembler _masm(&cbuf);
39624
39625#line 7269 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
39626
39627 int vlen_enc = Assembler::AVX_512bit;
39628 Assembler::ComparisonPredicateFP cmp = booltest_pred_to_comparison_pred_fp(opnd_array(3)->constant());
39629 KRegister mask = k0; // The comparison itself is not being masked.
39630 if (Matcher::vector_element_basic_type(this, opnd_array(1)) == T_FLOAT) {
39631 ___masm. evcmpps(opnd_array(5)->as_KRegister(ra_,this,idx5)/* ktmp */, mask, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, cmp, vlen_enc);
39632 ___masm. evmovdqul(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(5)->as_KRegister(ra_,this,idx5)/* ktmp */, ExternalAddress(vector_all_bits_set()), false, vlen_enc, opnd_array(4)->as_Register(ra_,this,idx4)/* scratch */);
39633 } else {
39634 ___masm. evcmppd(opnd_array(5)->as_KRegister(ra_,this,idx5)/* ktmp */, mask, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, cmp, vlen_enc);
39635 ___masm. evmovdquq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(5)->as_KRegister(ra_,this,idx5)/* ktmp */, ExternalAddress(vector_all_bits_set()), false, vlen_enc, opnd_array(4)->as_Register(ra_,this,idx4)/* scratch */);
39636 }
39637
39638#line 39638 "ad_x86.cpp"
39639 }
39640}
39641
39642void evcmpFDNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39643 cbuf.set_insts_mark();
39644 // Start at oper_input_base() and count operands
39645 unsigned idx0 = 1;
39646 unsigned idx1 = 1; // src1
39647 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
39648 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // cond
39649 {
39650 C2_MacroAssembler _masm(&cbuf);
39651
39652#line 7289 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
39653
39654 assert(bottom_type()->isa_vectmask(), "TypeVectMask expected")do { if (!(bottom_type()->isa_vectmask())) { (*g_assert_poison
) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 7290, "assert(" "bottom_type()->isa_vectmask()" ") failed"
, "TypeVectMask expected"); ::breakpoint(); } } while (0);
39655 int vlen_enc = vector_length_encoding(this, opnd_array(1));
39656 Assembler::ComparisonPredicateFP cmp = booltest_pred_to_comparison_pred_fp(opnd_array(3)->constant());
39657 KRegister mask = k0; // The comparison itself is not being masked.
39658 if (Matcher::vector_element_basic_type(this, opnd_array(1)) == T_FLOAT) {
39659 ___masm. evcmpps(opnd_array(0)->as_KRegister(ra_,this)/* dst */, mask, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, cmp, vlen_enc);
39660 } else {
39661 ___masm. evcmppd(opnd_array(0)->as_KRegister(ra_,this)/* dst */, mask, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, cmp, vlen_enc);
39662 }
39663
39664#line 39664 "ad_x86.cpp"
39665 }
39666}
39667
39668void vcmpNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39669 cbuf.set_insts_mark();
39670 // Start at oper_input_base() and count operands
39671 unsigned idx0 = 1;
39672 unsigned idx1 = 1; // src1
39673 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
39674 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // cond
39675 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // scratch
39676 {
39677 C2_MacroAssembler _masm(&cbuf);
39678
39679#line 7312 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
39680
39681 int vlen_enc = vector_length_encoding(this, opnd_array(1));
39682 Assembler::ComparisonPredicate cmp = booltest_pred_to_comparison_pred(opnd_array(3)->constant());
39683 Assembler::Width ww = widthForType(Matcher::vector_element_basic_type(this, opnd_array(1)));
39684 ___masm. vpcmpCCW(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, cmp, ww, vlen_enc, opnd_array(4)->as_Register(ra_,this,idx4)/* scratch */);
39685
39686#line 39686 "ad_x86.cpp"
39687 }
39688}
39689
39690void vcmpuNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39691 cbuf.set_insts_mark();
39692 // Start at oper_input_base() and count operands
39693 unsigned idx0 = 1;
39694 unsigned idx1 = 1; // src1
39695 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
39696 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // cond
39697 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp1
39698 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // vtmp2
39699 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // scratch
39700 {
39701 C2_MacroAssembler _masm(&cbuf);
39702
39703#line 7330 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
39704
39705 int vlen = Matcher::vector_length_in_bytes(this, opnd_array(1));
39706 Assembler::ComparisonPredicate cmp = booltest_pred_to_comparison_pred(opnd_array(3)->constant());
39707 BasicType bt = Matcher::vector_element_basic_type(this, opnd_array(1));
39708 ___masm. vpcmpu(bt, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, cmp, vlen, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */,
39709 opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, opnd_array(6)->as_Register(ra_,this,idx6)/* scratch */);
39710
39711#line 39711 "ad_x86.cpp"
39712 }
39713}
39714
39715void vcmpu32Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39716 cbuf.set_insts_mark();
39717 // Start at oper_input_base() and count operands
39718 unsigned idx0 = 1;
39719 unsigned idx1 = 1; // src1
39720 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
39721 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // cond
39722 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // dst
39723 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // vtmp1
39724 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // vtmp2
39725 unsigned idx7 = idx6 + opnd_array(6)->num_edges(); // vtmp3
39726 unsigned idx8 = idx7 + opnd_array(7)->num_edges(); // scratch
39727 {
39728 C2_MacroAssembler _masm(&cbuf);
39729
39730#line 7348 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
39731
39732 int vlen = Matcher::vector_length_in_bytes(this, opnd_array(1));
39733 Assembler::ComparisonPredicate cmp = booltest_pred_to_comparison_pred(opnd_array(3)->constant());
39734 BasicType bt = Matcher::vector_element_basic_type(this, opnd_array(1));
39735 ___masm. vpcmpu32(bt, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, cmp, vlen, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp1 */,
39736 opnd_array(6)->as_XMMRegister(ra_,this,idx6)/* vtmp2 */, opnd_array(7)->as_XMMRegister(ra_,this,idx7)/* vtmp3 */, opnd_array(8)->as_Register(ra_,this,idx8)/* scratch */);
39737
39738#line 39738 "ad_x86.cpp"
39739 }
39740}
39741
39742void vcmpu64Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39743 cbuf.set_insts_mark();
39744 // Start at oper_input_base() and count operands
39745 unsigned idx0 = 1;
39746 unsigned idx1 = 1; // src1
39747 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
39748 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // cond
39749 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // scratch
39750 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // ktmp
39751 {
39752 C2_MacroAssembler _masm(&cbuf);
39753
39754#line 7365 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
39755
39756 assert(UseAVX > 2, "required")do { if (!(UseAVX > 2)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
7366, "assert(" "UseAVX > 2" ") failed", "required"); ::breakpoint
(); } } while (0);
39757
39758 int vlen_enc = vector_length_encoding(this, opnd_array(1));
39759 Assembler::ComparisonPredicate cmp = booltest_pred_to_comparison_pred(opnd_array(3)->constant());
39760 bool is_unsigned = is_unsigned_booltest_pred(opnd_array(3)->constant());
39761 KRegister mask = k0; // The comparison itself is not being masked.
39762 bool merge = false;
39763 BasicType src1_elem_bt = Matcher::vector_element_basic_type(this, opnd_array(1));
39764
39765 switch (src1_elem_bt) {
39766 case T_INT: {
39767 ___masm. evpcmpd(opnd_array(5)->as_KRegister(ra_,this,idx5)/* ktmp */, mask, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, cmp, !is_unsigned, vlen_enc);
39768 ___masm. evmovdqul(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(5)->as_KRegister(ra_,this,idx5)/* ktmp */, ExternalAddress(vector_all_bits_set()), merge, vlen_enc, opnd_array(4)->as_Register(ra_,this,idx4)/* scratch */);
39769 break;
39770 }
39771 case T_LONG: {
39772 ___masm. evpcmpq(opnd_array(5)->as_KRegister(ra_,this,idx5)/* ktmp */, mask, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, cmp, !is_unsigned, vlen_enc);
39773 ___masm. evmovdquq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(5)->as_KRegister(ra_,this,idx5)/* ktmp */, ExternalAddress(vector_all_bits_set()), merge, vlen_enc, opnd_array(4)->as_Register(ra_,this,idx4)/* scratch */);
39774 break;
39775 }
39776 default: assert(false, "%s", type2name(src1_elem_bt))do { if (!(false)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
7386, "assert(" "false" ") failed", "%s", type2name(src1_elem_bt
)); ::breakpoint(); } } while (0);
39777 }
39778
39779#line 39779 "ad_x86.cpp"
39780 }
39781}
39782
39783void evcmpNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39784 cbuf.set_insts_mark();
39785 // Start at oper_input_base() and count operands
39786 unsigned idx0 = 1;
39787 unsigned idx1 = 1; // src1
39788 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
39789 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // cond
39790 {
39791 C2_MacroAssembler _masm(&cbuf);
39792
39793#line 7398 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
39794
39795 assert(UseAVX > 2, "required")do { if (!(UseAVX > 2)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
7399, "assert(" "UseAVX > 2" ") failed", "required"); ::breakpoint
(); } } while (0);
39796 assert(bottom_type()->isa_vectmask(), "TypeVectMask expected")do { if (!(bottom_type()->isa_vectmask())) { (*g_assert_poison
) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 7400, "assert(" "bottom_type()->isa_vectmask()" ") failed"
, "TypeVectMask expected"); ::breakpoint(); } } while (0);
39797
39798 int vlen_enc = vector_length_encoding(this, opnd_array(1));
39799 Assembler::ComparisonPredicate cmp = booltest_pred_to_comparison_pred(opnd_array(3)->constant());
39800 bool is_unsigned = is_unsigned_booltest_pred(opnd_array(3)->constant());
39801 BasicType src1_elem_bt = Matcher::vector_element_basic_type(this, opnd_array(1));
39802
39803 // Comparison i
39804 switch (src1_elem_bt) {
39805 case T_BYTE: {
39806 ___masm. evpcmpb(opnd_array(0)->as_KRegister(ra_,this)/* dst */, k0, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, cmp, !is_unsigned, vlen_enc);
39807 break;
39808 }
39809 case T_SHORT: {
39810 ___masm. evpcmpw(opnd_array(0)->as_KRegister(ra_,this)/* dst */, k0, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, cmp, !is_unsigned, vlen_enc);
39811 break;
39812 }
39813 case T_INT: {
39814 ___masm. evpcmpd(opnd_array(0)->as_KRegister(ra_,this)/* dst */, k0, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, cmp, !is_unsigned, vlen_enc);
39815 break;
39816 }
39817 case T_LONG: {
39818 ___masm. evpcmpq(opnd_array(0)->as_KRegister(ra_,this)/* dst */, k0, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, cmp, !is_unsigned, vlen_enc);
39819 break;
39820 }
39821 default: assert(false, "%s", type2name(src1_elem_bt))do { if (!(false)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
7425, "assert(" "false" ") failed", "%s", type2name(src1_elem_bt
)); ::breakpoint(); } } while (0);
39822 }
39823
39824#line 39824 "ad_x86.cpp"
39825 }
39826}
39827
39828void extractINode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39829 cbuf.set_insts_mark();
39830 // Start at oper_input_base() and count operands
39831 unsigned idx0 = 1;
39832 unsigned idx1 = 1; // src
39833 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // idx
39834 {
39835 C2_MacroAssembler _masm(&cbuf);
39836
39837#line 7441 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
39838
39839 assert(opnd_array(2)->constant()< (int)Matcher::vector_length(this, opnd_array(1)), "out of bounds")do { if (!(opnd_array(2)->constant()< (int)Matcher::vector_length
(this, opnd_array(1)))) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
7442, "assert(" "opnd_array(2)->constant()< (int)Matcher::vector_length(this, opnd_array(1))"
") failed", "out of bounds"); ::breakpoint(); } } while (0);
39840
39841 BasicType elem_bt = Matcher::vector_element_basic_type(this, opnd_array(1));
39842 ___masm. get_elem(elem_bt, opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->constant());
39843
39844#line 39844 "ad_x86.cpp"
39845 }
39846}
39847
39848void extractI_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39849 cbuf.set_insts_mark();
39850 // Start at oper_input_base() and count operands
39851 unsigned idx0 = 1;
39852 unsigned idx1 = 1; // src
39853 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // idx
39854 {
39855 C2_MacroAssembler _masm(&cbuf);
39856
39857#line 7441 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
39858
39859 assert(opnd_array(2)->constant()< (int)Matcher::vector_length(this, opnd_array(1)), "out of bounds")do { if (!(opnd_array(2)->constant()< (int)Matcher::vector_length
(this, opnd_array(1)))) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
7442, "assert(" "opnd_array(2)->constant()< (int)Matcher::vector_length(this, opnd_array(1))"
") failed", "out of bounds"); ::breakpoint(); } } while (0);
39860
39861 BasicType elem_bt = Matcher::vector_element_basic_type(this, opnd_array(1));
39862 ___masm. get_elem(elem_bt, opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->constant());
39863
39864#line 39864 "ad_x86.cpp"
39865 }
39866}
39867
39868void extractI_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39869 cbuf.set_insts_mark();
39870 // Start at oper_input_base() and count operands
39871 unsigned idx0 = 1;
39872 unsigned idx1 = 1; // src
39873 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // idx
39874 {
39875 C2_MacroAssembler _masm(&cbuf);
39876
39877#line 7441 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
39878
39879 assert(opnd_array(2)->constant()< (int)Matcher::vector_length(this, opnd_array(1)), "out of bounds")do { if (!(opnd_array(2)->constant()< (int)Matcher::vector_length
(this, opnd_array(1)))) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
7442, "assert(" "opnd_array(2)->constant()< (int)Matcher::vector_length(this, opnd_array(1))"
") failed", "out of bounds"); ::breakpoint(); } } while (0);
39880
39881 BasicType elem_bt = Matcher::vector_element_basic_type(this, opnd_array(1));
39882 ___masm. get_elem(elem_bt, opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->constant());
39883
39884#line 39884 "ad_x86.cpp"
39885 }
39886}
39887
39888void vextractINode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39889 cbuf.set_insts_mark();
39890 // Start at oper_input_base() and count operands
39891 unsigned idx0 = 1;
39892 unsigned idx1 = 1; // src
39893 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // idx
39894 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp
39895 {
39896 C2_MacroAssembler _masm(&cbuf);
39897
39898#line 7460 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
39899
39900 assert(opnd_array(2)->constant()< (int)Matcher::vector_length(this, opnd_array(1)), "out of bounds")do { if (!(opnd_array(2)->constant()< (int)Matcher::vector_length
(this, opnd_array(1)))) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
7461, "assert(" "opnd_array(2)->constant()< (int)Matcher::vector_length(this, opnd_array(1))"
") failed", "out of bounds"); ::breakpoint(); } } while (0);
39901
39902 BasicType elem_bt = Matcher::vector_element_basic_type(this, opnd_array(1));
39903 XMMRegister lane_xmm = ___masm. get_lane(elem_bt, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->constant());
39904 ___masm. get_elem(elem_bt, opnd_array(0)->as_Register(ra_,this)/* dst */, lane_xmm, opnd_array(2)->constant());
39905
39906#line 39906 "ad_x86.cpp"
39907 }
39908}
39909
39910void vextractI_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39911 cbuf.set_insts_mark();
39912 // Start at oper_input_base() and count operands
39913 unsigned idx0 = 1;
39914 unsigned idx1 = 1; // src
39915 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // idx
39916 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp
39917 {
39918 C2_MacroAssembler _masm(&cbuf);
39919
39920#line 7460 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
39921
39922 assert(opnd_array(2)->constant()< (int)Matcher::vector_length(this, opnd_array(1)), "out of bounds")do { if (!(opnd_array(2)->constant()< (int)Matcher::vector_length
(this, opnd_array(1)))) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
7461, "assert(" "opnd_array(2)->constant()< (int)Matcher::vector_length(this, opnd_array(1))"
") failed", "out of bounds"); ::breakpoint(); } } while (0);
39923
39924 BasicType elem_bt = Matcher::vector_element_basic_type(this, opnd_array(1));
39925 XMMRegister lane_xmm = ___masm. get_lane(elem_bt, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->constant());
39926 ___masm. get_elem(elem_bt, opnd_array(0)->as_Register(ra_,this)/* dst */, lane_xmm, opnd_array(2)->constant());
39927
39928#line 39928 "ad_x86.cpp"
39929 }
39930}
39931
39932void vextractI_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39933 cbuf.set_insts_mark();
39934 // Start at oper_input_base() and count operands
39935 unsigned idx0 = 1;
39936 unsigned idx1 = 1; // src
39937 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // idx
39938 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp
39939 {
39940 C2_MacroAssembler _masm(&cbuf);
39941
39942#line 7460 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
39943
39944 assert(opnd_array(2)->constant()< (int)Matcher::vector_length(this, opnd_array(1)), "out of bounds")do { if (!(opnd_array(2)->constant()< (int)Matcher::vector_length
(this, opnd_array(1)))) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
7461, "assert(" "opnd_array(2)->constant()< (int)Matcher::vector_length(this, opnd_array(1))"
") failed", "out of bounds"); ::breakpoint(); } } while (0);
39945
39946 BasicType elem_bt = Matcher::vector_element_basic_type(this, opnd_array(1));
39947 XMMRegister lane_xmm = ___masm. get_lane(elem_bt, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->constant());
39948 ___masm. get_elem(elem_bt, opnd_array(0)->as_Register(ra_,this)/* dst */, lane_xmm, opnd_array(2)->constant());
39949
39950#line 39950 "ad_x86.cpp"
39951 }
39952}
39953
39954void extractLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39955 cbuf.set_insts_mark();
39956 // Start at oper_input_base() and count operands
39957 unsigned idx0 = 1;
39958 unsigned idx1 = 1; // src
39959 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // idx
39960 {
39961 C2_MacroAssembler _masm(&cbuf);
39962
39963#line 7475 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
39964
39965 assert(UseSSE >= 4, "required")do { if (!(UseSSE >= 4)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
7476, "assert(" "UseSSE >= 4" ") failed", "required"); ::
breakpoint(); } } while (0);
39966 assert(opnd_array(2)->constant()< (int)Matcher::vector_length(this, opnd_array(1)), "out of bounds")do { if (!(opnd_array(2)->constant()< (int)Matcher::vector_length
(this, opnd_array(1)))) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
7477, "assert(" "opnd_array(2)->constant()< (int)Matcher::vector_length(this, opnd_array(1))"
") failed", "out of bounds"); ::breakpoint(); } } while (0);
39967
39968 ___masm. get_elem(T_LONG, opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->constant());
39969
39970#line 39970 "ad_x86.cpp"
39971 }
39972}
39973
39974void vextractLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39975 cbuf.set_insts_mark();
39976 // Start at oper_input_base() and count operands
39977 unsigned idx0 = 1;
39978 unsigned idx1 = 1; // src
39979 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // idx
39980 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp
39981 {
39982 C2_MacroAssembler _masm(&cbuf);
39983
39984#line 7490 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
39985
39986 assert(opnd_array(2)->constant()< (int)Matcher::vector_length(this, opnd_array(1)), "out of bounds")do { if (!(opnd_array(2)->constant()< (int)Matcher::vector_length
(this, opnd_array(1)))) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
7491, "assert(" "opnd_array(2)->constant()< (int)Matcher::vector_length(this, opnd_array(1))"
") failed", "out of bounds"); ::breakpoint(); } } while (0);
39987
39988 XMMRegister lane_reg = ___masm. get_lane(T_LONG, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->constant());
39989 ___masm. get_elem(T_LONG, opnd_array(0)->as_Register(ra_,this)/* dst */, lane_reg, opnd_array(2)->constant());
39990
39991#line 39991 "ad_x86.cpp"
39992 }
39993}
39994
39995void extractFNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
39996 cbuf.set_insts_mark();
39997 // Start at oper_input_base() and count operands
39998 unsigned idx0 = 1;
39999 unsigned idx1 = 1; // src
40000 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // idx
40001 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
40002 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
40003 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // vtmp
40004 {
40005 C2_MacroAssembler _masm(&cbuf);
40006
40007#line 7505 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
40008
40009 assert(opnd_array(2)->constant()< (int)Matcher::vector_length(this, opnd_array(1)), "out of bounds")do { if (!(opnd_array(2)->constant()< (int)Matcher::vector_length
(this, opnd_array(1)))) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
7506, "assert(" "opnd_array(2)->constant()< (int)Matcher::vector_length(this, opnd_array(1))"
") failed", "out of bounds"); ::breakpoint(); } } while (0);
40010
40011 ___masm. get_elem(T_FLOAT, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->constant(), opnd_array(4)->as_Register(ra_,this,idx4)/* tmp */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp */);
40012
40013#line 40013 "ad_x86.cpp"
40014 }
40015}
40016
40017void vextractFNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40018 cbuf.set_insts_mark();
40019 // Start at oper_input_base() and count operands
40020 unsigned idx0 = 1;
40021 unsigned idx1 = 1; // src
40022 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // idx
40023 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
40024 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp
40025 {
40026 C2_MacroAssembler _masm(&cbuf);
40027
40028#line 7519 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
40029
40030 assert(opnd_array(2)->constant()< (int)Matcher::vector_length(this, opnd_array(1)), "out of bounds")do { if (!(opnd_array(2)->constant()< (int)Matcher::vector_length
(this, opnd_array(1)))) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
7520, "assert(" "opnd_array(2)->constant()< (int)Matcher::vector_length(this, opnd_array(1))"
") failed", "out of bounds"); ::breakpoint(); } } while (0);
40031
40032 XMMRegister lane_reg = ___masm. get_lane(T_FLOAT, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->constant());
40033 ___masm. get_elem(T_FLOAT, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, lane_reg, opnd_array(2)->constant(), opnd_array(3)->as_Register(ra_,this,idx3)/* tmp */);
40034
40035#line 40035 "ad_x86.cpp"
40036 }
40037}
40038
40039void extractDNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40040 cbuf.set_insts_mark();
40041 // Start at oper_input_base() and count operands
40042 unsigned idx0 = 1;
40043 unsigned idx1 = 1; // src
40044 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // idx
40045 {
40046 C2_MacroAssembler _masm(&cbuf);
40047
40048#line 7532 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
40049
40050 assert(opnd_array(2)->constant()< (int)Matcher::vector_length(this, opnd_array(1)), "out of bounds")do { if (!(opnd_array(2)->constant()< (int)Matcher::vector_length
(this, opnd_array(1)))) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
7533, "assert(" "opnd_array(2)->constant()< (int)Matcher::vector_length(this, opnd_array(1))"
") failed", "out of bounds"); ::breakpoint(); } } while (0);
40051
40052 ___masm. get_elem(T_DOUBLE, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->constant());
40053
40054#line 40054 "ad_x86.cpp"
40055 }
40056}
40057
40058void vextractDNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40059 cbuf.set_insts_mark();
40060 // Start at oper_input_base() and count operands
40061 unsigned idx0 = 1;
40062 unsigned idx1 = 1; // src
40063 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // idx
40064 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp
40065 {
40066 C2_MacroAssembler _masm(&cbuf);
40067
40068#line 7546 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
40069
40070 assert(opnd_array(2)->constant()< (int)Matcher::vector_length(this, opnd_array(1)), "out of bounds")do { if (!(opnd_array(2)->constant()< (int)Matcher::vector_length
(this, opnd_array(1)))) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
7547, "assert(" "opnd_array(2)->constant()< (int)Matcher::vector_length(this, opnd_array(1))"
") failed", "out of bounds"); ::breakpoint(); } } while (0);
40071
40072 XMMRegister lane_reg = ___masm. get_lane(T_DOUBLE, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->constant());
40073 ___masm. get_elem(T_DOUBLE, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, lane_reg, opnd_array(2)->constant());
40074
40075#line 40075 "ad_x86.cpp"
40076 }
40077}
40078
40079void blendvpNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40080 cbuf.set_insts_mark();
40081 // Start at oper_input_base() and count operands
40082 unsigned idx0 = 1;
40083 unsigned idx1 = 1; // dst
40084 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
40085 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
40086 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
40087 {
40088 C2_MacroAssembler _masm(&cbuf);
40089
40090#line 7562 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
40091
40092 assert(UseSSE >= 4, "required")do { if (!(UseSSE >= 4)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
7563, "assert(" "UseSSE >= 4" ") failed", "required"); ::
breakpoint(); } } while (0);
40093
40094 if (opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* mask */!= opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */) {
40095 ___masm. movdqu(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* tmp */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* mask */);
40096 }
40097 ___masm. pblendvb(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */); // uses xmm0 as mask
40098
40099#line 40099 "ad_x86.cpp"
40100 }
40101}
40102
40103void vblendvpINode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40104 cbuf.set_insts_mark();
40105 // Start at oper_input_base() and count operands
40106 unsigned idx0 = 1;
40107 unsigned idx1 = 1; // src1
40108 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
40109 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
40110 {
40111 C2_MacroAssembler _masm(&cbuf);
40112
40113#line 7580 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
40114
40115 int vlen_enc = vector_length_encoding(this);
40116 ___masm. vpblendvb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* mask */, vlen_enc);
40117
40118#line 40118 "ad_x86.cpp"
40119 }
40120}
40121
40122void vblendvpFDNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40123 cbuf.set_insts_mark();
40124 // Start at oper_input_base() and count operands
40125 unsigned idx0 = 1;
40126 unsigned idx1 = 1; // src1
40127 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
40128 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
40129 {
40130 C2_MacroAssembler _masm(&cbuf);
40131
40132#line 7594 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
40133
40134 int vlen_enc = vector_length_encoding(this);
40135 ___masm. vblendvps(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* mask */, vlen_enc);
40136
40137#line 40137 "ad_x86.cpp"
40138 }
40139}
40140
40141void evblendvp64Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40142 cbuf.set_insts_mark();
40143 // Start at oper_input_base() and count operands
40144 unsigned idx0 = 1;
40145 unsigned idx1 = 1; // src1
40146 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
40147 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
40148 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // scratch
40149 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // ktmp
40150 {
40151 C2_MacroAssembler _masm(&cbuf);
40152
40153#line 7607 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
40154
40155 int vlen_enc = Assembler::AVX_512bit;
40156 BasicType elem_bt = Matcher::vector_element_basic_type(this);
40157 ___masm. evpcmp(elem_bt, opnd_array(5)->as_KRegister(ra_,this,idx5)/* ktmp */, k0, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* mask */, ExternalAddress(vector_all_bits_set()), Assembler::eq, vlen_enc, opnd_array(4)->as_Register(ra_,this,idx4)/* scratch */);
40158 ___masm. evpblend(elem_bt, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(5)->as_KRegister(ra_,this,idx5)/* ktmp */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, true, vlen_enc);
40159
40160#line 40160 "ad_x86.cpp"
40161 }
40162}
40163
40164void evblendvp64_maskedNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40165 cbuf.set_insts_mark();
40166 // Start at oper_input_base() and count operands
40167 unsigned idx0 = 1;
40168 unsigned idx1 = 1; // src1
40169 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
40170 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
40171 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // scratch
40172 {
40173 C2_MacroAssembler _masm(&cbuf);
40174
40175#line 7624 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
40176
40177 int vlen_enc = vector_length_encoding(this);
40178 BasicType elem_bt = Matcher::vector_element_basic_type(this);
40179 ___masm. evpblend(elem_bt, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, true, vlen_enc);
40180
40181#line 40181 "ad_x86.cpp"
40182 }
40183}
40184
40185void vabsB_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40186 cbuf.set_insts_mark();
40187 // Start at oper_input_base() and count operands
40188 unsigned idx0 = 1;
40189 unsigned idx1 = 1; // src
40190 {
40191 C2_MacroAssembler _masm(&cbuf);
40192
40193#line 7638 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
40194
40195 uint vlen = Matcher::vector_length(this);
40196 if (vlen <= 16) {
40197 ___masm. pabsb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
40198 } else {
40199 int vlen_enc = vector_length_encoding(this);
40200 ___masm. vpabsb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vlen_enc);
40201 }
40202
40203#line 40203 "ad_x86.cpp"
40204 }
40205}
40206
40207void vabsS_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40208 cbuf.set_insts_mark();
40209 // Start at oper_input_base() and count operands
40210 unsigned idx0 = 1;
40211 unsigned idx1 = 1; // src
40212 {
40213 C2_MacroAssembler _masm(&cbuf);
40214
40215#line 7654 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
40216
40217 uint vlen = Matcher::vector_length(this);
40218 if (vlen <= 8) {
40219 ___masm. pabsw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
40220 } else {
40221 int vlen_enc = vector_length_encoding(this);
40222 ___masm. vpabsw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vlen_enc);
40223 }
40224
40225#line 40225 "ad_x86.cpp"
40226 }
40227}
40228
40229void vabsI_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40230 cbuf.set_insts_mark();
40231 // Start at oper_input_base() and count operands
40232 unsigned idx0 = 1;
40233 unsigned idx1 = 1; // src
40234 {
40235 C2_MacroAssembler _masm(&cbuf);
40236
40237#line 7670 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
40238
40239 uint vlen = Matcher::vector_length(this);
40240 if (vlen <= 4) {
40241 ___masm. pabsd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
40242 } else {
40243 int vlen_enc = vector_length_encoding(this);
40244 ___masm. vpabsd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vlen_enc);
40245 }
40246
40247#line 40247 "ad_x86.cpp"
40248 }
40249}
40250
40251void vabsL_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40252 cbuf.set_insts_mark();
40253 // Start at oper_input_base() and count operands
40254 unsigned idx0 = 1;
40255 unsigned idx1 = 1; // src
40256 {
40257 C2_MacroAssembler _masm(&cbuf);
40258
40259#line 7686 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
40260
40261 assert(UseAVX > 2, "required")do { if (!(UseAVX > 2)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
7687, "assert(" "UseAVX > 2" ") failed", "required"); ::breakpoint
(); } } while (0);
40262 int vlen_enc = vector_length_encoding(this);
40263 if (!VM_Version::supports_avx512vl()) {
40264 vlen_enc = Assembler::AVX_512bit;
40265 }
40266 ___masm. evpabsq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vlen_enc);
40267
40268#line 40268 "ad_x86.cpp"
40269 }
40270}
40271
40272void vabsnegFNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40273 cbuf.set_insts_mark();
40274 // Start at oper_input_base() and count operands
40275 unsigned idx0 = 1;
40276 unsigned idx1 = 1; // src
40277 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // scratch
40278 {
40279 C2_MacroAssembler _masm(&cbuf);
40280
40281#line 7706 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
40282
40283 int opcode = this->ideal_Opcode();
40284 int vlen = Matcher::vector_length(this);
40285 if (vlen == 2) {
40286 ___masm. vabsnegf(opcode, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_Register(ra_,this,idx2)/* scratch */);
40287 } else {
40288 assert(vlen == 8 || vlen == 16, "required")do { if (!(vlen == 8 || vlen == 16)) { (*g_assert_poison) = 'X'
;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 7712, "assert(" "vlen == 8 || vlen == 16" ") failed", "required"
); ::breakpoint(); } } while (0);
40289 int vlen_enc = vector_length_encoding(this);
40290 ___masm. vabsnegf(opcode, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vlen_enc, opnd_array(2)->as_Register(ra_,this,idx2)/* scratch */);
40291 }
40292
40293#line 40293 "ad_x86.cpp"
40294 }
40295}
40296
40297void vabsnegF_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40298 cbuf.set_insts_mark();
40299 // Start at oper_input_base() and count operands
40300 unsigned idx0 = 1;
40301 unsigned idx1 = 1; // src
40302 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // scratch
40303 {
40304 C2_MacroAssembler _masm(&cbuf);
40305
40306#line 7706 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
40307
40308 int opcode = this->ideal_Opcode();
40309 int vlen = Matcher::vector_length(this);
40310 if (vlen == 2) {
40311 ___masm. vabsnegf(opcode, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_Register(ra_,this,idx2)/* scratch */);
40312 } else {
40313 assert(vlen == 8 || vlen == 16, "required")do { if (!(vlen == 8 || vlen == 16)) { (*g_assert_poison) = 'X'
;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 7712, "assert(" "vlen == 8 || vlen == 16" ") failed", "required"
); ::breakpoint(); } } while (0);
40314 int vlen_enc = vector_length_encoding(this);
40315 ___masm. vabsnegf(opcode, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vlen_enc, opnd_array(2)->as_Register(ra_,this,idx2)/* scratch */);
40316 }
40317
40318#line 40318 "ad_x86.cpp"
40319 }
40320}
40321
40322void vabsneg4FNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40323 cbuf.set_insts_mark();
40324 // Start at oper_input_base() and count operands
40325 unsigned idx0 = 1;
40326 unsigned idx1 = 1; // dst
40327 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // scratch
40328 {
40329 C2_MacroAssembler _masm(&cbuf);
40330
40331#line 7727 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
40332
40333 int opcode = this->ideal_Opcode();
40334 ___masm. vabsnegf(opcode, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_Register(ra_,this,idx2)/* scratch */);
40335
40336#line 40336 "ad_x86.cpp"
40337 }
40338}
40339
40340void vabsneg4F_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40341 cbuf.set_insts_mark();
40342 // Start at oper_input_base() and count operands
40343 unsigned idx0 = 1;
40344 unsigned idx1 = 1; // dst
40345 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // scratch
40346 {
40347 C2_MacroAssembler _masm(&cbuf);
40348
40349#line 7727 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
40350
40351 int opcode = this->ideal_Opcode();
40352 ___masm. vabsnegf(opcode, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_Register(ra_,this,idx2)/* scratch */);
40353
40354#line 40354 "ad_x86.cpp"
40355 }
40356}
40357
40358void vabsnegDNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40359 cbuf.set_insts_mark();
40360 // Start at oper_input_base() and count operands
40361 unsigned idx0 = 1;
40362 unsigned idx1 = 1; // src
40363 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // scratch
40364 {
40365 C2_MacroAssembler _masm(&cbuf);
40366
40367#line 7739 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
40368
40369 int opcode = this->ideal_Opcode();
40370 uint vlen = Matcher::vector_length(this);
40371 if (vlen == 2) {
40372 assert(UseSSE >= 2, "required")do { if (!(UseSSE >= 2)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
7743, "assert(" "UseSSE >= 2" ") failed", "required"); ::
breakpoint(); } } while (0);
40373 ___masm. vabsnegd(opcode, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_Register(ra_,this,idx2)/* scratch */);
40374 } else {
40375 int vlen_enc = vector_length_encoding(this);
40376 ___masm. vabsnegd(opcode, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vlen_enc, opnd_array(2)->as_Register(ra_,this,idx2)/* scratch */);
40377 }
40378
40379#line 40379 "ad_x86.cpp"
40380 }
40381}
40382
40383void vabsnegD_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40384 cbuf.set_insts_mark();
40385 // Start at oper_input_base() and count operands
40386 unsigned idx0 = 1;
40387 unsigned idx1 = 1; // src
40388 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // scratch
40389 {
40390 C2_MacroAssembler _masm(&cbuf);
40391
40392#line 7739 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
40393
40394 int opcode = this->ideal_Opcode();
40395 uint vlen = Matcher::vector_length(this);
40396 if (vlen == 2) {
40397 assert(UseSSE >= 2, "required")do { if (!(UseSSE >= 2)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
7743, "assert(" "UseSSE >= 2" ") failed", "required"); ::
breakpoint(); } } while (0);
40398 ___masm. vabsnegd(opcode, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_Register(ra_,this,idx2)/* scratch */);
40399 } else {
40400 int vlen_enc = vector_length_encoding(this);
40401 ___masm. vabsnegd(opcode, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vlen_enc, opnd_array(2)->as_Register(ra_,this,idx2)/* scratch */);
40402 }
40403
40404#line 40404 "ad_x86.cpp"
40405 }
40406}
40407
40408void vptest_alltrue_lt16Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40409 cbuf.set_insts_mark();
40410 // Start at oper_input_base() and count operands
40411 unsigned idx0 = 1;
40412 unsigned idx1 = 1; // src1
40413 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
40414 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp1
40415 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp2
40416 {
40417 C2_MacroAssembler _masm(&cbuf);
40418
40419#line 7764 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
40420
40421 int vlen = Matcher::vector_length_in_bytes(this, opnd_array(1));
40422 ___masm. vectortest(BoolTest::overflow, vlen, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp2 */);
40423 ___masm. setb(Assembler::carrySet, opnd_array(0)->as_Register(ra_,this)/* dst */);
40424 ___masm. movzbl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(0)->as_Register(ra_,this)/* dst */);
40425
40426#line 40426 "ad_x86.cpp"
40427 }
40428}
40429
40430void vptest_alltrue_ge16Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40431 cbuf.set_insts_mark();
40432 // Start at oper_input_base() and count operands
40433 unsigned idx0 = 1;
40434 unsigned idx1 = 1; // src1
40435 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
40436 {
40437 C2_MacroAssembler _masm(&cbuf);
40438
40439#line 7781 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
40440
40441 int vlen = Matcher::vector_length_in_bytes(this, opnd_array(1));
40442 ___masm. vectortest(BoolTest::overflow, vlen, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, xnoreg, xnoreg, knoreg);
40443 ___masm. setb(Assembler::carrySet, opnd_array(0)->as_Register(ra_,this)/* dst */);
40444 ___masm. movzbl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(0)->as_Register(ra_,this)/* dst */);
40445
40446#line 40446 "ad_x86.cpp"
40447 }
40448}
40449
40450void vptest_alltrue_lt8_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40451 cbuf.set_insts_mark();
40452 // Start at oper_input_base() and count operands
40453 unsigned idx0 = 1;
40454 unsigned idx1 = 1; // src1
40455 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
40456 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // kscratch
40457 {
40458 C2_MacroAssembler _masm(&cbuf);
40459
40460#line 7798 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
40461
40462 const MachNode* mask1 = static_cast<const MachNode*>(this->in(this->operand_index(opnd_array(1))));
40463 const MachNode* mask2 = static_cast<const MachNode*>(this->in(this->operand_index(opnd_array(2))));
40464 assert(0 == Type::cmp(mask1->bottom_type(), mask2->bottom_type()), "")do { if (!(0 == Type::cmp(mask1->bottom_type(), mask2->
bottom_type()))) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
7801, "assert(" "0 == Type::cmp(mask1->bottom_type(), mask2->bottom_type())"
") failed", ""); ::breakpoint(); } } while (0);
40465 uint masklen = Matcher::vector_length(this, opnd_array(1));
40466 ___masm. alltrue(opnd_array(0)->as_Register(ra_,this)/* dst */, masklen, opnd_array(1)->as_KRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_KRegister(ra_,this,idx2)/* src2 */, opnd_array(3)->as_KRegister(ra_,this,idx3)/* kscratch */);
40467
40468#line 40468 "ad_x86.cpp"
40469 }
40470}
40471
40472void vptest_alltrue_ge8_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40473 cbuf.set_insts_mark();
40474 // Start at oper_input_base() and count operands
40475 unsigned idx0 = 1;
40476 unsigned idx1 = 1; // src1
40477 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
40478 {
40479 C2_MacroAssembler _masm(&cbuf);
40480
40481#line 7817 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
40482
40483 const MachNode* mask1 = static_cast<const MachNode*>(this->in(this->operand_index(opnd_array(1))));
40484 const MachNode* mask2 = static_cast<const MachNode*>(this->in(this->operand_index(opnd_array(2))));
40485 assert(0 == Type::cmp(mask1->bottom_type(), mask2->bottom_type()), "")do { if (!(0 == Type::cmp(mask1->bottom_type(), mask2->
bottom_type()))) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
7820, "assert(" "0 == Type::cmp(mask1->bottom_type(), mask2->bottom_type())"
") failed", ""); ::breakpoint(); } } while (0);
40486 uint masklen = Matcher::vector_length(this, opnd_array(1));
40487 ___masm. alltrue(opnd_array(0)->as_Register(ra_,this)/* dst */, masklen, opnd_array(1)->as_KRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_KRegister(ra_,this,idx2)/* src2 */, knoreg);
40488
40489#line 40489 "ad_x86.cpp"
40490 }
40491}
40492
40493void vptest_anytrue_lt16Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40494 cbuf.set_insts_mark();
40495 // Start at oper_input_base() and count operands
40496 unsigned idx0 = 1;
40497 unsigned idx1 = 1; // src1
40498 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
40499 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp
40500 {
40501 C2_MacroAssembler _masm(&cbuf);
40502
40503#line 7836 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
40504
40505 int vlen = Matcher::vector_length_in_bytes(this, opnd_array(1));
40506 ___masm. vectortest(BoolTest::ne, vlen, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp */);
40507 ___masm. setb(Assembler::notZero, opnd_array(0)->as_Register(ra_,this)/* dst */);
40508 ___masm. movzbl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(0)->as_Register(ra_,this)/* dst */);
40509
40510#line 40510 "ad_x86.cpp"
40511 }
40512}
40513
40514void vptest_anytrue_ge16Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40515 cbuf.set_insts_mark();
40516 // Start at oper_input_base() and count operands
40517 unsigned idx0 = 1;
40518 unsigned idx1 = 1; // src1
40519 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
40520 {
40521 C2_MacroAssembler _masm(&cbuf);
40522
40523#line 7853 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
40524
40525 int vlen = Matcher::vector_length_in_bytes(this, opnd_array(1));
40526 ___masm. vectortest(BoolTest::ne, vlen, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, xnoreg, xnoreg, knoreg);
40527 ___masm. setb(Assembler::notZero, opnd_array(0)->as_Register(ra_,this)/* dst */);
40528 ___masm. movzbl(opnd_array(0)->as_Register(ra_,this)/* dst */, opnd_array(0)->as_Register(ra_,this)/* dst */);
40529
40530#line 40530 "ad_x86.cpp"
40531 }
40532}
40533
40534void vptest_anytrue_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40535 cbuf.set_insts_mark();
40536 // Start at oper_input_base() and count operands
40537 unsigned idx0 = 1;
40538 unsigned idx1 = 1; // src1
40539 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
40540 {
40541 C2_MacroAssembler _masm(&cbuf);
40542
40543#line 7868 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
40544
40545 const MachNode* mask1 = static_cast<const MachNode*>(this->in(this->operand_index(opnd_array(1))));
40546 const MachNode* mask2 = static_cast<const MachNode*>(this->in(this->operand_index(opnd_array(2))));
40547 assert(0 == Type::cmp(mask1->bottom_type(), mask2->bottom_type()), "")do { if (!(0 == Type::cmp(mask1->bottom_type(), mask2->
bottom_type()))) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
7871, "assert(" "0 == Type::cmp(mask1->bottom_type(), mask2->bottom_type())"
") failed", ""); ::breakpoint(); } } while (0);
40548 uint masklen = Matcher::vector_length(this, opnd_array(1));
40549 ___masm. anytrue(opnd_array(0)->as_Register(ra_,this)/* dst */, masklen, opnd_array(1)->as_KRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_KRegister(ra_,this,idx2)/* src2 */);
40550
40551#line 40551 "ad_x86.cpp"
40552 }
40553}
40554
40555void cmpvptest_anytrue_lt16Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40556 cbuf.set_insts_mark();
40557 // Start at oper_input_base() and count operands
40558 unsigned idx0 = 1;
40559 unsigned idx1 = 1; // src1
40560 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
40561 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // zero
40562 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp
40563 {
40564 C2_MacroAssembler _masm(&cbuf);
40565
40566#line 7886 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
40567
40568 int vlen = Matcher::vector_length_in_bytes(this, opnd_array(1));
40569 ___masm. vectortest(BoolTest::ne, vlen, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp */);
40570
40571#line 40571 "ad_x86.cpp"
40572 }
40573}
40574
40575void cmpvptest_anytrue_ge16Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40576 cbuf.set_insts_mark();
40577 // Start at oper_input_base() and count operands
40578 unsigned idx0 = 1;
40579 unsigned idx1 = 1; // src1
40580 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
40581 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // zero
40582 {
40583 C2_MacroAssembler _masm(&cbuf);
40584
40585#line 7900 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
40586
40587 int vlen = Matcher::vector_length_in_bytes(this, opnd_array(1));
40588 ___masm. vectortest(BoolTest::ne, vlen, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, xnoreg, xnoreg, knoreg);
40589
40590#line 40590 "ad_x86.cpp"
40591 }
40592}
40593
40594void cmpvptest_anytrue_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40595 cbuf.set_insts_mark();
40596 // Start at oper_input_base() and count operands
40597 unsigned idx0 = 1;
40598 unsigned idx1 = 1; // src1
40599 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
40600 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // zero
40601 {
40602 C2_MacroAssembler _masm(&cbuf);
40603
40604#line 7912 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
40605
40606 uint masklen = Matcher::vector_length(this, opnd_array(1));
40607 const MachNode* mask1 = static_cast<const MachNode*>(this->in(this->operand_index(opnd_array(1))));
40608 const MachNode* mask2 = static_cast<const MachNode*>(this->in(this->operand_index(opnd_array(2))));
40609 assert(0 == Type::cmp(mask1->bottom_type(), mask2->bottom_type()), "")do { if (!(0 == Type::cmp(mask1->bottom_type(), mask2->
bottom_type()))) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
7916, "assert(" "0 == Type::cmp(mask1->bottom_type(), mask2->bottom_type())"
") failed", ""); ::breakpoint(); } } while (0);
40610 masklen = masklen < 8 ? 8 : masklen;
40611 ___masm. ktest(masklen, opnd_array(1)->as_KRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_KRegister(ra_,this,idx2)/* src2 */);
40612
40613#line 40613 "ad_x86.cpp"
40614 }
40615}
40616
40617void loadMaskNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40618 cbuf.set_insts_mark();
40619 // Start at oper_input_base() and count operands
40620 unsigned idx0 = 1;
40621 unsigned idx1 = 1; // src
40622 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
40623 {
40624 C2_MacroAssembler _masm(&cbuf);
40625
40626#line 7931 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
40627
40628 int vlen_in_bytes = Matcher::vector_length_in_bytes(this);
40629 BasicType elem_bt = Matcher::vector_element_basic_type(this);
40630 ___masm. load_vector_mask(opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vlen_in_bytes, elem_bt, true);
40631
40632#line 40632 "ad_x86.cpp"
40633 }
40634}
40635
40636void loadMask64Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40637 cbuf.set_insts_mark();
40638 // Start at oper_input_base() and count operands
40639 unsigned idx0 = 1;
40640 unsigned idx1 = 1; // src
40641 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // xtmp
40642 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
40643 {
40644 C2_MacroAssembler _masm(&cbuf);
40645
40646#line 7944 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
40647
40648 ___masm. load_vector_mask(opnd_array(0)->as_KRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* xtmp */,
40649 opnd_array(3)->as_Register(ra_,this,idx3)/* tmp */, true, Assembler::AVX_512bit);
40650
40651#line 40651 "ad_x86.cpp"
40652 }
40653}
40654
40655void loadMask_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40656 cbuf.set_insts_mark();
40657 // Start at oper_input_base() and count operands
40658 unsigned idx0 = 1;
40659 unsigned idx1 = 1; // src
40660 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // xtmp
40661 {
40662 C2_MacroAssembler _masm(&cbuf);
40663
40664#line 7956 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
40665
40666 int vlen_enc = vector_length_encoding(in(1));
40667 ___masm. load_vector_mask(opnd_array(0)->as_KRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* xtmp */,
40668 noreg, false, vlen_enc);
40669
40670#line 40670 "ad_x86.cpp"
40671 }
40672}
40673
40674void vstoreMask1BNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40675 cbuf.set_insts_mark();
40676 // Start at oper_input_base() and count operands
40677 unsigned idx0 = 1;
40678 unsigned idx1 = 1; // src
40679 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // size
40680 {
40681 C2_MacroAssembler _masm(&cbuf);
40682
40683#line 7970 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
40684
40685 int vlen = Matcher::vector_length(this);
40686 if (vlen <= 16 && UseAVX <= 2) {
40687 assert(UseSSE >= 3, "required")do { if (!(UseSSE >= 3)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
7973, "assert(" "UseSSE >= 3" ") failed", "required"); ::
breakpoint(); } } while (0);
40688 ___masm. pabsb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
40689 } else {
40690 assert(UseAVX > 0, "required")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
7976, "assert(" "UseAVX > 0" ") failed", "required"); ::breakpoint
(); } } while (0);
40691 int src_vlen_enc = vector_length_encoding(this, opnd_array(1));
40692 ___masm. vpabsb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, src_vlen_enc);
40693 }
40694
40695#line 40695 "ad_x86.cpp"
40696 }
40697}
40698
40699void vstoreMask2BNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40700 cbuf.set_insts_mark();
40701 // Start at oper_input_base() and count operands
40702 unsigned idx0 = 1;
40703 unsigned idx1 = 1; // src
40704 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // size
40705 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
40706 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // xtmp
40707 {
40708 C2_MacroAssembler _masm(&cbuf);
40709
40710#line 7989 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
40711
40712 int vlen_enc = Assembler::AVX_128bit;
40713 int vlen = Matcher::vector_length(this);
40714 if (vlen <= 8) {
40715 assert(UseSSE >= 3, "required")do { if (!(UseSSE >= 3)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
7993, "assert(" "UseSSE >= 3" ") failed", "required"); ::
breakpoint(); } } while (0);
40716 ___masm. pxor(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* xtmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* xtmp */);
40717 ___masm. pabsw(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
40718 ___masm. packuswb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* xtmp */);
40719 } else {
40720 assert(UseAVX > 0, "required")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
7998, "assert(" "UseAVX > 0" ") failed", "required"); ::breakpoint
(); } } while (0);
40721 ___masm. vextracti128(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, 0x1);
40722 ___masm. vpacksswb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, vlen_enc);
40723 ___masm. vpabsb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, vlen_enc);
40724 }
40725
40726#line 40726 "ad_x86.cpp"
40727 }
40728}
40729
40730void vstoreMask4BNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40731 cbuf.set_insts_mark();
40732 // Start at oper_input_base() and count operands
40733 unsigned idx0 = 1;
40734 unsigned idx1 = 1; // src
40735 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // size
40736 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
40737 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // xtmp
40738 {
40739 C2_MacroAssembler _masm(&cbuf);
40740
40741#line 8012 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
40742
40743 int vlen_enc = Assembler::AVX_128bit;
40744 int vlen = Matcher::vector_length(this);
40745 if (vlen <= 4) {
40746 assert(UseSSE >= 3, "required")do { if (!(UseSSE >= 3)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
8016, "assert(" "UseSSE >= 3" ") failed", "required"); ::
breakpoint(); } } while (0);
40747 ___masm. pxor(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* xtmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* xtmp */);
40748 ___masm. pabsd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
40749 ___masm. packusdw(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* xtmp */);
40750 ___masm. packuswb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* xtmp */);
40751 } else {
40752 assert(UseAVX > 0, "required")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
8022, "assert(" "UseAVX > 0" ") failed", "required"); ::breakpoint
(); } } while (0);
40753 ___masm. vpxor(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* xtmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* xtmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* xtmp */, vlen_enc);
40754 ___masm. vextracti128(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, 0x1);
40755 ___masm. vpackssdw(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, vlen_enc);
40756 ___masm. vpacksswb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* xtmp */, vlen_enc);
40757 ___masm. vpabsb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, vlen_enc);
40758 }
40759
40760#line 40760 "ad_x86.cpp"
40761 }
40762}
40763
40764void storeMask8BNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40765 cbuf.set_insts_mark();
40766 // Start at oper_input_base() and count operands
40767 unsigned idx0 = 1;
40768 unsigned idx1 = 1; // src
40769 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // size
40770 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
40771 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // xtmp
40772 {
40773 C2_MacroAssembler _masm(&cbuf);
40774
40775#line 8038 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
40776
40777 assert(UseSSE >= 3, "required")do { if (!(UseSSE >= 3)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
8039, "assert(" "UseSSE >= 3" ") failed", "required"); ::
breakpoint(); } } while (0);
40778 ___masm. pxor(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* xtmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* xtmp */);
40779 ___masm. pshufd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, 0x8);
40780 ___masm. pabsd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */);
40781 ___masm. packusdw(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* xtmp */);
40782 ___masm. packuswb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* xtmp */);
40783
40784#line 40784 "ad_x86.cpp"
40785 }
40786}
40787
40788void storeMask8B_avxNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40789 cbuf.set_insts_mark();
40790 // Start at oper_input_base() and count operands
40791 unsigned idx0 = 1;
40792 unsigned idx1 = 1; // src
40793 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // size
40794 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
40795 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp
40796 {
40797 C2_MacroAssembler _masm(&cbuf);
40798
40799#line 8054 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
40800
40801 int vlen_enc = Assembler::AVX_128bit;
40802 ___masm. vpshufps(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, 0x88, Assembler::AVX_256bit);
40803 ___masm. vextracti128(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, 0x1);
40804 ___masm. vblendps(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp */, 0xC, vlen_enc);
40805 ___masm. vpxor(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp */, vlen_enc);
40806 ___masm. vpackssdw(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp */, vlen_enc);
40807 ___masm. vpacksswb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp */, vlen_enc);
40808 ___masm. vpabsb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, vlen_enc);
40809
40810#line 40810 "ad_x86.cpp"
40811 }
40812}
40813
40814void vstoreMask4B_evex_novectmaskNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40815 cbuf.set_insts_mark();
40816 // Start at oper_input_base() and count operands
40817 unsigned idx0 = 1;
40818 unsigned idx1 = 1; // src
40819 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // size
40820 {
40821 C2_MacroAssembler _masm(&cbuf);
40822
40823#line 8071 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
40824
40825 int src_vlen_enc = vector_length_encoding(this, opnd_array(1));
40826 int dst_vlen_enc = vector_length_encoding(this);
40827 if (!VM_Version::supports_avx512vl()) {
40828 src_vlen_enc = Assembler::AVX_512bit;
40829 }
40830 ___masm. evpmovdb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, src_vlen_enc);
40831 ___masm. vpabsb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, dst_vlen_enc);
40832
40833#line 40833 "ad_x86.cpp"
40834 }
40835}
40836
40837void vstoreMask8B_evex_novectmaskNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40838 cbuf.set_insts_mark();
40839 // Start at oper_input_base() and count operands
40840 unsigned idx0 = 1;
40841 unsigned idx1 = 1; // src
40842 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // size
40843 {
40844 C2_MacroAssembler _masm(&cbuf);
40845
40846#line 8087 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
40847
40848 int src_vlen_enc = vector_length_encoding(this, opnd_array(1));
40849 int dst_vlen_enc = vector_length_encoding(this);
40850 if (!VM_Version::supports_avx512vl()) {
40851 src_vlen_enc = Assembler::AVX_512bit;
40852 }
40853 ___masm. evpmovqb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, src_vlen_enc);
40854 ___masm. vpabsb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, dst_vlen_enc);
40855
40856#line 40856 "ad_x86.cpp"
40857 }
40858}
40859
40860void vstoreMask_evex_vectmaskNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40861 cbuf.set_insts_mark();
40862 // Start at oper_input_base() and count operands
40863 unsigned idx0 = 1;
40864 unsigned idx1 = 1; // mask
40865 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // size
40866 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
40867 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
40868 {
40869 C2_MacroAssembler _masm(&cbuf);
40870
40871#line 8104 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
40872
40873 assert(Matcher::vector_length_in_bytes(this, opnd_array(1)) == 64, "")do { if (!(Matcher::vector_length_in_bytes(this, opnd_array(1
)) == 64)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 8105, "assert(" "Matcher::vector_length_in_bytes(this, opnd_array(1)) == 64"
") failed", ""); ::breakpoint(); } } while (0);
40874 ___masm. evmovdqul(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_KRegister(ra_,this,idx1)/* mask */, ExternalAddress(vector_int_mask_cmp_bits()),
40875 false, Assembler::AVX_512bit, opnd_array(4)->as_Register(ra_,this,idx4)/* tmp */);
40876 ___masm. evpmovdb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, Assembler::AVX_512bit);
40877
40878#line 40878 "ad_x86.cpp"
40879 }
40880}
40881
40882void vstoreMask_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40883 cbuf.set_insts_mark();
40884 // Start at oper_input_base() and count operands
40885 unsigned idx0 = 1;
40886 unsigned idx1 = 1; // mask
40887 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // size
40888 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
40889 {
40890 C2_MacroAssembler _masm(&cbuf);
40891
40892#line 8118 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
40893
40894 int dst_vlen_enc = vector_length_encoding(this);
40895 ___masm. evpmovm2b(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_KRegister(ra_,this,idx1)/* mask */, dst_vlen_enc);
40896 ___masm. vpabsb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, dst_vlen_enc);
40897
40898#line 40898 "ad_x86.cpp"
40899 }
40900}
40901
40902void vmaskcast_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40903 cbuf.set_insts_mark();
40904 // Start at oper_input_base() and count operands
40905 unsigned idx0 = 1;
40906 unsigned idx1 = 1; // dst
40907 {
40908 C2_MacroAssembler _masm(&cbuf);
40909
40910#line 8131 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
40911
40912 // empty
40913
40914#line 40914 "ad_x86.cpp"
40915 }
40916}
40917
40918void vmaskcastNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40919 cbuf.set_insts_mark();
40920 // Start at oper_input_base() and count operands
40921 unsigned idx0 = 1;
40922 unsigned idx1 = 1; // dst
40923 {
40924 C2_MacroAssembler _masm(&cbuf);
40925
40926#line 8143 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
40927
40928 // empty
40929
40930#line 40930 "ad_x86.cpp"
40931 }
40932}
40933
40934void loadIotaIndicesNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40935 cbuf.set_insts_mark();
40936 // Start at oper_input_base() and count operands
40937 unsigned idx0 = 1;
40938 unsigned idx1 = 1; // src
40939 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // scratch
40940 {
40941 C2_MacroAssembler _masm(&cbuf);
40942
40943#line 8156 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
40944
40945 int vlen_in_bytes = Matcher::vector_length_in_bytes(this);
40946 ___masm. load_iota_indices(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_Register(ra_,this,idx2)/* scratch */, vlen_in_bytes);
40947
40948#line 40948 "ad_x86.cpp"
40949 }
40950}
40951
40952void loadShuffleBNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40953 cbuf.set_insts_mark();
40954 // Start at oper_input_base() and count operands
40955 unsigned idx0 = 1;
40956 unsigned idx1 = 1; // dst
40957 {
40958 C2_MacroAssembler _masm(&cbuf);
40959
40960#line 8171 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
40961
40962 // empty
40963
40964#line 40964 "ad_x86.cpp"
40965 }
40966}
40967
40968void rearrangeBNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40969 cbuf.set_insts_mark();
40970 // Start at oper_input_base() and count operands
40971 unsigned idx0 = 1;
40972 unsigned idx1 = 1; // dst
40973 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shuffle
40974 {
40975 C2_MacroAssembler _masm(&cbuf);
40976
40977#line 8182 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
40978
40979 assert(UseSSE >= 4, "required")do { if (!(UseSSE >= 4)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
8183, "assert(" "UseSSE >= 4" ") failed", "required"); ::
breakpoint(); } } while (0);
40980 ___masm. pshufb(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shuffle */);
40981
40982#line 40982 "ad_x86.cpp"
40983 }
40984}
40985
40986void rearrangeB_avxNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
40987 cbuf.set_insts_mark();
40988 // Start at oper_input_base() and count operands
40989 unsigned idx0 = 1;
40990 unsigned idx1 = 1; // src
40991 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shuffle
40992 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
40993 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp1
40994 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // vtmp2
40995 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // scratch
40996 {
40997 C2_MacroAssembler _masm(&cbuf);
40998
40999#line 8195 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
41000
41001 assert(UseAVX >= 2, "required")do { if (!(UseAVX >= 2)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
8196, "assert(" "UseAVX >= 2" ") failed", "required"); ::
breakpoint(); } } while (0);
41002 // Swap src into vtmp1
41003 ___masm. vperm2i128(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, 1);
41004 // Shuffle swapped src to get entries from other 128 bit lane
41005 ___masm. vpshufb(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shuffle */, Assembler::AVX_256bit);
41006 // Shuffle original src to get entries from self 128 bit lane
41007 ___masm. vpshufb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shuffle */, Assembler::AVX_256bit);
41008 // Create a blend mask by setting high bits for entries coming from other lane in shuffle
41009 ___masm. vpaddb(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shuffle */, ExternalAddress(vector_byte_shufflemask()), Assembler::AVX_256bit, opnd_array(6)->as_Register(ra_,this,idx6)/* scratch */);
41010 // Perform the blend
41011 ___masm. vpblendvb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, Assembler::AVX_256bit);
41012
41013#line 41013 "ad_x86.cpp"
41014 }
41015}
41016
41017void rearrangeB_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41018 cbuf.set_insts_mark();
41019 // Start at oper_input_base() and count operands
41020 unsigned idx0 = 1;
41021 unsigned idx1 = 1; // src
41022 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shuffle
41023 {
41024 C2_MacroAssembler _masm(&cbuf);
41025
41026#line 8216 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
41027
41028 int vlen_enc = vector_length_encoding(this);
41029 ___masm. vpermb(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shuffle */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vlen_enc);
41030
41031#line 41031 "ad_x86.cpp"
41032 }
41033}
41034
41035void loadShuffleSNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41036 cbuf.set_insts_mark();
41037 // Start at oper_input_base() and count operands
41038 unsigned idx0 = 1;
41039 unsigned idx1 = 1; // src
41040 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
41041 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp
41042 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // scratch
41043 {
41044 C2_MacroAssembler _masm(&cbuf);
41045
41046#line 8231 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
41047
41048 // Create a byte shuffle mask from short shuffle mask
41049 // only byte shuffle instruction available on these platforms
41050 int vlen_in_bytes = Matcher::vector_length_in_bytes(this);
41051 if (UseAVX == 0) {
41052 assert(vlen_in_bytes <= 16, "required")do { if (!(vlen_in_bytes <= 16)) { (*g_assert_poison) = 'X'
;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 8236, "assert(" "vlen_in_bytes <= 16" ") failed", "required"
); ::breakpoint(); } } while (0);
41053 // Multiply each shuffle by two to get byte index
41054 ___masm. pmovzxbw(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
41055 ___masm. psllw(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp */, 1);
41056
41057 // Duplicate to create 2 copies of byte index
41058 ___masm. movdqu(opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp */);
41059 ___masm. psllw(opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* dst */, 8);
41060 ___masm. por(opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp */);
41061
41062 // Add one to get alternate byte index
41063 ___masm. movdqu(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp */, ExternalAddress(vector_short_shufflemask()), opnd_array(4)->as_Register(ra_,this,idx4)/* scratch */);
41064 ___masm. paddb(opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp */);
41065 } else {
41066 assert(UseAVX > 1 || vlen_in_bytes <= 16, "required")do { if (!(UseAVX > 1 || vlen_in_bytes <= 16)) { (*g_assert_poison
) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 8250, "assert(" "UseAVX > 1 || vlen_in_bytes <= 16" ") failed"
, "required"); ::breakpoint(); } } while (0);
41067 int vlen_enc = vector_length_encoding(this);
41068 // Multiply each shuffle by two to get byte index
41069 ___masm. vpmovzxbw(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vlen_enc);
41070 ___masm. vpsllw(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp */, 1, vlen_enc);
41071
41072 // Duplicate to create 2 copies of byte index
41073 ___masm. vpsllw(opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp */, 8, vlen_enc);
41074 ___masm. vpor(opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp */, vlen_enc);
41075
41076 // Add one to get alternate byte index
41077 ___masm. vpaddb(opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* dst */, ExternalAddress(vector_short_shufflemask()), vlen_enc, opnd_array(4)->as_Register(ra_,this,idx4)/* scratch */);
41078 }
41079
41080#line 41080 "ad_x86.cpp"
41081 }
41082}
41083
41084void rearrangeSNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41085 cbuf.set_insts_mark();
41086 // Start at oper_input_base() and count operands
41087 unsigned idx0 = 1;
41088 unsigned idx1 = 1; // dst
41089 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shuffle
41090 {
41091 C2_MacroAssembler _masm(&cbuf);
41092
41093#line 8272 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
41094
41095 assert(UseSSE >= 4, "required")do { if (!(UseSSE >= 4)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
8273, "assert(" "UseSSE >= 4" ") failed", "required"); ::
breakpoint(); } } while (0);
41096 ___masm. pshufb(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shuffle */);
41097
41098#line 41098 "ad_x86.cpp"
41099 }
41100}
41101
41102void rearrangeS_avxNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41103 cbuf.set_insts_mark();
41104 // Start at oper_input_base() and count operands
41105 unsigned idx0 = 1;
41106 unsigned idx1 = 1; // src
41107 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shuffle
41108 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
41109 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // vtmp1
41110 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // vtmp2
41111 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // scratch
41112 {
41113 C2_MacroAssembler _masm(&cbuf);
41114
41115#line 8285 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
41116
41117 assert(UseAVX >= 2, "required")do { if (!(UseAVX >= 2)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
8286, "assert(" "UseAVX >= 2" ") failed", "required"); ::
breakpoint(); } } while (0);
41118 // Swap src into vtmp1
41119 ___masm. vperm2i128(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, 1);
41120 // Shuffle swapped src to get entries from other 128 bit lane
41121 ___masm. vpshufb(opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shuffle */, Assembler::AVX_256bit);
41122 // Shuffle original src to get entries from self 128 bit lane
41123 ___masm. vpshufb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shuffle */, Assembler::AVX_256bit);
41124 // Create a blend mask by setting high bits for entries coming from other lane in shuffle
41125 ___masm. vpaddb(opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shuffle */, ExternalAddress(vector_byte_shufflemask()), Assembler::AVX_256bit, opnd_array(6)->as_Register(ra_,this,idx6)/* scratch */);
41126 // Perform the blend
41127 ___masm. vpblendvb(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* vtmp1 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* vtmp2 */, Assembler::AVX_256bit);
41128
41129#line 41129 "ad_x86.cpp"
41130 }
41131}
41132
41133void loadShuffleS_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41134 cbuf.set_insts_mark();
41135 // Start at oper_input_base() and count operands
41136 unsigned idx0 = 1;
41137 unsigned idx1 = 1; // src
41138 {
41139 C2_MacroAssembler _masm(&cbuf);
41140
41141#line 8306 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
41142
41143 int vlen_enc = vector_length_encoding(this);
41144 if (!VM_Version::supports_avx512vl()) {
41145 vlen_enc = Assembler::AVX_512bit;
41146 }
41147 ___masm. vpmovzxbw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vlen_enc);
41148
41149#line 41149 "ad_x86.cpp"
41150 }
41151}
41152
41153void rearrangeS_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41154 cbuf.set_insts_mark();
41155 // Start at oper_input_base() and count operands
41156 unsigned idx0 = 1;
41157 unsigned idx1 = 1; // src
41158 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shuffle
41159 {
41160 C2_MacroAssembler _masm(&cbuf);
41161
41162#line 8321 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
41163
41164 int vlen_enc = vector_length_encoding(this);
41165 if (!VM_Version::supports_avx512vl()) {
41166 vlen_enc = Assembler::AVX_512bit;
41167 }
41168 ___masm. vpermw(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shuffle */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vlen_enc);
41169
41170#line 41170 "ad_x86.cpp"
41171 }
41172}
41173
41174void loadShuffleINode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41175 cbuf.set_insts_mark();
41176 // Start at oper_input_base() and count operands
41177 unsigned idx0 = 1;
41178 unsigned idx1 = 1; // src
41179 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
41180 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp
41181 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // scratch
41182 {
41183 C2_MacroAssembler _masm(&cbuf);
41184
41185#line 8339 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
41186
41187 assert(UseSSE >= 4, "required")do { if (!(UseSSE >= 4)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
8340, "assert(" "UseSSE >= 4" ") failed", "required"); ::
breakpoint(); } } while (0);
41188
41189 // Create a byte shuffle mask from int shuffle mask
41190 // only byte shuffle instruction available on these platforms
41191
41192 // Duplicate and multiply each shuffle by 4
41193 ___masm. pmovzxbd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */);
41194 ___masm. pshuflw(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp */, 0xA0);
41195 ___masm. pshufhw(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp */, 0xA0);
41196 ___masm. psllw(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp */, 2);
41197
41198 // Duplicate again to create 4 copies of byte index
41199 ___masm. movdqu(opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp */);
41200 ___masm. psllw(opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* dst */, 8);
41201 ___masm. por(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* dst */);
41202
41203 // Add 3,2,1,0 to get alternate byte index
41204 ___masm. movdqu(opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* dst */, ExternalAddress(vector_int_shufflemask()), opnd_array(4)->as_Register(ra_,this,idx4)/* scratch */);
41205 ___masm. paddb(opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp */);
41206
41207#line 41207 "ad_x86.cpp"
41208 }
41209}
41210
41211void rearrangeINode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41212 cbuf.set_insts_mark();
41213 // Start at oper_input_base() and count operands
41214 unsigned idx0 = 1;
41215 unsigned idx1 = 1; // dst
41216 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shuffle
41217 {
41218 C2_MacroAssembler _masm(&cbuf);
41219
41220#line 8368 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
41221
41222 assert(UseSSE >= 4, "required")do { if (!(UseSSE >= 4)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
8369, "assert(" "UseSSE >= 4" ") failed", "required"); ::
breakpoint(); } } while (0);
41223 ___masm. pshufb(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shuffle */);
41224
41225#line 41225 "ad_x86.cpp"
41226 }
41227}
41228
41229void loadShuffleI_avxNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41230 cbuf.set_insts_mark();
41231 // Start at oper_input_base() and count operands
41232 unsigned idx0 = 1;
41233 unsigned idx1 = 1; // src
41234 {
41235 C2_MacroAssembler _masm(&cbuf);
41236
41237#line 8380 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
41238
41239 int vlen_enc = vector_length_encoding(this);
41240 ___masm. vpmovzxbd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vlen_enc);
41241
41242#line 41242 "ad_x86.cpp"
41243 }
41244}
41245
41246void rearrangeI_avxNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41247 cbuf.set_insts_mark();
41248 // Start at oper_input_base() and count operands
41249 unsigned idx0 = 1;
41250 unsigned idx1 = 1; // src
41251 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shuffle
41252 {
41253 C2_MacroAssembler _masm(&cbuf);
41254
41255#line 8392 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
41256
41257 int vlen_enc = vector_length_encoding(this);
41258 if (vlen_enc == Assembler::AVX_128bit) {
41259 vlen_enc = Assembler::AVX_256bit;
41260 }
41261 ___masm. vpermd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shuffle */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vlen_enc);
41262
41263#line 41263 "ad_x86.cpp"
41264 }
41265}
41266
41267void loadShuffleLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41268 cbuf.set_insts_mark();
41269 // Start at oper_input_base() and count operands
41270 unsigned idx0 = 1;
41271 unsigned idx1 = 1; // src
41272 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
41273 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // vtmp
41274 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // scratch
41275 {
41276 C2_MacroAssembler _masm(&cbuf);
41277
41278#line 8410 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
41279
41280 assert(UseAVX >= 2, "required")do { if (!(UseAVX >= 2)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
8411, "assert(" "UseAVX >= 2" ") failed", "required"); ::
breakpoint(); } } while (0);
41281
41282 int vlen_enc = vector_length_encoding(this);
41283 // Create a double word shuffle mask from long shuffle mask
41284 // only double word shuffle instruction available on these platforms
41285
41286 // Multiply each shuffle by two to get double word index
41287 ___masm. vpmovzxbq(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vlen_enc);
41288 ___masm. vpsllq(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp */, 1, vlen_enc);
41289
41290 // Duplicate each double word shuffle
41291 ___masm. vpsllq(opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp */, 32, vlen_enc);
41292 ___masm. vpor(opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* dst */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* vtmp */, vlen_enc);
41293
41294 // Add one to get alternate double word index
41295 ___masm. vpaddd(opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* dst */, ExternalAddress(vector_long_shufflemask()), vlen_enc, opnd_array(4)->as_Register(ra_,this,idx4)/* scratch */);
41296
41297#line 41297 "ad_x86.cpp"
41298 }
41299}
41300
41301void rearrangeLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41302 cbuf.set_insts_mark();
41303 // Start at oper_input_base() and count operands
41304 unsigned idx0 = 1;
41305 unsigned idx1 = 1; // src
41306 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shuffle
41307 {
41308 C2_MacroAssembler _masm(&cbuf);
41309
41310#line 8436 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
41311
41312 assert(UseAVX >= 2, "required")do { if (!(UseAVX >= 2)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
8437, "assert(" "UseAVX >= 2" ") failed", "required"); ::
breakpoint(); } } while (0);
41313
41314 int vlen_enc = vector_length_encoding(this);
41315 ___masm. vpermd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shuffle */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vlen_enc);
41316
41317#line 41317 "ad_x86.cpp"
41318 }
41319}
41320
41321void loadShuffleL_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41322 cbuf.set_insts_mark();
41323 // Start at oper_input_base() and count operands
41324 unsigned idx0 = 1;
41325 unsigned idx1 = 1; // src
41326 {
41327 C2_MacroAssembler _masm(&cbuf);
41328
41329#line 8450 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
41330
41331 assert(UseAVX > 2, "required")do { if (!(UseAVX > 2)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
8451, "assert(" "UseAVX > 2" ") failed", "required"); ::breakpoint
(); } } while (0);
41332
41333 int vlen_enc = vector_length_encoding(this);
41334 ___masm. vpmovzxbq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vlen_enc);
41335
41336#line 41336 "ad_x86.cpp"
41337 }
41338}
41339
41340void rearrangeL_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41341 cbuf.set_insts_mark();
41342 // Start at oper_input_base() and count operands
41343 unsigned idx0 = 1;
41344 unsigned idx1 = 1; // src
41345 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shuffle
41346 {
41347 C2_MacroAssembler _masm(&cbuf);
41348
41349#line 8464 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
41350
41351 assert(UseAVX > 2, "required")do { if (!(UseAVX > 2)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
8465, "assert(" "UseAVX > 2" ") failed", "required"); ::breakpoint
(); } } while (0);
41352
41353 int vlen_enc = vector_length_encoding(this);
41354 if (vlen_enc == Assembler::AVX_128bit) {
41355 vlen_enc = Assembler::AVX_256bit;
41356 }
41357 ___masm. vpermq(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shuffle */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vlen_enc);
41358
41359#line 41359 "ad_x86.cpp"
41360 }
41361}
41362
41363void vfmaF_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41364 cbuf.set_insts_mark();
41365 // Start at oper_input_base() and count operands
41366 unsigned idx0 = 1;
41367 unsigned idx1 = 1; // c
41368 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // a
41369 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // b
41370 {
41371 C2_MacroAssembler _masm(&cbuf);
41372
41373#line 8483 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
41374
41375 assert(UseFMA, "not enabled")do { if (!(UseFMA)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
8484, "assert(" "UseFMA" ") failed", "not enabled"); ::breakpoint
(); } } while (0);
41376 int vlen_enc = vector_length_encoding(this);
41377 ___masm. vfmaf(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* c */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* a */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* b */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* c */, vlen_enc);
41378
41379#line 41379 "ad_x86.cpp"
41380 }
41381}
41382
41383void vfmaF_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41384 cbuf.set_insts_mark();
41385 // Start at oper_input_base() and count operands
41386 unsigned idx0 = 2;
41387 unsigned idx1 = 2; // c
41388 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // a
41389 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // b
41390 {
41391 C2_MacroAssembler _masm(&cbuf);
41392
41393#line 8496 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
41394
41395 assert(UseFMA, "not enabled")do { if (!(UseFMA)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
8497, "assert(" "UseFMA" ") failed", "not enabled"); ::breakpoint
(); } } while (0);
41396 int vlen_enc = vector_length_encoding(this);
41397 ___masm. vfmaf(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* c */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* a */, Address::make_raw(opnd_array(3)->base(ra_,this,idx3), opnd_array(3)->index(ra_,this,idx3), opnd_array(3)->scale(), opnd_array(3)->disp(ra_,this,idx3), opnd_array(3)->disp_reloc()), opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* c */, vlen_enc);
41398
41399#line 41399 "ad_x86.cpp"
41400 }
41401}
41402
41403void vfmaD_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41404 cbuf.set_insts_mark();
41405 // Start at oper_input_base() and count operands
41406 unsigned idx0 = 1;
41407 unsigned idx1 = 1; // c
41408 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // a
41409 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // b
41410 {
41411 C2_MacroAssembler _masm(&cbuf);
41412
41413#line 8508 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
41414
41415 assert(UseFMA, "not enabled")do { if (!(UseFMA)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
8509, "assert(" "UseFMA" ") failed", "not enabled"); ::breakpoint
(); } } while (0);
41416 int vlen_enc = vector_length_encoding(this);
41417 ___masm. vfmad(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* c */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* a */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* b */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* c */, vlen_enc);
41418
41419#line 41419 "ad_x86.cpp"
41420 }
41421}
41422
41423void vfmaD_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41424 cbuf.set_insts_mark();
41425 // Start at oper_input_base() and count operands
41426 unsigned idx0 = 2;
41427 unsigned idx1 = 2; // c
41428 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // a
41429 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // b
41430 {
41431 C2_MacroAssembler _masm(&cbuf);
41432
41433#line 8521 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
41434
41435 assert(UseFMA, "not enabled")do { if (!(UseFMA)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
8522, "assert(" "UseFMA" ") failed", "not enabled"); ::breakpoint
(); } } while (0);
41436 int vlen_enc = vector_length_encoding(this);
41437 ___masm. vfmad(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* c */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* a */, Address::make_raw(opnd_array(3)->base(ra_,this,idx3), opnd_array(3)->index(ra_,this,idx3), opnd_array(3)->scale(), opnd_array(3)->disp(ra_,this,idx3), opnd_array(3)->disp_reloc()), opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* c */, vlen_enc);
41438
41439#line 41439 "ad_x86.cpp"
41440 }
41441}
41442
41443void vmuladdS2I_reg_sseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41444 cbuf.set_insts_mark();
41445 // Start at oper_input_base() and count operands
41446 unsigned idx0 = 1;
41447 unsigned idx1 = 1; // dst
41448 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src1
41449 {
41450 C2_MacroAssembler _masm(&cbuf);
41451
41452#line 8535 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
41453
41454 ___masm. pmaddwd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src1 */);
41455
41456#line 41456 "ad_x86.cpp"
41457 }
41458}
41459
41460void vmuladdS2I_reg_avxNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41461 cbuf.set_insts_mark();
41462 // Start at oper_input_base() and count operands
41463 unsigned idx0 = 1;
41464 unsigned idx1 = 1; // src1
41465 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
41466 {
41467 C2_MacroAssembler _masm(&cbuf);
41468
41469#line 8545 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
41470
41471 int vlen_enc = vector_length_encoding(this);
41472 ___masm. vpmaddwd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vlen_enc);
41473
41474#line 41474 "ad_x86.cpp"
41475 }
41476}
41477
41478void vmuladdaddS2I_regNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41479 cbuf.set_insts_mark();
41480 // Start at oper_input_base() and count operands
41481 unsigned idx0 = 1;
41482 unsigned idx1 = 1; // src1
41483 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
41484 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
41485 {
41486 C2_MacroAssembler _masm(&cbuf);
41487
41488#line 8558 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
41489
41490 assert(UseAVX > 2, "required")do { if (!(UseAVX > 2)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
8559, "assert(" "UseAVX > 2" ") failed", "required"); ::breakpoint
(); } } while (0);
41491 int vlen_enc = vector_length_encoding(this);
41492 ___masm. evpdpwssd(opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, vlen_enc);
41493
41494#line 41494 "ad_x86.cpp"
41495 }
41496}
41497
41498void vmuladdaddS2I_reg_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41499 cbuf.set_insts_mark();
41500 // Start at oper_input_base() and count operands
41501 unsigned idx0 = 1;
41502 unsigned idx1 = 1; // dst
41503 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src1
41504 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // src2
41505 {
41506 C2_MacroAssembler _masm(&cbuf);
41507
41508#line 8558 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
41509
41510 assert(UseAVX > 2, "required")do { if (!(UseAVX > 2)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
8559, "assert(" "UseAVX > 2" ") failed", "required"); ::breakpoint
(); } } while (0);
41511 int vlen_enc = vector_length_encoding(this);
41512 ___masm. evpdpwssd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src1 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* src2 */, vlen_enc);
41513
41514#line 41514 "ad_x86.cpp"
41515 }
41516}
41517
41518void vpopcountINode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41519 cbuf.set_insts_mark();
41520 // Start at oper_input_base() and count operands
41521 unsigned idx0 = 1;
41522 unsigned idx1 = 1; // src
41523 {
41524 C2_MacroAssembler _masm(&cbuf);
41525
41526#line 8572 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
41527
41528 assert(UsePopCountInstruction, "not enabled")do { if (!(UsePopCountInstruction)) { (*g_assert_poison) = 'X'
;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 8573, "assert(" "UsePopCountInstruction" ") failed", "not enabled"
); ::breakpoint(); } } while (0);
41529
41530 int vlen_enc = vector_length_encoding(this);
41531 ___masm. vpopcntd(opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, vlen_enc);
41532
41533#line 41533 "ad_x86.cpp"
41534 }
41535}
41536
41537void vpternlogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41538 cbuf.set_insts_mark();
41539 // Start at oper_input_base() and count operands
41540 unsigned idx0 = 1;
41541 unsigned idx1 = 1; // dst
41542 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
41543 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // src3
41544 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // func
41545 {
41546 C2_MacroAssembler _masm(&cbuf);
41547
41548#line 8587 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
41549
41550 int vector_len = vector_length_encoding(this);
41551 ___masm. vpternlogd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(4)->constant(), opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* src3 */, vector_len);
41552
41553#line 41553 "ad_x86.cpp"
41554 }
41555}
41556
41557void vpternlog_memNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41558 cbuf.set_insts_mark();
41559 // Start at oper_input_base() and count operands
41560 unsigned idx0 = 2;
41561 unsigned idx1 = 2; // dst
41562 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
41563 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // src3
41564 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // func
41565 {
41566 C2_MacroAssembler _masm(&cbuf);
41567
41568#line 8599 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
41569
41570 int vector_len = vector_length_encoding(this);
41571 ___masm. vpternlogd(opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(4)->constant(), opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, Address::make_raw(opnd_array(3)->base(ra_,this,idx3), opnd_array(3)->index(ra_,this,idx3), opnd_array(3)->scale(), opnd_array(3)->disp(ra_,this,idx3), opnd_array(3)->disp_reloc()), vector_len);
41572
41573#line 41573 "ad_x86.cpp"
41574 }
41575}
41576
41577void vprotate_immI8Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41578 cbuf.set_insts_mark();
41579 // Start at oper_input_base() and count operands
41580 unsigned idx0 = 1;
41581 unsigned idx1 = 1; // src
41582 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
41583 {
41584 C2_MacroAssembler _masm(&cbuf);
41585
41586#line 8611 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
41587
41588 int opcode = this->ideal_Opcode();
41589 int vector_len = vector_length_encoding(this);
41590 BasicType etype = this->bottom_type()->is_vect()->element_basic_type();
41591 ___masm. vprotate_imm(opcode, etype, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->constant(), vector_len);
41592
41593#line 41593 "ad_x86.cpp"
41594 }
41595}
41596
41597void vprotate_immI8_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41598 cbuf.set_insts_mark();
41599 // Start at oper_input_base() and count operands
41600 unsigned idx0 = 1;
41601 unsigned idx1 = 1; // src
41602 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
41603 {
41604 C2_MacroAssembler _masm(&cbuf);
41605
41606#line 8611 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
41607
41608 int opcode = this->ideal_Opcode();
41609 int vector_len = vector_length_encoding(this);
41610 BasicType etype = this->bottom_type()->is_vect()->element_basic_type();
41611 ___masm. vprotate_imm(opcode, etype, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->constant(), vector_len);
41612
41613#line 41613 "ad_x86.cpp"
41614 }
41615}
41616
41617void vprorateNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41618 cbuf.set_insts_mark();
41619 // Start at oper_input_base() and count operands
41620 unsigned idx0 = 1;
41621 unsigned idx1 = 1; // src
41622 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
41623 {
41624 C2_MacroAssembler _masm(&cbuf);
41625
41626#line 8624 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
41627
41628 int opcode = this->ideal_Opcode();
41629 int vector_len = vector_length_encoding(this);
41630 BasicType etype = this->bottom_type()->is_vect()->element_basic_type();
41631 ___masm. vprotate_var(opcode, etype, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vector_len);
41632
41633#line 41633 "ad_x86.cpp"
41634 }
41635}
41636
41637void vprorate_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41638 cbuf.set_insts_mark();
41639 // Start at oper_input_base() and count operands
41640 unsigned idx0 = 1;
41641 unsigned idx1 = 1; // src
41642 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
41643 {
41644 C2_MacroAssembler _masm(&cbuf);
41645
41646#line 8624 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
41647
41648 int opcode = this->ideal_Opcode();
41649 int vector_len = vector_length_encoding(this);
41650 BasicType etype = this->bottom_type()->is_vect()->element_basic_type();
41651 ___masm. vprotate_var(opcode, etype, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* shift */, vector_len);
41652
41653#line 41653 "ad_x86.cpp"
41654 }
41655}
41656
41657void vmask_cmp_nodeNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41658 cbuf.set_insts_mark();
41659 // Start at oper_input_base() and count operands
41660 unsigned idx0 = 1;
41661 unsigned idx1 = 1; // src1
41662 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
41663 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
41664 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // dst
41665 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // ktmp1
41666 unsigned idx6 = idx5 + opnd_array(5)->num_edges(); // ktmp2
41667 {
41668 C2_MacroAssembler _masm(&cbuf);
41669
41670#line 8640 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
41671
41672 assert(vector_length_encoding(this, opnd_array(1)) == vector_length_encoding(this, opnd_array(2)), "mismatch")do { if (!(vector_length_encoding(this, opnd_array(1)) == vector_length_encoding
(this, opnd_array(2)))) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
8641, "assert(" "vector_length_encoding(this, opnd_array(1)) == vector_length_encoding(this, opnd_array(2))"
") failed", "mismatch"); ::breakpoint(); } } while (0);
41673 assert(Matcher::vector_element_basic_type(this, opnd_array(1)) == Matcher::vector_element_basic_type(this, opnd_array(2)), "mismatch")do { if (!(Matcher::vector_element_basic_type(this, opnd_array
(1)) == Matcher::vector_element_basic_type(this, opnd_array(2
)))) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 8642, "assert(" "Matcher::vector_element_basic_type(this, opnd_array(1)) == Matcher::vector_element_basic_type(this, opnd_array(2))"
") failed", "mismatch"); ::breakpoint(); } } while (0);
41674
41675 Label DONE;
41676 int vlen_enc = vector_length_encoding(this, opnd_array(1));
41677 BasicType elem_bt = Matcher::vector_element_basic_type(this, opnd_array(1));
41678
41679 ___masm. knotql(opnd_array(6)->as_KRegister(ra_,this,idx6)/* ktmp2 */, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */);
41680 ___masm. mov64(opnd_array(4)->as_Register(ra_,this,idx4)/* dst */, -1L);
41681 ___masm. evpcmp(elem_bt, opnd_array(5)->as_KRegister(ra_,this,idx5)/* ktmp1 */, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, Assembler::eq, vlen_enc);
41682 ___masm. kortestql(opnd_array(6)->as_KRegister(ra_,this,idx6)/* ktmp2 */, opnd_array(5)->as_KRegister(ra_,this,idx5)/* ktmp1 */);
41683 ___masm. jccb(Assembler::carrySet, DONE)jccb_0(Assembler::carrySet, DONE, "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 8652);
41684 ___masm. kmovql(opnd_array(4)->as_Register(ra_,this,idx4)/* dst */, opnd_array(5)->as_KRegister(ra_,this,idx5)/* ktmp1 */);
41685 ___masm. notq(opnd_array(4)->as_Register(ra_,this,idx4)/* dst */);
41686 ___masm. tzcntq(opnd_array(4)->as_Register(ra_,this,idx4)/* dst */, opnd_array(4)->as_Register(ra_,this,idx4)/* dst */);
41687 ___masm. bind(DONE);
41688
41689#line 41689 "ad_x86.cpp"
41690 }
41691}
41692
41693void vmasked_load64Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41694 cbuf.set_insts_mark();
41695 // Start at oper_input_base() and count operands
41696 unsigned idx0 = 2;
41697 unsigned idx1 = 2; // mem
41698 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask
41699 {
41700 C2_MacroAssembler _masm(&cbuf);
41701
41702#line 8665 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
41703
41704 BasicType elmType = this->bottom_type()->is_vect()->element_basic_type();
41705 int vector_len = vector_length_encoding(this);
41706 ___masm. evmovdqu(elmType, opnd_array(2)->as_KRegister(ra_,this,idx2)/* mask */, opnd_array(0)->as_XMMRegister(ra_,this)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), vector_len);
41707
41708#line 41708 "ad_x86.cpp"
41709 }
41710}
41711
41712void vmask_genNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41713 cbuf.set_insts_mark();
41714 // Start at oper_input_base() and count operands
41715 unsigned idx0 = 1;
41716 unsigned idx1 = 1; // len
41717 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // temp
41718 {
41719 C2_MacroAssembler _masm(&cbuf);
41720
41721#line 8677 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
41722
41723 ___masm. genmask(opnd_array(0)->as_KRegister(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* len */, opnd_array(2)->as_Register(ra_,this,idx2)/* temp */);
41724
41725#line 41725 "ad_x86.cpp"
41726 }
41727}
41728
41729void vmask_gen_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41730 cbuf.set_insts_mark();
41731 // Start at oper_input_base() and count operands
41732 unsigned idx0 = 1;
41733 unsigned idx1 = 1; // len
41734 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // temp
41735 {
41736 C2_MacroAssembler _masm(&cbuf);
41737
41738#line 8687 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
41739
41740 ___masm. mov64(opnd_array(2)->as_Register(ra_,this,idx2)/* temp */, (0xFFFFFFFFFFFFFFFFUL >> (64 -opnd_array(1)->constantL())));
41741 ___masm. kmovql(opnd_array(0)->as_KRegister(ra_,this)/* dst */, opnd_array(2)->as_Register(ra_,this,idx2)/* temp */);
41742
41743#line 41743 "ad_x86.cpp"
41744 }
41745}
41746
41747void vmasked_store64Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41748 cbuf.set_insts_mark();
41749 // Start at oper_input_base() and count operands
41750 unsigned idx0 = 2;
41751 unsigned idx1 = 2; // mem
41752 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src
41753 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
41754 {
41755 C2_MacroAssembler _masm(&cbuf);
41756
41757#line 8697 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
41758
41759 const MachNode* src_node = static_cast<const MachNode*>(this->in(this->operand_index(opnd_array(2))));
41760 BasicType elmType = src_node->bottom_type()->is_vect()->element_basic_type();
41761 int vector_len = vector_length_encoding(src_node);
41762 ___masm. evmovdqu(elmType, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src */, vector_len);
41763
41764#line 41764 "ad_x86.cpp"
41765 }
41766}
41767
41768void vmask_tolong_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41769 cbuf.set_insts_mark();
41770 // Start at oper_input_base() and count operands
41771 unsigned idx0 = 1;
41772 unsigned idx1 = 1; // mask
41773 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
41774 {
41775 C2_MacroAssembler _masm(&cbuf);
41776
41777#line 8711 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
41778
41779 int opcode = this->ideal_Opcode();
41780 BasicType mbt = Matcher::vector_element_basic_type(this, opnd_array(1));
41781 int mask_len = Matcher::vector_length(this, opnd_array(1));
41782 int mask_size = mask_len * type2aelembytes(mbt);
41783 int vlen_enc = vector_length_encoding(this, opnd_array(1));
41784 ___masm. vector_mask_operation(opcode, opnd_array(2)->as_Register(ra_,this,idx2)/* dst */, opnd_array(1)->as_KRegister(ra_,this,idx1)/* mask */,
41785 opnd_array(2)->as_Register(ra_,this,idx2)/* dst */, mask_len, mask_size, vlen_enc);
41786
41787#line 41787 "ad_x86.cpp"
41788 }
41789}
41790
41791void vmask_tolong_boolNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41792 cbuf.set_insts_mark();
41793 // Start at oper_input_base() and count operands
41794 unsigned idx0 = 1;
41795 unsigned idx1 = 1; // mask
41796 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
41797 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // xtmp
41798 {
41799 C2_MacroAssembler _masm(&cbuf);
41800
41801#line 8728 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
41802
41803 int opcode = this->ideal_Opcode();
41804 BasicType mbt = Matcher::vector_element_basic_type(this, opnd_array(1));
41805 int mask_len = Matcher::vector_length(this, opnd_array(1));
41806 int vlen_enc = vector_length_encoding(this, opnd_array(1));
41807 ___masm. vector_mask_operation(opcode, opnd_array(2)->as_Register(ra_,this,idx2)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* mask */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* xtmp */,
41808 opnd_array(2)->as_Register(ra_,this,idx2)/* dst */, mask_len, mbt, vlen_enc);
41809
41810#line 41810 "ad_x86.cpp"
41811 }
41812}
41813
41814void vmask_tolong_avxNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41815 cbuf.set_insts_mark();
41816 // Start at oper_input_base() and count operands
41817 unsigned idx0 = 1;
41818 unsigned idx1 = 1; // mask
41819 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // size
41820 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
41821 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // xtmp
41822 {
41823 C2_MacroAssembler _masm(&cbuf);
41824
41825#line 8744 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
41826
41827 int opcode = this->ideal_Opcode();
41828 BasicType mbt = Matcher::vector_element_basic_type(this, opnd_array(1));
41829 int mask_len = Matcher::vector_length(this, opnd_array(1));
41830 int vlen_enc = vector_length_encoding(this, opnd_array(1));
41831 ___masm. vector_mask_operation(opcode, opnd_array(3)->as_Register(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* mask */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* xtmp */,
41832 opnd_array(3)->as_Register(ra_,this,idx3)/* dst */, mask_len, mbt, vlen_enc);
41833
41834#line 41834 "ad_x86.cpp"
41835 }
41836}
41837
41838void vmask_truecount_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41839 cbuf.set_insts_mark();
41840 // Start at oper_input_base() and count operands
41841 unsigned idx0 = 1;
41842 unsigned idx1 = 1; // mask
41843 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
41844 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
41845 {
41846 C2_MacroAssembler _masm(&cbuf);
41847
41848#line 8760 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
41849
41850 int opcode = this->ideal_Opcode();
41851 BasicType mbt = Matcher::vector_element_basic_type(this, opnd_array(1));
41852 int mask_len = Matcher::vector_length(this, opnd_array(1));
41853 int mask_size = mask_len * type2aelembytes(mbt);
41854 int vlen_enc = vector_length_encoding(this, opnd_array(1));
41855 ___masm. vector_mask_operation(opcode, opnd_array(2)->as_Register(ra_,this,idx2)/* dst */, opnd_array(1)->as_KRegister(ra_,this,idx1)/* mask */,
41856 opnd_array(3)->as_Register(ra_,this,idx3)/* tmp */, mask_len, mask_size, vlen_enc);
41857
41858#line 41858 "ad_x86.cpp"
41859 }
41860}
41861
41862void vmask_truecount_boolNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41863 cbuf.set_insts_mark();
41864 // Start at oper_input_base() and count operands
41865 unsigned idx0 = 1;
41866 unsigned idx1 = 1; // mask
41867 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
41868 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
41869 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // xtmp
41870 {
41871 C2_MacroAssembler _masm(&cbuf);
41872
41873#line 8777 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
41874
41875 int opcode = this->ideal_Opcode();
41876 BasicType mbt = Matcher::vector_element_basic_type(this, opnd_array(1));
41877 int mask_len = Matcher::vector_length(this, opnd_array(1));
41878 int vlen_enc = vector_length_encoding(this, opnd_array(1));
41879 ___masm. vector_mask_operation(opcode, opnd_array(2)->as_Register(ra_,this,idx2)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* mask */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* xtmp */,
41880 opnd_array(3)->as_Register(ra_,this,idx3)/* tmp */, mask_len, mbt, vlen_enc);
41881
41882#line 41882 "ad_x86.cpp"
41883 }
41884}
41885
41886void vmask_truecount_avxNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41887 cbuf.set_insts_mark();
41888 // Start at oper_input_base() and count operands
41889 unsigned idx0 = 1;
41890 unsigned idx1 = 1; // mask
41891 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // size
41892 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
41893 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
41894 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // xtmp
41895 {
41896 C2_MacroAssembler _masm(&cbuf);
41897
41898#line 8793 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
41899
41900 int opcode = this->ideal_Opcode();
41901 BasicType mbt = Matcher::vector_element_basic_type(this, opnd_array(1));
41902 int mask_len = Matcher::vector_length(this, opnd_array(1));
41903 int vlen_enc = vector_length_encoding(this, opnd_array(1));
41904 ___masm. vector_mask_operation(opcode, opnd_array(3)->as_Register(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* mask */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* xtmp */,
41905 opnd_array(4)->as_Register(ra_,this,idx4)/* tmp */, mask_len, mbt, vlen_enc);
41906
41907#line 41907 "ad_x86.cpp"
41908 }
41909}
41910
41911void vmask_first_or_last_true_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41912 cbuf.set_insts_mark();
41913 // Start at oper_input_base() and count operands
41914 unsigned idx0 = 1;
41915 unsigned idx1 = 1; // mask
41916 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
41917 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
41918 {
41919 C2_MacroAssembler _masm(&cbuf);
41920
41921#line 8810 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
41922
41923 int opcode = this->ideal_Opcode();
41924 BasicType mbt = Matcher::vector_element_basic_type(this, opnd_array(1));
41925 int mask_len = Matcher::vector_length(this, opnd_array(1));
41926 int mask_size = mask_len * type2aelembytes(mbt);
41927 int vlen_enc = vector_length_encoding(this, opnd_array(1));
41928 ___masm. vector_mask_operation(opcode, opnd_array(2)->as_Register(ra_,this,idx2)/* dst */, opnd_array(1)->as_KRegister(ra_,this,idx1)/* mask */,
41929 opnd_array(3)->as_Register(ra_,this,idx3)/* tmp */, mask_len, mask_size, vlen_enc);
41930
41931#line 41931 "ad_x86.cpp"
41932 }
41933}
41934
41935void vmask_first_or_last_true_evex_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41936 cbuf.set_insts_mark();
41937 // Start at oper_input_base() and count operands
41938 unsigned idx0 = 1;
41939 unsigned idx1 = 1; // mask
41940 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
41941 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
41942 {
41943 C2_MacroAssembler _masm(&cbuf);
41944
41945#line 8810 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
41946
41947 int opcode = this->ideal_Opcode();
41948 BasicType mbt = Matcher::vector_element_basic_type(this, opnd_array(1));
41949 int mask_len = Matcher::vector_length(this, opnd_array(1));
41950 int mask_size = mask_len * type2aelembytes(mbt);
41951 int vlen_enc = vector_length_encoding(this, opnd_array(1));
41952 ___masm. vector_mask_operation(opcode, opnd_array(2)->as_Register(ra_,this,idx2)/* dst */, opnd_array(1)->as_KRegister(ra_,this,idx1)/* mask */,
41953 opnd_array(3)->as_Register(ra_,this,idx3)/* tmp */, mask_len, mask_size, vlen_enc);
41954
41955#line 41955 "ad_x86.cpp"
41956 }
41957}
41958
41959void vmask_first_or_last_true_boolNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41960 cbuf.set_insts_mark();
41961 // Start at oper_input_base() and count operands
41962 unsigned idx0 = 1;
41963 unsigned idx1 = 1; // mask
41964 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
41965 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
41966 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // xtmp
41967 {
41968 C2_MacroAssembler _masm(&cbuf);
41969
41970#line 8828 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
41971
41972 int opcode = this->ideal_Opcode();
41973 BasicType mbt = Matcher::vector_element_basic_type(this, opnd_array(1));
41974 int mask_len = Matcher::vector_length(this, opnd_array(1));
41975 int vlen_enc = vector_length_encoding(this, opnd_array(1));
41976 ___masm. vector_mask_operation(opcode, opnd_array(2)->as_Register(ra_,this,idx2)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* mask */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* xtmp */,
41977 opnd_array(3)->as_Register(ra_,this,idx3)/* tmp */, mask_len, mbt, vlen_enc);
41978
41979#line 41979 "ad_x86.cpp"
41980 }
41981}
41982
41983void vmask_first_or_last_true_bool_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
41984 cbuf.set_insts_mark();
41985 // Start at oper_input_base() and count operands
41986 unsigned idx0 = 1;
41987 unsigned idx1 = 1; // mask
41988 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
41989 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
41990 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // xtmp
41991 {
41992 C2_MacroAssembler _masm(&cbuf);
41993
41994#line 8828 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
41995
41996 int opcode = this->ideal_Opcode();
41997 BasicType mbt = Matcher::vector_element_basic_type(this, opnd_array(1));
41998 int mask_len = Matcher::vector_length(this, opnd_array(1));
41999 int vlen_enc = vector_length_encoding(this, opnd_array(1));
42000 ___masm. vector_mask_operation(opcode, opnd_array(2)->as_Register(ra_,this,idx2)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* mask */, opnd_array(4)->as_XMMRegister(ra_,this,idx4)/* xtmp */,
42001 opnd_array(3)->as_Register(ra_,this,idx3)/* tmp */, mask_len, mbt, vlen_enc);
42002
42003#line 42003 "ad_x86.cpp"
42004 }
42005}
42006
42007void vmask_first_or_last_true_avxNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42008 cbuf.set_insts_mark();
42009 // Start at oper_input_base() and count operands
42010 unsigned idx0 = 1;
42011 unsigned idx1 = 1; // mask
42012 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // size
42013 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
42014 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
42015 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // xtmp
42016 {
42017 C2_MacroAssembler _masm(&cbuf);
42018
42019#line 8845 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
42020
42021 int opcode = this->ideal_Opcode();
42022 BasicType mbt = Matcher::vector_element_basic_type(this, opnd_array(1));
42023 int mask_len = Matcher::vector_length(this, opnd_array(1));
42024 int vlen_enc = vector_length_encoding(this, opnd_array(1));
42025 ___masm. vector_mask_operation(opcode, opnd_array(3)->as_Register(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* mask */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* xtmp */,
42026 opnd_array(4)->as_Register(ra_,this,idx4)/* tmp */, mask_len, mbt, vlen_enc);
42027
42028#line 42028 "ad_x86.cpp"
42029 }
42030}
42031
42032void vmask_first_or_last_true_avx_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42033 cbuf.set_insts_mark();
42034 // Start at oper_input_base() and count operands
42035 unsigned idx0 = 1;
42036 unsigned idx1 = 1; // mask
42037 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // size
42038 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
42039 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
42040 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // xtmp
42041 {
42042 C2_MacroAssembler _masm(&cbuf);
42043
42044#line 8845 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
42045
42046 int opcode = this->ideal_Opcode();
42047 BasicType mbt = Matcher::vector_element_basic_type(this, opnd_array(1));
42048 int mask_len = Matcher::vector_length(this, opnd_array(1));
42049 int vlen_enc = vector_length_encoding(this, opnd_array(1));
42050 ___masm. vector_mask_operation(opcode, opnd_array(3)->as_Register(ra_,this,idx3)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* mask */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* xtmp */,
42051 opnd_array(4)->as_Register(ra_,this,idx4)/* tmp */, mask_len, mbt, vlen_enc);
42052
42053#line 42053 "ad_x86.cpp"
42054 }
42055}
42056
42057void vadd_reg_maskedNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42058 cbuf.set_insts_mark();
42059 // Start at oper_input_base() and count operands
42060 unsigned idx0 = 1;
42061 unsigned idx1 = 1; // dst
42062 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
42063 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
42064 {
42065 C2_MacroAssembler _masm(&cbuf);
42066
42067#line 8867 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
42068
42069 int vlen_enc = vector_length_encoding(this);
42070 BasicType bt = Matcher::vector_element_basic_type(this);
42071 int opc = this->ideal_Opcode();
42072 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
42073 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, true, vlen_enc);
42074
42075#line 42075 "ad_x86.cpp"
42076 }
42077}
42078
42079void vadd_reg_masked_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42080 cbuf.set_insts_mark();
42081 // Start at oper_input_base() and count operands
42082 unsigned idx0 = 1;
42083 unsigned idx1 = 1; // dst
42084 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
42085 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
42086 {
42087 C2_MacroAssembler _masm(&cbuf);
42088
42089#line 8867 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
42090
42091 int vlen_enc = vector_length_encoding(this);
42092 BasicType bt = Matcher::vector_element_basic_type(this);
42093 int opc = this->ideal_Opcode();
42094 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
42095 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, true, vlen_enc);
42096
42097#line 42097 "ad_x86.cpp"
42098 }
42099}
42100
42101void vadd_reg_masked_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42102 cbuf.set_insts_mark();
42103 // Start at oper_input_base() and count operands
42104 unsigned idx0 = 1;
42105 unsigned idx1 = 1; // dst
42106 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
42107 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
42108 {
42109 C2_MacroAssembler _masm(&cbuf);
42110
42111#line 8867 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
42112
42113 int vlen_enc = vector_length_encoding(this);
42114 BasicType bt = Matcher::vector_element_basic_type(this);
42115 int opc = this->ideal_Opcode();
42116 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
42117 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, true, vlen_enc);
42118
42119#line 42119 "ad_x86.cpp"
42120 }
42121}
42122
42123void vadd_reg_masked_2Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42124 cbuf.set_insts_mark();
42125 // Start at oper_input_base() and count operands
42126 unsigned idx0 = 1;
42127 unsigned idx1 = 1; // dst
42128 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
42129 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
42130 {
42131 C2_MacroAssembler _masm(&cbuf);
42132
42133#line 8867 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
42134
42135 int vlen_enc = vector_length_encoding(this);
42136 BasicType bt = Matcher::vector_element_basic_type(this);
42137 int opc = this->ideal_Opcode();
42138 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
42139 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, true, vlen_enc);
42140
42141#line 42141 "ad_x86.cpp"
42142 }
42143}
42144
42145void vadd_reg_masked_3Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42146 cbuf.set_insts_mark();
42147 // Start at oper_input_base() and count operands
42148 unsigned idx0 = 1;
42149 unsigned idx1 = 1; // dst
42150 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
42151 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
42152 {
42153 C2_MacroAssembler _masm(&cbuf);
42154
42155#line 8867 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
42156
42157 int vlen_enc = vector_length_encoding(this);
42158 BasicType bt = Matcher::vector_element_basic_type(this);
42159 int opc = this->ideal_Opcode();
42160 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
42161 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, true, vlen_enc);
42162
42163#line 42163 "ad_x86.cpp"
42164 }
42165}
42166
42167void vadd_reg_masked_4Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42168 cbuf.set_insts_mark();
42169 // Start at oper_input_base() and count operands
42170 unsigned idx0 = 1;
42171 unsigned idx1 = 1; // dst
42172 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
42173 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
42174 {
42175 C2_MacroAssembler _masm(&cbuf);
42176
42177#line 8867 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
42178
42179 int vlen_enc = vector_length_encoding(this);
42180 BasicType bt = Matcher::vector_element_basic_type(this);
42181 int opc = this->ideal_Opcode();
42182 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
42183 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, true, vlen_enc);
42184
42185#line 42185 "ad_x86.cpp"
42186 }
42187}
42188
42189void vadd_mem_maskedNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42190 cbuf.set_insts_mark();
42191 // Start at oper_input_base() and count operands
42192 unsigned idx0 = 2;
42193 unsigned idx1 = 2; // dst
42194 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
42195 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
42196 {
42197 C2_MacroAssembler _masm(&cbuf);
42198
42199#line 8885 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
42200
42201 int vlen_enc = vector_length_encoding(this);
42202 BasicType bt = Matcher::vector_element_basic_type(this);
42203 int opc = this->ideal_Opcode();
42204 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
42205 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), true, vlen_enc);
42206
42207#line 42207 "ad_x86.cpp"
42208 }
42209}
42210
42211void vadd_mem_masked_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42212 cbuf.set_insts_mark();
42213 // Start at oper_input_base() and count operands
42214 unsigned idx0 = 2;
42215 unsigned idx1 = 2; // dst
42216 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
42217 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
42218 {
42219 C2_MacroAssembler _masm(&cbuf);
42220
42221#line 8885 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
42222
42223 int vlen_enc = vector_length_encoding(this);
42224 BasicType bt = Matcher::vector_element_basic_type(this);
42225 int opc = this->ideal_Opcode();
42226 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
42227 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), true, vlen_enc);
42228
42229#line 42229 "ad_x86.cpp"
42230 }
42231}
42232
42233void vadd_mem_masked_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42234 cbuf.set_insts_mark();
42235 // Start at oper_input_base() and count operands
42236 unsigned idx0 = 2;
42237 unsigned idx1 = 2; // dst
42238 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
42239 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
42240 {
42241 C2_MacroAssembler _masm(&cbuf);
42242
42243#line 8885 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
42244
42245 int vlen_enc = vector_length_encoding(this);
42246 BasicType bt = Matcher::vector_element_basic_type(this);
42247 int opc = this->ideal_Opcode();
42248 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
42249 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), true, vlen_enc);
42250
42251#line 42251 "ad_x86.cpp"
42252 }
42253}
42254
42255void vadd_mem_masked_2Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42256 cbuf.set_insts_mark();
42257 // Start at oper_input_base() and count operands
42258 unsigned idx0 = 2;
42259 unsigned idx1 = 2; // dst
42260 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
42261 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
42262 {
42263 C2_MacroAssembler _masm(&cbuf);
42264
42265#line 8885 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
42266
42267 int vlen_enc = vector_length_encoding(this);
42268 BasicType bt = Matcher::vector_element_basic_type(this);
42269 int opc = this->ideal_Opcode();
42270 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
42271 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), true, vlen_enc);
42272
42273#line 42273 "ad_x86.cpp"
42274 }
42275}
42276
42277void vadd_mem_masked_3Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42278 cbuf.set_insts_mark();
42279 // Start at oper_input_base() and count operands
42280 unsigned idx0 = 2;
42281 unsigned idx1 = 2; // dst
42282 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
42283 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
42284 {
42285 C2_MacroAssembler _masm(&cbuf);
42286
42287#line 8885 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
42288
42289 int vlen_enc = vector_length_encoding(this);
42290 BasicType bt = Matcher::vector_element_basic_type(this);
42291 int opc = this->ideal_Opcode();
42292 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
42293 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), true, vlen_enc);
42294
42295#line 42295 "ad_x86.cpp"
42296 }
42297}
42298
42299void vadd_mem_masked_4Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42300 cbuf.set_insts_mark();
42301 // Start at oper_input_base() and count operands
42302 unsigned idx0 = 2;
42303 unsigned idx1 = 2; // dst
42304 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
42305 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
42306 {
42307 C2_MacroAssembler _masm(&cbuf);
42308
42309#line 8885 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
42310
42311 int vlen_enc = vector_length_encoding(this);
42312 BasicType bt = Matcher::vector_element_basic_type(this);
42313 int opc = this->ideal_Opcode();
42314 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
42315 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), true, vlen_enc);
42316
42317#line 42317 "ad_x86.cpp"
42318 }
42319}
42320
42321void vxor_reg_maskedNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42322 cbuf.set_insts_mark();
42323 // Start at oper_input_base() and count operands
42324 unsigned idx0 = 1;
42325 unsigned idx1 = 1; // dst
42326 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
42327 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
42328 {
42329 C2_MacroAssembler _masm(&cbuf);
42330
42331#line 8898 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
42332
42333 int vlen_enc = vector_length_encoding(this);
42334 BasicType bt = Matcher::vector_element_basic_type(this);
42335 int opc = this->ideal_Opcode();
42336 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
42337 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, true, vlen_enc);
42338
42339#line 42339 "ad_x86.cpp"
42340 }
42341}
42342
42343void vxor_mem_maskedNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42344 cbuf.set_insts_mark();
42345 // Start at oper_input_base() and count operands
42346 unsigned idx0 = 2;
42347 unsigned idx1 = 2; // dst
42348 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
42349 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
42350 {
42351 C2_MacroAssembler _masm(&cbuf);
42352
42353#line 8911 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
42354
42355 int vlen_enc = vector_length_encoding(this);
42356 BasicType bt = Matcher::vector_element_basic_type(this);
42357 int opc = this->ideal_Opcode();
42358 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
42359 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), true, vlen_enc);
42360
42361#line 42361 "ad_x86.cpp"
42362 }
42363}
42364
42365void vor_reg_maskedNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42366 cbuf.set_insts_mark();
42367 // Start at oper_input_base() and count operands
42368 unsigned idx0 = 1;
42369 unsigned idx1 = 1; // dst
42370 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
42371 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
42372 {
42373 C2_MacroAssembler _masm(&cbuf);
42374
42375#line 8924 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
42376
42377 int vlen_enc = vector_length_encoding(this);
42378 BasicType bt = Matcher::vector_element_basic_type(this);
42379 int opc = this->ideal_Opcode();
42380 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
42381 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, true, vlen_enc);
42382
42383#line 42383 "ad_x86.cpp"
42384 }
42385}
42386
42387void vor_mem_maskedNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42388 cbuf.set_insts_mark();
42389 // Start at oper_input_base() and count operands
42390 unsigned idx0 = 2;
42391 unsigned idx1 = 2; // dst
42392 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
42393 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
42394 {
42395 C2_MacroAssembler _masm(&cbuf);
42396
42397#line 8937 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
42398
42399 int vlen_enc = vector_length_encoding(this);
42400 BasicType bt = Matcher::vector_element_basic_type(this);
42401 int opc = this->ideal_Opcode();
42402 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
42403 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), true, vlen_enc);
42404
42405#line 42405 "ad_x86.cpp"
42406 }
42407}
42408
42409void vand_reg_maskedNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42410 cbuf.set_insts_mark();
42411 // Start at oper_input_base() and count operands
42412 unsigned idx0 = 1;
42413 unsigned idx1 = 1; // dst
42414 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
42415 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
42416 {
42417 C2_MacroAssembler _masm(&cbuf);
42418
42419#line 8950 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
42420
42421 int vlen_enc = vector_length_encoding(this);
42422 BasicType bt = Matcher::vector_element_basic_type(this);
42423 int opc = this->ideal_Opcode();
42424 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
42425 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, true, vlen_enc);
42426
42427#line 42427 "ad_x86.cpp"
42428 }
42429}
42430
42431void vand_mem_maskedNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42432 cbuf.set_insts_mark();
42433 // Start at oper_input_base() and count operands
42434 unsigned idx0 = 2;
42435 unsigned idx1 = 2; // dst
42436 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
42437 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
42438 {
42439 C2_MacroAssembler _masm(&cbuf);
42440
42441#line 8963 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
42442
42443 int vlen_enc = vector_length_encoding(this);
42444 BasicType bt = Matcher::vector_element_basic_type(this);
42445 int opc = this->ideal_Opcode();
42446 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
42447 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), true, vlen_enc);
42448
42449#line 42449 "ad_x86.cpp"
42450 }
42451}
42452
42453void vsub_reg_maskedNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42454 cbuf.set_insts_mark();
42455 // Start at oper_input_base() and count operands
42456 unsigned idx0 = 1;
42457 unsigned idx1 = 1; // dst
42458 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
42459 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
42460 {
42461 C2_MacroAssembler _masm(&cbuf);
42462
42463#line 8981 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
42464
42465 int vlen_enc = vector_length_encoding(this);
42466 BasicType bt = Matcher::vector_element_basic_type(this);
42467 int opc = this->ideal_Opcode();
42468 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
42469 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, true, vlen_enc);
42470
42471#line 42471 "ad_x86.cpp"
42472 }
42473}
42474
42475void vsub_reg_masked_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42476 cbuf.set_insts_mark();
42477 // Start at oper_input_base() and count operands
42478 unsigned idx0 = 1;
42479 unsigned idx1 = 1; // dst
42480 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
42481 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
42482 {
42483 C2_MacroAssembler _masm(&cbuf);
42484
42485#line 8981 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
42486
42487 int vlen_enc = vector_length_encoding(this);
42488 BasicType bt = Matcher::vector_element_basic_type(this);
42489 int opc = this->ideal_Opcode();
42490 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
42491 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, true, vlen_enc);
42492
42493#line 42493 "ad_x86.cpp"
42494 }
42495}
42496
42497void vsub_reg_masked_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42498 cbuf.set_insts_mark();
42499 // Start at oper_input_base() and count operands
42500 unsigned idx0 = 1;
42501 unsigned idx1 = 1; // dst
42502 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
42503 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
42504 {
42505 C2_MacroAssembler _masm(&cbuf);
42506
42507#line 8981 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
42508
42509 int vlen_enc = vector_length_encoding(this);
42510 BasicType bt = Matcher::vector_element_basic_type(this);
42511 int opc = this->ideal_Opcode();
42512 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
42513 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, true, vlen_enc);
42514
42515#line 42515 "ad_x86.cpp"
42516 }
42517}
42518
42519void vsub_reg_masked_2Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42520 cbuf.set_insts_mark();
42521 // Start at oper_input_base() and count operands
42522 unsigned idx0 = 1;
42523 unsigned idx1 = 1; // dst
42524 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
42525 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
42526 {
42527 C2_MacroAssembler _masm(&cbuf);
42528
42529#line 8981 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
42530
42531 int vlen_enc = vector_length_encoding(this);
42532 BasicType bt = Matcher::vector_element_basic_type(this);
42533 int opc = this->ideal_Opcode();
42534 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
42535 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, true, vlen_enc);
42536
42537#line 42537 "ad_x86.cpp"
42538 }
42539}
42540
42541void vsub_reg_masked_3Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42542 cbuf.set_insts_mark();
42543 // Start at oper_input_base() and count operands
42544 unsigned idx0 = 1;
42545 unsigned idx1 = 1; // dst
42546 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
42547 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
42548 {
42549 C2_MacroAssembler _masm(&cbuf);
42550
42551#line 8981 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
42552
42553 int vlen_enc = vector_length_encoding(this);
42554 BasicType bt = Matcher::vector_element_basic_type(this);
42555 int opc = this->ideal_Opcode();
42556 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
42557 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, true, vlen_enc);
42558
42559#line 42559 "ad_x86.cpp"
42560 }
42561}
42562
42563void vsub_reg_masked_4Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42564 cbuf.set_insts_mark();
42565 // Start at oper_input_base() and count operands
42566 unsigned idx0 = 1;
42567 unsigned idx1 = 1; // dst
42568 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
42569 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
42570 {
42571 C2_MacroAssembler _masm(&cbuf);
42572
42573#line 8981 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
42574
42575 int vlen_enc = vector_length_encoding(this);
42576 BasicType bt = Matcher::vector_element_basic_type(this);
42577 int opc = this->ideal_Opcode();
42578 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
42579 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, true, vlen_enc);
42580
42581#line 42581 "ad_x86.cpp"
42582 }
42583}
42584
42585void vsub_mem_maskedNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42586 cbuf.set_insts_mark();
42587 // Start at oper_input_base() and count operands
42588 unsigned idx0 = 2;
42589 unsigned idx1 = 2; // dst
42590 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
42591 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
42592 {
42593 C2_MacroAssembler _masm(&cbuf);
42594
42595#line 8999 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
42596
42597 int vlen_enc = vector_length_encoding(this);
42598 BasicType bt = Matcher::vector_element_basic_type(this);
42599 int opc = this->ideal_Opcode();
42600 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
42601 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), true, vlen_enc);
42602
42603#line 42603 "ad_x86.cpp"
42604 }
42605}
42606
42607void vsub_mem_masked_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42608 cbuf.set_insts_mark();
42609 // Start at oper_input_base() and count operands
42610 unsigned idx0 = 2;
42611 unsigned idx1 = 2; // dst
42612 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
42613 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
42614 {
42615 C2_MacroAssembler _masm(&cbuf);
42616
42617#line 8999 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
42618
42619 int vlen_enc = vector_length_encoding(this);
42620 BasicType bt = Matcher::vector_element_basic_type(this);
42621 int opc = this->ideal_Opcode();
42622 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
42623 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), true, vlen_enc);
42624
42625#line 42625 "ad_x86.cpp"
42626 }
42627}
42628
42629void vsub_mem_masked_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42630 cbuf.set_insts_mark();
42631 // Start at oper_input_base() and count operands
42632 unsigned idx0 = 2;
42633 unsigned idx1 = 2; // dst
42634 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
42635 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
42636 {
42637 C2_MacroAssembler _masm(&cbuf);
42638
42639#line 8999 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
42640
42641 int vlen_enc = vector_length_encoding(this);
42642 BasicType bt = Matcher::vector_element_basic_type(this);
42643 int opc = this->ideal_Opcode();
42644 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
42645 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), true, vlen_enc);
42646
42647#line 42647 "ad_x86.cpp"
42648 }
42649}
42650
42651void vsub_mem_masked_2Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42652 cbuf.set_insts_mark();
42653 // Start at oper_input_base() and count operands
42654 unsigned idx0 = 2;
42655 unsigned idx1 = 2; // dst
42656 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
42657 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
42658 {
42659 C2_MacroAssembler _masm(&cbuf);
42660
42661#line 8999 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
42662
42663 int vlen_enc = vector_length_encoding(this);
42664 BasicType bt = Matcher::vector_element_basic_type(this);
42665 int opc = this->ideal_Opcode();
42666 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
42667 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), true, vlen_enc);
42668
42669#line 42669 "ad_x86.cpp"
42670 }
42671}
42672
42673void vsub_mem_masked_3Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42674 cbuf.set_insts_mark();
42675 // Start at oper_input_base() and count operands
42676 unsigned idx0 = 2;
42677 unsigned idx1 = 2; // dst
42678 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
42679 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
42680 {
42681 C2_MacroAssembler _masm(&cbuf);
42682
42683#line 8999 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
42684
42685 int vlen_enc = vector_length_encoding(this);
42686 BasicType bt = Matcher::vector_element_basic_type(this);
42687 int opc = this->ideal_Opcode();
42688 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
42689 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), true, vlen_enc);
42690
42691#line 42691 "ad_x86.cpp"
42692 }
42693}
42694
42695void vsub_mem_masked_4Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42696 cbuf.set_insts_mark();
42697 // Start at oper_input_base() and count operands
42698 unsigned idx0 = 2;
42699 unsigned idx1 = 2; // dst
42700 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
42701 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
42702 {
42703 C2_MacroAssembler _masm(&cbuf);
42704
42705#line 8999 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
42706
42707 int vlen_enc = vector_length_encoding(this);
42708 BasicType bt = Matcher::vector_element_basic_type(this);
42709 int opc = this->ideal_Opcode();
42710 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
42711 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), true, vlen_enc);
42712
42713#line 42713 "ad_x86.cpp"
42714 }
42715}
42716
42717void vmul_reg_maskedNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42718 cbuf.set_insts_mark();
42719 // Start at oper_input_base() and count operands
42720 unsigned idx0 = 1;
42721 unsigned idx1 = 1; // dst
42722 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
42723 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
42724 {
42725 C2_MacroAssembler _masm(&cbuf);
42726
42727#line 9016 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
42728
42729 int vlen_enc = vector_length_encoding(this);
42730 BasicType bt = Matcher::vector_element_basic_type(this);
42731 int opc = this->ideal_Opcode();
42732 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
42733 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, true, vlen_enc);
42734
42735#line 42735 "ad_x86.cpp"
42736 }
42737}
42738
42739void vmul_reg_masked_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42740 cbuf.set_insts_mark();
42741 // Start at oper_input_base() and count operands
42742 unsigned idx0 = 1;
42743 unsigned idx1 = 1; // dst
42744 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
42745 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
42746 {
42747 C2_MacroAssembler _masm(&cbuf);
42748
42749#line 9016 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
42750
42751 int vlen_enc = vector_length_encoding(this);
42752 BasicType bt = Matcher::vector_element_basic_type(this);
42753 int opc = this->ideal_Opcode();
42754 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
42755 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, true, vlen_enc);
42756
42757#line 42757 "ad_x86.cpp"
42758 }
42759}
42760
42761void vmul_reg_masked_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42762 cbuf.set_insts_mark();
42763 // Start at oper_input_base() and count operands
42764 unsigned idx0 = 1;
42765 unsigned idx1 = 1; // dst
42766 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
42767 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
42768 {
42769 C2_MacroAssembler _masm(&cbuf);
42770
42771#line 9016 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
42772
42773 int vlen_enc = vector_length_encoding(this);
42774 BasicType bt = Matcher::vector_element_basic_type(this);
42775 int opc = this->ideal_Opcode();
42776 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
42777 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, true, vlen_enc);
42778
42779#line 42779 "ad_x86.cpp"
42780 }
42781}
42782
42783void vmul_reg_masked_2Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42784 cbuf.set_insts_mark();
42785 // Start at oper_input_base() and count operands
42786 unsigned idx0 = 1;
42787 unsigned idx1 = 1; // dst
42788 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
42789 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
42790 {
42791 C2_MacroAssembler _masm(&cbuf);
42792
42793#line 9016 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
42794
42795 int vlen_enc = vector_length_encoding(this);
42796 BasicType bt = Matcher::vector_element_basic_type(this);
42797 int opc = this->ideal_Opcode();
42798 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
42799 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, true, vlen_enc);
42800
42801#line 42801 "ad_x86.cpp"
42802 }
42803}
42804
42805void vmul_reg_masked_3Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42806 cbuf.set_insts_mark();
42807 // Start at oper_input_base() and count operands
42808 unsigned idx0 = 1;
42809 unsigned idx1 = 1; // dst
42810 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
42811 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
42812 {
42813 C2_MacroAssembler _masm(&cbuf);
42814
42815#line 9016 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
42816
42817 int vlen_enc = vector_length_encoding(this);
42818 BasicType bt = Matcher::vector_element_basic_type(this);
42819 int opc = this->ideal_Opcode();
42820 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
42821 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, true, vlen_enc);
42822
42823#line 42823 "ad_x86.cpp"
42824 }
42825}
42826
42827void vmul_mem_maskedNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42828 cbuf.set_insts_mark();
42829 // Start at oper_input_base() and count operands
42830 unsigned idx0 = 2;
42831 unsigned idx1 = 2; // dst
42832 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
42833 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
42834 {
42835 C2_MacroAssembler _masm(&cbuf);
42836
42837#line 9033 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
42838
42839 int vlen_enc = vector_length_encoding(this);
42840 BasicType bt = Matcher::vector_element_basic_type(this);
42841 int opc = this->ideal_Opcode();
42842 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
42843 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), true, vlen_enc);
42844
42845#line 42845 "ad_x86.cpp"
42846 }
42847}
42848
42849void vmul_mem_masked_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42850 cbuf.set_insts_mark();
42851 // Start at oper_input_base() and count operands
42852 unsigned idx0 = 2;
42853 unsigned idx1 = 2; // dst
42854 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
42855 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
42856 {
42857 C2_MacroAssembler _masm(&cbuf);
42858
42859#line 9033 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
42860
42861 int vlen_enc = vector_length_encoding(this);
42862 BasicType bt = Matcher::vector_element_basic_type(this);
42863 int opc = this->ideal_Opcode();
42864 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
42865 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), true, vlen_enc);
42866
42867#line 42867 "ad_x86.cpp"
42868 }
42869}
42870
42871void vmul_mem_masked_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42872 cbuf.set_insts_mark();
42873 // Start at oper_input_base() and count operands
42874 unsigned idx0 = 2;
42875 unsigned idx1 = 2; // dst
42876 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
42877 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
42878 {
42879 C2_MacroAssembler _masm(&cbuf);
42880
42881#line 9033 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
42882
42883 int vlen_enc = vector_length_encoding(this);
42884 BasicType bt = Matcher::vector_element_basic_type(this);
42885 int opc = this->ideal_Opcode();
42886 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
42887 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), true, vlen_enc);
42888
42889#line 42889 "ad_x86.cpp"
42890 }
42891}
42892
42893void vmul_mem_masked_2Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42894 cbuf.set_insts_mark();
42895 // Start at oper_input_base() and count operands
42896 unsigned idx0 = 2;
42897 unsigned idx1 = 2; // dst
42898 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
42899 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
42900 {
42901 C2_MacroAssembler _masm(&cbuf);
42902
42903#line 9033 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
42904
42905 int vlen_enc = vector_length_encoding(this);
42906 BasicType bt = Matcher::vector_element_basic_type(this);
42907 int opc = this->ideal_Opcode();
42908 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
42909 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), true, vlen_enc);
42910
42911#line 42911 "ad_x86.cpp"
42912 }
42913}
42914
42915void vmul_mem_masked_3Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42916 cbuf.set_insts_mark();
42917 // Start at oper_input_base() and count operands
42918 unsigned idx0 = 2;
42919 unsigned idx1 = 2; // dst
42920 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
42921 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
42922 {
42923 C2_MacroAssembler _masm(&cbuf);
42924
42925#line 9033 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
42926
42927 int vlen_enc = vector_length_encoding(this);
42928 BasicType bt = Matcher::vector_element_basic_type(this);
42929 int opc = this->ideal_Opcode();
42930 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
42931 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), true, vlen_enc);
42932
42933#line 42933 "ad_x86.cpp"
42934 }
42935}
42936
42937void vsqrt_reg_maskedNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42938 cbuf.set_insts_mark();
42939 // Start at oper_input_base() and count operands
42940 unsigned idx0 = 1;
42941 unsigned idx1 = 1; // dst
42942 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask
42943 {
42944 C2_MacroAssembler _masm(&cbuf);
42945
42946#line 9048 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
42947
42948 int vlen_enc = vector_length_encoding(this);
42949 BasicType bt = Matcher::vector_element_basic_type(this);
42950 int opc = this->ideal_Opcode();
42951 ___masm. evmasked_op(opc, bt, opnd_array(2)->as_KRegister(ra_,this,idx2)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
42952 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, true, vlen_enc);
42953
42954#line 42954 "ad_x86.cpp"
42955 }
42956}
42957
42958void vsqrt_reg_masked_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42959 cbuf.set_insts_mark();
42960 // Start at oper_input_base() and count operands
42961 unsigned idx0 = 1;
42962 unsigned idx1 = 1; // dst
42963 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask
42964 {
42965 C2_MacroAssembler _masm(&cbuf);
42966
42967#line 9048 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
42968
42969 int vlen_enc = vector_length_encoding(this);
42970 BasicType bt = Matcher::vector_element_basic_type(this);
42971 int opc = this->ideal_Opcode();
42972 ___masm. evmasked_op(opc, bt, opnd_array(2)->as_KRegister(ra_,this,idx2)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
42973 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, true, vlen_enc);
42974
42975#line 42975 "ad_x86.cpp"
42976 }
42977}
42978
42979void vdiv_reg_maskedNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
42980 cbuf.set_insts_mark();
42981 // Start at oper_input_base() and count operands
42982 unsigned idx0 = 1;
42983 unsigned idx1 = 1; // dst
42984 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
42985 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
42986 {
42987 C2_MacroAssembler _masm(&cbuf);
42988
42989#line 9062 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
42990
42991 int vlen_enc = vector_length_encoding(this);
42992 BasicType bt = Matcher::vector_element_basic_type(this);
42993 int opc = this->ideal_Opcode();
42994 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
42995 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, true, vlen_enc);
42996
42997#line 42997 "ad_x86.cpp"
42998 }
42999}
43000
43001void vdiv_reg_masked_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43002 cbuf.set_insts_mark();
43003 // Start at oper_input_base() and count operands
43004 unsigned idx0 = 1;
43005 unsigned idx1 = 1; // dst
43006 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
43007 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
43008 {
43009 C2_MacroAssembler _masm(&cbuf);
43010
43011#line 9062 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
43012
43013 int vlen_enc = vector_length_encoding(this);
43014 BasicType bt = Matcher::vector_element_basic_type(this);
43015 int opc = this->ideal_Opcode();
43016 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
43017 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, true, vlen_enc);
43018
43019#line 43019 "ad_x86.cpp"
43020 }
43021}
43022
43023void vdiv_mem_maskedNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43024 cbuf.set_insts_mark();
43025 // Start at oper_input_base() and count operands
43026 unsigned idx0 = 2;
43027 unsigned idx1 = 2; // dst
43028 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
43029 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
43030 {
43031 C2_MacroAssembler _masm(&cbuf);
43032
43033#line 9076 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
43034
43035 int vlen_enc = vector_length_encoding(this);
43036 BasicType bt = Matcher::vector_element_basic_type(this);
43037 int opc = this->ideal_Opcode();
43038 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
43039 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), true, vlen_enc);
43040
43041#line 43041 "ad_x86.cpp"
43042 }
43043}
43044
43045void vdiv_mem_masked_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43046 cbuf.set_insts_mark();
43047 // Start at oper_input_base() and count operands
43048 unsigned idx0 = 2;
43049 unsigned idx1 = 2; // dst
43050 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
43051 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
43052 {
43053 C2_MacroAssembler _masm(&cbuf);
43054
43055#line 9076 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
43056
43057 int vlen_enc = vector_length_encoding(this);
43058 BasicType bt = Matcher::vector_element_basic_type(this);
43059 int opc = this->ideal_Opcode();
43060 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
43061 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), true, vlen_enc);
43062
43063#line 43063 "ad_x86.cpp"
43064 }
43065}
43066
43067void vrol_imm_maskedNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43068 cbuf.set_insts_mark();
43069 // Start at oper_input_base() and count operands
43070 unsigned idx0 = 1;
43071 unsigned idx1 = 1; // dst
43072 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
43073 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
43074 {
43075 C2_MacroAssembler _masm(&cbuf);
43076
43077#line 9091 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
43078
43079 int vlen_enc = vector_length_encoding(this);
43080 BasicType bt = Matcher::vector_element_basic_type(this);
43081 int opc = this->ideal_Opcode();
43082 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
43083 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->constant(), true, vlen_enc);
43084
43085#line 43085 "ad_x86.cpp"
43086 }
43087}
43088
43089void vrol_imm_masked_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43090 cbuf.set_insts_mark();
43091 // Start at oper_input_base() and count operands
43092 unsigned idx0 = 1;
43093 unsigned idx1 = 1; // dst
43094 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
43095 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
43096 {
43097 C2_MacroAssembler _masm(&cbuf);
43098
43099#line 9091 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
43100
43101 int vlen_enc = vector_length_encoding(this);
43102 BasicType bt = Matcher::vector_element_basic_type(this);
43103 int opc = this->ideal_Opcode();
43104 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
43105 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->constant(), true, vlen_enc);
43106
43107#line 43107 "ad_x86.cpp"
43108 }
43109}
43110
43111void vrol_reg_maskedNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43112 cbuf.set_insts_mark();
43113 // Start at oper_input_base() and count operands
43114 unsigned idx0 = 1;
43115 unsigned idx1 = 1; // dst
43116 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
43117 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
43118 {
43119 C2_MacroAssembler _masm(&cbuf);
43120
43121#line 9105 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
43122
43123 int vlen_enc = vector_length_encoding(this);
43124 BasicType bt = Matcher::vector_element_basic_type(this);
43125 int opc = this->ideal_Opcode();
43126 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
43127 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, true, vlen_enc);
43128
43129#line 43129 "ad_x86.cpp"
43130 }
43131}
43132
43133void vrol_reg_masked_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43134 cbuf.set_insts_mark();
43135 // Start at oper_input_base() and count operands
43136 unsigned idx0 = 1;
43137 unsigned idx1 = 1; // dst
43138 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
43139 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
43140 {
43141 C2_MacroAssembler _masm(&cbuf);
43142
43143#line 9105 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
43144
43145 int vlen_enc = vector_length_encoding(this);
43146 BasicType bt = Matcher::vector_element_basic_type(this);
43147 int opc = this->ideal_Opcode();
43148 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
43149 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, true, vlen_enc);
43150
43151#line 43151 "ad_x86.cpp"
43152 }
43153}
43154
43155void vlshift_imm_maskedNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43156 cbuf.set_insts_mark();
43157 // Start at oper_input_base() and count operands
43158 unsigned idx0 = 1;
43159 unsigned idx1 = 1; // dst
43160 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
43161 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
43162 {
43163 C2_MacroAssembler _masm(&cbuf);
43164
43165#line 9120 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
43166
43167 int vlen_enc = vector_length_encoding(this);
43168 BasicType bt = Matcher::vector_element_basic_type(this);
43169 int opc = this->ideal_Opcode();
43170 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
43171 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->constant(), true, vlen_enc);
43172
43173#line 43173 "ad_x86.cpp"
43174 }
43175}
43176
43177void vlshift_imm_masked_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43178 cbuf.set_insts_mark();
43179 // Start at oper_input_base() and count operands
43180 unsigned idx0 = 1;
43181 unsigned idx1 = 1; // dst
43182 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
43183 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
43184 {
43185 C2_MacroAssembler _masm(&cbuf);
43186
43187#line 9120 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
43188
43189 int vlen_enc = vector_length_encoding(this);
43190 BasicType bt = Matcher::vector_element_basic_type(this);
43191 int opc = this->ideal_Opcode();
43192 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
43193 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->constant(), true, vlen_enc);
43194
43195#line 43195 "ad_x86.cpp"
43196 }
43197}
43198
43199void vlshift_imm_masked_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43200 cbuf.set_insts_mark();
43201 // Start at oper_input_base() and count operands
43202 unsigned idx0 = 1;
43203 unsigned idx1 = 1; // dst
43204 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
43205 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
43206 {
43207 C2_MacroAssembler _masm(&cbuf);
43208
43209#line 9120 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
43210
43211 int vlen_enc = vector_length_encoding(this);
43212 BasicType bt = Matcher::vector_element_basic_type(this);
43213 int opc = this->ideal_Opcode();
43214 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
43215 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->constant(), true, vlen_enc);
43216
43217#line 43217 "ad_x86.cpp"
43218 }
43219}
43220
43221void vlshift_reg_maskedNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43222 cbuf.set_insts_mark();
43223 // Start at oper_input_base() and count operands
43224 unsigned idx0 = 1;
43225 unsigned idx1 = 1; // dst
43226 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
43227 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
43228 {
43229 C2_MacroAssembler _masm(&cbuf);
43230
43231#line 9136 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
43232
43233 int vlen_enc = vector_length_encoding(this);
43234 BasicType bt = Matcher::vector_element_basic_type(this);
43235 int opc = this->ideal_Opcode();
43236 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
43237 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, true, vlen_enc, false);
43238
43239#line 43239 "ad_x86.cpp"
43240 }
43241}
43242
43243void vlshift_reg_masked_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43244 cbuf.set_insts_mark();
43245 // Start at oper_input_base() and count operands
43246 unsigned idx0 = 1;
43247 unsigned idx1 = 1; // dst
43248 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
43249 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
43250 {
43251 C2_MacroAssembler _masm(&cbuf);
43252
43253#line 9136 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
43254
43255 int vlen_enc = vector_length_encoding(this);
43256 BasicType bt = Matcher::vector_element_basic_type(this);
43257 int opc = this->ideal_Opcode();
43258 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
43259 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, true, vlen_enc, false);
43260
43261#line 43261 "ad_x86.cpp"
43262 }
43263}
43264
43265void vlshift_reg_masked_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43266 cbuf.set_insts_mark();
43267 // Start at oper_input_base() and count operands
43268 unsigned idx0 = 1;
43269 unsigned idx1 = 1; // dst
43270 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
43271 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
43272 {
43273 C2_MacroAssembler _masm(&cbuf);
43274
43275#line 9136 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
43276
43277 int vlen_enc = vector_length_encoding(this);
43278 BasicType bt = Matcher::vector_element_basic_type(this);
43279 int opc = this->ideal_Opcode();
43280 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
43281 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, true, vlen_enc, false);
43282
43283#line 43283 "ad_x86.cpp"
43284 }
43285}
43286
43287void vlshiftv_reg_maskedNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43288 cbuf.set_insts_mark();
43289 // Start at oper_input_base() and count operands
43290 unsigned idx0 = 1;
43291 unsigned idx1 = 1; // dst
43292 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
43293 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
43294 {
43295 C2_MacroAssembler _masm(&cbuf);
43296
43297#line 9152 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
43298
43299 int vlen_enc = vector_length_encoding(this);
43300 BasicType bt = Matcher::vector_element_basic_type(this);
43301 int opc = this->ideal_Opcode();
43302 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
43303 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, true, vlen_enc, true);
43304
43305#line 43305 "ad_x86.cpp"
43306 }
43307}
43308
43309void vlshiftv_reg_masked_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43310 cbuf.set_insts_mark();
43311 // Start at oper_input_base() and count operands
43312 unsigned idx0 = 1;
43313 unsigned idx1 = 1; // dst
43314 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
43315 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
43316 {
43317 C2_MacroAssembler _masm(&cbuf);
43318
43319#line 9152 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
43320
43321 int vlen_enc = vector_length_encoding(this);
43322 BasicType bt = Matcher::vector_element_basic_type(this);
43323 int opc = this->ideal_Opcode();
43324 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
43325 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, true, vlen_enc, true);
43326
43327#line 43327 "ad_x86.cpp"
43328 }
43329}
43330
43331void vlshiftv_reg_masked_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43332 cbuf.set_insts_mark();
43333 // Start at oper_input_base() and count operands
43334 unsigned idx0 = 1;
43335 unsigned idx1 = 1; // dst
43336 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
43337 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
43338 {
43339 C2_MacroAssembler _masm(&cbuf);
43340
43341#line 9152 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
43342
43343 int vlen_enc = vector_length_encoding(this);
43344 BasicType bt = Matcher::vector_element_basic_type(this);
43345 int opc = this->ideal_Opcode();
43346 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
43347 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, true, vlen_enc, true);
43348
43349#line 43349 "ad_x86.cpp"
43350 }
43351}
43352
43353void vlshift_mem_maskedNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43354 cbuf.set_insts_mark();
43355 // Start at oper_input_base() and count operands
43356 unsigned idx0 = 2;
43357 unsigned idx1 = 2; // dst
43358 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
43359 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
43360 {
43361 C2_MacroAssembler _masm(&cbuf);
43362
43363#line 9167 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
43364
43365 int vlen_enc = vector_length_encoding(this);
43366 BasicType bt = Matcher::vector_element_basic_type(this);
43367 int opc = this->ideal_Opcode();
43368 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
43369 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), true, vlen_enc);
43370
43371#line 43371 "ad_x86.cpp"
43372 }
43373}
43374
43375void vlshift_mem_masked_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43376 cbuf.set_insts_mark();
43377 // Start at oper_input_base() and count operands
43378 unsigned idx0 = 2;
43379 unsigned idx1 = 2; // dst
43380 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
43381 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
43382 {
43383 C2_MacroAssembler _masm(&cbuf);
43384
43385#line 9167 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
43386
43387 int vlen_enc = vector_length_encoding(this);
43388 BasicType bt = Matcher::vector_element_basic_type(this);
43389 int opc = this->ideal_Opcode();
43390 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
43391 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), true, vlen_enc);
43392
43393#line 43393 "ad_x86.cpp"
43394 }
43395}
43396
43397void vlshift_mem_masked_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43398 cbuf.set_insts_mark();
43399 // Start at oper_input_base() and count operands
43400 unsigned idx0 = 2;
43401 unsigned idx1 = 2; // dst
43402 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
43403 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
43404 {
43405 C2_MacroAssembler _masm(&cbuf);
43406
43407#line 9167 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
43408
43409 int vlen_enc = vector_length_encoding(this);
43410 BasicType bt = Matcher::vector_element_basic_type(this);
43411 int opc = this->ideal_Opcode();
43412 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
43413 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), true, vlen_enc);
43414
43415#line 43415 "ad_x86.cpp"
43416 }
43417}
43418
43419void vrshift_imm_maskedNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43420 cbuf.set_insts_mark();
43421 // Start at oper_input_base() and count operands
43422 unsigned idx0 = 1;
43423 unsigned idx1 = 1; // dst
43424 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
43425 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
43426 {
43427 C2_MacroAssembler _masm(&cbuf);
43428
43429#line 9182 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
43430
43431 int vlen_enc = vector_length_encoding(this);
43432 BasicType bt = Matcher::vector_element_basic_type(this);
43433 int opc = this->ideal_Opcode();
43434 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
43435 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->constant(), true, vlen_enc);
43436
43437#line 43437 "ad_x86.cpp"
43438 }
43439}
43440
43441void vrshift_imm_masked_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43442 cbuf.set_insts_mark();
43443 // Start at oper_input_base() and count operands
43444 unsigned idx0 = 1;
43445 unsigned idx1 = 1; // dst
43446 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
43447 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
43448 {
43449 C2_MacroAssembler _masm(&cbuf);
43450
43451#line 9182 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
43452
43453 int vlen_enc = vector_length_encoding(this);
43454 BasicType bt = Matcher::vector_element_basic_type(this);
43455 int opc = this->ideal_Opcode();
43456 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
43457 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->constant(), true, vlen_enc);
43458
43459#line 43459 "ad_x86.cpp"
43460 }
43461}
43462
43463void vrshift_imm_masked_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43464 cbuf.set_insts_mark();
43465 // Start at oper_input_base() and count operands
43466 unsigned idx0 = 1;
43467 unsigned idx1 = 1; // dst
43468 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
43469 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
43470 {
43471 C2_MacroAssembler _masm(&cbuf);
43472
43473#line 9182 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
43474
43475 int vlen_enc = vector_length_encoding(this);
43476 BasicType bt = Matcher::vector_element_basic_type(this);
43477 int opc = this->ideal_Opcode();
43478 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
43479 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->constant(), true, vlen_enc);
43480
43481#line 43481 "ad_x86.cpp"
43482 }
43483}
43484
43485void vrshift_reg_maskedNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43486 cbuf.set_insts_mark();
43487 // Start at oper_input_base() and count operands
43488 unsigned idx0 = 1;
43489 unsigned idx1 = 1; // dst
43490 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
43491 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
43492 {
43493 C2_MacroAssembler _masm(&cbuf);
43494
43495#line 9198 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
43496
43497 int vlen_enc = vector_length_encoding(this);
43498 BasicType bt = Matcher::vector_element_basic_type(this);
43499 int opc = this->ideal_Opcode();
43500 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
43501 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, true, vlen_enc, false);
43502
43503#line 43503 "ad_x86.cpp"
43504 }
43505}
43506
43507void vrshift_reg_masked_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43508 cbuf.set_insts_mark();
43509 // Start at oper_input_base() and count operands
43510 unsigned idx0 = 1;
43511 unsigned idx1 = 1; // dst
43512 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
43513 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
43514 {
43515 C2_MacroAssembler _masm(&cbuf);
43516
43517#line 9198 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
43518
43519 int vlen_enc = vector_length_encoding(this);
43520 BasicType bt = Matcher::vector_element_basic_type(this);
43521 int opc = this->ideal_Opcode();
43522 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
43523 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, true, vlen_enc, false);
43524
43525#line 43525 "ad_x86.cpp"
43526 }
43527}
43528
43529void vrshift_reg_masked_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43530 cbuf.set_insts_mark();
43531 // Start at oper_input_base() and count operands
43532 unsigned idx0 = 1;
43533 unsigned idx1 = 1; // dst
43534 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
43535 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
43536 {
43537 C2_MacroAssembler _masm(&cbuf);
43538
43539#line 9198 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
43540
43541 int vlen_enc = vector_length_encoding(this);
43542 BasicType bt = Matcher::vector_element_basic_type(this);
43543 int opc = this->ideal_Opcode();
43544 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
43545 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, true, vlen_enc, false);
43546
43547#line 43547 "ad_x86.cpp"
43548 }
43549}
43550
43551void vrshiftv_reg_maskedNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43552 cbuf.set_insts_mark();
43553 // Start at oper_input_base() and count operands
43554 unsigned idx0 = 1;
43555 unsigned idx1 = 1; // dst
43556 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
43557 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
43558 {
43559 C2_MacroAssembler _masm(&cbuf);
43560
43561#line 9214 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
43562
43563 int vlen_enc = vector_length_encoding(this);
43564 BasicType bt = Matcher::vector_element_basic_type(this);
43565 int opc = this->ideal_Opcode();
43566 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
43567 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, true, vlen_enc, true);
43568
43569#line 43569 "ad_x86.cpp"
43570 }
43571}
43572
43573void vrshiftv_reg_masked_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43574 cbuf.set_insts_mark();
43575 // Start at oper_input_base() and count operands
43576 unsigned idx0 = 1;
43577 unsigned idx1 = 1; // dst
43578 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
43579 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
43580 {
43581 C2_MacroAssembler _masm(&cbuf);
43582
43583#line 9214 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
43584
43585 int vlen_enc = vector_length_encoding(this);
43586 BasicType bt = Matcher::vector_element_basic_type(this);
43587 int opc = this->ideal_Opcode();
43588 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
43589 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, true, vlen_enc, true);
43590
43591#line 43591 "ad_x86.cpp"
43592 }
43593}
43594
43595void vrshiftv_reg_masked_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43596 cbuf.set_insts_mark();
43597 // Start at oper_input_base() and count operands
43598 unsigned idx0 = 1;
43599 unsigned idx1 = 1; // dst
43600 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
43601 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
43602 {
43603 C2_MacroAssembler _masm(&cbuf);
43604
43605#line 9214 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
43606
43607 int vlen_enc = vector_length_encoding(this);
43608 BasicType bt = Matcher::vector_element_basic_type(this);
43609 int opc = this->ideal_Opcode();
43610 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
43611 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, true, vlen_enc, true);
43612
43613#line 43613 "ad_x86.cpp"
43614 }
43615}
43616
43617void vrshift_mem_maskedNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43618 cbuf.set_insts_mark();
43619 // Start at oper_input_base() and count operands
43620 unsigned idx0 = 2;
43621 unsigned idx1 = 2; // dst
43622 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
43623 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
43624 {
43625 C2_MacroAssembler _masm(&cbuf);
43626
43627#line 9229 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
43628
43629 int vlen_enc = vector_length_encoding(this);
43630 BasicType bt = Matcher::vector_element_basic_type(this);
43631 int opc = this->ideal_Opcode();
43632 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
43633 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), true, vlen_enc);
43634
43635#line 43635 "ad_x86.cpp"
43636 }
43637}
43638
43639void vrshift_mem_masked_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43640 cbuf.set_insts_mark();
43641 // Start at oper_input_base() and count operands
43642 unsigned idx0 = 2;
43643 unsigned idx1 = 2; // dst
43644 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
43645 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
43646 {
43647 C2_MacroAssembler _masm(&cbuf);
43648
43649#line 9229 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
43650
43651 int vlen_enc = vector_length_encoding(this);
43652 BasicType bt = Matcher::vector_element_basic_type(this);
43653 int opc = this->ideal_Opcode();
43654 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
43655 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), true, vlen_enc);
43656
43657#line 43657 "ad_x86.cpp"
43658 }
43659}
43660
43661void vrshift_mem_masked_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43662 cbuf.set_insts_mark();
43663 // Start at oper_input_base() and count operands
43664 unsigned idx0 = 2;
43665 unsigned idx1 = 2; // dst
43666 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
43667 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
43668 {
43669 C2_MacroAssembler _masm(&cbuf);
43670
43671#line 9229 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
43672
43673 int vlen_enc = vector_length_encoding(this);
43674 BasicType bt = Matcher::vector_element_basic_type(this);
43675 int opc = this->ideal_Opcode();
43676 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
43677 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), true, vlen_enc);
43678
43679#line 43679 "ad_x86.cpp"
43680 }
43681}
43682
43683void vurshift_imm_maskedNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43684 cbuf.set_insts_mark();
43685 // Start at oper_input_base() and count operands
43686 unsigned idx0 = 1;
43687 unsigned idx1 = 1; // dst
43688 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
43689 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
43690 {
43691 C2_MacroAssembler _masm(&cbuf);
43692
43693#line 9244 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
43694
43695 int vlen_enc = vector_length_encoding(this);
43696 BasicType bt = Matcher::vector_element_basic_type(this);
43697 int opc = this->ideal_Opcode();
43698 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
43699 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->constant(), true, vlen_enc);
43700
43701#line 43701 "ad_x86.cpp"
43702 }
43703}
43704
43705void vurshift_imm_masked_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43706 cbuf.set_insts_mark();
43707 // Start at oper_input_base() and count operands
43708 unsigned idx0 = 1;
43709 unsigned idx1 = 1; // dst
43710 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
43711 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
43712 {
43713 C2_MacroAssembler _masm(&cbuf);
43714
43715#line 9244 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
43716
43717 int vlen_enc = vector_length_encoding(this);
43718 BasicType bt = Matcher::vector_element_basic_type(this);
43719 int opc = this->ideal_Opcode();
43720 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
43721 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->constant(), true, vlen_enc);
43722
43723#line 43723 "ad_x86.cpp"
43724 }
43725}
43726
43727void vurshift_imm_masked_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43728 cbuf.set_insts_mark();
43729 // Start at oper_input_base() and count operands
43730 unsigned idx0 = 1;
43731 unsigned idx1 = 1; // dst
43732 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // shift
43733 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
43734 {
43735 C2_MacroAssembler _masm(&cbuf);
43736
43737#line 9244 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
43738
43739 int vlen_enc = vector_length_encoding(this);
43740 BasicType bt = Matcher::vector_element_basic_type(this);
43741 int opc = this->ideal_Opcode();
43742 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
43743 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->constant(), true, vlen_enc);
43744
43745#line 43745 "ad_x86.cpp"
43746 }
43747}
43748
43749void vurshift_reg_maskedNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43750 cbuf.set_insts_mark();
43751 // Start at oper_input_base() and count operands
43752 unsigned idx0 = 1;
43753 unsigned idx1 = 1; // dst
43754 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
43755 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
43756 {
43757 C2_MacroAssembler _masm(&cbuf);
43758
43759#line 9260 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
43760
43761 int vlen_enc = vector_length_encoding(this);
43762 BasicType bt = Matcher::vector_element_basic_type(this);
43763 int opc = this->ideal_Opcode();
43764 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
43765 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, true, vlen_enc, false);
43766
43767#line 43767 "ad_x86.cpp"
43768 }
43769}
43770
43771void vurshift_reg_masked_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43772 cbuf.set_insts_mark();
43773 // Start at oper_input_base() and count operands
43774 unsigned idx0 = 1;
43775 unsigned idx1 = 1; // dst
43776 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
43777 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
43778 {
43779 C2_MacroAssembler _masm(&cbuf);
43780
43781#line 9260 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
43782
43783 int vlen_enc = vector_length_encoding(this);
43784 BasicType bt = Matcher::vector_element_basic_type(this);
43785 int opc = this->ideal_Opcode();
43786 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
43787 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, true, vlen_enc, false);
43788
43789#line 43789 "ad_x86.cpp"
43790 }
43791}
43792
43793void vurshift_reg_masked_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43794 cbuf.set_insts_mark();
43795 // Start at oper_input_base() and count operands
43796 unsigned idx0 = 1;
43797 unsigned idx1 = 1; // dst
43798 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
43799 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
43800 {
43801 C2_MacroAssembler _masm(&cbuf);
43802
43803#line 9260 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
43804
43805 int vlen_enc = vector_length_encoding(this);
43806 BasicType bt = Matcher::vector_element_basic_type(this);
43807 int opc = this->ideal_Opcode();
43808 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
43809 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, true, vlen_enc, false);
43810
43811#line 43811 "ad_x86.cpp"
43812 }
43813}
43814
43815void vurshiftv_reg_maskedNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43816 cbuf.set_insts_mark();
43817 // Start at oper_input_base() and count operands
43818 unsigned idx0 = 1;
43819 unsigned idx1 = 1; // dst
43820 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
43821 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
43822 {
43823 C2_MacroAssembler _masm(&cbuf);
43824
43825#line 9276 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
43826
43827 int vlen_enc = vector_length_encoding(this);
43828 BasicType bt = Matcher::vector_element_basic_type(this);
43829 int opc = this->ideal_Opcode();
43830 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
43831 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, true, vlen_enc, true);
43832
43833#line 43833 "ad_x86.cpp"
43834 }
43835}
43836
43837void vurshiftv_reg_masked_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43838 cbuf.set_insts_mark();
43839 // Start at oper_input_base() and count operands
43840 unsigned idx0 = 1;
43841 unsigned idx1 = 1; // dst
43842 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
43843 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
43844 {
43845 C2_MacroAssembler _masm(&cbuf);
43846
43847#line 9276 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
43848
43849 int vlen_enc = vector_length_encoding(this);
43850 BasicType bt = Matcher::vector_element_basic_type(this);
43851 int opc = this->ideal_Opcode();
43852 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
43853 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, true, vlen_enc, true);
43854
43855#line 43855 "ad_x86.cpp"
43856 }
43857}
43858
43859void vurshiftv_reg_masked_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43860 cbuf.set_insts_mark();
43861 // Start at oper_input_base() and count operands
43862 unsigned idx0 = 1;
43863 unsigned idx1 = 1; // dst
43864 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
43865 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
43866 {
43867 C2_MacroAssembler _masm(&cbuf);
43868
43869#line 9276 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
43870
43871 int vlen_enc = vector_length_encoding(this);
43872 BasicType bt = Matcher::vector_element_basic_type(this);
43873 int opc = this->ideal_Opcode();
43874 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
43875 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, true, vlen_enc, true);
43876
43877#line 43877 "ad_x86.cpp"
43878 }
43879}
43880
43881void vurshift_mem_maskedNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43882 cbuf.set_insts_mark();
43883 // Start at oper_input_base() and count operands
43884 unsigned idx0 = 2;
43885 unsigned idx1 = 2; // dst
43886 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
43887 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
43888 {
43889 C2_MacroAssembler _masm(&cbuf);
43890
43891#line 9291 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
43892
43893 int vlen_enc = vector_length_encoding(this);
43894 BasicType bt = Matcher::vector_element_basic_type(this);
43895 int opc = this->ideal_Opcode();
43896 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
43897 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), true, vlen_enc);
43898
43899#line 43899 "ad_x86.cpp"
43900 }
43901}
43902
43903void vurshift_mem_masked_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43904 cbuf.set_insts_mark();
43905 // Start at oper_input_base() and count operands
43906 unsigned idx0 = 2;
43907 unsigned idx1 = 2; // dst
43908 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
43909 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
43910 {
43911 C2_MacroAssembler _masm(&cbuf);
43912
43913#line 9291 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
43914
43915 int vlen_enc = vector_length_encoding(this);
43916 BasicType bt = Matcher::vector_element_basic_type(this);
43917 int opc = this->ideal_Opcode();
43918 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
43919 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), true, vlen_enc);
43920
43921#line 43921 "ad_x86.cpp"
43922 }
43923}
43924
43925void vurshift_mem_masked_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43926 cbuf.set_insts_mark();
43927 // Start at oper_input_base() and count operands
43928 unsigned idx0 = 2;
43929 unsigned idx1 = 2; // dst
43930 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
43931 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
43932 {
43933 C2_MacroAssembler _masm(&cbuf);
43934
43935#line 9291 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
43936
43937 int vlen_enc = vector_length_encoding(this);
43938 BasicType bt = Matcher::vector_element_basic_type(this);
43939 int opc = this->ideal_Opcode();
43940 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
43941 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), true, vlen_enc);
43942
43943#line 43943 "ad_x86.cpp"
43944 }
43945}
43946
43947void vmaxv_reg_maskedNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43948 cbuf.set_insts_mark();
43949 // Start at oper_input_base() and count operands
43950 unsigned idx0 = 1;
43951 unsigned idx1 = 1; // dst
43952 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
43953 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
43954 {
43955 C2_MacroAssembler _masm(&cbuf);
43956
43957#line 9304 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
43958
43959 int vlen_enc = vector_length_encoding(this);
43960 BasicType bt = Matcher::vector_element_basic_type(this);
43961 int opc = this->ideal_Opcode();
43962 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
43963 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, true, vlen_enc);
43964
43965#line 43965 "ad_x86.cpp"
43966 }
43967}
43968
43969void vmaxv_mem_maskedNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43970 cbuf.set_insts_mark();
43971 // Start at oper_input_base() and count operands
43972 unsigned idx0 = 2;
43973 unsigned idx1 = 2; // dst
43974 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
43975 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
43976 {
43977 C2_MacroAssembler _masm(&cbuf);
43978
43979#line 9317 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
43980
43981 int vlen_enc = vector_length_encoding(this);
43982 BasicType bt = Matcher::vector_element_basic_type(this);
43983 int opc = this->ideal_Opcode();
43984 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
43985 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), true, vlen_enc);
43986
43987#line 43987 "ad_x86.cpp"
43988 }
43989}
43990
43991void vminv_reg_maskedNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
43992 cbuf.set_insts_mark();
43993 // Start at oper_input_base() and count operands
43994 unsigned idx0 = 1;
43995 unsigned idx1 = 1; // dst
43996 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
43997 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
43998 {
43999 C2_MacroAssembler _masm(&cbuf);
44000
44001#line 9330 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
44002
44003 int vlen_enc = vector_length_encoding(this);
44004 BasicType bt = Matcher::vector_element_basic_type(this);
44005 int opc = this->ideal_Opcode();
44006 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
44007 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, true, vlen_enc);
44008
44009#line 44009 "ad_x86.cpp"
44010 }
44011}
44012
44013void vminv_mem_maskedNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44014 cbuf.set_insts_mark();
44015 // Start at oper_input_base() and count operands
44016 unsigned idx0 = 2;
44017 unsigned idx1 = 2; // dst
44018 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
44019 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
44020 {
44021 C2_MacroAssembler _masm(&cbuf);
44022
44023#line 9343 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
44024
44025 int vlen_enc = vector_length_encoding(this);
44026 BasicType bt = Matcher::vector_element_basic_type(this);
44027 int opc = this->ideal_Opcode();
44028 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
44029 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, Address::make_raw(opnd_array(2)->base(ra_,this,idx2), opnd_array(2)->index(ra_,this,idx2), opnd_array(2)->scale(), opnd_array(2)->disp(ra_,this,idx2), opnd_array(2)->disp_reloc()), true, vlen_enc);
44030
44031#line 44031 "ad_x86.cpp"
44032 }
44033}
44034
44035void vrearrangev_reg_maskedNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44036 cbuf.set_insts_mark();
44037 // Start at oper_input_base() and count operands
44038 unsigned idx0 = 1;
44039 unsigned idx1 = 1; // dst
44040 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
44041 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // mask
44042 {
44043 C2_MacroAssembler _masm(&cbuf);
44044
44045#line 9356 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
44046
44047 int vlen_enc = vector_length_encoding(this);
44048 BasicType bt = Matcher::vector_element_basic_type(this);
44049 int opc = this->ideal_Opcode();
44050 ___masm. evmasked_op(opc, bt, opnd_array(3)->as_KRegister(ra_,this,idx3)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
44051 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, false, vlen_enc);
44052
44053#line 44053 "ad_x86.cpp"
44054 }
44055}
44056
44057void vabs_maskedNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44058 cbuf.set_insts_mark();
44059 // Start at oper_input_base() and count operands
44060 unsigned idx0 = 1;
44061 unsigned idx1 = 1; // dst
44062 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask
44063 {
44064 C2_MacroAssembler _masm(&cbuf);
44065
44066#line 9373 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
44067
44068 int vlen_enc = vector_length_encoding(this);
44069 BasicType bt = Matcher::vector_element_basic_type(this);
44070 int opc = this->ideal_Opcode();
44071 ___masm. evmasked_op(opc, bt, opnd_array(2)->as_KRegister(ra_,this,idx2)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
44072 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, true, vlen_enc);
44073
44074#line 44074 "ad_x86.cpp"
44075 }
44076}
44077
44078void vabs_masked_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44079 cbuf.set_insts_mark();
44080 // Start at oper_input_base() and count operands
44081 unsigned idx0 = 1;
44082 unsigned idx1 = 1; // dst
44083 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask
44084 {
44085 C2_MacroAssembler _masm(&cbuf);
44086
44087#line 9373 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
44088
44089 int vlen_enc = vector_length_encoding(this);
44090 BasicType bt = Matcher::vector_element_basic_type(this);
44091 int opc = this->ideal_Opcode();
44092 ___masm. evmasked_op(opc, bt, opnd_array(2)->as_KRegister(ra_,this,idx2)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
44093 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, true, vlen_enc);
44094
44095#line 44095 "ad_x86.cpp"
44096 }
44097}
44098
44099void vabs_masked_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44100 cbuf.set_insts_mark();
44101 // Start at oper_input_base() and count operands
44102 unsigned idx0 = 1;
44103 unsigned idx1 = 1; // dst
44104 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask
44105 {
44106 C2_MacroAssembler _masm(&cbuf);
44107
44108#line 9373 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
44109
44110 int vlen_enc = vector_length_encoding(this);
44111 BasicType bt = Matcher::vector_element_basic_type(this);
44112 int opc = this->ideal_Opcode();
44113 ___masm. evmasked_op(opc, bt, opnd_array(2)->as_KRegister(ra_,this,idx2)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
44114 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, true, vlen_enc);
44115
44116#line 44116 "ad_x86.cpp"
44117 }
44118}
44119
44120void vabs_masked_2Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44121 cbuf.set_insts_mark();
44122 // Start at oper_input_base() and count operands
44123 unsigned idx0 = 1;
44124 unsigned idx1 = 1; // dst
44125 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // mask
44126 {
44127 C2_MacroAssembler _masm(&cbuf);
44128
44129#line 9373 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
44130
44131 int vlen_enc = vector_length_encoding(this);
44132 BasicType bt = Matcher::vector_element_basic_type(this);
44133 int opc = this->ideal_Opcode();
44134 ___masm. evmasked_op(opc, bt, opnd_array(2)->as_KRegister(ra_,this,idx2)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
44135 opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */, true, vlen_enc);
44136
44137#line 44137 "ad_x86.cpp"
44138 }
44139}
44140
44141void vfma_reg_maskedNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44142 cbuf.set_insts_mark();
44143 // Start at oper_input_base() and count operands
44144 unsigned idx0 = 1;
44145 unsigned idx1 = 1; // dst
44146 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
44147 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // src3
44148 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // mask
44149 {
44150 C2_MacroAssembler _masm(&cbuf);
44151
44152#line 9387 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
44153
44154 int vlen_enc = vector_length_encoding(this);
44155 BasicType bt = Matcher::vector_element_basic_type(this);
44156 int opc = this->ideal_Opcode();
44157 ___masm. evmasked_op(opc, bt, opnd_array(4)->as_KRegister(ra_,this,idx4)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
44158 opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* src3 */, true, vlen_enc);
44159
44160#line 44160 "ad_x86.cpp"
44161 }
44162}
44163
44164void vfma_reg_masked_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44165 cbuf.set_insts_mark();
44166 // Start at oper_input_base() and count operands
44167 unsigned idx0 = 1;
44168 unsigned idx1 = 1; // dst
44169 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
44170 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // src3
44171 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // mask
44172 {
44173 C2_MacroAssembler _masm(&cbuf);
44174
44175#line 9387 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
44176
44177 int vlen_enc = vector_length_encoding(this);
44178 BasicType bt = Matcher::vector_element_basic_type(this);
44179 int opc = this->ideal_Opcode();
44180 ___masm. evmasked_op(opc, bt, opnd_array(4)->as_KRegister(ra_,this,idx4)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
44181 opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, opnd_array(3)->as_XMMRegister(ra_,this,idx3)/* src3 */, true, vlen_enc);
44182
44183#line 44183 "ad_x86.cpp"
44184 }
44185}
44186
44187void vfma_mem_maskedNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44188 cbuf.set_insts_mark();
44189 // Start at oper_input_base() and count operands
44190 unsigned idx0 = 2;
44191 unsigned idx1 = 2; // dst
44192 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
44193 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // src3
44194 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // mask
44195 {
44196 C2_MacroAssembler _masm(&cbuf);
44197
44198#line 9401 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
44199
44200 int vlen_enc = vector_length_encoding(this);
44201 BasicType bt = Matcher::vector_element_basic_type(this);
44202 int opc = this->ideal_Opcode();
44203 ___masm. evmasked_op(opc, bt, opnd_array(4)->as_KRegister(ra_,this,idx4)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
44204 opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, Address::make_raw(opnd_array(3)->base(ra_,this,idx3), opnd_array(3)->index(ra_,this,idx3), opnd_array(3)->scale(), opnd_array(3)->disp(ra_,this,idx3), opnd_array(3)->disp_reloc()), true, vlen_enc);
44205
44206#line 44206 "ad_x86.cpp"
44207 }
44208}
44209
44210void vfma_mem_masked_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44211 cbuf.set_insts_mark();
44212 // Start at oper_input_base() and count operands
44213 unsigned idx0 = 2;
44214 unsigned idx1 = 2; // dst
44215 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
44216 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // src3
44217 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // mask
44218 {
44219 C2_MacroAssembler _masm(&cbuf);
44220
44221#line 9401 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
44222
44223 int vlen_enc = vector_length_encoding(this);
44224 BasicType bt = Matcher::vector_element_basic_type(this);
44225 int opc = this->ideal_Opcode();
44226 ___masm. evmasked_op(opc, bt, opnd_array(4)->as_KRegister(ra_,this,idx4)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* dst */,
44227 opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, Address::make_raw(opnd_array(3)->base(ra_,this,idx3), opnd_array(3)->index(ra_,this,idx3), opnd_array(3)->scale(), opnd_array(3)->disp(ra_,this,idx3), opnd_array(3)->disp_reloc()), true, vlen_enc);
44228
44229#line 44229 "ad_x86.cpp"
44230 }
44231}
44232
44233void evcmp_maskedNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44234 cbuf.set_insts_mark();
44235 // Start at oper_input_base() and count operands
44236 unsigned idx0 = 1;
44237 unsigned idx1 = 1; // src1
44238 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
44239 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // cond
44240 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // mask
44241 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // scratch
44242 {
44243 C2_MacroAssembler _masm(&cbuf);
44244
44245#line 9415 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
44246
44247 assert(bottom_type()->isa_vectmask(), "TypeVectMask expected")do { if (!(bottom_type()->isa_vectmask())) { (*g_assert_poison
) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
, 9416, "assert(" "bottom_type()->isa_vectmask()" ") failed"
, "TypeVectMask expected"); ::breakpoint(); } } while (0);
44248 int vlen_enc = vector_length_encoding(this, opnd_array(1));
44249 BasicType src1_elem_bt = Matcher::vector_element_basic_type(this, opnd_array(1));
44250
44251 // Comparison i
44252 switch (src1_elem_bt) {
44253 case T_BYTE: {
44254 bool is_unsigned = is_unsigned_booltest_pred(opnd_array(3)->constant());
44255 Assembler::ComparisonPredicate cmp = booltest_pred_to_comparison_pred(opnd_array(3)->constant());
44256 ___masm. evpcmpb(opnd_array(0)->as_KRegister(ra_,this)/* dst */, opnd_array(4)->as_KRegister(ra_,this,idx4)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, cmp, !is_unsigned, vlen_enc);
44257 break;
44258 }
44259 case T_SHORT: {
44260 bool is_unsigned = is_unsigned_booltest_pred(opnd_array(3)->constant());
44261 Assembler::ComparisonPredicate cmp = booltest_pred_to_comparison_pred(opnd_array(3)->constant());
44262 ___masm. evpcmpw(opnd_array(0)->as_KRegister(ra_,this)/* dst */, opnd_array(4)->as_KRegister(ra_,this,idx4)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, cmp, !is_unsigned, vlen_enc);
44263 break;
44264 }
44265 case T_INT: {
44266 bool is_unsigned = is_unsigned_booltest_pred(opnd_array(3)->constant());
44267 Assembler::ComparisonPredicate cmp = booltest_pred_to_comparison_pred(opnd_array(3)->constant());
44268 ___masm. evpcmpd(opnd_array(0)->as_KRegister(ra_,this)/* dst */, opnd_array(4)->as_KRegister(ra_,this,idx4)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, cmp, !is_unsigned, vlen_enc);
44269 break;
44270 }
44271 case T_LONG: {
44272 bool is_unsigned = is_unsigned_booltest_pred(opnd_array(3)->constant());
44273 Assembler::ComparisonPredicate cmp = booltest_pred_to_comparison_pred(opnd_array(3)->constant());
44274 ___masm. evpcmpq(opnd_array(0)->as_KRegister(ra_,this)/* dst */, opnd_array(4)->as_KRegister(ra_,this,idx4)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, cmp, !is_unsigned, vlen_enc);
44275 break;
44276 }
44277 case T_FLOAT: {
44278 Assembler::ComparisonPredicateFP cmp = booltest_pred_to_comparison_pred_fp(opnd_array(3)->constant());
44279 ___masm. evcmpps(opnd_array(0)->as_KRegister(ra_,this)/* dst */, opnd_array(4)->as_KRegister(ra_,this,idx4)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, cmp, vlen_enc);
44280 break;
44281 }
44282 case T_DOUBLE: {
44283 Assembler::ComparisonPredicateFP cmp = booltest_pred_to_comparison_pred_fp(opnd_array(3)->constant());
44284 ___masm. evcmppd(opnd_array(0)->as_KRegister(ra_,this)/* dst */, opnd_array(4)->as_KRegister(ra_,this,idx4)/* mask */, opnd_array(1)->as_XMMRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* src2 */, cmp, vlen_enc);
44285 break;
44286 }
44287 default: assert(false, "%s", type2name(src1_elem_bt))do { if (!(false)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
9456, "assert(" "false" ") failed", "%s", type2name(src1_elem_bt
)); ::breakpoint(); } } while (0); break;
44288 }
44289
44290#line 44290 "ad_x86.cpp"
44291 }
44292}
44293
44294void mask_all_evexI_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44295 cbuf.set_insts_mark();
44296 // Start at oper_input_base() and count operands
44297 unsigned idx0 = 1;
44298 unsigned idx1 = 1; // cnt
44299 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
44300 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
44301 {
44302 C2_MacroAssembler _masm(&cbuf);
44303
44304#line 9467 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
44305
44306 int vec_len = Matcher::vector_length(this);
44307 if (VM_Version::supports_avx512bw()) {
44308 ___masm. movq(opnd_array(3)->as_Register(ra_,this,idx3)/* tmp */, opnd_array(1)->constant());
44309 ___masm. kmovql(opnd_array(2)->as_KRegister(ra_,this,idx2)/* dst */, opnd_array(3)->as_Register(ra_,this,idx3)/* tmp */);
44310 ___masm. kshiftrql(opnd_array(2)->as_KRegister(ra_,this,idx2)/* dst */, opnd_array(2)->as_KRegister(ra_,this,idx2)/* dst */, 64 - vec_len);
44311 } else {
44312 assert(vec_len <= 16, "")do { if (!(vec_len <= 16)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
9474, "assert(" "vec_len <= 16" ") failed", ""); ::breakpoint
(); } } while (0);
44313 ___masm. movq(opnd_array(3)->as_Register(ra_,this,idx3)/* tmp */, opnd_array(1)->constant());
44314 ___masm. kmovwl(opnd_array(2)->as_KRegister(ra_,this,idx2)/* dst */, opnd_array(3)->as_Register(ra_,this,idx3)/* tmp */);
44315 ___masm. kshiftrwl(opnd_array(2)->as_KRegister(ra_,this,idx2)/* dst */, opnd_array(2)->as_KRegister(ra_,this,idx2)/* dst */, 16 - vec_len);
44316 }
44317
44318#line 44318 "ad_x86.cpp"
44319 }
44320}
44321
44322void mask_all_evexINode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44323 cbuf.set_insts_mark();
44324 // Start at oper_input_base() and count operands
44325 unsigned idx0 = 1;
44326 unsigned idx1 = 1; // src
44327 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
44328 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // tmp
44329 {
44330 C2_MacroAssembler _masm(&cbuf);
44331
44332#line 9487 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
44333
44334 int vec_len = Matcher::vector_length(this);
44335 if (VM_Version::supports_avx512bw()) {
44336 ___masm. movslq(opnd_array(3)->as_Register(ra_,this,idx3)/* tmp */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
44337 ___masm. kmovql(opnd_array(2)->as_KRegister(ra_,this,idx2)/* dst */, opnd_array(3)->as_Register(ra_,this,idx3)/* tmp */);
44338 ___masm. kshiftrql(opnd_array(2)->as_KRegister(ra_,this,idx2)/* dst */, opnd_array(2)->as_KRegister(ra_,this,idx2)/* dst */, 64 - vec_len);
44339 } else {
44340 assert(vec_len <= 16, "")do { if (!(vec_len <= 16)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
9494, "assert(" "vec_len <= 16" ") failed", ""); ::breakpoint
(); } } while (0);
44341 ___masm. kmovwl(opnd_array(2)->as_KRegister(ra_,this,idx2)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
44342 ___masm. kshiftrwl(opnd_array(2)->as_KRegister(ra_,this,idx2)/* dst */, opnd_array(2)->as_KRegister(ra_,this,idx2)/* dst */, 16 - vec_len);
44343 }
44344
44345#line 44345 "ad_x86.cpp"
44346 }
44347}
44348
44349void mask_all_evexLNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44350 cbuf.set_insts_mark();
44351 // Start at oper_input_base() and count operands
44352 unsigned idx0 = 1;
44353 unsigned idx1 = 1; // src
44354 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
44355 {
44356 C2_MacroAssembler _masm(&cbuf);
44357
44358#line 9506 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
44359
44360 int vec_len = Matcher::vector_length(this);
44361 if (VM_Version::supports_avx512bw()) {
44362 ___masm. kmovql(opnd_array(2)->as_KRegister(ra_,this,idx2)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
44363 ___masm. kshiftrql(opnd_array(2)->as_KRegister(ra_,this,idx2)/* dst */, opnd_array(2)->as_KRegister(ra_,this,idx2)/* dst */, 64 - vec_len);
44364 } else {
44365 assert(vec_len <= 16, "")do { if (!(vec_len <= 16)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
9512, "assert(" "vec_len <= 16" ") failed", ""); ::breakpoint
(); } } while (0);
44366 ___masm. kmovwl(opnd_array(2)->as_KRegister(ra_,this,idx2)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
44367 ___masm. kshiftrwl(opnd_array(2)->as_KRegister(ra_,this,idx2)/* dst */, opnd_array(2)->as_KRegister(ra_,this,idx2)/* dst */, 16 - vec_len);
44368 }
44369
44370#line 44370 "ad_x86.cpp"
44371 }
44372}
44373
44374void mask_not_immLT8Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44375 cbuf.set_insts_mark();
44376 // Start at oper_input_base() and count operands
44377 unsigned idx0 = 1;
44378 unsigned idx1 = 1; // src
44379 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cnt
44380 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // dst
44381 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // rtmp
44382 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // ktmp
44383 {
44384 C2_MacroAssembler _masm(&cbuf);
44385
44386#line 9525 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
44387
44388 uint masklen = Matcher::vector_length(this);
44389 ___masm. knot(masklen, opnd_array(3)->as_KRegister(ra_,this,idx3)/* dst */, opnd_array(1)->as_KRegister(ra_,this,idx1)/* src */, opnd_array(5)->as_KRegister(ra_,this,idx5)/* ktmp */, opnd_array(4)->as_Register(ra_,this,idx4)/* rtmp */);
44390
44391#line 44391 "ad_x86.cpp"
44392 }
44393}
44394
44395void mask_not_immNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44396 cbuf.set_insts_mark();
44397 // Start at oper_input_base() and count operands
44398 unsigned idx0 = 1;
44399 unsigned idx1 = 1; // src
44400 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // cnt
44401 {
44402 C2_MacroAssembler _masm(&cbuf);
44403
44404#line 9538 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
44405
44406 uint masklen = Matcher::vector_length(this);
44407 ___masm. knot(masklen, opnd_array(0)->as_KRegister(ra_,this)/* dst */, opnd_array(1)->as_KRegister(ra_,this,idx1)/* src */);
44408
44409#line 44409 "ad_x86.cpp"
44410 }
44411}
44412
44413void long_to_maskLE8_avxNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44414 cbuf.set_insts_mark();
44415 // Start at oper_input_base() and count operands
44416 unsigned idx0 = 1;
44417 unsigned idx1 = 1; // src
44418 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
44419 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // rtmp1
44420 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // rtmp2
44421 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // xtmp
44422 {
44423 C2_MacroAssembler _masm(&cbuf);
44424
44425#line 9550 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
44426
44427 int mask_len = Matcher::vector_length(this);
44428 int vec_enc = vector_length_encoding(mask_len);
44429 ___masm. vector_long_to_maskvec(opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */, opnd_array(3)->as_Register(ra_,this,idx3)/* rtmp1 */,
44430 opnd_array(4)->as_Register(ra_,this,idx4)/* rtmp2 */, xnoreg, mask_len, vec_enc);
44431
44432#line 44432 "ad_x86.cpp"
44433 }
44434}
44435
44436void long_to_maskGT8_avxNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44437 cbuf.set_insts_mark();
44438 // Start at oper_input_base() and count operands
44439 unsigned idx0 = 1;
44440 unsigned idx1 = 1; // src
44441 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
44442 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // rtmp1
44443 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // rtmp2
44444 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // xtmp1
44445 {
44446 C2_MacroAssembler _masm(&cbuf);
44447
44448#line 9565 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
44449
44450 int mask_len = Matcher::vector_length(this);
44451 assert(mask_len <= 32, "invalid mask length")do { if (!(mask_len <= 32)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
9567, "assert(" "mask_len <= 32" ") failed", "invalid mask length"
); ::breakpoint(); } } while (0);
44452 int vec_enc = vector_length_encoding(mask_len);
44453 ___masm. vector_long_to_maskvec(opnd_array(2)->as_XMMRegister(ra_,this,idx2)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */, opnd_array(3)->as_Register(ra_,this,idx3)/* rtmp1 */,
44454 opnd_array(4)->as_Register(ra_,this,idx4)/* rtmp2 */, opnd_array(5)->as_XMMRegister(ra_,this,idx5)/* xtmp1 */, mask_len, vec_enc);
44455
44456#line 44456 "ad_x86.cpp"
44457 }
44458}
44459
44460void long_to_mask_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44461 cbuf.set_insts_mark();
44462 // Start at oper_input_base() and count operands
44463 unsigned idx0 = 1;
44464 unsigned idx1 = 1; // src
44465 {
44466 C2_MacroAssembler _masm(&cbuf);
44467
44468#line 9579 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
44469
44470 ___masm. kmov(opnd_array(0)->as_KRegister(ra_,this)/* dst */, opnd_array(1)->as_Register(ra_,this,idx1)/* src */);
44471
44472#line 44472 "ad_x86.cpp"
44473 }
44474}
44475
44476void mask_opers_evexNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44477 cbuf.set_insts_mark();
44478 // Start at oper_input_base() and count operands
44479 unsigned idx0 = 1;
44480 unsigned idx1 = 1; // src1
44481 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
44482 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // kscratch
44483 {
44484 C2_MacroAssembler _masm(&cbuf);
44485
44486#line 9592 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
44487
44488 const MachNode* mask1 = static_cast<const MachNode*>(this->in(this->operand_index(opnd_array(1))));
44489 const MachNode* mask2 = static_cast<const MachNode*>(this->in(this->operand_index(opnd_array(2))));
44490 assert(0 == Type::cmp(mask1->bottom_type(), mask2->bottom_type()), "")do { if (!(0 == Type::cmp(mask1->bottom_type(), mask2->
bottom_type()))) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
9595, "assert(" "0 == Type::cmp(mask1->bottom_type(), mask2->bottom_type())"
") failed", ""); ::breakpoint(); } } while (0);
44491 uint masklen = Matcher::vector_length(this);
44492 masklen = (masklen < 16 && !VM_Version::supports_avx512dq()) ? 16 : masklen;
44493 ___masm. masked_op(this->ideal_Opcode(), masklen, opnd_array(0)->as_KRegister(ra_,this)/* dst */, opnd_array(1)->as_KRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_KRegister(ra_,this,idx2)/* src2 */);
44494
44495#line 44495 "ad_x86.cpp"
44496 }
44497}
44498
44499void mask_opers_evex_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44500 cbuf.set_insts_mark();
44501 // Start at oper_input_base() and count operands
44502 unsigned idx0 = 1;
44503 unsigned idx1 = 1; // src1
44504 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
44505 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // kscratch
44506 {
44507 C2_MacroAssembler _masm(&cbuf);
44508
44509#line 9592 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
44510
44511 const MachNode* mask1 = static_cast<const MachNode*>(this->in(this->operand_index(opnd_array(1))));
44512 const MachNode* mask2 = static_cast<const MachNode*>(this->in(this->operand_index(opnd_array(2))));
44513 assert(0 == Type::cmp(mask1->bottom_type(), mask2->bottom_type()), "")do { if (!(0 == Type::cmp(mask1->bottom_type(), mask2->
bottom_type()))) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
9595, "assert(" "0 == Type::cmp(mask1->bottom_type(), mask2->bottom_type())"
") failed", ""); ::breakpoint(); } } while (0);
44514 uint masklen = Matcher::vector_length(this);
44515 masklen = (masklen < 16 && !VM_Version::supports_avx512dq()) ? 16 : masklen;
44516 ___masm. masked_op(this->ideal_Opcode(), masklen, opnd_array(0)->as_KRegister(ra_,this)/* dst */, opnd_array(1)->as_KRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_KRegister(ra_,this,idx2)/* src2 */);
44517
44518#line 44518 "ad_x86.cpp"
44519 }
44520}
44521
44522void mask_opers_evex_1Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44523 cbuf.set_insts_mark();
44524 // Start at oper_input_base() and count operands
44525 unsigned idx0 = 1;
44526 unsigned idx1 = 1; // src1
44527 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // src2
44528 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // kscratch
44529 {
44530 C2_MacroAssembler _masm(&cbuf);
44531
44532#line 9592 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad"
44533
44534 const MachNode* mask1 = static_cast<const MachNode*>(this->in(this->operand_index(opnd_array(1))));
44535 const MachNode* mask2 = static_cast<const MachNode*>(this->in(this->operand_index(opnd_array(2))));
44536 assert(0 == Type::cmp(mask1->bottom_type(), mask2->bottom_type()), "")do { if (!(0 == Type::cmp(mask1->bottom_type(), mask2->
bottom_type()))) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86.ad",
9595, "assert(" "0 == Type::cmp(mask1->bottom_type(), mask2->bottom_type())"
") failed", ""); ::breakpoint(); } } while (0);
44537 uint masklen = Matcher::vector_length(this);
44538 masklen = (masklen < 16 && !VM_Version::supports_avx512dq()) ? 16 : masklen;
44539 ___masm. masked_op(this->ideal_Opcode(), masklen, opnd_array(0)->as_KRegister(ra_,this)/* dst */, opnd_array(1)->as_KRegister(ra_,this,idx1)/* src1 */, opnd_array(2)->as_KRegister(ra_,this,idx2)/* src2 */);
44540
44541#line 44541 "ad_x86.cpp"
44542 }
44543}
44544
44545void castMMNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44546 cbuf.set_insts_mark();
44547 // Start at oper_input_base() and count operands
44548 unsigned idx0 = 1;
44549 unsigned idx1 = 1; // dst
44550 // User did not define which encode class to use.
44551}
44552
44553uint castMMNode::size(PhaseRegAlloc *ra_) const {
44554 assert(VerifyOops || MachNode::size(ra_) <= 0, "bad fixed size")do { if (!(VerifyOops || MachNode::size(ra_) <= 0)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 44553, "assert(" "VerifyOops || MachNode::size(ra_) <= 0"
") failed", "bad fixed size"); ::breakpoint(); } } while (0);
44555 return (VerifyOops ? MachNode::size(ra_) : 0);
44556}
44557
44558void castVVNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44559 cbuf.set_insts_mark();
44560 // Start at oper_input_base() and count operands
44561 unsigned idx0 = 1;
44562 unsigned idx1 = 1; // dst
44563 // User did not define which encode class to use.
44564}
44565
44566uint castVVNode::size(PhaseRegAlloc *ra_) const {
44567 assert(VerifyOops || MachNode::size(ra_) <= 0, "bad fixed size")do { if (!(VerifyOops || MachNode::size(ra_) <= 0)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 44566, "assert(" "VerifyOops || MachNode::size(ra_) <= 0"
") failed", "bad fixed size"); ::breakpoint(); } } while (0);
44568 return (VerifyOops ? MachNode::size(ra_) : 0);
44569}
44570
44571void castVVLegNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44572 cbuf.set_insts_mark();
44573 // Start at oper_input_base() and count operands
44574 unsigned idx0 = 1;
44575 unsigned idx1 = 1; // dst
44576 // User did not define which encode class to use.
44577}
44578
44579uint castVVLegNode::size(PhaseRegAlloc *ra_) const {
44580 assert(VerifyOops || MachNode::size(ra_) <= 0, "bad fixed size")do { if (!(VerifyOops || MachNode::size(ra_) <= 0)) { (*g_assert_poison
) = 'X';; report_vm_error("ad_x86.cpp", 44579, "assert(" "VerifyOops || MachNode::size(ra_) <= 0"
") failed", "bad fixed size"); ::breakpoint(); } } while (0);
44581 return (VerifyOops ? MachNode::size(ra_) : 0);
44582}
44583
44584void compareAndSwapP_shenandoahNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44585 cbuf.set_insts_mark();
44586 // Start at oper_input_base() and count operands
44587 unsigned idx0 = 2;
44588 unsigned idx1 = 2; // mem_ptr
44589 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
44590 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
44591 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
44592 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
44593 {
44594 C2_MacroAssembler _masm(&cbuf);
44595
44596#line 43 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/gc/shenandoah/shenandoah_x86_64.ad"
44597
44598 ShenandoahBarrierSet::assembler()->cmpxchg_oop(&_masm,
44599 opnd_array(0)->as_Register(ra_,this)/* res */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_Register(ra_,this,idx2)/* oldval */, opnd_array(3)->as_Register(ra_,this,idx3)/* newval */,
44600 false, // swap
44601 opnd_array(4)->as_Register(ra_,this,idx4)/* tmp1 */, opnd_array(5)->as_Register(ra_,this,idx5)/* tmp2 */);
44602
44603#line 44603 "ad_x86.cpp"
44604 }
44605}
44606
44607void compareAndSwapP_shenandoah_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44608 cbuf.set_insts_mark();
44609 // Start at oper_input_base() and count operands
44610 unsigned idx0 = 2;
44611 unsigned idx1 = 2; // mem_ptr
44612 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
44613 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
44614 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
44615 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
44616 {
44617 C2_MacroAssembler _masm(&cbuf);
44618
44619#line 43 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/gc/shenandoah/shenandoah_x86_64.ad"
44620
44621 ShenandoahBarrierSet::assembler()->cmpxchg_oop(&_masm,
44622 opnd_array(0)->as_Register(ra_,this)/* res */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_Register(ra_,this,idx2)/* oldval */, opnd_array(3)->as_Register(ra_,this,idx3)/* newval */,
44623 false, // swap
44624 opnd_array(4)->as_Register(ra_,this,idx4)/* tmp1 */, opnd_array(5)->as_Register(ra_,this,idx5)/* tmp2 */);
44625
44626#line 44626 "ad_x86.cpp"
44627 }
44628}
44629
44630void compareAndSwapN_shenandoahNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44631 cbuf.set_insts_mark();
44632 // Start at oper_input_base() and count operands
44633 unsigned idx0 = 2;
44634 unsigned idx1 = 2; // mem_ptr
44635 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
44636 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
44637 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
44638 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
44639 {
44640 C2_MacroAssembler _masm(&cbuf);
44641
44642#line 64 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/gc/shenandoah/shenandoah_x86_64.ad"
44643
44644 ShenandoahBarrierSet::assembler()->cmpxchg_oop(&_masm,
44645 opnd_array(0)->as_Register(ra_,this)/* res */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_Register(ra_,this,idx2)/* oldval */, opnd_array(3)->as_Register(ra_,this,idx3)/* newval */,
44646 false, // swap
44647 opnd_array(4)->as_Register(ra_,this,idx4)/* tmp1 */, opnd_array(5)->as_Register(ra_,this,idx5)/* tmp2 */);
44648
44649#line 44649 "ad_x86.cpp"
44650 }
44651}
44652
44653void compareAndSwapN_shenandoah_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44654 cbuf.set_insts_mark();
44655 // Start at oper_input_base() and count operands
44656 unsigned idx0 = 2;
44657 unsigned idx1 = 2; // mem_ptr
44658 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
44659 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
44660 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
44661 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
44662 {
44663 C2_MacroAssembler _masm(&cbuf);
44664
44665#line 64 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/gc/shenandoah/shenandoah_x86_64.ad"
44666
44667 ShenandoahBarrierSet::assembler()->cmpxchg_oop(&_masm,
44668 opnd_array(0)->as_Register(ra_,this)/* res */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_Register(ra_,this,idx2)/* oldval */, opnd_array(3)->as_Register(ra_,this,idx3)/* newval */,
44669 false, // swap
44670 opnd_array(4)->as_Register(ra_,this,idx4)/* tmp1 */, opnd_array(5)->as_Register(ra_,this,idx5)/* tmp2 */);
44671
44672#line 44672 "ad_x86.cpp"
44673 }
44674}
44675
44676void compareAndExchangeN_shenandoahNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44677 cbuf.set_insts_mark();
44678 // Start at oper_input_base() and count operands
44679 unsigned idx0 = 2;
44680 unsigned idx1 = 2; // mem_ptr
44681 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
44682 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
44683 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
44684 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
44685 {
44686 C2_MacroAssembler _masm(&cbuf);
44687
44688#line 83 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/gc/shenandoah/shenandoah_x86_64.ad"
44689
44690 ShenandoahBarrierSet::assembler()->cmpxchg_oop(&_masm,
44691 NULL__null, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_Register(ra_,this,idx2)/* oldval */, opnd_array(3)->as_Register(ra_,this,idx3)/* newval */,
44692 true, // exchange
44693 opnd_array(4)->as_Register(ra_,this,idx4)/* tmp1 */, opnd_array(5)->as_Register(ra_,this,idx5)/* tmp2 */);
44694
44695#line 44695 "ad_x86.cpp"
44696 }
44697}
44698
44699void compareAndExchangeP_shenandoahNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44700 cbuf.set_insts_mark();
44701 // Start at oper_input_base() and count operands
44702 unsigned idx0 = 2;
44703 unsigned idx1 = 2; // mem_ptr
44704 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
44705 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
44706 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp1
44707 unsigned idx5 = idx4 + opnd_array(4)->num_edges(); // tmp2
44708 {
44709 C2_MacroAssembler _masm(&cbuf);
44710
44711#line 105 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/gc/shenandoah/shenandoah_x86_64.ad"
44712
44713 ShenandoahBarrierSet::assembler()->cmpxchg_oop(&_masm,
44714 NULL__null, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_Register(ra_,this,idx2)/* oldval */, opnd_array(3)->as_Register(ra_,this,idx3)/* newval */,
44715 true, // exchange
44716 opnd_array(4)->as_Register(ra_,this,idx4)/* tmp1 */, opnd_array(5)->as_Register(ra_,this,idx5)/* tmp2 */);
44717
44718#line 44718 "ad_x86.cpp"
44719 }
44720}
44721
44722void zLoadPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44723 cbuf.set_insts_mark();
44724 // Start at oper_input_base() and count operands
44725 unsigned idx0 = 2;
44726 unsigned idx1 = 2; // mem
44727 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // dst
44728 {
44729 C2_MacroAssembler _masm(&cbuf);
44730
44731#line 76 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/gc/z/z_x86_64.ad"
44732
44733 ___masm. movptr(opnd_array(2)->as_Register(ra_,this,idx2)/* dst */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
44734 z_load_barrier(_masm, this, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_Register(ra_,this,idx2)/* dst */, noreg /* tmp */, barrier_data());
44735
44736#line 44736 "ad_x86.cpp"
44737 }
44738}
44739
44740void zCompareAndExchangePNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44741 cbuf.set_insts_mark();
44742 // Start at oper_input_base() and count operands
44743 unsigned idx0 = 2;
44744 unsigned idx1 = 2; // mem
44745 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
44746 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
44747 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
44748 {
44749 C2_MacroAssembler _masm(&cbuf);
44750
44751#line 92 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/gc/z/z_x86_64.ad"
44752
44753 if (barrier_data() != ZLoadBarrierElided) { // barrier could be elided by ZBarrierSetC2::analyze_dominating_barriers()
44754 ___masm. movptr(opnd_array(4)->as_Register(ra_,this,idx4)/* tmp */, opnd_array(2)->as_Register(ra_,this,idx2)/* oldval */);
44755 }
44756 ___masm. lock();
44757 ___masm. cmpxchgptr(opnd_array(3)->as_Register(ra_,this,idx3)/* newval */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
44758
44759 if (barrier_data() != ZLoadBarrierElided) {
44760 Label good;
44761 z_load_barrier_cmpxchg(_masm, this, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_Register(ra_,this,idx2)/* oldval */, opnd_array(4)->as_Register(ra_,this,idx4)/* tmp */, good);
44762 ___masm. movptr(opnd_array(2)->as_Register(ra_,this,idx2)/* oldval */, opnd_array(4)->as_Register(ra_,this,idx4)/* tmp */);
44763 ___masm. lock();
44764 ___masm. cmpxchgptr(opnd_array(3)->as_Register(ra_,this,idx3)/* newval */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
44765 ___masm. bind(good);
44766 }
44767
44768#line 44768 "ad_x86.cpp"
44769 }
44770}
44771
44772void zCompareAndSwapPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44773 cbuf.set_insts_mark();
44774 // Start at oper_input_base() and count operands
44775 unsigned idx0 = 2;
44776 unsigned idx1 = 2; // mem
44777 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
44778 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
44779 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
44780 {
44781 C2_MacroAssembler _masm(&cbuf);
44782
44783#line 123 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/gc/z/z_x86_64.ad"
44784
44785 if (barrier_data() != ZLoadBarrierElided) { // barrier could be elided by ZBarrierSetC2::analyze_dominating_barriers()
44786 ___masm. movptr(opnd_array(4)->as_Register(ra_,this,idx4)/* tmp */, opnd_array(2)->as_Register(ra_,this,idx2)/* oldval */);
44787 }
44788 ___masm. lock();
44789 ___masm. cmpxchgptr(opnd_array(3)->as_Register(ra_,this,idx3)/* newval */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
44790
44791 if (barrier_data() != ZLoadBarrierElided) {
44792 Label good;
44793 z_load_barrier_cmpxchg(_masm, this, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_Register(ra_,this,idx2)/* oldval */, opnd_array(4)->as_Register(ra_,this,idx4)/* tmp */, good);
44794 ___masm. movptr(opnd_array(2)->as_Register(ra_,this,idx2)/* oldval */, opnd_array(4)->as_Register(ra_,this,idx4)/* tmp */);
44795 ___masm. lock();
44796 ___masm. cmpxchgptr(opnd_array(3)->as_Register(ra_,this,idx3)/* newval */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
44797 ___masm. bind(good);
44798 ___masm. cmpptr(opnd_array(4)->as_Register(ra_,this,idx4)/* tmp */, opnd_array(2)->as_Register(ra_,this,idx2)/* oldval */);
44799 }
44800 ___masm. setb(Assembler::equal, opnd_array(0)->as_Register(ra_,this)/* res */);
44801 ___masm. movzbl(opnd_array(0)->as_Register(ra_,this)/* res */, opnd_array(0)->as_Register(ra_,this)/* res */);
44802
44803#line 44803 "ad_x86.cpp"
44804 }
44805}
44806
44807void zCompareAndSwapP_0Node::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44808 cbuf.set_insts_mark();
44809 // Start at oper_input_base() and count operands
44810 unsigned idx0 = 2;
44811 unsigned idx1 = 2; // mem
44812 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // oldval
44813 unsigned idx3 = idx2 + opnd_array(2)->num_edges(); // newval
44814 unsigned idx4 = idx3 + opnd_array(3)->num_edges(); // tmp
44815 {
44816 C2_MacroAssembler _masm(&cbuf);
44817
44818#line 123 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/gc/z/z_x86_64.ad"
44819
44820 if (barrier_data() != ZLoadBarrierElided) { // barrier could be elided by ZBarrierSetC2::analyze_dominating_barriers()
44821 ___masm. movptr(opnd_array(4)->as_Register(ra_,this,idx4)/* tmp */, opnd_array(2)->as_Register(ra_,this,idx2)/* oldval */);
44822 }
44823 ___masm. lock();
44824 ___masm. cmpxchgptr(opnd_array(3)->as_Register(ra_,this,idx3)/* newval */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
44825
44826 if (barrier_data() != ZLoadBarrierElided) {
44827 Label good;
44828 z_load_barrier_cmpxchg(_masm, this, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()), opnd_array(2)->as_Register(ra_,this,idx2)/* oldval */, opnd_array(4)->as_Register(ra_,this,idx4)/* tmp */, good);
44829 ___masm. movptr(opnd_array(2)->as_Register(ra_,this,idx2)/* oldval */, opnd_array(4)->as_Register(ra_,this,idx4)/* tmp */);
44830 ___masm. lock();
44831 ___masm. cmpxchgptr(opnd_array(3)->as_Register(ra_,this,idx3)/* newval */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
44832 ___masm. bind(good);
44833 ___masm. cmpptr(opnd_array(4)->as_Register(ra_,this,idx4)/* tmp */, opnd_array(2)->as_Register(ra_,this,idx2)/* oldval */);
44834 }
44835 ___masm. setb(Assembler::equal, opnd_array(0)->as_Register(ra_,this)/* res */);
44836 ___masm. movzbl(opnd_array(0)->as_Register(ra_,this)/* res */, opnd_array(0)->as_Register(ra_,this)/* res */);
44837
44838#line 44838 "ad_x86.cpp"
44839 }
44840}
44841
44842void zXChgPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
44843 cbuf.set_insts_mark();
44844 // Start at oper_input_base() and count operands
44845 unsigned idx0 = 2;
44846 unsigned idx1 = 2; // mem
44847 unsigned idx2 = idx1 + opnd_array(1)->num_edges(); // newval
44848 {
44849 C2_MacroAssembler _masm(&cbuf);
44850
44851#line 153 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/gc/z/z_x86_64.ad"
44852
44853 ___masm. xchgptr(opnd_array(2)->as_Register(ra_,this,idx2)/* newval */, Address::make_raw(opnd_array(1)->base(ra_,this,idx1), opnd_array(1)->index(ra_,this,idx1), opnd_array(1)->scale(), opnd_array(1)->disp(ra_,this,idx1), opnd_array(1)->disp_reloc()));
44854 z_load_barrier(_masm, this, Address(noreg, 0), opnd_array(2)->as_Register(ra_,this,idx2)/* newval */, noreg /* tmp */, barrier_data());
44855
44856#line 44856 "ad_x86.cpp"
44857 }
44858}
44859
44860const MachOper* loadBNode::memory_operand() const { return _opnds[1]; }
44861const MachOper* loadB2LNode::memory_operand() const { return _opnds[1]; }
44862const MachOper* loadUBNode::memory_operand() const { return _opnds[1]; }
44863const MachOper* loadUB2LNode::memory_operand() const { return _opnds[1]; }
44864const MachOper* loadUB2L_immINode::memory_operand() const { return _opnds[1]; }
44865const MachOper* loadSNode::memory_operand() const { return _opnds[1]; }
44866const MachOper* loadS2BNode::memory_operand() const { return _opnds[1]; }
44867const MachOper* loadS2LNode::memory_operand() const { return _opnds[1]; }
44868const MachOper* loadUSNode::memory_operand() const { return _opnds[1]; }
44869const MachOper* loadUS2BNode::memory_operand() const { return _opnds[1]; }
44870const MachOper* loadUS2LNode::memory_operand() const { return _opnds[1]; }
44871const MachOper* loadUS2L_immI_255Node::memory_operand() const { return _opnds[1]; }
44872const MachOper* loadUS2L_immINode::memory_operand() const { return _opnds[1]; }
44873const MachOper* loadINode::memory_operand() const { return _opnds[1]; }
44874const MachOper* loadI2BNode::memory_operand() const { return _opnds[1]; }
44875const MachOper* loadI2UBNode::memory_operand() const { return _opnds[1]; }
44876const MachOper* loadI2SNode::memory_operand() const { return _opnds[1]; }
44877const MachOper* loadI2USNode::memory_operand() const { return _opnds[1]; }
44878const MachOper* loadI2LNode::memory_operand() const { return _opnds[1]; }
44879const MachOper* loadI2L_immI_255Node::memory_operand() const { return _opnds[1]; }
44880const MachOper* loadI2L_immI_65535Node::memory_operand() const { return _opnds[1]; }
44881const MachOper* loadI2L_immU31Node::memory_operand() const { return _opnds[1]; }
44882const MachOper* loadUI2LNode::memory_operand() const { return _opnds[1]; }
44883const MachOper* loadLNode::memory_operand() const { return _opnds[1]; }
44884const MachOper* loadRangeNode::memory_operand() const { return _opnds[1]; }
44885const MachOper* loadPNode::memory_operand() const { return _opnds[1]; }
44886const MachOper* loadNNode::memory_operand() const { return _opnds[1]; }
44887const MachOper* loadKlassNode::memory_operand() const { return _opnds[1]; }
44888const MachOper* loadNKlassNode::memory_operand() const { return _opnds[1]; }
44889const MachOper* loadFNode::memory_operand() const { return _opnds[1]; }
44890const MachOper* loadD_partialNode::memory_operand() const { return _opnds[1]; }
44891const MachOper* loadDNode::memory_operand() const { return _opnds[1]; }
44892const MachOper* prefetchAllocNode::memory_operand() const { return _opnds[1]; }
44893const MachOper* prefetchAllocNTANode::memory_operand() const { return _opnds[1]; }
44894const MachOper* prefetchAllocT0Node::memory_operand() const { return _opnds[1]; }
44895const MachOper* prefetchAllocT2Node::memory_operand() const { return _opnds[1]; }
44896const MachOper* storeBNode::memory_operand() const { return _opnds[1]; }
44897const MachOper* storeCNode::memory_operand() const { return _opnds[1]; }
44898const MachOper* storeINode::memory_operand() const { return _opnds[1]; }
44899const MachOper* storeLNode::memory_operand() const { return _opnds[1]; }
44900const MachOper* storePNode::memory_operand() const { return _opnds[1]; }
44901const MachOper* storeImmP0Node::memory_operand() const { return _opnds[1]; }
44902const MachOper* storeImmPNode::memory_operand() const { return _opnds[1]; }
44903const MachOper* storeNNode::memory_operand() const { return _opnds[1]; }
44904const MachOper* storeNKlassNode::memory_operand() const { return _opnds[1]; }
44905const MachOper* storeImmN0Node::memory_operand() const { return _opnds[1]; }
44906const MachOper* storeImmNNode::memory_operand() const { return _opnds[1]; }
44907const MachOper* storeImmNKlassNode::memory_operand() const { return _opnds[1]; }
44908const MachOper* storeImmI0Node::memory_operand() const { return _opnds[1]; }
44909const MachOper* storeImmINode::memory_operand() const { return _opnds[1]; }
44910const MachOper* storeImmL0Node::memory_operand() const { return _opnds[1]; }
44911const MachOper* storeImmLNode::memory_operand() const { return _opnds[1]; }
44912const MachOper* storeImmC0Node::memory_operand() const { return _opnds[1]; }
44913const MachOper* storeImmI16Node::memory_operand() const { return _opnds[1]; }
44914const MachOper* storeImmB0Node::memory_operand() const { return _opnds[1]; }
44915const MachOper* storeImmBNode::memory_operand() const { return _opnds[1]; }
44916const MachOper* storeImmCM0_regNode::memory_operand() const { return _opnds[1]; }
44917const MachOper* storeImmCM0Node::memory_operand() const { return _opnds[1]; }
44918const MachOper* storeFNode::memory_operand() const { return _opnds[1]; }
44919const MachOper* storeF0Node::memory_operand() const { return _opnds[1]; }
44920const MachOper* storeF_immNode::memory_operand() const { return _opnds[1]; }
44921const MachOper* storeDNode::memory_operand() const { return _opnds[1]; }
44922const MachOper* storeD0_immNode::memory_operand() const { return _opnds[1]; }
44923const MachOper* storeD0Node::memory_operand() const { return _opnds[1]; }
44924const MachOper* cacheWBNode::memory_operand() const { return _opnds[1]; }
44925const MachOper* popCountI_memNode::memory_operand() const { return _opnds[1]; }
44926const MachOper* popCountL_memNode::memory_operand() const { return _opnds[1]; }
44927const MachOper* cmovI_memNode::memory_operand() const { return _opnds[4]; }
44928const MachOper* cmovI_memUNode::memory_operand() const { return _opnds[4]; }
44929const MachOper* cmovI_memUCFNode::memory_operand() const { return _opnds[4]; }
44930const MachOper* cmovL_memNode::memory_operand() const { return _opnds[4]; }
44931const MachOper* cmovL_memUNode::memory_operand() const { return _opnds[4]; }
44932const MachOper* cmovL_memUCFNode::memory_operand() const { return _opnds[4]; }
44933const MachOper* addI_rReg_memNode::memory_operand() const { return _opnds[2]; }
44934const MachOper* addI_rReg_mem_0Node::memory_operand() const { return _opnds[1]; }
44935const MachOper* addI_mem_rRegNode::memory_operand() const { return _opnds[1]; }
44936const MachOper* addI_mem_rReg_0Node::memory_operand() const { return _opnds[1]; }
44937const MachOper* addI_mem_immNode::memory_operand() const { return _opnds[1]; }
44938const MachOper* incI_memNode::memory_operand() const { return _opnds[1]; }
44939const MachOper* decI_memNode::memory_operand() const { return _opnds[1]; }
44940const MachOper* addL_rReg_memNode::memory_operand() const { return _opnds[2]; }
44941const MachOper* addL_rReg_mem_0Node::memory_operand() const { return _opnds[1]; }
44942const MachOper* addL_mem_rRegNode::memory_operand() const { return _opnds[1]; }
44943const MachOper* addL_mem_rReg_0Node::memory_operand() const { return _opnds[1]; }
44944const MachOper* addL_mem_immNode::memory_operand() const { return _opnds[1]; }
44945const MachOper* incL_memNode::memory_operand() const { return _opnds[1]; }
44946const MachOper* decL_memNode::memory_operand() const { return _opnds[1]; }
44947const MachOper* loadPLockedNode::memory_operand() const { return _opnds[1]; }
44948const MachOper* storePConditionalNode::memory_operand() const { return _opnds[1]; }
44949const MachOper* storeIConditionalNode::memory_operand() const { return _opnds[1]; }
44950const MachOper* storeLConditionalNode::memory_operand() const { return _opnds[1]; }
44951const MachOper* compareAndSwapPNode::memory_operand() const { return _opnds[1]; }
44952const MachOper* compareAndSwapP_0Node::memory_operand() const { return _opnds[1]; }
44953const MachOper* compareAndSwapLNode::memory_operand() const { return _opnds[1]; }
44954const MachOper* compareAndSwapL_0Node::memory_operand() const { return _opnds[1]; }
44955const MachOper* compareAndSwapINode::memory_operand() const { return _opnds[1]; }
44956const MachOper* compareAndSwapI_0Node::memory_operand() const { return _opnds[1]; }
44957const MachOper* compareAndSwapBNode::memory_operand() const { return _opnds[1]; }
44958const MachOper* compareAndSwapB_0Node::memory_operand() const { return _opnds[1]; }
44959const MachOper* compareAndSwapSNode::memory_operand() const { return _opnds[1]; }
44960const MachOper* compareAndSwapS_0Node::memory_operand() const { return _opnds[1]; }
44961const MachOper* compareAndSwapNNode::memory_operand() const { return _opnds[1]; }
44962const MachOper* compareAndSwapN_0Node::memory_operand() const { return _opnds[1]; }
44963const MachOper* compareAndExchangeBNode::memory_operand() const { return _opnds[1]; }
44964const MachOper* compareAndExchangeSNode::memory_operand() const { return _opnds[1]; }
44965const MachOper* compareAndExchangeINode::memory_operand() const { return _opnds[1]; }
44966const MachOper* compareAndExchangeLNode::memory_operand() const { return _opnds[1]; }
44967const MachOper* compareAndExchangeNNode::memory_operand() const { return _opnds[1]; }
44968const MachOper* compareAndExchangePNode::memory_operand() const { return _opnds[1]; }
44969const MachOper* xaddB_no_resNode::memory_operand() const { return _opnds[1]; }
44970const MachOper* xaddBNode::memory_operand() const { return _opnds[1]; }
44971const MachOper* xaddS_no_resNode::memory_operand() const { return _opnds[1]; }
44972const MachOper* xaddSNode::memory_operand() const { return _opnds[1]; }
44973const MachOper* xaddI_no_resNode::memory_operand() const { return _opnds[1]; }
44974const MachOper* xaddINode::memory_operand() const { return _opnds[1]; }
44975const MachOper* xaddL_no_resNode::memory_operand() const { return _opnds[1]; }
44976const MachOper* xaddLNode::memory_operand() const { return _opnds[1]; }
44977const MachOper* xchgBNode::memory_operand() const { return _opnds[1]; }
44978const MachOper* xchgSNode::memory_operand() const { return _opnds[1]; }
44979const MachOper* xchgINode::memory_operand() const { return _opnds[1]; }
44980const MachOper* xchgLNode::memory_operand() const { return _opnds[1]; }
44981const MachOper* xchgPNode::memory_operand() const { return _opnds[1]; }
44982const MachOper* xchgNNode::memory_operand() const { return _opnds[1]; }
44983const MachOper* subI_rReg_memNode::memory_operand() const { return _opnds[2]; }
44984const MachOper* subI_mem_rRegNode::memory_operand() const { return _opnds[1]; }
44985const MachOper* subI_mem_immNode::memory_operand() const { return _opnds[1]; }
44986const MachOper* subL_rReg_memNode::memory_operand() const { return _opnds[2]; }
44987const MachOper* subL_mem_rRegNode::memory_operand() const { return _opnds[1]; }
44988const MachOper* subL_mem_immNode::memory_operand() const { return _opnds[1]; }
44989const MachOper* negI_memNode::memory_operand() const { return _opnds[1]; }
44990const MachOper* negL_memNode::memory_operand() const { return _opnds[1]; }
44991const MachOper* mulI_memNode::memory_operand() const { return _opnds[2]; }
44992const MachOper* mulI_mem_0Node::memory_operand() const { return _opnds[1]; }
44993const MachOper* mulI_mem_immNode::memory_operand() const { return _opnds[1]; }
44994const MachOper* mulL_memNode::memory_operand() const { return _opnds[2]; }
44995const MachOper* mulL_mem_0Node::memory_operand() const { return _opnds[1]; }
44996const MachOper* mulL_mem_immNode::memory_operand() const { return _opnds[1]; }
44997const MachOper* salI_mem_1Node::memory_operand() const { return _opnds[1]; }
44998const MachOper* salI_mem_immNode::memory_operand() const { return _opnds[1]; }
44999const MachOper* salI_mem_CLNode::memory_operand() const { return _opnds[1]; }
45000const MachOper* sarI_mem_1Node::memory_operand() const { return _opnds[1]; }
45001const MachOper* sarI_mem_immNode::memory_operand() const { return _opnds[1]; }
45002const MachOper* sarI_mem_CLNode::memory_operand() const { return _opnds[1]; }
45003const MachOper* shrI_mem_1Node::memory_operand() const { return _opnds[1]; }
45004const MachOper* shrI_mem_immNode::memory_operand() const { return _opnds[1]; }
45005const MachOper* shrI_mem_CLNode::memory_operand() const { return _opnds[1]; }
45006const MachOper* salL_mem_1Node::memory_operand() const { return _opnds[1]; }
45007const MachOper* salL_mem_immNode::memory_operand() const { return _opnds[1]; }
45008const MachOper* salL_mem_CLNode::memory_operand() const { return _opnds[1]; }
45009const MachOper* sarL_mem_1Node::memory_operand() const { return _opnds[1]; }
45010const MachOper* sarL_mem_immNode::memory_operand() const { return _opnds[1]; }
45011const MachOper* sarL_mem_CLNode::memory_operand() const { return _opnds[1]; }
45012const MachOper* shrL_mem_1Node::memory_operand() const { return _opnds[1]; }
45013const MachOper* shrL_mem_immNode::memory_operand() const { return _opnds[1]; }
45014const MachOper* shrL_mem_CLNode::memory_operand() const { return _opnds[1]; }
45015const MachOper* andI_rReg_memNode::memory_operand() const { return _opnds[2]; }
45016const MachOper* andI_rReg_mem_0Node::memory_operand() const { return _opnds[1]; }
45017const MachOper* andB_mem_rRegNode::memory_operand() const { return _opnds[1]; }
45018const MachOper* andB_mem_rReg_0Node::memory_operand() const { return _opnds[1]; }
45019const MachOper* andI_mem_rRegNode::memory_operand() const { return _opnds[1]; }
45020const MachOper* andI_mem_rReg_0Node::memory_operand() const { return _opnds[1]; }
45021const MachOper* andI_mem_immNode::memory_operand() const { return _opnds[1]; }
45022const MachOper* andnI_rReg_rReg_memNode::memory_operand() const { return _opnds[3]; }
45023const MachOper* andnI_rReg_rReg_mem_0Node::memory_operand() const { return _opnds[1]; }
45024const MachOper* blsiI_rReg_memNode::memory_operand() const { return _opnds[2]; }
45025const MachOper* blsiI_rReg_mem_0Node::memory_operand() const { return _opnds[1]; }
45026const MachOper* blsmskI_rReg_memNode::memory_operand() const { return _opnds[1]; }
45027const MachOper* blsmskI_rReg_mem_0Node::memory_operand() const { return _opnds[1]; }
45028const MachOper* blsrI_rReg_memNode::memory_operand() const { return _opnds[1]; }
45029const MachOper* blsrI_rReg_mem_0Node::memory_operand() const { return _opnds[1]; }
45030const MachOper* orI_rReg_memNode::memory_operand() const { return _opnds[2]; }
45031const MachOper* orI_rReg_mem_0Node::memory_operand() const { return _opnds[1]; }
45032const MachOper* orB_mem_rRegNode::memory_operand() const { return _opnds[1]; }
45033const MachOper* orB_mem_rReg_0Node::memory_operand() const { return _opnds[1]; }
45034const MachOper* orI_mem_rRegNode::memory_operand() const { return _opnds[1]; }
45035const MachOper* orI_mem_rReg_0Node::memory_operand() const { return _opnds[1]; }
45036const MachOper* orI_mem_immNode::memory_operand() const { return _opnds[1]; }
45037const MachOper* xorI_rReg_memNode::memory_operand() const { return _opnds[2]; }
45038const MachOper* xorI_rReg_mem_0Node::memory_operand() const { return _opnds[1]; }
45039const MachOper* xorB_mem_rRegNode::memory_operand() const { return _opnds[1]; }
45040const MachOper* xorB_mem_rReg_0Node::memory_operand() const { return _opnds[1]; }
45041const MachOper* xorI_mem_rRegNode::memory_operand() const { return _opnds[1]; }
45042const MachOper* xorI_mem_rReg_0Node::memory_operand() const { return _opnds[1]; }
45043const MachOper* xorI_mem_immNode::memory_operand() const { return _opnds[1]; }
45044const MachOper* andL_rReg_memNode::memory_operand() const { return _opnds[2]; }
45045const MachOper* andL_rReg_mem_0Node::memory_operand() const { return _opnds[1]; }
45046const MachOper* andL_mem_rRegNode::memory_operand() const { return _opnds[1]; }
45047const MachOper* andL_mem_rReg_0Node::memory_operand() const { return _opnds[1]; }
45048const MachOper* andL_mem_immNode::memory_operand() const { return _opnds[1]; }
45049const MachOper* btrL_mem_immNode::memory_operand() const { return _opnds[1]; }
45050const MachOper* andnL_rReg_rReg_memNode::memory_operand() const { return _opnds[3]; }
45051const MachOper* andnL_rReg_rReg_mem_0Node::memory_operand() const { return _opnds[1]; }
45052const MachOper* blsiL_rReg_memNode::memory_operand() const { return _opnds[2]; }
45053const MachOper* blsiL_rReg_mem_0Node::memory_operand() const { return _opnds[1]; }
45054const MachOper* blsmskL_rReg_memNode::memory_operand() const { return _opnds[1]; }
45055const MachOper* blsmskL_rReg_mem_0Node::memory_operand() const { return _opnds[1]; }
45056const MachOper* blsrL_rReg_memNode::memory_operand() const { return _opnds[1]; }
45057const MachOper* blsrL_rReg_mem_0Node::memory_operand() const { return _opnds[1]; }
45058const MachOper* orL_rReg_memNode::memory_operand() const { return _opnds[2]; }
45059const MachOper* orL_rReg_mem_0Node::memory_operand() const { return _opnds[1]; }
45060const MachOper* orL_mem_rRegNode::memory_operand() const { return _opnds[1]; }
45061const MachOper* orL_mem_rReg_0Node::memory_operand() const { return _opnds[1]; }
45062const MachOper* orL_mem_immNode::memory_operand() const { return _opnds[1]; }
45063const MachOper* btsL_mem_immNode::memory_operand() const { return _opnds[1]; }
45064const MachOper* xorL_rReg_memNode::memory_operand() const { return _opnds[2]; }
45065const MachOper* xorL_rReg_mem_0Node::memory_operand() const { return _opnds[1]; }
45066const MachOper* xorL_mem_rRegNode::memory_operand() const { return _opnds[1]; }
45067const MachOper* xorL_mem_rReg_0Node::memory_operand() const { return _opnds[1]; }
45068const MachOper* xorL_mem_immNode::memory_operand() const { return _opnds[1]; }
45069const MachOper* cmpF_cc_memNode::memory_operand() const { return _opnds[2]; }
45070const MachOper* cmpF_cc_memCFNode::memory_operand() const { return _opnds[2]; }
45071const MachOper* cmpD_cc_memNode::memory_operand() const { return _opnds[2]; }
45072const MachOper* cmpD_cc_memCFNode::memory_operand() const { return _opnds[2]; }
45073const MachOper* cmpF_memNode::memory_operand() const { return _opnds[2]; }
45074const MachOper* cmpD_memNode::memory_operand() const { return _opnds[2]; }
45075const MachOper* convF2D_reg_memNode::memory_operand() const { return _opnds[1]; }
45076const MachOper* convD2F_reg_memNode::memory_operand() const { return _opnds[1]; }
45077const MachOper* convI2F_reg_memNode::memory_operand() const { return _opnds[1]; }
45078const MachOper* convI2D_reg_memNode::memory_operand() const { return _opnds[1]; }
45079const MachOper* convL2F_reg_memNode::memory_operand() const { return _opnds[1]; }
45080const MachOper* convL2D_reg_memNode::memory_operand() const { return _opnds[1]; }
45081const MachOper* convI2L_reg_mem_zexNode::memory_operand() const { return _opnds[1]; }
45082const MachOper* compI_rReg_memNode::memory_operand() const { return _opnds[2]; }
45083const MachOper* testI_reg_memNode::memory_operand() const { return _opnds[2]; }
45084const MachOper* testI_reg_mem_0Node::memory_operand() const { return _opnds[1]; }
45085const MachOper* compU_rReg_memNode::memory_operand() const { return _opnds[2]; }
45086const MachOper* compP_rReg_memNode::memory_operand() const { return _opnds[2]; }
45087const MachOper* compP_mem_rRegNode::memory_operand() const { return _opnds[2]; }
45088const MachOper* testP_memNode::memory_operand() const { return _opnds[1]; }
45089const MachOper* testP_mem_reg0Node::memory_operand() const { return _opnds[1]; }
45090const MachOper* compN_rReg_memNode::memory_operand() const { return _opnds[2]; }
45091const MachOper* compN_mem_immNode::memory_operand() const { return _opnds[2]; }
45092const MachOper* compN_mem_imm_klassNode::memory_operand() const { return _opnds[2]; }
45093const MachOper* testN_memNode::memory_operand() const { return _opnds[1]; }
45094const MachOper* testN_mem_reg0Node::memory_operand() const { return _opnds[1]; }
45095const MachOper* compL_rReg_memNode::memory_operand() const { return _opnds[2]; }
45096const MachOper* testL_reg_memNode::memory_operand() const { return _opnds[2]; }
45097const MachOper* testL_reg_mem_0Node::memory_operand() const { return _opnds[1]; }
45098const MachOper* testL_reg_mem2Node::memory_operand() const { return _opnds[2]; }
45099const MachOper* testL_reg_mem2_0Node::memory_operand() const { return _opnds[1]; }
45100const MachOper* compUL_rReg_memNode::memory_operand() const { return _opnds[2]; }
45101const MachOper* compB_mem_immNode::memory_operand() const { return _opnds[1]; }
45102const MachOper* testUB_mem_immNode::memory_operand() const { return _opnds[1]; }
45103const MachOper* testB_mem_immNode::memory_operand() const { return _opnds[1]; }
45104const MachOper* addF_memNode::memory_operand() const { return _opnds[2]; }
45105const MachOper* addF_mem_0Node::memory_operand() const { return _opnds[1]; }
45106const MachOper* addF_reg_memNode::memory_operand() const { return _opnds[2]; }
45107const MachOper* addF_reg_mem_0Node::memory_operand() const { return _opnds[1]; }
45108const MachOper* addD_memNode::memory_operand() const { return _opnds[2]; }
45109const MachOper* addD_mem_0Node::memory_operand() const { return _opnds[1]; }
45110const MachOper* addD_reg_memNode::memory_operand() const { return _opnds[2]; }
45111const MachOper* addD_reg_mem_0Node::memory_operand() const { return _opnds[1]; }
45112const MachOper* subF_memNode::memory_operand() const { return _opnds[2]; }
45113const MachOper* subF_reg_memNode::memory_operand() const { return _opnds[2]; }
45114const MachOper* subD_memNode::memory_operand() const { return _opnds[2]; }
45115const MachOper* subD_reg_memNode::memory_operand() const { return _opnds[2]; }
45116const MachOper* mulF_memNode::memory_operand() const { return _opnds[2]; }
45117const MachOper* mulF_mem_0Node::memory_operand() const { return _opnds[1]; }
45118const MachOper* mulF_reg_memNode::memory_operand() const { return _opnds[2]; }
45119const MachOper* mulF_reg_mem_0Node::memory_operand() const { return _opnds[1]; }
45120const MachOper* mulD_memNode::memory_operand() const { return _opnds[2]; }
45121const MachOper* mulD_mem_0Node::memory_operand() const { return _opnds[1]; }
45122const MachOper* mulD_reg_memNode::memory_operand() const { return _opnds[2]; }
45123const MachOper* mulD_reg_mem_0Node::memory_operand() const { return _opnds[1]; }
45124const MachOper* divF_memNode::memory_operand() const { return _opnds[2]; }
45125const MachOper* divF_reg_memNode::memory_operand() const { return _opnds[2]; }
45126const MachOper* divD_memNode::memory_operand() const { return _opnds[2]; }
45127const MachOper* divD_reg_memNode::memory_operand() const { return _opnds[2]; }
45128const MachOper* roundD_memNode::memory_operand() const { return _opnds[1]; }
45129const MachOper* vroundD_memNode::memory_operand() const { return _opnds[1]; }
45130const MachOper* vround8D_memNode::memory_operand() const { return _opnds[1]; }
45131const MachOper* loadVNode::memory_operand() const { return _opnds[1]; }
45132const MachOper* storeVNode::memory_operand() const { return _opnds[1]; }
45133const MachOper* gatherNode::memory_operand() const { return _opnds[1]; }
45134const MachOper* evgatherNode::memory_operand() const { return _opnds[1]; }
45135const MachOper* evgather_maskedNode::memory_operand() const { return _opnds[1]; }
45136const MachOper* scatterNode::memory_operand() const { return _opnds[1]; }
45137const MachOper* scatter_maskedNode::memory_operand() const { return _opnds[1]; }
45138const MachOper* ReplB_memNode::memory_operand() const { return _opnds[1]; }
45139const MachOper* ReplS_memNode::memory_operand() const { return _opnds[1]; }
45140const MachOper* ReplI_memNode::memory_operand() const { return _opnds[1]; }
45141const MachOper* ReplL_memNode::memory_operand() const { return _opnds[1]; }
45142const MachOper* ReplF_memNode::memory_operand() const { return _opnds[1]; }
45143const MachOper* ReplD_memNode::memory_operand() const { return _opnds[1]; }
45144const MachOper* vaddB_memNode::memory_operand() const { return _opnds[2]; }
45145const MachOper* vaddB_mem_0Node::memory_operand() const { return _opnds[1]; }
45146const MachOper* vaddS_memNode::memory_operand() const { return _opnds[2]; }
45147const MachOper* vaddS_mem_0Node::memory_operand() const { return _opnds[1]; }
45148const MachOper* vaddI_memNode::memory_operand() const { return _opnds[2]; }
45149const MachOper* vaddI_mem_0Node::memory_operand() const { return _opnds[1]; }
45150const MachOper* vaddL_memNode::memory_operand() const { return _opnds[2]; }
45151const MachOper* vaddL_mem_0Node::memory_operand() const { return _opnds[1]; }
45152const MachOper* vaddF_memNode::memory_operand() const { return _opnds[2]; }
45153const MachOper* vaddF_mem_0Node::memory_operand() const { return _opnds[1]; }
45154const MachOper* vaddD_memNode::memory_operand() const { return _opnds[2]; }
45155const MachOper* vaddD_mem_0Node::memory_operand() const { return _opnds[1]; }
45156const MachOper* vsubB_memNode::memory_operand() const { return _opnds[2]; }
45157const MachOper* vsubS_memNode::memory_operand() const { return _opnds[2]; }
45158const MachOper* vsubI_memNode::memory_operand() const { return _opnds[2]; }
45159const MachOper* vsubL_memNode::memory_operand() const { return _opnds[2]; }
45160const MachOper* vsubF_memNode::memory_operand() const { return _opnds[2]; }
45161const MachOper* vsubD_memNode::memory_operand() const { return _opnds[2]; }
45162const MachOper* vmulS_memNode::memory_operand() const { return _opnds[2]; }
45163const MachOper* vmulS_mem_0Node::memory_operand() const { return _opnds[1]; }
45164const MachOper* vmulI_memNode::memory_operand() const { return _opnds[2]; }
45165const MachOper* vmulI_mem_0Node::memory_operand() const { return _opnds[1]; }
45166const MachOper* vmulL_memNode::memory_operand() const { return _opnds[2]; }
45167const MachOper* vmulL_mem_0Node::memory_operand() const { return _opnds[1]; }
45168const MachOper* vmulF_memNode::memory_operand() const { return _opnds[2]; }
45169const MachOper* vmulF_mem_0Node::memory_operand() const { return _opnds[1]; }
45170const MachOper* vmulD_memNode::memory_operand() const { return _opnds[2]; }
45171const MachOper* vmulD_mem_0Node::memory_operand() const { return _opnds[1]; }
45172const MachOper* vdivF_memNode::memory_operand() const { return _opnds[2]; }
45173const MachOper* vdivD_memNode::memory_operand() const { return _opnds[2]; }
45174const MachOper* vsqrtF_memNode::memory_operand() const { return _opnds[1]; }
45175const MachOper* vsqrtD_memNode::memory_operand() const { return _opnds[1]; }
45176const MachOper* vand_memNode::memory_operand() const { return _opnds[2]; }
45177const MachOper* vand_mem_0Node::memory_operand() const { return _opnds[1]; }
45178const MachOper* vor_memNode::memory_operand() const { return _opnds[2]; }
45179const MachOper* vor_mem_0Node::memory_operand() const { return _opnds[1]; }
45180const MachOper* vxor_memNode::memory_operand() const { return _opnds[2]; }
45181const MachOper* vxor_mem_0Node::memory_operand() const { return _opnds[1]; }
45182const MachOper* vfmaF_memNode::memory_operand() const { return _opnds[3]; }
45183const MachOper* vfmaD_memNode::memory_operand() const { return _opnds[3]; }
45184const MachOper* vpternlog_memNode::memory_operand() const { return _opnds[3]; }
45185const MachOper* vmasked_load64Node::memory_operand() const { return _opnds[1]; }
45186const MachOper* vmasked_store64Node::memory_operand() const { return _opnds[1]; }
45187const MachOper* vadd_mem_maskedNode::memory_operand() const { return _opnds[2]; }
45188const MachOper* vadd_mem_masked_0Node::memory_operand() const { return _opnds[2]; }
45189const MachOper* vadd_mem_masked_1Node::memory_operand() const { return _opnds[2]; }
45190const MachOper* vadd_mem_masked_2Node::memory_operand() const { return _opnds[2]; }
45191const MachOper* vadd_mem_masked_3Node::memory_operand() const { return _opnds[2]; }
45192const MachOper* vadd_mem_masked_4Node::memory_operand() const { return _opnds[2]; }
45193const MachOper* vxor_mem_maskedNode::memory_operand() const { return _opnds[2]; }
45194const MachOper* vor_mem_maskedNode::memory_operand() const { return _opnds[2]; }
45195const MachOper* vand_mem_maskedNode::memory_operand() const { return _opnds[2]; }
45196const MachOper* vsub_mem_maskedNode::memory_operand() const { return _opnds[2]; }
45197const MachOper* vsub_mem_masked_0Node::memory_operand() const { return _opnds[2]; }
45198const MachOper* vsub_mem_masked_1Node::memory_operand() const { return _opnds[2]; }
45199const MachOper* vsub_mem_masked_2Node::memory_operand() const { return _opnds[2]; }
45200const MachOper* vsub_mem_masked_3Node::memory_operand() const { return _opnds[2]; }
45201const MachOper* vsub_mem_masked_4Node::memory_operand() const { return _opnds[2]; }
45202const MachOper* vmul_mem_maskedNode::memory_operand() const { return _opnds[2]; }
45203const MachOper* vmul_mem_masked_0Node::memory_operand() const { return _opnds[2]; }
45204const MachOper* vmul_mem_masked_1Node::memory_operand() const { return _opnds[2]; }
45205const MachOper* vmul_mem_masked_2Node::memory_operand() const { return _opnds[2]; }
45206const MachOper* vmul_mem_masked_3Node::memory_operand() const { return _opnds[2]; }
45207const MachOper* vdiv_mem_maskedNode::memory_operand() const { return _opnds[2]; }
45208const MachOper* vdiv_mem_masked_0Node::memory_operand() const { return _opnds[2]; }
45209const MachOper* vlshift_mem_maskedNode::memory_operand() const { return _opnds[2]; }
45210const MachOper* vlshift_mem_masked_0Node::memory_operand() const { return _opnds[2]; }
45211const MachOper* vlshift_mem_masked_1Node::memory_operand() const { return _opnds[2]; }
45212const MachOper* vrshift_mem_maskedNode::memory_operand() const { return _opnds[2]; }
45213const MachOper* vrshift_mem_masked_0Node::memory_operand() const { return _opnds[2]; }
45214const MachOper* vrshift_mem_masked_1Node::memory_operand() const { return _opnds[2]; }
45215const MachOper* vurshift_mem_maskedNode::memory_operand() const { return _opnds[2]; }
45216const MachOper* vurshift_mem_masked_0Node::memory_operand() const { return _opnds[2]; }
45217const MachOper* vurshift_mem_masked_1Node::memory_operand() const { return _opnds[2]; }
45218const MachOper* vmaxv_mem_maskedNode::memory_operand() const { return _opnds[2]; }
45219const MachOper* vminv_mem_maskedNode::memory_operand() const { return _opnds[2]; }
45220const MachOper* vfma_mem_maskedNode::memory_operand() const { return _opnds[3]; }
45221const MachOper* vfma_mem_masked_0Node::memory_operand() const { return _opnds[3]; }
45222const MachOper* compareAndSwapP_shenandoahNode::memory_operand() const { return _opnds[1]; }
45223const MachOper* compareAndSwapP_shenandoah_0Node::memory_operand() const { return _opnds[1]; }
45224const MachOper* compareAndSwapN_shenandoahNode::memory_operand() const { return _opnds[1]; }
45225const MachOper* compareAndSwapN_shenandoah_0Node::memory_operand() const { return _opnds[1]; }
45226const MachOper* compareAndExchangeN_shenandoahNode::memory_operand() const { return _opnds[1]; }
45227const MachOper* compareAndExchangeP_shenandoahNode::memory_operand() const { return _opnds[1]; }
45228const MachOper* zLoadPNode::memory_operand() const { return _opnds[1]; }
45229const MachOper* zCompareAndExchangePNode::memory_operand() const { return _opnds[1]; }
45230const MachOper* zCompareAndSwapPNode::memory_operand() const { return _opnds[1]; }
45231const MachOper* zCompareAndSwapP_0Node::memory_operand() const { return _opnds[1]; }
45232const MachOper* zXChgPNode::memory_operand() const { return _opnds[1]; }
45233
45234
45235const bool Matcher::has_match_rule(int opcode) {
45236 assert(_last_machine_leaf < opcode && opcode < _last_opcode, "opcode in range")do { if (!(_last_machine_leaf < opcode && opcode <
_last_opcode)) { (*g_assert_poison) = 'X';; report_vm_error(
"ad_x86.cpp", 45235, "assert(" "_last_machine_leaf < opcode && opcode < _last_opcode"
") failed", "opcode in range"); ::breakpoint(); } } while (0
);
45237 return _hasMatchRule[opcode];
45238}
45239
45240const bool Matcher::_hasMatchRule[_last_opcode] = {
45241 false, // Node
45242 false, // Set
45243 false, // RegN
45244 false, // RegI
45245 false, // RegP
45246 false, // RegF
45247 false, // RegD
45248 false, // RegL
45249 false, // VecA
45250 false, // VecS
45251 false, // VecD
45252 false, // VecX
45253 false, // VecY
45254 false, // VecZ
45255 false, // RegVectMask
45256 false, // RegFlags
45257 false, // _last_machine_leaf
45258 true , // AbsD
45259 true , // AbsF
45260 true , // AbsI
45261 true , // AbsL
45262 true , // AddD
45263 true , // AddF
45264 true , // AddI
45265 true , // AddL
45266 true , // AddP
45267 false, // Allocate
45268 false, // AllocateArray
45269 true , // AndI
45270 true , // AndL
45271 false, // ArrayCopy
45272 true , // AryEq
45273 false, // AtanD
45274 true , // Binary
45275 false, // Blackhole
45276 true , // Bool
45277 false, // BoxLock
45278 true , // ReverseBytesI
45279 true , // ReverseBytesL
45280 true , // ReverseBytesUS
45281 true , // ReverseBytesS
45282 false, // CProj
45283 true , // CacheWB
45284 true , // CacheWBPreSync
45285 true , // CacheWBPostSync
45286 true , // CallDynamicJava
45287 false, // CallJava
45288 true , // CallLeaf
45289 true , // CallLeafNoFP
45290 true , // CallLeafVector
45291 true , // CallRuntime
45292 true , // CallNative
45293 true , // CallStaticJava
45294 true , // CastDD
45295 true , // CastFF
45296 true , // CastII
45297 true , // CastLL
45298 true , // CastVV
45299 true , // CastX2P
45300 true , // CastP2X
45301 true , // CastPP
45302 false, // Catch
45303 false, // CatchProj
45304 true , // CheckCastPP
45305 true , // ClearArray
45306 false, // ConstraintCast
45307 true , // CMoveD
45308 true , // CMoveVD
45309 true , // CMoveF
45310 true , // CMoveVF
45311 true , // CMoveI
45312 true , // CMoveL
45313 true , // CMoveP
45314 true , // CMoveN
45315 true , // CmpN
45316 true , // CmpD
45317 true , // CmpD3
45318 true , // CmpF
45319 true , // CmpF3
45320 true , // CmpI
45321 true , // CmpL
45322 true , // CmpL3
45323 true , // CmpLTMask
45324 true , // CmpP
45325 true , // CmpU
45326 true , // CmpUL
45327 true , // CompareAndSwapB
45328 true , // CompareAndSwapS
45329 true , // CompareAndSwapI
45330 true , // CompareAndSwapL
45331 true , // CompareAndSwapP
45332 true , // CompareAndSwapN
45333 true , // WeakCompareAndSwapB
45334 true , // WeakCompareAndSwapS
45335 true , // WeakCompareAndSwapI
45336 true , // WeakCompareAndSwapL
45337 true , // WeakCompareAndSwapP
45338 true , // WeakCompareAndSwapN
45339 true , // CompareAndExchangeB
45340 true , // CompareAndExchangeS
45341 true , // CompareAndExchangeI
45342 true , // CompareAndExchangeL
45343 true , // CompareAndExchangeP
45344 true , // CompareAndExchangeN
45345 true , // GetAndAddB
45346 true , // GetAndAddS
45347 true , // GetAndAddI
45348 true , // GetAndAddL
45349 true , // GetAndSetB
45350 true , // GetAndSetS
45351 true , // GetAndSetI
45352 true , // GetAndSetL
45353 true , // GetAndSetP
45354 true , // GetAndSetN
45355 false, // Con
45356 true , // ConN
45357 true , // ConNKlass
45358 true , // ConD
45359 true , // ConF
45360 true , // ConI
45361 true , // ConL
45362 true , // ConP
45363 true , // Conv2B
45364 true , // ConvD2F
45365 true , // ConvD2I
45366 true , // ConvD2L
45367 true , // ConvF2D
45368 true , // ConvF2I
45369 true , // ConvF2L
45370 true , // ConvI2D
45371 true , // ConvI2F
45372 true , // ConvI2L
45373 true , // ConvL2D
45374 true , // ConvL2F
45375 true , // ConvL2I
45376 false, // CountedLoop
45377 true , // CountedLoopEnd
45378 false, // OuterStripMinedLoop
45379 false, // OuterStripMinedLoopEnd
45380 false, // LongCountedLoop
45381 false, // LongCountedLoopEnd
45382 true , // CountLeadingZerosI
45383 true , // CountLeadingZerosL
45384 true , // CountTrailingZerosI
45385 true , // CountTrailingZerosL
45386 true , // CreateEx
45387 true , // DecodeN
45388 true , // DecodeNKlass
45389 true , // DivD
45390 true , // DivF
45391 true , // DivI
45392 true , // DivL
45393 false, // DivMod
45394 true , // DivModI
45395 true , // DivModL
45396 true , // EncodeISOArray
45397 true , // EncodeP
45398 true , // EncodePKlass
45399 true , // FastLock
45400 true , // FastUnlock
45401 true , // FmaD
45402 true , // FmaF
45403 true , // Goto
45404 true , // Halt
45405 true , // HasNegatives
45406 true , // If
45407 false, // RangeCheck
45408 false, // IfFalse
45409 false, // IfTrue
45410 false, // Initialize
45411 false, // JProj
45412 true , // Jump
45413 false, // JumpProj
45414 true , // LShiftI
45415 true , // LShiftL
45416 true , // LoadB
45417 true , // LoadUB
45418 true , // LoadUS
45419 true , // LoadD
45420 false, // LoadD_unaligned
45421 true , // LoadF
45422 true , // LoadI
45423 true , // LoadKlass
45424 true , // LoadNKlass
45425 true , // LoadL
45426 false, // LoadL_unaligned
45427 true , // LoadPLocked
45428 true , // LoadP
45429 true , // LoadN
45430 true , // LoadRange
45431 true , // LoadS
45432 false, // Lock
45433 false, // Loop
45434 false, // LoopLimit
45435 false, // Mach
45436 false, // MachNullCheck
45437 false, // MachProj
45438 true , // MulAddS2I
45439 true , // MaxI
45440 false, // MaxL
45441 true , // MaxD
45442 true , // MaxF
45443 true , // MemBarAcquire
45444 true , // LoadFence
45445 true , // SetVectMaskI
45446 true , // MemBarAcquireLock
45447 false, // MemBarCPUOrder
45448 true , // MemBarRelease
45449 true , // StoreFence
45450 true , // StoreStoreFence
45451 true , // MemBarReleaseLock
45452 true , // MemBarVolatile
45453 true , // MemBarStoreStore
45454 false, // MergeMem
45455 true , // MinI
45456 false, // MinL
45457 true , // MinF
45458 true , // MinD
45459 false, // ModD
45460 false, // ModF
45461 true , // ModI
45462 true , // ModL
45463 true , // MoveI2F
45464 true , // MoveF2I
45465 true , // MoveL2D
45466 true , // MoveD2L
45467 true , // MulD
45468 true , // MulF
45469 true , // MulHiL
45470 true , // UMulHiL
45471 true , // MulI
45472 true , // MulL
45473 false, // Multi
45474 true , // NegI
45475 true , // NegL
45476 true , // NegD
45477 true , // NegF
45478 false, // NeverBranch
45479 true , // OnSpinWait
45480 false, // Opaque1
45481 false, // OpaqueLoopInit
45482 false, // OpaqueLoopStride
45483 false, // Opaque2
45484 false, // Opaque3
45485 false, // Opaque4
45486 false, // ProfileBoolean
45487 true , // OrI
45488 true , // OrL
45489 true , // OverflowAddI
45490 true , // OverflowSubI
45491 true , // OverflowMulI
45492 true , // OverflowAddL
45493 true , // OverflowSubL
45494 true , // OverflowMulL
45495 false, // PCTable
45496 false, // Parm
45497 true , // PartialSubtypeCheck
45498 false, // SubTypeCheck
45499 false, // Phi
45500 true , // PopCountI
45501 true , // PopCountL
45502 true , // PopCountVI
45503 true , // PrefetchAllocation
45504 false, // Proj
45505 true , // RShiftI
45506 true , // RShiftL
45507 false, // Region
45508 true , // Rethrow
45509 true , // Return
45510 false, // Root
45511 false, // RoundDouble
45512 true , // RoundDoubleMode
45513 true , // RoundDoubleModeV
45514 false, // RoundFloat
45515 true , // RotateLeft
45516 true , // RotateLeftV
45517 true , // RotateRight
45518 true , // RotateRightV
45519 true , // SafePoint
45520 false, // SafePointScalarObject
45521 true , // ShenandoahCompareAndExchangeP
45522 true , // ShenandoahCompareAndExchangeN
45523 true , // ShenandoahCompareAndSwapN
45524 true , // ShenandoahCompareAndSwapP
45525 true , // ShenandoahWeakCompareAndSwapN
45526 true , // ShenandoahWeakCompareAndSwapP
45527 false, // ShenandoahIUBarrier
45528 false, // ShenandoahLoadReferenceBarrier
45529 false, // SCMemProj
45530 true , // CopySignD
45531 true , // CopySignF
45532 true , // SignumD
45533 true , // SignumF
45534 true , // SqrtD
45535 true , // SqrtF
45536 false, // Start
45537 false, // StartOSR
45538 true , // StoreB
45539 true , // StoreC
45540 true , // StoreCM
45541 true , // StorePConditional
45542 true , // StoreIConditional
45543 true , // StoreLConditional
45544 true , // StoreD
45545 true , // StoreF
45546 true , // StoreI
45547 true , // StoreL
45548 true , // StoreP
45549 true , // StoreN
45550 true , // StoreNKlass
45551 true , // StrComp
45552 true , // StrCompressedCopy
45553 true , // StrEquals
45554 true , // StrIndexOf
45555 true , // StrIndexOfChar
45556 true , // StrInflatedCopy
45557 true , // SubD
45558 true , // SubF
45559 true , // SubI
45560 true , // SubL
45561 true , // TailCall
45562 true , // TailJump
45563 true , // MacroLogicV
45564 true , // ThreadLocal
45565 false, // Unlock
45566 false, // URShiftB
45567 false, // URShiftS
45568 true , // URShiftI
45569 true , // URShiftL
45570 true , // XorI
45571 true , // XorL
45572 false, // Vector
45573 true , // AddVB
45574 true , // AddVS
45575 true , // AddVI
45576 true , // AddReductionVI
45577 true , // AddVL
45578 true , // AddReductionVL
45579 true , // AddVF
45580 true , // AddReductionVF
45581 true , // AddVD
45582 true , // AddReductionVD
45583 true , // SubVB
45584 true , // SubVS
45585 true , // SubVI
45586 true , // SubVL
45587 true , // SubVF
45588 true , // SubVD
45589 true , // MulVB
45590 true , // MulVS
45591 true , // MulVI
45592 true , // MulReductionVI
45593 true , // MulVL
45594 true , // MulReductionVL
45595 true , // MulVF
45596 true , // MulReductionVF
45597 true , // MulVD
45598 true , // MulReductionVD
45599 true , // MulAddVS2VI
45600 true , // FmaVD
45601 true , // FmaVF
45602 true , // DivVF
45603 true , // DivVD
45604 true , // AbsVB
45605 true , // AbsVS
45606 true , // AbsVI
45607 true , // AbsVL
45608 true , // AbsVF
45609 true , // AbsVD
45610 false, // NegVI
45611 true , // NegVF
45612 true , // NegVD
45613 true , // SqrtVD
45614 true , // SqrtVF
45615 true , // LShiftCntV
45616 true , // RShiftCntV
45617 true , // LShiftVB
45618 true , // LShiftVS
45619 true , // LShiftVI
45620 true , // LShiftVL
45621 true , // RShiftVB
45622 true , // RShiftVS
45623 true , // RShiftVI
45624 true , // RShiftVL
45625 true , // URShiftVB
45626 true , // URShiftVS
45627 true , // URShiftVI
45628 true , // URShiftVL
45629 true , // AndV
45630 true , // AndReductionV
45631 true , // OrV
45632 true , // OrReductionV
45633 true , // XorV
45634 true , // XorReductionV
45635 true , // MinV
45636 true , // MaxV
45637 true , // MinReductionV
45638 true , // MaxReductionV
45639 true , // LoadVector
45640 true , // LoadVectorGather
45641 true , // LoadVectorGatherMasked
45642 true , // StoreVector
45643 true , // StoreVectorScatter
45644 true , // StoreVectorScatterMasked
45645 true , // LoadVectorMasked
45646 true , // StoreVectorMasked
45647 true , // VectorCmpMasked
45648 true , // VectorMaskGen
45649 false, // VectorMaskOp
45650 true , // VectorMaskTrueCount
45651 true , // VectorMaskFirstTrue
45652 true , // VectorMaskLastTrue
45653 true , // VectorMaskToLong
45654 true , // VectorLongToMask
45655 false, // Pack
45656 false, // PackB
45657 false, // PackS
45658 false, // PackI
45659 false, // PackL
45660 false, // PackF
45661 false, // PackD
45662 false, // Pack2L
45663 false, // Pack2D
45664 true , // ReplicateB
45665 true , // ReplicateS
45666 true , // ReplicateI
45667 true , // ReplicateL
45668 true , // ReplicateF
45669 true , // ReplicateD
45670 false, // Extract
45671 true , // ExtractB
45672 false, // ExtractUB
45673 false, // ExtractC
45674 true , // ExtractS
45675 true , // ExtractI
45676 true , // ExtractL
45677 true , // ExtractF
45678 true , // ExtractD
45679 false, // Digit
45680 false, // LowerCase
45681 false, // UpperCase
45682 false, // Whitespace
45683 false, // VectorBox
45684 false, // VectorBoxAllocate
45685 false, // VectorUnbox
45686 false, // VectorMaskWrapper
45687 true , // VectorMaskCmp
45688 true , // VectorMaskCast
45689 true , // VectorTest
45690 true , // VectorBlend
45691 true , // VectorRearrange
45692 true , // VectorLoadMask
45693 true , // VectorLoadShuffle
45694 true , // VectorLoadConst
45695 true , // VectorStoreMask
45696 true , // VectorReinterpret
45697 false, // VectorCast
45698 true , // VectorCastB2X
45699 true , // VectorCastS2X
45700 true , // VectorCastI2X
45701 true , // VectorCastL2X
45702 true , // VectorCastF2X
45703 true , // VectorCastD2X
45704 true , // VectorInsert
45705 true , // MaskAll
45706 true , // AndVMask
45707 true , // OrVMask
45708 true // XorVMask
45709};
45710
45711
45712int Compile::sync_stack_slots() const { return 2; }
45713
45714uint Matcher::stack_alignment_in_bytes() { return StackAlignmentInBytes; }
45715
45716OptoReg::Name Matcher::return_addr() const { return OptoReg::stack2reg(- 2 +
45717 align_up((Compile::current()->in_preserve_stack_slots() +
45718 Compile::current()->fixed_slots()),
45719 stack_alignment_in_slots())); }
45720
45721uint Compile::varargs_C_out_slots_killed() const { return frame::arg_reg_save_area_bytes/BytesPerInt; }
45722
45723OptoRegPair Matcher::return_value(uint ideal_reg) {
45724
45725#line 2834 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
45726
45727 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,do { if (!(ideal_reg >= Op_RegI && ideal_reg <=
Op_RegL)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 2836, "assert(" "ideal_reg >= Op_RegI && ideal_reg <= Op_RegL"
") failed", "only return normal values"); ::breakpoint(); } }
while (0)
45728 "only return normal values")do { if (!(ideal_reg >= Op_RegI && ideal_reg <=
Op_RegL)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 2836, "assert(" "ideal_reg >= Op_RegI && ideal_reg <= Op_RegL"
") failed", "only return normal values"); ::breakpoint(); } }
while (0);
45729
45730 static const int lo[Op_RegL + 1] = {
45731 0,
45732 0,
45733 RAX_num, // Op_RegN
45734 RAX_num, // Op_RegI
45735 RAX_num, // Op_RegP
45736 XMM0_num, // Op_RegF
45737 XMM0_num, // Op_RegD
45738 RAX_num // Op_RegL
45739 };
45740 static const int hi[Op_RegL + 1] = {
45741 0,
45742 0,
45743 OptoReg::Bad, // Op_RegN
45744 OptoReg::Bad, // Op_RegI
45745 RAX_H_num, // Op_RegP
45746 OptoReg::Bad, // Op_RegF
45747 XMM0b_num, // Op_RegD
45748 RAX_H_num // Op_RegL
45749 };
45750 // Excluded flags and vector registers.
45751 assert(ARRAY_SIZE(hi) == _last_machine_leaf - 8, "missing type")do { if (!(sizeof(array_size_impl(hi)) == _last_machine_leaf -
8)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 2859, "assert(" "sizeof(array_size_impl(hi)) == _last_machine_leaf - 8"
") failed", "missing type"); ::breakpoint(); } } while (0);
45752 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
45753
45754#line 45754 "ad_x86.cpp"
45755
45756}
45757
45758OptoRegPair Matcher::c_return_value(uint ideal_reg) {
45759
45760#line 2834 "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
45761
45762 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,do { if (!(ideal_reg >= Op_RegI && ideal_reg <=
Op_RegL)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 2836, "assert(" "ideal_reg >= Op_RegI && ideal_reg <= Op_RegL"
") failed", "only return normal values"); ::breakpoint(); } }
while (0)
45763 "only return normal values")do { if (!(ideal_reg >= Op_RegI && ideal_reg <=
Op_RegL)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 2836, "assert(" "ideal_reg >= Op_RegI && ideal_reg <= Op_RegL"
") failed", "only return normal values"); ::breakpoint(); } }
while (0);
45764
45765 static const int lo[Op_RegL + 1] = {
45766 0,
45767 0,
45768 RAX_num, // Op_RegN
45769 RAX_num, // Op_RegI
45770 RAX_num, // Op_RegP
45771 XMM0_num, // Op_RegF
45772 XMM0_num, // Op_RegD
45773 RAX_num // Op_RegL
45774 };
45775 static const int hi[Op_RegL + 1] = {
45776 0,
45777 0,
45778 OptoReg::Bad, // Op_RegN
45779 OptoReg::Bad, // Op_RegI
45780 RAX_H_num, // Op_RegP
45781 OptoReg::Bad, // Op_RegF
45782 XMM0b_num, // Op_RegD
45783 RAX_H_num // Op_RegL
45784 };
45785 // Excluded flags and vector registers.
45786 assert(ARRAY_SIZE(hi) == _last_machine_leaf - 8, "missing type")do { if (!(sizeof(array_size_impl(hi)) == _last_machine_leaf -
8)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/x86_64.ad"
, 2859, "assert(" "sizeof(array_size_impl(hi)) == _last_machine_leaf - 8"
") failed", "missing type"); ::breakpoint(); } } while (0);
45787 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
45788
45789#line 45789 "ad_x86.cpp"
45790
45791}
45792
45793OptoReg::Name Matcher::inline_cache_reg() { return OptoReg::Name(RAX_num); }
45794
45795int Matcher::inline_cache_reg_encode() { return _regEncode[inline_cache_reg()]; }
45796
45797OptoReg::Name Matcher::interpreter_frame_pointer_reg() { return OptoReg::Name(RBP_num); }
45798
45799OptoReg::Name Matcher::c_frame_pointer() const { return OptoReg::Name(RSP_num); }
45800
45801// Number of callee-save + always-save registers
45802int Matcher::number_of_saved_registers() {
45803 return 0;
45804};
45805
45806bool Compile::needs_deep_clone_jvms() { return false; }
45807
45808// Check consistency of C++ compilation with ADLC options:
45809// Check adlc -DLINUX=1
45810#ifndef LINUX1
45811# error "LINUX must be defined"
45812#endif // LINUX
45813// Check adlc -D_GNU_SOURCE=1
45814#ifndef _GNU_SOURCE1
45815# error "_GNU_SOURCE must be defined"
45816#endif // _GNU_SOURCE
45817// Check adlc -DAMD64=1
45818#ifndef AMD641
45819# error "AMD64 must be defined"
45820#endif // AMD64
45821// Check adlc -D_LP64=1
45822#ifndef _LP641
45823# error "_LP64 must be defined"
45824#endif // _LP64