| File: | jdk/src/hotspot/cpu/x86/assembler_x86.cpp |
| Warning: | line 11708, column 33 Called C++ object pointer is null |
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| 1 | /* | |||
| 2 | * Copyright (c) 1997, 2021, Oracle and/or its affiliates. All rights reserved. | |||
| 3 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |||
| 4 | * | |||
| 5 | * This code is free software; you can redistribute it and/or modify it | |||
| 6 | * under the terms of the GNU General Public License version 2 only, as | |||
| 7 | * published by the Free Software Foundation. | |||
| 8 | * | |||
| 9 | * This code is distributed in the hope that it will be useful, but WITHOUT | |||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |||
| 12 | * version 2 for more details (a copy is included in the LICENSE file that | |||
| 13 | * accompanied this code). | |||
| 14 | * | |||
| 15 | * You should have received a copy of the GNU General Public License version | |||
| 16 | * 2 along with this work; if not, write to the Free Software Foundation, | |||
| 17 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |||
| 18 | * | |||
| 19 | * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA | |||
| 20 | * or visit www.oracle.com if you need additional information or have any | |||
| 21 | * questions. | |||
| 22 | * | |||
| 23 | */ | |||
| 24 | ||||
| 25 | #include "precompiled.hpp" | |||
| 26 | #include "asm/assembler.hpp" | |||
| 27 | #include "asm/assembler.inline.hpp" | |||
| 28 | #include "gc/shared/cardTableBarrierSet.hpp" | |||
| 29 | #include "gc/shared/collectedHeap.inline.hpp" | |||
| 30 | #include "interpreter/interpreter.hpp" | |||
| 31 | #include "memory/resourceArea.hpp" | |||
| 32 | #include "prims/methodHandles.hpp" | |||
| 33 | #include "runtime/objectMonitor.hpp" | |||
| 34 | #include "runtime/os.hpp" | |||
| 35 | #include "runtime/sharedRuntime.hpp" | |||
| 36 | #include "runtime/stubRoutines.hpp" | |||
| 37 | #include "runtime/vm_version.hpp" | |||
| 38 | #include "utilities/macros.hpp" | |||
| 39 | ||||
| 40 | #ifdef PRODUCT | |||
| 41 | #define BLOCK_COMMENT(str)block_comment(str) /* nothing */ | |||
| 42 | #define STOP(error)block_comment(error); stop(error) stop(error) | |||
| 43 | #else | |||
| 44 | #define BLOCK_COMMENT(str)block_comment(str) block_comment(str) | |||
| 45 | #define STOP(error)block_comment(error); stop(error) block_comment(error); stop(error) | |||
| 46 | #endif | |||
| 47 | ||||
| 48 | #define BIND(label)bind(label); block_comment("label" ":") bind(label); BLOCK_COMMENT(#label ":")block_comment(#label ":") | |||
| 49 | // Implementation of AddressLiteral | |||
| 50 | ||||
| 51 | // A 2-D table for managing compressed displacement(disp8) on EVEX enabled platforms. | |||
| 52 | unsigned char tuple_table[Assembler::EVEX_ETUP + 1][Assembler::AVX_512bit + 1] = { | |||
| 53 | // -----------------Table 4.5 -------------------- // | |||
| 54 | 16, 32, 64, // EVEX_FV(0) | |||
| 55 | 4, 4, 4, // EVEX_FV(1) - with Evex.b | |||
| 56 | 16, 32, 64, // EVEX_FV(2) - with Evex.w | |||
| 57 | 8, 8, 8, // EVEX_FV(3) - with Evex.w and Evex.b | |||
| 58 | 8, 16, 32, // EVEX_HV(0) | |||
| 59 | 4, 4, 4, // EVEX_HV(1) - with Evex.b | |||
| 60 | // -----------------Table 4.6 -------------------- // | |||
| 61 | 16, 32, 64, // EVEX_FVM(0) | |||
| 62 | 1, 1, 1, // EVEX_T1S(0) | |||
| 63 | 2, 2, 2, // EVEX_T1S(1) | |||
| 64 | 4, 4, 4, // EVEX_T1S(2) | |||
| 65 | 8, 8, 8, // EVEX_T1S(3) | |||
| 66 | 4, 4, 4, // EVEX_T1F(0) | |||
| 67 | 8, 8, 8, // EVEX_T1F(1) | |||
| 68 | 8, 8, 8, // EVEX_T2(0) | |||
| 69 | 0, 16, 16, // EVEX_T2(1) | |||
| 70 | 0, 16, 16, // EVEX_T4(0) | |||
| 71 | 0, 0, 32, // EVEX_T4(1) | |||
| 72 | 0, 0, 32, // EVEX_T8(0) | |||
| 73 | 8, 16, 32, // EVEX_HVM(0) | |||
| 74 | 4, 8, 16, // EVEX_QVM(0) | |||
| 75 | 2, 4, 8, // EVEX_OVM(0) | |||
| 76 | 16, 16, 16, // EVEX_M128(0) | |||
| 77 | 8, 32, 64, // EVEX_DUP(0) | |||
| 78 | 0, 0, 0 // EVEX_NTUP | |||
| 79 | }; | |||
| 80 | ||||
| 81 | AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) { | |||
| 82 | _is_lval = false; | |||
| 83 | _target = target; | |||
| 84 | switch (rtype) { | |||
| 85 | case relocInfo::oop_type: | |||
| 86 | case relocInfo::metadata_type: | |||
| 87 | // Oops are a special case. Normally they would be their own section | |||
| 88 | // but in cases like icBuffer they are literals in the code stream that | |||
| 89 | // we don't have a section for. We use none so that we get a literal address | |||
| 90 | // which is always patchable. | |||
| 91 | break; | |||
| 92 | case relocInfo::external_word_type: | |||
| 93 | _rspec = external_word_Relocation::spec(target); | |||
| 94 | break; | |||
| 95 | case relocInfo::internal_word_type: | |||
| 96 | _rspec = internal_word_Relocation::spec(target); | |||
| 97 | break; | |||
| 98 | case relocInfo::opt_virtual_call_type: | |||
| 99 | _rspec = opt_virtual_call_Relocation::spec(); | |||
| 100 | break; | |||
| 101 | case relocInfo::static_call_type: | |||
| 102 | _rspec = static_call_Relocation::spec(); | |||
| 103 | break; | |||
| 104 | case relocInfo::runtime_call_type: | |||
| 105 | _rspec = runtime_call_Relocation::spec(); | |||
| 106 | break; | |||
| 107 | case relocInfo::poll_type: | |||
| 108 | case relocInfo::poll_return_type: | |||
| 109 | _rspec = Relocation::spec_simple(rtype); | |||
| 110 | break; | |||
| 111 | case relocInfo::none: | |||
| 112 | break; | |||
| 113 | default: | |||
| 114 | ShouldNotReachHere()do { (*g_assert_poison) = 'X';; report_should_not_reach_here( "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 114); ::breakpoint(); } while (0); | |||
| 115 | break; | |||
| 116 | } | |||
| 117 | } | |||
| 118 | ||||
| 119 | // Implementation of Address | |||
| 120 | ||||
| 121 | #ifdef _LP641 | |||
| 122 | ||||
| 123 | Address Address::make_array(ArrayAddress adr) { | |||
| 124 | // Not implementable on 64bit machines | |||
| 125 | // Should have been handled higher up the call chain. | |||
| 126 | ShouldNotReachHere()do { (*g_assert_poison) = 'X';; report_should_not_reach_here( "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 126); ::breakpoint(); } while (0); | |||
| 127 | return Address(); | |||
| 128 | } | |||
| 129 | ||||
| 130 | // exceedingly dangerous constructor | |||
| 131 | Address::Address(int disp, address loc, relocInfo::relocType rtype) { | |||
| 132 | _base = noreg; | |||
| 133 | _index = noreg; | |||
| 134 | _scale = no_scale; | |||
| 135 | _disp = disp; | |||
| 136 | _xmmindex = xnoreg; | |||
| 137 | _isxmmindex = false; | |||
| 138 | switch (rtype) { | |||
| 139 | case relocInfo::external_word_type: | |||
| 140 | _rspec = external_word_Relocation::spec(loc); | |||
| 141 | break; | |||
| 142 | case relocInfo::internal_word_type: | |||
| 143 | _rspec = internal_word_Relocation::spec(loc); | |||
| 144 | break; | |||
| 145 | case relocInfo::runtime_call_type: | |||
| 146 | // HMM | |||
| 147 | _rspec = runtime_call_Relocation::spec(); | |||
| 148 | break; | |||
| 149 | case relocInfo::poll_type: | |||
| 150 | case relocInfo::poll_return_type: | |||
| 151 | _rspec = Relocation::spec_simple(rtype); | |||
| 152 | break; | |||
| 153 | case relocInfo::none: | |||
| 154 | break; | |||
| 155 | default: | |||
| 156 | ShouldNotReachHere()do { (*g_assert_poison) = 'X';; report_should_not_reach_here( "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 156); ::breakpoint(); } while (0); | |||
| 157 | } | |||
| 158 | } | |||
| 159 | #else // LP64 | |||
| 160 | ||||
| 161 | Address Address::make_array(ArrayAddress adr) { | |||
| 162 | AddressLiteral base = adr.base(); | |||
| 163 | Address index = adr.index(); | |||
| 164 | assert(index._disp == 0, "must not have disp")do { if (!(index._disp == 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 164, "assert(" "index._disp == 0" ") failed", "must not have disp" ); ::breakpoint(); } } while (0); // maybe it can? | |||
| 165 | Address array(index._base, index._index, index._scale, (intptr_t) base.target()); | |||
| 166 | array._rspec = base._rspec; | |||
| 167 | return array; | |||
| 168 | } | |||
| 169 | ||||
| 170 | // exceedingly dangerous constructor | |||
| 171 | Address::Address(address loc, RelocationHolder spec) { | |||
| 172 | _base = noreg; | |||
| 173 | _index = noreg; | |||
| 174 | _scale = no_scale; | |||
| 175 | _disp = (intptr_t) loc; | |||
| 176 | _rspec = spec; | |||
| 177 | _xmmindex = xnoreg; | |||
| 178 | _isxmmindex = false; | |||
| 179 | } | |||
| 180 | ||||
| 181 | #endif // _LP64 | |||
| 182 | ||||
| 183 | ||||
| 184 | ||||
| 185 | // Convert the raw encoding form into the form expected by the constructor for | |||
| 186 | // Address. An index of 4 (rsp) corresponds to having no index, so convert | |||
| 187 | // that to noreg for the Address constructor. | |||
| 188 | Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) { | |||
| 189 | RelocationHolder rspec = RelocationHolder::none; | |||
| 190 | if (disp_reloc != relocInfo::none) { | |||
| 191 | rspec = Relocation::spec_simple(disp_reloc); | |||
| 192 | } | |||
| 193 | bool valid_index = index != rsp->encoding(); | |||
| 194 | if (valid_index) { | |||
| 195 | Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp)); | |||
| 196 | madr._rspec = rspec; | |||
| 197 | return madr; | |||
| 198 | } else { | |||
| 199 | Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp)); | |||
| 200 | madr._rspec = rspec; | |||
| 201 | return madr; | |||
| 202 | } | |||
| 203 | } | |||
| 204 | ||||
| 205 | // Implementation of Assembler | |||
| 206 | ||||
| 207 | int AbstractAssembler::code_fill_byte() { | |||
| 208 | return (u_char)'\xF4'; // hlt | |||
| 209 | } | |||
| 210 | ||||
| 211 | void Assembler::init_attributes(void) { | |||
| 212 | _legacy_mode_bw = (VM_Version::supports_avx512bw() == false); | |||
| 213 | _legacy_mode_dq = (VM_Version::supports_avx512dq() == false); | |||
| 214 | _legacy_mode_vl = (VM_Version::supports_avx512vl() == false); | |||
| 215 | _legacy_mode_vlbw = (VM_Version::supports_avx512vlbw() == false); | |||
| 216 | NOT_LP64(_is_managed = false;) | |||
| 217 | _attributes = NULL__null; | |||
| 218 | } | |||
| 219 | ||||
| 220 | ||||
| 221 | void Assembler::membar(Membar_mask_bits order_constraint) { | |||
| 222 | // We only have to handle StoreLoad | |||
| 223 | if (order_constraint & StoreLoad) { | |||
| 224 | // All usable chips support "locked" instructions which suffice | |||
| 225 | // as barriers, and are much faster than the alternative of | |||
| 226 | // using cpuid instruction. We use here a locked add [esp-C],0. | |||
| 227 | // This is conveniently otherwise a no-op except for blowing | |||
| 228 | // flags, and introducing a false dependency on target memory | |||
| 229 | // location. We can't do anything with flags, but we can avoid | |||
| 230 | // memory dependencies in the current method by locked-adding | |||
| 231 | // somewhere else on the stack. Doing [esp+C] will collide with | |||
| 232 | // something on stack in current method, hence we go for [esp-C]. | |||
| 233 | // It is convenient since it is almost always in data cache, for | |||
| 234 | // any small C. We need to step back from SP to avoid data | |||
| 235 | // dependencies with other things on below SP (callee-saves, for | |||
| 236 | // example). Without a clear way to figure out the minimal safe | |||
| 237 | // distance from SP, it makes sense to step back the complete | |||
| 238 | // cache line, as this will also avoid possible second-order effects | |||
| 239 | // with locked ops against the cache line. Our choice of offset | |||
| 240 | // is bounded by x86 operand encoding, which should stay within | |||
| 241 | // [-128; +127] to have the 8-byte displacement encoding. | |||
| 242 | // | |||
| 243 | // Any change to this code may need to revisit other places in | |||
| 244 | // the code where this idiom is used, in particular the | |||
| 245 | // orderAccess code. | |||
| 246 | ||||
| 247 | int offset = -VM_Version::L1_line_size(); | |||
| 248 | if (offset < -128) { | |||
| 249 | offset = -128; | |||
| 250 | } | |||
| 251 | ||||
| 252 | lock(); | |||
| 253 | addl(Address(rsp, offset), 0);// Assert the lock# signal here | |||
| 254 | } | |||
| 255 | } | |||
| 256 | ||||
| 257 | // make this go away someday | |||
| 258 | void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) { | |||
| 259 | if (rtype == relocInfo::none) | |||
| 260 | emit_int32(data); | |||
| 261 | else | |||
| 262 | emit_data(data, Relocation::spec_simple(rtype), format); | |||
| 263 | } | |||
| 264 | ||||
| 265 | void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) { | |||
| 266 | assert(imm_operand == 0, "default format must be immediate in this file")do { if (!(imm_operand == 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 266, "assert(" "imm_operand == 0" ") failed", "default format must be immediate in this file" ); ::breakpoint(); } } while (0); | |||
| 267 | assert(inst_mark() != NULL, "must be inside InstructionMark")do { if (!(inst_mark() != __null)) { (*g_assert_poison) = 'X' ;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 267, "assert(" "inst_mark() != __null" ") failed", "must be inside InstructionMark" ); ::breakpoint(); } } while (0); | |||
| 268 | if (rspec.type() != relocInfo::none) { | |||
| 269 | #ifdef ASSERT1 | |||
| 270 | check_relocation(rspec, format); | |||
| 271 | #endif | |||
| 272 | // Do not use AbstractAssembler::relocate, which is not intended for | |||
| 273 | // embedded words. Instead, relocate to the enclosing instruction. | |||
| 274 | ||||
| 275 | // hack. call32 is too wide for mask so use disp32 | |||
| 276 | if (format == call32_operand) | |||
| 277 | code_section()->relocate(inst_mark(), rspec, disp32_operand); | |||
| 278 | else | |||
| 279 | code_section()->relocate(inst_mark(), rspec, format); | |||
| 280 | } | |||
| 281 | emit_int32(data); | |||
| 282 | } | |||
| 283 | ||||
| 284 | static int encode(Register r) { | |||
| 285 | int enc = r->encoding(); | |||
| 286 | if (enc >= 8) { | |||
| 287 | enc -= 8; | |||
| 288 | } | |||
| 289 | return enc; | |||
| 290 | } | |||
| 291 | ||||
| 292 | void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) { | |||
| 293 | assert(dst->has_byte_register(), "must have byte register")do { if (!(dst->has_byte_register())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 293, "assert(" "dst->has_byte_register()" ") failed", "must have byte register" ); ::breakpoint(); } } while (0); | |||
| 294 | assert(isByte(op1) && isByte(op2), "wrong opcode")do { if (!(isByte(op1) && isByte(op2))) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 294, "assert(" "isByte(op1) && isByte(op2)" ") failed" , "wrong opcode"); ::breakpoint(); } } while (0); | |||
| 295 | assert(isByte(imm8), "not a byte")do { if (!(isByte(imm8))) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 295, "assert(" "isByte(imm8)" ") failed", "not a byte"); :: breakpoint(); } } while (0); | |||
| 296 | assert((op1 & 0x01) == 0, "should be 8bit operation")do { if (!((op1 & 0x01) == 0)) { (*g_assert_poison) = 'X' ;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 296, "assert(" "(op1 & 0x01) == 0" ") failed", "should be 8bit operation" ); ::breakpoint(); } } while (0); | |||
| 297 | emit_int24(op1, (op2 | encode(dst)), imm8); | |||
| 298 | } | |||
| 299 | ||||
| 300 | ||||
| 301 | void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) { | |||
| 302 | assert(isByte(op1) && isByte(op2), "wrong opcode")do { if (!(isByte(op1) && isByte(op2))) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 302, "assert(" "isByte(op1) && isByte(op2)" ") failed" , "wrong opcode"); ::breakpoint(); } } while (0); | |||
| 303 | assert((op1 & 0x01) == 1, "should be 32bit operation")do { if (!((op1 & 0x01) == 1)) { (*g_assert_poison) = 'X' ;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 303, "assert(" "(op1 & 0x01) == 1" ") failed", "should be 32bit operation" ); ::breakpoint(); } } while (0); | |||
| 304 | assert((op1 & 0x02) == 0, "sign-extension bit should not be set")do { if (!((op1 & 0x02) == 0)) { (*g_assert_poison) = 'X' ;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 304, "assert(" "(op1 & 0x02) == 0" ") failed", "sign-extension bit should not be set" ); ::breakpoint(); } } while (0); | |||
| 305 | if (is8bit(imm32)) { | |||
| 306 | emit_int24(op1 | 0x02, // set sign bit | |||
| 307 | op2 | encode(dst), | |||
| 308 | imm32 & 0xFF); | |||
| 309 | } else { | |||
| 310 | emit_int16(op1, (op2 | encode(dst))); | |||
| 311 | emit_int32(imm32); | |||
| 312 | } | |||
| 313 | } | |||
| 314 | ||||
| 315 | // Force generation of a 4 byte immediate value even if it fits into 8bit | |||
| 316 | void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) { | |||
| 317 | assert(isByte(op1) && isByte(op2), "wrong opcode")do { if (!(isByte(op1) && isByte(op2))) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 317, "assert(" "isByte(op1) && isByte(op2)" ") failed" , "wrong opcode"); ::breakpoint(); } } while (0); | |||
| 318 | assert((op1 & 0x01) == 1, "should be 32bit operation")do { if (!((op1 & 0x01) == 1)) { (*g_assert_poison) = 'X' ;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 318, "assert(" "(op1 & 0x01) == 1" ") failed", "should be 32bit operation" ); ::breakpoint(); } } while (0); | |||
| 319 | assert((op1 & 0x02) == 0, "sign-extension bit should not be set")do { if (!((op1 & 0x02) == 0)) { (*g_assert_poison) = 'X' ;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 319, "assert(" "(op1 & 0x02) == 0" ") failed", "sign-extension bit should not be set" ); ::breakpoint(); } } while (0); | |||
| 320 | emit_int16(op1, (op2 | encode(dst))); | |||
| 321 | emit_int32(imm32); | |||
| 322 | } | |||
| 323 | ||||
| 324 | // immediate-to-memory forms | |||
| 325 | void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) { | |||
| 326 | assert((op1 & 0x01) == 1, "should be 32bit operation")do { if (!((op1 & 0x01) == 1)) { (*g_assert_poison) = 'X' ;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 326, "assert(" "(op1 & 0x01) == 1" ") failed", "should be 32bit operation" ); ::breakpoint(); } } while (0); | |||
| 327 | assert((op1 & 0x02) == 0, "sign-extension bit should not be set")do { if (!((op1 & 0x02) == 0)) { (*g_assert_poison) = 'X' ;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 327, "assert(" "(op1 & 0x02) == 0" ") failed", "sign-extension bit should not be set" ); ::breakpoint(); } } while (0); | |||
| 328 | if (is8bit(imm32)) { | |||
| 329 | emit_int8(op1 | 0x02); // set sign bit | |||
| 330 | emit_operand(rm, adr, 1); | |||
| 331 | emit_int8(imm32 & 0xFF); | |||
| 332 | } else { | |||
| 333 | emit_int8(op1); | |||
| 334 | emit_operand(rm, adr, 4); | |||
| 335 | emit_int32(imm32); | |||
| 336 | } | |||
| 337 | } | |||
| 338 | ||||
| 339 | ||||
| 340 | void Assembler::emit_arith(int op1, int op2, Register dst, Register src) { | |||
| 341 | assert(isByte(op1) && isByte(op2), "wrong opcode")do { if (!(isByte(op1) && isByte(op2))) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 341, "assert(" "isByte(op1) && isByte(op2)" ") failed" , "wrong opcode"); ::breakpoint(); } } while (0); | |||
| 342 | emit_int16(op1, (op2 | encode(dst) << 3 | encode(src))); | |||
| 343 | } | |||
| 344 | ||||
| 345 | ||||
| 346 | bool Assembler::query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len, | |||
| 347 | int cur_tuple_type, int in_size_in_bits, int cur_encoding) { | |||
| 348 | int mod_idx = 0; | |||
| 349 | // We will test if the displacement fits the compressed format and if so | |||
| 350 | // apply the compression to the displacment iff the result is8bit. | |||
| 351 | if (VM_Version::supports_evex() && is_evex_inst) { | |||
| 352 | switch (cur_tuple_type) { | |||
| 353 | case EVEX_FV: | |||
| 354 | if ((cur_encoding & VEX_W) == VEX_W) { | |||
| 355 | mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2; | |||
| 356 | } else { | |||
| 357 | mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0; | |||
| 358 | } | |||
| 359 | break; | |||
| 360 | ||||
| 361 | case EVEX_HV: | |||
| 362 | mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0; | |||
| 363 | break; | |||
| 364 | ||||
| 365 | case EVEX_FVM: | |||
| 366 | break; | |||
| 367 | ||||
| 368 | case EVEX_T1S: | |||
| 369 | switch (in_size_in_bits) { | |||
| 370 | case EVEX_8bit: | |||
| 371 | break; | |||
| 372 | ||||
| 373 | case EVEX_16bit: | |||
| 374 | mod_idx = 1; | |||
| 375 | break; | |||
| 376 | ||||
| 377 | case EVEX_32bit: | |||
| 378 | mod_idx = 2; | |||
| 379 | break; | |||
| 380 | ||||
| 381 | case EVEX_64bit: | |||
| 382 | mod_idx = 3; | |||
| 383 | break; | |||
| 384 | } | |||
| 385 | break; | |||
| 386 | ||||
| 387 | case EVEX_T1F: | |||
| 388 | case EVEX_T2: | |||
| 389 | case EVEX_T4: | |||
| 390 | mod_idx = (in_size_in_bits == EVEX_64bit) ? 1 : 0; | |||
| 391 | break; | |||
| 392 | ||||
| 393 | case EVEX_T8: | |||
| 394 | break; | |||
| 395 | ||||
| 396 | case EVEX_HVM: | |||
| 397 | break; | |||
| 398 | ||||
| 399 | case EVEX_QVM: | |||
| 400 | break; | |||
| 401 | ||||
| 402 | case EVEX_OVM: | |||
| 403 | break; | |||
| 404 | ||||
| 405 | case EVEX_M128: | |||
| 406 | break; | |||
| 407 | ||||
| 408 | case EVEX_DUP: | |||
| 409 | break; | |||
| 410 | ||||
| 411 | default: | |||
| 412 | assert(0, "no valid evex tuple_table entry")do { if (!(0)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 412, "assert(" "0" ") failed", "no valid evex tuple_table entry" ); ::breakpoint(); } } while (0); | |||
| 413 | break; | |||
| 414 | } | |||
| 415 | ||||
| 416 | if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) { | |||
| 417 | int disp_factor = tuple_table[cur_tuple_type + mod_idx][vector_len]; | |||
| 418 | if ((disp % disp_factor) == 0) { | |||
| 419 | int new_disp = disp / disp_factor; | |||
| 420 | if ((-0x80 <= new_disp && new_disp < 0x80)) { | |||
| 421 | disp = new_disp; | |||
| 422 | } | |||
| 423 | } else { | |||
| 424 | return false; | |||
| 425 | } | |||
| 426 | } | |||
| 427 | } | |||
| 428 | return (-0x80 <= disp && disp < 0x80); | |||
| 429 | } | |||
| 430 | ||||
| 431 | ||||
| 432 | bool Assembler::emit_compressed_disp_byte(int &disp) { | |||
| 433 | int mod_idx = 0; | |||
| 434 | // We will test if the displacement fits the compressed format and if so | |||
| 435 | // apply the compression to the displacment iff the result is8bit. | |||
| 436 | if (VM_Version::supports_evex() && _attributes && _attributes->is_evex_instruction()) { | |||
| 437 | int evex_encoding = _attributes->get_evex_encoding(); | |||
| 438 | int tuple_type = _attributes->get_tuple_type(); | |||
| 439 | switch (tuple_type) { | |||
| 440 | case EVEX_FV: | |||
| 441 | if ((evex_encoding & VEX_W) == VEX_W) { | |||
| 442 | mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2; | |||
| 443 | } else { | |||
| 444 | mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0; | |||
| 445 | } | |||
| 446 | break; | |||
| 447 | ||||
| 448 | case EVEX_HV: | |||
| 449 | mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0; | |||
| 450 | break; | |||
| 451 | ||||
| 452 | case EVEX_FVM: | |||
| 453 | break; | |||
| 454 | ||||
| 455 | case EVEX_T1S: | |||
| 456 | switch (_attributes->get_input_size()) { | |||
| 457 | case EVEX_8bit: | |||
| 458 | break; | |||
| 459 | ||||
| 460 | case EVEX_16bit: | |||
| 461 | mod_idx = 1; | |||
| 462 | break; | |||
| 463 | ||||
| 464 | case EVEX_32bit: | |||
| 465 | mod_idx = 2; | |||
| 466 | break; | |||
| 467 | ||||
| 468 | case EVEX_64bit: | |||
| 469 | mod_idx = 3; | |||
| 470 | break; | |||
| 471 | } | |||
| 472 | break; | |||
| 473 | ||||
| 474 | case EVEX_T1F: | |||
| 475 | case EVEX_T2: | |||
| 476 | case EVEX_T4: | |||
| 477 | mod_idx = (_attributes->get_input_size() == EVEX_64bit) ? 1 : 0; | |||
| 478 | break; | |||
| 479 | ||||
| 480 | case EVEX_T8: | |||
| 481 | break; | |||
| 482 | ||||
| 483 | case EVEX_HVM: | |||
| 484 | break; | |||
| 485 | ||||
| 486 | case EVEX_QVM: | |||
| 487 | break; | |||
| 488 | ||||
| 489 | case EVEX_OVM: | |||
| 490 | break; | |||
| 491 | ||||
| 492 | case EVEX_M128: | |||
| 493 | break; | |||
| 494 | ||||
| 495 | case EVEX_DUP: | |||
| 496 | break; | |||
| 497 | ||||
| 498 | default: | |||
| 499 | assert(0, "no valid evex tuple_table entry")do { if (!(0)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 499, "assert(" "0" ") failed", "no valid evex tuple_table entry" ); ::breakpoint(); } } while (0); | |||
| 500 | break; | |||
| 501 | } | |||
| 502 | ||||
| 503 | int vector_len = _attributes->get_vector_len(); | |||
| 504 | if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) { | |||
| 505 | int disp_factor = tuple_table[tuple_type + mod_idx][vector_len]; | |||
| 506 | if ((disp % disp_factor) == 0) { | |||
| 507 | int new_disp = disp / disp_factor; | |||
| 508 | if (is8bit(new_disp)) { | |||
| 509 | disp = new_disp; | |||
| 510 | } | |||
| 511 | } else { | |||
| 512 | return false; | |||
| 513 | } | |||
| 514 | } | |||
| 515 | } | |||
| 516 | return is8bit(disp); | |||
| 517 | } | |||
| 518 | ||||
| 519 | static bool is_valid_encoding(int reg_enc) { | |||
| 520 | return reg_enc >= 0; | |||
| 521 | } | |||
| 522 | ||||
| 523 | static int raw_encode(Register reg) { | |||
| 524 | assert(reg == noreg || reg->is_valid(), "sanity")do { if (!(reg == noreg || reg->is_valid())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 524, "assert(" "reg == noreg || reg->is_valid()" ") failed" , "sanity"); ::breakpoint(); } } while (0); | |||
| 525 | int reg_enc = (intptr_t)reg; | |||
| 526 | assert(reg_enc == -1 || is_valid_encoding(reg_enc), "sanity")do { if (!(reg_enc == -1 || is_valid_encoding(reg_enc))) { (* g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 526, "assert(" "reg_enc == -1 || is_valid_encoding(reg_enc)" ") failed", "sanity"); ::breakpoint(); } } while (0); | |||
| 527 | return reg_enc; | |||
| 528 | } | |||
| 529 | ||||
| 530 | static int raw_encode(XMMRegister xmmreg) { | |||
| 531 | assert(xmmreg == xnoreg || xmmreg->is_valid(), "sanity")do { if (!(xmmreg == xnoreg || xmmreg->is_valid())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 531, "assert(" "xmmreg == xnoreg || xmmreg->is_valid()" ") failed" , "sanity"); ::breakpoint(); } } while (0); | |||
| 532 | int xmmreg_enc = (intptr_t)xmmreg; | |||
| 533 | assert(xmmreg_enc == -1 || is_valid_encoding(xmmreg_enc), "sanity")do { if (!(xmmreg_enc == -1 || is_valid_encoding(xmmreg_enc)) ) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 533, "assert(" "xmmreg_enc == -1 || is_valid_encoding(xmmreg_enc)" ") failed", "sanity"); ::breakpoint(); } } while (0); | |||
| 534 | return xmmreg_enc; | |||
| 535 | } | |||
| 536 | ||||
| 537 | static int modrm_encoding(int mod, int dst_enc, int src_enc) { | |||
| 538 | return (mod & 3) << 6 | (dst_enc & 7) << 3 | (src_enc & 7); | |||
| 539 | } | |||
| 540 | ||||
| 541 | static int sib_encoding(Address::ScaleFactor scale, int index_enc, int base_enc) { | |||
| 542 | return (scale & 3) << 6 | (index_enc & 7) << 3 | (base_enc & 7); | |||
| 543 | } | |||
| 544 | ||||
| 545 | inline void Assembler::emit_modrm(int mod, int dst_enc, int src_enc) { | |||
| 546 | assert((mod & 3) != 0b11, "forbidden")do { if (!((mod & 3) != 0b11)) { (*g_assert_poison) = 'X' ;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 546, "assert(" "(mod & 3) != 0b11" ") failed", "forbidden" ); ::breakpoint(); } } while (0); | |||
| 547 | int modrm = modrm_encoding(mod, dst_enc, src_enc); | |||
| 548 | emit_int8(modrm); | |||
| 549 | } | |||
| 550 | ||||
| 551 | inline void Assembler::emit_modrm_disp8(int mod, int dst_enc, int src_enc, | |||
| 552 | int disp) { | |||
| 553 | int modrm = modrm_encoding(mod, dst_enc, src_enc); | |||
| 554 | emit_int16(modrm, disp & 0xFF); | |||
| 555 | } | |||
| 556 | ||||
| 557 | inline void Assembler::emit_modrm_sib(int mod, int dst_enc, int src_enc, | |||
| 558 | Address::ScaleFactor scale, int index_enc, int base_enc) { | |||
| 559 | int modrm = modrm_encoding(mod, dst_enc, src_enc); | |||
| 560 | int sib = sib_encoding(scale, index_enc, base_enc); | |||
| 561 | emit_int16(modrm, sib); | |||
| 562 | } | |||
| 563 | ||||
| 564 | inline void Assembler::emit_modrm_sib_disp8(int mod, int dst_enc, int src_enc, | |||
| 565 | Address::ScaleFactor scale, int index_enc, int base_enc, | |||
| 566 | int disp) { | |||
| 567 | int modrm = modrm_encoding(mod, dst_enc, src_enc); | |||
| 568 | int sib = sib_encoding(scale, index_enc, base_enc); | |||
| 569 | emit_int24(modrm, sib, disp & 0xFF); | |||
| 570 | } | |||
| 571 | ||||
| 572 | void Assembler::emit_operand_helper(int reg_enc, int base_enc, int index_enc, | |||
| 573 | Address::ScaleFactor scale, int disp, | |||
| 574 | RelocationHolder const& rspec, | |||
| 575 | int rip_relative_correction) { | |||
| 576 | bool no_relocation = (rspec.type() == relocInfo::none); | |||
| 577 | ||||
| 578 | if (is_valid_encoding(base_enc)) { | |||
| 579 | if (is_valid_encoding(index_enc)) { | |||
| 580 | assert(scale != Address::no_scale, "inconsistent address")do { if (!(scale != Address::no_scale)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 580, "assert(" "scale != Address::no_scale" ") failed", "inconsistent address" ); ::breakpoint(); } } while (0); | |||
| 581 | // [base + index*scale + disp] | |||
| 582 | if (disp == 0 && no_relocation && | |||
| 583 | base_enc != rbp->encoding() LP64_ONLY(&& base_enc != r13->encoding())&& base_enc != r13->encoding()) { | |||
| 584 | // [base + index*scale] | |||
| 585 | // [00 reg 100][ss index base] | |||
| 586 | emit_modrm_sib(0b00, reg_enc, 0b100, | |||
| 587 | scale, index_enc, base_enc); | |||
| 588 | } else if (emit_compressed_disp_byte(disp) && no_relocation) { | |||
| 589 | // [base + index*scale + imm8] | |||
| 590 | // [01 reg 100][ss index base] imm8 | |||
| 591 | emit_modrm_sib_disp8(0b01, reg_enc, 0b100, | |||
| 592 | scale, index_enc, base_enc, | |||
| 593 | disp); | |||
| 594 | } else { | |||
| 595 | // [base + index*scale + disp32] | |||
| 596 | // [10 reg 100][ss index base] disp32 | |||
| 597 | emit_modrm_sib(0b10, reg_enc, 0b100, | |||
| 598 | scale, index_enc, base_enc); | |||
| 599 | emit_data(disp, rspec, disp32_operand); | |||
| 600 | } | |||
| 601 | } else if (base_enc == rsp->encoding() LP64_ONLY(|| base_enc == r12->encoding())|| base_enc == r12->encoding()) { | |||
| 602 | // [rsp + disp] | |||
| 603 | if (disp == 0 && no_relocation) { | |||
| 604 | // [rsp] | |||
| 605 | // [00 reg 100][00 100 100] | |||
| 606 | emit_modrm_sib(0b00, reg_enc, 0b100, | |||
| 607 | Address::times_1, 0b100, 0b100); | |||
| 608 | } else if (emit_compressed_disp_byte(disp) && no_relocation) { | |||
| 609 | // [rsp + imm8] | |||
| 610 | // [01 reg 100][00 100 100] disp8 | |||
| 611 | emit_modrm_sib_disp8(0b01, reg_enc, 0b100, | |||
| 612 | Address::times_1, 0b100, 0b100, | |||
| 613 | disp); | |||
| 614 | } else { | |||
| 615 | // [rsp + imm32] | |||
| 616 | // [10 reg 100][00 100 100] disp32 | |||
| 617 | emit_modrm_sib(0b10, reg_enc, 0b100, | |||
| 618 | Address::times_1, 0b100, 0b100); | |||
| 619 | emit_data(disp, rspec, disp32_operand); | |||
| 620 | } | |||
| 621 | } else { | |||
| 622 | // [base + disp] | |||
| 623 | assert(base_enc != rsp->encoding() LP64_ONLY(&& base_enc != r12->encoding()), "illegal addressing mode")do { if (!(base_enc != rsp->encoding() && base_enc != r12->encoding())) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 623, "assert(" "base_enc != rsp->encoding() && base_enc != r12->encoding()" ") failed", "illegal addressing mode"); ::breakpoint(); } } while (0); | |||
| 624 | if (disp == 0 && no_relocation && | |||
| 625 | base_enc != rbp->encoding() LP64_ONLY(&& base_enc != r13->encoding())&& base_enc != r13->encoding()) { | |||
| 626 | // [base] | |||
| 627 | // [00 reg base] | |||
| 628 | emit_modrm(0, reg_enc, base_enc); | |||
| 629 | } else if (emit_compressed_disp_byte(disp) && no_relocation) { | |||
| 630 | // [base + disp8] | |||
| 631 | // [01 reg base] disp8 | |||
| 632 | emit_modrm_disp8(0b01, reg_enc, base_enc, | |||
| 633 | disp); | |||
| 634 | } else { | |||
| 635 | // [base + disp32] | |||
| 636 | // [10 reg base] disp32 | |||
| 637 | emit_modrm(0b10, reg_enc, base_enc); | |||
| 638 | emit_data(disp, rspec, disp32_operand); | |||
| 639 | } | |||
| 640 | } | |||
| 641 | } else { | |||
| 642 | if (is_valid_encoding(index_enc)) { | |||
| 643 | assert(scale != Address::no_scale, "inconsistent address")do { if (!(scale != Address::no_scale)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 643, "assert(" "scale != Address::no_scale" ") failed", "inconsistent address" ); ::breakpoint(); } } while (0); | |||
| 644 | // base == noreg | |||
| 645 | // [index*scale + disp] | |||
| 646 | // [00 reg 100][ss index 101] disp32 | |||
| 647 | emit_modrm_sib(0b00, reg_enc, 0b100, | |||
| 648 | scale, index_enc, 0b101 /* no base */); | |||
| 649 | emit_data(disp, rspec, disp32_operand); | |||
| 650 | } else if (!no_relocation) { | |||
| 651 | // base == noreg, index == noreg | |||
| 652 | // [disp] (64bit) RIP-RELATIVE (32bit) abs | |||
| 653 | // [00 reg 101] disp32 | |||
| 654 | ||||
| 655 | emit_modrm(0b00, reg_enc, 0b101 /* no base */); | |||
| 656 | // Note that the RIP-rel. correction applies to the generated | |||
| 657 | // disp field, but _not_ to the target address in the rspec. | |||
| 658 | ||||
| 659 | // disp was created by converting the target address minus the pc | |||
| 660 | // at the start of the instruction. That needs more correction here. | |||
| 661 | // intptr_t disp = target - next_ip; | |||
| 662 | assert(inst_mark() != NULL, "must be inside InstructionMark")do { if (!(inst_mark() != __null)) { (*g_assert_poison) = 'X' ;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 662, "assert(" "inst_mark() != __null" ") failed", "must be inside InstructionMark" ); ::breakpoint(); } } while (0); | |||
| 663 | address next_ip = pc() + sizeof(int32_t) + rip_relative_correction; | |||
| 664 | int64_t adjusted = disp; | |||
| 665 | // Do rip-rel adjustment for 64bit | |||
| 666 | LP64_ONLY(adjusted -= (next_ip - inst_mark()))adjusted -= (next_ip - inst_mark()); | |||
| 667 | assert(is_simm32(adjusted),do { if (!(is_simm32(adjusted))) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 668, "assert(" "is_simm32(adjusted)" ") failed", "must be 32bit offset (RIP relative address)" ); ::breakpoint(); } } while (0) | |||
| 668 | "must be 32bit offset (RIP relative address)")do { if (!(is_simm32(adjusted))) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 668, "assert(" "is_simm32(adjusted)" ") failed", "must be 32bit offset (RIP relative address)" ); ::breakpoint(); } } while (0); | |||
| 669 | emit_data((int32_t) adjusted, rspec, disp32_operand); | |||
| 670 | ||||
| 671 | } else { | |||
| 672 | // base == noreg, index == noreg, no_relocation == true | |||
| 673 | // 32bit never did this, did everything as the rip-rel/disp code above | |||
| 674 | // [disp] ABSOLUTE | |||
| 675 | // [00 reg 100][00 100 101] disp32 | |||
| 676 | emit_modrm_sib(0b00, reg_enc, 0b100 /* no base */, | |||
| 677 | Address::times_1, 0b100, 0b101); | |||
| 678 | emit_data(disp, rspec, disp32_operand); | |||
| 679 | } | |||
| 680 | } | |||
| 681 | } | |||
| 682 | ||||
| 683 | void Assembler::emit_operand(Register reg, Register base, Register index, | |||
| 684 | Address::ScaleFactor scale, int disp, | |||
| 685 | RelocationHolder const& rspec, | |||
| 686 | int rip_relative_correction) { | |||
| 687 | assert(!index->is_valid() || index != rsp, "illegal addressing mode")do { if (!(!index->is_valid() || index != rsp)) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 687, "assert(" "!index->is_valid() || index != rsp" ") failed" , "illegal addressing mode"); ::breakpoint(); } } while (0); | |||
| 688 | emit_operand_helper(raw_encode(reg), raw_encode(base), raw_encode(index), | |||
| 689 | scale, disp, rspec, rip_relative_correction); | |||
| 690 | ||||
| 691 | } | |||
| 692 | void Assembler::emit_operand(XMMRegister xmmreg, Register base, Register index, | |||
| 693 | Address::ScaleFactor scale, int disp, | |||
| 694 | RelocationHolder const& rspec) { | |||
| 695 | assert(!index->is_valid() || index != rsp, "illegal addressing mode")do { if (!(!index->is_valid() || index != rsp)) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 695, "assert(" "!index->is_valid() || index != rsp" ") failed" , "illegal addressing mode"); ::breakpoint(); } } while (0); | |||
| 696 | assert(xmmreg->encoding() < 16 || UseAVX > 2, "not supported")do { if (!(xmmreg->encoding() < 16 || UseAVX > 2)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 696, "assert(" "xmmreg->encoding() < 16 || UseAVX > 2" ") failed", "not supported"); ::breakpoint(); } } while (0); | |||
| 697 | emit_operand_helper(raw_encode(xmmreg), raw_encode(base), raw_encode(index), | |||
| 698 | scale, disp, rspec); | |||
| 699 | } | |||
| 700 | ||||
| 701 | void Assembler::emit_operand(XMMRegister xmmreg, Register base, XMMRegister xmmindex, | |||
| 702 | Address::ScaleFactor scale, int disp, | |||
| 703 | RelocationHolder const& rspec) { | |||
| 704 | assert(xmmreg->encoding() < 16 || UseAVX > 2, "not supported")do { if (!(xmmreg->encoding() < 16 || UseAVX > 2)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 704, "assert(" "xmmreg->encoding() < 16 || UseAVX > 2" ") failed", "not supported"); ::breakpoint(); } } while (0); | |||
| 705 | assert(xmmindex->encoding() < 16 || UseAVX > 2, "not supported")do { if (!(xmmindex->encoding() < 16 || UseAVX > 2)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 705, "assert(" "xmmindex->encoding() < 16 || UseAVX > 2" ") failed", "not supported"); ::breakpoint(); } } while (0); | |||
| 706 | emit_operand_helper(raw_encode(xmmreg), raw_encode(base), raw_encode(xmmindex), | |||
| 707 | scale, disp, rspec, /* rip_relative_correction */ 0); | |||
| 708 | } | |||
| 709 | ||||
| 710 | // Secret local extension to Assembler::WhichOperand: | |||
| 711 | #define end_pc_operand(_WhichOperand_limit) (_WhichOperand_limit) | |||
| 712 | ||||
| 713 | address Assembler::locate_operand(address inst, WhichOperand which) { | |||
| 714 | // Decode the given instruction, and return the address of | |||
| 715 | // an embedded 32-bit operand word. | |||
| 716 | ||||
| 717 | // If "which" is disp32_operand, selects the displacement portion | |||
| 718 | // of an effective address specifier. | |||
| 719 | // If "which" is imm64_operand, selects the trailing immediate constant. | |||
| 720 | // If "which" is call32_operand, selects the displacement of a call or jump. | |||
| 721 | // Caller is responsible for ensuring that there is such an operand, | |||
| 722 | // and that it is 32/64 bits wide. | |||
| 723 | ||||
| 724 | // If "which" is end_pc_operand, find the end of the instruction. | |||
| 725 | ||||
| 726 | address ip = inst; | |||
| 727 | bool is_64bit = false; | |||
| 728 | ||||
| 729 | debug_only(bool has_disp32 = false)bool has_disp32 = false; | |||
| 730 | int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn | |||
| 731 | ||||
| 732 | again_after_prefix: | |||
| 733 | switch (0xFF & *ip++) { | |||
| 734 | ||||
| 735 | // These convenience macros generate groups of "case" labels for the switch. | |||
| 736 | #define REP4(x)(x)+0: case (x)+1: case (x)+2: case (x)+3 (x)+0: case (x)+1: case (x)+2: case (x)+3 | |||
| 737 | #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \ | |||
| 738 | case (x)+4: case (x)+5: case (x)+6: case (x)+7 | |||
| 739 | #define REP16(x) REP8((x)+0): \ | |||
| 740 | case REP8((x)+8) | |||
| 741 | ||||
| 742 | case CS_segment: | |||
| 743 | case SS_segment: | |||
| 744 | case DS_segment: | |||
| 745 | case ES_segment: | |||
| 746 | case FS_segment: | |||
| 747 | case GS_segment: | |||
| 748 | // Seems dubious | |||
| 749 | LP64_ONLY(assert(false, "shouldn't have that prefix"))do { if (!(false)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 749, "assert(" "false" ") failed", "shouldn't have that prefix" ); ::breakpoint(); } } while (0); | |||
| 750 | assert(ip == inst+1, "only one prefix allowed")do { if (!(ip == inst+1)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 750, "assert(" "ip == inst+1" ") failed", "only one prefix allowed" ); ::breakpoint(); } } while (0); | |||
| 751 | goto again_after_prefix; | |||
| 752 | ||||
| 753 | case 0x67: | |||
| 754 | case REX: | |||
| 755 | case REX_B: | |||
| 756 | case REX_X: | |||
| 757 | case REX_XB: | |||
| 758 | case REX_R: | |||
| 759 | case REX_RB: | |||
| 760 | case REX_RX: | |||
| 761 | case REX_RXB: | |||
| 762 | NOT_LP64(assert(false, "64bit prefixes")); | |||
| 763 | goto again_after_prefix; | |||
| 764 | ||||
| 765 | case REX_W: | |||
| 766 | case REX_WB: | |||
| 767 | case REX_WX: | |||
| 768 | case REX_WXB: | |||
| 769 | case REX_WR: | |||
| 770 | case REX_WRB: | |||
| 771 | case REX_WRX: | |||
| 772 | case REX_WRXB: | |||
| 773 | NOT_LP64(assert(false, "64bit prefixes")); | |||
| 774 | is_64bit = true; | |||
| 775 | goto again_after_prefix; | |||
| 776 | ||||
| 777 | case 0xFF: // pushq a; decl a; incl a; call a; jmp a | |||
| 778 | case 0x88: // movb a, r | |||
| 779 | case 0x89: // movl a, r | |||
| 780 | case 0x8A: // movb r, a | |||
| 781 | case 0x8B: // movl r, a | |||
| 782 | case 0x8F: // popl a | |||
| 783 | debug_only(has_disp32 = true)has_disp32 = true; | |||
| 784 | break; | |||
| 785 | ||||
| 786 | case 0x68: // pushq #32 | |||
| 787 | if (which == end_pc_operand(_WhichOperand_limit)) { | |||
| 788 | return ip + 4; | |||
| 789 | } | |||
| 790 | assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate")do { if (!(which == imm_operand && !is_64bit)) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 790, "assert(" "which == imm_operand && !is_64bit" ") failed" , "pushl has no disp32 or 64bit immediate"); ::breakpoint(); } } while (0); | |||
| 791 | return ip; // not produced by emit_operand | |||
| 792 | ||||
| 793 | case 0x66: // movw ... (size prefix) | |||
| 794 | again_after_size_prefix2: | |||
| 795 | switch (0xFF & *ip++) { | |||
| 796 | case REX: | |||
| 797 | case REX_B: | |||
| 798 | case REX_X: | |||
| 799 | case REX_XB: | |||
| 800 | case REX_R: | |||
| 801 | case REX_RB: | |||
| 802 | case REX_RX: | |||
| 803 | case REX_RXB: | |||
| 804 | case REX_W: | |||
| 805 | case REX_WB: | |||
| 806 | case REX_WX: | |||
| 807 | case REX_WXB: | |||
| 808 | case REX_WR: | |||
| 809 | case REX_WRB: | |||
| 810 | case REX_WRX: | |||
| 811 | case REX_WRXB: | |||
| 812 | NOT_LP64(assert(false, "64bit prefix found")); | |||
| 813 | goto again_after_size_prefix2; | |||
| 814 | case 0x8B: // movw r, a | |||
| 815 | case 0x89: // movw a, r | |||
| 816 | debug_only(has_disp32 = true)has_disp32 = true; | |||
| 817 | break; | |||
| 818 | case 0xC7: // movw a, #16 | |||
| 819 | debug_only(has_disp32 = true)has_disp32 = true; | |||
| 820 | tail_size = 2; // the imm16 | |||
| 821 | break; | |||
| 822 | case 0x0F: // several SSE/SSE2 variants | |||
| 823 | ip--; // reparse the 0x0F | |||
| 824 | goto again_after_prefix; | |||
| 825 | default: | |||
| 826 | ShouldNotReachHere()do { (*g_assert_poison) = 'X';; report_should_not_reach_here( "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 826); ::breakpoint(); } while (0); | |||
| 827 | } | |||
| 828 | break; | |||
| 829 | ||||
| 830 | case REP8(0xB8): // movl/q r, #32/#64(oop?) | |||
| 831 | if (which == end_pc_operand(_WhichOperand_limit)) return ip + (is_64bit ? 8 : 4); | |||
| 832 | // these asserts are somewhat nonsensical | |||
| 833 | #ifndef _LP641 | |||
| 834 | assert(which == imm_operand || which == disp32_operand,do { if (!(which == imm_operand || which == disp32_operand)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 835, "assert(" "which == imm_operand || which == disp32_operand" ") failed", "which %d is_64_bit %d ip " "0x%016" "l" "x", which , is_64bit, p2i(ip)); ::breakpoint(); } } while (0) | |||
| 835 | "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip))do { if (!(which == imm_operand || which == disp32_operand)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 835, "assert(" "which == imm_operand || which == disp32_operand" ") failed", "which %d is_64_bit %d ip " "0x%016" "l" "x", which , is_64bit, p2i(ip)); ::breakpoint(); } } while (0); | |||
| 836 | #else | |||
| 837 | assert((which == call32_operand || which == imm_operand) && is_64bit ||do { if (!((which == call32_operand || which == imm_operand) && is_64bit || which == narrow_oop_operand && !is_64bit )) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 839, "assert(" "(which == call32_operand || which == imm_operand) && is_64bit || which == narrow_oop_operand && !is_64bit" ") failed", "which %d is_64_bit %d ip " "0x%016" "l" "x", which , is_64bit, p2i(ip)); ::breakpoint(); } } while (0) | |||
| 838 | which == narrow_oop_operand && !is_64bit,do { if (!((which == call32_operand || which == imm_operand) && is_64bit || which == narrow_oop_operand && !is_64bit )) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 839, "assert(" "(which == call32_operand || which == imm_operand) && is_64bit || which == narrow_oop_operand && !is_64bit" ") failed", "which %d is_64_bit %d ip " "0x%016" "l" "x", which , is_64bit, p2i(ip)); ::breakpoint(); } } while (0) | |||
| 839 | "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip))do { if (!((which == call32_operand || which == imm_operand) && is_64bit || which == narrow_oop_operand && !is_64bit )) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 839, "assert(" "(which == call32_operand || which == imm_operand) && is_64bit || which == narrow_oop_operand && !is_64bit" ") failed", "which %d is_64_bit %d ip " "0x%016" "l" "x", which , is_64bit, p2i(ip)); ::breakpoint(); } } while (0); | |||
| 840 | #endif // _LP64 | |||
| 841 | return ip; | |||
| 842 | ||||
| 843 | case 0x69: // imul r, a, #32 | |||
| 844 | case 0xC7: // movl a, #32(oop?) | |||
| 845 | tail_size = 4; | |||
| 846 | debug_only(has_disp32 = true)has_disp32 = true; // has both kinds of operands! | |||
| 847 | break; | |||
| 848 | ||||
| 849 | case 0x0F: // movx..., etc. | |||
| 850 | switch (0xFF & *ip++) { | |||
| 851 | case 0x3A: // pcmpestri | |||
| 852 | tail_size = 1; | |||
| 853 | case 0x38: // ptest, pmovzxbw | |||
| 854 | ip++; // skip opcode | |||
| 855 | debug_only(has_disp32 = true)has_disp32 = true; // has both kinds of operands! | |||
| 856 | break; | |||
| 857 | ||||
| 858 | case 0x70: // pshufd r, r/a, #8 | |||
| 859 | debug_only(has_disp32 = true)has_disp32 = true; // has both kinds of operands! | |||
| 860 | case 0x73: // psrldq r, #8 | |||
| 861 | tail_size = 1; | |||
| 862 | break; | |||
| 863 | ||||
| 864 | case 0x12: // movlps | |||
| 865 | case 0x28: // movaps | |||
| 866 | case 0x2E: // ucomiss | |||
| 867 | case 0x2F: // comiss | |||
| 868 | case 0x54: // andps | |||
| 869 | case 0x55: // andnps | |||
| 870 | case 0x56: // orps | |||
| 871 | case 0x57: // xorps | |||
| 872 | case 0x58: // addpd | |||
| 873 | case 0x59: // mulpd | |||
| 874 | case 0x6E: // movd | |||
| 875 | case 0x7E: // movd | |||
| 876 | case 0x6F: // movdq | |||
| 877 | case 0x7F: // movdq | |||
| 878 | case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush | |||
| 879 | case 0xFE: // paddd | |||
| 880 | debug_only(has_disp32 = true)has_disp32 = true; | |||
| 881 | break; | |||
| 882 | ||||
| 883 | case 0xAD: // shrd r, a, %cl | |||
| 884 | case 0xAF: // imul r, a | |||
| 885 | case 0xBE: // movsbl r, a (movsxb) | |||
| 886 | case 0xBF: // movswl r, a (movsxw) | |||
| 887 | case 0xB6: // movzbl r, a (movzxb) | |||
| 888 | case 0xB7: // movzwl r, a (movzxw) | |||
| 889 | case REP16(0x40): // cmovl cc, r, a | |||
| 890 | case 0xB0: // cmpxchgb | |||
| 891 | case 0xB1: // cmpxchg | |||
| 892 | case 0xC1: // xaddl | |||
| 893 | case 0xC7: // cmpxchg8 | |||
| 894 | case REP16(0x90): // setcc a | |||
| 895 | debug_only(has_disp32 = true)has_disp32 = true; | |||
| 896 | // fall out of the switch to decode the address | |||
| 897 | break; | |||
| 898 | ||||
| 899 | case 0xC4: // pinsrw r, a, #8 | |||
| 900 | debug_only(has_disp32 = true)has_disp32 = true; | |||
| 901 | case 0xC5: // pextrw r, r, #8 | |||
| 902 | tail_size = 1; // the imm8 | |||
| 903 | break; | |||
| 904 | ||||
| 905 | case 0xAC: // shrd r, a, #8 | |||
| 906 | debug_only(has_disp32 = true)has_disp32 = true; | |||
| 907 | tail_size = 1; // the imm8 | |||
| 908 | break; | |||
| 909 | ||||
| 910 | case REP16(0x80): // jcc rdisp32 | |||
| 911 | if (which == end_pc_operand(_WhichOperand_limit)) return ip + 4; | |||
| 912 | assert(which == call32_operand, "jcc has no disp32 or imm")do { if (!(which == call32_operand)) { (*g_assert_poison) = 'X' ;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 912, "assert(" "which == call32_operand" ") failed", "jcc has no disp32 or imm" ); ::breakpoint(); } } while (0); | |||
| 913 | return ip; | |||
| 914 | default: | |||
| 915 | ShouldNotReachHere()do { (*g_assert_poison) = 'X';; report_should_not_reach_here( "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 915); ::breakpoint(); } while (0); | |||
| 916 | } | |||
| 917 | break; | |||
| 918 | ||||
| 919 | case 0x81: // addl a, #32; addl r, #32 | |||
| 920 | // also: orl, adcl, sbbl, andl, subl, xorl, cmpl | |||
| 921 | // on 32bit in the case of cmpl, the imm might be an oop | |||
| 922 | tail_size = 4; | |||
| 923 | debug_only(has_disp32 = true)has_disp32 = true; // has both kinds of operands! | |||
| 924 | break; | |||
| 925 | ||||
| 926 | case 0x83: // addl a, #8; addl r, #8 | |||
| 927 | // also: orl, adcl, sbbl, andl, subl, xorl, cmpl | |||
| 928 | debug_only(has_disp32 = true)has_disp32 = true; // has both kinds of operands! | |||
| 929 | tail_size = 1; | |||
| 930 | break; | |||
| 931 | ||||
| 932 | case 0x9B: | |||
| 933 | switch (0xFF & *ip++) { | |||
| 934 | case 0xD9: // fnstcw a | |||
| 935 | debug_only(has_disp32 = true)has_disp32 = true; | |||
| 936 | break; | |||
| 937 | default: | |||
| 938 | ShouldNotReachHere()do { (*g_assert_poison) = 'X';; report_should_not_reach_here( "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 938); ::breakpoint(); } while (0); | |||
| 939 | } | |||
| 940 | break; | |||
| 941 | ||||
| 942 | case REP4(0x00)(0x00)+0: case (0x00)+1: case (0x00)+2: case (0x00)+3: // addb a, r; addl a, r; addb r, a; addl r, a | |||
| 943 | case REP4(0x10)(0x10)+0: case (0x10)+1: case (0x10)+2: case (0x10)+3: // adc... | |||
| 944 | case REP4(0x20)(0x20)+0: case (0x20)+1: case (0x20)+2: case (0x20)+3: // and... | |||
| 945 | case REP4(0x30)(0x30)+0: case (0x30)+1: case (0x30)+2: case (0x30)+3: // xor... | |||
| 946 | case REP4(0x08)(0x08)+0: case (0x08)+1: case (0x08)+2: case (0x08)+3: // or... | |||
| 947 | case REP4(0x18)(0x18)+0: case (0x18)+1: case (0x18)+2: case (0x18)+3: // sbb... | |||
| 948 | case REP4(0x28)(0x28)+0: case (0x28)+1: case (0x28)+2: case (0x28)+3: // sub... | |||
| 949 | case 0xF7: // mull a | |||
| 950 | case 0x8D: // lea r, a | |||
| 951 | case 0x87: // xchg r, a | |||
| 952 | case REP4(0x38)(0x38)+0: case (0x38)+1: case (0x38)+2: case (0x38)+3: // cmp... | |||
| 953 | case 0x85: // test r, a | |||
| 954 | debug_only(has_disp32 = true)has_disp32 = true; // has both kinds of operands! | |||
| 955 | break; | |||
| 956 | ||||
| 957 | case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8 | |||
| 958 | case 0xC6: // movb a, #8 | |||
| 959 | case 0x80: // cmpb a, #8 | |||
| 960 | case 0x6B: // imul r, a, #8 | |||
| 961 | debug_only(has_disp32 = true)has_disp32 = true; // has both kinds of operands! | |||
| 962 | tail_size = 1; // the imm8 | |||
| 963 | break; | |||
| 964 | ||||
| 965 | case 0xC4: // VEX_3bytes | |||
| 966 | case 0xC5: // VEX_2bytes | |||
| 967 | assert((UseAVX > 0), "shouldn't have VEX prefix")do { if (!((UseAVX > 0))) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 967, "assert(" "(UseAVX > 0)" ") failed", "shouldn't have VEX prefix" ); ::breakpoint(); } } while (0); | |||
| 968 | assert(ip == inst+1, "no prefixes allowed")do { if (!(ip == inst+1)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 968, "assert(" "ip == inst+1" ") failed", "no prefixes allowed" ); ::breakpoint(); } } while (0); | |||
| 969 | // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions | |||
| 970 | // but they have prefix 0x0F and processed when 0x0F processed above. | |||
| 971 | // | |||
| 972 | // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES | |||
| 973 | // instructions (these instructions are not supported in 64-bit mode). | |||
| 974 | // To distinguish them bits [7:6] are set in the VEX second byte since | |||
| 975 | // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set | |||
| 976 | // those VEX bits REX and vvvv bits are inverted. | |||
| 977 | // | |||
| 978 | // Fortunately C2 doesn't generate these instructions so we don't need | |||
| 979 | // to check for them in product version. | |||
| 980 | ||||
| 981 | // Check second byte | |||
| 982 | NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions")); | |||
| 983 | ||||
| 984 | int vex_opcode; | |||
| 985 | // First byte | |||
| 986 | if ((0xFF & *inst) == VEX_3bytes) { | |||
| 987 | vex_opcode = VEX_OPCODE_MASK & *ip; | |||
| 988 | ip++; // third byte | |||
| 989 | is_64bit = ((VEX_W & *ip) == VEX_W); | |||
| 990 | } else { | |||
| 991 | vex_opcode = VEX_OPCODE_0F; | |||
| 992 | } | |||
| 993 | ip++; // opcode | |||
| 994 | // To find the end of instruction (which == end_pc_operand). | |||
| 995 | switch (vex_opcode) { | |||
| 996 | case VEX_OPCODE_0F: | |||
| 997 | switch (0xFF & *ip) { | |||
| 998 | case 0x70: // pshufd r, r/a, #8 | |||
| 999 | case 0x71: // ps[rl|ra|ll]w r, #8 | |||
| 1000 | case 0x72: // ps[rl|ra|ll]d r, #8 | |||
| 1001 | case 0x73: // ps[rl|ra|ll]q r, #8 | |||
| 1002 | case 0xC2: // cmp[ps|pd|ss|sd] r, r, r/a, #8 | |||
| 1003 | case 0xC4: // pinsrw r, r, r/a, #8 | |||
| 1004 | case 0xC5: // pextrw r/a, r, #8 | |||
| 1005 | case 0xC6: // shufp[s|d] r, r, r/a, #8 | |||
| 1006 | tail_size = 1; // the imm8 | |||
| 1007 | break; | |||
| 1008 | } | |||
| 1009 | break; | |||
| 1010 | case VEX_OPCODE_0F_3A: | |||
| 1011 | tail_size = 1; | |||
| 1012 | break; | |||
| 1013 | } | |||
| 1014 | ip++; // skip opcode | |||
| 1015 | debug_only(has_disp32 = true)has_disp32 = true; // has both kinds of operands! | |||
| 1016 | break; | |||
| 1017 | ||||
| 1018 | case 0x62: // EVEX_4bytes | |||
| 1019 | assert(VM_Version::supports_evex(), "shouldn't have EVEX prefix")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 1019, "assert(" "VM_Version::supports_evex()" ") failed", "shouldn't have EVEX prefix" ); ::breakpoint(); } } while (0); | |||
| 1020 | assert(ip == inst+1, "no prefixes allowed")do { if (!(ip == inst+1)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 1020, "assert(" "ip == inst+1" ") failed", "no prefixes allowed" ); ::breakpoint(); } } while (0); | |||
| 1021 | // no EVEX collisions, all instructions that have 0x62 opcodes | |||
| 1022 | // have EVEX versions and are subopcodes of 0x66 | |||
| 1023 | ip++; // skip P0 and exmaine W in P1 | |||
| 1024 | is_64bit = ((VEX_W & *ip) == VEX_W); | |||
| 1025 | ip++; // move to P2 | |||
| 1026 | ip++; // skip P2, move to opcode | |||
| 1027 | // To find the end of instruction (which == end_pc_operand). | |||
| 1028 | switch (0xFF & *ip) { | |||
| 1029 | case 0x22: // pinsrd r, r/a, #8 | |||
| 1030 | case 0x61: // pcmpestri r, r/a, #8 | |||
| 1031 | case 0x70: // pshufd r, r/a, #8 | |||
| 1032 | case 0x73: // psrldq r, #8 | |||
| 1033 | case 0x1f: // evpcmpd/evpcmpq | |||
| 1034 | case 0x3f: // evpcmpb/evpcmpw | |||
| 1035 | tail_size = 1; // the imm8 | |||
| 1036 | break; | |||
| 1037 | default: | |||
| 1038 | break; | |||
| 1039 | } | |||
| 1040 | ip++; // skip opcode | |||
| 1041 | debug_only(has_disp32 = true)has_disp32 = true; // has both kinds of operands! | |||
| 1042 | break; | |||
| 1043 | ||||
| 1044 | case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1 | |||
| 1045 | case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl | |||
| 1046 | case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a | |||
| 1047 | case 0xDD: // fld_d a; fst_d a; fstp_d a | |||
| 1048 | case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a | |||
| 1049 | case 0xDF: // fild_d a; fistp_d a | |||
| 1050 | case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a | |||
| 1051 | case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a | |||
| 1052 | case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a | |||
| 1053 | debug_only(has_disp32 = true)has_disp32 = true; | |||
| 1054 | break; | |||
| 1055 | ||||
| 1056 | case 0xE8: // call rdisp32 | |||
| 1057 | case 0xE9: // jmp rdisp32 | |||
| 1058 | if (which == end_pc_operand(_WhichOperand_limit)) return ip + 4; | |||
| 1059 | assert(which == call32_operand, "call has no disp32 or imm")do { if (!(which == call32_operand)) { (*g_assert_poison) = 'X' ;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 1059, "assert(" "which == call32_operand" ") failed", "call has no disp32 or imm" ); ::breakpoint(); } } while (0); | |||
| 1060 | return ip; | |||
| 1061 | ||||
| 1062 | case 0xF0: // Lock | |||
| 1063 | goto again_after_prefix; | |||
| 1064 | ||||
| 1065 | case 0xF3: // For SSE | |||
| 1066 | case 0xF2: // For SSE2 | |||
| 1067 | switch (0xFF & *ip++) { | |||
| 1068 | case REX: | |||
| 1069 | case REX_B: | |||
| 1070 | case REX_X: | |||
| 1071 | case REX_XB: | |||
| 1072 | case REX_R: | |||
| 1073 | case REX_RB: | |||
| 1074 | case REX_RX: | |||
| 1075 | case REX_RXB: | |||
| 1076 | case REX_W: | |||
| 1077 | case REX_WB: | |||
| 1078 | case REX_WX: | |||
| 1079 | case REX_WXB: | |||
| 1080 | case REX_WR: | |||
| 1081 | case REX_WRB: | |||
| 1082 | case REX_WRX: | |||
| 1083 | case REX_WRXB: | |||
| 1084 | NOT_LP64(assert(false, "found 64bit prefix")); | |||
| 1085 | ip++; | |||
| 1086 | default: | |||
| 1087 | ip++; | |||
| 1088 | } | |||
| 1089 | debug_only(has_disp32 = true)has_disp32 = true; // has both kinds of operands! | |||
| 1090 | break; | |||
| 1091 | ||||
| 1092 | default: | |||
| 1093 | ShouldNotReachHere()do { (*g_assert_poison) = 'X';; report_should_not_reach_here( "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 1093); ::breakpoint(); } while (0); | |||
| 1094 | ||||
| 1095 | #undef REP8 | |||
| 1096 | #undef REP16 | |||
| 1097 | } | |||
| 1098 | ||||
| 1099 | assert(which != call32_operand, "instruction is not a call, jmp, or jcc")do { if (!(which != call32_operand)) { (*g_assert_poison) = 'X' ;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 1099, "assert(" "which != call32_operand" ") failed", "instruction is not a call, jmp, or jcc" ); ::breakpoint(); } } while (0); | |||
| 1100 | #ifdef _LP641 | |||
| 1101 | assert(which != imm_operand, "instruction is not a movq reg, imm64")do { if (!(which != imm_operand)) { (*g_assert_poison) = 'X'; ; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 1101, "assert(" "which != imm_operand" ") failed", "instruction is not a movq reg, imm64" ); ::breakpoint(); } } while (0); | |||
| 1102 | #else | |||
| 1103 | // assert(which != imm_operand || has_imm32, "instruction has no imm32 field"); | |||
| 1104 | assert(which != imm_operand || has_disp32, "instruction has no imm32 field")do { if (!(which != imm_operand || has_disp32)) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 1104, "assert(" "which != imm_operand || has_disp32" ") failed" , "instruction has no imm32 field"); ::breakpoint(); } } while (0); | |||
| 1105 | #endif // LP64 | |||
| 1106 | assert(which != disp32_operand || has_disp32, "instruction has no disp32 field")do { if (!(which != disp32_operand || has_disp32)) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 1106, "assert(" "which != disp32_operand || has_disp32" ") failed" , "instruction has no disp32 field"); ::breakpoint(); } } while (0); | |||
| 1107 | ||||
| 1108 | // parse the output of emit_operand | |||
| 1109 | int op2 = 0xFF & *ip++; | |||
| 1110 | int base = op2 & 0x07; | |||
| 1111 | int op3 = -1; | |||
| 1112 | const int b100 = 4; | |||
| 1113 | const int b101 = 5; | |||
| 1114 | if (base == b100 && (op2 >> 6) != 3) { | |||
| 1115 | op3 = 0xFF & *ip++; | |||
| 1116 | base = op3 & 0x07; // refetch the base | |||
| 1117 | } | |||
| 1118 | // now ip points at the disp (if any) | |||
| 1119 | ||||
| 1120 | switch (op2 >> 6) { | |||
| 1121 | case 0: | |||
| 1122 | // [00 reg 100][ss index base] | |||
| 1123 | // [00 reg 100][00 100 esp] | |||
| 1124 | // [00 reg base] | |||
| 1125 | // [00 reg 100][ss index 101][disp32] | |||
| 1126 | // [00 reg 101] [disp32] | |||
| 1127 | ||||
| 1128 | if (base == b101) { | |||
| 1129 | if (which == disp32_operand) | |||
| 1130 | return ip; // caller wants the disp32 | |||
| 1131 | ip += 4; // skip the disp32 | |||
| 1132 | } | |||
| 1133 | break; | |||
| 1134 | ||||
| 1135 | case 1: | |||
| 1136 | // [01 reg 100][ss index base][disp8] | |||
| 1137 | // [01 reg 100][00 100 esp][disp8] | |||
| 1138 | // [01 reg base] [disp8] | |||
| 1139 | ip += 1; // skip the disp8 | |||
| 1140 | break; | |||
| 1141 | ||||
| 1142 | case 2: | |||
| 1143 | // [10 reg 100][ss index base][disp32] | |||
| 1144 | // [10 reg 100][00 100 esp][disp32] | |||
| 1145 | // [10 reg base] [disp32] | |||
| 1146 | if (which == disp32_operand) | |||
| 1147 | return ip; // caller wants the disp32 | |||
| 1148 | ip += 4; // skip the disp32 | |||
| 1149 | break; | |||
| 1150 | ||||
| 1151 | case 3: | |||
| 1152 | // [11 reg base] (not a memory addressing mode) | |||
| 1153 | break; | |||
| 1154 | } | |||
| 1155 | ||||
| 1156 | if (which == end_pc_operand(_WhichOperand_limit)) { | |||
| 1157 | return ip + tail_size; | |||
| 1158 | } | |||
| 1159 | ||||
| 1160 | #ifdef _LP641 | |||
| 1161 | assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32")do { if (!(which == narrow_oop_operand && !is_64bit)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 1161, "assert(" "which == narrow_oop_operand && !is_64bit" ") failed", "instruction is not a movl adr, imm32"); ::breakpoint (); } } while (0); | |||
| 1162 | #else | |||
| 1163 | assert(which == imm_operand, "instruction has only an imm field")do { if (!(which == imm_operand)) { (*g_assert_poison) = 'X'; ; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 1163, "assert(" "which == imm_operand" ") failed", "instruction has only an imm field" ); ::breakpoint(); } } while (0); | |||
| 1164 | #endif // LP64 | |||
| 1165 | return ip; | |||
| 1166 | } | |||
| 1167 | ||||
| 1168 | address Assembler::locate_next_instruction(address inst) { | |||
| 1169 | // Secretly share code with locate_operand: | |||
| 1170 | return locate_operand(inst, end_pc_operand(_WhichOperand_limit)); | |||
| 1171 | } | |||
| 1172 | ||||
| 1173 | ||||
| 1174 | #ifdef ASSERT1 | |||
| 1175 | void Assembler::check_relocation(RelocationHolder const& rspec, int format) { | |||
| 1176 | address inst = inst_mark(); | |||
| 1177 | assert(inst != NULL && inst < pc(), "must point to beginning of instruction")do { if (!(inst != __null && inst < pc())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 1177, "assert(" "inst != __null && inst < pc()" ") failed" , "must point to beginning of instruction"); ::breakpoint(); } } while (0); | |||
| 1178 | address opnd; | |||
| 1179 | ||||
| 1180 | Relocation* r = rspec.reloc(); | |||
| 1181 | if (r->type() == relocInfo::none) { | |||
| 1182 | return; | |||
| 1183 | } else if (r->is_call() || format == call32_operand) { | |||
| 1184 | // assert(format == imm32_operand, "cannot specify a nonzero format"); | |||
| 1185 | opnd = locate_operand(inst, call32_operand); | |||
| 1186 | } else if (r->is_data()) { | |||
| 1187 | assert(format == imm_operand || format == disp32_operanddo { if (!(format == imm_operand || format == disp32_operand || format == narrow_oop_operand)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 1188, "assert(" "format == imm_operand || format == disp32_operand || format == narrow_oop_operand" ") failed", "format ok"); ::breakpoint(); } } while (0) | |||
| 1188 | LP64_ONLY(|| format == narrow_oop_operand), "format ok")do { if (!(format == imm_operand || format == disp32_operand || format == narrow_oop_operand)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 1188, "assert(" "format == imm_operand || format == disp32_operand || format == narrow_oop_operand" ") failed", "format ok"); ::breakpoint(); } } while (0); | |||
| 1189 | opnd = locate_operand(inst, (WhichOperand)format); | |||
| 1190 | } else { | |||
| 1191 | assert(format == imm_operand, "cannot specify a format")do { if (!(format == imm_operand)) { (*g_assert_poison) = 'X' ;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 1191, "assert(" "format == imm_operand" ") failed", "cannot specify a format" ); ::breakpoint(); } } while (0); | |||
| 1192 | return; | |||
| 1193 | } | |||
| 1194 | assert(opnd == pc(), "must put operand where relocs can find it")do { if (!(opnd == pc())) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 1194, "assert(" "opnd == pc()" ") failed", "must put operand where relocs can find it" ); ::breakpoint(); } } while (0); | |||
| 1195 | } | |||
| 1196 | #endif // ASSERT | |||
| 1197 | ||||
| 1198 | void Assembler::emit_operand(Register reg, Address adr, | |||
| 1199 | int rip_relative_correction) { | |||
| 1200 | emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, | |||
| 1201 | adr._rspec, | |||
| 1202 | rip_relative_correction); | |||
| 1203 | } | |||
| 1204 | ||||
| 1205 | void Assembler::emit_operand(XMMRegister reg, Address adr) { | |||
| 1206 | if (adr.isxmmindex()) { | |||
| 1207 | emit_operand(reg, adr._base, adr._xmmindex, adr._scale, adr._disp, adr._rspec); | |||
| 1208 | } else { | |||
| 1209 | emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, | |||
| 1210 | adr._rspec); | |||
| 1211 | } | |||
| 1212 | } | |||
| 1213 | ||||
| 1214 | // Now the Assembler instructions (identical for 32/64 bits) | |||
| 1215 | ||||
| 1216 | void Assembler::adcl(Address dst, int32_t imm32) { | |||
| 1217 | InstructionMark im(this); | |||
| 1218 | prefix(dst); | |||
| 1219 | emit_arith_operand(0x81, rdx, dst, imm32); | |||
| 1220 | } | |||
| 1221 | ||||
| 1222 | void Assembler::adcl(Address dst, Register src) { | |||
| 1223 | InstructionMark im(this); | |||
| 1224 | prefix(dst, src); | |||
| 1225 | emit_int8(0x11); | |||
| 1226 | emit_operand(src, dst); | |||
| 1227 | } | |||
| 1228 | ||||
| 1229 | void Assembler::adcl(Register dst, int32_t imm32) { | |||
| 1230 | prefix(dst); | |||
| 1231 | emit_arith(0x81, 0xD0, dst, imm32); | |||
| 1232 | } | |||
| 1233 | ||||
| 1234 | void Assembler::adcl(Register dst, Address src) { | |||
| 1235 | InstructionMark im(this); | |||
| 1236 | prefix(src, dst); | |||
| 1237 | emit_int8(0x13); | |||
| 1238 | emit_operand(dst, src); | |||
| 1239 | } | |||
| 1240 | ||||
| 1241 | void Assembler::adcl(Register dst, Register src) { | |||
| 1242 | (void) prefix_and_encode(dst->encoding(), src->encoding()); | |||
| 1243 | emit_arith(0x13, 0xC0, dst, src); | |||
| 1244 | } | |||
| 1245 | ||||
| 1246 | void Assembler::addl(Address dst, int32_t imm32) { | |||
| 1247 | InstructionMark im(this); | |||
| 1248 | prefix(dst); | |||
| 1249 | emit_arith_operand(0x81, rax, dst, imm32); | |||
| 1250 | } | |||
| 1251 | ||||
| 1252 | void Assembler::addb(Address dst, int imm8) { | |||
| 1253 | InstructionMark im(this); | |||
| 1254 | prefix(dst); | |||
| 1255 | emit_int8((unsigned char)0x80); | |||
| 1256 | emit_operand(rax, dst, 1); | |||
| 1257 | emit_int8(imm8); | |||
| 1258 | } | |||
| 1259 | ||||
| 1260 | void Assembler::addw(Register dst, Register src) { | |||
| 1261 | (void)prefix_and_encode(dst->encoding(), src->encoding()); | |||
| 1262 | emit_arith(0x03, 0xC0, dst, src); | |||
| 1263 | } | |||
| 1264 | ||||
| 1265 | void Assembler::addw(Address dst, int imm16) { | |||
| 1266 | InstructionMark im(this); | |||
| 1267 | emit_int8(0x66); | |||
| 1268 | prefix(dst); | |||
| 1269 | emit_int8((unsigned char)0x81); | |||
| 1270 | emit_operand(rax, dst, 2); | |||
| 1271 | emit_int16(imm16); | |||
| 1272 | } | |||
| 1273 | ||||
| 1274 | void Assembler::addl(Address dst, Register src) { | |||
| 1275 | InstructionMark im(this); | |||
| 1276 | prefix(dst, src); | |||
| 1277 | emit_int8(0x01); | |||
| 1278 | emit_operand(src, dst); | |||
| 1279 | } | |||
| 1280 | ||||
| 1281 | void Assembler::addl(Register dst, int32_t imm32) { | |||
| 1282 | prefix(dst); | |||
| 1283 | emit_arith(0x81, 0xC0, dst, imm32); | |||
| 1284 | } | |||
| 1285 | ||||
| 1286 | void Assembler::addl(Register dst, Address src) { | |||
| 1287 | InstructionMark im(this); | |||
| 1288 | prefix(src, dst); | |||
| 1289 | emit_int8(0x03); | |||
| 1290 | emit_operand(dst, src); | |||
| 1291 | } | |||
| 1292 | ||||
| 1293 | void Assembler::addl(Register dst, Register src) { | |||
| 1294 | (void) prefix_and_encode(dst->encoding(), src->encoding()); | |||
| 1295 | emit_arith(0x03, 0xC0, dst, src); | |||
| 1296 | } | |||
| 1297 | ||||
| 1298 | void Assembler::addr_nop_4() { | |||
| 1299 | assert(UseAddressNop, "no CPU support")do { if (!(UseAddressNop)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 1299, "assert(" "UseAddressNop" ") failed", "no CPU support" ); ::breakpoint(); } } while (0); | |||
| 1300 | // 4 bytes: NOP DWORD PTR [EAX+0] | |||
| 1301 | emit_int32(0x0F, | |||
| 1302 | 0x1F, | |||
| 1303 | 0x40, // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc); | |||
| 1304 | 0); // 8-bits offset (1 byte) | |||
| 1305 | } | |||
| 1306 | ||||
| 1307 | void Assembler::addr_nop_5() { | |||
| 1308 | assert(UseAddressNop, "no CPU support")do { if (!(UseAddressNop)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 1308, "assert(" "UseAddressNop" ") failed", "no CPU support" ); ::breakpoint(); } } while (0); | |||
| 1309 | // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset | |||
| 1310 | emit_int32(0x0F, | |||
| 1311 | 0x1F, | |||
| 1312 | 0x44, // emit_rm(cbuf, 0x1, EAX_enc, 0x4); | |||
| 1313 | 0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc); | |||
| 1314 | emit_int8(0); // 8-bits offset (1 byte) | |||
| 1315 | } | |||
| 1316 | ||||
| 1317 | void Assembler::addr_nop_7() { | |||
| 1318 | assert(UseAddressNop, "no CPU support")do { if (!(UseAddressNop)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 1318, "assert(" "UseAddressNop" ") failed", "no CPU support" ); ::breakpoint(); } } while (0); | |||
| 1319 | // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset | |||
| 1320 | emit_int24(0x0F, | |||
| 1321 | 0x1F, | |||
| 1322 | (unsigned char)0x80); | |||
| 1323 | // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc); | |||
| 1324 | emit_int32(0); // 32-bits offset (4 bytes) | |||
| 1325 | } | |||
| 1326 | ||||
| 1327 | void Assembler::addr_nop_8() { | |||
| 1328 | assert(UseAddressNop, "no CPU support")do { if (!(UseAddressNop)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 1328, "assert(" "UseAddressNop" ") failed", "no CPU support" ); ::breakpoint(); } } while (0); | |||
| 1329 | // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset | |||
| 1330 | emit_int32(0x0F, | |||
| 1331 | 0x1F, | |||
| 1332 | (unsigned char)0x84, | |||
| 1333 | // emit_rm(cbuf, 0x2, EAX_enc, 0x4); | |||
| 1334 | 0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc); | |||
| 1335 | emit_int32(0); // 32-bits offset (4 bytes) | |||
| 1336 | } | |||
| 1337 | ||||
| 1338 | void Assembler::addsd(XMMRegister dst, XMMRegister src) { | |||
| 1339 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 1340 | InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 1341 | attributes.set_rex_vex_w_reverted(); | |||
| 1342 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); | |||
| 1343 | emit_int16(0x58, (0xC0 | encode)); | |||
| 1344 | } | |||
| 1345 | ||||
| 1346 | void Assembler::addsd(XMMRegister dst, Address src) { | |||
| 1347 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 1348 | InstructionMark im(this); | |||
| 1349 | InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 1350 | attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); | |||
| 1351 | attributes.set_rex_vex_w_reverted(); | |||
| 1352 | simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); | |||
| 1353 | emit_int8(0x58); | |||
| 1354 | emit_operand(dst, src); | |||
| 1355 | } | |||
| 1356 | ||||
| 1357 | void Assembler::addss(XMMRegister dst, XMMRegister src) { | |||
| 1358 | NOT_LP64(assert(VM_Version::supports_sse(), "")); | |||
| 1359 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 1360 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); | |||
| 1361 | emit_int16(0x58, (0xC0 | encode)); | |||
| 1362 | } | |||
| 1363 | ||||
| 1364 | void Assembler::addss(XMMRegister dst, Address src) { | |||
| 1365 | NOT_LP64(assert(VM_Version::supports_sse(), "")); | |||
| 1366 | InstructionMark im(this); | |||
| 1367 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 1368 | attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); | |||
| 1369 | simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); | |||
| 1370 | emit_int8(0x58); | |||
| 1371 | emit_operand(dst, src); | |||
| 1372 | } | |||
| 1373 | ||||
| 1374 | void Assembler::aesdec(XMMRegister dst, Address src) { | |||
| 1375 | assert(VM_Version::supports_aes(), "")do { if (!(VM_Version::supports_aes())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 1375, "assert(" "VM_Version::supports_aes()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 1376 | InstructionMark im(this); | |||
| 1377 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 1378 | simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 1379 | emit_int8((unsigned char)0xDE); | |||
| 1380 | emit_operand(dst, src); | |||
| 1381 | } | |||
| 1382 | ||||
| 1383 | void Assembler::aesdec(XMMRegister dst, XMMRegister src) { | |||
| 1384 | assert(VM_Version::supports_aes(), "")do { if (!(VM_Version::supports_aes())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 1384, "assert(" "VM_Version::supports_aes()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 1385 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 1386 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 1387 | emit_int16((unsigned char)0xDE, (0xC0 | encode)); | |||
| 1388 | } | |||
| 1389 | ||||
| 1390 | void Assembler::vaesdec(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 1391 | assert(VM_Version::supports_avx512_vaes(), "")do { if (!(VM_Version::supports_avx512_vaes())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 1391, "assert(" "VM_Version::supports_avx512_vaes()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 1392 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 1393 | attributes.set_is_evex_instruction(); | |||
| 1394 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 1395 | emit_int16((unsigned char)0xDE, (0xC0 | encode)); | |||
| 1396 | } | |||
| 1397 | ||||
| 1398 | ||||
| 1399 | void Assembler::aesdeclast(XMMRegister dst, Address src) { | |||
| 1400 | assert(VM_Version::supports_aes(), "")do { if (!(VM_Version::supports_aes())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 1400, "assert(" "VM_Version::supports_aes()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 1401 | InstructionMark im(this); | |||
| 1402 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 1403 | simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 1404 | emit_int8((unsigned char)0xDF); | |||
| 1405 | emit_operand(dst, src); | |||
| 1406 | } | |||
| 1407 | ||||
| 1408 | void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) { | |||
| 1409 | assert(VM_Version::supports_aes(), "")do { if (!(VM_Version::supports_aes())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 1409, "assert(" "VM_Version::supports_aes()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 1410 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 1411 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 1412 | emit_int16((unsigned char)0xDF, (0xC0 | encode)); | |||
| 1413 | } | |||
| 1414 | ||||
| 1415 | void Assembler::vaesdeclast(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 1416 | assert(VM_Version::supports_avx512_vaes(), "")do { if (!(VM_Version::supports_avx512_vaes())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 1416, "assert(" "VM_Version::supports_avx512_vaes()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 1417 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 1418 | attributes.set_is_evex_instruction(); | |||
| 1419 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 1420 | emit_int16((unsigned char)0xDF, (0xC0 | encode)); | |||
| 1421 | } | |||
| 1422 | ||||
| 1423 | void Assembler::aesenc(XMMRegister dst, Address src) { | |||
| 1424 | assert(VM_Version::supports_aes(), "")do { if (!(VM_Version::supports_aes())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 1424, "assert(" "VM_Version::supports_aes()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 1425 | InstructionMark im(this); | |||
| 1426 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 1427 | simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 1428 | emit_int8((unsigned char)0xDC); | |||
| 1429 | emit_operand(dst, src); | |||
| 1430 | } | |||
| 1431 | ||||
| 1432 | void Assembler::aesenc(XMMRegister dst, XMMRegister src) { | |||
| 1433 | assert(VM_Version::supports_aes(), "")do { if (!(VM_Version::supports_aes())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 1433, "assert(" "VM_Version::supports_aes()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 1434 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 1435 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 1436 | emit_int16((unsigned char)0xDC, 0xC0 | encode); | |||
| 1437 | } | |||
| 1438 | ||||
| 1439 | void Assembler::vaesenc(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 1440 | assert(VM_Version::supports_avx512_vaes(), "requires vaes support/enabling")do { if (!(VM_Version::supports_avx512_vaes())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 1440, "assert(" "VM_Version::supports_avx512_vaes()" ") failed" , "requires vaes support/enabling"); ::breakpoint(); } } while (0); | |||
| 1441 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 1442 | attributes.set_is_evex_instruction(); | |||
| 1443 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 1444 | emit_int16((unsigned char)0xDC, (0xC0 | encode)); | |||
| 1445 | } | |||
| 1446 | ||||
| 1447 | void Assembler::aesenclast(XMMRegister dst, Address src) { | |||
| 1448 | assert(VM_Version::supports_aes(), "")do { if (!(VM_Version::supports_aes())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 1448, "assert(" "VM_Version::supports_aes()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 1449 | InstructionMark im(this); | |||
| 1450 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 1451 | simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 1452 | emit_int8((unsigned char)0xDD); | |||
| 1453 | emit_operand(dst, src); | |||
| 1454 | } | |||
| 1455 | ||||
| 1456 | void Assembler::aesenclast(XMMRegister dst, XMMRegister src) { | |||
| 1457 | assert(VM_Version::supports_aes(), "")do { if (!(VM_Version::supports_aes())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 1457, "assert(" "VM_Version::supports_aes()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 1458 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 1459 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 1460 | emit_int16((unsigned char)0xDD, (0xC0 | encode)); | |||
| 1461 | } | |||
| 1462 | ||||
| 1463 | void Assembler::vaesenclast(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 1464 | assert(VM_Version::supports_avx512_vaes(), "requires vaes support/enabling")do { if (!(VM_Version::supports_avx512_vaes())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 1464, "assert(" "VM_Version::supports_avx512_vaes()" ") failed" , "requires vaes support/enabling"); ::breakpoint(); } } while (0); | |||
| 1465 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 1466 | attributes.set_is_evex_instruction(); | |||
| 1467 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 1468 | emit_int16((unsigned char)0xDD, (0xC0 | encode)); | |||
| 1469 | } | |||
| 1470 | ||||
| 1471 | void Assembler::andb(Address dst, Register src) { | |||
| 1472 | InstructionMark im(this); | |||
| 1473 | prefix(dst, src, true); | |||
| 1474 | emit_int8(0x20); | |||
| 1475 | emit_operand(src, dst); | |||
| 1476 | } | |||
| 1477 | ||||
| 1478 | void Assembler::andw(Register dst, Register src) { | |||
| 1479 | (void)prefix_and_encode(dst->encoding(), src->encoding()); | |||
| 1480 | emit_arith(0x23, 0xC0, dst, src); | |||
| 1481 | } | |||
| 1482 | ||||
| 1483 | void Assembler::andl(Address dst, int32_t imm32) { | |||
| 1484 | InstructionMark im(this); | |||
| 1485 | prefix(dst); | |||
| 1486 | emit_arith_operand(0x81, as_Register(4), dst, imm32); | |||
| 1487 | } | |||
| 1488 | ||||
| 1489 | void Assembler::andl(Register dst, int32_t imm32) { | |||
| 1490 | prefix(dst); | |||
| 1491 | emit_arith(0x81, 0xE0, dst, imm32); | |||
| 1492 | } | |||
| 1493 | ||||
| 1494 | void Assembler::andl(Address dst, Register src) { | |||
| 1495 | InstructionMark im(this); | |||
| 1496 | prefix(dst, src); | |||
| 1497 | emit_int8(0x21); | |||
| 1498 | emit_operand(src, dst); | |||
| 1499 | } | |||
| 1500 | ||||
| 1501 | void Assembler::andl(Register dst, Address src) { | |||
| 1502 | InstructionMark im(this); | |||
| 1503 | prefix(src, dst); | |||
| 1504 | emit_int8(0x23); | |||
| 1505 | emit_operand(dst, src); | |||
| 1506 | } | |||
| 1507 | ||||
| 1508 | void Assembler::andl(Register dst, Register src) { | |||
| 1509 | (void) prefix_and_encode(dst->encoding(), src->encoding()); | |||
| 1510 | emit_arith(0x23, 0xC0, dst, src); | |||
| 1511 | } | |||
| 1512 | ||||
| 1513 | void Assembler::andnl(Register dst, Register src1, Register src2) { | |||
| 1514 | assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported")do { if (!(VM_Version::supports_bmi1())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 1514, "assert(" "VM_Version::supports_bmi1()" ") failed", "bit manipulation instructions not supported" ); ::breakpoint(); } } while (0); | |||
| 1515 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 1516 | int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); | |||
| 1517 | emit_int16((unsigned char)0xF2, (0xC0 | encode)); | |||
| 1518 | } | |||
| 1519 | ||||
| 1520 | void Assembler::andnl(Register dst, Register src1, Address src2) { | |||
| 1521 | assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported")do { if (!(VM_Version::supports_bmi1())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 1521, "assert(" "VM_Version::supports_bmi1()" ") failed", "bit manipulation instructions not supported" ); ::breakpoint(); } } while (0); | |||
| 1522 | InstructionMark im(this); | |||
| 1523 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 1524 | vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); | |||
| 1525 | emit_int8((unsigned char)0xF2); | |||
| 1526 | emit_operand(dst, src2); | |||
| 1527 | } | |||
| 1528 | ||||
| 1529 | void Assembler::bsfl(Register dst, Register src) { | |||
| 1530 | int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |||
| 1531 | emit_int24(0x0F, | |||
| 1532 | (unsigned char)0xBC, | |||
| 1533 | 0xC0 | encode); | |||
| 1534 | } | |||
| 1535 | ||||
| 1536 | void Assembler::bsrl(Register dst, Register src) { | |||
| 1537 | int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |||
| 1538 | emit_int24(0x0F, | |||
| 1539 | (unsigned char)0xBD, | |||
| 1540 | 0xC0 | encode); | |||
| 1541 | } | |||
| 1542 | ||||
| 1543 | void Assembler::bswapl(Register reg) { // bswap | |||
| 1544 | int encode = prefix_and_encode(reg->encoding()); | |||
| 1545 | emit_int16(0x0F, (0xC8 | encode)); | |||
| 1546 | } | |||
| 1547 | ||||
| 1548 | void Assembler::blsil(Register dst, Register src) { | |||
| 1549 | assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported")do { if (!(VM_Version::supports_bmi1())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 1549, "assert(" "VM_Version::supports_bmi1()" ") failed", "bit manipulation instructions not supported" ); ::breakpoint(); } } while (0); | |||
| 1550 | InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 1551 | int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); | |||
| 1552 | emit_int16((unsigned char)0xF3, (0xC0 | encode)); | |||
| 1553 | } | |||
| 1554 | ||||
| 1555 | void Assembler::blsil(Register dst, Address src) { | |||
| 1556 | assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported")do { if (!(VM_Version::supports_bmi1())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 1556, "assert(" "VM_Version::supports_bmi1()" ") failed", "bit manipulation instructions not supported" ); ::breakpoint(); } } while (0); | |||
| 1557 | InstructionMark im(this); | |||
| 1558 | InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 1559 | vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); | |||
| 1560 | emit_int8((unsigned char)0xF3); | |||
| 1561 | emit_operand(rbx, src); | |||
| 1562 | } | |||
| 1563 | ||||
| 1564 | void Assembler::blsmskl(Register dst, Register src) { | |||
| 1565 | assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported")do { if (!(VM_Version::supports_bmi1())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 1565, "assert(" "VM_Version::supports_bmi1()" ") failed", "bit manipulation instructions not supported" ); ::breakpoint(); } } while (0); | |||
| 1566 | InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 1567 | int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); | |||
| 1568 | emit_int16((unsigned char)0xF3, | |||
| 1569 | 0xC0 | encode); | |||
| 1570 | } | |||
| 1571 | ||||
| 1572 | void Assembler::blsmskl(Register dst, Address src) { | |||
| 1573 | assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported")do { if (!(VM_Version::supports_bmi1())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 1573, "assert(" "VM_Version::supports_bmi1()" ") failed", "bit manipulation instructions not supported" ); ::breakpoint(); } } while (0); | |||
| 1574 | InstructionMark im(this); | |||
| 1575 | InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 1576 | vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); | |||
| 1577 | emit_int8((unsigned char)0xF3); | |||
| 1578 | emit_operand(rdx, src); | |||
| 1579 | } | |||
| 1580 | ||||
| 1581 | void Assembler::blsrl(Register dst, Register src) { | |||
| 1582 | assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported")do { if (!(VM_Version::supports_bmi1())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 1582, "assert(" "VM_Version::supports_bmi1()" ") failed", "bit manipulation instructions not supported" ); ::breakpoint(); } } while (0); | |||
| 1583 | InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 1584 | int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); | |||
| 1585 | emit_int16((unsigned char)0xF3, (0xC0 | encode)); | |||
| 1586 | } | |||
| 1587 | ||||
| 1588 | void Assembler::blsrl(Register dst, Address src) { | |||
| 1589 | assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported")do { if (!(VM_Version::supports_bmi1())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 1589, "assert(" "VM_Version::supports_bmi1()" ") failed", "bit manipulation instructions not supported" ); ::breakpoint(); } } while (0); | |||
| 1590 | InstructionMark im(this); | |||
| 1591 | InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 1592 | vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); | |||
| 1593 | emit_int8((unsigned char)0xF3); | |||
| 1594 | emit_operand(rcx, src); | |||
| 1595 | } | |||
| 1596 | ||||
| 1597 | void Assembler::call(Label& L, relocInfo::relocType rtype) { | |||
| 1598 | // suspect disp32 is always good | |||
| 1599 | int operand = LP64_ONLY(disp32_operand)disp32_operand NOT_LP64(imm_operand); | |||
| 1600 | ||||
| 1601 | if (L.is_bound()) { | |||
| 1602 | const int long_size = 5; | |||
| 1603 | int offs = (int)( target(L) - pc() ); | |||
| 1604 | assert(offs <= 0, "assembler error")do { if (!(offs <= 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 1604, "assert(" "offs <= 0" ") failed", "assembler error" ); ::breakpoint(); } } while (0); | |||
| 1605 | InstructionMark im(this); | |||
| 1606 | // 1110 1000 #32-bit disp | |||
| 1607 | emit_int8((unsigned char)0xE8); | |||
| 1608 | emit_data(offs - long_size, rtype, operand); | |||
| 1609 | } else { | |||
| 1610 | InstructionMark im(this); | |||
| 1611 | // 1110 1000 #32-bit disp | |||
| 1612 | L.add_patch_at(code(), locator()); | |||
| 1613 | ||||
| 1614 | emit_int8((unsigned char)0xE8); | |||
| 1615 | emit_data(int(0), rtype, operand); | |||
| 1616 | } | |||
| 1617 | } | |||
| 1618 | ||||
| 1619 | void Assembler::call(Register dst) { | |||
| 1620 | int encode = prefix_and_encode(dst->encoding()); | |||
| 1621 | emit_int16((unsigned char)0xFF, (0xD0 | encode)); | |||
| 1622 | } | |||
| 1623 | ||||
| 1624 | ||||
| 1625 | void Assembler::call(Address adr) { | |||
| 1626 | InstructionMark im(this); | |||
| 1627 | prefix(adr); | |||
| 1628 | emit_int8((unsigned char)0xFF); | |||
| 1629 | emit_operand(rdx, adr); | |||
| 1630 | } | |||
| 1631 | ||||
| 1632 | void Assembler::call_literal(address entry, RelocationHolder const& rspec) { | |||
| 1633 | InstructionMark im(this); | |||
| 1634 | emit_int8((unsigned char)0xE8); | |||
| 1635 | intptr_t disp = entry - (pc() + sizeof(int32_t)); | |||
| 1636 | // Entry is NULL in case of a scratch emit. | |||
| 1637 | assert(entry == NULL || is_simm32(disp), "disp=" INTPTR_FORMAT " must be 32bit offset (call2)", disp)do { if (!(entry == __null || is_simm32(disp))) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 1637, "assert(" "entry == __null || is_simm32(disp)" ") failed" , "disp=" "0x%016" "l" "x" " must be 32bit offset (call2)", disp ); ::breakpoint(); } } while (0); | |||
| 1638 | // Technically, should use call32_operand, but this format is | |||
| 1639 | // implied by the fact that we're emitting a call instruction. | |||
| 1640 | ||||
| 1641 | int operand = LP64_ONLY(disp32_operand)disp32_operand NOT_LP64(call32_operand); | |||
| 1642 | emit_data((int) disp, rspec, operand); | |||
| 1643 | } | |||
| 1644 | ||||
| 1645 | void Assembler::cdql() { | |||
| 1646 | emit_int8((unsigned char)0x99); | |||
| 1647 | } | |||
| 1648 | ||||
| 1649 | void Assembler::cld() { | |||
| 1650 | emit_int8((unsigned char)0xFC); | |||
| 1651 | } | |||
| 1652 | ||||
| 1653 | void Assembler::cmovl(Condition cc, Register dst, Register src) { | |||
| 1654 | NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction")); | |||
| 1655 | int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |||
| 1656 | emit_int24(0x0F, | |||
| 1657 | 0x40 | cc, | |||
| 1658 | 0xC0 | encode); | |||
| 1659 | } | |||
| 1660 | ||||
| 1661 | ||||
| 1662 | void Assembler::cmovl(Condition cc, Register dst, Address src) { | |||
| 1663 | InstructionMark im(this); | |||
| 1664 | NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction")); | |||
| 1665 | prefix(src, dst); | |||
| 1666 | emit_int16(0x0F, (0x40 | cc)); | |||
| 1667 | emit_operand(dst, src); | |||
| 1668 | } | |||
| 1669 | ||||
| 1670 | void Assembler::cmpb(Address dst, int imm8) { | |||
| 1671 | InstructionMark im(this); | |||
| 1672 | prefix(dst); | |||
| 1673 | emit_int8((unsigned char)0x80); | |||
| 1674 | emit_operand(rdi, dst, 1); | |||
| 1675 | emit_int8(imm8); | |||
| 1676 | } | |||
| 1677 | ||||
| 1678 | void Assembler::cmpl(Address dst, int32_t imm32) { | |||
| 1679 | InstructionMark im(this); | |||
| 1680 | prefix(dst); | |||
| 1681 | emit_int8((unsigned char)0x81); | |||
| 1682 | emit_operand(rdi, dst, 4); | |||
| 1683 | emit_int32(imm32); | |||
| 1684 | } | |||
| 1685 | ||||
| 1686 | void Assembler::cmp(Register dst, int32_t imm32) { | |||
| 1687 | prefix(dst); | |||
| 1688 | emit_int8((unsigned char)0x3D); | |||
| 1689 | emit_int32(imm32); | |||
| 1690 | } | |||
| 1691 | ||||
| 1692 | void Assembler::cmpl(Register dst, int32_t imm32) { | |||
| 1693 | prefix(dst); | |||
| 1694 | emit_arith(0x81, 0xF8, dst, imm32); | |||
| 1695 | } | |||
| 1696 | ||||
| 1697 | void Assembler::cmpl(Register dst, Register src) { | |||
| 1698 | (void) prefix_and_encode(dst->encoding(), src->encoding()); | |||
| 1699 | emit_arith(0x3B, 0xC0, dst, src); | |||
| 1700 | } | |||
| 1701 | ||||
| 1702 | void Assembler::cmpl(Register dst, Address src) { | |||
| 1703 | InstructionMark im(this); | |||
| 1704 | prefix(src, dst); | |||
| 1705 | emit_int8(0x3B); | |||
| 1706 | emit_operand(dst, src); | |||
| 1707 | } | |||
| 1708 | ||||
| 1709 | void Assembler::cmpw(Address dst, int imm16) { | |||
| 1710 | InstructionMark im(this); | |||
| 1711 | assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers")do { if (!(!dst.base_needs_rex() && !dst.index_needs_rex ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 1711, "assert(" "!dst.base_needs_rex() && !dst.index_needs_rex()" ") failed", "no extended registers"); ::breakpoint(); } } while (0); | |||
| 1712 | emit_int16(0x66, (unsigned char)0x81); | |||
| 1713 | emit_operand(rdi, dst, 2); | |||
| 1714 | emit_int16(imm16); | |||
| 1715 | } | |||
| 1716 | ||||
| 1717 | // The 32-bit cmpxchg compares the value at adr with the contents of rax, | |||
| 1718 | // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,. | |||
| 1719 | // The ZF is set if the compared values were equal, and cleared otherwise. | |||
| 1720 | void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg | |||
| 1721 | InstructionMark im(this); | |||
| 1722 | prefix(adr, reg); | |||
| 1723 | emit_int16(0x0F, (unsigned char)0xB1); | |||
| 1724 | emit_operand(reg, adr); | |||
| 1725 | } | |||
| 1726 | ||||
| 1727 | void Assembler::cmpxchgw(Register reg, Address adr) { // cmpxchg | |||
| 1728 | InstructionMark im(this); | |||
| 1729 | size_prefix(); | |||
| 1730 | prefix(adr, reg); | |||
| 1731 | emit_int16(0x0F, (unsigned char)0xB1); | |||
| 1732 | emit_operand(reg, adr); | |||
| 1733 | } | |||
| 1734 | ||||
| 1735 | // The 8-bit cmpxchg compares the value at adr with the contents of rax, | |||
| 1736 | // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,. | |||
| 1737 | // The ZF is set if the compared values were equal, and cleared otherwise. | |||
| 1738 | void Assembler::cmpxchgb(Register reg, Address adr) { // cmpxchg | |||
| 1739 | InstructionMark im(this); | |||
| 1740 | prefix(adr, reg, true); | |||
| 1741 | emit_int16(0x0F, (unsigned char)0xB0); | |||
| 1742 | emit_operand(reg, adr); | |||
| 1743 | } | |||
| 1744 | ||||
| 1745 | void Assembler::comisd(XMMRegister dst, Address src) { | |||
| 1746 | // NOTE: dbx seems to decode this as comiss even though the | |||
| 1747 | // 0x66 is there. Strangly ucomisd comes out correct | |||
| 1748 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 1749 | InstructionMark im(this); | |||
| 1750 | InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);; | |||
| 1751 | attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); | |||
| 1752 | attributes.set_rex_vex_w_reverted(); | |||
| 1753 | simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 1754 | emit_int8(0x2F); | |||
| 1755 | emit_operand(dst, src); | |||
| 1756 | } | |||
| 1757 | ||||
| 1758 | void Assembler::comisd(XMMRegister dst, XMMRegister src) { | |||
| 1759 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 1760 | InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 1761 | attributes.set_rex_vex_w_reverted(); | |||
| 1762 | int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 1763 | emit_int16(0x2F, (0xC0 | encode)); | |||
| 1764 | } | |||
| 1765 | ||||
| 1766 | void Assembler::comiss(XMMRegister dst, Address src) { | |||
| 1767 | NOT_LP64(assert(VM_Version::supports_sse(), "")); | |||
| 1768 | InstructionMark im(this); | |||
| 1769 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 1770 | attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); | |||
| 1771 | simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 1772 | emit_int8(0x2F); | |||
| 1773 | emit_operand(dst, src); | |||
| 1774 | } | |||
| 1775 | ||||
| 1776 | void Assembler::comiss(XMMRegister dst, XMMRegister src) { | |||
| 1777 | NOT_LP64(assert(VM_Version::supports_sse(), "")); | |||
| 1778 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 1779 | int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 1780 | emit_int16(0x2F, (0xC0 | encode)); | |||
| 1781 | } | |||
| 1782 | ||||
| 1783 | void Assembler::cpuid() { | |||
| 1784 | emit_int16(0x0F, (unsigned char)0xA2); | |||
| 1785 | } | |||
| 1786 | ||||
| 1787 | // Opcode / Instruction Op / En 64 - Bit Mode Compat / Leg Mode Description Implemented | |||
| 1788 | // F2 0F 38 F0 / r CRC32 r32, r / m8 RM Valid Valid Accumulate CRC32 on r / m8. v | |||
| 1789 | // F2 REX 0F 38 F0 / r CRC32 r32, r / m8* RM Valid N.E. Accumulate CRC32 on r / m8. - | |||
| 1790 | // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E. Accumulate CRC32 on r / m8. - | |||
| 1791 | // | |||
| 1792 | // F2 0F 38 F1 / r CRC32 r32, r / m16 RM Valid Valid Accumulate CRC32 on r / m16. v | |||
| 1793 | // | |||
| 1794 | // F2 0F 38 F1 / r CRC32 r32, r / m32 RM Valid Valid Accumulate CRC32 on r / m32. v | |||
| 1795 | // | |||
| 1796 | // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E. Accumulate CRC32 on r / m64. v | |||
| 1797 | void Assembler::crc32(Register crc, Register v, int8_t sizeInBytes) { | |||
| 1798 | assert(VM_Version::supports_sse4_2(), "")do { if (!(VM_Version::supports_sse4_2())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 1798, "assert(" "VM_Version::supports_sse4_2()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 1799 | int8_t w = 0x01; | |||
| 1800 | Prefix p = Prefix_EMPTY; | |||
| 1801 | ||||
| 1802 | emit_int8((unsigned char)0xF2); | |||
| 1803 | switch (sizeInBytes) { | |||
| 1804 | case 1: | |||
| 1805 | w = 0; | |||
| 1806 | break; | |||
| 1807 | case 2: | |||
| 1808 | case 4: | |||
| 1809 | break; | |||
| 1810 | LP64_ONLY(case 8:)case 8: | |||
| 1811 | // This instruction is not valid in 32 bits | |||
| 1812 | // Note: | |||
| 1813 | // http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf | |||
| 1814 | // | |||
| 1815 | // Page B - 72 Vol. 2C says | |||
| 1816 | // qwreg2 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : 11 qwreg1 qwreg2 | |||
| 1817 | // mem64 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : mod qwreg r / m | |||
| 1818 | // F0!!! | |||
| 1819 | // while 3 - 208 Vol. 2A | |||
| 1820 | // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E.Accumulate CRC32 on r / m64. | |||
| 1821 | // | |||
| 1822 | // the 0 on a last bit is reserved for a different flavor of this instruction : | |||
| 1823 | // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E.Accumulate CRC32 on r / m8. | |||
| 1824 | p = REX_W; | |||
| 1825 | break; | |||
| 1826 | default: | |||
| 1827 | assert(0, "Unsupported value for a sizeInBytes argument")do { if (!(0)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 1827, "assert(" "0" ") failed", "Unsupported value for a sizeInBytes argument" ); ::breakpoint(); } } while (0); | |||
| 1828 | break; | |||
| 1829 | } | |||
| 1830 | LP64_ONLY(prefix(crc, v, p);)prefix(crc, v, p); | |||
| 1831 | emit_int32(0x0F, | |||
| 1832 | 0x38, | |||
| 1833 | 0xF0 | w, | |||
| 1834 | 0xC0 | ((crc->encoding() & 0x7) << 3) | (v->encoding() & 7)); | |||
| 1835 | } | |||
| 1836 | ||||
| 1837 | void Assembler::crc32(Register crc, Address adr, int8_t sizeInBytes) { | |||
| 1838 | assert(VM_Version::supports_sse4_2(), "")do { if (!(VM_Version::supports_sse4_2())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 1838, "assert(" "VM_Version::supports_sse4_2()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 1839 | InstructionMark im(this); | |||
| 1840 | int8_t w = 0x01; | |||
| 1841 | Prefix p = Prefix_EMPTY; | |||
| 1842 | ||||
| 1843 | emit_int8((int8_t)0xF2); | |||
| 1844 | switch (sizeInBytes) { | |||
| 1845 | case 1: | |||
| 1846 | w = 0; | |||
| 1847 | break; | |||
| 1848 | case 2: | |||
| 1849 | case 4: | |||
| 1850 | break; | |||
| 1851 | LP64_ONLY(case 8:)case 8: | |||
| 1852 | // This instruction is not valid in 32 bits | |||
| 1853 | p = REX_W; | |||
| 1854 | break; | |||
| 1855 | default: | |||
| 1856 | assert(0, "Unsupported value for a sizeInBytes argument")do { if (!(0)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 1856, "assert(" "0" ") failed", "Unsupported value for a sizeInBytes argument" ); ::breakpoint(); } } while (0); | |||
| 1857 | break; | |||
| 1858 | } | |||
| 1859 | LP64_ONLY(prefix(crc, adr, p);)prefix(crc, adr, p); | |||
| 1860 | emit_int24(0x0F, 0x38, (0xF0 | w)); | |||
| 1861 | emit_operand(crc, adr); | |||
| 1862 | } | |||
| 1863 | ||||
| 1864 | void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) { | |||
| 1865 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 1866 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 1867 | int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); | |||
| 1868 | emit_int16((unsigned char)0xE6, (0xC0 | encode)); | |||
| 1869 | } | |||
| 1870 | ||||
| 1871 | void Assembler::vcvtdq2pd(XMMRegister dst, XMMRegister src, int vector_len) { | |||
| 1872 | assert(vector_len <= AVX_256bit ? VM_Version::supports_avx() : VM_Version::supports_evex(), "")do { if (!(vector_len <= AVX_256bit ? VM_Version::supports_avx () : VM_Version::supports_evex())) { (*g_assert_poison) = 'X' ;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 1872, "assert(" "vector_len <= AVX_256bit ? VM_Version::supports_avx() : VM_Version::supports_evex()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 1873 | InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 1874 | int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); | |||
| 1875 | emit_int16((unsigned char)0xE6, (0xC0 | encode)); | |||
| 1876 | } | |||
| 1877 | ||||
| 1878 | void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) { | |||
| 1879 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 1880 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 1881 | int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 1882 | emit_int16(0x5B, (0xC0 | encode)); | |||
| 1883 | } | |||
| 1884 | ||||
| 1885 | void Assembler::vcvtdq2ps(XMMRegister dst, XMMRegister src, int vector_len) { | |||
| 1886 | assert(vector_len <= AVX_256bit ? VM_Version::supports_avx() : VM_Version::supports_evex(), "")do { if (!(vector_len <= AVX_256bit ? VM_Version::supports_avx () : VM_Version::supports_evex())) { (*g_assert_poison) = 'X' ;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 1886, "assert(" "vector_len <= AVX_256bit ? VM_Version::supports_avx() : VM_Version::supports_evex()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 1887 | InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 1888 | int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 1889 | emit_int16(0x5B, (0xC0 | encode)); | |||
| 1890 | } | |||
| 1891 | ||||
| 1892 | void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) { | |||
| 1893 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 1894 | InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 1895 | attributes.set_rex_vex_w_reverted(); | |||
| 1896 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); | |||
| 1897 | emit_int16(0x5A, (0xC0 | encode)); | |||
| 1898 | } | |||
| 1899 | ||||
| 1900 | void Assembler::cvtsd2ss(XMMRegister dst, Address src) { | |||
| 1901 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 1902 | InstructionMark im(this); | |||
| 1903 | InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 1904 | attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); | |||
| 1905 | attributes.set_rex_vex_w_reverted(); | |||
| 1906 | simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); | |||
| 1907 | emit_int8(0x5A); | |||
| 1908 | emit_operand(dst, src); | |||
| 1909 | } | |||
| 1910 | ||||
| 1911 | void Assembler::cvtsi2sdl(XMMRegister dst, Register src) { | |||
| 1912 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 1913 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 1914 | int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); | |||
| 1915 | emit_int16(0x2A, (0xC0 | encode)); | |||
| 1916 | } | |||
| 1917 | ||||
| 1918 | void Assembler::cvtsi2sdl(XMMRegister dst, Address src) { | |||
| 1919 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 1920 | InstructionMark im(this); | |||
| 1921 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 1922 | attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); | |||
| 1923 | simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); | |||
| 1924 | emit_int8(0x2A); | |||
| 1925 | emit_operand(dst, src); | |||
| 1926 | } | |||
| 1927 | ||||
| 1928 | void Assembler::cvtsi2ssl(XMMRegister dst, Register src) { | |||
| 1929 | NOT_LP64(assert(VM_Version::supports_sse(), "")); | |||
| 1930 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 1931 | int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); | |||
| 1932 | emit_int16(0x2A, (0xC0 | encode)); | |||
| 1933 | } | |||
| 1934 | ||||
| 1935 | void Assembler::cvtsi2ssl(XMMRegister dst, Address src) { | |||
| 1936 | NOT_LP64(assert(VM_Version::supports_sse(), "")); | |||
| 1937 | InstructionMark im(this); | |||
| 1938 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 1939 | attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); | |||
| 1940 | simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); | |||
| 1941 | emit_int8(0x2A); | |||
| 1942 | emit_operand(dst, src); | |||
| 1943 | } | |||
| 1944 | ||||
| 1945 | void Assembler::cvtsi2ssq(XMMRegister dst, Register src) { | |||
| 1946 | NOT_LP64(assert(VM_Version::supports_sse(), "")); | |||
| 1947 | InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 1948 | int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); | |||
| 1949 | emit_int16(0x2A, (0xC0 | encode)); | |||
| 1950 | } | |||
| 1951 | ||||
| 1952 | void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) { | |||
| 1953 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 1954 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 1955 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); | |||
| 1956 | emit_int16(0x5A, (0xC0 | encode)); | |||
| 1957 | } | |||
| 1958 | ||||
| 1959 | void Assembler::cvtss2sd(XMMRegister dst, Address src) { | |||
| 1960 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 1961 | InstructionMark im(this); | |||
| 1962 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 1963 | attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); | |||
| 1964 | simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); | |||
| 1965 | emit_int8(0x5A); | |||
| 1966 | emit_operand(dst, src); | |||
| 1967 | } | |||
| 1968 | ||||
| 1969 | ||||
| 1970 | void Assembler::cvttsd2sil(Register dst, XMMRegister src) { | |||
| 1971 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 1972 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 1973 | int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); | |||
| 1974 | emit_int16(0x2C, (0xC0 | encode)); | |||
| 1975 | } | |||
| 1976 | ||||
| 1977 | void Assembler::cvttss2sil(Register dst, XMMRegister src) { | |||
| 1978 | NOT_LP64(assert(VM_Version::supports_sse(), "")); | |||
| 1979 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 1980 | int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); | |||
| 1981 | emit_int16(0x2C, (0xC0 | encode)); | |||
| 1982 | } | |||
| 1983 | ||||
| 1984 | void Assembler::cvttpd2dq(XMMRegister dst, XMMRegister src) { | |||
| 1985 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 1986 | int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit; | |||
| 1987 | InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 1988 | int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 1989 | emit_int16((unsigned char)0xE6, (0xC0 | encode)); | |||
| 1990 | } | |||
| 1991 | ||||
| 1992 | void Assembler::pabsb(XMMRegister dst, XMMRegister src) { | |||
| 1993 | assert(VM_Version::supports_ssse3(), "")do { if (!(VM_Version::supports_ssse3())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 1993, "assert(" "VM_Version::supports_ssse3()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 1994 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 1995 | int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 1996 | emit_int16(0x1C, (0xC0 | encode)); | |||
| 1997 | } | |||
| 1998 | ||||
| 1999 | void Assembler::pabsw(XMMRegister dst, XMMRegister src) { | |||
| 2000 | assert(VM_Version::supports_ssse3(), "")do { if (!(VM_Version::supports_ssse3())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2000, "assert(" "VM_Version::supports_ssse3()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 2001 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 2002 | int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 2003 | emit_int16(0x1D, (0xC0 | encode)); | |||
| 2004 | } | |||
| 2005 | ||||
| 2006 | void Assembler::pabsd(XMMRegister dst, XMMRegister src) { | |||
| 2007 | assert(VM_Version::supports_ssse3(), "")do { if (!(VM_Version::supports_ssse3())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2007, "assert(" "VM_Version::supports_ssse3()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 2008 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 2009 | int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 2010 | emit_int16(0x1E, (0xC0 | encode)); | |||
| 2011 | } | |||
| 2012 | ||||
| 2013 | void Assembler::vpabsb(XMMRegister dst, XMMRegister src, int vector_len) { | |||
| 2014 | assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :do { if (!(vector_len == AVX_128bit ? VM_Version::supports_avx () : vector_len == AVX_256bit ? VM_Version::supports_avx2() : vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : false)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2016, "assert(" "vector_len == AVX_128bit ? VM_Version::supports_avx() : vector_len == AVX_256bit ? VM_Version::supports_avx2() : vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : false" ") failed", "not supported"); ::breakpoint(); } } while (0) | |||
| 2015 | vector_len == AVX_256bit ? VM_Version::supports_avx2() :do { if (!(vector_len == AVX_128bit ? VM_Version::supports_avx () : vector_len == AVX_256bit ? VM_Version::supports_avx2() : vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : false)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2016, "assert(" "vector_len == AVX_128bit ? VM_Version::supports_avx() : vector_len == AVX_256bit ? VM_Version::supports_avx2() : vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : false" ") failed", "not supported"); ::breakpoint(); } } while (0) | |||
| 2016 | vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : false, "not supported")do { if (!(vector_len == AVX_128bit ? VM_Version::supports_avx () : vector_len == AVX_256bit ? VM_Version::supports_avx2() : vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : false)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2016, "assert(" "vector_len == AVX_128bit ? VM_Version::supports_avx() : vector_len == AVX_256bit ? VM_Version::supports_avx2() : vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : false" ") failed", "not supported"); ::breakpoint(); } } while (0); | |||
| 2017 | InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 2018 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 2019 | emit_int16(0x1C, (0xC0 | encode)); | |||
| 2020 | } | |||
| 2021 | ||||
| 2022 | void Assembler::vpabsw(XMMRegister dst, XMMRegister src, int vector_len) { | |||
| 2023 | assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :do { if (!(vector_len == AVX_128bit ? VM_Version::supports_avx () : vector_len == AVX_256bit ? VM_Version::supports_avx2() : vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : false)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2025, "assert(" "vector_len == AVX_128bit ? VM_Version::supports_avx() : vector_len == AVX_256bit ? VM_Version::supports_avx2() : vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : false" ") failed", ""); ::breakpoint(); } } while (0) | |||
| 2024 | vector_len == AVX_256bit ? VM_Version::supports_avx2() :do { if (!(vector_len == AVX_128bit ? VM_Version::supports_avx () : vector_len == AVX_256bit ? VM_Version::supports_avx2() : vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : false)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2025, "assert(" "vector_len == AVX_128bit ? VM_Version::supports_avx() : vector_len == AVX_256bit ? VM_Version::supports_avx2() : vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : false" ") failed", ""); ::breakpoint(); } } while (0) | |||
| 2025 | vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : false, "")do { if (!(vector_len == AVX_128bit ? VM_Version::supports_avx () : vector_len == AVX_256bit ? VM_Version::supports_avx2() : vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : false)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2025, "assert(" "vector_len == AVX_128bit ? VM_Version::supports_avx() : vector_len == AVX_256bit ? VM_Version::supports_avx2() : vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : false" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 2026 | InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 2027 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 2028 | emit_int16(0x1D, (0xC0 | encode)); | |||
| 2029 | } | |||
| 2030 | ||||
| 2031 | void Assembler::vpabsd(XMMRegister dst, XMMRegister src, int vector_len) { | |||
| 2032 | assert(vector_len == AVX_128bit? VM_Version::supports_avx() :do { if (!(vector_len == AVX_128bit? VM_Version::supports_avx () : vector_len == AVX_256bit? VM_Version::supports_avx2() : vector_len == AVX_512bit? VM_Version::supports_evex() : 0)) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2034, "assert(" "vector_len == AVX_128bit? VM_Version::supports_avx() : vector_len == AVX_256bit? VM_Version::supports_avx2() : vector_len == AVX_512bit? VM_Version::supports_evex() : 0" ") failed", ""); ::breakpoint(); } } while (0) | |||
| 2033 | vector_len == AVX_256bit? VM_Version::supports_avx2() :do { if (!(vector_len == AVX_128bit? VM_Version::supports_avx () : vector_len == AVX_256bit? VM_Version::supports_avx2() : vector_len == AVX_512bit? VM_Version::supports_evex() : 0)) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2034, "assert(" "vector_len == AVX_128bit? VM_Version::supports_avx() : vector_len == AVX_256bit? VM_Version::supports_avx2() : vector_len == AVX_512bit? VM_Version::supports_evex() : 0" ") failed", ""); ::breakpoint(); } } while (0) | |||
| 2034 | vector_len == AVX_512bit? VM_Version::supports_evex() : 0, "")do { if (!(vector_len == AVX_128bit? VM_Version::supports_avx () : vector_len == AVX_256bit? VM_Version::supports_avx2() : vector_len == AVX_512bit? VM_Version::supports_evex() : 0)) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2034, "assert(" "vector_len == AVX_128bit? VM_Version::supports_avx() : vector_len == AVX_256bit? VM_Version::supports_avx2() : vector_len == AVX_512bit? VM_Version::supports_evex() : 0" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 2035 | InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 2036 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 2037 | emit_int16(0x1E, (0xC0 | encode)); | |||
| 2038 | } | |||
| 2039 | ||||
| 2040 | void Assembler::evpabsq(XMMRegister dst, XMMRegister src, int vector_len) { | |||
| 2041 | assert(UseAVX > 2, "")do { if (!(UseAVX > 2)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2041, "assert(" "UseAVX > 2" ") failed", ""); ::breakpoint (); } } while (0); | |||
| 2042 | InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 2043 | attributes.set_is_evex_instruction(); | |||
| 2044 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 2045 | emit_int16(0x1F, (0xC0 | encode)); | |||
| 2046 | } | |||
| 2047 | ||||
| 2048 | void Assembler::vcvtps2pd(XMMRegister dst, XMMRegister src, int vector_len) { | |||
| 2049 | assert(vector_len <= AVX_256bit ? VM_Version::supports_avx() : VM_Version::supports_evex(), "")do { if (!(vector_len <= AVX_256bit ? VM_Version::supports_avx () : VM_Version::supports_evex())) { (*g_assert_poison) = 'X' ;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2049, "assert(" "vector_len <= AVX_256bit ? VM_Version::supports_avx() : VM_Version::supports_evex()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 2050 | InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 2051 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 2052 | emit_int16(0x5A, (0xC0 | encode)); | |||
| 2053 | } | |||
| 2054 | ||||
| 2055 | void Assembler::vcvtpd2ps(XMMRegister dst, XMMRegister src, int vector_len) { | |||
| 2056 | assert(vector_len <= AVX_256bit ? VM_Version::supports_avx() : VM_Version::supports_evex(), "")do { if (!(vector_len <= AVX_256bit ? VM_Version::supports_avx () : VM_Version::supports_evex())) { (*g_assert_poison) = 'X' ;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2056, "assert(" "vector_len <= AVX_256bit ? VM_Version::supports_avx() : VM_Version::supports_evex()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 2057 | InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 2058 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 2059 | attributes.set_rex_vex_w_reverted(); | |||
| 2060 | emit_int16(0x5A, (0xC0 | encode)); | |||
| 2061 | } | |||
| 2062 | ||||
| 2063 | void Assembler::vcvttps2dq(XMMRegister dst, XMMRegister src, int vector_len) { | |||
| 2064 | assert(vector_len <= AVX_256bit ? VM_Version::supports_avx() : VM_Version::supports_evex(), "")do { if (!(vector_len <= AVX_256bit ? VM_Version::supports_avx () : VM_Version::supports_evex())) { (*g_assert_poison) = 'X' ;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2064, "assert(" "vector_len <= AVX_256bit ? VM_Version::supports_avx() : VM_Version::supports_evex()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 2065 | InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 2066 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); | |||
| 2067 | emit_int16(0x5B, (0xC0 | encode)); | |||
| 2068 | } | |||
| 2069 | ||||
| 2070 | void Assembler::evcvtqq2ps(XMMRegister dst, XMMRegister src, int vector_len) { | |||
| 2071 | assert(UseAVX > 2 && VM_Version::supports_avx512dq(), "")do { if (!(UseAVX > 2 && VM_Version::supports_avx512dq ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2071, "assert(" "UseAVX > 2 && VM_Version::supports_avx512dq()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 2072 | InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 2073 | attributes.set_is_evex_instruction(); | |||
| 2074 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 2075 | emit_int16(0x5B, (0xC0 | encode)); | |||
| 2076 | } | |||
| 2077 | ||||
| 2078 | void Assembler::evcvttpd2qq(XMMRegister dst, XMMRegister src, int vector_len) { | |||
| 2079 | assert(UseAVX > 2 && VM_Version::supports_avx512dq(), "")do { if (!(UseAVX > 2 && VM_Version::supports_avx512dq ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2079, "assert(" "UseAVX > 2 && VM_Version::supports_avx512dq()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 2080 | InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 2081 | attributes.set_is_evex_instruction(); | |||
| 2082 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 2083 | emit_int16(0x7A, (0xC0 | encode)); | |||
| 2084 | } | |||
| 2085 | ||||
| 2086 | void Assembler::evcvtqq2pd(XMMRegister dst, XMMRegister src, int vector_len) { | |||
| 2087 | assert(UseAVX > 2 && VM_Version::supports_avx512dq(), "")do { if (!(UseAVX > 2 && VM_Version::supports_avx512dq ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2087, "assert(" "UseAVX > 2 && VM_Version::supports_avx512dq()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 2088 | InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 2089 | attributes.set_is_evex_instruction(); | |||
| 2090 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); | |||
| 2091 | emit_int16((unsigned char)0xE6, (0xC0 | encode)); | |||
| 2092 | } | |||
| 2093 | ||||
| 2094 | void Assembler::evpmovwb(XMMRegister dst, XMMRegister src, int vector_len) { | |||
| 2095 | assert(UseAVX > 2 && VM_Version::supports_avx512bw(), "")do { if (!(UseAVX > 2 && VM_Version::supports_avx512bw ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2095, "assert(" "UseAVX > 2 && VM_Version::supports_avx512bw()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 2096 | InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 2097 | attributes.set_is_evex_instruction(); | |||
| 2098 | int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes); | |||
| 2099 | emit_int16(0x30, (0xC0 | encode)); | |||
| 2100 | } | |||
| 2101 | ||||
| 2102 | void Assembler::evpmovdw(XMMRegister dst, XMMRegister src, int vector_len) { | |||
| 2103 | assert(UseAVX > 2, "")do { if (!(UseAVX > 2)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2103, "assert(" "UseAVX > 2" ") failed", ""); ::breakpoint (); } } while (0); | |||
| 2104 | InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 2105 | attributes.set_is_evex_instruction(); | |||
| 2106 | int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes); | |||
| 2107 | emit_int16(0x33, (0xC0 | encode)); | |||
| 2108 | } | |||
| 2109 | ||||
| 2110 | void Assembler::evpmovdb(XMMRegister dst, XMMRegister src, int vector_len) { | |||
| 2111 | assert(UseAVX > 2, "")do { if (!(UseAVX > 2)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2111, "assert(" "UseAVX > 2" ") failed", ""); ::breakpoint (); } } while (0); | |||
| 2112 | InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 2113 | attributes.set_is_evex_instruction(); | |||
| 2114 | int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes); | |||
| 2115 | emit_int16(0x31, (0xC0 | encode)); | |||
| 2116 | } | |||
| 2117 | ||||
| 2118 | void Assembler::evpmovqd(XMMRegister dst, XMMRegister src, int vector_len) { | |||
| 2119 | assert(UseAVX > 2, "")do { if (!(UseAVX > 2)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2119, "assert(" "UseAVX > 2" ") failed", ""); ::breakpoint (); } } while (0); | |||
| 2120 | InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 2121 | attributes.set_is_evex_instruction(); | |||
| 2122 | int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes); | |||
| 2123 | emit_int16(0x35, (0xC0 | encode)); | |||
| 2124 | } | |||
| 2125 | ||||
| 2126 | void Assembler::evpmovqb(XMMRegister dst, XMMRegister src, int vector_len) { | |||
| 2127 | assert(UseAVX > 2, "")do { if (!(UseAVX > 2)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2127, "assert(" "UseAVX > 2" ") failed", ""); ::breakpoint (); } } while (0); | |||
| 2128 | InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 2129 | attributes.set_is_evex_instruction(); | |||
| 2130 | int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes); | |||
| 2131 | emit_int16(0x32, (0xC0 | encode)); | |||
| 2132 | } | |||
| 2133 | ||||
| 2134 | void Assembler::evpmovqw(XMMRegister dst, XMMRegister src, int vector_len) { | |||
| 2135 | assert(UseAVX > 2, "")do { if (!(UseAVX > 2)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2135, "assert(" "UseAVX > 2" ") failed", ""); ::breakpoint (); } } while (0); | |||
| 2136 | InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 2137 | attributes.set_is_evex_instruction(); | |||
| 2138 | int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes); | |||
| 2139 | emit_int16(0x34, (0xC0 | encode)); | |||
| 2140 | } | |||
| 2141 | ||||
| 2142 | void Assembler::decl(Address dst) { | |||
| 2143 | // Don't use it directly. Use MacroAssembler::decrement() instead. | |||
| 2144 | InstructionMark im(this); | |||
| 2145 | prefix(dst); | |||
| 2146 | emit_int8((unsigned char)0xFF); | |||
| 2147 | emit_operand(rcx, dst); | |||
| 2148 | } | |||
| 2149 | ||||
| 2150 | void Assembler::divsd(XMMRegister dst, Address src) { | |||
| 2151 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 2152 | InstructionMark im(this); | |||
| 2153 | InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 2154 | attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); | |||
| 2155 | attributes.set_rex_vex_w_reverted(); | |||
| 2156 | simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); | |||
| 2157 | emit_int8(0x5E); | |||
| 2158 | emit_operand(dst, src); | |||
| 2159 | } | |||
| 2160 | ||||
| 2161 | void Assembler::divsd(XMMRegister dst, XMMRegister src) { | |||
| 2162 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 2163 | InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 2164 | attributes.set_rex_vex_w_reverted(); | |||
| 2165 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); | |||
| 2166 | emit_int16(0x5E, (0xC0 | encode)); | |||
| 2167 | } | |||
| 2168 | ||||
| 2169 | void Assembler::divss(XMMRegister dst, Address src) { | |||
| 2170 | NOT_LP64(assert(VM_Version::supports_sse(), "")); | |||
| 2171 | InstructionMark im(this); | |||
| 2172 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 2173 | attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); | |||
| 2174 | simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); | |||
| 2175 | emit_int8(0x5E); | |||
| 2176 | emit_operand(dst, src); | |||
| 2177 | } | |||
| 2178 | ||||
| 2179 | void Assembler::divss(XMMRegister dst, XMMRegister src) { | |||
| 2180 | NOT_LP64(assert(VM_Version::supports_sse(), "")); | |||
| 2181 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 2182 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); | |||
| 2183 | emit_int16(0x5E, (0xC0 | encode)); | |||
| 2184 | } | |||
| 2185 | ||||
| 2186 | void Assembler::hlt() { | |||
| 2187 | emit_int8((unsigned char)0xF4); | |||
| 2188 | } | |||
| 2189 | ||||
| 2190 | void Assembler::idivl(Register src) { | |||
| 2191 | int encode = prefix_and_encode(src->encoding()); | |||
| 2192 | emit_int16((unsigned char)0xF7, (0xF8 | encode)); | |||
| 2193 | } | |||
| 2194 | ||||
| 2195 | void Assembler::divl(Register src) { // Unsigned | |||
| 2196 | int encode = prefix_and_encode(src->encoding()); | |||
| 2197 | emit_int16((unsigned char)0xF7, (0xF0 | encode)); | |||
| 2198 | } | |||
| 2199 | ||||
| 2200 | void Assembler::imull(Register src) { | |||
| 2201 | int encode = prefix_and_encode(src->encoding()); | |||
| 2202 | emit_int16((unsigned char)0xF7, (0xE8 | encode)); | |||
| 2203 | } | |||
| 2204 | ||||
| 2205 | void Assembler::imull(Register dst, Register src) { | |||
| 2206 | int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |||
| 2207 | emit_int24(0x0F, | |||
| 2208 | (unsigned char)0xAF, | |||
| 2209 | (0xC0 | encode)); | |||
| 2210 | } | |||
| 2211 | ||||
| 2212 | void Assembler::imull(Register dst, Address src, int32_t value) { | |||
| 2213 | InstructionMark im(this); | |||
| 2214 | prefix(src, dst); | |||
| 2215 | if (is8bit(value)) { | |||
| 2216 | emit_int8((unsigned char)0x6B); | |||
| 2217 | emit_operand(dst, src); | |||
| 2218 | emit_int8(value); | |||
| 2219 | } else { | |||
| 2220 | emit_int8((unsigned char)0x69); | |||
| 2221 | emit_operand(dst, src); | |||
| 2222 | emit_int32(value); | |||
| 2223 | } | |||
| 2224 | } | |||
| 2225 | ||||
| 2226 | void Assembler::imull(Register dst, Register src, int value) { | |||
| 2227 | int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |||
| 2228 | if (is8bit(value)) { | |||
| 2229 | emit_int24(0x6B, (0xC0 | encode), value & 0xFF); | |||
| 2230 | } else { | |||
| 2231 | emit_int16(0x69, (0xC0 | encode)); | |||
| 2232 | emit_int32(value); | |||
| 2233 | } | |||
| 2234 | } | |||
| 2235 | ||||
| 2236 | void Assembler::imull(Register dst, Address src) { | |||
| 2237 | InstructionMark im(this); | |||
| 2238 | prefix(src, dst); | |||
| 2239 | emit_int16(0x0F, (unsigned char)0xAF); | |||
| 2240 | emit_operand(dst, src); | |||
| 2241 | } | |||
| 2242 | ||||
| 2243 | ||||
| 2244 | void Assembler::incl(Address dst) { | |||
| 2245 | // Don't use it directly. Use MacroAssembler::increment() instead. | |||
| 2246 | InstructionMark im(this); | |||
| 2247 | prefix(dst); | |||
| 2248 | emit_int8((unsigned char)0xFF); | |||
| 2249 | emit_operand(rax, dst); | |||
| 2250 | } | |||
| 2251 | ||||
| 2252 | void Assembler::jcc(Condition cc, Label& L, bool maybe_short) { | |||
| 2253 | InstructionMark im(this); | |||
| 2254 | assert((0 <= cc) && (cc < 16), "illegal cc")do { if (!((0 <= cc) && (cc < 16))) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2254, "assert(" "(0 <= cc) && (cc < 16)" ") failed" , "illegal cc"); ::breakpoint(); } } while (0); | |||
| 2255 | if (L.is_bound()) { | |||
| 2256 | address dst = target(L); | |||
| 2257 | assert(dst != NULL, "jcc most probably wrong")do { if (!(dst != __null)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2257, "assert(" "dst != __null" ") failed", "jcc most probably wrong" ); ::breakpoint(); } } while (0); | |||
| 2258 | ||||
| 2259 | const int short_size = 2; | |||
| 2260 | const int long_size = 6; | |||
| 2261 | intptr_t offs = (intptr_t)dst - (intptr_t)pc(); | |||
| 2262 | if (maybe_short && is8bit(offs - short_size)) { | |||
| 2263 | // 0111 tttn #8-bit disp | |||
| 2264 | emit_int16(0x70 | cc, (offs - short_size) & 0xFF); | |||
| 2265 | } else { | |||
| 2266 | // 0000 1111 1000 tttn #32-bit disp | |||
| 2267 | assert(is_simm32(offs - long_size),do { if (!(is_simm32(offs - long_size))) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2268, "assert(" "is_simm32(offs - long_size)" ") failed", "must be 32bit offset (call4)" ); ::breakpoint(); } } while (0) | |||
| 2268 | "must be 32bit offset (call4)")do { if (!(is_simm32(offs - long_size))) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2268, "assert(" "is_simm32(offs - long_size)" ") failed", "must be 32bit offset (call4)" ); ::breakpoint(); } } while (0); | |||
| 2269 | emit_int16(0x0F, (0x80 | cc)); | |||
| 2270 | emit_int32(offs - long_size); | |||
| 2271 | } | |||
| 2272 | } else { | |||
| 2273 | // Note: could eliminate cond. jumps to this jump if condition | |||
| 2274 | // is the same however, seems to be rather unlikely case. | |||
| 2275 | // Note: use jccb() if label to be bound is very close to get | |||
| 2276 | // an 8-bit displacement | |||
| 2277 | L.add_patch_at(code(), locator()); | |||
| 2278 | emit_int16(0x0F, (0x80 | cc)); | |||
| 2279 | emit_int32(0); | |||
| 2280 | } | |||
| 2281 | } | |||
| 2282 | ||||
| 2283 | void Assembler::jccb_0(Condition cc, Label& L, const char* file, int line) { | |||
| 2284 | if (L.is_bound()) { | |||
| 2285 | const int short_size = 2; | |||
| 2286 | address entry = target(L); | |||
| 2287 | #ifdef ASSERT1 | |||
| 2288 | intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size); | |||
| 2289 | intptr_t delta = short_branch_delta(); | |||
| 2290 | if (delta != 0) { | |||
| 2291 | dist += (dist < 0 ? (-delta) :delta); | |||
| 2292 | } | |||
| 2293 | assert(is8bit(dist), "Dispacement too large for a short jmp at %s:%d", file, line)do { if (!(is8bit(dist))) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2293, "assert(" "is8bit(dist)" ") failed", "Dispacement too large for a short jmp at %s:%d" , file, line); ::breakpoint(); } } while (0); | |||
| 2294 | #endif | |||
| 2295 | intptr_t offs = (intptr_t)entry - (intptr_t)pc(); | |||
| 2296 | // 0111 tttn #8-bit disp | |||
| 2297 | emit_int16(0x70 | cc, (offs - short_size) & 0xFF); | |||
| 2298 | } else { | |||
| 2299 | InstructionMark im(this); | |||
| 2300 | L.add_patch_at(code(), locator(), file, line); | |||
| 2301 | emit_int16(0x70 | cc, 0); | |||
| 2302 | } | |||
| 2303 | } | |||
| 2304 | ||||
| 2305 | void Assembler::jmp(Address adr) { | |||
| 2306 | InstructionMark im(this); | |||
| 2307 | prefix(adr); | |||
| 2308 | emit_int8((unsigned char)0xFF); | |||
| 2309 | emit_operand(rsp, adr); | |||
| 2310 | } | |||
| 2311 | ||||
| 2312 | void Assembler::jmp(Label& L, bool maybe_short) { | |||
| 2313 | if (L.is_bound()) { | |||
| 2314 | address entry = target(L); | |||
| 2315 | assert(entry != NULL, "jmp most probably wrong")do { if (!(entry != __null)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2315, "assert(" "entry != __null" ") failed", "jmp most probably wrong" ); ::breakpoint(); } } while (0); | |||
| 2316 | InstructionMark im(this); | |||
| 2317 | const int short_size = 2; | |||
| 2318 | const int long_size = 5; | |||
| 2319 | intptr_t offs = entry - pc(); | |||
| 2320 | if (maybe_short && is8bit(offs - short_size)) { | |||
| 2321 | emit_int16((unsigned char)0xEB, ((offs - short_size) & 0xFF)); | |||
| 2322 | } else { | |||
| 2323 | emit_int8((unsigned char)0xE9); | |||
| 2324 | emit_int32(offs - long_size); | |||
| 2325 | } | |||
| 2326 | } else { | |||
| 2327 | // By default, forward jumps are always 32-bit displacements, since | |||
| 2328 | // we can't yet know where the label will be bound. If you're sure that | |||
| 2329 | // the forward jump will not run beyond 256 bytes, use jmpb to | |||
| 2330 | // force an 8-bit displacement. | |||
| 2331 | InstructionMark im(this); | |||
| 2332 | L.add_patch_at(code(), locator()); | |||
| 2333 | emit_int8((unsigned char)0xE9); | |||
| 2334 | emit_int32(0); | |||
| 2335 | } | |||
| 2336 | } | |||
| 2337 | ||||
| 2338 | void Assembler::jmp(Register entry) { | |||
| 2339 | int encode = prefix_and_encode(entry->encoding()); | |||
| 2340 | emit_int16((unsigned char)0xFF, (0xE0 | encode)); | |||
| 2341 | } | |||
| 2342 | ||||
| 2343 | void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) { | |||
| 2344 | InstructionMark im(this); | |||
| 2345 | emit_int8((unsigned char)0xE9); | |||
| 2346 | assert(dest != NULL, "must have a target")do { if (!(dest != __null)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2346, "assert(" "dest != __null" ") failed", "must have a target" ); ::breakpoint(); } } while (0); | |||
| 2347 | intptr_t disp = dest - (pc() + sizeof(int32_t)); | |||
| 2348 | assert(is_simm32(disp), "must be 32bit offset (jmp)")do { if (!(is_simm32(disp))) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2348, "assert(" "is_simm32(disp)" ") failed", "must be 32bit offset (jmp)" ); ::breakpoint(); } } while (0); | |||
| 2349 | emit_data(disp, rspec.reloc(), call32_operand); | |||
| 2350 | } | |||
| 2351 | ||||
| 2352 | void Assembler::jmpb_0(Label& L, const char* file, int line) { | |||
| 2353 | if (L.is_bound()) { | |||
| 2354 | const int short_size = 2; | |||
| 2355 | address entry = target(L); | |||
| 2356 | assert(entry != NULL, "jmp most probably wrong")do { if (!(entry != __null)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2356, "assert(" "entry != __null" ") failed", "jmp most probably wrong" ); ::breakpoint(); } } while (0); | |||
| 2357 | #ifdef ASSERT1 | |||
| 2358 | intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size); | |||
| 2359 | intptr_t delta = short_branch_delta(); | |||
| 2360 | if (delta != 0) { | |||
| 2361 | dist += (dist < 0 ? (-delta) :delta); | |||
| 2362 | } | |||
| 2363 | assert(is8bit(dist), "Dispacement too large for a short jmp at %s:%d", file, line)do { if (!(is8bit(dist))) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2363, "assert(" "is8bit(dist)" ") failed", "Dispacement too large for a short jmp at %s:%d" , file, line); ::breakpoint(); } } while (0); | |||
| 2364 | #endif | |||
| 2365 | intptr_t offs = entry - pc(); | |||
| 2366 | emit_int16((unsigned char)0xEB, (offs - short_size) & 0xFF); | |||
| 2367 | } else { | |||
| 2368 | InstructionMark im(this); | |||
| 2369 | L.add_patch_at(code(), locator(), file, line); | |||
| 2370 | emit_int16((unsigned char)0xEB, 0); | |||
| 2371 | } | |||
| 2372 | } | |||
| 2373 | ||||
| 2374 | void Assembler::ldmxcsr( Address src) { | |||
| 2375 | if (UseAVX > 0 ) { | |||
| 2376 | InstructionMark im(this); | |||
| 2377 | InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 2378 | vex_prefix(src, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 2379 | emit_int8((unsigned char)0xAE); | |||
| 2380 | emit_operand(as_Register(2), src); | |||
| 2381 | } else { | |||
| 2382 | NOT_LP64(assert(VM_Version::supports_sse(), "")); | |||
| 2383 | InstructionMark im(this); | |||
| 2384 | prefix(src); | |||
| 2385 | emit_int16(0x0F, (unsigned char)0xAE); | |||
| 2386 | emit_operand(as_Register(2), src); | |||
| 2387 | } | |||
| 2388 | } | |||
| 2389 | ||||
| 2390 | void Assembler::leal(Register dst, Address src) { | |||
| 2391 | InstructionMark im(this); | |||
| 2392 | #ifdef _LP641 | |||
| 2393 | emit_int8(0x67); // addr32 | |||
| 2394 | prefix(src, dst); | |||
| 2395 | #endif // LP64 | |||
| 2396 | emit_int8((unsigned char)0x8D); | |||
| 2397 | emit_operand(dst, src); | |||
| 2398 | } | |||
| 2399 | ||||
| 2400 | void Assembler::lfence() { | |||
| 2401 | emit_int24(0x0F, (unsigned char)0xAE, (unsigned char)0xE8); | |||
| 2402 | } | |||
| 2403 | ||||
| 2404 | void Assembler::lock() { | |||
| 2405 | emit_int8((unsigned char)0xF0); | |||
| 2406 | } | |||
| 2407 | ||||
| 2408 | void Assembler::size_prefix() { | |||
| 2409 | emit_int8(0x66); | |||
| 2410 | } | |||
| 2411 | ||||
| 2412 | void Assembler::lzcntl(Register dst, Register src) { | |||
| 2413 | assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR")do { if (!(VM_Version::supports_lzcnt())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2413, "assert(" "VM_Version::supports_lzcnt()" ") failed", "encoding is treated as BSR" ); ::breakpoint(); } } while (0); | |||
| 2414 | emit_int8((unsigned char)0xF3); | |||
| 2415 | int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |||
| 2416 | emit_int24(0x0F, (unsigned char)0xBD, (0xC0 | encode)); | |||
| 2417 | } | |||
| 2418 | ||||
| 2419 | // Emit mfence instruction | |||
| 2420 | void Assembler::mfence() { | |||
| 2421 | NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");) | |||
| 2422 | emit_int24(0x0F, (unsigned char)0xAE, (unsigned char)0xF0); | |||
| 2423 | } | |||
| 2424 | ||||
| 2425 | // Emit sfence instruction | |||
| 2426 | void Assembler::sfence() { | |||
| 2427 | NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");) | |||
| 2428 | emit_int24(0x0F, (unsigned char)0xAE, (unsigned char)0xF8); | |||
| 2429 | } | |||
| 2430 | ||||
| 2431 | void Assembler::mov(Register dst, Register src) { | |||
| 2432 | LP64_ONLY(movq(dst, src))movq(dst, src) NOT_LP64(movl(dst, src)); | |||
| 2433 | } | |||
| 2434 | ||||
| 2435 | void Assembler::movapd(XMMRegister dst, XMMRegister src) { | |||
| 2436 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 2437 | int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit; | |||
| 2438 | InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 2439 | attributes.set_rex_vex_w_reverted(); | |||
| 2440 | int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 2441 | emit_int16(0x28, (0xC0 | encode)); | |||
| 2442 | } | |||
| 2443 | ||||
| 2444 | void Assembler::movaps(XMMRegister dst, XMMRegister src) { | |||
| 2445 | NOT_LP64(assert(VM_Version::supports_sse(), "")); | |||
| 2446 | int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit; | |||
| 2447 | InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 2448 | int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 2449 | emit_int16(0x28, (0xC0 | encode)); | |||
| 2450 | } | |||
| 2451 | ||||
| 2452 | void Assembler::movlhps(XMMRegister dst, XMMRegister src) { | |||
| 2453 | NOT_LP64(assert(VM_Version::supports_sse(), "")); | |||
| 2454 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 2455 | int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 2456 | emit_int16(0x16, (0xC0 | encode)); | |||
| 2457 | } | |||
| 2458 | ||||
| 2459 | void Assembler::movb(Register dst, Address src) { | |||
| 2460 | NOT_LP64(assert(dst->has_byte_register(), "must have byte register")); | |||
| 2461 | InstructionMark im(this); | |||
| 2462 | prefix(src, dst, true); | |||
| 2463 | emit_int8((unsigned char)0x8A); | |||
| 2464 | emit_operand(dst, src); | |||
| 2465 | } | |||
| 2466 | ||||
| 2467 | void Assembler::movddup(XMMRegister dst, XMMRegister src) { | |||
| 2468 | NOT_LP64(assert(VM_Version::supports_sse3(), "")); | |||
| 2469 | int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit; | |||
| 2470 | InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 2471 | attributes.set_rex_vex_w_reverted(); | |||
| 2472 | int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); | |||
| 2473 | emit_int16(0x12, 0xC0 | encode); | |||
| 2474 | } | |||
| 2475 | ||||
| 2476 | void Assembler::kmovbl(KRegister dst, KRegister src) { | |||
| 2477 | assert(VM_Version::supports_avx512dq(), "")do { if (!(VM_Version::supports_avx512dq())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2477, "assert(" "VM_Version::supports_avx512dq()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 2478 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 2479 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 2480 | emit_int16((unsigned char)0x90, (0xC0 | encode)); | |||
| 2481 | } | |||
| 2482 | ||||
| 2483 | void Assembler::kmovbl(KRegister dst, Register src) { | |||
| 2484 | assert(VM_Version::supports_avx512dq(), "")do { if (!(VM_Version::supports_avx512dq())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2484, "assert(" "VM_Version::supports_avx512dq()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 2485 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 2486 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 2487 | emit_int16((unsigned char)0x92, (0xC0 | encode)); | |||
| 2488 | } | |||
| 2489 | ||||
| 2490 | void Assembler::kmovbl(Register dst, KRegister src) { | |||
| 2491 | assert(VM_Version::supports_avx512dq(), "")do { if (!(VM_Version::supports_avx512dq())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2491, "assert(" "VM_Version::supports_avx512dq()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 2492 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 2493 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 2494 | emit_int16((unsigned char)0x93, (0xC0 | encode)); | |||
| 2495 | } | |||
| 2496 | ||||
| 2497 | void Assembler::kmovwl(KRegister dst, Register src) { | |||
| 2498 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2498, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 2499 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 2500 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 2501 | emit_int16((unsigned char)0x92, (0xC0 | encode)); | |||
| 2502 | } | |||
| 2503 | ||||
| 2504 | void Assembler::kmovwl(Register dst, KRegister src) { | |||
| 2505 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2505, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 2506 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 2507 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 2508 | emit_int16((unsigned char)0x93, (0xC0 | encode)); | |||
| 2509 | } | |||
| 2510 | ||||
| 2511 | void Assembler::kmovwl(KRegister dst, Address src) { | |||
| 2512 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2512, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 2513 | InstructionMark im(this); | |||
| 2514 | InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 2515 | vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 2516 | emit_int8((unsigned char)0x90); | |||
| 2517 | emit_operand((Register)dst, src); | |||
| 2518 | } | |||
| 2519 | ||||
| 2520 | void Assembler::kmovwl(Address dst, KRegister src) { | |||
| 2521 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2521, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 2522 | InstructionMark im(this); | |||
| 2523 | InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 2524 | vex_prefix(dst, 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 2525 | emit_int8((unsigned char)0x91); | |||
| 2526 | emit_operand((Register)src, dst); | |||
| 2527 | } | |||
| 2528 | ||||
| 2529 | void Assembler::kmovwl(KRegister dst, KRegister src) { | |||
| 2530 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2530, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 2531 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 2532 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 2533 | emit_int16((unsigned char)0x90, (0xC0 | encode)); | |||
| 2534 | } | |||
| 2535 | ||||
| 2536 | void Assembler::kmovdl(KRegister dst, Register src) { | |||
| 2537 | assert(VM_Version::supports_avx512bw(), "")do { if (!(VM_Version::supports_avx512bw())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2537, "assert(" "VM_Version::supports_avx512bw()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 2538 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 2539 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); | |||
| 2540 | emit_int16((unsigned char)0x92, (0xC0 | encode)); | |||
| 2541 | } | |||
| 2542 | ||||
| 2543 | void Assembler::kmovdl(Register dst, KRegister src) { | |||
| 2544 | assert(VM_Version::supports_avx512bw(), "")do { if (!(VM_Version::supports_avx512bw())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2544, "assert(" "VM_Version::supports_avx512bw()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 2545 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 2546 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); | |||
| 2547 | emit_int16((unsigned char)0x93, (0xC0 | encode)); | |||
| 2548 | } | |||
| 2549 | ||||
| 2550 | void Assembler::kmovql(KRegister dst, KRegister src) { | |||
| 2551 | assert(VM_Version::supports_avx512bw(), "")do { if (!(VM_Version::supports_avx512bw())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2551, "assert(" "VM_Version::supports_avx512bw()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 2552 | InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 2553 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 2554 | emit_int16((unsigned char)0x90, (0xC0 | encode)); | |||
| 2555 | } | |||
| 2556 | ||||
| 2557 | void Assembler::kmovql(KRegister dst, Address src) { | |||
| 2558 | assert(VM_Version::supports_avx512bw(), "")do { if (!(VM_Version::supports_avx512bw())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2558, "assert(" "VM_Version::supports_avx512bw()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 2559 | InstructionMark im(this); | |||
| 2560 | InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 2561 | vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 2562 | emit_int8((unsigned char)0x90); | |||
| 2563 | emit_operand((Register)dst, src); | |||
| 2564 | } | |||
| 2565 | ||||
| 2566 | void Assembler::kmovql(Address dst, KRegister src) { | |||
| 2567 | assert(VM_Version::supports_avx512bw(), "")do { if (!(VM_Version::supports_avx512bw())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2567, "assert(" "VM_Version::supports_avx512bw()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 2568 | InstructionMark im(this); | |||
| 2569 | InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 2570 | vex_prefix(dst, 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 2571 | emit_int8((unsigned char)0x91); | |||
| 2572 | emit_operand((Register)src, dst); | |||
| 2573 | } | |||
| 2574 | ||||
| 2575 | void Assembler::kmovql(KRegister dst, Register src) { | |||
| 2576 | assert(VM_Version::supports_avx512bw(), "")do { if (!(VM_Version::supports_avx512bw())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2576, "assert(" "VM_Version::supports_avx512bw()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 2577 | InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 2578 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); | |||
| 2579 | emit_int16((unsigned char)0x92, (0xC0 | encode)); | |||
| 2580 | } | |||
| 2581 | ||||
| 2582 | void Assembler::kmovql(Register dst, KRegister src) { | |||
| 2583 | assert(VM_Version::supports_avx512bw(), "")do { if (!(VM_Version::supports_avx512bw())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2583, "assert(" "VM_Version::supports_avx512bw()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 2584 | InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 2585 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); | |||
| 2586 | emit_int16((unsigned char)0x93, (0xC0 | encode)); | |||
| 2587 | } | |||
| 2588 | ||||
| 2589 | void Assembler::knotwl(KRegister dst, KRegister src) { | |||
| 2590 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2590, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 2591 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 2592 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 2593 | emit_int16(0x44, (0xC0 | encode)); | |||
| 2594 | } | |||
| 2595 | ||||
| 2596 | void Assembler::knotbl(KRegister dst, KRegister src) { | |||
| 2597 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2597, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 2598 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 2599 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 2600 | emit_int16(0x44, (0xC0 | encode)); | |||
| 2601 | } | |||
| 2602 | ||||
| 2603 | void Assembler::korbl(KRegister dst, KRegister src1, KRegister src2) { | |||
| 2604 | assert(VM_Version::supports_avx512dq(), "")do { if (!(VM_Version::supports_avx512dq())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2604, "assert(" "VM_Version::supports_avx512dq()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 2605 | InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 2606 | int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 2607 | emit_int16(0x45, (0xC0 | encode)); | |||
| 2608 | } | |||
| 2609 | ||||
| 2610 | void Assembler::korwl(KRegister dst, KRegister src1, KRegister src2) { | |||
| 2611 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2611, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 2612 | InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 2613 | int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 2614 | emit_int16(0x45, (0xC0 | encode)); | |||
| 2615 | } | |||
| 2616 | ||||
| 2617 | void Assembler::kordl(KRegister dst, KRegister src1, KRegister src2) { | |||
| 2618 | assert(VM_Version::supports_avx512bw(), "")do { if (!(VM_Version::supports_avx512bw())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2618, "assert(" "VM_Version::supports_avx512bw()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 2619 | InstructionAttr attributes(AVX_256bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 2620 | int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 2621 | emit_int16(0x45, (0xC0 | encode)); | |||
| 2622 | } | |||
| 2623 | ||||
| 2624 | void Assembler::korql(KRegister dst, KRegister src1, KRegister src2) { | |||
| 2625 | assert(VM_Version::supports_avx512bw(), "")do { if (!(VM_Version::supports_avx512bw())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2625, "assert(" "VM_Version::supports_avx512bw()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 2626 | InstructionAttr attributes(AVX_256bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 2627 | int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 2628 | emit_int16(0x45, (0xC0 | encode)); | |||
| 2629 | } | |||
| 2630 | ||||
| 2631 | void Assembler::kxorbl(KRegister dst, KRegister src1, KRegister src2) { | |||
| 2632 | assert(VM_Version::supports_avx512dq(), "")do { if (!(VM_Version::supports_avx512dq())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2632, "assert(" "VM_Version::supports_avx512dq()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 2633 | InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 2634 | int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 2635 | emit_int16(0x47, (0xC0 | encode)); | |||
| 2636 | } | |||
| 2637 | ||||
| 2638 | void Assembler::kxorwl(KRegister dst, KRegister src1, KRegister src2) { | |||
| 2639 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2639, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 2640 | InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 2641 | int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 2642 | emit_int16(0x47, (0xC0 | encode)); | |||
| 2643 | } | |||
| 2644 | ||||
| 2645 | void Assembler::kxordl(KRegister dst, KRegister src1, KRegister src2) { | |||
| 2646 | assert(VM_Version::supports_avx512bw(), "")do { if (!(VM_Version::supports_avx512bw())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2646, "assert(" "VM_Version::supports_avx512bw()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 2647 | InstructionAttr attributes(AVX_256bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 2648 | int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 2649 | emit_int16(0x47, (0xC0 | encode)); | |||
| 2650 | } | |||
| 2651 | ||||
| 2652 | void Assembler::kxorql(KRegister dst, KRegister src1, KRegister src2) { | |||
| 2653 | assert(VM_Version::supports_avx512bw(), "")do { if (!(VM_Version::supports_avx512bw())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2653, "assert(" "VM_Version::supports_avx512bw()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 2654 | InstructionAttr attributes(AVX_256bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 2655 | int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 2656 | emit_int16(0x47, (0xC0 | encode)); | |||
| 2657 | } | |||
| 2658 | ||||
| 2659 | void Assembler::kandbl(KRegister dst, KRegister src1, KRegister src2) { | |||
| 2660 | assert(VM_Version::supports_avx512dq(), "")do { if (!(VM_Version::supports_avx512dq())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2660, "assert(" "VM_Version::supports_avx512dq()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 2661 | InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 2662 | int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 2663 | emit_int16(0x41, (0xC0 | encode)); | |||
| 2664 | } | |||
| 2665 | ||||
| 2666 | void Assembler::kandwl(KRegister dst, KRegister src1, KRegister src2) { | |||
| 2667 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2667, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 2668 | InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 2669 | int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 2670 | emit_int16(0x41, (0xC0 | encode)); | |||
| 2671 | } | |||
| 2672 | ||||
| 2673 | void Assembler::kanddl(KRegister dst, KRegister src1, KRegister src2) { | |||
| 2674 | assert(VM_Version::supports_avx512bw(), "")do { if (!(VM_Version::supports_avx512bw())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2674, "assert(" "VM_Version::supports_avx512bw()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 2675 | InstructionAttr attributes(AVX_256bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 2676 | int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 2677 | emit_int16(0x41, (0xC0 | encode)); | |||
| 2678 | } | |||
| 2679 | ||||
| 2680 | void Assembler::kandql(KRegister dst, KRegister src1, KRegister src2) { | |||
| 2681 | assert(VM_Version::supports_avx512bw(), "")do { if (!(VM_Version::supports_avx512bw())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2681, "assert(" "VM_Version::supports_avx512bw()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 2682 | InstructionAttr attributes(AVX_256bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 2683 | int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 2684 | emit_int16(0x41, (0xC0 | encode)); | |||
| 2685 | } | |||
| 2686 | ||||
| 2687 | void Assembler::knotdl(KRegister dst, KRegister src) { | |||
| 2688 | assert(VM_Version::supports_avx512bw(), "")do { if (!(VM_Version::supports_avx512bw())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2688, "assert(" "VM_Version::supports_avx512bw()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 2689 | InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 2690 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 2691 | emit_int16(0x44, (0xC0 | encode)); | |||
| 2692 | } | |||
| 2693 | ||||
| 2694 | void Assembler::knotql(KRegister dst, KRegister src) { | |||
| 2695 | assert(VM_Version::supports_avx512bw(), "")do { if (!(VM_Version::supports_avx512bw())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2695, "assert(" "VM_Version::supports_avx512bw()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 2696 | InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 2697 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 2698 | emit_int16(0x44, (0xC0 | encode)); | |||
| 2699 | } | |||
| 2700 | ||||
| 2701 | // This instruction produces ZF or CF flags | |||
| 2702 | void Assembler::kortestbl(KRegister src1, KRegister src2) { | |||
| 2703 | assert(VM_Version::supports_avx512dq(), "")do { if (!(VM_Version::supports_avx512dq())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2703, "assert(" "VM_Version::supports_avx512dq()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 2704 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 2705 | int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 2706 | emit_int16((unsigned char)0x98, (0xC0 | encode)); | |||
| 2707 | } | |||
| 2708 | ||||
| 2709 | // This instruction produces ZF or CF flags | |||
| 2710 | void Assembler::kortestwl(KRegister src1, KRegister src2) { | |||
| 2711 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2711, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 2712 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 2713 | int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 2714 | emit_int16((unsigned char)0x98, (0xC0 | encode)); | |||
| 2715 | } | |||
| 2716 | ||||
| 2717 | // This instruction produces ZF or CF flags | |||
| 2718 | void Assembler::kortestdl(KRegister src1, KRegister src2) { | |||
| 2719 | assert(VM_Version::supports_avx512bw(), "")do { if (!(VM_Version::supports_avx512bw())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2719, "assert(" "VM_Version::supports_avx512bw()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 2720 | InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 2721 | int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 2722 | emit_int16((unsigned char)0x98, (0xC0 | encode)); | |||
| 2723 | } | |||
| 2724 | ||||
| 2725 | // This instruction produces ZF or CF flags | |||
| 2726 | void Assembler::kortestql(KRegister src1, KRegister src2) { | |||
| 2727 | assert(VM_Version::supports_avx512bw(), "")do { if (!(VM_Version::supports_avx512bw())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2727, "assert(" "VM_Version::supports_avx512bw()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 2728 | InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 2729 | int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 2730 | emit_int16((unsigned char)0x98, (0xC0 | encode)); | |||
| 2731 | } | |||
| 2732 | ||||
| 2733 | // This instruction produces ZF or CF flags | |||
| 2734 | void Assembler::ktestql(KRegister src1, KRegister src2) { | |||
| 2735 | assert(VM_Version::supports_avx512bw(), "")do { if (!(VM_Version::supports_avx512bw())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2735, "assert(" "VM_Version::supports_avx512bw()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 2736 | InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 2737 | int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 2738 | emit_int16((unsigned char)0x99, (0xC0 | encode)); | |||
| 2739 | } | |||
| 2740 | ||||
| 2741 | void Assembler::ktestdl(KRegister src1, KRegister src2) { | |||
| 2742 | assert(VM_Version::supports_avx512bw(), "")do { if (!(VM_Version::supports_avx512bw())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2742, "assert(" "VM_Version::supports_avx512bw()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 2743 | InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 2744 | int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 2745 | emit_int16((unsigned char)0x99, (0xC0 | encode)); | |||
| 2746 | } | |||
| 2747 | ||||
| 2748 | void Assembler::ktestwl(KRegister src1, KRegister src2) { | |||
| 2749 | assert(VM_Version::supports_avx512dq(), "")do { if (!(VM_Version::supports_avx512dq())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2749, "assert(" "VM_Version::supports_avx512dq()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 2750 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 2751 | int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 2752 | emit_int16((unsigned char)0x99, (0xC0 | encode)); | |||
| 2753 | } | |||
| 2754 | ||||
| 2755 | void Assembler::ktestbl(KRegister src1, KRegister src2) { | |||
| 2756 | assert(VM_Version::supports_avx512dq(), "")do { if (!(VM_Version::supports_avx512dq())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2756, "assert(" "VM_Version::supports_avx512dq()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 2757 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 2758 | int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 2759 | emit_int16((unsigned char)0x99, (0xC0 | encode)); | |||
| 2760 | } | |||
| 2761 | ||||
| 2762 | void Assembler::ktestq(KRegister src1, KRegister src2) { | |||
| 2763 | assert(VM_Version::supports_avx512bw(), "")do { if (!(VM_Version::supports_avx512bw())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2763, "assert(" "VM_Version::supports_avx512bw()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 2764 | InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 2765 | int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 2766 | emit_int16((unsigned char)0x99, (0xC0 | encode)); | |||
| 2767 | } | |||
| 2768 | ||||
| 2769 | void Assembler::ktestd(KRegister src1, KRegister src2) { | |||
| 2770 | assert(VM_Version::supports_avx512bw(), "")do { if (!(VM_Version::supports_avx512bw())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2770, "assert(" "VM_Version::supports_avx512bw()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 2771 | InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 2772 | int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 2773 | emit_int16((unsigned char)0x99, (0xC0 | encode)); | |||
| 2774 | } | |||
| 2775 | ||||
| 2776 | void Assembler::kxnorbl(KRegister dst, KRegister src1, KRegister src2) { | |||
| 2777 | assert(VM_Version::supports_avx512dq(), "")do { if (!(VM_Version::supports_avx512dq())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2777, "assert(" "VM_Version::supports_avx512dq()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 2778 | InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 2779 | int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 2780 | emit_int16(0x46, (0xC0 | encode)); | |||
| 2781 | } | |||
| 2782 | ||||
| 2783 | void Assembler::kshiftlbl(KRegister dst, KRegister src, int imm8) { | |||
| 2784 | assert(VM_Version::supports_avx512dq(), "")do { if (!(VM_Version::supports_avx512dq())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2784, "assert(" "VM_Version::supports_avx512dq()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 2785 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 2786 | int encode = vex_prefix_and_encode(dst->encoding(), 0 , src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 2787 | emit_int16(0x32, (0xC0 | encode)); | |||
| 2788 | emit_int8(imm8); | |||
| 2789 | } | |||
| 2790 | ||||
| 2791 | void Assembler::kshiftrbl(KRegister dst, KRegister src, int imm8) { | |||
| 2792 | assert(VM_Version::supports_avx512dq(), "")do { if (!(VM_Version::supports_avx512dq())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2792, "assert(" "VM_Version::supports_avx512dq()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 2793 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 2794 | int encode = vex_prefix_and_encode(dst->encoding(), 0 , src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 2795 | emit_int16(0x30, (0xC0 | encode)); | |||
| 2796 | } | |||
| 2797 | ||||
| 2798 | void Assembler::kshiftrwl(KRegister dst, KRegister src, int imm8) { | |||
| 2799 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2799, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 2800 | InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 2801 | int encode = vex_prefix_and_encode(dst->encoding(), 0 , src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 2802 | emit_int16(0x30, (0xC0 | encode)); | |||
| 2803 | emit_int8(imm8); | |||
| 2804 | } | |||
| 2805 | ||||
| 2806 | void Assembler::kshiftrdl(KRegister dst, KRegister src, int imm8) { | |||
| 2807 | assert(VM_Version::supports_avx512bw(), "")do { if (!(VM_Version::supports_avx512bw())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2807, "assert(" "VM_Version::supports_avx512bw()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 2808 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 2809 | int encode = vex_prefix_and_encode(dst->encoding(), 0 , src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 2810 | emit_int16(0x31, (0xC0 | encode)); | |||
| 2811 | emit_int8(imm8); | |||
| 2812 | } | |||
| 2813 | ||||
| 2814 | void Assembler::kshiftrql(KRegister dst, KRegister src, int imm8) { | |||
| 2815 | assert(VM_Version::supports_avx512bw(), "")do { if (!(VM_Version::supports_avx512bw())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2815, "assert(" "VM_Version::supports_avx512bw()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 2816 | InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 2817 | int encode = vex_prefix_and_encode(dst->encoding(), 0 , src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 2818 | emit_int16(0x31, (0xC0 | encode)); | |||
| 2819 | emit_int8(imm8); | |||
| 2820 | } | |||
| 2821 | ||||
| 2822 | void Assembler::movb(Address dst, int imm8) { | |||
| 2823 | InstructionMark im(this); | |||
| 2824 | prefix(dst); | |||
| 2825 | emit_int8((unsigned char)0xC6); | |||
| 2826 | emit_operand(rax, dst, 1); | |||
| 2827 | emit_int8(imm8); | |||
| 2828 | } | |||
| 2829 | ||||
| 2830 | ||||
| 2831 | void Assembler::movb(Address dst, Register src) { | |||
| 2832 | assert(src->has_byte_register(), "must have byte register")do { if (!(src->has_byte_register())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2832, "assert(" "src->has_byte_register()" ") failed", "must have byte register" ); ::breakpoint(); } } while (0); | |||
| 2833 | InstructionMark im(this); | |||
| 2834 | prefix(dst, src, true); | |||
| 2835 | emit_int8((unsigned char)0x88); | |||
| 2836 | emit_operand(src, dst); | |||
| 2837 | } | |||
| 2838 | ||||
| 2839 | void Assembler::movdl(XMMRegister dst, Register src) { | |||
| 2840 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 2841 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 2842 | int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 2843 | emit_int16(0x6E, (0xC0 | encode)); | |||
| 2844 | } | |||
| 2845 | ||||
| 2846 | void Assembler::movdl(Register dst, XMMRegister src) { | |||
| 2847 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 2848 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 2849 | // swap src/dst to get correct prefix | |||
| 2850 | int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 2851 | emit_int16(0x7E, (0xC0 | encode)); | |||
| 2852 | } | |||
| 2853 | ||||
| 2854 | void Assembler::movdl(XMMRegister dst, Address src) { | |||
| 2855 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 2856 | InstructionMark im(this); | |||
| 2857 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 2858 | attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); | |||
| 2859 | simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 2860 | emit_int8(0x6E); | |||
| 2861 | emit_operand(dst, src); | |||
| 2862 | } | |||
| 2863 | ||||
| 2864 | void Assembler::movdl(Address dst, XMMRegister src) { | |||
| 2865 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 2866 | InstructionMark im(this); | |||
| 2867 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 2868 | attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); | |||
| 2869 | simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 2870 | emit_int8(0x7E); | |||
| 2871 | emit_operand(src, dst); | |||
| 2872 | } | |||
| 2873 | ||||
| 2874 | void Assembler::movdqa(XMMRegister dst, XMMRegister src) { | |||
| 2875 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 2876 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 2877 | int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 2878 | emit_int16(0x6F, (0xC0 | encode)); | |||
| 2879 | } | |||
| 2880 | ||||
| 2881 | void Assembler::movdqa(XMMRegister dst, Address src) { | |||
| 2882 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 2883 | InstructionMark im(this); | |||
| 2884 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 2885 | attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); | |||
| 2886 | simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 2887 | emit_int8(0x6F); | |||
| 2888 | emit_operand(dst, src); | |||
| 2889 | } | |||
| 2890 | ||||
| 2891 | void Assembler::movdqu(XMMRegister dst, Address src) { | |||
| 2892 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 2893 | InstructionMark im(this); | |||
| 2894 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 2895 | attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); | |||
| 2896 | simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); | |||
| 2897 | emit_int8(0x6F); | |||
| 2898 | emit_operand(dst, src); | |||
| 2899 | } | |||
| 2900 | ||||
| 2901 | void Assembler::movdqu(XMMRegister dst, XMMRegister src) { | |||
| 2902 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 2903 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 2904 | int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); | |||
| 2905 | emit_int16(0x6F, (0xC0 | encode)); | |||
| 2906 | } | |||
| 2907 | ||||
| 2908 | void Assembler::movdqu(Address dst, XMMRegister src) { | |||
| 2909 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 2910 | InstructionMark im(this); | |||
| 2911 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 2912 | attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); | |||
| 2913 | attributes.reset_is_clear_context(); | |||
| 2914 | simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); | |||
| 2915 | emit_int8(0x7F); | |||
| 2916 | emit_operand(src, dst); | |||
| 2917 | } | |||
| 2918 | ||||
| 2919 | // Move Unaligned 256bit Vector | |||
| 2920 | void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) { | |||
| 2921 | assert(UseAVX > 0, "")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2921, "assert(" "UseAVX > 0" ") failed", ""); ::breakpoint (); } } while (0); | |||
| 2922 | InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 2923 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); | |||
| 2924 | emit_int16(0x6F, (0xC0 | encode)); | |||
| 2925 | } | |||
| 2926 | ||||
| 2927 | void Assembler::vmovdqu(XMMRegister dst, Address src) { | |||
| 2928 | assert(UseAVX > 0, "")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2928, "assert(" "UseAVX > 0" ") failed", ""); ::breakpoint (); } } while (0); | |||
| 2929 | InstructionMark im(this); | |||
| 2930 | InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 2931 | attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); | |||
| 2932 | vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); | |||
| 2933 | emit_int8(0x6F); | |||
| 2934 | emit_operand(dst, src); | |||
| 2935 | } | |||
| 2936 | ||||
| 2937 | void Assembler::vmovdqu(Address dst, XMMRegister src) { | |||
| 2938 | assert(UseAVX > 0, "")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2938, "assert(" "UseAVX > 0" ") failed", ""); ::breakpoint (); } } while (0); | |||
| 2939 | InstructionMark im(this); | |||
| 2940 | InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 2941 | attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); | |||
| 2942 | attributes.reset_is_clear_context(); | |||
| 2943 | // swap src<->dst for encoding | |||
| 2944 | assert(src != xnoreg, "sanity")do { if (!(src != xnoreg)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2944, "assert(" "src != xnoreg" ") failed", "sanity"); ::breakpoint (); } } while (0); | |||
| 2945 | vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); | |||
| 2946 | emit_int8(0x7F); | |||
| 2947 | emit_operand(src, dst); | |||
| 2948 | } | |||
| 2949 | ||||
| 2950 | // Move Unaligned EVEX enabled Vector (programmable : 8,16,32,64) | |||
| 2951 | void Assembler::evmovdqub(XMMRegister dst, XMMRegister src, bool merge, int vector_len) { | |||
| 2952 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2952, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 2953 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 2954 | attributes.set_is_evex_instruction(); | |||
| 2955 | if (merge) { | |||
| 2956 | attributes.reset_is_clear_context(); | |||
| 2957 | } | |||
| 2958 | int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3; | |||
| 2959 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes); | |||
| 2960 | emit_int16(0x6F, (0xC0 | encode)); | |||
| 2961 | } | |||
| 2962 | ||||
| 2963 | void Assembler::evmovdqub(XMMRegister dst, Address src, bool merge, int vector_len) { | |||
| 2964 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2964, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 2965 | InstructionMark im(this); | |||
| 2966 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 2967 | int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3; | |||
| 2968 | attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); | |||
| 2969 | attributes.set_is_evex_instruction(); | |||
| 2970 | if (merge) { | |||
| 2971 | attributes.reset_is_clear_context(); | |||
| 2972 | } | |||
| 2973 | vex_prefix(src, 0, dst->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes); | |||
| 2974 | emit_int8(0x6F); | |||
| 2975 | emit_operand(dst, src); | |||
| 2976 | } | |||
| 2977 | ||||
| 2978 | void Assembler::evmovdqub(Address dst, XMMRegister src, bool merge, int vector_len) { | |||
| 2979 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2979, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 2980 | assert(src != xnoreg, "sanity")do { if (!(src != xnoreg)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2980, "assert(" "src != xnoreg" ") failed", "sanity"); ::breakpoint (); } } while (0); | |||
| 2981 | InstructionMark im(this); | |||
| 2982 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 2983 | int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3; | |||
| 2984 | attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); | |||
| 2985 | attributes.set_is_evex_instruction(); | |||
| 2986 | if (merge) { | |||
| 2987 | attributes.reset_is_clear_context(); | |||
| 2988 | } | |||
| 2989 | vex_prefix(dst, 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes); | |||
| 2990 | emit_int8(0x7F); | |||
| 2991 | emit_operand(src, dst); | |||
| 2992 | } | |||
| 2993 | ||||
| 2994 | void Assembler::evmovdqub(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) { | |||
| 2995 | assert(VM_Version::supports_avx512vlbw(), "")do { if (!(VM_Version::supports_avx512vlbw())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 2995, "assert(" "VM_Version::supports_avx512vlbw()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 2996 | InstructionMark im(this); | |||
| 2997 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 2998 | attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); | |||
| 2999 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 3000 | attributes.set_is_evex_instruction(); | |||
| 3001 | if (merge) { | |||
| 3002 | attributes.reset_is_clear_context(); | |||
| 3003 | } | |||
| 3004 | vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); | |||
| 3005 | emit_int8(0x6F); | |||
| 3006 | emit_operand(dst, src); | |||
| 3007 | } | |||
| 3008 | ||||
| 3009 | void Assembler::evmovdqub(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len) { | |||
| 3010 | assert(VM_Version::supports_avx512vlbw(), "")do { if (!(VM_Version::supports_avx512vlbw())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 3010, "assert(" "VM_Version::supports_avx512vlbw()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 3011 | assert(src != xnoreg, "sanity")do { if (!(src != xnoreg)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 3011, "assert(" "src != xnoreg" ") failed", "sanity"); ::breakpoint (); } } while (0); | |||
| 3012 | InstructionMark im(this); | |||
| 3013 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 3014 | attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); | |||
| 3015 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 3016 | attributes.set_is_evex_instruction(); | |||
| 3017 | if (merge) { | |||
| 3018 | attributes.reset_is_clear_context(); | |||
| 3019 | } | |||
| 3020 | vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); | |||
| 3021 | emit_int8(0x7F); | |||
| 3022 | emit_operand(src, dst); | |||
| 3023 | } | |||
| 3024 | ||||
| 3025 | void Assembler::evmovdquw(XMMRegister dst, Address src, bool merge, int vector_len) { | |||
| 3026 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 3026, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 3027 | InstructionMark im(this); | |||
| 3028 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 3029 | attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); | |||
| 3030 | attributes.set_is_evex_instruction(); | |||
| 3031 | if (merge) { | |||
| 3032 | attributes.reset_is_clear_context(); | |||
| 3033 | } | |||
| 3034 | int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3; | |||
| 3035 | vex_prefix(src, 0, dst->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes); | |||
| 3036 | emit_int8(0x6F); | |||
| 3037 | emit_operand(dst, src); | |||
| 3038 | } | |||
| 3039 | ||||
| 3040 | void Assembler::evmovdquw(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) { | |||
| 3041 | assert(VM_Version::supports_avx512vlbw(), "")do { if (!(VM_Version::supports_avx512vlbw())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 3041, "assert(" "VM_Version::supports_avx512vlbw()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 3042 | InstructionMark im(this); | |||
| 3043 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 3044 | attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); | |||
| 3045 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 3046 | attributes.set_is_evex_instruction(); | |||
| 3047 | if (merge) { | |||
| 3048 | attributes.reset_is_clear_context(); | |||
| 3049 | } | |||
| 3050 | vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); | |||
| 3051 | emit_int8(0x6F); | |||
| 3052 | emit_operand(dst, src); | |||
| 3053 | } | |||
| 3054 | ||||
| 3055 | void Assembler::evmovdquw(Address dst, XMMRegister src, bool merge, int vector_len) { | |||
| 3056 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 3056, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 3057 | assert(src != xnoreg, "sanity")do { if (!(src != xnoreg)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 3057, "assert(" "src != xnoreg" ") failed", "sanity"); ::breakpoint (); } } while (0); | |||
| 3058 | InstructionMark im(this); | |||
| 3059 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 3060 | attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); | |||
| 3061 | attributes.set_is_evex_instruction(); | |||
| 3062 | if (merge) { | |||
| 3063 | attributes.reset_is_clear_context(); | |||
| 3064 | } | |||
| 3065 | int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3; | |||
| 3066 | vex_prefix(dst, 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes); | |||
| 3067 | emit_int8(0x7F); | |||
| 3068 | emit_operand(src, dst); | |||
| 3069 | } | |||
| 3070 | ||||
| 3071 | void Assembler::evmovdquw(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len) { | |||
| 3072 | assert(VM_Version::supports_avx512vlbw(), "")do { if (!(VM_Version::supports_avx512vlbw())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 3072, "assert(" "VM_Version::supports_avx512vlbw()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 3073 | assert(src != xnoreg, "sanity")do { if (!(src != xnoreg)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 3073, "assert(" "src != xnoreg" ") failed", "sanity"); ::breakpoint (); } } while (0); | |||
| 3074 | InstructionMark im(this); | |||
| 3075 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 3076 | attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); | |||
| 3077 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 3078 | attributes.set_is_evex_instruction(); | |||
| 3079 | if (merge) { | |||
| 3080 | attributes.reset_is_clear_context(); | |||
| 3081 | } | |||
| 3082 | vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); | |||
| 3083 | emit_int8(0x7F); | |||
| 3084 | emit_operand(src, dst); | |||
| 3085 | } | |||
| 3086 | ||||
| 3087 | void Assembler::evmovdqul(XMMRegister dst, XMMRegister src, int vector_len) { | |||
| 3088 | // Unmasked instruction | |||
| 3089 | evmovdqul(dst, k0, src, /*merge*/ false, vector_len); | |||
| 3090 | } | |||
| 3091 | ||||
| 3092 | void Assembler::evmovdqul(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) { | |||
| 3093 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 3093, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 3094 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 3095 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 3096 | attributes.set_is_evex_instruction(); | |||
| 3097 | if (merge) { | |||
| 3098 | attributes.reset_is_clear_context(); | |||
| 3099 | } | |||
| 3100 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); | |||
| 3101 | emit_int16(0x6F, (0xC0 | encode)); | |||
| 3102 | } | |||
| 3103 | ||||
| 3104 | void Assembler::evmovdqul(XMMRegister dst, Address src, int vector_len) { | |||
| 3105 | // Unmasked instruction | |||
| 3106 | evmovdqul(dst, k0, src, /*merge*/ false, vector_len); | |||
| 3107 | } | |||
| 3108 | ||||
| 3109 | void Assembler::evmovdqul(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) { | |||
| 3110 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 3110, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 3111 | InstructionMark im(this); | |||
| 3112 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false , /* uses_vl */ true); | |||
| 3113 | attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); | |||
| 3114 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 3115 | attributes.set_is_evex_instruction(); | |||
| 3116 | if (merge) { | |||
| 3117 | attributes.reset_is_clear_context(); | |||
| 3118 | } | |||
| 3119 | vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); | |||
| 3120 | emit_int8(0x6F); | |||
| 3121 | emit_operand(dst, src); | |||
| 3122 | } | |||
| 3123 | ||||
| 3124 | void Assembler::evmovdqul(Address dst, XMMRegister src, int vector_len) { | |||
| 3125 | // Unmasked isntruction | |||
| 3126 | evmovdqul(dst, k0, src, /*merge*/ true, vector_len); | |||
| 3127 | } | |||
| 3128 | ||||
| 3129 | void Assembler::evmovdqul(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len) { | |||
| 3130 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 3130, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 3131 | assert(src != xnoreg, "sanity")do { if (!(src != xnoreg)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 3131, "assert(" "src != xnoreg" ") failed", "sanity"); ::breakpoint (); } } while (0); | |||
| 3132 | InstructionMark im(this); | |||
| 3133 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 3134 | attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); | |||
| 3135 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 3136 | attributes.set_is_evex_instruction(); | |||
| 3137 | if (merge) { | |||
| 3138 | attributes.reset_is_clear_context(); | |||
| 3139 | } | |||
| 3140 | vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); | |||
| 3141 | emit_int8(0x7F); | |||
| 3142 | emit_operand(src, dst); | |||
| 3143 | } | |||
| 3144 | ||||
| 3145 | void Assembler::evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) { | |||
| 3146 | // Unmasked instruction | |||
| 3147 | if (dst->encoding() == src->encoding()) return; | |||
| 3148 | evmovdquq(dst, k0, src, /*merge*/ false, vector_len); | |||
| 3149 | } | |||
| 3150 | ||||
| 3151 | void Assembler::evmovdquq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) { | |||
| 3152 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 3152, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 3153 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 3154 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 3155 | attributes.set_is_evex_instruction(); | |||
| 3156 | if (merge) { | |||
| 3157 | attributes.reset_is_clear_context(); | |||
| 3158 | } | |||
| 3159 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); | |||
| 3160 | emit_int16(0x6F, (0xC0 | encode)); | |||
| 3161 | } | |||
| 3162 | ||||
| 3163 | void Assembler::evmovdquq(XMMRegister dst, Address src, int vector_len) { | |||
| 3164 | // Unmasked instruction | |||
| 3165 | evmovdquq(dst, k0, src, /*merge*/ false, vector_len); | |||
| 3166 | } | |||
| 3167 | ||||
| 3168 | void Assembler::evmovdquq(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) { | |||
| 3169 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 3169, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 3170 | InstructionMark im(this); | |||
| 3171 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 3172 | attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); | |||
| 3173 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 3174 | attributes.set_is_evex_instruction(); | |||
| 3175 | if (merge) { | |||
| 3176 | attributes.reset_is_clear_context(); | |||
| 3177 | } | |||
| 3178 | vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); | |||
| 3179 | emit_int8(0x6F); | |||
| 3180 | emit_operand(dst, src); | |||
| 3181 | } | |||
| 3182 | ||||
| 3183 | void Assembler::evmovdquq(Address dst, XMMRegister src, int vector_len) { | |||
| 3184 | // Unmasked instruction | |||
| 3185 | evmovdquq(dst, k0, src, /*merge*/ true, vector_len); | |||
| 3186 | } | |||
| 3187 | ||||
| 3188 | void Assembler::evmovdquq(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len) { | |||
| 3189 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 3189, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 3190 | assert(src != xnoreg, "sanity")do { if (!(src != xnoreg)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 3190, "assert(" "src != xnoreg" ") failed", "sanity"); ::breakpoint (); } } while (0); | |||
| 3191 | InstructionMark im(this); | |||
| 3192 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 3193 | attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); | |||
| 3194 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 3195 | if (merge) { | |||
| 3196 | attributes.reset_is_clear_context(); | |||
| 3197 | } | |||
| 3198 | attributes.set_is_evex_instruction(); | |||
| 3199 | vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); | |||
| 3200 | emit_int8(0x7F); | |||
| 3201 | emit_operand(src, dst); | |||
| 3202 | } | |||
| 3203 | ||||
| 3204 | // Uses zero extension on 64bit | |||
| 3205 | ||||
| 3206 | void Assembler::movl(Register dst, int32_t imm32) { | |||
| 3207 | int encode = prefix_and_encode(dst->encoding()); | |||
| 3208 | emit_int8(0xB8 | encode); | |||
| 3209 | emit_int32(imm32); | |||
| 3210 | } | |||
| 3211 | ||||
| 3212 | void Assembler::movl(Register dst, Register src) { | |||
| 3213 | int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |||
| 3214 | emit_int16((unsigned char)0x8B, (0xC0 | encode)); | |||
| 3215 | } | |||
| 3216 | ||||
| 3217 | void Assembler::movl(Register dst, Address src) { | |||
| 3218 | InstructionMark im(this); | |||
| 3219 | prefix(src, dst); | |||
| 3220 | emit_int8((unsigned char)0x8B); | |||
| 3221 | emit_operand(dst, src); | |||
| 3222 | } | |||
| 3223 | ||||
| 3224 | void Assembler::movl(Address dst, int32_t imm32) { | |||
| 3225 | InstructionMark im(this); | |||
| 3226 | prefix(dst); | |||
| 3227 | emit_int8((unsigned char)0xC7); | |||
| 3228 | emit_operand(rax, dst, 4); | |||
| 3229 | emit_int32(imm32); | |||
| 3230 | } | |||
| 3231 | ||||
| 3232 | void Assembler::movl(Address dst, Register src) { | |||
| 3233 | InstructionMark im(this); | |||
| 3234 | prefix(dst, src); | |||
| 3235 | emit_int8((unsigned char)0x89); | |||
| 3236 | emit_operand(src, dst); | |||
| 3237 | } | |||
| 3238 | ||||
| 3239 | // New cpus require to use movsd and movss to avoid partial register stall | |||
| 3240 | // when loading from memory. But for old Opteron use movlpd instead of movsd. | |||
| 3241 | // The selection is done in MacroAssembler::movdbl() and movflt(). | |||
| 3242 | void Assembler::movlpd(XMMRegister dst, Address src) { | |||
| 3243 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 3244 | InstructionMark im(this); | |||
| 3245 | InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 3246 | attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); | |||
| 3247 | attributes.set_rex_vex_w_reverted(); | |||
| 3248 | simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 3249 | emit_int8(0x12); | |||
| 3250 | emit_operand(dst, src); | |||
| 3251 | } | |||
| 3252 | ||||
| 3253 | void Assembler::movq(XMMRegister dst, Address src) { | |||
| 3254 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 3255 | InstructionMark im(this); | |||
| 3256 | InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 3257 | attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); | |||
| 3258 | attributes.set_rex_vex_w_reverted(); | |||
| 3259 | simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); | |||
| 3260 | emit_int8(0x7E); | |||
| 3261 | emit_operand(dst, src); | |||
| 3262 | } | |||
| 3263 | ||||
| 3264 | void Assembler::movq(Address dst, XMMRegister src) { | |||
| 3265 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 3266 | InstructionMark im(this); | |||
| 3267 | InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 3268 | attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); | |||
| 3269 | attributes.set_rex_vex_w_reverted(); | |||
| 3270 | simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 3271 | emit_int8((unsigned char)0xD6); | |||
| 3272 | emit_operand(src, dst); | |||
| 3273 | } | |||
| 3274 | ||||
| 3275 | void Assembler::movq(XMMRegister dst, XMMRegister src) { | |||
| 3276 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 3277 | InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 3278 | attributes.set_rex_vex_w_reverted(); | |||
| 3279 | int encode = simd_prefix_and_encode(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 3280 | emit_int16((unsigned char)0xD6, (0xC0 | encode)); | |||
| 3281 | } | |||
| 3282 | ||||
| 3283 | void Assembler::movq(Register dst, XMMRegister src) { | |||
| 3284 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 3285 | InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 3286 | // swap src/dst to get correct prefix | |||
| 3287 | int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 3288 | emit_int16(0x7E, (0xC0 | encode)); | |||
| 3289 | } | |||
| 3290 | ||||
| 3291 | void Assembler::movq(XMMRegister dst, Register src) { | |||
| 3292 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 3293 | InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 3294 | int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 3295 | emit_int16(0x6E, (0xC0 | encode)); | |||
| 3296 | } | |||
| 3297 | ||||
| 3298 | void Assembler::movsbl(Register dst, Address src) { // movsxb | |||
| 3299 | InstructionMark im(this); | |||
| 3300 | prefix(src, dst); | |||
| 3301 | emit_int16(0x0F, (unsigned char)0xBE); | |||
| 3302 | emit_operand(dst, src); | |||
| 3303 | } | |||
| 3304 | ||||
| 3305 | void Assembler::movsbl(Register dst, Register src) { // movsxb | |||
| 3306 | NOT_LP64(assert(src->has_byte_register(), "must have byte register")); | |||
| 3307 | int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true); | |||
| 3308 | emit_int24(0x0F, (unsigned char)0xBE, (0xC0 | encode)); | |||
| 3309 | } | |||
| 3310 | ||||
| 3311 | void Assembler::movsd(XMMRegister dst, XMMRegister src) { | |||
| 3312 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 3313 | InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 3314 | attributes.set_rex_vex_w_reverted(); | |||
| 3315 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); | |||
| 3316 | emit_int16(0x10, (0xC0 | encode)); | |||
| 3317 | } | |||
| 3318 | ||||
| 3319 | void Assembler::movsd(XMMRegister dst, Address src) { | |||
| 3320 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 3321 | InstructionMark im(this); | |||
| 3322 | InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 3323 | attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); | |||
| 3324 | attributes.set_rex_vex_w_reverted(); | |||
| 3325 | simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); | |||
| 3326 | emit_int8(0x10); | |||
| 3327 | emit_operand(dst, src); | |||
| 3328 | } | |||
| 3329 | ||||
| 3330 | void Assembler::movsd(Address dst, XMMRegister src) { | |||
| 3331 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 3332 | InstructionMark im(this); | |||
| 3333 | InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 3334 | attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); | |||
| 3335 | attributes.reset_is_clear_context(); | |||
| 3336 | attributes.set_rex_vex_w_reverted(); | |||
| 3337 | simd_prefix(src, xnoreg, dst, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); | |||
| 3338 | emit_int8(0x11); | |||
| 3339 | emit_operand(src, dst); | |||
| 3340 | } | |||
| 3341 | ||||
| 3342 | void Assembler::movss(XMMRegister dst, XMMRegister src) { | |||
| 3343 | NOT_LP64(assert(VM_Version::supports_sse(), "")); | |||
| 3344 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 3345 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); | |||
| 3346 | emit_int16(0x10, (0xC0 | encode)); | |||
| 3347 | } | |||
| 3348 | ||||
| 3349 | void Assembler::movss(XMMRegister dst, Address src) { | |||
| 3350 | NOT_LP64(assert(VM_Version::supports_sse(), "")); | |||
| 3351 | InstructionMark im(this); | |||
| 3352 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 3353 | attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); | |||
| 3354 | simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); | |||
| 3355 | emit_int8(0x10); | |||
| 3356 | emit_operand(dst, src); | |||
| 3357 | } | |||
| 3358 | ||||
| 3359 | void Assembler::movss(Address dst, XMMRegister src) { | |||
| 3360 | NOT_LP64(assert(VM_Version::supports_sse(), "")); | |||
| 3361 | InstructionMark im(this); | |||
| 3362 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 3363 | attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); | |||
| 3364 | attributes.reset_is_clear_context(); | |||
| 3365 | simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); | |||
| 3366 | emit_int8(0x11); | |||
| 3367 | emit_operand(src, dst); | |||
| 3368 | } | |||
| 3369 | ||||
| 3370 | void Assembler::movswl(Register dst, Address src) { // movsxw | |||
| 3371 | InstructionMark im(this); | |||
| 3372 | prefix(src, dst); | |||
| 3373 | emit_int16(0x0F, (unsigned char)0xBF); | |||
| 3374 | emit_operand(dst, src); | |||
| 3375 | } | |||
| 3376 | ||||
| 3377 | void Assembler::movswl(Register dst, Register src) { // movsxw | |||
| 3378 | int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |||
| 3379 | emit_int24(0x0F, (unsigned char)0xBF, (0xC0 | encode)); | |||
| 3380 | } | |||
| 3381 | ||||
| 3382 | void Assembler::movw(Address dst, int imm16) { | |||
| 3383 | InstructionMark im(this); | |||
| 3384 | ||||
| 3385 | emit_int8(0x66); // switch to 16-bit mode | |||
| 3386 | prefix(dst); | |||
| 3387 | emit_int8((unsigned char)0xC7); | |||
| 3388 | emit_operand(rax, dst, 2); | |||
| 3389 | emit_int16(imm16); | |||
| 3390 | } | |||
| 3391 | ||||
| 3392 | void Assembler::movw(Register dst, Address src) { | |||
| 3393 | InstructionMark im(this); | |||
| 3394 | emit_int8(0x66); | |||
| 3395 | prefix(src, dst); | |||
| 3396 | emit_int8((unsigned char)0x8B); | |||
| 3397 | emit_operand(dst, src); | |||
| 3398 | } | |||
| 3399 | ||||
| 3400 | void Assembler::movw(Address dst, Register src) { | |||
| 3401 | InstructionMark im(this); | |||
| 3402 | emit_int8(0x66); | |||
| 3403 | prefix(dst, src); | |||
| 3404 | emit_int8((unsigned char)0x89); | |||
| 3405 | emit_operand(src, dst); | |||
| 3406 | } | |||
| 3407 | ||||
| 3408 | void Assembler::movzbl(Register dst, Address src) { // movzxb | |||
| 3409 | InstructionMark im(this); | |||
| 3410 | prefix(src, dst); | |||
| 3411 | emit_int16(0x0F, (unsigned char)0xB6); | |||
| 3412 | emit_operand(dst, src); | |||
| 3413 | } | |||
| 3414 | ||||
| 3415 | void Assembler::movzbl(Register dst, Register src) { // movzxb | |||
| 3416 | NOT_LP64(assert(src->has_byte_register(), "must have byte register")); | |||
| 3417 | int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true); | |||
| 3418 | emit_int24(0x0F, (unsigned char)0xB6, 0xC0 | encode); | |||
| 3419 | } | |||
| 3420 | ||||
| 3421 | void Assembler::movzwl(Register dst, Address src) { // movzxw | |||
| 3422 | InstructionMark im(this); | |||
| 3423 | prefix(src, dst); | |||
| 3424 | emit_int16(0x0F, (unsigned char)0xB7); | |||
| 3425 | emit_operand(dst, src); | |||
| 3426 | } | |||
| 3427 | ||||
| 3428 | void Assembler::movzwl(Register dst, Register src) { // movzxw | |||
| 3429 | int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |||
| 3430 | emit_int24(0x0F, (unsigned char)0xB7, 0xC0 | encode); | |||
| 3431 | } | |||
| 3432 | ||||
| 3433 | void Assembler::mull(Address src) { | |||
| 3434 | InstructionMark im(this); | |||
| 3435 | prefix(src); | |||
| 3436 | emit_int8((unsigned char)0xF7); | |||
| 3437 | emit_operand(rsp, src); | |||
| 3438 | } | |||
| 3439 | ||||
| 3440 | void Assembler::mull(Register src) { | |||
| 3441 | int encode = prefix_and_encode(src->encoding()); | |||
| 3442 | emit_int16((unsigned char)0xF7, (0xE0 | encode)); | |||
| 3443 | } | |||
| 3444 | ||||
| 3445 | void Assembler::mulsd(XMMRegister dst, Address src) { | |||
| 3446 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 3447 | InstructionMark im(this); | |||
| 3448 | InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 3449 | attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); | |||
| 3450 | attributes.set_rex_vex_w_reverted(); | |||
| 3451 | simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); | |||
| 3452 | emit_int8(0x59); | |||
| 3453 | emit_operand(dst, src); | |||
| 3454 | } | |||
| 3455 | ||||
| 3456 | void Assembler::mulsd(XMMRegister dst, XMMRegister src) { | |||
| 3457 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 3458 | InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 3459 | attributes.set_rex_vex_w_reverted(); | |||
| 3460 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); | |||
| 3461 | emit_int16(0x59, (0xC0 | encode)); | |||
| 3462 | } | |||
| 3463 | ||||
| 3464 | void Assembler::mulss(XMMRegister dst, Address src) { | |||
| 3465 | NOT_LP64(assert(VM_Version::supports_sse(), "")); | |||
| 3466 | InstructionMark im(this); | |||
| 3467 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 3468 | attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); | |||
| 3469 | simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); | |||
| 3470 | emit_int8(0x59); | |||
| 3471 | emit_operand(dst, src); | |||
| 3472 | } | |||
| 3473 | ||||
| 3474 | void Assembler::mulss(XMMRegister dst, XMMRegister src) { | |||
| 3475 | NOT_LP64(assert(VM_Version::supports_sse(), "")); | |||
| 3476 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 3477 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); | |||
| 3478 | emit_int16(0x59, (0xC0 | encode)); | |||
| 3479 | } | |||
| 3480 | ||||
| 3481 | void Assembler::negl(Register dst) { | |||
| 3482 | int encode = prefix_and_encode(dst->encoding()); | |||
| 3483 | emit_int16((unsigned char)0xF7, (0xD8 | encode)); | |||
| 3484 | } | |||
| 3485 | ||||
| 3486 | void Assembler::negl(Address dst) { | |||
| 3487 | InstructionMark im(this); | |||
| 3488 | prefix(dst); | |||
| 3489 | emit_int8((unsigned char)0xF7); | |||
| 3490 | emit_operand(as_Register(3), dst); | |||
| 3491 | } | |||
| 3492 | ||||
| 3493 | void Assembler::nop(int i) { | |||
| 3494 | #ifdef ASSERT1 | |||
| 3495 | assert(i > 0, " ")do { if (!(i > 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 3495, "assert(" "i > 0" ") failed", " "); ::breakpoint() ; } } while (0); | |||
| 3496 | // The fancy nops aren't currently recognized by debuggers making it a | |||
| 3497 | // pain to disassemble code while debugging. If asserts are on clearly | |||
| 3498 | // speed is not an issue so simply use the single byte traditional nop | |||
| 3499 | // to do alignment. | |||
| 3500 | ||||
| 3501 | for (; i > 0 ; i--) emit_int8((unsigned char)0x90); | |||
| 3502 | return; | |||
| 3503 | ||||
| 3504 | #endif // ASSERT | |||
| 3505 | ||||
| 3506 | if (UseAddressNop && VM_Version::is_intel()) { | |||
| 3507 | // | |||
| 3508 | // Using multi-bytes nops "0x0F 0x1F [address]" for Intel | |||
| 3509 | // 1: 0x90 | |||
| 3510 | // 2: 0x66 0x90 | |||
| 3511 | // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding) | |||
| 3512 | // 4: 0x0F 0x1F 0x40 0x00 | |||
| 3513 | // 5: 0x0F 0x1F 0x44 0x00 0x00 | |||
| 3514 | // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00 | |||
| 3515 | // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |||
| 3516 | // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |||
| 3517 | // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |||
| 3518 | // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |||
| 3519 | // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |||
| 3520 | ||||
| 3521 | // The rest coding is Intel specific - don't use consecutive address nops | |||
| 3522 | ||||
| 3523 | // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |||
| 3524 | // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |||
| 3525 | // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |||
| 3526 | // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |||
| 3527 | ||||
| 3528 | while(i >= 15) { | |||
| 3529 | // For Intel don't generate consecutive addess nops (mix with regular nops) | |||
| 3530 | i -= 15; | |||
| 3531 | emit_int24(0x66, 0x66, 0x66); | |||
| 3532 | addr_nop_8(); | |||
| 3533 | emit_int32(0x66, 0x66, 0x66, (unsigned char)0x90); | |||
| 3534 | } | |||
| 3535 | switch (i) { | |||
| 3536 | case 14: | |||
| 3537 | emit_int8(0x66); // size prefix | |||
| 3538 | case 13: | |||
| 3539 | emit_int8(0x66); // size prefix | |||
| 3540 | case 12: | |||
| 3541 | addr_nop_8(); | |||
| 3542 | emit_int32(0x66, 0x66, 0x66, (unsigned char)0x90); | |||
| 3543 | break; | |||
| 3544 | case 11: | |||
| 3545 | emit_int8(0x66); // size prefix | |||
| 3546 | case 10: | |||
| 3547 | emit_int8(0x66); // size prefix | |||
| 3548 | case 9: | |||
| 3549 | emit_int8(0x66); // size prefix | |||
| 3550 | case 8: | |||
| 3551 | addr_nop_8(); | |||
| 3552 | break; | |||
| 3553 | case 7: | |||
| 3554 | addr_nop_7(); | |||
| 3555 | break; | |||
| 3556 | case 6: | |||
| 3557 | emit_int8(0x66); // size prefix | |||
| 3558 | case 5: | |||
| 3559 | addr_nop_5(); | |||
| 3560 | break; | |||
| 3561 | case 4: | |||
| 3562 | addr_nop_4(); | |||
| 3563 | break; | |||
| 3564 | case 3: | |||
| 3565 | // Don't use "0x0F 0x1F 0x00" - need patching safe padding | |||
| 3566 | emit_int8(0x66); // size prefix | |||
| 3567 | case 2: | |||
| 3568 | emit_int8(0x66); // size prefix | |||
| 3569 | case 1: | |||
| 3570 | emit_int8((unsigned char)0x90); | |||
| 3571 | // nop | |||
| 3572 | break; | |||
| 3573 | default: | |||
| 3574 | assert(i == 0, " ")do { if (!(i == 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 3574, "assert(" "i == 0" ") failed", " "); ::breakpoint(); } } while (0); | |||
| 3575 | } | |||
| 3576 | return; | |||
| 3577 | } | |||
| 3578 | if (UseAddressNop && VM_Version::is_amd_family()) { | |||
| 3579 | // | |||
| 3580 | // Using multi-bytes nops "0x0F 0x1F [address]" for AMD. | |||
| 3581 | // 1: 0x90 | |||
| 3582 | // 2: 0x66 0x90 | |||
| 3583 | // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding) | |||
| 3584 | // 4: 0x0F 0x1F 0x40 0x00 | |||
| 3585 | // 5: 0x0F 0x1F 0x44 0x00 0x00 | |||
| 3586 | // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00 | |||
| 3587 | // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |||
| 3588 | // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |||
| 3589 | // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |||
| 3590 | // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |||
| 3591 | // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |||
| 3592 | ||||
| 3593 | // The rest coding is AMD specific - use consecutive address nops | |||
| 3594 | ||||
| 3595 | // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00 | |||
| 3596 | // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00 | |||
| 3597 | // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |||
| 3598 | // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |||
| 3599 | // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |||
| 3600 | // Size prefixes (0x66) are added for larger sizes | |||
| 3601 | ||||
| 3602 | while(i >= 22) { | |||
| 3603 | i -= 11; | |||
| 3604 | emit_int24(0x66, 0x66, 0x66); | |||
| 3605 | addr_nop_8(); | |||
| 3606 | } | |||
| 3607 | // Generate first nop for size between 21-12 | |||
| 3608 | switch (i) { | |||
| 3609 | case 21: | |||
| 3610 | i -= 1; | |||
| 3611 | emit_int8(0x66); // size prefix | |||
| 3612 | case 20: | |||
| 3613 | case 19: | |||
| 3614 | i -= 1; | |||
| 3615 | emit_int8(0x66); // size prefix | |||
| 3616 | case 18: | |||
| 3617 | case 17: | |||
| 3618 | i -= 1; | |||
| 3619 | emit_int8(0x66); // size prefix | |||
| 3620 | case 16: | |||
| 3621 | case 15: | |||
| 3622 | i -= 8; | |||
| 3623 | addr_nop_8(); | |||
| 3624 | break; | |||
| 3625 | case 14: | |||
| 3626 | case 13: | |||
| 3627 | i -= 7; | |||
| 3628 | addr_nop_7(); | |||
| 3629 | break; | |||
| 3630 | case 12: | |||
| 3631 | i -= 6; | |||
| 3632 | emit_int8(0x66); // size prefix | |||
| 3633 | addr_nop_5(); | |||
| 3634 | break; | |||
| 3635 | default: | |||
| 3636 | assert(i < 12, " ")do { if (!(i < 12)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 3636, "assert(" "i < 12" ") failed", " "); ::breakpoint( ); } } while (0); | |||
| 3637 | } | |||
| 3638 | ||||
| 3639 | // Generate second nop for size between 11-1 | |||
| 3640 | switch (i) { | |||
| 3641 | case 11: | |||
| 3642 | emit_int8(0x66); // size prefix | |||
| 3643 | case 10: | |||
| 3644 | emit_int8(0x66); // size prefix | |||
| 3645 | case 9: | |||
| 3646 | emit_int8(0x66); // size prefix | |||
| 3647 | case 8: | |||
| 3648 | addr_nop_8(); | |||
| 3649 | break; | |||
| 3650 | case 7: | |||
| 3651 | addr_nop_7(); | |||
| 3652 | break; | |||
| 3653 | case 6: | |||
| 3654 | emit_int8(0x66); // size prefix | |||
| 3655 | case 5: | |||
| 3656 | addr_nop_5(); | |||
| 3657 | break; | |||
| 3658 | case 4: | |||
| 3659 | addr_nop_4(); | |||
| 3660 | break; | |||
| 3661 | case 3: | |||
| 3662 | // Don't use "0x0F 0x1F 0x00" - need patching safe padding | |||
| 3663 | emit_int8(0x66); // size prefix | |||
| 3664 | case 2: | |||
| 3665 | emit_int8(0x66); // size prefix | |||
| 3666 | case 1: | |||
| 3667 | emit_int8((unsigned char)0x90); | |||
| 3668 | // nop | |||
| 3669 | break; | |||
| 3670 | default: | |||
| 3671 | assert(i == 0, " ")do { if (!(i == 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 3671, "assert(" "i == 0" ") failed", " "); ::breakpoint(); } } while (0); | |||
| 3672 | } | |||
| 3673 | return; | |||
| 3674 | } | |||
| 3675 | ||||
| 3676 | if (UseAddressNop && VM_Version::is_zx()) { | |||
| 3677 | // | |||
| 3678 | // Using multi-bytes nops "0x0F 0x1F [address]" for ZX | |||
| 3679 | // 1: 0x90 | |||
| 3680 | // 2: 0x66 0x90 | |||
| 3681 | // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding) | |||
| 3682 | // 4: 0x0F 0x1F 0x40 0x00 | |||
| 3683 | // 5: 0x0F 0x1F 0x44 0x00 0x00 | |||
| 3684 | // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00 | |||
| 3685 | // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |||
| 3686 | // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |||
| 3687 | // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |||
| 3688 | // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |||
| 3689 | // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |||
| 3690 | ||||
| 3691 | // The rest coding is ZX specific - don't use consecutive address nops | |||
| 3692 | ||||
| 3693 | // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |||
| 3694 | // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |||
| 3695 | // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |||
| 3696 | // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |||
| 3697 | ||||
| 3698 | while (i >= 15) { | |||
| 3699 | // For ZX don't generate consecutive addess nops (mix with regular nops) | |||
| 3700 | i -= 15; | |||
| 3701 | emit_int24(0x66, 0x66, 0x66); | |||
| 3702 | addr_nop_8(); | |||
| 3703 | emit_int32(0x66, 0x66, 0x66, (unsigned char)0x90); | |||
| 3704 | } | |||
| 3705 | switch (i) { | |||
| 3706 | case 14: | |||
| 3707 | emit_int8(0x66); // size prefix | |||
| 3708 | case 13: | |||
| 3709 | emit_int8(0x66); // size prefix | |||
| 3710 | case 12: | |||
| 3711 | addr_nop_8(); | |||
| 3712 | emit_int32(0x66, 0x66, 0x66, (unsigned char)0x90); | |||
| 3713 | break; | |||
| 3714 | case 11: | |||
| 3715 | emit_int8(0x66); // size prefix | |||
| 3716 | case 10: | |||
| 3717 | emit_int8(0x66); // size prefix | |||
| 3718 | case 9: | |||
| 3719 | emit_int8(0x66); // size prefix | |||
| 3720 | case 8: | |||
| 3721 | addr_nop_8(); | |||
| 3722 | break; | |||
| 3723 | case 7: | |||
| 3724 | addr_nop_7(); | |||
| 3725 | break; | |||
| 3726 | case 6: | |||
| 3727 | emit_int8(0x66); // size prefix | |||
| 3728 | case 5: | |||
| 3729 | addr_nop_5(); | |||
| 3730 | break; | |||
| 3731 | case 4: | |||
| 3732 | addr_nop_4(); | |||
| 3733 | break; | |||
| 3734 | case 3: | |||
| 3735 | // Don't use "0x0F 0x1F 0x00" - need patching safe padding | |||
| 3736 | emit_int8(0x66); // size prefix | |||
| 3737 | case 2: | |||
| 3738 | emit_int8(0x66); // size prefix | |||
| 3739 | case 1: | |||
| 3740 | emit_int8((unsigned char)0x90); | |||
| 3741 | // nop | |||
| 3742 | break; | |||
| 3743 | default: | |||
| 3744 | assert(i == 0, " ")do { if (!(i == 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 3744, "assert(" "i == 0" ") failed", " "); ::breakpoint(); } } while (0); | |||
| 3745 | } | |||
| 3746 | return; | |||
| 3747 | } | |||
| 3748 | ||||
| 3749 | // Using nops with size prefixes "0x66 0x90". | |||
| 3750 | // From AMD Optimization Guide: | |||
| 3751 | // 1: 0x90 | |||
| 3752 | // 2: 0x66 0x90 | |||
| 3753 | // 3: 0x66 0x66 0x90 | |||
| 3754 | // 4: 0x66 0x66 0x66 0x90 | |||
| 3755 | // 5: 0x66 0x66 0x90 0x66 0x90 | |||
| 3756 | // 6: 0x66 0x66 0x90 0x66 0x66 0x90 | |||
| 3757 | // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 | |||
| 3758 | // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90 | |||
| 3759 | // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90 | |||
| 3760 | // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90 | |||
| 3761 | // | |||
| 3762 | while (i > 12) { | |||
| 3763 | i -= 4; | |||
| 3764 | emit_int32(0x66, 0x66, 0x66, (unsigned char)0x90); | |||
| 3765 | } | |||
| 3766 | // 1 - 12 nops | |||
| 3767 | if (i > 8) { | |||
| 3768 | if (i > 9) { | |||
| 3769 | i -= 1; | |||
| 3770 | emit_int8(0x66); | |||
| 3771 | } | |||
| 3772 | i -= 3; | |||
| 3773 | emit_int24(0x66, 0x66, (unsigned char)0x90); | |||
| 3774 | } | |||
| 3775 | // 1 - 8 nops | |||
| 3776 | if (i > 4) { | |||
| 3777 | if (i > 6) { | |||
| 3778 | i -= 1; | |||
| 3779 | emit_int8(0x66); | |||
| 3780 | } | |||
| 3781 | i -= 3; | |||
| 3782 | emit_int24(0x66, 0x66, (unsigned char)0x90); | |||
| 3783 | } | |||
| 3784 | switch (i) { | |||
| 3785 | case 4: | |||
| 3786 | emit_int8(0x66); | |||
| 3787 | case 3: | |||
| 3788 | emit_int8(0x66); | |||
| 3789 | case 2: | |||
| 3790 | emit_int8(0x66); | |||
| 3791 | case 1: | |||
| 3792 | emit_int8((unsigned char)0x90); | |||
| 3793 | break; | |||
| 3794 | default: | |||
| 3795 | assert(i == 0, " ")do { if (!(i == 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 3795, "assert(" "i == 0" ") failed", " "); ::breakpoint(); } } while (0); | |||
| 3796 | } | |||
| 3797 | } | |||
| 3798 | ||||
| 3799 | void Assembler::notl(Register dst) { | |||
| 3800 | int encode = prefix_and_encode(dst->encoding()); | |||
| 3801 | emit_int16((unsigned char)0xF7, (0xD0 | encode)); | |||
| 3802 | } | |||
| 3803 | ||||
| 3804 | void Assembler::orw(Register dst, Register src) { | |||
| 3805 | (void)prefix_and_encode(dst->encoding(), src->encoding()); | |||
| 3806 | emit_arith(0x0B, 0xC0, dst, src); | |||
| 3807 | } | |||
| 3808 | ||||
| 3809 | void Assembler::orl(Address dst, int32_t imm32) { | |||
| 3810 | InstructionMark im(this); | |||
| 3811 | prefix(dst); | |||
| 3812 | emit_arith_operand(0x81, rcx, dst, imm32); | |||
| 3813 | } | |||
| 3814 | ||||
| 3815 | void Assembler::orl(Register dst, int32_t imm32) { | |||
| 3816 | prefix(dst); | |||
| 3817 | emit_arith(0x81, 0xC8, dst, imm32); | |||
| 3818 | } | |||
| 3819 | ||||
| 3820 | void Assembler::orl(Register dst, Address src) { | |||
| 3821 | InstructionMark im(this); | |||
| 3822 | prefix(src, dst); | |||
| 3823 | emit_int8(0x0B); | |||
| 3824 | emit_operand(dst, src); | |||
| 3825 | } | |||
| 3826 | ||||
| 3827 | void Assembler::orl(Register dst, Register src) { | |||
| 3828 | (void) prefix_and_encode(dst->encoding(), src->encoding()); | |||
| 3829 | emit_arith(0x0B, 0xC0, dst, src); | |||
| 3830 | } | |||
| 3831 | ||||
| 3832 | void Assembler::orl(Address dst, Register src) { | |||
| 3833 | InstructionMark im(this); | |||
| 3834 | prefix(dst, src); | |||
| 3835 | emit_int8(0x09); | |||
| 3836 | emit_operand(src, dst); | |||
| 3837 | } | |||
| 3838 | ||||
| 3839 | void Assembler::orb(Address dst, int imm8) { | |||
| 3840 | InstructionMark im(this); | |||
| 3841 | prefix(dst); | |||
| 3842 | emit_int8((unsigned char)0x80); | |||
| 3843 | emit_operand(rcx, dst, 1); | |||
| 3844 | emit_int8(imm8); | |||
| 3845 | } | |||
| 3846 | ||||
| 3847 | void Assembler::orb(Address dst, Register src) { | |||
| 3848 | InstructionMark im(this); | |||
| 3849 | prefix(dst, src, true); | |||
| 3850 | emit_int8(0x08); | |||
| 3851 | emit_operand(src, dst); | |||
| 3852 | } | |||
| 3853 | ||||
| 3854 | void Assembler::packsswb(XMMRegister dst, XMMRegister src) { | |||
| 3855 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 3856 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 3857 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 3858 | emit_int16(0x63, (0xC0 | encode)); | |||
| 3859 | } | |||
| 3860 | ||||
| 3861 | void Assembler::vpacksswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 3862 | assert(UseAVX > 0, "some form of AVX must be enabled")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 3862, "assert(" "UseAVX > 0" ") failed", "some form of AVX must be enabled" ); ::breakpoint(); } } while (0); | |||
| 3863 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 3864 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 3865 | emit_int16(0x63, (0xC0 | encode)); | |||
| 3866 | } | |||
| 3867 | ||||
| 3868 | void Assembler::packssdw(XMMRegister dst, XMMRegister src) { | |||
| 3869 | assert(VM_Version::supports_sse2(), "")do { if (!(VM_Version::supports_sse2())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 3869, "assert(" "VM_Version::supports_sse2()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 3870 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 3871 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 3872 | emit_int16(0x6B, (0xC0 | encode)); | |||
| 3873 | } | |||
| 3874 | ||||
| 3875 | void Assembler::vpackssdw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 3876 | assert(UseAVX > 0, "some form of AVX must be enabled")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 3876, "assert(" "UseAVX > 0" ") failed", "some form of AVX must be enabled" ); ::breakpoint(); } } while (0); | |||
| 3877 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 3878 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 3879 | emit_int16(0x6B, (0xC0 | encode)); | |||
| 3880 | } | |||
| 3881 | ||||
| 3882 | void Assembler::packuswb(XMMRegister dst, Address src) { | |||
| 3883 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 3884 | assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes")do { if (!((UseAVX > 0))) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 3884, "assert(" "(UseAVX > 0)" ") failed", "SSE mode requires address alignment 16 bytes" ); ::breakpoint(); } } while (0); | |||
| 3885 | InstructionMark im(this); | |||
| 3886 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 3887 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); | |||
| 3888 | simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 3889 | emit_int8(0x67); | |||
| 3890 | emit_operand(dst, src); | |||
| 3891 | } | |||
| 3892 | ||||
| 3893 | void Assembler::packuswb(XMMRegister dst, XMMRegister src) { | |||
| 3894 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 3895 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 3896 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 3897 | emit_int16(0x67, (0xC0 | encode)); | |||
| 3898 | } | |||
| 3899 | ||||
| 3900 | void Assembler::vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 3901 | assert(UseAVX > 0, "some form of AVX must be enabled")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 3901, "assert(" "UseAVX > 0" ") failed", "some form of AVX must be enabled" ); ::breakpoint(); } } while (0); | |||
| 3902 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 3903 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 3904 | emit_int16(0x67, (0xC0 | encode)); | |||
| 3905 | } | |||
| 3906 | ||||
| 3907 | void Assembler::packusdw(XMMRegister dst, XMMRegister src) { | |||
| 3908 | assert(VM_Version::supports_sse4_1(), "")do { if (!(VM_Version::supports_sse4_1())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 3908, "assert(" "VM_Version::supports_sse4_1()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 3909 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 3910 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 3911 | emit_int16(0x2B, (0xC0 | encode)); | |||
| 3912 | } | |||
| 3913 | ||||
| 3914 | void Assembler::vpackusdw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 3915 | assert(UseAVX > 0, "some form of AVX must be enabled")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 3915, "assert(" "UseAVX > 0" ") failed", "some form of AVX must be enabled" ); ::breakpoint(); } } while (0); | |||
| 3916 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 3917 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 3918 | emit_int16(0x2B, (0xC0 | encode)); | |||
| 3919 | } | |||
| 3920 | ||||
| 3921 | void Assembler::vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len) { | |||
| 3922 | assert(VM_Version::supports_avx2(), "")do { if (!(VM_Version::supports_avx2())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 3922, "assert(" "VM_Version::supports_avx2()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 3923 | assert(vector_len != AVX_128bit, "")do { if (!(vector_len != AVX_128bit)) { (*g_assert_poison) = 'X' ;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 3923, "assert(" "vector_len != AVX_128bit" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 3924 | // VEX.256.66.0F3A.W1 00 /r ib | |||
| 3925 | InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 3926 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 3927 | emit_int24(0x00, (0xC0 | encode), imm8); | |||
| 3928 | } | |||
| 3929 | ||||
| 3930 | void Assembler::vpermq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 3931 | assert(vector_len == AVX_256bit ? VM_Version::supports_avx512vl() :do { if (!(vector_len == AVX_256bit ? VM_Version::supports_avx512vl () : vector_len == AVX_512bit ? VM_Version::supports_evex() : false)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 3932, "assert(" "vector_len == AVX_256bit ? VM_Version::supports_avx512vl() : vector_len == AVX_512bit ? VM_Version::supports_evex() : false" ") failed", "not supported"); ::breakpoint(); } } while (0) | |||
| 3932 | vector_len == AVX_512bit ? VM_Version::supports_evex() : false, "not supported")do { if (!(vector_len == AVX_256bit ? VM_Version::supports_avx512vl () : vector_len == AVX_512bit ? VM_Version::supports_evex() : false)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 3932, "assert(" "vector_len == AVX_256bit ? VM_Version::supports_avx512vl() : vector_len == AVX_512bit ? VM_Version::supports_evex() : false" ") failed", "not supported"); ::breakpoint(); } } while (0); | |||
| 3933 | InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 3934 | attributes.set_is_evex_instruction(); | |||
| 3935 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 3936 | emit_int16(0x36, (0xC0 | encode)); | |||
| 3937 | } | |||
| 3938 | ||||
| 3939 | void Assembler::vpermb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 3940 | assert(VM_Version::supports_avx512_vbmi(), "")do { if (!(VM_Version::supports_avx512_vbmi())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 3940, "assert(" "VM_Version::supports_avx512_vbmi()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 3941 | InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 3942 | attributes.set_is_evex_instruction(); | |||
| 3943 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 3944 | emit_int16((unsigned char)0x8D, (0xC0 | encode)); | |||
| 3945 | } | |||
| 3946 | ||||
| 3947 | void Assembler::vpermb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { | |||
| 3948 | assert(VM_Version::supports_avx512_vbmi(), "")do { if (!(VM_Version::supports_avx512_vbmi())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 3948, "assert(" "VM_Version::supports_avx512_vbmi()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 3949 | InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 3950 | attributes.set_is_evex_instruction(); | |||
| 3951 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 3952 | emit_int8((unsigned char)0x8D); | |||
| 3953 | emit_operand(dst, src); | |||
| 3954 | } | |||
| 3955 | ||||
| 3956 | void Assembler::vpermw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 3957 | assert(vector_len == AVX_128bit ? VM_Version::supports_avx512vlbw() :do { if (!(vector_len == AVX_128bit ? VM_Version::supports_avx512vlbw () : vector_len == AVX_256bit ? VM_Version::supports_avx512vlbw () : vector_len == AVX_512bit ? VM_Version::supports_avx512bw () : false)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 3959, "assert(" "vector_len == AVX_128bit ? VM_Version::supports_avx512vlbw() : vector_len == AVX_256bit ? VM_Version::supports_avx512vlbw() : vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : false" ") failed", "not supported"); ::breakpoint(); } } while (0) | |||
| 3958 | vector_len == AVX_256bit ? VM_Version::supports_avx512vlbw() :do { if (!(vector_len == AVX_128bit ? VM_Version::supports_avx512vlbw () : vector_len == AVX_256bit ? VM_Version::supports_avx512vlbw () : vector_len == AVX_512bit ? VM_Version::supports_avx512bw () : false)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 3959, "assert(" "vector_len == AVX_128bit ? VM_Version::supports_avx512vlbw() : vector_len == AVX_256bit ? VM_Version::supports_avx512vlbw() : vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : false" ") failed", "not supported"); ::breakpoint(); } } while (0) | |||
| 3959 | vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : false, "not supported")do { if (!(vector_len == AVX_128bit ? VM_Version::supports_avx512vlbw () : vector_len == AVX_256bit ? VM_Version::supports_avx512vlbw () : vector_len == AVX_512bit ? VM_Version::supports_avx512bw () : false)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 3959, "assert(" "vector_len == AVX_128bit ? VM_Version::supports_avx512vlbw() : vector_len == AVX_256bit ? VM_Version::supports_avx512vlbw() : vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : false" ") failed", "not supported"); ::breakpoint(); } } while (0); | |||
| 3960 | InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 3961 | attributes.set_is_evex_instruction(); | |||
| 3962 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 3963 | emit_int16((unsigned char)0x8D, (0xC0 | encode)); | |||
| 3964 | } | |||
| 3965 | ||||
| 3966 | void Assembler::vpermd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 3967 | assert(vector_len <= AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_evex(), "")do { if (!(vector_len <= AVX_256bit ? VM_Version::supports_avx2 () : VM_Version::supports_evex())) { (*g_assert_poison) = 'X' ;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 3967, "assert(" "vector_len <= AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_evex()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 3968 | // VEX.NDS.256.66.0F38.W0 36 /r | |||
| 3969 | InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 3970 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 3971 | emit_int16(0x36, (0xC0 | encode)); | |||
| 3972 | } | |||
| 3973 | ||||
| 3974 | void Assembler::vpermd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { | |||
| 3975 | assert(vector_len <= AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_evex(), "")do { if (!(vector_len <= AVX_256bit ? VM_Version::supports_avx2 () : VM_Version::supports_evex())) { (*g_assert_poison) = 'X' ;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 3975, "assert(" "vector_len <= AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_evex()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 3976 | // VEX.NDS.256.66.0F38.W0 36 /r | |||
| 3977 | InstructionMark im(this); | |||
| 3978 | InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 3979 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 3980 | emit_int8(0x36); | |||
| 3981 | emit_operand(dst, src); | |||
| 3982 | } | |||
| 3983 | ||||
| 3984 | void Assembler::vperm2i128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8) { | |||
| 3985 | assert(VM_Version::supports_avx2(), "")do { if (!(VM_Version::supports_avx2())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 3985, "assert(" "VM_Version::supports_avx2()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 3986 | InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 3987 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 3988 | emit_int24(0x46, (0xC0 | encode), imm8); | |||
| 3989 | } | |||
| 3990 | ||||
| 3991 | void Assembler::vperm2f128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8) { | |||
| 3992 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 3992, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 3993 | InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 3994 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 3995 | emit_int24(0x06, (0xC0 | encode), imm8); | |||
| 3996 | } | |||
| 3997 | ||||
| 3998 | void Assembler::vpermilps(XMMRegister dst, XMMRegister src, int imm8, int vector_len) { | |||
| 3999 | assert(vector_len <= AVX_256bit ? VM_Version::supports_avx() : VM_Version::supports_evex(), "")do { if (!(vector_len <= AVX_256bit ? VM_Version::supports_avx () : VM_Version::supports_evex())) { (*g_assert_poison) = 'X' ;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 3999, "assert(" "vector_len <= AVX_256bit ? VM_Version::supports_avx() : VM_Version::supports_evex()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 4000 | InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 4001 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 4002 | emit_int24(0x04, (0xC0 | encode), imm8); | |||
| 4003 | } | |||
| 4004 | ||||
| 4005 | void Assembler::vpermilpd(XMMRegister dst, XMMRegister src, int imm8, int vector_len) { | |||
| 4006 | assert(vector_len <= AVX_256bit ? VM_Version::supports_avx() : VM_Version::supports_evex(), "")do { if (!(vector_len <= AVX_256bit ? VM_Version::supports_avx () : VM_Version::supports_evex())) { (*g_assert_poison) = 'X' ;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4006, "assert(" "vector_len <= AVX_256bit ? VM_Version::supports_avx() : VM_Version::supports_evex()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 4007 | InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(),/* legacy_mode */ false,/* no_mask_reg */ true, /* uses_vl */ false); | |||
| 4008 | attributes.set_rex_vex_w_reverted(); | |||
| 4009 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 4010 | emit_int24(0x05, (0xC0 | encode), imm8); | |||
| 4011 | } | |||
| 4012 | ||||
| 4013 | void Assembler::vpermpd(XMMRegister dst, XMMRegister src, int imm8, int vector_len) { | |||
| 4014 | assert(vector_len <= AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_evex(), "")do { if (!(vector_len <= AVX_256bit ? VM_Version::supports_avx2 () : VM_Version::supports_evex())) { (*g_assert_poison) = 'X' ;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4014, "assert(" "vector_len <= AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_evex()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 4015 | InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 4016 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 4017 | emit_int24(0x01, (0xC0 | encode), imm8); | |||
| 4018 | } | |||
| 4019 | ||||
| 4020 | void Assembler::evpermi2q(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 4021 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4021, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 4022 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 4023 | attributes.set_is_evex_instruction(); | |||
| 4024 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 4025 | emit_int16(0x76, (0xC0 | encode)); | |||
| 4026 | } | |||
| 4027 | ||||
| 4028 | void Assembler::evpermt2b(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 4029 | assert(VM_Version::supports_avx512_vbmi(), "")do { if (!(VM_Version::supports_avx512_vbmi())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4029, "assert(" "VM_Version::supports_avx512_vbmi()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 4030 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 4031 | attributes.set_is_evex_instruction(); | |||
| 4032 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 4033 | emit_int16(0x7D, (0xC0 | encode)); | |||
| 4034 | } | |||
| 4035 | ||||
| 4036 | void Assembler::evpmultishiftqb(XMMRegister dst, XMMRegister ctl, XMMRegister src, int vector_len) { | |||
| 4037 | assert(VM_Version::supports_avx512_vbmi(), "")do { if (!(VM_Version::supports_avx512_vbmi())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4037, "assert(" "VM_Version::supports_avx512_vbmi()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 4038 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 4039 | attributes.set_is_evex_instruction(); | |||
| 4040 | int encode = vex_prefix_and_encode(dst->encoding(), ctl->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 4041 | emit_int16((unsigned char)0x83, (unsigned char)(0xC0 | encode)); | |||
| 4042 | } | |||
| 4043 | ||||
| 4044 | void Assembler::pause() { | |||
| 4045 | emit_int16((unsigned char)0xF3, (unsigned char)0x90); | |||
| 4046 | } | |||
| 4047 | ||||
| 4048 | void Assembler::ud2() { | |||
| 4049 | emit_int16(0x0F, 0x0B); | |||
| 4050 | } | |||
| 4051 | ||||
| 4052 | void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) { | |||
| 4053 | assert(VM_Version::supports_sse4_2(), "")do { if (!(VM_Version::supports_sse4_2())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4053, "assert(" "VM_Version::supports_sse4_2()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 4054 | InstructionMark im(this); | |||
| 4055 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 4056 | simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 4057 | emit_int8(0x61); | |||
| 4058 | emit_operand(dst, src); | |||
| 4059 | emit_int8(imm8); | |||
| 4060 | } | |||
| 4061 | ||||
| 4062 | void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) { | |||
| 4063 | assert(VM_Version::supports_sse4_2(), "")do { if (!(VM_Version::supports_sse4_2())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4063, "assert(" "VM_Version::supports_sse4_2()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 4064 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 4065 | int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 4066 | emit_int24(0x61, (0xC0 | encode), imm8); | |||
| 4067 | } | |||
| 4068 | ||||
| 4069 | // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst | |||
| 4070 | void Assembler::pcmpeqb(XMMRegister dst, XMMRegister src) { | |||
| 4071 | assert(VM_Version::supports_sse2(), "")do { if (!(VM_Version::supports_sse2())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4071, "assert(" "VM_Version::supports_sse2()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 4072 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 4073 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 4074 | emit_int16(0x74, (0xC0 | encode)); | |||
| 4075 | } | |||
| 4076 | ||||
| 4077 | void Assembler::vpcmpCCbwd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, int vector_len) { | |||
| 4078 | assert(vector_len == AVX_128bit ? VM_Version::supports_avx() : VM_Version::supports_avx2(), "")do { if (!(vector_len == AVX_128bit ? VM_Version::supports_avx () : VM_Version::supports_avx2())) { (*g_assert_poison) = 'X' ;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4078, "assert(" "vector_len == AVX_128bit ? VM_Version::supports_avx() : VM_Version::supports_avx2()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 4079 | assert(vector_len <= AVX_256bit, "evex encoding is different - has k register as dest")do { if (!(vector_len <= AVX_256bit)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4079, "assert(" "vector_len <= AVX_256bit" ") failed", "evex encoding is different - has k register as dest" ); ::breakpoint(); } } while (0); | |||
| 4080 | InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 4081 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 4082 | emit_int16(cond_encoding, (0xC0 | encode)); | |||
| 4083 | } | |||
| 4084 | ||||
| 4085 | // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst | |||
| 4086 | void Assembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 4087 | assert(vector_len == AVX_128bit ? VM_Version::supports_avx() : VM_Version::supports_avx2(), "")do { if (!(vector_len == AVX_128bit ? VM_Version::supports_avx () : VM_Version::supports_avx2())) { (*g_assert_poison) = 'X' ;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4087, "assert(" "vector_len == AVX_128bit ? VM_Version::supports_avx() : VM_Version::supports_avx2()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 4088 | assert(vector_len <= AVX_256bit, "evex encoding is different - has k register as dest")do { if (!(vector_len <= AVX_256bit)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4088, "assert(" "vector_len <= AVX_256bit" ") failed", "evex encoding is different - has k register as dest" ); ::breakpoint(); } } while (0); | |||
| 4089 | InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 4090 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 4091 | emit_int16(0x74, (0xC0 | encode)); | |||
| 4092 | } | |||
| 4093 | ||||
| 4094 | // In this context, kdst is written the mask used to process the equal components | |||
| 4095 | void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 4096 | assert(VM_Version::supports_avx512bw(), "")do { if (!(VM_Version::supports_avx512bw())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4096, "assert(" "VM_Version::supports_avx512bw()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 4097 | InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 4098 | attributes.set_is_evex_instruction(); | |||
| 4099 | int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 4100 | emit_int16(0x74, (0xC0 | encode)); | |||
| 4101 | } | |||
| 4102 | ||||
| 4103 | void Assembler::evpcmpgtb(KRegister kdst, XMMRegister nds, Address src, int vector_len) { | |||
| 4104 | assert(VM_Version::supports_avx512vlbw(), "")do { if (!(VM_Version::supports_avx512vlbw())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4104, "assert(" "VM_Version::supports_avx512vlbw()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 4105 | InstructionMark im(this); | |||
| 4106 | InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 4107 | attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); | |||
| 4108 | attributes.set_is_evex_instruction(); | |||
| 4109 | int dst_enc = kdst->encoding(); | |||
| 4110 | vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 4111 | emit_int8(0x64); | |||
| 4112 | emit_operand(as_Register(dst_enc), src); | |||
| 4113 | } | |||
| 4114 | ||||
| 4115 | void Assembler::evpcmpgtb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len) { | |||
| 4116 | assert(VM_Version::supports_avx512vlbw(), "")do { if (!(VM_Version::supports_avx512vlbw())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4116, "assert(" "VM_Version::supports_avx512vlbw()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 4117 | InstructionMark im(this); | |||
| 4118 | InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 4119 | attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); | |||
| 4120 | attributes.reset_is_clear_context(); | |||
| 4121 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 4122 | attributes.set_is_evex_instruction(); | |||
| 4123 | int dst_enc = kdst->encoding(); | |||
| 4124 | vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 4125 | emit_int8(0x64); | |||
| 4126 | emit_operand(as_Register(dst_enc), src); | |||
| 4127 | } | |||
| 4128 | ||||
| 4129 | void Assembler::evpcmpuw(KRegister kdst, XMMRegister nds, XMMRegister src, ComparisonPredicate vcc, int vector_len) { | |||
| 4130 | assert(VM_Version::supports_avx512vlbw(), "")do { if (!(VM_Version::supports_avx512vlbw())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4130, "assert(" "VM_Version::supports_avx512vlbw()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 4131 | InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 4132 | attributes.set_is_evex_instruction(); | |||
| 4133 | int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 4134 | emit_int24(0x3E, (0xC0 | encode), vcc); | |||
| 4135 | } | |||
| 4136 | ||||
| 4137 | void Assembler::evpcmpuw(KRegister kdst, XMMRegister nds, Address src, ComparisonPredicate vcc, int vector_len) { | |||
| 4138 | assert(VM_Version::supports_avx512vlbw(), "")do { if (!(VM_Version::supports_avx512vlbw())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4138, "assert(" "VM_Version::supports_avx512vlbw()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 4139 | InstructionMark im(this); | |||
| 4140 | InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 4141 | attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); | |||
| 4142 | attributes.set_is_evex_instruction(); | |||
| 4143 | int dst_enc = kdst->encoding(); | |||
| 4144 | vex_prefix(src, nds->encoding(), kdst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 4145 | emit_int8(0x3E); | |||
| 4146 | emit_operand(as_Register(dst_enc), src); | |||
| 4147 | emit_int8(vcc); | |||
| 4148 | } | |||
| 4149 | ||||
| 4150 | void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, Address src, int vector_len) { | |||
| 4151 | assert(VM_Version::supports_avx512bw(), "")do { if (!(VM_Version::supports_avx512bw())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4151, "assert(" "VM_Version::supports_avx512bw()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 4152 | InstructionMark im(this); | |||
| 4153 | InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 4154 | attributes.set_is_evex_instruction(); | |||
| 4155 | attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); | |||
| 4156 | int dst_enc = kdst->encoding(); | |||
| 4157 | vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 4158 | emit_int8(0x74); | |||
| 4159 | emit_operand(as_Register(dst_enc), src); | |||
| 4160 | } | |||
| 4161 | ||||
| 4162 | void Assembler::evpcmpeqb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len) { | |||
| 4163 | assert(VM_Version::supports_avx512vlbw(), "")do { if (!(VM_Version::supports_avx512vlbw())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4163, "assert(" "VM_Version::supports_avx512vlbw()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 4164 | InstructionMark im(this); | |||
| 4165 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 4166 | attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); | |||
| 4167 | attributes.reset_is_clear_context(); | |||
| 4168 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 4169 | attributes.set_is_evex_instruction(); | |||
| 4170 | vex_prefix(src, nds->encoding(), kdst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 4171 | emit_int8(0x74); | |||
| 4172 | emit_operand(as_Register(kdst->encoding()), src); | |||
| 4173 | } | |||
| 4174 | ||||
| 4175 | // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst | |||
| 4176 | void Assembler::pcmpeqw(XMMRegister dst, XMMRegister src) { | |||
| 4177 | assert(VM_Version::supports_sse2(), "")do { if (!(VM_Version::supports_sse2())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4177, "assert(" "VM_Version::supports_sse2()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 4178 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 4179 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 4180 | emit_int16(0x75, (0xC0 | encode)); | |||
| 4181 | } | |||
| 4182 | ||||
| 4183 | // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst | |||
| 4184 | void Assembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 4185 | assert(vector_len == AVX_128bit ? VM_Version::supports_avx() : VM_Version::supports_avx2(), "")do { if (!(vector_len == AVX_128bit ? VM_Version::supports_avx () : VM_Version::supports_avx2())) { (*g_assert_poison) = 'X' ;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4185, "assert(" "vector_len == AVX_128bit ? VM_Version::supports_avx() : VM_Version::supports_avx2()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 4186 | assert(vector_len <= AVX_256bit, "evex encoding is different - has k register as dest")do { if (!(vector_len <= AVX_256bit)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4186, "assert(" "vector_len <= AVX_256bit" ") failed", "evex encoding is different - has k register as dest" ); ::breakpoint(); } } while (0); | |||
| 4187 | InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 4188 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 4189 | emit_int16(0x75, (0xC0 | encode)); | |||
| 4190 | } | |||
| 4191 | ||||
| 4192 | // In this context, kdst is written the mask used to process the equal components | |||
| 4193 | void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 4194 | assert(VM_Version::supports_avx512bw(), "")do { if (!(VM_Version::supports_avx512bw())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4194, "assert(" "VM_Version::supports_avx512bw()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 4195 | InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 4196 | attributes.set_is_evex_instruction(); | |||
| 4197 | int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 4198 | emit_int16(0x75, (0xC0 | encode)); | |||
| 4199 | } | |||
| 4200 | ||||
| 4201 | void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, Address src, int vector_len) { | |||
| 4202 | assert(VM_Version::supports_avx512bw(), "")do { if (!(VM_Version::supports_avx512bw())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4202, "assert(" "VM_Version::supports_avx512bw()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 4203 | InstructionMark im(this); | |||
| 4204 | InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 4205 | attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); | |||
| 4206 | attributes.set_is_evex_instruction(); | |||
| 4207 | int dst_enc = kdst->encoding(); | |||
| 4208 | vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 4209 | emit_int8(0x75); | |||
| 4210 | emit_operand(as_Register(dst_enc), src); | |||
| 4211 | } | |||
| 4212 | ||||
| 4213 | // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst | |||
| 4214 | void Assembler::pcmpeqd(XMMRegister dst, XMMRegister src) { | |||
| 4215 | assert(VM_Version::supports_sse2(), "")do { if (!(VM_Version::supports_sse2())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4215, "assert(" "VM_Version::supports_sse2()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 4216 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 4217 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 4218 | emit_int16(0x76, (0xC0 | encode)); | |||
| 4219 | } | |||
| 4220 | ||||
| 4221 | // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst | |||
| 4222 | void Assembler::vpcmpeqd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 4223 | assert(vector_len == AVX_128bit ? VM_Version::supports_avx() : VM_Version::supports_avx2(), "")do { if (!(vector_len == AVX_128bit ? VM_Version::supports_avx () : VM_Version::supports_avx2())) { (*g_assert_poison) = 'X' ;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4223, "assert(" "vector_len == AVX_128bit ? VM_Version::supports_avx() : VM_Version::supports_avx2()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 4224 | assert(vector_len <= AVX_256bit, "evex encoding is different - has k register as dest")do { if (!(vector_len <= AVX_256bit)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4224, "assert(" "vector_len <= AVX_256bit" ") failed", "evex encoding is different - has k register as dest" ); ::breakpoint(); } } while (0); | |||
| 4225 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 4226 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 4227 | emit_int16(0x76, (0xC0 | encode)); | |||
| 4228 | } | |||
| 4229 | ||||
| 4230 | // In this context, kdst is written the mask used to process the equal components | |||
| 4231 | void Assembler::evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 4232 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4232, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 4233 | InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 4234 | attributes.set_is_evex_instruction(); | |||
| 4235 | attributes.reset_is_clear_context(); | |||
| 4236 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 4237 | int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 4238 | emit_int16(0x76, (0xC0 | encode)); | |||
| 4239 | } | |||
| 4240 | ||||
| 4241 | void Assembler::evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len) { | |||
| 4242 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4242, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 4243 | InstructionMark im(this); | |||
| 4244 | InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 4245 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); | |||
| 4246 | attributes.set_is_evex_instruction(); | |||
| 4247 | attributes.reset_is_clear_context(); | |||
| 4248 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 4249 | int dst_enc = kdst->encoding(); | |||
| 4250 | vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 4251 | emit_int8(0x76); | |||
| 4252 | emit_operand(as_Register(dst_enc), src); | |||
| 4253 | } | |||
| 4254 | ||||
| 4255 | // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst | |||
| 4256 | void Assembler::pcmpeqq(XMMRegister dst, XMMRegister src) { | |||
| 4257 | assert(VM_Version::supports_sse4_1(), "")do { if (!(VM_Version::supports_sse4_1())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4257, "assert(" "VM_Version::supports_sse4_1()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 4258 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 4259 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 4260 | emit_int16(0x29, (0xC0 | encode)); | |||
| 4261 | } | |||
| 4262 | ||||
| 4263 | void Assembler::vpcmpCCq(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, int vector_len) { | |||
| 4264 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4264, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 4265 | InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 4266 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 4267 | emit_int16(cond_encoding, (0xC0 | encode)); | |||
| 4268 | } | |||
| 4269 | ||||
| 4270 | // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst | |||
| 4271 | void Assembler::vpcmpeqq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 4272 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4272, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 4273 | InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 4274 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 4275 | emit_int16(0x29, (0xC0 | encode)); | |||
| 4276 | } | |||
| 4277 | ||||
| 4278 | // In this context, kdst is written the mask used to process the equal components | |||
| 4279 | void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 4280 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4280, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 4281 | InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 4282 | attributes.reset_is_clear_context(); | |||
| 4283 | attributes.set_is_evex_instruction(); | |||
| 4284 | int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 4285 | emit_int16(0x29, (0xC0 | encode)); | |||
| 4286 | } | |||
| 4287 | ||||
| 4288 | // In this context, kdst is written the mask used to process the equal components | |||
| 4289 | void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, Address src, int vector_len) { | |||
| 4290 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4290, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 4291 | InstructionMark im(this); | |||
| 4292 | InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 4293 | attributes.reset_is_clear_context(); | |||
| 4294 | attributes.set_is_evex_instruction(); | |||
| 4295 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); | |||
| 4296 | int dst_enc = kdst->encoding(); | |||
| 4297 | vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 4298 | emit_int8(0x29); | |||
| 4299 | emit_operand(as_Register(dst_enc), src); | |||
| 4300 | } | |||
| 4301 | ||||
| 4302 | void Assembler::pcmpgtq(XMMRegister dst, XMMRegister src) { | |||
| 4303 | assert(VM_Version::supports_sse4_1(), "")do { if (!(VM_Version::supports_sse4_1())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4303, "assert(" "VM_Version::supports_sse4_1()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 4304 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 4305 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 4306 | emit_int16(0x37, (0xC0 | encode)); | |||
| 4307 | } | |||
| 4308 | ||||
| 4309 | void Assembler::pmovmskb(Register dst, XMMRegister src) { | |||
| 4310 | assert(VM_Version::supports_sse2(), "")do { if (!(VM_Version::supports_sse2())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4310, "assert(" "VM_Version::supports_sse2()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 4311 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 4312 | int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 4313 | emit_int16((unsigned char)0xD7, (0xC0 | encode)); | |||
| 4314 | } | |||
| 4315 | ||||
| 4316 | void Assembler::vpmovmskb(Register dst, XMMRegister src, int vec_enc) { | |||
| 4317 | assert((VM_Version::supports_avx() && vec_enc == AVX_128bit) ||do { if (!((VM_Version::supports_avx() && vec_enc == AVX_128bit ) || (VM_Version::supports_avx2() && vec_enc == AVX_256bit ))) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4318, "assert(" "(VM_Version::supports_avx() && vec_enc == AVX_128bit) || (VM_Version::supports_avx2() && vec_enc == AVX_256bit)" ") failed", ""); ::breakpoint(); } } while (0) | |||
| 4318 | (VM_Version::supports_avx2() && vec_enc == AVX_256bit), "")do { if (!((VM_Version::supports_avx() && vec_enc == AVX_128bit ) || (VM_Version::supports_avx2() && vec_enc == AVX_256bit ))) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4318, "assert(" "(VM_Version::supports_avx() && vec_enc == AVX_128bit) || (VM_Version::supports_avx2() && vec_enc == AVX_256bit)" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 4319 | InstructionAttr attributes(vec_enc, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 4320 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 4321 | emit_int16((unsigned char)0xD7, (0xC0 | encode)); | |||
| 4322 | } | |||
| 4323 | ||||
| 4324 | void Assembler::vmovmskps(Register dst, XMMRegister src, int vec_enc) { | |||
| 4325 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4325, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 4326 | InstructionAttr attributes(vec_enc, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 4327 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 4328 | emit_int16(0x50, (0xC0 | encode)); | |||
| 4329 | } | |||
| 4330 | ||||
| 4331 | void Assembler::vmovmskpd(Register dst, XMMRegister src, int vec_enc) { | |||
| 4332 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4332, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 4333 | InstructionAttr attributes(vec_enc, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 4334 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 4335 | emit_int16(0x50, (0xC0 | encode)); | |||
| 4336 | } | |||
| 4337 | ||||
| 4338 | void Assembler::vpmaskmovd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { | |||
| 4339 | assert((VM_Version::supports_avx2() && vector_len == AVX_256bit), "")do { if (!((VM_Version::supports_avx2() && vector_len == AVX_256bit))) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4339, "assert(" "(VM_Version::supports_avx2() && vector_len == AVX_256bit)" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 4340 | InstructionMark im(this); | |||
| 4341 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 4342 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 4343 | emit_int8((unsigned char)0x8C); | |||
| 4344 | emit_operand(dst, src); | |||
| 4345 | } | |||
| 4346 | ||||
| 4347 | void Assembler::pextrd(Register dst, XMMRegister src, int imm8) { | |||
| 4348 | assert(VM_Version::supports_sse4_1(), "")do { if (!(VM_Version::supports_sse4_1())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4348, "assert(" "VM_Version::supports_sse4_1()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 4349 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 4350 | int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 4351 | emit_int24(0x16, (0xC0 | encode), imm8); | |||
| 4352 | } | |||
| 4353 | ||||
| 4354 | void Assembler::pextrd(Address dst, XMMRegister src, int imm8) { | |||
| 4355 | assert(VM_Version::supports_sse4_1(), "")do { if (!(VM_Version::supports_sse4_1())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4355, "assert(" "VM_Version::supports_sse4_1()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 4356 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 4357 | attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); | |||
| 4358 | simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 4359 | emit_int8(0x16); | |||
| 4360 | emit_operand(src, dst); | |||
| 4361 | emit_int8(imm8); | |||
| 4362 | } | |||
| 4363 | ||||
| 4364 | void Assembler::pextrq(Register dst, XMMRegister src, int imm8) { | |||
| 4365 | assert(VM_Version::supports_sse4_1(), "")do { if (!(VM_Version::supports_sse4_1())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4365, "assert(" "VM_Version::supports_sse4_1()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 4366 | InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 4367 | int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 4368 | emit_int24(0x16, (0xC0 | encode), imm8); | |||
| 4369 | } | |||
| 4370 | ||||
| 4371 | void Assembler::pextrq(Address dst, XMMRegister src, int imm8) { | |||
| 4372 | assert(VM_Version::supports_sse4_1(), "")do { if (!(VM_Version::supports_sse4_1())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4372, "assert(" "VM_Version::supports_sse4_1()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 4373 | InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 4374 | attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); | |||
| 4375 | simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 4376 | emit_int8(0x16); | |||
| 4377 | emit_operand(src, dst); | |||
| 4378 | emit_int8(imm8); | |||
| 4379 | } | |||
| 4380 | ||||
| 4381 | void Assembler::pextrw(Register dst, XMMRegister src, int imm8) { | |||
| 4382 | assert(VM_Version::supports_sse2(), "")do { if (!(VM_Version::supports_sse2())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4382, "assert(" "VM_Version::supports_sse2()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 4383 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 4384 | int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 4385 | emit_int24((unsigned char)0xC5, (0xC0 | encode), imm8); | |||
| 4386 | } | |||
| 4387 | ||||
| 4388 | void Assembler::pextrw(Address dst, XMMRegister src, int imm8) { | |||
| 4389 | assert(VM_Version::supports_sse4_1(), "")do { if (!(VM_Version::supports_sse4_1())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4389, "assert(" "VM_Version::supports_sse4_1()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 4390 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 4391 | attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit); | |||
| 4392 | simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 4393 | emit_int8(0x15); | |||
| 4394 | emit_operand(src, dst); | |||
| 4395 | emit_int8(imm8); | |||
| 4396 | } | |||
| 4397 | ||||
| 4398 | void Assembler::pextrb(Register dst, XMMRegister src, int imm8) { | |||
| 4399 | assert(VM_Version::supports_sse4_1(), "")do { if (!(VM_Version::supports_sse4_1())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4399, "assert(" "VM_Version::supports_sse4_1()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 4400 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 4401 | int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 4402 | emit_int24(0x14, (0xC0 | encode), imm8); | |||
| 4403 | } | |||
| 4404 | ||||
| 4405 | void Assembler::pextrb(Address dst, XMMRegister src, int imm8) { | |||
| 4406 | assert(VM_Version::supports_sse4_1(), "")do { if (!(VM_Version::supports_sse4_1())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4406, "assert(" "VM_Version::supports_sse4_1()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 4407 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 4408 | attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit); | |||
| 4409 | simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 4410 | emit_int8(0x14); | |||
| 4411 | emit_operand(src, dst); | |||
| 4412 | emit_int8(imm8); | |||
| 4413 | } | |||
| 4414 | ||||
| 4415 | void Assembler::pinsrd(XMMRegister dst, Register src, int imm8) { | |||
| 4416 | assert(VM_Version::supports_sse4_1(), "")do { if (!(VM_Version::supports_sse4_1())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4416, "assert(" "VM_Version::supports_sse4_1()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 4417 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 4418 | int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 4419 | emit_int24(0x22, (0xC0 | encode), imm8); | |||
| 4420 | } | |||
| 4421 | ||||
| 4422 | void Assembler::pinsrd(XMMRegister dst, Address src, int imm8) { | |||
| 4423 | assert(VM_Version::supports_sse4_1(), "")do { if (!(VM_Version::supports_sse4_1())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4423, "assert(" "VM_Version::supports_sse4_1()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 4424 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 4425 | attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); | |||
| 4426 | simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 4427 | emit_int8(0x22); | |||
| 4428 | emit_operand(dst,src); | |||
| 4429 | emit_int8(imm8); | |||
| 4430 | } | |||
| 4431 | ||||
| 4432 | void Assembler::vpinsrd(XMMRegister dst, XMMRegister nds, Register src, int imm8) { | |||
| 4433 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4433, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 4434 | InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 4435 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 4436 | emit_int24(0x22, (0xC0 | encode), imm8); | |||
| 4437 | } | |||
| 4438 | ||||
| 4439 | void Assembler::pinsrq(XMMRegister dst, Register src, int imm8) { | |||
| 4440 | assert(VM_Version::supports_sse4_1(), "")do { if (!(VM_Version::supports_sse4_1())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4440, "assert(" "VM_Version::supports_sse4_1()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 4441 | InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 4442 | int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 4443 | emit_int24(0x22, (0xC0 | encode), imm8); | |||
| 4444 | } | |||
| 4445 | ||||
| 4446 | void Assembler::pinsrq(XMMRegister dst, Address src, int imm8) { | |||
| 4447 | assert(VM_Version::supports_sse4_1(), "")do { if (!(VM_Version::supports_sse4_1())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4447, "assert(" "VM_Version::supports_sse4_1()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 4448 | InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 4449 | attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); | |||
| 4450 | simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 4451 | emit_int8(0x22); | |||
| 4452 | emit_operand(dst, src); | |||
| 4453 | emit_int8(imm8); | |||
| 4454 | } | |||
| 4455 | ||||
| 4456 | void Assembler::vpinsrq(XMMRegister dst, XMMRegister nds, Register src, int imm8) { | |||
| 4457 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4457, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 4458 | InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 4459 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 4460 | emit_int24(0x22, (0xC0 | encode), imm8); | |||
| 4461 | } | |||
| 4462 | ||||
| 4463 | void Assembler::pinsrw(XMMRegister dst, Register src, int imm8) { | |||
| 4464 | assert(VM_Version::supports_sse2(), "")do { if (!(VM_Version::supports_sse2())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4464, "assert(" "VM_Version::supports_sse2()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 4465 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 4466 | int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 4467 | emit_int24((unsigned char)0xC4, (0xC0 | encode), imm8); | |||
| 4468 | } | |||
| 4469 | ||||
| 4470 | void Assembler::pinsrw(XMMRegister dst, Address src, int imm8) { | |||
| 4471 | assert(VM_Version::supports_sse2(), "")do { if (!(VM_Version::supports_sse2())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4471, "assert(" "VM_Version::supports_sse2()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 4472 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 4473 | attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit); | |||
| 4474 | simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 4475 | emit_int8((unsigned char)0xC4); | |||
| 4476 | emit_operand(dst, src); | |||
| 4477 | emit_int8(imm8); | |||
| 4478 | } | |||
| 4479 | ||||
| 4480 | void Assembler::vpinsrw(XMMRegister dst, XMMRegister nds, Register src, int imm8) { | |||
| 4481 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4481, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 4482 | InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 4483 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 4484 | emit_int24((unsigned char)0xC4, (0xC0 | encode), imm8); | |||
| 4485 | } | |||
| 4486 | ||||
| 4487 | void Assembler::pinsrb(XMMRegister dst, Address src, int imm8) { | |||
| 4488 | assert(VM_Version::supports_sse4_1(), "")do { if (!(VM_Version::supports_sse4_1())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4488, "assert(" "VM_Version::supports_sse4_1()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 4489 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 4490 | attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit); | |||
| 4491 | simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 4492 | emit_int8(0x20); | |||
| 4493 | emit_operand(dst, src); | |||
| 4494 | emit_int8(imm8); | |||
| 4495 | } | |||
| 4496 | ||||
| 4497 | void Assembler::pinsrb(XMMRegister dst, Register src, int imm8) { | |||
| 4498 | assert(VM_Version::supports_sse4_1(), "")do { if (!(VM_Version::supports_sse4_1())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4498, "assert(" "VM_Version::supports_sse4_1()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 4499 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 4500 | int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 4501 | emit_int24(0x20, (0xC0 | encode), imm8); | |||
| 4502 | } | |||
| 4503 | ||||
| 4504 | void Assembler::vpinsrb(XMMRegister dst, XMMRegister nds, Register src, int imm8) { | |||
| 4505 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4505, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 4506 | InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 4507 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 4508 | emit_int24(0x20, (0xC0 | encode), imm8); | |||
| 4509 | } | |||
| 4510 | ||||
| 4511 | void Assembler::insertps(XMMRegister dst, XMMRegister src, int imm8) { | |||
| 4512 | assert(VM_Version::supports_sse4_1(), "")do { if (!(VM_Version::supports_sse4_1())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4512, "assert(" "VM_Version::supports_sse4_1()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 4513 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 4514 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 4515 | emit_int24(0x21, (0xC0 | encode), imm8); | |||
| 4516 | } | |||
| 4517 | ||||
| 4518 | void Assembler::vinsertps(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8) { | |||
| 4519 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4519, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 4520 | InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 4521 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 4522 | emit_int24(0x21, (0xC0 | encode), imm8); | |||
| 4523 | } | |||
| 4524 | ||||
| 4525 | void Assembler::pmovzxbw(XMMRegister dst, Address src) { | |||
| 4526 | assert(VM_Version::supports_sse4_1(), "")do { if (!(VM_Version::supports_sse4_1())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4526, "assert(" "VM_Version::supports_sse4_1()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 4527 | InstructionMark im(this); | |||
| 4528 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 4529 | attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit); | |||
| 4530 | simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 4531 | emit_int8(0x30); | |||
| 4532 | emit_operand(dst, src); | |||
| 4533 | } | |||
| 4534 | ||||
| 4535 | void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) { | |||
| 4536 | assert(VM_Version::supports_sse4_1(), "")do { if (!(VM_Version::supports_sse4_1())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4536, "assert(" "VM_Version::supports_sse4_1()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 4537 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 4538 | int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 4539 | emit_int16(0x30, (0xC0 | encode)); | |||
| 4540 | } | |||
| 4541 | ||||
| 4542 | void Assembler::pmovsxbw(XMMRegister dst, XMMRegister src) { | |||
| 4543 | assert(VM_Version::supports_sse4_1(), "")do { if (!(VM_Version::supports_sse4_1())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4543, "assert(" "VM_Version::supports_sse4_1()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 4544 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 4545 | int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 4546 | emit_int16(0x20, (0xC0 | encode)); | |||
| 4547 | } | |||
| 4548 | ||||
| 4549 | void Assembler::pmovzxdq(XMMRegister dst, XMMRegister src) { | |||
| 4550 | assert(VM_Version::supports_sse4_1(), "")do { if (!(VM_Version::supports_sse4_1())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4550, "assert(" "VM_Version::supports_sse4_1()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 4551 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 4552 | int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 4553 | emit_int16(0x35, (0xC0 | encode)); | |||
| 4554 | } | |||
| 4555 | ||||
| 4556 | void Assembler::pmovsxbd(XMMRegister dst, XMMRegister src) { | |||
| 4557 | assert(VM_Version::supports_sse4_1(), "")do { if (!(VM_Version::supports_sse4_1())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4557, "assert(" "VM_Version::supports_sse4_1()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 4558 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 4559 | int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 4560 | emit_int16(0x21, (0xC0 | encode)); | |||
| 4561 | } | |||
| 4562 | ||||
| 4563 | void Assembler::pmovzxbd(XMMRegister dst, XMMRegister src) { | |||
| 4564 | assert(VM_Version::supports_sse4_1(), "")do { if (!(VM_Version::supports_sse4_1())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4564, "assert(" "VM_Version::supports_sse4_1()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 4565 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 4566 | int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 4567 | emit_int16(0x31, (0xC0 | encode)); | |||
| 4568 | } | |||
| 4569 | ||||
| 4570 | void Assembler::pmovsxbq(XMMRegister dst, XMMRegister src) { | |||
| 4571 | assert(VM_Version::supports_sse4_1(), "")do { if (!(VM_Version::supports_sse4_1())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4571, "assert(" "VM_Version::supports_sse4_1()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 4572 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 4573 | int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 4574 | emit_int16(0x22, (0xC0 | encode)); | |||
| 4575 | } | |||
| 4576 | ||||
| 4577 | void Assembler::pmovsxwd(XMMRegister dst, XMMRegister src) { | |||
| 4578 | assert(VM_Version::supports_sse4_1(), "")do { if (!(VM_Version::supports_sse4_1())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4578, "assert(" "VM_Version::supports_sse4_1()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 4579 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 4580 | int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 4581 | emit_int16(0x23, (0xC0 | encode)); | |||
| 4582 | } | |||
| 4583 | ||||
| 4584 | void Assembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) { | |||
| 4585 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4585, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 4586 | InstructionMark im(this); | |||
| 4587 | assert(dst != xnoreg, "sanity")do { if (!(dst != xnoreg)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4587, "assert(" "dst != xnoreg" ") failed", "sanity"); ::breakpoint (); } } while (0); | |||
| 4588 | InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 4589 | attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit); | |||
| 4590 | vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 4591 | emit_int8(0x30); | |||
| 4592 | emit_operand(dst, src); | |||
| 4593 | } | |||
| 4594 | ||||
| 4595 | void Assembler::vpmovzxbw(XMMRegister dst, XMMRegister src, int vector_len) { | |||
| 4596 | assert(vector_len == AVX_128bit? VM_Version::supports_avx() :do { if (!(vector_len == AVX_128bit? VM_Version::supports_avx () : vector_len == AVX_256bit? VM_Version::supports_avx2() : vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0)) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4598, "assert(" "vector_len == AVX_128bit? VM_Version::supports_avx() : vector_len == AVX_256bit? VM_Version::supports_avx2() : vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0" ") failed", ""); ::breakpoint(); } } while (0) | |||
| 4597 | vector_len == AVX_256bit? VM_Version::supports_avx2() :do { if (!(vector_len == AVX_128bit? VM_Version::supports_avx () : vector_len == AVX_256bit? VM_Version::supports_avx2() : vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0)) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4598, "assert(" "vector_len == AVX_128bit? VM_Version::supports_avx() : vector_len == AVX_256bit? VM_Version::supports_avx2() : vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0" ") failed", ""); ::breakpoint(); } } while (0) | |||
| 4598 | vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0, "")do { if (!(vector_len == AVX_128bit? VM_Version::supports_avx () : vector_len == AVX_256bit? VM_Version::supports_avx2() : vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0)) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4598, "assert(" "vector_len == AVX_128bit? VM_Version::supports_avx() : vector_len == AVX_256bit? VM_Version::supports_avx2() : vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 4599 | InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 4600 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 4601 | emit_int16(0x30, (unsigned char) (0xC0 | encode)); | |||
| 4602 | } | |||
| 4603 | ||||
| 4604 | void Assembler::vpmovsxbw(XMMRegister dst, XMMRegister src, int vector_len) { | |||
| 4605 | assert(vector_len == AVX_128bit? VM_Version::supports_avx() :do { if (!(vector_len == AVX_128bit? VM_Version::supports_avx () : vector_len == AVX_256bit? VM_Version::supports_avx2() : vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0)) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4607, "assert(" "vector_len == AVX_128bit? VM_Version::supports_avx() : vector_len == AVX_256bit? VM_Version::supports_avx2() : vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0" ") failed", ""); ::breakpoint(); } } while (0) | |||
| 4606 | vector_len == AVX_256bit? VM_Version::supports_avx2() :do { if (!(vector_len == AVX_128bit? VM_Version::supports_avx () : vector_len == AVX_256bit? VM_Version::supports_avx2() : vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0)) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4607, "assert(" "vector_len == AVX_128bit? VM_Version::supports_avx() : vector_len == AVX_256bit? VM_Version::supports_avx2() : vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0" ") failed", ""); ::breakpoint(); } } while (0) | |||
| 4607 | vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0, "")do { if (!(vector_len == AVX_128bit? VM_Version::supports_avx () : vector_len == AVX_256bit? VM_Version::supports_avx2() : vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0)) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4607, "assert(" "vector_len == AVX_128bit? VM_Version::supports_avx() : vector_len == AVX_256bit? VM_Version::supports_avx2() : vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 4608 | InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 4609 | int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 4610 | emit_int16(0x20, (0xC0 | encode)); | |||
| 4611 | } | |||
| 4612 | ||||
| 4613 | void Assembler::evpmovzxbw(XMMRegister dst, KRegister mask, Address src, int vector_len) { | |||
| 4614 | assert(VM_Version::supports_avx512vlbw(), "")do { if (!(VM_Version::supports_avx512vlbw())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4614, "assert(" "VM_Version::supports_avx512vlbw()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 4615 | assert(dst != xnoreg, "sanity")do { if (!(dst != xnoreg)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4615, "assert(" "dst != xnoreg" ") failed", "sanity"); ::breakpoint (); } } while (0); | |||
| 4616 | InstructionMark im(this); | |||
| 4617 | InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 4618 | attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit); | |||
| 4619 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 4620 | attributes.set_is_evex_instruction(); | |||
| 4621 | vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 4622 | emit_int8(0x30); | |||
| 4623 | emit_operand(dst, src); | |||
| 4624 | } | |||
| 4625 | ||||
| 4626 | void Assembler::evpandd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 4627 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4627, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 4628 | // Encoding: EVEX.NDS.XXX.66.0F.W0 DB /r | |||
| 4629 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 4630 | attributes.set_is_evex_instruction(); | |||
| 4631 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 4632 | if (merge) { | |||
| 4633 | attributes.reset_is_clear_context(); | |||
| 4634 | } | |||
| 4635 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 4636 | emit_int16((unsigned char)0xDB, (0xC0 | encode)); | |||
| 4637 | } | |||
| 4638 | ||||
| 4639 | void Assembler::vpmovzxdq(XMMRegister dst, XMMRegister src, int vector_len) { | |||
| 4640 | assert(vector_len > AVX_128bit ? VM_Version::supports_avx2() : VM_Version::supports_avx(), "")do { if (!(vector_len > AVX_128bit ? VM_Version::supports_avx2 () : VM_Version::supports_avx())) { (*g_assert_poison) = 'X'; ; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4640, "assert(" "vector_len > AVX_128bit ? VM_Version::supports_avx2() : VM_Version::supports_avx()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 4641 | InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 4642 | int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 4643 | emit_int16(0x35, (0xC0 | encode)); | |||
| 4644 | } | |||
| 4645 | ||||
| 4646 | void Assembler::vpmovzxbd(XMMRegister dst, XMMRegister src, int vector_len) { | |||
| 4647 | assert(vector_len > AVX_128bit ? VM_Version::supports_avx2() : VM_Version::supports_avx(), "")do { if (!(vector_len > AVX_128bit ? VM_Version::supports_avx2 () : VM_Version::supports_avx())) { (*g_assert_poison) = 'X'; ; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4647, "assert(" "vector_len > AVX_128bit ? VM_Version::supports_avx2() : VM_Version::supports_avx()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 4648 | InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 4649 | int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 4650 | emit_int16(0x31, (0xC0 | encode)); | |||
| 4651 | } | |||
| 4652 | ||||
| 4653 | void Assembler::vpmovzxbq(XMMRegister dst, XMMRegister src, int vector_len) { | |||
| 4654 | assert(vector_len > AVX_128bit ? VM_Version::supports_avx2() : VM_Version::supports_avx(), "")do { if (!(vector_len > AVX_128bit ? VM_Version::supports_avx2 () : VM_Version::supports_avx())) { (*g_assert_poison) = 'X'; ; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4654, "assert(" "vector_len > AVX_128bit ? VM_Version::supports_avx2() : VM_Version::supports_avx()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 4655 | InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 4656 | int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 4657 | emit_int16(0x32, (0xC0 | encode)); | |||
| 4658 | } | |||
| 4659 | ||||
| 4660 | void Assembler::vpmovsxbd(XMMRegister dst, XMMRegister src, int vector_len) { | |||
| 4661 | assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :do { if (!(vector_len == AVX_128bit ? VM_Version::supports_avx () : vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4663, "assert(" "vector_len == AVX_128bit ? VM_Version::supports_avx() : vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_evex()" ") failed", ""); ::breakpoint(); } } while (0) | |||
| 4662 | vector_len == AVX_256bit ? VM_Version::supports_avx2() :do { if (!(vector_len == AVX_128bit ? VM_Version::supports_avx () : vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4663, "assert(" "vector_len == AVX_128bit ? VM_Version::supports_avx() : vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_evex()" ") failed", ""); ::breakpoint(); } } while (0) | |||
| 4663 | VM_Version::supports_evex(), "")do { if (!(vector_len == AVX_128bit ? VM_Version::supports_avx () : vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4663, "assert(" "vector_len == AVX_128bit ? VM_Version::supports_avx() : vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_evex()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 4664 | InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 4665 | int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 4666 | emit_int16(0x21, (0xC0 | encode)); | |||
| 4667 | } | |||
| 4668 | ||||
| 4669 | void Assembler::vpmovsxbq(XMMRegister dst, XMMRegister src, int vector_len) { | |||
| 4670 | assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :do { if (!(vector_len == AVX_128bit ? VM_Version::supports_avx () : vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4672, "assert(" "vector_len == AVX_128bit ? VM_Version::supports_avx() : vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_evex()" ") failed", ""); ::breakpoint(); } } while (0) | |||
| 4671 | vector_len == AVX_256bit ? VM_Version::supports_avx2() :do { if (!(vector_len == AVX_128bit ? VM_Version::supports_avx () : vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4672, "assert(" "vector_len == AVX_128bit ? VM_Version::supports_avx() : vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_evex()" ") failed", ""); ::breakpoint(); } } while (0) | |||
| 4672 | VM_Version::supports_evex(), "")do { if (!(vector_len == AVX_128bit ? VM_Version::supports_avx () : vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4672, "assert(" "vector_len == AVX_128bit ? VM_Version::supports_avx() : vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_evex()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 4673 | InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 4674 | int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 4675 | emit_int16(0x22, (0xC0 | encode)); | |||
| 4676 | } | |||
| 4677 | ||||
| 4678 | void Assembler::vpmovsxwd(XMMRegister dst, XMMRegister src, int vector_len) { | |||
| 4679 | assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :do { if (!(vector_len == AVX_128bit ? VM_Version::supports_avx () : vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4681, "assert(" "vector_len == AVX_128bit ? VM_Version::supports_avx() : vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_evex()" ") failed", ""); ::breakpoint(); } } while (0) | |||
| 4680 | vector_len == AVX_256bit ? VM_Version::supports_avx2() :do { if (!(vector_len == AVX_128bit ? VM_Version::supports_avx () : vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4681, "assert(" "vector_len == AVX_128bit ? VM_Version::supports_avx() : vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_evex()" ") failed", ""); ::breakpoint(); } } while (0) | |||
| 4681 | VM_Version::supports_evex(), "")do { if (!(vector_len == AVX_128bit ? VM_Version::supports_avx () : vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4681, "assert(" "vector_len == AVX_128bit ? VM_Version::supports_avx() : vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_evex()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 4682 | InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 4683 | int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 4684 | emit_int16(0x23, (0xC0 | encode)); | |||
| 4685 | } | |||
| 4686 | ||||
| 4687 | void Assembler::vpmovsxwq(XMMRegister dst, XMMRegister src, int vector_len) { | |||
| 4688 | assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :do { if (!(vector_len == AVX_128bit ? VM_Version::supports_avx () : vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4690, "assert(" "vector_len == AVX_128bit ? VM_Version::supports_avx() : vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_evex()" ") failed", ""); ::breakpoint(); } } while (0) | |||
| 4689 | vector_len == AVX_256bit ? VM_Version::supports_avx2() :do { if (!(vector_len == AVX_128bit ? VM_Version::supports_avx () : vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4690, "assert(" "vector_len == AVX_128bit ? VM_Version::supports_avx() : vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_evex()" ") failed", ""); ::breakpoint(); } } while (0) | |||
| 4690 | VM_Version::supports_evex(), "")do { if (!(vector_len == AVX_128bit ? VM_Version::supports_avx () : vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4690, "assert(" "vector_len == AVX_128bit ? VM_Version::supports_avx() : vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_evex()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 4691 | InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 4692 | int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 4693 | emit_int16(0x24, (0xC0 | encode)); | |||
| 4694 | } | |||
| 4695 | ||||
| 4696 | void Assembler::vpmovsxdq(XMMRegister dst, XMMRegister src, int vector_len) { | |||
| 4697 | assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :do { if (!(vector_len == AVX_128bit ? VM_Version::supports_avx () : vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4699, "assert(" "vector_len == AVX_128bit ? VM_Version::supports_avx() : vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_evex()" ") failed", ""); ::breakpoint(); } } while (0) | |||
| 4698 | vector_len == AVX_256bit ? VM_Version::supports_avx2() :do { if (!(vector_len == AVX_128bit ? VM_Version::supports_avx () : vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4699, "assert(" "vector_len == AVX_128bit ? VM_Version::supports_avx() : vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_evex()" ") failed", ""); ::breakpoint(); } } while (0) | |||
| 4699 | VM_Version::supports_evex(), "")do { if (!(vector_len == AVX_128bit ? VM_Version::supports_avx () : vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4699, "assert(" "vector_len == AVX_128bit ? VM_Version::supports_avx() : vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_evex()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 4700 | InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 4701 | int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 4702 | emit_int16(0x25, (0xC0 | encode)); | |||
| 4703 | } | |||
| 4704 | ||||
| 4705 | void Assembler::evpmovwb(Address dst, XMMRegister src, int vector_len) { | |||
| 4706 | assert(VM_Version::supports_avx512vlbw(), "")do { if (!(VM_Version::supports_avx512vlbw())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4706, "assert(" "VM_Version::supports_avx512vlbw()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 4707 | assert(src != xnoreg, "sanity")do { if (!(src != xnoreg)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4707, "assert(" "src != xnoreg" ") failed", "sanity"); ::breakpoint (); } } while (0); | |||
| 4708 | InstructionMark im(this); | |||
| 4709 | InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 4710 | attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit); | |||
| 4711 | attributes.set_is_evex_instruction(); | |||
| 4712 | vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes); | |||
| 4713 | emit_int8(0x30); | |||
| 4714 | emit_operand(src, dst); | |||
| 4715 | } | |||
| 4716 | ||||
| 4717 | void Assembler::evpmovwb(Address dst, KRegister mask, XMMRegister src, int vector_len) { | |||
| 4718 | assert(VM_Version::supports_avx512vlbw(), "")do { if (!(VM_Version::supports_avx512vlbw())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4718, "assert(" "VM_Version::supports_avx512vlbw()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 4719 | assert(src != xnoreg, "sanity")do { if (!(src != xnoreg)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4719, "assert(" "src != xnoreg" ") failed", "sanity"); ::breakpoint (); } } while (0); | |||
| 4720 | InstructionMark im(this); | |||
| 4721 | InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 4722 | attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit); | |||
| 4723 | attributes.reset_is_clear_context(); | |||
| 4724 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 4725 | attributes.set_is_evex_instruction(); | |||
| 4726 | vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes); | |||
| 4727 | emit_int8(0x30); | |||
| 4728 | emit_operand(src, dst); | |||
| 4729 | } | |||
| 4730 | ||||
| 4731 | void Assembler::evpmovdb(Address dst, XMMRegister src, int vector_len) { | |||
| 4732 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4732, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 4733 | assert(src != xnoreg, "sanity")do { if (!(src != xnoreg)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4733, "assert(" "src != xnoreg" ") failed", "sanity"); ::breakpoint (); } } while (0); | |||
| 4734 | InstructionMark im(this); | |||
| 4735 | InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 4736 | attributes.set_address_attributes(/* tuple_type */ EVEX_QVM, /* input_size_in_bits */ EVEX_NObit); | |||
| 4737 | attributes.set_is_evex_instruction(); | |||
| 4738 | vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes); | |||
| 4739 | emit_int8(0x31); | |||
| 4740 | emit_operand(src, dst); | |||
| 4741 | } | |||
| 4742 | ||||
| 4743 | void Assembler::vpmovzxwd(XMMRegister dst, XMMRegister src, int vector_len) { | |||
| 4744 | assert(vector_len == AVX_128bit? VM_Version::supports_avx() :do { if (!(vector_len == AVX_128bit? VM_Version::supports_avx () : vector_len == AVX_256bit? VM_Version::supports_avx2() : vector_len == AVX_512bit? VM_Version::supports_evex() : 0)) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4746, "assert(" "vector_len == AVX_128bit? VM_Version::supports_avx() : vector_len == AVX_256bit? VM_Version::supports_avx2() : vector_len == AVX_512bit? VM_Version::supports_evex() : 0" ") failed", " "); ::breakpoint(); } } while (0) | |||
| 4745 | vector_len == AVX_256bit? VM_Version::supports_avx2() :do { if (!(vector_len == AVX_128bit? VM_Version::supports_avx () : vector_len == AVX_256bit? VM_Version::supports_avx2() : vector_len == AVX_512bit? VM_Version::supports_evex() : 0)) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4746, "assert(" "vector_len == AVX_128bit? VM_Version::supports_avx() : vector_len == AVX_256bit? VM_Version::supports_avx2() : vector_len == AVX_512bit? VM_Version::supports_evex() : 0" ") failed", " "); ::breakpoint(); } } while (0) | |||
| 4746 | vector_len == AVX_512bit? VM_Version::supports_evex() : 0, " ")do { if (!(vector_len == AVX_128bit? VM_Version::supports_avx () : vector_len == AVX_256bit? VM_Version::supports_avx2() : vector_len == AVX_512bit? VM_Version::supports_evex() : 0)) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4746, "assert(" "vector_len == AVX_128bit? VM_Version::supports_avx() : vector_len == AVX_256bit? VM_Version::supports_avx2() : vector_len == AVX_512bit? VM_Version::supports_evex() : 0" ") failed", " "); ::breakpoint(); } } while (0); | |||
| 4747 | InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 4748 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 4749 | emit_int16(0x33, (0xC0 | encode)); | |||
| 4750 | } | |||
| 4751 | ||||
| 4752 | void Assembler::pmaddwd(XMMRegister dst, XMMRegister src) { | |||
| 4753 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 4754 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 4755 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 4756 | emit_int16((unsigned char)0xF5, (0xC0 | encode)); | |||
| 4757 | } | |||
| 4758 | ||||
| 4759 | void Assembler::vpmaddwd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 4760 | assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :do { if (!(vector_len == AVX_128bit ? VM_Version::supports_avx () : (vector_len == AVX_256bit ? VM_Version::supports_avx2() : (vector_len == AVX_512bit ? VM_Version::supports_evex() : 0) ))) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4762, "assert(" "vector_len == AVX_128bit ? VM_Version::supports_avx() : (vector_len == AVX_256bit ? VM_Version::supports_avx2() : (vector_len == AVX_512bit ? VM_Version::supports_evex() : 0))" ") failed", ""); ::breakpoint(); } } while (0) | |||
| 4761 | (vector_len == AVX_256bit ? VM_Version::supports_avx2() :do { if (!(vector_len == AVX_128bit ? VM_Version::supports_avx () : (vector_len == AVX_256bit ? VM_Version::supports_avx2() : (vector_len == AVX_512bit ? VM_Version::supports_evex() : 0) ))) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4762, "assert(" "vector_len == AVX_128bit ? VM_Version::supports_avx() : (vector_len == AVX_256bit ? VM_Version::supports_avx2() : (vector_len == AVX_512bit ? VM_Version::supports_evex() : 0))" ") failed", ""); ::breakpoint(); } } while (0) | |||
| 4762 | (vector_len == AVX_512bit ? VM_Version::supports_evex() : 0)), "")do { if (!(vector_len == AVX_128bit ? VM_Version::supports_avx () : (vector_len == AVX_256bit ? VM_Version::supports_avx2() : (vector_len == AVX_512bit ? VM_Version::supports_evex() : 0) ))) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4762, "assert(" "vector_len == AVX_128bit ? VM_Version::supports_avx() : (vector_len == AVX_256bit ? VM_Version::supports_avx2() : (vector_len == AVX_512bit ? VM_Version::supports_evex() : 0))" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 4763 | InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 4764 | int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 4765 | emit_int16((unsigned char)0xF5, (0xC0 | encode)); | |||
| 4766 | } | |||
| 4767 | ||||
| 4768 | void Assembler::vpmaddubsw(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len) { | |||
| 4769 | assert(vector_len == AVX_128bit? VM_Version::supports_avx() :do { if (!(vector_len == AVX_128bit? VM_Version::supports_avx () : vector_len == AVX_256bit? VM_Version::supports_avx2() : vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0)) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4771, "assert(" "vector_len == AVX_128bit? VM_Version::supports_avx() : vector_len == AVX_256bit? VM_Version::supports_avx2() : vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0" ") failed", ""); ::breakpoint(); } } while (0) | |||
| 4770 | vector_len == AVX_256bit? VM_Version::supports_avx2() :do { if (!(vector_len == AVX_128bit? VM_Version::supports_avx () : vector_len == AVX_256bit? VM_Version::supports_avx2() : vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0)) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4771, "assert(" "vector_len == AVX_128bit? VM_Version::supports_avx() : vector_len == AVX_256bit? VM_Version::supports_avx2() : vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0" ") failed", ""); ::breakpoint(); } } while (0) | |||
| 4771 | vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0, "")do { if (!(vector_len == AVX_128bit? VM_Version::supports_avx () : vector_len == AVX_256bit? VM_Version::supports_avx2() : vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0)) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4771, "assert(" "vector_len == AVX_128bit? VM_Version::supports_avx() : vector_len == AVX_256bit? VM_Version::supports_avx2() : vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 4772 | InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 4773 | int encode = simd_prefix_and_encode(dst, src1, src2, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 4774 | emit_int16(0x04, (0xC0 | encode)); | |||
| 4775 | } | |||
| 4776 | ||||
| 4777 | void Assembler::evpdpwssd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 4778 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4778, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 4779 | assert(VM_Version::supports_avx512_vnni(), "must support vnni")do { if (!(VM_Version::supports_avx512_vnni())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4779, "assert(" "VM_Version::supports_avx512_vnni()" ") failed" , "must support vnni"); ::breakpoint(); } } while (0); | |||
| 4780 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 4781 | attributes.set_is_evex_instruction(); | |||
| 4782 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 4783 | emit_int16(0x52, (0xC0 | encode)); | |||
| 4784 | } | |||
| 4785 | ||||
| 4786 | // generic | |||
| 4787 | void Assembler::pop(Register dst) { | |||
| 4788 | int encode = prefix_and_encode(dst->encoding()); | |||
| 4789 | emit_int8(0x58 | encode); | |||
| 4790 | } | |||
| 4791 | ||||
| 4792 | void Assembler::popcntl(Register dst, Address src) { | |||
| 4793 | assert(VM_Version::supports_popcnt(), "must support")do { if (!(VM_Version::supports_popcnt())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4793, "assert(" "VM_Version::supports_popcnt()" ") failed", "must support"); ::breakpoint(); } } while (0); | |||
| 4794 | InstructionMark im(this); | |||
| 4795 | emit_int8((unsigned char)0xF3); | |||
| 4796 | prefix(src, dst); | |||
| 4797 | emit_int16(0x0F, (unsigned char)0xB8); | |||
| 4798 | emit_operand(dst, src); | |||
| 4799 | } | |||
| 4800 | ||||
| 4801 | void Assembler::popcntl(Register dst, Register src) { | |||
| 4802 | assert(VM_Version::supports_popcnt(), "must support")do { if (!(VM_Version::supports_popcnt())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4802, "assert(" "VM_Version::supports_popcnt()" ") failed", "must support"); ::breakpoint(); } } while (0); | |||
| 4803 | emit_int8((unsigned char)0xF3); | |||
| 4804 | int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |||
| 4805 | emit_int24(0x0F, (unsigned char)0xB8, (0xC0 | encode)); | |||
| 4806 | } | |||
| 4807 | ||||
| 4808 | void Assembler::vpopcntd(XMMRegister dst, XMMRegister src, int vector_len) { | |||
| 4809 | assert(VM_Version::supports_avx512_vpopcntdq(), "must support vpopcntdq feature")do { if (!(VM_Version::supports_avx512_vpopcntdq())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4809, "assert(" "VM_Version::supports_avx512_vpopcntdq()" ") failed" , "must support vpopcntdq feature"); ::breakpoint(); } } while (0); | |||
| 4810 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 4811 | attributes.set_is_evex_instruction(); | |||
| 4812 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 4813 | emit_int16(0x55, (0xC0 | encode)); | |||
| 4814 | } | |||
| 4815 | ||||
| 4816 | void Assembler::popf() { | |||
| 4817 | emit_int8((unsigned char)0x9D); | |||
| 4818 | } | |||
| 4819 | ||||
| 4820 | #ifndef _LP641 // no 32bit push/pop on amd64 | |||
| 4821 | void Assembler::popl(Address dst) { | |||
| 4822 | // NOTE: this will adjust stack by 8byte on 64bits | |||
| 4823 | InstructionMark im(this); | |||
| 4824 | prefix(dst); | |||
| 4825 | emit_int8((unsigned char)0x8F); | |||
| 4826 | emit_operand(rax, dst); | |||
| 4827 | } | |||
| 4828 | #endif | |||
| 4829 | ||||
| 4830 | void Assembler::prefetchnta(Address src) { | |||
| 4831 | NOT_LP64(assert(VM_Version::supports_sse(), "must support")); | |||
| 4832 | InstructionMark im(this); | |||
| 4833 | prefix(src); | |||
| 4834 | emit_int16(0x0F, 0x18); | |||
| 4835 | emit_operand(rax, src); // 0, src | |||
| 4836 | } | |||
| 4837 | ||||
| 4838 | void Assembler::prefetchr(Address src) { | |||
| 4839 | assert(VM_Version::supports_3dnow_prefetch(), "must support")do { if (!(VM_Version::supports_3dnow_prefetch())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4839, "assert(" "VM_Version::supports_3dnow_prefetch()" ") failed" , "must support"); ::breakpoint(); } } while (0); | |||
| 4840 | InstructionMark im(this); | |||
| 4841 | prefix(src); | |||
| 4842 | emit_int16(0x0F, 0x0D); | |||
| 4843 | emit_operand(rax, src); // 0, src | |||
| 4844 | } | |||
| 4845 | ||||
| 4846 | void Assembler::prefetcht0(Address src) { | |||
| 4847 | NOT_LP64(assert(VM_Version::supports_sse(), "must support")); | |||
| 4848 | InstructionMark im(this); | |||
| 4849 | prefix(src); | |||
| 4850 | emit_int16(0x0F, 0x18); | |||
| 4851 | emit_operand(rcx, src); // 1, src | |||
| 4852 | } | |||
| 4853 | ||||
| 4854 | void Assembler::prefetcht1(Address src) { | |||
| 4855 | NOT_LP64(assert(VM_Version::supports_sse(), "must support")); | |||
| 4856 | InstructionMark im(this); | |||
| 4857 | prefix(src); | |||
| 4858 | emit_int16(0x0F, 0x18); | |||
| 4859 | emit_operand(rdx, src); // 2, src | |||
| 4860 | } | |||
| 4861 | ||||
| 4862 | void Assembler::prefetcht2(Address src) { | |||
| 4863 | NOT_LP64(assert(VM_Version::supports_sse(), "must support")); | |||
| 4864 | InstructionMark im(this); | |||
| 4865 | prefix(src); | |||
| 4866 | emit_int16(0x0F, 0x18); | |||
| 4867 | emit_operand(rbx, src); // 3, src | |||
| 4868 | } | |||
| 4869 | ||||
| 4870 | void Assembler::prefetchw(Address src) { | |||
| 4871 | assert(VM_Version::supports_3dnow_prefetch(), "must support")do { if (!(VM_Version::supports_3dnow_prefetch())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4871, "assert(" "VM_Version::supports_3dnow_prefetch()" ") failed" , "must support"); ::breakpoint(); } } while (0); | |||
| 4872 | InstructionMark im(this); | |||
| 4873 | prefix(src); | |||
| 4874 | emit_int16(0x0F, 0x0D); | |||
| 4875 | emit_operand(rcx, src); // 1, src | |||
| 4876 | } | |||
| 4877 | ||||
| 4878 | void Assembler::prefix(Prefix p) { | |||
| 4879 | emit_int8(p); | |||
| 4880 | } | |||
| 4881 | ||||
| 4882 | void Assembler::pshufb(XMMRegister dst, XMMRegister src) { | |||
| 4883 | assert(VM_Version::supports_ssse3(), "")do { if (!(VM_Version::supports_ssse3())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4883, "assert(" "VM_Version::supports_ssse3()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 4884 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 4885 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 4886 | emit_int16(0x00, (0xC0 | encode)); | |||
| 4887 | } | |||
| 4888 | ||||
| 4889 | void Assembler::vpshufb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 4890 | assert(vector_len == AVX_128bit? VM_Version::supports_avx() :do { if (!(vector_len == AVX_128bit? VM_Version::supports_avx () : vector_len == AVX_256bit? VM_Version::supports_avx2() : vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0)) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4892, "assert(" "vector_len == AVX_128bit? VM_Version::supports_avx() : vector_len == AVX_256bit? VM_Version::supports_avx2() : vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0" ") failed", ""); ::breakpoint(); } } while (0) | |||
| 4891 | vector_len == AVX_256bit? VM_Version::supports_avx2() :do { if (!(vector_len == AVX_128bit? VM_Version::supports_avx () : vector_len == AVX_256bit? VM_Version::supports_avx2() : vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0)) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4892, "assert(" "vector_len == AVX_128bit? VM_Version::supports_avx() : vector_len == AVX_256bit? VM_Version::supports_avx2() : vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0" ") failed", ""); ::breakpoint(); } } while (0) | |||
| 4892 | vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0, "")do { if (!(vector_len == AVX_128bit? VM_Version::supports_avx () : vector_len == AVX_256bit? VM_Version::supports_avx2() : vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0)) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4892, "assert(" "vector_len == AVX_128bit? VM_Version::supports_avx() : vector_len == AVX_256bit? VM_Version::supports_avx2() : vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 4893 | InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 4894 | int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 4895 | emit_int16(0x00, (0xC0 | encode)); | |||
| 4896 | } | |||
| 4897 | ||||
| 4898 | void Assembler::pshufb(XMMRegister dst, Address src) { | |||
| 4899 | assert(VM_Version::supports_ssse3(), "")do { if (!(VM_Version::supports_ssse3())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4899, "assert(" "VM_Version::supports_ssse3()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 4900 | InstructionMark im(this); | |||
| 4901 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 4902 | attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); | |||
| 4903 | simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 4904 | emit_int8(0x00); | |||
| 4905 | emit_operand(dst, src); | |||
| 4906 | } | |||
| 4907 | ||||
| 4908 | void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) { | |||
| 4909 | assert(isByte(mode), "invalid value")do { if (!(isByte(mode))) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4909, "assert(" "isByte(mode)" ") failed", "invalid value") ; ::breakpoint(); } } while (0); | |||
| 4910 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 4911 | int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit; | |||
| 4912 | InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 4913 | int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 4914 | emit_int24(0x70, (0xC0 | encode), mode & 0xFF); | |||
| 4915 | } | |||
| 4916 | ||||
| 4917 | void Assembler::vpshufd(XMMRegister dst, XMMRegister src, int mode, int vector_len) { | |||
| 4918 | assert(vector_len == AVX_128bit? VM_Version::supports_avx() :do { if (!(vector_len == AVX_128bit? VM_Version::supports_avx () : (vector_len == AVX_256bit? VM_Version::supports_avx2() : (vector_len == AVX_512bit? VM_Version::supports_evex() : 0)) )) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4920, "assert(" "vector_len == AVX_128bit? VM_Version::supports_avx() : (vector_len == AVX_256bit? VM_Version::supports_avx2() : (vector_len == AVX_512bit? VM_Version::supports_evex() : 0))" ") failed", ""); ::breakpoint(); } } while (0) | |||
| 4919 | (vector_len == AVX_256bit? VM_Version::supports_avx2() :do { if (!(vector_len == AVX_128bit? VM_Version::supports_avx () : (vector_len == AVX_256bit? VM_Version::supports_avx2() : (vector_len == AVX_512bit? VM_Version::supports_evex() : 0)) )) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4920, "assert(" "vector_len == AVX_128bit? VM_Version::supports_avx() : (vector_len == AVX_256bit? VM_Version::supports_avx2() : (vector_len == AVX_512bit? VM_Version::supports_evex() : 0))" ") failed", ""); ::breakpoint(); } } while (0) | |||
| 4920 | (vector_len == AVX_512bit? VM_Version::supports_evex() : 0)), "")do { if (!(vector_len == AVX_128bit? VM_Version::supports_avx () : (vector_len == AVX_256bit? VM_Version::supports_avx2() : (vector_len == AVX_512bit? VM_Version::supports_evex() : 0)) )) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4920, "assert(" "vector_len == AVX_128bit? VM_Version::supports_avx() : (vector_len == AVX_256bit? VM_Version::supports_avx2() : (vector_len == AVX_512bit? VM_Version::supports_evex() : 0))" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 4921 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 4922 | InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 4923 | int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 4924 | emit_int24(0x70, (0xC0 | encode), mode & 0xFF); | |||
| 4925 | } | |||
| 4926 | ||||
| 4927 | void Assembler::pshufd(XMMRegister dst, Address src, int mode) { | |||
| 4928 | assert(isByte(mode), "invalid value")do { if (!(isByte(mode))) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4928, "assert(" "isByte(mode)" ") failed", "invalid value") ; ::breakpoint(); } } while (0); | |||
| 4929 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 4930 | assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes")do { if (!((UseAVX > 0))) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4930, "assert(" "(UseAVX > 0)" ") failed", "SSE mode requires address alignment 16 bytes" ); ::breakpoint(); } } while (0); | |||
| 4931 | InstructionMark im(this); | |||
| 4932 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 4933 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); | |||
| 4934 | simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 4935 | emit_int8(0x70); | |||
| 4936 | emit_operand(dst, src); | |||
| 4937 | emit_int8(mode & 0xFF); | |||
| 4938 | } | |||
| 4939 | ||||
| 4940 | void Assembler::pshufhw(XMMRegister dst, XMMRegister src, int mode) { | |||
| 4941 | assert(isByte(mode), "invalid value")do { if (!(isByte(mode))) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4941, "assert(" "isByte(mode)" ") failed", "invalid value") ; ::breakpoint(); } } while (0); | |||
| 4942 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 4943 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 4944 | int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); | |||
| 4945 | emit_int24(0x70, (0xC0 | encode), mode & 0xFF); | |||
| 4946 | } | |||
| 4947 | ||||
| 4948 | void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) { | |||
| 4949 | assert(isByte(mode), "invalid value")do { if (!(isByte(mode))) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4949, "assert(" "isByte(mode)" ") failed", "invalid value") ; ::breakpoint(); } } while (0); | |||
| 4950 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 4951 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 4952 | int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); | |||
| 4953 | emit_int24(0x70, (0xC0 | encode), mode & 0xFF); | |||
| 4954 | } | |||
| 4955 | ||||
| 4956 | void Assembler::pshuflw(XMMRegister dst, Address src, int mode) { | |||
| 4957 | assert(isByte(mode), "invalid value")do { if (!(isByte(mode))) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4957, "assert(" "isByte(mode)" ") failed", "invalid value") ; ::breakpoint(); } } while (0); | |||
| 4958 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 4959 | assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes")do { if (!((UseAVX > 0))) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4959, "assert(" "(UseAVX > 0)" ") failed", "SSE mode requires address alignment 16 bytes" ); ::breakpoint(); } } while (0); | |||
| 4960 | InstructionMark im(this); | |||
| 4961 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 4962 | attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); | |||
| 4963 | simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); | |||
| 4964 | emit_int8(0x70); | |||
| 4965 | emit_operand(dst, src); | |||
| 4966 | emit_int8(mode & 0xFF); | |||
| 4967 | } | |||
| 4968 | ||||
| 4969 | void Assembler::evshufi64x2(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) { | |||
| 4970 | assert(VM_Version::supports_evex(), "requires EVEX support")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4970, "assert(" "VM_Version::supports_evex()" ") failed", "requires EVEX support" ); ::breakpoint(); } } while (0); | |||
| 4971 | assert(vector_len == Assembler::AVX_256bit || vector_len == Assembler::AVX_512bit, "")do { if (!(vector_len == Assembler::AVX_256bit || vector_len == Assembler::AVX_512bit)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4971, "assert(" "vector_len == Assembler::AVX_256bit || vector_len == Assembler::AVX_512bit" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 4972 | InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 4973 | attributes.set_is_evex_instruction(); | |||
| 4974 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 4975 | emit_int24(0x43, (0xC0 | encode), imm8 & 0xFF); | |||
| 4976 | } | |||
| 4977 | ||||
| 4978 | void Assembler::pshufpd(XMMRegister dst, XMMRegister src, int imm8) { | |||
| 4979 | assert(isByte(imm8), "invalid value")do { if (!(isByte(imm8))) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4979, "assert(" "isByte(imm8)" ") failed", "invalid value") ; ::breakpoint(); } } while (0); | |||
| 4980 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 4981 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 4982 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 4983 | emit_int24((unsigned char)0xC6, (0xC0 | encode), imm8 & 0xFF); | |||
| 4984 | } | |||
| 4985 | ||||
| 4986 | void Assembler::vpshufpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) { | |||
| 4987 | InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 4988 | attributes.set_rex_vex_w_reverted(); | |||
| 4989 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 4990 | emit_int24((unsigned char)0xC6, (0xC0 | encode), imm8 & 0xFF); | |||
| 4991 | } | |||
| 4992 | ||||
| 4993 | void Assembler::pshufps(XMMRegister dst, XMMRegister src, int imm8) { | |||
| 4994 | assert(isByte(imm8), "invalid value")do { if (!(isByte(imm8))) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 4994, "assert(" "isByte(imm8)" ") failed", "invalid value") ; ::breakpoint(); } } while (0); | |||
| 4995 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 4996 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 4997 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 4998 | emit_int24((unsigned char)0xC6, (0xC0 | encode), imm8 & 0xFF); | |||
| 4999 | } | |||
| 5000 | ||||
| 5001 | void Assembler::vpshufps(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) { | |||
| 5002 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 5003 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 5004 | emit_int24((unsigned char)0xC6, (0xC0 | encode), imm8 & 0xFF); | |||
| 5005 | } | |||
| 5006 | ||||
| 5007 | void Assembler::psrldq(XMMRegister dst, int shift) { | |||
| 5008 | // Shift left 128 bit value in dst XMMRegister by shift number of bytes. | |||
| 5009 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 5010 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 5011 | int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 5012 | emit_int24(0x73, (0xC0 | encode), shift); | |||
| 5013 | } | |||
| 5014 | ||||
| 5015 | void Assembler::vpsrldq(XMMRegister dst, XMMRegister src, int shift, int vector_len) { | |||
| 5016 | assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :do { if (!(vector_len == AVX_128bit ? VM_Version::supports_avx () : vector_len == AVX_256bit ? VM_Version::supports_avx2() : vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : 0)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 5018, "assert(" "vector_len == AVX_128bit ? VM_Version::supports_avx() : vector_len == AVX_256bit ? VM_Version::supports_avx2() : vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : 0" ") failed", ""); ::breakpoint(); } } while (0) | |||
| 5017 | vector_len == AVX_256bit ? VM_Version::supports_avx2() :do { if (!(vector_len == AVX_128bit ? VM_Version::supports_avx () : vector_len == AVX_256bit ? VM_Version::supports_avx2() : vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : 0)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 5018, "assert(" "vector_len == AVX_128bit ? VM_Version::supports_avx() : vector_len == AVX_256bit ? VM_Version::supports_avx2() : vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : 0" ") failed", ""); ::breakpoint(); } } while (0) | |||
| 5018 | vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : 0, "")do { if (!(vector_len == AVX_128bit ? VM_Version::supports_avx () : vector_len == AVX_256bit ? VM_Version::supports_avx2() : vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : 0)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 5018, "assert(" "vector_len == AVX_128bit ? VM_Version::supports_avx() : vector_len == AVX_256bit ? VM_Version::supports_avx2() : vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : 0" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 5019 | InstructionAttr attributes(vector_len, /*vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 5020 | int encode = vex_prefix_and_encode(xmm3->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 5021 | emit_int24(0x73, (0xC0 | encode), shift & 0xFF); | |||
| 5022 | } | |||
| 5023 | ||||
| 5024 | void Assembler::pslldq(XMMRegister dst, int shift) { | |||
| 5025 | // Shift left 128 bit value in dst XMMRegister by shift number of bytes. | |||
| 5026 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 5027 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 5028 | // XMM7 is for /7 encoding: 66 0F 73 /7 ib | |||
| 5029 | int encode = simd_prefix_and_encode(xmm7, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 5030 | emit_int24(0x73, (0xC0 | encode), shift); | |||
| 5031 | } | |||
| 5032 | ||||
| 5033 | void Assembler::vpslldq(XMMRegister dst, XMMRegister src, int shift, int vector_len) { | |||
| 5034 | assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :do { if (!(vector_len == AVX_128bit ? VM_Version::supports_avx () : vector_len == AVX_256bit ? VM_Version::supports_avx2() : vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : 0)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 5036, "assert(" "vector_len == AVX_128bit ? VM_Version::supports_avx() : vector_len == AVX_256bit ? VM_Version::supports_avx2() : vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : 0" ") failed", ""); ::breakpoint(); } } while (0) | |||
| 5035 | vector_len == AVX_256bit ? VM_Version::supports_avx2() :do { if (!(vector_len == AVX_128bit ? VM_Version::supports_avx () : vector_len == AVX_256bit ? VM_Version::supports_avx2() : vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : 0)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 5036, "assert(" "vector_len == AVX_128bit ? VM_Version::supports_avx() : vector_len == AVX_256bit ? VM_Version::supports_avx2() : vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : 0" ") failed", ""); ::breakpoint(); } } while (0) | |||
| 5036 | vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : 0, "")do { if (!(vector_len == AVX_128bit ? VM_Version::supports_avx () : vector_len == AVX_256bit ? VM_Version::supports_avx2() : vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : 0)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 5036, "assert(" "vector_len == AVX_128bit ? VM_Version::supports_avx() : vector_len == AVX_256bit ? VM_Version::supports_avx2() : vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : 0" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 5037 | InstructionAttr attributes(vector_len, /*vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 5038 | int encode = vex_prefix_and_encode(xmm7->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 5039 | emit_int24(0x73, (0xC0 | encode), shift & 0xFF); | |||
| 5040 | } | |||
| 5041 | ||||
| 5042 | void Assembler::ptest(XMMRegister dst, Address src) { | |||
| 5043 | assert(VM_Version::supports_sse4_1(), "")do { if (!(VM_Version::supports_sse4_1())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 5043, "assert(" "VM_Version::supports_sse4_1()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 5044 | assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes")do { if (!((UseAVX > 0))) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 5044, "assert(" "(UseAVX > 0)" ") failed", "SSE mode requires address alignment 16 bytes" ); ::breakpoint(); } } while (0); | |||
| 5045 | InstructionMark im(this); | |||
| 5046 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 5047 | simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 5048 | emit_int8(0x17); | |||
| 5049 | emit_operand(dst, src); | |||
| 5050 | } | |||
| 5051 | ||||
| 5052 | void Assembler::ptest(XMMRegister dst, XMMRegister src) { | |||
| 5053 | assert(VM_Version::supports_sse4_1() || VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_sse4_1() || VM_Version::supports_avx ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 5053, "assert(" "VM_Version::supports_sse4_1() || VM_Version::supports_avx()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 5054 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 5055 | int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 5056 | emit_int8(0x17); | |||
| 5057 | emit_int8((0xC0 | encode)); | |||
| 5058 | } | |||
| 5059 | ||||
| 5060 | void Assembler::vptest(XMMRegister dst, Address src) { | |||
| 5061 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 5061, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 5062 | InstructionMark im(this); | |||
| 5063 | InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 5064 | assert(dst != xnoreg, "sanity")do { if (!(dst != xnoreg)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 5064, "assert(" "dst != xnoreg" ") failed", "sanity"); ::breakpoint (); } } while (0); | |||
| 5065 | // swap src<->dst for encoding | |||
| 5066 | vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 5067 | emit_int8(0x17); | |||
| 5068 | emit_operand(dst, src); | |||
| 5069 | } | |||
| 5070 | ||||
| 5071 | void Assembler::vptest(XMMRegister dst, XMMRegister src) { | |||
| 5072 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 5072, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 5073 | InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 5074 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 5075 | emit_int16(0x17, (0xC0 | encode)); | |||
| 5076 | } | |||
| 5077 | ||||
| 5078 | void Assembler::vptest(XMMRegister dst, XMMRegister src, int vector_len) { | |||
| 5079 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 5079, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 5080 | InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 5081 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 5082 | emit_int16(0x17, (0xC0 | encode)); | |||
| 5083 | } | |||
| 5084 | ||||
| 5085 | void Assembler::evptestmb(KRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 5086 | assert(VM_Version::supports_avx512vlbw(), "")do { if (!(VM_Version::supports_avx512vlbw())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 5086, "assert(" "VM_Version::supports_avx512vlbw()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 5087 | // Encoding: EVEX.NDS.XXX.66.0F.W0 DB /r | |||
| 5088 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 5089 | attributes.set_is_evex_instruction(); | |||
| 5090 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 5091 | emit_int16((unsigned char)0x26, (0xC0 | encode)); | |||
| 5092 | } | |||
| 5093 | ||||
| 5094 | void Assembler::punpcklbw(XMMRegister dst, Address src) { | |||
| 5095 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 5096 | assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes")do { if (!((UseAVX > 0))) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 5096, "assert(" "(UseAVX > 0)" ") failed", "SSE mode requires address alignment 16 bytes" ); ::breakpoint(); } } while (0); | |||
| 5097 | InstructionMark im(this); | |||
| 5098 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 5099 | attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); | |||
| 5100 | simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 5101 | emit_int8(0x60); | |||
| 5102 | emit_operand(dst, src); | |||
| 5103 | } | |||
| 5104 | ||||
| 5105 | void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) { | |||
| 5106 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 5107 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 5108 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 5109 | emit_int16(0x60, (0xC0 | encode)); | |||
| 5110 | } | |||
| 5111 | ||||
| 5112 | void Assembler::punpckldq(XMMRegister dst, Address src) { | |||
| 5113 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 5114 | assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes")do { if (!((UseAVX > 0))) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 5114, "assert(" "(UseAVX > 0)" ") failed", "SSE mode requires address alignment 16 bytes" ); ::breakpoint(); } } while (0); | |||
| 5115 | InstructionMark im(this); | |||
| 5116 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 5117 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); | |||
| 5118 | simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 5119 | emit_int8(0x62); | |||
| 5120 | emit_operand(dst, src); | |||
| 5121 | } | |||
| 5122 | ||||
| 5123 | void Assembler::punpckldq(XMMRegister dst, XMMRegister src) { | |||
| 5124 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 5125 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 5126 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 5127 | emit_int16(0x62, (0xC0 | encode)); | |||
| 5128 | } | |||
| 5129 | ||||
| 5130 | void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) { | |||
| 5131 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 5132 | InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 5133 | attributes.set_rex_vex_w_reverted(); | |||
| 5134 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 5135 | emit_int16(0x6C, (0xC0 | encode)); | |||
| 5136 | } | |||
| 5137 | ||||
| 5138 | void Assembler::push(int32_t imm32) { | |||
| 5139 | // in 64bits we push 64bits onto the stack but only | |||
| 5140 | // take a 32bit immediate | |||
| 5141 | emit_int8(0x68); | |||
| 5142 | emit_int32(imm32); | |||
| 5143 | } | |||
| 5144 | ||||
| 5145 | void Assembler::push(Register src) { | |||
| 5146 | int encode = prefix_and_encode(src->encoding()); | |||
| 5147 | emit_int8(0x50 | encode); | |||
| 5148 | } | |||
| 5149 | ||||
| 5150 | void Assembler::pushf() { | |||
| 5151 | emit_int8((unsigned char)0x9C); | |||
| 5152 | } | |||
| 5153 | ||||
| 5154 | #ifndef _LP641 // no 32bit push/pop on amd64 | |||
| 5155 | void Assembler::pushl(Address src) { | |||
| 5156 | // Note this will push 64bit on 64bit | |||
| 5157 | InstructionMark im(this); | |||
| 5158 | prefix(src); | |||
| 5159 | emit_int8((unsigned char)0xFF); | |||
| 5160 | emit_operand(rsi, src); | |||
| 5161 | } | |||
| 5162 | #endif | |||
| 5163 | ||||
| 5164 | void Assembler::rcll(Register dst, int imm8) { | |||
| 5165 | assert(isShiftCount(imm8), "illegal shift count")do { if (!(isShiftCount(imm8))) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 5165, "assert(" "isShiftCount(imm8)" ") failed", "illegal shift count" ); ::breakpoint(); } } while (0); | |||
| 5166 | int encode = prefix_and_encode(dst->encoding()); | |||
| 5167 | if (imm8 == 1) { | |||
| 5168 | emit_int16((unsigned char)0xD1, (0xD0 | encode)); | |||
| 5169 | } else { | |||
| 5170 | emit_int24((unsigned char)0xC1, (0xD0 | encode), imm8); | |||
| 5171 | } | |||
| 5172 | } | |||
| 5173 | ||||
| 5174 | void Assembler::rcpps(XMMRegister dst, XMMRegister src) { | |||
| 5175 | NOT_LP64(assert(VM_Version::supports_sse(), "")); | |||
| 5176 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 5177 | int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 5178 | emit_int16(0x53, (0xC0 | encode)); | |||
| 5179 | } | |||
| 5180 | ||||
| 5181 | void Assembler::rcpss(XMMRegister dst, XMMRegister src) { | |||
| 5182 | NOT_LP64(assert(VM_Version::supports_sse(), "")); | |||
| 5183 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 5184 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); | |||
| 5185 | emit_int16(0x53, (0xC0 | encode)); | |||
| 5186 | } | |||
| 5187 | ||||
| 5188 | void Assembler::rdtsc() { | |||
| 5189 | emit_int16(0x0F, 0x31); | |||
| 5190 | } | |||
| 5191 | ||||
| 5192 | // copies data from [esi] to [edi] using rcx pointer sized words | |||
| 5193 | // generic | |||
| 5194 | void Assembler::rep_mov() { | |||
| 5195 | // REP | |||
| 5196 | // MOVSQ | |||
| 5197 | LP64_ONLY(emit_int24((unsigned char)0xF3, REX_W, (unsigned char)0xA5);)emit_int24((unsigned char)0xF3, REX_W, (unsigned char)0xA5); | |||
| 5198 | NOT_LP64( emit_int16((unsigned char)0xF3, (unsigned char)0xA5);) | |||
| 5199 | } | |||
| 5200 | ||||
| 5201 | // sets rcx bytes with rax, value at [edi] | |||
| 5202 | void Assembler::rep_stosb() { | |||
| 5203 | // REP | |||
| 5204 | // STOSB | |||
| 5205 | LP64_ONLY(emit_int24((unsigned char)0xF3, REX_W, (unsigned char)0xAA);)emit_int24((unsigned char)0xF3, REX_W, (unsigned char)0xAA); | |||
| 5206 | NOT_LP64( emit_int16((unsigned char)0xF3, (unsigned char)0xAA);) | |||
| 5207 | } | |||
| 5208 | ||||
| 5209 | // sets rcx pointer sized words with rax, value at [edi] | |||
| 5210 | // generic | |||
| 5211 | void Assembler::rep_stos() { | |||
| 5212 | // REP | |||
| 5213 | // LP64:STOSQ, LP32:STOSD | |||
| 5214 | LP64_ONLY(emit_int24((unsigned char)0xF3, REX_W, (unsigned char)0xAB);)emit_int24((unsigned char)0xF3, REX_W, (unsigned char)0xAB); | |||
| 5215 | NOT_LP64( emit_int16((unsigned char)0xF3, (unsigned char)0xAB);) | |||
| 5216 | } | |||
| 5217 | ||||
| 5218 | // scans rcx pointer sized words at [edi] for occurance of rax, | |||
| 5219 | // generic | |||
| 5220 | void Assembler::repne_scan() { // repne_scan | |||
| 5221 | // SCASQ | |||
| 5222 | LP64_ONLY(emit_int24((unsigned char)0xF2, REX_W, (unsigned char)0xAF);)emit_int24((unsigned char)0xF2, REX_W, (unsigned char)0xAF); | |||
| 5223 | NOT_LP64( emit_int16((unsigned char)0xF2, (unsigned char)0xAF);) | |||
| 5224 | } | |||
| 5225 | ||||
| 5226 | #ifdef _LP641 | |||
| 5227 | // scans rcx 4 byte words at [edi] for occurance of rax, | |||
| 5228 | // generic | |||
| 5229 | void Assembler::repne_scanl() { // repne_scan | |||
| 5230 | // SCASL | |||
| 5231 | emit_int16((unsigned char)0xF2, (unsigned char)0xAF); | |||
| 5232 | } | |||
| 5233 | #endif | |||
| 5234 | ||||
| 5235 | void Assembler::ret(int imm16) { | |||
| 5236 | if (imm16 == 0) { | |||
| 5237 | emit_int8((unsigned char)0xC3); | |||
| 5238 | } else { | |||
| 5239 | emit_int8((unsigned char)0xC2); | |||
| 5240 | emit_int16(imm16); | |||
| 5241 | } | |||
| 5242 | } | |||
| 5243 | ||||
| 5244 | void Assembler::roll(Register dst, int imm8) { | |||
| 5245 | assert(isShiftCount(imm8), "illegal shift count")do { if (!(isShiftCount(imm8))) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 5245, "assert(" "isShiftCount(imm8)" ") failed", "illegal shift count" ); ::breakpoint(); } } while (0); | |||
| 5246 | int encode = prefix_and_encode(dst->encoding()); | |||
| 5247 | if (imm8 == 1) { | |||
| 5248 | emit_int16((unsigned char)0xD1, (0xC0 | encode)); | |||
| 5249 | } else { | |||
| 5250 | emit_int24((unsigned char)0xC1, (0xc0 | encode), imm8); | |||
| 5251 | } | |||
| 5252 | } | |||
| 5253 | ||||
| 5254 | void Assembler::roll(Register dst) { | |||
| 5255 | int encode = prefix_and_encode(dst->encoding()); | |||
| 5256 | emit_int16((unsigned char)0xD3, (0xC0 | encode)); | |||
| 5257 | } | |||
| 5258 | ||||
| 5259 | void Assembler::rorl(Register dst, int imm8) { | |||
| 5260 | assert(isShiftCount(imm8), "illegal shift count")do { if (!(isShiftCount(imm8))) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 5260, "assert(" "isShiftCount(imm8)" ") failed", "illegal shift count" ); ::breakpoint(); } } while (0); | |||
| 5261 | int encode = prefix_and_encode(dst->encoding()); | |||
| 5262 | if (imm8 == 1) { | |||
| 5263 | emit_int16((unsigned char)0xD1, (0xC8 | encode)); | |||
| 5264 | } else { | |||
| 5265 | emit_int24((unsigned char)0xC1, (0xc8 | encode), imm8); | |||
| 5266 | } | |||
| 5267 | } | |||
| 5268 | ||||
| 5269 | void Assembler::rorl(Register dst) { | |||
| 5270 | int encode = prefix_and_encode(dst->encoding()); | |||
| 5271 | emit_int16((unsigned char)0xD3, (0xC8 | encode)); | |||
| 5272 | } | |||
| 5273 | ||||
| 5274 | #ifdef _LP641 | |||
| 5275 | void Assembler::rorq(Register dst) { | |||
| 5276 | int encode = prefixq_and_encode(dst->encoding()); | |||
| 5277 | emit_int16((unsigned char)0xD3, (0xC8 | encode)); | |||
| 5278 | } | |||
| 5279 | ||||
| 5280 | void Assembler::rorq(Register dst, int imm8) { | |||
| 5281 | assert(isShiftCount(imm8 >> 1), "illegal shift count")do { if (!(isShiftCount(imm8 >> 1))) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 5281, "assert(" "isShiftCount(imm8 >> 1)" ") failed", "illegal shift count"); ::breakpoint(); } } while (0); | |||
| 5282 | int encode = prefixq_and_encode(dst->encoding()); | |||
| 5283 | if (imm8 == 1) { | |||
| 5284 | emit_int16((unsigned char)0xD1, (0xC8 | encode)); | |||
| 5285 | } else { | |||
| 5286 | emit_int24((unsigned char)0xC1, (0xc8 | encode), imm8); | |||
| 5287 | } | |||
| 5288 | } | |||
| 5289 | ||||
| 5290 | void Assembler::rolq(Register dst) { | |||
| 5291 | int encode = prefixq_and_encode(dst->encoding()); | |||
| 5292 | emit_int16((unsigned char)0xD3, (0xC0 | encode)); | |||
| 5293 | } | |||
| 5294 | ||||
| 5295 | void Assembler::rolq(Register dst, int imm8) { | |||
| 5296 | assert(isShiftCount(imm8 >> 1), "illegal shift count")do { if (!(isShiftCount(imm8 >> 1))) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 5296, "assert(" "isShiftCount(imm8 >> 1)" ") failed", "illegal shift count"); ::breakpoint(); } } while (0); | |||
| 5297 | int encode = prefixq_and_encode(dst->encoding()); | |||
| 5298 | if (imm8 == 1) { | |||
| 5299 | emit_int16((unsigned char)0xD1, (0xC0 | encode)); | |||
| 5300 | } else { | |||
| 5301 | emit_int24((unsigned char)0xC1, (0xc0 | encode), imm8); | |||
| 5302 | } | |||
| 5303 | } | |||
| 5304 | #endif | |||
| 5305 | ||||
| 5306 | void Assembler::sahf() { | |||
| 5307 | #ifdef _LP641 | |||
| 5308 | // Not supported in 64bit mode | |||
| 5309 | ShouldNotReachHere()do { (*g_assert_poison) = 'X';; report_should_not_reach_here( "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 5309); ::breakpoint(); } while (0); | |||
| 5310 | #endif | |||
| 5311 | emit_int8((unsigned char)0x9E); | |||
| 5312 | } | |||
| 5313 | ||||
| 5314 | void Assembler::sall(Address dst, int imm8) { | |||
| 5315 | InstructionMark im(this); | |||
| 5316 | assert(isShiftCount(imm8), "illegal shift count")do { if (!(isShiftCount(imm8))) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 5316, "assert(" "isShiftCount(imm8)" ") failed", "illegal shift count" ); ::breakpoint(); } } while (0); | |||
| 5317 | prefix(dst); | |||
| 5318 | if (imm8 == 1) { | |||
| 5319 | emit_int8((unsigned char)0xD1); | |||
| 5320 | emit_operand(as_Register(4), dst); | |||
| 5321 | } | |||
| 5322 | else { | |||
| 5323 | emit_int8((unsigned char)0xC1); | |||
| 5324 | emit_operand(as_Register(4), dst); | |||
| 5325 | emit_int8(imm8); | |||
| 5326 | } | |||
| 5327 | } | |||
| 5328 | ||||
| 5329 | void Assembler::sall(Address dst) { | |||
| 5330 | InstructionMark im(this); | |||
| 5331 | prefix(dst); | |||
| 5332 | emit_int8((unsigned char)0xD3); | |||
| 5333 | emit_operand(as_Register(4), dst); | |||
| 5334 | } | |||
| 5335 | ||||
| 5336 | void Assembler::sall(Register dst, int imm8) { | |||
| 5337 | assert(isShiftCount(imm8), "illegal shift count")do { if (!(isShiftCount(imm8))) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 5337, "assert(" "isShiftCount(imm8)" ") failed", "illegal shift count" ); ::breakpoint(); } } while (0); | |||
| 5338 | int encode = prefix_and_encode(dst->encoding()); | |||
| 5339 | if (imm8 == 1) { | |||
| 5340 | emit_int16((unsigned char)0xD1, (0xE0 | encode)); | |||
| 5341 | } else { | |||
| 5342 | emit_int24((unsigned char)0xC1, (0xE0 | encode), imm8); | |||
| 5343 | } | |||
| 5344 | } | |||
| 5345 | ||||
| 5346 | void Assembler::sall(Register dst) { | |||
| 5347 | int encode = prefix_and_encode(dst->encoding()); | |||
| 5348 | emit_int16((unsigned char)0xD3, (0xE0 | encode)); | |||
| 5349 | } | |||
| 5350 | ||||
| 5351 | void Assembler::sarl(Address dst, int imm8) { | |||
| 5352 | assert(isShiftCount(imm8), "illegal shift count")do { if (!(isShiftCount(imm8))) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 5352, "assert(" "isShiftCount(imm8)" ") failed", "illegal shift count" ); ::breakpoint(); } } while (0); | |||
| 5353 | InstructionMark im(this); | |||
| 5354 | prefix(dst); | |||
| 5355 | if (imm8 == 1) { | |||
| 5356 | emit_int8((unsigned char)0xD1); | |||
| 5357 | emit_operand(as_Register(7), dst); | |||
| 5358 | } | |||
| 5359 | else { | |||
| 5360 | emit_int8((unsigned char)0xC1); | |||
| 5361 | emit_operand(as_Register(7), dst); | |||
| 5362 | emit_int8(imm8); | |||
| 5363 | } | |||
| 5364 | } | |||
| 5365 | ||||
| 5366 | void Assembler::sarl(Address dst) { | |||
| 5367 | InstructionMark im(this); | |||
| 5368 | prefix(dst); | |||
| 5369 | emit_int8((unsigned char)0xD3); | |||
| 5370 | emit_operand(as_Register(7), dst); | |||
| 5371 | } | |||
| 5372 | ||||
| 5373 | void Assembler::sarl(Register dst, int imm8) { | |||
| 5374 | int encode = prefix_and_encode(dst->encoding()); | |||
| 5375 | assert(isShiftCount(imm8), "illegal shift count")do { if (!(isShiftCount(imm8))) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 5375, "assert(" "isShiftCount(imm8)" ") failed", "illegal shift count" ); ::breakpoint(); } } while (0); | |||
| 5376 | if (imm8 == 1) { | |||
| 5377 | emit_int16((unsigned char)0xD1, (0xF8 | encode)); | |||
| 5378 | } else { | |||
| 5379 | emit_int24((unsigned char)0xC1, (0xF8 | encode), imm8); | |||
| 5380 | } | |||
| 5381 | } | |||
| 5382 | ||||
| 5383 | void Assembler::sarl(Register dst) { | |||
| 5384 | int encode = prefix_and_encode(dst->encoding()); | |||
| 5385 | emit_int16((unsigned char)0xD3, (0xF8 | encode)); | |||
| 5386 | } | |||
| 5387 | ||||
| 5388 | void Assembler::sbbl(Address dst, int32_t imm32) { | |||
| 5389 | InstructionMark im(this); | |||
| 5390 | prefix(dst); | |||
| 5391 | emit_arith_operand(0x81, rbx, dst, imm32); | |||
| 5392 | } | |||
| 5393 | ||||
| 5394 | void Assembler::sbbl(Register dst, int32_t imm32) { | |||
| 5395 | prefix(dst); | |||
| 5396 | emit_arith(0x81, 0xD8, dst, imm32); | |||
| 5397 | } | |||
| 5398 | ||||
| 5399 | ||||
| 5400 | void Assembler::sbbl(Register dst, Address src) { | |||
| 5401 | InstructionMark im(this); | |||
| 5402 | prefix(src, dst); | |||
| 5403 | emit_int8(0x1B); | |||
| 5404 | emit_operand(dst, src); | |||
| 5405 | } | |||
| 5406 | ||||
| 5407 | void Assembler::sbbl(Register dst, Register src) { | |||
| 5408 | (void) prefix_and_encode(dst->encoding(), src->encoding()); | |||
| 5409 | emit_arith(0x1B, 0xC0, dst, src); | |||
| 5410 | } | |||
| 5411 | ||||
| 5412 | void Assembler::setb(Condition cc, Register dst) { | |||
| 5413 | assert(0 <= cc && cc < 16, "illegal cc")do { if (!(0 <= cc && cc < 16)) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 5413, "assert(" "0 <= cc && cc < 16" ") failed" , "illegal cc"); ::breakpoint(); } } while (0); | |||
| 5414 | int encode = prefix_and_encode(dst->encoding(), true); | |||
| 5415 | emit_int24(0x0F, (unsigned char)0x90 | cc, (0xC0 | encode)); | |||
| 5416 | } | |||
| 5417 | ||||
| 5418 | void Assembler::sete(Register dst) { | |||
| 5419 | int encode = prefix_and_encode(dst->encoding(), true); | |||
| 5420 | emit_int24(0x0F, (unsigned char)0x94, (0xC0 | encode)); | |||
| 5421 | } | |||
| 5422 | ||||
| 5423 | void Assembler::setl(Register dst) { | |||
| 5424 | int encode = prefix_and_encode(dst->encoding(), true); | |||
| 5425 | emit_int24(0x0F, (unsigned char)0x9C, (0xC0 | encode)); | |||
| 5426 | } | |||
| 5427 | ||||
| 5428 | void Assembler::setne(Register dst) { | |||
| 5429 | int encode = prefix_and_encode(dst->encoding(), true); | |||
| 5430 | emit_int24(0x0F, (unsigned char)0x95, (0xC0 | encode)); | |||
| 5431 | } | |||
| 5432 | ||||
| 5433 | void Assembler::palignr(XMMRegister dst, XMMRegister src, int imm8) { | |||
| 5434 | assert(VM_Version::supports_ssse3(), "")do { if (!(VM_Version::supports_ssse3())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 5434, "assert(" "VM_Version::supports_ssse3()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 5435 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 5436 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 5437 | emit_int24(0x0F, (0xC0 | encode), imm8); | |||
| 5438 | } | |||
| 5439 | ||||
| 5440 | void Assembler::vpalignr(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) { | |||
| 5441 | assert(vector_len == AVX_128bit? VM_Version::supports_avx() :do { if (!(vector_len == AVX_128bit? VM_Version::supports_avx () : vector_len == AVX_256bit? VM_Version::supports_avx2() : 0 )) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 5443, "assert(" "vector_len == AVX_128bit? VM_Version::supports_avx() : vector_len == AVX_256bit? VM_Version::supports_avx2() : 0" ") failed", ""); ::breakpoint(); } } while (0) | |||
| 5442 | vector_len == AVX_256bit? VM_Version::supports_avx2() :do { if (!(vector_len == AVX_128bit? VM_Version::supports_avx () : vector_len == AVX_256bit? VM_Version::supports_avx2() : 0 )) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 5443, "assert(" "vector_len == AVX_128bit? VM_Version::supports_avx() : vector_len == AVX_256bit? VM_Version::supports_avx2() : 0" ") failed", ""); ::breakpoint(); } } while (0) | |||
| 5443 | 0, "")do { if (!(vector_len == AVX_128bit? VM_Version::supports_avx () : vector_len == AVX_256bit? VM_Version::supports_avx2() : 0 )) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 5443, "assert(" "vector_len == AVX_128bit? VM_Version::supports_avx() : vector_len == AVX_256bit? VM_Version::supports_avx2() : 0" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 5444 | InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 5445 | int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 5446 | emit_int24(0x0F, (0xC0 | encode), imm8); | |||
| 5447 | } | |||
| 5448 | ||||
| 5449 | void Assembler::evalignq(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) { | |||
| 5450 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 5450, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 5451 | InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 5452 | attributes.set_is_evex_instruction(); | |||
| 5453 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 5454 | emit_int24(0x3, (0xC0 | encode), imm8); | |||
| 5455 | } | |||
| 5456 | ||||
| 5457 | void Assembler::pblendw(XMMRegister dst, XMMRegister src, int imm8) { | |||
| 5458 | assert(VM_Version::supports_sse4_1(), "")do { if (!(VM_Version::supports_sse4_1())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 5458, "assert(" "VM_Version::supports_sse4_1()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 5459 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 5460 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 5461 | emit_int24(0x0E, (0xC0 | encode), imm8); | |||
| 5462 | } | |||
| 5463 | ||||
| 5464 | void Assembler::sha1rnds4(XMMRegister dst, XMMRegister src, int imm8) { | |||
| 5465 | assert(VM_Version::supports_sha(), "")do { if (!(VM_Version::supports_sha())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 5465, "assert(" "VM_Version::supports_sha()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 5466 | int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3A, /* rex_w */ false); | |||
| 5467 | emit_int24((unsigned char)0xCC, (0xC0 | encode), (unsigned char)imm8); | |||
| 5468 | } | |||
| 5469 | ||||
| 5470 | void Assembler::sha1nexte(XMMRegister dst, XMMRegister src) { | |||
| 5471 | assert(VM_Version::supports_sha(), "")do { if (!(VM_Version::supports_sha())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 5471, "assert(" "VM_Version::supports_sha()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 5472 | int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false); | |||
| 5473 | emit_int16((unsigned char)0xC8, (0xC0 | encode)); | |||
| 5474 | } | |||
| 5475 | ||||
| 5476 | void Assembler::sha1msg1(XMMRegister dst, XMMRegister src) { | |||
| 5477 | assert(VM_Version::supports_sha(), "")do { if (!(VM_Version::supports_sha())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 5477, "assert(" "VM_Version::supports_sha()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 5478 | int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false); | |||
| 5479 | emit_int16((unsigned char)0xC9, (0xC0 | encode)); | |||
| 5480 | } | |||
| 5481 | ||||
| 5482 | void Assembler::sha1msg2(XMMRegister dst, XMMRegister src) { | |||
| 5483 | assert(VM_Version::supports_sha(), "")do { if (!(VM_Version::supports_sha())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 5483, "assert(" "VM_Version::supports_sha()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 5484 | int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false); | |||
| 5485 | emit_int16((unsigned char)0xCA, (0xC0 | encode)); | |||
| 5486 | } | |||
| 5487 | ||||
| 5488 | // xmm0 is implicit additional source to this instruction. | |||
| 5489 | void Assembler::sha256rnds2(XMMRegister dst, XMMRegister src) { | |||
| 5490 | assert(VM_Version::supports_sha(), "")do { if (!(VM_Version::supports_sha())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 5490, "assert(" "VM_Version::supports_sha()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 5491 | int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false); | |||
| 5492 | emit_int16((unsigned char)0xCB, (0xC0 | encode)); | |||
| 5493 | } | |||
| 5494 | ||||
| 5495 | void Assembler::sha256msg1(XMMRegister dst, XMMRegister src) { | |||
| 5496 | assert(VM_Version::supports_sha(), "")do { if (!(VM_Version::supports_sha())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 5496, "assert(" "VM_Version::supports_sha()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 5497 | int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false); | |||
| 5498 | emit_int16((unsigned char)0xCC, (0xC0 | encode)); | |||
| 5499 | } | |||
| 5500 | ||||
| 5501 | void Assembler::sha256msg2(XMMRegister dst, XMMRegister src) { | |||
| 5502 | assert(VM_Version::supports_sha(), "")do { if (!(VM_Version::supports_sha())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 5502, "assert(" "VM_Version::supports_sha()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 5503 | int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false); | |||
| 5504 | emit_int16((unsigned char)0xCD, (0xC0 | encode)); | |||
| 5505 | } | |||
| 5506 | ||||
| 5507 | ||||
| 5508 | void Assembler::shll(Register dst, int imm8) { | |||
| 5509 | assert(isShiftCount(imm8), "illegal shift count")do { if (!(isShiftCount(imm8))) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 5509, "assert(" "isShiftCount(imm8)" ") failed", "illegal shift count" ); ::breakpoint(); } } while (0); | |||
| 5510 | int encode = prefix_and_encode(dst->encoding()); | |||
| 5511 | if (imm8 == 1 ) { | |||
| 5512 | emit_int16((unsigned char)0xD1, (0xE0 | encode)); | |||
| 5513 | } else { | |||
| 5514 | emit_int24((unsigned char)0xC1, (0xE0 | encode), imm8); | |||
| 5515 | } | |||
| 5516 | } | |||
| 5517 | ||||
| 5518 | void Assembler::shll(Register dst) { | |||
| 5519 | int encode = prefix_and_encode(dst->encoding()); | |||
| 5520 | emit_int16((unsigned char)0xD3, (0xE0 | encode)); | |||
| 5521 | } | |||
| 5522 | ||||
| 5523 | void Assembler::shrl(Register dst, int imm8) { | |||
| 5524 | assert(isShiftCount(imm8), "illegal shift count")do { if (!(isShiftCount(imm8))) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 5524, "assert(" "isShiftCount(imm8)" ") failed", "illegal shift count" ); ::breakpoint(); } } while (0); | |||
| 5525 | int encode = prefix_and_encode(dst->encoding()); | |||
| 5526 | if (imm8 == 1) { | |||
| 5527 | emit_int16((unsigned char)0xD1, (0xE8 | encode)); | |||
| 5528 | } | |||
| 5529 | else { | |||
| 5530 | emit_int24((unsigned char)0xC1, (0xE8 | encode), imm8); | |||
| 5531 | } | |||
| 5532 | } | |||
| 5533 | ||||
| 5534 | void Assembler::shrl(Register dst) { | |||
| 5535 | int encode = prefix_and_encode(dst->encoding()); | |||
| 5536 | emit_int16((unsigned char)0xD3, (0xE8 | encode)); | |||
| 5537 | } | |||
| 5538 | ||||
| 5539 | void Assembler::shrl(Address dst) { | |||
| 5540 | InstructionMark im(this); | |||
| 5541 | prefix(dst); | |||
| 5542 | emit_int8((unsigned char)0xD3); | |||
| 5543 | emit_operand(as_Register(5), dst); | |||
| 5544 | } | |||
| 5545 | ||||
| 5546 | void Assembler::shrl(Address dst, int imm8) { | |||
| 5547 | InstructionMark im(this); | |||
| 5548 | assert(isShiftCount(imm8), "illegal shift count")do { if (!(isShiftCount(imm8))) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 5548, "assert(" "isShiftCount(imm8)" ") failed", "illegal shift count" ); ::breakpoint(); } } while (0); | |||
| 5549 | prefix(dst); | |||
| 5550 | if (imm8 == 1) { | |||
| 5551 | emit_int8((unsigned char)0xD1); | |||
| 5552 | emit_operand(as_Register(5), dst); | |||
| 5553 | } | |||
| 5554 | else { | |||
| 5555 | emit_int8((unsigned char)0xC1); | |||
| 5556 | emit_operand(as_Register(5), dst); | |||
| 5557 | emit_int8(imm8); | |||
| 5558 | } | |||
| 5559 | } | |||
| 5560 | ||||
| 5561 | ||||
| 5562 | void Assembler::shldl(Register dst, Register src) { | |||
| 5563 | int encode = prefix_and_encode(src->encoding(), dst->encoding()); | |||
| 5564 | emit_int24(0x0F, (unsigned char)0xA5, (0xC0 | encode)); | |||
| 5565 | } | |||
| 5566 | ||||
| 5567 | void Assembler::shldl(Register dst, Register src, int8_t imm8) { | |||
| 5568 | int encode = prefix_and_encode(src->encoding(), dst->encoding()); | |||
| 5569 | emit_int32(0x0F, (unsigned char)0xA4, (0xC0 | encode), imm8); | |||
| 5570 | } | |||
| 5571 | ||||
| 5572 | void Assembler::shrdl(Register dst, Register src) { | |||
| 5573 | int encode = prefix_and_encode(src->encoding(), dst->encoding()); | |||
| 5574 | emit_int24(0x0F, (unsigned char)0xAD, (0xC0 | encode)); | |||
| 5575 | } | |||
| 5576 | ||||
| 5577 | void Assembler::shrdl(Register dst, Register src, int8_t imm8) { | |||
| 5578 | int encode = prefix_and_encode(src->encoding(), dst->encoding()); | |||
| 5579 | emit_int32(0x0F, (unsigned char)0xAC, (0xC0 | encode), imm8); | |||
| 5580 | } | |||
| 5581 | ||||
| 5582 | // copies a single word from [esi] to [edi] | |||
| 5583 | void Assembler::smovl() { | |||
| 5584 | emit_int8((unsigned char)0xA5); | |||
| 5585 | } | |||
| 5586 | ||||
| 5587 | void Assembler::roundsd(XMMRegister dst, XMMRegister src, int32_t rmode) { | |||
| 5588 | assert(VM_Version::supports_sse4_1(), "")do { if (!(VM_Version::supports_sse4_1())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 5588, "assert(" "VM_Version::supports_sse4_1()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 5589 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 5590 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 5591 | emit_int24(0x0B, (0xC0 | encode), (unsigned char)rmode); | |||
| 5592 | } | |||
| 5593 | ||||
| 5594 | void Assembler::roundsd(XMMRegister dst, Address src, int32_t rmode) { | |||
| 5595 | assert(VM_Version::supports_sse4_1(), "")do { if (!(VM_Version::supports_sse4_1())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 5595, "assert(" "VM_Version::supports_sse4_1()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 5596 | InstructionMark im(this); | |||
| 5597 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 5598 | simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 5599 | emit_int8(0x0B); | |||
| 5600 | emit_operand(dst, src); | |||
| 5601 | emit_int8((unsigned char)rmode); | |||
| 5602 | } | |||
| 5603 | ||||
| 5604 | void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) { | |||
| 5605 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 5606 | InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 5607 | attributes.set_rex_vex_w_reverted(); | |||
| 5608 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); | |||
| 5609 | emit_int16(0x51, (0xC0 | encode)); | |||
| 5610 | } | |||
| 5611 | ||||
| 5612 | void Assembler::sqrtsd(XMMRegister dst, Address src) { | |||
| 5613 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 5614 | InstructionMark im(this); | |||
| 5615 | InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 5616 | attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); | |||
| 5617 | attributes.set_rex_vex_w_reverted(); | |||
| 5618 | simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); | |||
| 5619 | emit_int8(0x51); | |||
| 5620 | emit_operand(dst, src); | |||
| 5621 | } | |||
| 5622 | ||||
| 5623 | void Assembler::sqrtss(XMMRegister dst, XMMRegister src) { | |||
| 5624 | NOT_LP64(assert(VM_Version::supports_sse(), "")); | |||
| 5625 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 5626 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); | |||
| 5627 | emit_int16(0x51, (0xC0 | encode)); | |||
| 5628 | } | |||
| 5629 | ||||
| 5630 | void Assembler::std() { | |||
| 5631 | emit_int8((unsigned char)0xFD); | |||
| 5632 | } | |||
| 5633 | ||||
| 5634 | void Assembler::sqrtss(XMMRegister dst, Address src) { | |||
| 5635 | NOT_LP64(assert(VM_Version::supports_sse(), "")); | |||
| 5636 | InstructionMark im(this); | |||
| 5637 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 5638 | attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); | |||
| 5639 | simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); | |||
| 5640 | emit_int8(0x51); | |||
| 5641 | emit_operand(dst, src); | |||
| 5642 | } | |||
| 5643 | ||||
| 5644 | void Assembler::stmxcsr( Address dst) { | |||
| 5645 | if (UseAVX > 0 ) { | |||
| 5646 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 5646, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 5647 | InstructionMark im(this); | |||
| 5648 | InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 5649 | vex_prefix(dst, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 5650 | emit_int8((unsigned char)0xAE); | |||
| 5651 | emit_operand(as_Register(3), dst); | |||
| 5652 | } else { | |||
| 5653 | NOT_LP64(assert(VM_Version::supports_sse(), "")); | |||
| 5654 | InstructionMark im(this); | |||
| 5655 | prefix(dst); | |||
| 5656 | emit_int16(0x0F, (unsigned char)0xAE); | |||
| 5657 | emit_operand(as_Register(3), dst); | |||
| 5658 | } | |||
| 5659 | } | |||
| 5660 | ||||
| 5661 | void Assembler::subl(Address dst, int32_t imm32) { | |||
| 5662 | InstructionMark im(this); | |||
| 5663 | prefix(dst); | |||
| 5664 | emit_arith_operand(0x81, rbp, dst, imm32); | |||
| 5665 | } | |||
| 5666 | ||||
| 5667 | void Assembler::subl(Address dst, Register src) { | |||
| 5668 | InstructionMark im(this); | |||
| 5669 | prefix(dst, src); | |||
| 5670 | emit_int8(0x29); | |||
| 5671 | emit_operand(src, dst); | |||
| 5672 | } | |||
| 5673 | ||||
| 5674 | void Assembler::subl(Register dst, int32_t imm32) { | |||
| 5675 | prefix(dst); | |||
| 5676 | emit_arith(0x81, 0xE8, dst, imm32); | |||
| 5677 | } | |||
| 5678 | ||||
| 5679 | // Force generation of a 4 byte immediate value even if it fits into 8bit | |||
| 5680 | void Assembler::subl_imm32(Register dst, int32_t imm32) { | |||
| 5681 | prefix(dst); | |||
| 5682 | emit_arith_imm32(0x81, 0xE8, dst, imm32); | |||
| 5683 | } | |||
| 5684 | ||||
| 5685 | void Assembler::subl(Register dst, Address src) { | |||
| 5686 | InstructionMark im(this); | |||
| 5687 | prefix(src, dst); | |||
| 5688 | emit_int8(0x2B); | |||
| 5689 | emit_operand(dst, src); | |||
| 5690 | } | |||
| 5691 | ||||
| 5692 | void Assembler::subl(Register dst, Register src) { | |||
| 5693 | (void) prefix_and_encode(dst->encoding(), src->encoding()); | |||
| 5694 | emit_arith(0x2B, 0xC0, dst, src); | |||
| 5695 | } | |||
| 5696 | ||||
| 5697 | void Assembler::subsd(XMMRegister dst, XMMRegister src) { | |||
| 5698 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 5699 | InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 5700 | attributes.set_rex_vex_w_reverted(); | |||
| 5701 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); | |||
| 5702 | emit_int16(0x5C, (0xC0 | encode)); | |||
| 5703 | } | |||
| 5704 | ||||
| 5705 | void Assembler::subsd(XMMRegister dst, Address src) { | |||
| 5706 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 5707 | InstructionMark im(this); | |||
| 5708 | InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 5709 | attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); | |||
| 5710 | attributes.set_rex_vex_w_reverted(); | |||
| 5711 | simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); | |||
| 5712 | emit_int8(0x5C); | |||
| 5713 | emit_operand(dst, src); | |||
| 5714 | } | |||
| 5715 | ||||
| 5716 | void Assembler::subss(XMMRegister dst, XMMRegister src) { | |||
| 5717 | NOT_LP64(assert(VM_Version::supports_sse(), "")); | |||
| 5718 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true , /* uses_vl */ false); | |||
| 5719 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); | |||
| 5720 | emit_int16(0x5C, (0xC0 | encode)); | |||
| 5721 | } | |||
| 5722 | ||||
| 5723 | void Assembler::subss(XMMRegister dst, Address src) { | |||
| 5724 | NOT_LP64(assert(VM_Version::supports_sse(), "")); | |||
| 5725 | InstructionMark im(this); | |||
| 5726 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 5727 | attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); | |||
| 5728 | simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); | |||
| 5729 | emit_int8(0x5C); | |||
| 5730 | emit_operand(dst, src); | |||
| 5731 | } | |||
| 5732 | ||||
| 5733 | void Assembler::testb(Register dst, int imm8) { | |||
| 5734 | NOT_LP64(assert(dst->has_byte_register(), "must have byte register")); | |||
| 5735 | (void) prefix_and_encode(dst->encoding(), true); | |||
| 5736 | emit_arith_b(0xF6, 0xC0, dst, imm8); | |||
| 5737 | } | |||
| 5738 | ||||
| 5739 | void Assembler::testb(Address dst, int imm8) { | |||
| 5740 | InstructionMark im(this); | |||
| 5741 | prefix(dst); | |||
| 5742 | emit_int8((unsigned char)0xF6); | |||
| 5743 | emit_operand(rax, dst, 1); | |||
| 5744 | emit_int8(imm8); | |||
| 5745 | } | |||
| 5746 | ||||
| 5747 | void Assembler::testl(Register dst, int32_t imm32) { | |||
| 5748 | // not using emit_arith because test | |||
| 5749 | // doesn't support sign-extension of | |||
| 5750 | // 8bit operands | |||
| 5751 | int encode = dst->encoding(); | |||
| 5752 | encode = prefix_and_encode(encode); | |||
| 5753 | emit_int16((unsigned char)0xF7, (0xC0 | encode)); | |||
| 5754 | emit_int32(imm32); | |||
| 5755 | } | |||
| 5756 | ||||
| 5757 | void Assembler::testl(Register dst, Register src) { | |||
| 5758 | (void) prefix_and_encode(dst->encoding(), src->encoding()); | |||
| 5759 | emit_arith(0x85, 0xC0, dst, src); | |||
| 5760 | } | |||
| 5761 | ||||
| 5762 | void Assembler::testl(Register dst, Address src) { | |||
| 5763 | InstructionMark im(this); | |||
| 5764 | prefix(src, dst); | |||
| 5765 | emit_int8((unsigned char)0x85); | |||
| 5766 | emit_operand(dst, src); | |||
| 5767 | } | |||
| 5768 | ||||
| 5769 | void Assembler::tzcntl(Register dst, Register src) { | |||
| 5770 | assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported")do { if (!(VM_Version::supports_bmi1())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 5770, "assert(" "VM_Version::supports_bmi1()" ") failed", "tzcnt instruction not supported" ); ::breakpoint(); } } while (0); | |||
| 5771 | emit_int8((unsigned char)0xF3); | |||
| 5772 | int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |||
| 5773 | emit_int24(0x0F, | |||
| 5774 | (unsigned char)0xBC, | |||
| 5775 | 0xC0 | encode); | |||
| 5776 | } | |||
| 5777 | ||||
| 5778 | void Assembler::tzcntq(Register dst, Register src) { | |||
| 5779 | assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported")do { if (!(VM_Version::supports_bmi1())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 5779, "assert(" "VM_Version::supports_bmi1()" ") failed", "tzcnt instruction not supported" ); ::breakpoint(); } } while (0); | |||
| 5780 | emit_int8((unsigned char)0xF3); | |||
| 5781 | int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |||
| 5782 | emit_int24(0x0F, (unsigned char)0xBC, (0xC0 | encode)); | |||
| 5783 | } | |||
| 5784 | ||||
| 5785 | void Assembler::ucomisd(XMMRegister dst, Address src) { | |||
| 5786 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 5787 | InstructionMark im(this); | |||
| 5788 | InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 5789 | attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); | |||
| 5790 | attributes.set_rex_vex_w_reverted(); | |||
| 5791 | simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 5792 | emit_int8(0x2E); | |||
| 5793 | emit_operand(dst, src); | |||
| 5794 | } | |||
| 5795 | ||||
| 5796 | void Assembler::ucomisd(XMMRegister dst, XMMRegister src) { | |||
| 5797 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 5798 | InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 5799 | attributes.set_rex_vex_w_reverted(); | |||
| 5800 | int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 5801 | emit_int16(0x2E, (0xC0 | encode)); | |||
| 5802 | } | |||
| 5803 | ||||
| 5804 | void Assembler::ucomiss(XMMRegister dst, Address src) { | |||
| 5805 | NOT_LP64(assert(VM_Version::supports_sse(), "")); | |||
| 5806 | InstructionMark im(this); | |||
| 5807 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 5808 | attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); | |||
| 5809 | simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 5810 | emit_int8(0x2E); | |||
| 5811 | emit_operand(dst, src); | |||
| 5812 | } | |||
| 5813 | ||||
| 5814 | void Assembler::ucomiss(XMMRegister dst, XMMRegister src) { | |||
| 5815 | NOT_LP64(assert(VM_Version::supports_sse(), "")); | |||
| 5816 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 5817 | int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 5818 | emit_int16(0x2E, (0xC0 | encode)); | |||
| 5819 | } | |||
| 5820 | ||||
| 5821 | void Assembler::xabort(int8_t imm8) { | |||
| 5822 | emit_int24((unsigned char)0xC6, (unsigned char)0xF8, (imm8 & 0xFF)); | |||
| 5823 | } | |||
| 5824 | ||||
| 5825 | void Assembler::xaddb(Address dst, Register src) { | |||
| 5826 | InstructionMark im(this); | |||
| 5827 | prefix(dst, src, true); | |||
| 5828 | emit_int16(0x0F, (unsigned char)0xC0); | |||
| 5829 | emit_operand(src, dst); | |||
| 5830 | } | |||
| 5831 | ||||
| 5832 | void Assembler::xaddw(Address dst, Register src) { | |||
| 5833 | InstructionMark im(this); | |||
| 5834 | emit_int8(0x66); | |||
| 5835 | prefix(dst, src); | |||
| 5836 | emit_int16(0x0F, (unsigned char)0xC1); | |||
| 5837 | emit_operand(src, dst); | |||
| 5838 | } | |||
| 5839 | ||||
| 5840 | void Assembler::xaddl(Address dst, Register src) { | |||
| 5841 | InstructionMark im(this); | |||
| 5842 | prefix(dst, src); | |||
| 5843 | emit_int16(0x0F, (unsigned char)0xC1); | |||
| 5844 | emit_operand(src, dst); | |||
| 5845 | } | |||
| 5846 | ||||
| 5847 | void Assembler::xbegin(Label& abort, relocInfo::relocType rtype) { | |||
| 5848 | InstructionMark im(this); | |||
| 5849 | relocate(rtype); | |||
| 5850 | if (abort.is_bound()) { | |||
| 5851 | address entry = target(abort); | |||
| 5852 | assert(entry != NULL, "abort entry NULL")do { if (!(entry != __null)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 5852, "assert(" "entry != __null" ") failed", "abort entry NULL" ); ::breakpoint(); } } while (0); | |||
| 5853 | intptr_t offset = entry - pc(); | |||
| 5854 | emit_int16((unsigned char)0xC7, (unsigned char)0xF8); | |||
| 5855 | emit_int32(offset - 6); // 2 opcode + 4 address | |||
| 5856 | } else { | |||
| 5857 | abort.add_patch_at(code(), locator()); | |||
| 5858 | emit_int16((unsigned char)0xC7, (unsigned char)0xF8); | |||
| 5859 | emit_int32(0); | |||
| 5860 | } | |||
| 5861 | } | |||
| 5862 | ||||
| 5863 | void Assembler::xchgb(Register dst, Address src) { // xchg | |||
| 5864 | InstructionMark im(this); | |||
| 5865 | prefix(src, dst, true); | |||
| 5866 | emit_int8((unsigned char)0x86); | |||
| 5867 | emit_operand(dst, src); | |||
| 5868 | } | |||
| 5869 | ||||
| 5870 | void Assembler::xchgw(Register dst, Address src) { // xchg | |||
| 5871 | InstructionMark im(this); | |||
| 5872 | emit_int8(0x66); | |||
| 5873 | prefix(src, dst); | |||
| 5874 | emit_int8((unsigned char)0x87); | |||
| 5875 | emit_operand(dst, src); | |||
| 5876 | } | |||
| 5877 | ||||
| 5878 | void Assembler::xchgl(Register dst, Address src) { // xchg | |||
| 5879 | InstructionMark im(this); | |||
| 5880 | prefix(src, dst); | |||
| 5881 | emit_int8((unsigned char)0x87); | |||
| 5882 | emit_operand(dst, src); | |||
| 5883 | } | |||
| 5884 | ||||
| 5885 | void Assembler::xchgl(Register dst, Register src) { | |||
| 5886 | int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |||
| 5887 | emit_int16((unsigned char)0x87, (0xC0 | encode)); | |||
| 5888 | } | |||
| 5889 | ||||
| 5890 | void Assembler::xend() { | |||
| 5891 | emit_int24(0x0F, 0x01, (unsigned char)0xD5); | |||
| 5892 | } | |||
| 5893 | ||||
| 5894 | void Assembler::xgetbv() { | |||
| 5895 | emit_int24(0x0F, 0x01, (unsigned char)0xD0); | |||
| 5896 | } | |||
| 5897 | ||||
| 5898 | void Assembler::xorl(Address dst, int32_t imm32) { | |||
| 5899 | InstructionMark im(this); | |||
| 5900 | prefix(dst); | |||
| 5901 | emit_arith_operand(0x81, as_Register(6), dst, imm32); | |||
| 5902 | } | |||
| 5903 | ||||
| 5904 | void Assembler::xorl(Register dst, int32_t imm32) { | |||
| 5905 | prefix(dst); | |||
| 5906 | emit_arith(0x81, 0xF0, dst, imm32); | |||
| 5907 | } | |||
| 5908 | ||||
| 5909 | void Assembler::xorl(Register dst, Address src) { | |||
| 5910 | InstructionMark im(this); | |||
| 5911 | prefix(src, dst); | |||
| 5912 | emit_int8(0x33); | |||
| 5913 | emit_operand(dst, src); | |||
| 5914 | } | |||
| 5915 | ||||
| 5916 | void Assembler::xorl(Register dst, Register src) { | |||
| 5917 | (void) prefix_and_encode(dst->encoding(), src->encoding()); | |||
| 5918 | emit_arith(0x33, 0xC0, dst, src); | |||
| 5919 | } | |||
| 5920 | ||||
| 5921 | void Assembler::xorl(Address dst, Register src) { | |||
| 5922 | InstructionMark im(this); | |||
| 5923 | prefix(dst, src); | |||
| 5924 | emit_int8(0x31); | |||
| 5925 | emit_operand(src, dst); | |||
| 5926 | } | |||
| 5927 | ||||
| 5928 | void Assembler::xorb(Register dst, Address src) { | |||
| 5929 | InstructionMark im(this); | |||
| 5930 | prefix(src, dst); | |||
| 5931 | emit_int8(0x32); | |||
| 5932 | emit_operand(dst, src); | |||
| 5933 | } | |||
| 5934 | ||||
| 5935 | void Assembler::xorb(Address dst, Register src) { | |||
| 5936 | InstructionMark im(this); | |||
| 5937 | prefix(dst, src, true); | |||
| 5938 | emit_int8(0x30); | |||
| 5939 | emit_operand(src, dst); | |||
| 5940 | } | |||
| 5941 | ||||
| 5942 | void Assembler::xorw(Register dst, Register src) { | |||
| 5943 | (void)prefix_and_encode(dst->encoding(), src->encoding()); | |||
| 5944 | emit_arith(0x33, 0xC0, dst, src); | |||
| 5945 | } | |||
| 5946 | ||||
| 5947 | // AVX 3-operands scalar float-point arithmetic instructions | |||
| 5948 | ||||
| 5949 | void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) { | |||
| 5950 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 5950, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 5951 | InstructionMark im(this); | |||
| 5952 | InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 5953 | attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); | |||
| 5954 | attributes.set_rex_vex_w_reverted(); | |||
| 5955 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); | |||
| 5956 | emit_int8(0x58); | |||
| 5957 | emit_operand(dst, src); | |||
| 5958 | } | |||
| 5959 | ||||
| 5960 | void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { | |||
| 5961 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 5961, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 5962 | InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 5963 | attributes.set_rex_vex_w_reverted(); | |||
| 5964 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); | |||
| 5965 | emit_int16(0x58, (0xC0 | encode)); | |||
| 5966 | } | |||
| 5967 | ||||
| 5968 | void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) { | |||
| 5969 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 5969, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 5970 | InstructionMark im(this); | |||
| 5971 | InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 5972 | attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); | |||
| 5973 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); | |||
| 5974 | emit_int8(0x58); | |||
| 5975 | emit_operand(dst, src); | |||
| 5976 | } | |||
| 5977 | ||||
| 5978 | void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { | |||
| 5979 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 5979, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 5980 | InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 5981 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); | |||
| 5982 | emit_int16(0x58, (0xC0 | encode)); | |||
| 5983 | } | |||
| 5984 | ||||
| 5985 | void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) { | |||
| 5986 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 5986, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 5987 | InstructionMark im(this); | |||
| 5988 | InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 5989 | attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); | |||
| 5990 | attributes.set_rex_vex_w_reverted(); | |||
| 5991 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); | |||
| 5992 | emit_int8(0x5E); | |||
| 5993 | emit_operand(dst, src); | |||
| 5994 | } | |||
| 5995 | ||||
| 5996 | void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { | |||
| 5997 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 5997, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 5998 | InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 5999 | attributes.set_rex_vex_w_reverted(); | |||
| 6000 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); | |||
| 6001 | emit_int16(0x5E, (0xC0 | encode)); | |||
| 6002 | } | |||
| 6003 | ||||
| 6004 | void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) { | |||
| 6005 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6005, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 6006 | InstructionMark im(this); | |||
| 6007 | InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 6008 | attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); | |||
| 6009 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); | |||
| 6010 | emit_int8(0x5E); | |||
| 6011 | emit_operand(dst, src); | |||
| 6012 | } | |||
| 6013 | ||||
| 6014 | void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { | |||
| 6015 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6015, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 6016 | InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 6017 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); | |||
| 6018 | emit_int16(0x5E, (0xC0 | encode)); | |||
| 6019 | } | |||
| 6020 | ||||
| 6021 | void Assembler::vfmadd231sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) { | |||
| 6022 | assert(VM_Version::supports_fma(), "")do { if (!(VM_Version::supports_fma())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6022, "assert(" "VM_Version::supports_fma()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 6023 | InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 6024 | int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 6025 | emit_int16((unsigned char)0xB9, (0xC0 | encode)); | |||
| 6026 | } | |||
| 6027 | ||||
| 6028 | void Assembler::vfmadd231ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) { | |||
| 6029 | assert(VM_Version::supports_fma(), "")do { if (!(VM_Version::supports_fma())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6029, "assert(" "VM_Version::supports_fma()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 6030 | InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 6031 | int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 6032 | emit_int16((unsigned char)0xB9, (0xC0 | encode)); | |||
| 6033 | } | |||
| 6034 | ||||
| 6035 | void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) { | |||
| 6036 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6036, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 6037 | InstructionMark im(this); | |||
| 6038 | InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 6039 | attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); | |||
| 6040 | attributes.set_rex_vex_w_reverted(); | |||
| 6041 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); | |||
| 6042 | emit_int8(0x59); | |||
| 6043 | emit_operand(dst, src); | |||
| 6044 | } | |||
| 6045 | ||||
| 6046 | void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { | |||
| 6047 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6047, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 6048 | InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 6049 | attributes.set_rex_vex_w_reverted(); | |||
| 6050 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); | |||
| 6051 | emit_int16(0x59, (0xC0 | encode)); | |||
| 6052 | } | |||
| 6053 | ||||
| 6054 | void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) { | |||
| 6055 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6055, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 6056 | InstructionMark im(this); | |||
| 6057 | InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 6058 | attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); | |||
| 6059 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); | |||
| 6060 | emit_int8(0x59); | |||
| 6061 | emit_operand(dst, src); | |||
| 6062 | } | |||
| 6063 | ||||
| 6064 | void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { | |||
| 6065 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6065, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 6066 | InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 6067 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); | |||
| 6068 | emit_int16(0x59, (0xC0 | encode)); | |||
| 6069 | } | |||
| 6070 | ||||
| 6071 | void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) { | |||
| 6072 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6072, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 6073 | InstructionMark im(this); | |||
| 6074 | InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 6075 | attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); | |||
| 6076 | attributes.set_rex_vex_w_reverted(); | |||
| 6077 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); | |||
| 6078 | emit_int8(0x5C); | |||
| 6079 | emit_operand(dst, src); | |||
| 6080 | } | |||
| 6081 | ||||
| 6082 | void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { | |||
| 6083 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6083, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 6084 | InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 6085 | attributes.set_rex_vex_w_reverted(); | |||
| 6086 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); | |||
| 6087 | emit_int16(0x5C, (0xC0 | encode)); | |||
| 6088 | } | |||
| 6089 | ||||
| 6090 | void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) { | |||
| 6091 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6091, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 6092 | InstructionMark im(this); | |||
| 6093 | InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 6094 | attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); | |||
| 6095 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); | |||
| 6096 | emit_int8(0x5C); | |||
| 6097 | emit_operand(dst, src); | |||
| 6098 | } | |||
| 6099 | ||||
| 6100 | void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { | |||
| 6101 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6101, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 6102 | InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 6103 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); | |||
| 6104 | emit_int16(0x5C, (0xC0 | encode)); | |||
| 6105 | } | |||
| 6106 | ||||
| 6107 | //====================VECTOR ARITHMETIC===================================== | |||
| 6108 | ||||
| 6109 | // Float-point vector arithmetic | |||
| 6110 | ||||
| 6111 | void Assembler::addpd(XMMRegister dst, XMMRegister src) { | |||
| 6112 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 6113 | InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6114 | attributes.set_rex_vex_w_reverted(); | |||
| 6115 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 6116 | emit_int16(0x58, (0xC0 | encode)); | |||
| 6117 | } | |||
| 6118 | ||||
| 6119 | void Assembler::addpd(XMMRegister dst, Address src) { | |||
| 6120 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 6121 | InstructionMark im(this); | |||
| 6122 | InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6123 | attributes.set_rex_vex_w_reverted(); | |||
| 6124 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); | |||
| 6125 | simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 6126 | emit_int8(0x58); | |||
| 6127 | emit_operand(dst, src); | |||
| 6128 | } | |||
| 6129 | ||||
| 6130 | ||||
| 6131 | void Assembler::addps(XMMRegister dst, XMMRegister src) { | |||
| 6132 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 6133 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6134 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 6135 | emit_int16(0x58, (0xC0 | encode)); | |||
| 6136 | } | |||
| 6137 | ||||
| 6138 | void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 6139 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6139, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 6140 | InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6141 | attributes.set_rex_vex_w_reverted(); | |||
| 6142 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 6143 | emit_int16(0x58, (0xC0 | encode)); | |||
| 6144 | } | |||
| 6145 | ||||
| 6146 | void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 6147 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6147, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 6148 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6149 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 6150 | emit_int16(0x58, (0xC0 | encode)); | |||
| 6151 | } | |||
| 6152 | ||||
| 6153 | void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { | |||
| 6154 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6154, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 6155 | InstructionMark im(this); | |||
| 6156 | InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6157 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); | |||
| 6158 | attributes.set_rex_vex_w_reverted(); | |||
| 6159 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 6160 | emit_int8(0x58); | |||
| 6161 | emit_operand(dst, src); | |||
| 6162 | } | |||
| 6163 | ||||
| 6164 | void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { | |||
| 6165 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6165, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 6166 | InstructionMark im(this); | |||
| 6167 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6168 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); | |||
| 6169 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 6170 | emit_int8(0x58); | |||
| 6171 | emit_operand(dst, src); | |||
| 6172 | } | |||
| 6173 | ||||
| 6174 | void Assembler::subpd(XMMRegister dst, XMMRegister src) { | |||
| 6175 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 6176 | InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6177 | attributes.set_rex_vex_w_reverted(); | |||
| 6178 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 6179 | emit_int16(0x5C, (0xC0 | encode)); | |||
| 6180 | } | |||
| 6181 | ||||
| 6182 | void Assembler::subps(XMMRegister dst, XMMRegister src) { | |||
| 6183 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 6184 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6185 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 6186 | emit_int16(0x5C, (0xC0 | encode)); | |||
| 6187 | } | |||
| 6188 | ||||
| 6189 | void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 6190 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6190, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 6191 | InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6192 | attributes.set_rex_vex_w_reverted(); | |||
| 6193 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 6194 | emit_int16(0x5C, (0xC0 | encode)); | |||
| 6195 | } | |||
| 6196 | ||||
| 6197 | void Assembler::vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 6198 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6198, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 6199 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6200 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 6201 | emit_int16(0x5C, (0xC0 | encode)); | |||
| 6202 | } | |||
| 6203 | ||||
| 6204 | void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { | |||
| 6205 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6205, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 6206 | InstructionMark im(this); | |||
| 6207 | InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6208 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); | |||
| 6209 | attributes.set_rex_vex_w_reverted(); | |||
| 6210 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 6211 | emit_int8(0x5C); | |||
| 6212 | emit_operand(dst, src); | |||
| 6213 | } | |||
| 6214 | ||||
| 6215 | void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { | |||
| 6216 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6216, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 6217 | InstructionMark im(this); | |||
| 6218 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6219 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); | |||
| 6220 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 6221 | emit_int8(0x5C); | |||
| 6222 | emit_operand(dst, src); | |||
| 6223 | } | |||
| 6224 | ||||
| 6225 | void Assembler::mulpd(XMMRegister dst, XMMRegister src) { | |||
| 6226 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 6227 | InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6228 | attributes.set_rex_vex_w_reverted(); | |||
| 6229 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 6230 | emit_int16(0x59, (0xC0 | encode)); | |||
| 6231 | } | |||
| 6232 | ||||
| 6233 | void Assembler::mulpd(XMMRegister dst, Address src) { | |||
| 6234 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 6235 | InstructionMark im(this); | |||
| 6236 | InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6237 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); | |||
| 6238 | attributes.set_rex_vex_w_reverted(); | |||
| 6239 | simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 6240 | emit_int8(0x59); | |||
| 6241 | emit_operand(dst, src); | |||
| 6242 | } | |||
| 6243 | ||||
| 6244 | void Assembler::mulps(XMMRegister dst, XMMRegister src) { | |||
| 6245 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 6246 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6247 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 6248 | emit_int16(0x59, (0xC0 | encode)); | |||
| 6249 | } | |||
| 6250 | ||||
| 6251 | void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 6252 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6252, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 6253 | InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6254 | attributes.set_rex_vex_w_reverted(); | |||
| 6255 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 6256 | emit_int16(0x59, (0xC0 | encode)); | |||
| 6257 | } | |||
| 6258 | ||||
| 6259 | void Assembler::vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 6260 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6260, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 6261 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6262 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 6263 | emit_int16(0x59, (0xC0 | encode)); | |||
| 6264 | } | |||
| 6265 | ||||
| 6266 | void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { | |||
| 6267 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6267, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 6268 | InstructionMark im(this); | |||
| 6269 | InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6270 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); | |||
| 6271 | attributes.set_rex_vex_w_reverted(); | |||
| 6272 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 6273 | emit_int8(0x59); | |||
| 6274 | emit_operand(dst, src); | |||
| 6275 | } | |||
| 6276 | ||||
| 6277 | void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { | |||
| 6278 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6278, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 6279 | InstructionMark im(this); | |||
| 6280 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6281 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); | |||
| 6282 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 6283 | emit_int8(0x59); | |||
| 6284 | emit_operand(dst, src); | |||
| 6285 | } | |||
| 6286 | ||||
| 6287 | void Assembler::vfmadd231pd(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len) { | |||
| 6288 | assert(VM_Version::supports_fma(), "")do { if (!(VM_Version::supports_fma())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6288, "assert(" "VM_Version::supports_fma()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 6289 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6290 | int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 6291 | emit_int16((unsigned char)0xB8, (0xC0 | encode)); | |||
| 6292 | } | |||
| 6293 | ||||
| 6294 | void Assembler::vfmadd231ps(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len) { | |||
| 6295 | assert(VM_Version::supports_fma(), "")do { if (!(VM_Version::supports_fma())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6295, "assert(" "VM_Version::supports_fma()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 6296 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6297 | int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 6298 | emit_int16((unsigned char)0xB8, (0xC0 | encode)); | |||
| 6299 | } | |||
| 6300 | ||||
| 6301 | void Assembler::vfmadd231pd(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) { | |||
| 6302 | assert(VM_Version::supports_fma(), "")do { if (!(VM_Version::supports_fma())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6302, "assert(" "VM_Version::supports_fma()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 6303 | InstructionMark im(this); | |||
| 6304 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6305 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); | |||
| 6306 | vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 6307 | emit_int8((unsigned char)0xB8); | |||
| 6308 | emit_operand(dst, src2); | |||
| 6309 | } | |||
| 6310 | ||||
| 6311 | void Assembler::vfmadd231ps(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) { | |||
| 6312 | assert(VM_Version::supports_fma(), "")do { if (!(VM_Version::supports_fma())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6312, "assert(" "VM_Version::supports_fma()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 6313 | InstructionMark im(this); | |||
| 6314 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6315 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); | |||
| 6316 | vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 6317 | emit_int8((unsigned char)0xB8); | |||
| 6318 | emit_operand(dst, src2); | |||
| 6319 | } | |||
| 6320 | ||||
| 6321 | void Assembler::divpd(XMMRegister dst, XMMRegister src) { | |||
| 6322 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 6323 | InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6324 | attributes.set_rex_vex_w_reverted(); | |||
| 6325 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 6326 | emit_int16(0x5E, (0xC0 | encode)); | |||
| 6327 | } | |||
| 6328 | ||||
| 6329 | void Assembler::divps(XMMRegister dst, XMMRegister src) { | |||
| 6330 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 6331 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6332 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 6333 | emit_int16(0x5E, (0xC0 | encode)); | |||
| 6334 | } | |||
| 6335 | ||||
| 6336 | void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 6337 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6337, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 6338 | InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6339 | attributes.set_rex_vex_w_reverted(); | |||
| 6340 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 6341 | emit_int16(0x5E, (0xC0 | encode)); | |||
| 6342 | } | |||
| 6343 | ||||
| 6344 | void Assembler::vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 6345 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6345, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 6346 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6347 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 6348 | emit_int16(0x5E, (0xC0 | encode)); | |||
| 6349 | } | |||
| 6350 | ||||
| 6351 | void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { | |||
| 6352 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6352, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 6353 | InstructionMark im(this); | |||
| 6354 | InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6355 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); | |||
| 6356 | attributes.set_rex_vex_w_reverted(); | |||
| 6357 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 6358 | emit_int8(0x5E); | |||
| 6359 | emit_operand(dst, src); | |||
| 6360 | } | |||
| 6361 | ||||
| 6362 | void Assembler::vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { | |||
| 6363 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6363, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 6364 | InstructionMark im(this); | |||
| 6365 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6366 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); | |||
| 6367 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 6368 | emit_int8(0x5E); | |||
| 6369 | emit_operand(dst, src); | |||
| 6370 | } | |||
| 6371 | ||||
| 6372 | void Assembler::vroundpd(XMMRegister dst, XMMRegister src, int32_t rmode, int vector_len) { | |||
| 6373 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6373, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 6374 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 6375 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 6376 | emit_int24(0x09, (0xC0 | encode), (rmode)); | |||
| 6377 | } | |||
| 6378 | ||||
| 6379 | void Assembler::vroundpd(XMMRegister dst, Address src, int32_t rmode, int vector_len) { | |||
| 6380 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6380, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 6381 | InstructionMark im(this); | |||
| 6382 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 6383 | vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 6384 | emit_int8(0x09); | |||
| 6385 | emit_operand(dst, src); | |||
| 6386 | emit_int8((rmode)); | |||
| 6387 | } | |||
| 6388 | ||||
| 6389 | void Assembler::vrndscalepd(XMMRegister dst, XMMRegister src, int32_t rmode, int vector_len) { | |||
| 6390 | assert(VM_Version::supports_evex(), "requires EVEX support")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6390, "assert(" "VM_Version::supports_evex()" ") failed", "requires EVEX support" ); ::breakpoint(); } } while (0); | |||
| 6391 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6392 | attributes.set_is_evex_instruction(); | |||
| 6393 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 6394 | emit_int24(0x09, (0xC0 | encode), (rmode)); | |||
| 6395 | } | |||
| 6396 | ||||
| 6397 | void Assembler::vrndscalepd(XMMRegister dst, Address src, int32_t rmode, int vector_len) { | |||
| 6398 | assert(VM_Version::supports_evex(), "requires EVEX support")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6398, "assert(" "VM_Version::supports_evex()" ") failed", "requires EVEX support" ); ::breakpoint(); } } while (0); | |||
| 6399 | assert(dst != xnoreg, "sanity")do { if (!(dst != xnoreg)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6399, "assert(" "dst != xnoreg" ") failed", "sanity"); ::breakpoint (); } } while (0); | |||
| 6400 | InstructionMark im(this); | |||
| 6401 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6402 | attributes.set_is_evex_instruction(); | |||
| 6403 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); | |||
| 6404 | vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 6405 | emit_int8(0x09); | |||
| 6406 | emit_operand(dst, src); | |||
| 6407 | emit_int8((rmode)); | |||
| 6408 | } | |||
| 6409 | ||||
| 6410 | ||||
| 6411 | void Assembler::vsqrtpd(XMMRegister dst, XMMRegister src, int vector_len) { | |||
| 6412 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6412, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 6413 | InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6414 | attributes.set_rex_vex_w_reverted(); | |||
| 6415 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 6416 | emit_int16(0x51, (0xC0 | encode)); | |||
| 6417 | } | |||
| 6418 | ||||
| 6419 | void Assembler::vsqrtpd(XMMRegister dst, Address src, int vector_len) { | |||
| 6420 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6420, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 6421 | InstructionMark im(this); | |||
| 6422 | InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6423 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); | |||
| 6424 | attributes.set_rex_vex_w_reverted(); | |||
| 6425 | vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 6426 | emit_int8(0x51); | |||
| 6427 | emit_operand(dst, src); | |||
| 6428 | } | |||
| 6429 | ||||
| 6430 | void Assembler::vsqrtps(XMMRegister dst, XMMRegister src, int vector_len) { | |||
| 6431 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6431, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 6432 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6433 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 6434 | emit_int16(0x51, (0xC0 | encode)); | |||
| 6435 | } | |||
| 6436 | ||||
| 6437 | void Assembler::vsqrtps(XMMRegister dst, Address src, int vector_len) { | |||
| 6438 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6438, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 6439 | InstructionMark im(this); | |||
| 6440 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6441 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); | |||
| 6442 | vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 6443 | emit_int8(0x51); | |||
| 6444 | emit_operand(dst, src); | |||
| 6445 | } | |||
| 6446 | ||||
| 6447 | void Assembler::andpd(XMMRegister dst, XMMRegister src) { | |||
| 6448 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 6449 | InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6450 | attributes.set_rex_vex_w_reverted(); | |||
| 6451 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 6452 | emit_int16(0x54, (0xC0 | encode)); | |||
| 6453 | } | |||
| 6454 | ||||
| 6455 | void Assembler::andps(XMMRegister dst, XMMRegister src) { | |||
| 6456 | NOT_LP64(assert(VM_Version::supports_sse(), "")); | |||
| 6457 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6458 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 6459 | emit_int16(0x54, (0xC0 | encode)); | |||
| 6460 | } | |||
| 6461 | ||||
| 6462 | void Assembler::andps(XMMRegister dst, Address src) { | |||
| 6463 | NOT_LP64(assert(VM_Version::supports_sse(), "")); | |||
| 6464 | InstructionMark im(this); | |||
| 6465 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6466 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); | |||
| 6467 | simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 6468 | emit_int8(0x54); | |||
| 6469 | emit_operand(dst, src); | |||
| 6470 | } | |||
| 6471 | ||||
| 6472 | void Assembler::andpd(XMMRegister dst, Address src) { | |||
| 6473 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 6474 | InstructionMark im(this); | |||
| 6475 | InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6476 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); | |||
| 6477 | attributes.set_rex_vex_w_reverted(); | |||
| 6478 | simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 6479 | emit_int8(0x54); | |||
| 6480 | emit_operand(dst, src); | |||
| 6481 | } | |||
| 6482 | ||||
| 6483 | void Assembler::vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 6484 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6484, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 6485 | InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6486 | attributes.set_rex_vex_w_reverted(); | |||
| 6487 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 6488 | emit_int16(0x54, (0xC0 | encode)); | |||
| 6489 | } | |||
| 6490 | ||||
| 6491 | void Assembler::vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 6492 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6492, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 6493 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6494 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 6495 | emit_int16(0x54, (0xC0 | encode)); | |||
| 6496 | } | |||
| 6497 | ||||
| 6498 | void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { | |||
| 6499 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6499, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 6500 | InstructionMark im(this); | |||
| 6501 | InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6502 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); | |||
| 6503 | attributes.set_rex_vex_w_reverted(); | |||
| 6504 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 6505 | emit_int8(0x54); | |||
| 6506 | emit_operand(dst, src); | |||
| 6507 | } | |||
| 6508 | ||||
| 6509 | void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { | |||
| 6510 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6510, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 6511 | InstructionMark im(this); | |||
| 6512 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6513 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); | |||
| 6514 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 6515 | emit_int8(0x54); | |||
| 6516 | emit_operand(dst, src); | |||
| 6517 | } | |||
| 6518 | ||||
| 6519 | void Assembler::unpckhpd(XMMRegister dst, XMMRegister src) { | |||
| 6520 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 6521 | InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6522 | attributes.set_rex_vex_w_reverted(); | |||
| 6523 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 6524 | emit_int8(0x15); | |||
| 6525 | emit_int8((0xC0 | encode)); | |||
| 6526 | } | |||
| 6527 | ||||
| 6528 | void Assembler::unpcklpd(XMMRegister dst, XMMRegister src) { | |||
| 6529 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 6530 | InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6531 | attributes.set_rex_vex_w_reverted(); | |||
| 6532 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 6533 | emit_int16(0x14, (0xC0 | encode)); | |||
| 6534 | } | |||
| 6535 | ||||
| 6536 | void Assembler::xorpd(XMMRegister dst, XMMRegister src) { | |||
| 6537 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 6538 | InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6539 | attributes.set_rex_vex_w_reverted(); | |||
| 6540 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 6541 | emit_int16(0x57, (0xC0 | encode)); | |||
| 6542 | } | |||
| 6543 | ||||
| 6544 | void Assembler::xorps(XMMRegister dst, XMMRegister src) { | |||
| 6545 | NOT_LP64(assert(VM_Version::supports_sse(), "")); | |||
| 6546 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6547 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 6548 | emit_int16(0x57, (0xC0 | encode)); | |||
| 6549 | } | |||
| 6550 | ||||
| 6551 | void Assembler::xorpd(XMMRegister dst, Address src) { | |||
| 6552 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 6553 | InstructionMark im(this); | |||
| 6554 | InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6555 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); | |||
| 6556 | attributes.set_rex_vex_w_reverted(); | |||
| 6557 | simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 6558 | emit_int8(0x57); | |||
| 6559 | emit_operand(dst, src); | |||
| 6560 | } | |||
| 6561 | ||||
| 6562 | void Assembler::xorps(XMMRegister dst, Address src) { | |||
| 6563 | NOT_LP64(assert(VM_Version::supports_sse(), "")); | |||
| 6564 | InstructionMark im(this); | |||
| 6565 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6566 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); | |||
| 6567 | simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 6568 | emit_int8(0x57); | |||
| 6569 | emit_operand(dst, src); | |||
| 6570 | } | |||
| 6571 | ||||
| 6572 | void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 6573 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6573, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 6574 | InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6575 | attributes.set_rex_vex_w_reverted(); | |||
| 6576 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 6577 | emit_int16(0x57, (0xC0 | encode)); | |||
| 6578 | } | |||
| 6579 | ||||
| 6580 | void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 6581 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6581, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 6582 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6583 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 6584 | emit_int16(0x57, (0xC0 | encode)); | |||
| 6585 | } | |||
| 6586 | ||||
| 6587 | void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { | |||
| 6588 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6588, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 6589 | InstructionMark im(this); | |||
| 6590 | InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6591 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); | |||
| 6592 | attributes.set_rex_vex_w_reverted(); | |||
| 6593 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 6594 | emit_int8(0x57); | |||
| 6595 | emit_operand(dst, src); | |||
| 6596 | } | |||
| 6597 | ||||
| 6598 | void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { | |||
| 6599 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6599, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 6600 | InstructionMark im(this); | |||
| 6601 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6602 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); | |||
| 6603 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 6604 | emit_int8(0x57); | |||
| 6605 | emit_operand(dst, src); | |||
| 6606 | } | |||
| 6607 | ||||
| 6608 | // Integer vector arithmetic | |||
| 6609 | void Assembler::vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 6610 | assert(VM_Version::supports_avx() && (vector_len == 0) ||do { if (!(VM_Version::supports_avx() && (vector_len == 0) || VM_Version::supports_avx2())) { (*g_assert_poison) = 'X' ;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6611, "assert(" "VM_Version::supports_avx() && (vector_len == 0) || VM_Version::supports_avx2()" ") failed", "256 bit integer vectors requires AVX2"); ::breakpoint (); } } while (0) | |||
| 6611 | VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2")do { if (!(VM_Version::supports_avx() && (vector_len == 0) || VM_Version::supports_avx2())) { (*g_assert_poison) = 'X' ;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6611, "assert(" "VM_Version::supports_avx() && (vector_len == 0) || VM_Version::supports_avx2()" ") failed", "256 bit integer vectors requires AVX2"); ::breakpoint (); } } while (0); | |||
| 6612 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6613 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 6614 | emit_int16(0x01, (0xC0 | encode)); | |||
| 6615 | } | |||
| 6616 | ||||
| 6617 | void Assembler::vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 6618 | assert(VM_Version::supports_avx() && (vector_len == 0) ||do { if (!(VM_Version::supports_avx() && (vector_len == 0) || VM_Version::supports_avx2())) { (*g_assert_poison) = 'X' ;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6619, "assert(" "VM_Version::supports_avx() && (vector_len == 0) || VM_Version::supports_avx2()" ") failed", "256 bit integer vectors requires AVX2"); ::breakpoint (); } } while (0) | |||
| 6619 | VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2")do { if (!(VM_Version::supports_avx() && (vector_len == 0) || VM_Version::supports_avx2())) { (*g_assert_poison) = 'X' ;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6619, "assert(" "VM_Version::supports_avx() && (vector_len == 0) || VM_Version::supports_avx2()" ") failed", "256 bit integer vectors requires AVX2"); ::breakpoint (); } } while (0); | |||
| 6620 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6621 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 6622 | emit_int16(0x02, (0xC0 | encode)); | |||
| 6623 | } | |||
| 6624 | ||||
| 6625 | void Assembler::paddb(XMMRegister dst, XMMRegister src) { | |||
| 6626 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 6627 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6628 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 6629 | emit_int16((unsigned char)0xFC, (0xC0 | encode)); | |||
| 6630 | } | |||
| 6631 | ||||
| 6632 | void Assembler::paddw(XMMRegister dst, XMMRegister src) { | |||
| 6633 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 6634 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6635 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 6636 | emit_int16((unsigned char)0xFD, (0xC0 | encode)); | |||
| 6637 | } | |||
| 6638 | ||||
| 6639 | void Assembler::paddd(XMMRegister dst, XMMRegister src) { | |||
| 6640 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 6641 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6642 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 6643 | emit_int16((unsigned char)0xFE, (0xC0 | encode)); | |||
| 6644 | } | |||
| 6645 | ||||
| 6646 | void Assembler::paddd(XMMRegister dst, Address src) { | |||
| 6647 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 6648 | InstructionMark im(this); | |||
| 6649 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6650 | simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 6651 | emit_int8((unsigned char)0xFE); | |||
| 6652 | emit_operand(dst, src); | |||
| 6653 | } | |||
| 6654 | ||||
| 6655 | void Assembler::paddq(XMMRegister dst, XMMRegister src) { | |||
| 6656 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 6657 | InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6658 | attributes.set_rex_vex_w_reverted(); | |||
| 6659 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 6660 | emit_int16((unsigned char)0xD4, (0xC0 | encode)); | |||
| 6661 | } | |||
| 6662 | ||||
| 6663 | void Assembler::phaddw(XMMRegister dst, XMMRegister src) { | |||
| 6664 | assert(VM_Version::supports_sse3(), "")do { if (!(VM_Version::supports_sse3())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6664, "assert(" "VM_Version::supports_sse3()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 6665 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6666 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 6667 | emit_int16(0x01, (0xC0 | encode)); | |||
| 6668 | } | |||
| 6669 | ||||
| 6670 | void Assembler::phaddd(XMMRegister dst, XMMRegister src) { | |||
| 6671 | assert(VM_Version::supports_sse3(), "")do { if (!(VM_Version::supports_sse3())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6671, "assert(" "VM_Version::supports_sse3()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 6672 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6673 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 6674 | emit_int16(0x02, (0xC0 | encode)); | |||
| 6675 | } | |||
| 6676 | ||||
| 6677 | void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 6678 | assert(UseAVX > 0, "requires some form of AVX")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6678, "assert(" "UseAVX > 0" ") failed", "requires some form of AVX" ); ::breakpoint(); } } while (0); | |||
| 6679 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6680 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 6681 | emit_int16((unsigned char)0xFC, (0xC0 | encode)); | |||
| 6682 | } | |||
| 6683 | ||||
| 6684 | void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 6685 | assert(UseAVX > 0, "requires some form of AVX")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6685, "assert(" "UseAVX > 0" ") failed", "requires some form of AVX" ); ::breakpoint(); } } while (0); | |||
| 6686 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6687 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 6688 | emit_int16((unsigned char)0xFD, (0xC0 | encode)); | |||
| 6689 | } | |||
| 6690 | ||||
| 6691 | void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 6692 | assert(UseAVX > 0, "requires some form of AVX")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6692, "assert(" "UseAVX > 0" ") failed", "requires some form of AVX" ); ::breakpoint(); } } while (0); | |||
| 6693 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6694 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 6695 | emit_int16((unsigned char)0xFE, (0xC0 | encode)); | |||
| 6696 | } | |||
| 6697 | ||||
| 6698 | void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 6699 | assert(UseAVX > 0, "requires some form of AVX")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6699, "assert(" "UseAVX > 0" ") failed", "requires some form of AVX" ); ::breakpoint(); } } while (0); | |||
| 6700 | InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6701 | attributes.set_rex_vex_w_reverted(); | |||
| 6702 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 6703 | emit_int16((unsigned char)0xD4, (0xC0 | encode)); | |||
| 6704 | } | |||
| 6705 | ||||
| 6706 | void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { | |||
| 6707 | assert(UseAVX > 0, "requires some form of AVX")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6707, "assert(" "UseAVX > 0" ") failed", "requires some form of AVX" ); ::breakpoint(); } } while (0); | |||
| 6708 | InstructionMark im(this); | |||
| 6709 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6710 | attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); | |||
| 6711 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 6712 | emit_int8((unsigned char)0xFC); | |||
| 6713 | emit_operand(dst, src); | |||
| 6714 | } | |||
| 6715 | ||||
| 6716 | void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { | |||
| 6717 | assert(UseAVX > 0, "requires some form of AVX")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6717, "assert(" "UseAVX > 0" ") failed", "requires some form of AVX" ); ::breakpoint(); } } while (0); | |||
| 6718 | InstructionMark im(this); | |||
| 6719 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6720 | attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); | |||
| 6721 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 6722 | emit_int8((unsigned char)0xFD); | |||
| 6723 | emit_operand(dst, src); | |||
| 6724 | } | |||
| 6725 | ||||
| 6726 | void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { | |||
| 6727 | assert(UseAVX > 0, "requires some form of AVX")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6727, "assert(" "UseAVX > 0" ") failed", "requires some form of AVX" ); ::breakpoint(); } } while (0); | |||
| 6728 | InstructionMark im(this); | |||
| 6729 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6730 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); | |||
| 6731 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 6732 | emit_int8((unsigned char)0xFE); | |||
| 6733 | emit_operand(dst, src); | |||
| 6734 | } | |||
| 6735 | ||||
| 6736 | void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { | |||
| 6737 | assert(UseAVX > 0, "requires some form of AVX")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6737, "assert(" "UseAVX > 0" ") failed", "requires some form of AVX" ); ::breakpoint(); } } while (0); | |||
| 6738 | InstructionMark im(this); | |||
| 6739 | InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6740 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); | |||
| 6741 | attributes.set_rex_vex_w_reverted(); | |||
| 6742 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 6743 | emit_int8((unsigned char)0xD4); | |||
| 6744 | emit_operand(dst, src); | |||
| 6745 | } | |||
| 6746 | ||||
| 6747 | void Assembler::psubb(XMMRegister dst, XMMRegister src) { | |||
| 6748 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 6749 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6750 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 6751 | emit_int16((unsigned char)0xF8, (0xC0 | encode)); | |||
| 6752 | } | |||
| 6753 | ||||
| 6754 | void Assembler::psubw(XMMRegister dst, XMMRegister src) { | |||
| 6755 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 6756 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6757 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 6758 | emit_int16((unsigned char)0xF9, (0xC0 | encode)); | |||
| 6759 | } | |||
| 6760 | ||||
| 6761 | void Assembler::psubd(XMMRegister dst, XMMRegister src) { | |||
| 6762 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6763 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 6764 | emit_int16((unsigned char)0xFA, (0xC0 | encode)); | |||
| 6765 | } | |||
| 6766 | ||||
| 6767 | void Assembler::psubq(XMMRegister dst, XMMRegister src) { | |||
| 6768 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 6769 | InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6770 | attributes.set_rex_vex_w_reverted(); | |||
| 6771 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 6772 | emit_int8((unsigned char)0xFB); | |||
| 6773 | emit_int8((0xC0 | encode)); | |||
| 6774 | } | |||
| 6775 | ||||
| 6776 | void Assembler::vpsubusb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 6777 | assert(UseAVX > 0, "requires some form of AVX")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6777, "assert(" "UseAVX > 0" ") failed", "requires some form of AVX" ); ::breakpoint(); } } while (0); | |||
| 6778 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6779 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 6780 | emit_int16((unsigned char)0xD8, (0xC0 | encode)); | |||
| 6781 | } | |||
| 6782 | ||||
| 6783 | void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 6784 | assert(UseAVX > 0, "requires some form of AVX")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6784, "assert(" "UseAVX > 0" ") failed", "requires some form of AVX" ); ::breakpoint(); } } while (0); | |||
| 6785 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6786 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 6787 | emit_int16((unsigned char)0xF8, (0xC0 | encode)); | |||
| 6788 | } | |||
| 6789 | ||||
| 6790 | void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 6791 | assert(UseAVX > 0, "requires some form of AVX")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6791, "assert(" "UseAVX > 0" ") failed", "requires some form of AVX" ); ::breakpoint(); } } while (0); | |||
| 6792 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6793 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 6794 | emit_int16((unsigned char)0xF9, (0xC0 | encode)); | |||
| 6795 | } | |||
| 6796 | ||||
| 6797 | void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 6798 | assert(UseAVX > 0, "requires some form of AVX")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6798, "assert(" "UseAVX > 0" ") failed", "requires some form of AVX" ); ::breakpoint(); } } while (0); | |||
| 6799 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6800 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 6801 | emit_int16((unsigned char)0xFA, (0xC0 | encode)); | |||
| 6802 | } | |||
| 6803 | ||||
| 6804 | void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 6805 | assert(UseAVX > 0, "requires some form of AVX")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6805, "assert(" "UseAVX > 0" ") failed", "requires some form of AVX" ); ::breakpoint(); } } while (0); | |||
| 6806 | InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6807 | attributes.set_rex_vex_w_reverted(); | |||
| 6808 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 6809 | emit_int16((unsigned char)0xFB, (0xC0 | encode)); | |||
| 6810 | } | |||
| 6811 | ||||
| 6812 | void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { | |||
| 6813 | assert(UseAVX > 0, "requires some form of AVX")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6813, "assert(" "UseAVX > 0" ") failed", "requires some form of AVX" ); ::breakpoint(); } } while (0); | |||
| 6814 | InstructionMark im(this); | |||
| 6815 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6816 | attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); | |||
| 6817 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 6818 | emit_int8((unsigned char)0xF8); | |||
| 6819 | emit_operand(dst, src); | |||
| 6820 | } | |||
| 6821 | ||||
| 6822 | void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { | |||
| 6823 | assert(UseAVX > 0, "requires some form of AVX")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6823, "assert(" "UseAVX > 0" ") failed", "requires some form of AVX" ); ::breakpoint(); } } while (0); | |||
| 6824 | InstructionMark im(this); | |||
| 6825 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6826 | attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); | |||
| 6827 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 6828 | emit_int8((unsigned char)0xF9); | |||
| 6829 | emit_operand(dst, src); | |||
| 6830 | } | |||
| 6831 | ||||
| 6832 | void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { | |||
| 6833 | assert(UseAVX > 0, "requires some form of AVX")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6833, "assert(" "UseAVX > 0" ") failed", "requires some form of AVX" ); ::breakpoint(); } } while (0); | |||
| 6834 | InstructionMark im(this); | |||
| 6835 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6836 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); | |||
| 6837 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 6838 | emit_int8((unsigned char)0xFA); | |||
| 6839 | emit_operand(dst, src); | |||
| 6840 | } | |||
| 6841 | ||||
| 6842 | void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { | |||
| 6843 | assert(UseAVX > 0, "requires some form of AVX")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6843, "assert(" "UseAVX > 0" ") failed", "requires some form of AVX" ); ::breakpoint(); } } while (0); | |||
| 6844 | InstructionMark im(this); | |||
| 6845 | InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6846 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); | |||
| 6847 | attributes.set_rex_vex_w_reverted(); | |||
| 6848 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 6849 | emit_int8((unsigned char)0xFB); | |||
| 6850 | emit_operand(dst, src); | |||
| 6851 | } | |||
| 6852 | ||||
| 6853 | void Assembler::pmullw(XMMRegister dst, XMMRegister src) { | |||
| 6854 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 6855 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6856 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 6857 | emit_int16((unsigned char)0xD5, (0xC0 | encode)); | |||
| 6858 | } | |||
| 6859 | ||||
| 6860 | void Assembler::pmulld(XMMRegister dst, XMMRegister src) { | |||
| 6861 | assert(VM_Version::supports_sse4_1(), "")do { if (!(VM_Version::supports_sse4_1())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6861, "assert(" "VM_Version::supports_sse4_1()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 6862 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6863 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 6864 | emit_int16(0x40, (0xC0 | encode)); | |||
| 6865 | } | |||
| 6866 | ||||
| 6867 | void Assembler::pmuludq(XMMRegister dst, XMMRegister src) { | |||
| 6868 | assert(VM_Version::supports_sse2(), "")do { if (!(VM_Version::supports_sse2())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6868, "assert(" "VM_Version::supports_sse2()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 6869 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6870 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 6871 | emit_int16((unsigned char)0xF4, (0xC0 | encode)); | |||
| 6872 | } | |||
| 6873 | ||||
| 6874 | void Assembler::vpmulhuw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 6875 | assert((vector_len == AVX_128bit && VM_Version::supports_avx()) ||do { if (!((vector_len == AVX_128bit && VM_Version::supports_avx ()) || (vector_len == AVX_256bit && VM_Version::supports_avx2 ()) || (vector_len == AVX_512bit && VM_Version::supports_avx512bw ()))) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6877, "assert(" "(vector_len == AVX_128bit && VM_Version::supports_avx()) || (vector_len == AVX_256bit && VM_Version::supports_avx2()) || (vector_len == AVX_512bit && VM_Version::supports_avx512bw())" ") failed", ""); ::breakpoint(); } } while (0) | |||
| 6876 | (vector_len == AVX_256bit && VM_Version::supports_avx2()) ||do { if (!((vector_len == AVX_128bit && VM_Version::supports_avx ()) || (vector_len == AVX_256bit && VM_Version::supports_avx2 ()) || (vector_len == AVX_512bit && VM_Version::supports_avx512bw ()))) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6877, "assert(" "(vector_len == AVX_128bit && VM_Version::supports_avx()) || (vector_len == AVX_256bit && VM_Version::supports_avx2()) || (vector_len == AVX_512bit && VM_Version::supports_avx512bw())" ") failed", ""); ::breakpoint(); } } while (0) | |||
| 6877 | (vector_len == AVX_512bit && VM_Version::supports_avx512bw()), "")do { if (!((vector_len == AVX_128bit && VM_Version::supports_avx ()) || (vector_len == AVX_256bit && VM_Version::supports_avx2 ()) || (vector_len == AVX_512bit && VM_Version::supports_avx512bw ()))) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6877, "assert(" "(vector_len == AVX_128bit && VM_Version::supports_avx()) || (vector_len == AVX_256bit && VM_Version::supports_avx2()) || (vector_len == AVX_512bit && VM_Version::supports_avx512bw())" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 6878 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6879 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 6880 | emit_int16((unsigned char)0xE4, (0xC0 | encode)); | |||
| 6881 | } | |||
| 6882 | ||||
| 6883 | void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 6884 | assert(UseAVX > 0, "requires some form of AVX")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6884, "assert(" "UseAVX > 0" ") failed", "requires some form of AVX" ); ::breakpoint(); } } while (0); | |||
| 6885 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6886 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 6887 | emit_int16((unsigned char)0xD5, (0xC0 | encode)); | |||
| 6888 | } | |||
| 6889 | ||||
| 6890 | void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 6891 | assert(UseAVX > 0, "requires some form of AVX")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6891, "assert(" "UseAVX > 0" ") failed", "requires some form of AVX" ); ::breakpoint(); } } while (0); | |||
| 6892 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6893 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 6894 | emit_int16(0x40, (0xC0 | encode)); | |||
| 6895 | } | |||
| 6896 | ||||
| 6897 | void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 6898 | assert(UseAVX > 2, "requires some form of EVEX")do { if (!(UseAVX > 2)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6898, "assert(" "UseAVX > 2" ") failed", "requires some form of EVEX" ); ::breakpoint(); } } while (0); | |||
| 6899 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6900 | attributes.set_is_evex_instruction(); | |||
| 6901 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 6902 | emit_int16(0x40, (0xC0 | encode)); | |||
| 6903 | } | |||
| 6904 | ||||
| 6905 | void Assembler::vpmuludq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 6906 | assert(UseAVX > 0, "requires some form of AVX")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6906, "assert(" "UseAVX > 0" ") failed", "requires some form of AVX" ); ::breakpoint(); } } while (0); | |||
| 6907 | InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6908 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 6909 | emit_int16((unsigned char)0xF4, (0xC0 | encode)); | |||
| 6910 | } | |||
| 6911 | ||||
| 6912 | void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { | |||
| 6913 | assert(UseAVX > 0, "requires some form of AVX")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6913, "assert(" "UseAVX > 0" ") failed", "requires some form of AVX" ); ::breakpoint(); } } while (0); | |||
| 6914 | InstructionMark im(this); | |||
| 6915 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6916 | attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); | |||
| 6917 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 6918 | emit_int8((unsigned char)0xD5); | |||
| 6919 | emit_operand(dst, src); | |||
| 6920 | } | |||
| 6921 | ||||
| 6922 | void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { | |||
| 6923 | assert(UseAVX > 0, "requires some form of AVX")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6923, "assert(" "UseAVX > 0" ") failed", "requires some form of AVX" ); ::breakpoint(); } } while (0); | |||
| 6924 | InstructionMark im(this); | |||
| 6925 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6926 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); | |||
| 6927 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 6928 | emit_int8(0x40); | |||
| 6929 | emit_operand(dst, src); | |||
| 6930 | } | |||
| 6931 | ||||
| 6932 | void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { | |||
| 6933 | assert(UseAVX > 2, "requires some form of EVEX")do { if (!(UseAVX > 2)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6933, "assert(" "UseAVX > 2" ") failed", "requires some form of EVEX" ); ::breakpoint(); } } while (0); | |||
| 6934 | InstructionMark im(this); | |||
| 6935 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6936 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); | |||
| 6937 | attributes.set_is_evex_instruction(); | |||
| 6938 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 6939 | emit_int8(0x40); | |||
| 6940 | emit_operand(dst, src); | |||
| 6941 | } | |||
| 6942 | ||||
| 6943 | // Min, max | |||
| 6944 | void Assembler::pminsb(XMMRegister dst, XMMRegister src) { | |||
| 6945 | assert(VM_Version::supports_sse4_1(), "")do { if (!(VM_Version::supports_sse4_1())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6945, "assert(" "VM_Version::supports_sse4_1()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 6946 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6947 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 6948 | emit_int16(0x38, (0xC0 | encode)); | |||
| 6949 | } | |||
| 6950 | ||||
| 6951 | void Assembler::vpminsb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 6952 | assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :do { if (!(vector_len == AVX_128bit ? VM_Version::supports_avx () : (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_avx512bw()))) { (*g_assert_poison) = 'X' ;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6953, "assert(" "vector_len == AVX_128bit ? VM_Version::supports_avx() : (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_avx512bw())" ") failed", ""); ::breakpoint(); } } while (0) | |||
| 6953 | (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_avx512bw()), "")do { if (!(vector_len == AVX_128bit ? VM_Version::supports_avx () : (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_avx512bw()))) { (*g_assert_poison) = 'X' ;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6953, "assert(" "vector_len == AVX_128bit ? VM_Version::supports_avx() : (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_avx512bw())" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 6954 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6955 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 6956 | emit_int16(0x38, (0xC0 | encode)); | |||
| 6957 | } | |||
| 6958 | ||||
| 6959 | void Assembler::pminsw(XMMRegister dst, XMMRegister src) { | |||
| 6960 | assert(VM_Version::supports_sse2(), "")do { if (!(VM_Version::supports_sse2())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6960, "assert(" "VM_Version::supports_sse2()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 6961 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6962 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 6963 | emit_int16((unsigned char)0xEA, (0xC0 | encode)); | |||
| 6964 | } | |||
| 6965 | ||||
| 6966 | void Assembler::vpminsw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 6967 | assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :do { if (!(vector_len == AVX_128bit ? VM_Version::supports_avx () : (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_avx512bw()))) { (*g_assert_poison) = 'X' ;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6968, "assert(" "vector_len == AVX_128bit ? VM_Version::supports_avx() : (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_avx512bw())" ") failed", ""); ::breakpoint(); } } while (0) | |||
| 6968 | (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_avx512bw()), "")do { if (!(vector_len == AVX_128bit ? VM_Version::supports_avx () : (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_avx512bw()))) { (*g_assert_poison) = 'X' ;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6968, "assert(" "vector_len == AVX_128bit ? VM_Version::supports_avx() : (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_avx512bw())" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 6969 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6970 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 6971 | emit_int16((unsigned char)0xEA, (0xC0 | encode)); | |||
| 6972 | } | |||
| 6973 | ||||
| 6974 | void Assembler::pminsd(XMMRegister dst, XMMRegister src) { | |||
| 6975 | assert(VM_Version::supports_sse4_1(), "")do { if (!(VM_Version::supports_sse4_1())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6975, "assert(" "VM_Version::supports_sse4_1()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 6976 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6977 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 6978 | emit_int16(0x39, (0xC0 | encode)); | |||
| 6979 | } | |||
| 6980 | ||||
| 6981 | void Assembler::vpminsd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 6982 | assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :do { if (!(vector_len == AVX_128bit ? VM_Version::supports_avx () : (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_evex()))) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6983, "assert(" "vector_len == AVX_128bit ? VM_Version::supports_avx() : (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_evex())" ") failed", ""); ::breakpoint(); } } while (0) | |||
| 6983 | (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_evex()), "")do { if (!(vector_len == AVX_128bit ? VM_Version::supports_avx () : (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_evex()))) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6983, "assert(" "vector_len == AVX_128bit ? VM_Version::supports_avx() : (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_evex())" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 6984 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6985 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 6986 | emit_int16(0x39, (0xC0 | encode)); | |||
| 6987 | } | |||
| 6988 | ||||
| 6989 | void Assembler::vpminsq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 6990 | assert(UseAVX > 2, "requires AVX512F")do { if (!(UseAVX > 2)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 6990, "assert(" "UseAVX > 2" ") failed", "requires AVX512F" ); ::breakpoint(); } } while (0); | |||
| 6991 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 6992 | attributes.set_is_evex_instruction(); | |||
| 6993 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 6994 | emit_int16(0x39, (0xC0 | encode)); | |||
| 6995 | } | |||
| 6996 | ||||
| 6997 | void Assembler::minps(XMMRegister dst, XMMRegister src) { | |||
| 6998 | NOT_LP64(assert(VM_Version::supports_sse(), "")); | |||
| 6999 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7000 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 7001 | emit_int16(0x5D, (0xC0 | encode)); | |||
| 7002 | } | |||
| 7003 | void Assembler::vminps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 7004 | assert(vector_len >= AVX_512bit ? VM_Version::supports_evex() : VM_Version::supports_avx(), "")do { if (!(vector_len >= AVX_512bit ? VM_Version::supports_evex () : VM_Version::supports_avx())) { (*g_assert_poison) = 'X'; ; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7004, "assert(" "vector_len >= AVX_512bit ? VM_Version::supports_evex() : VM_Version::supports_avx()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 7005 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7006 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 7007 | emit_int16(0x5D, (0xC0 | encode)); | |||
| 7008 | } | |||
| 7009 | ||||
| 7010 | void Assembler::minpd(XMMRegister dst, XMMRegister src) { | |||
| 7011 | NOT_LP64(assert(VM_Version::supports_sse(), "")); | |||
| 7012 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7013 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7014 | emit_int16(0x5D, (0xC0 | encode)); | |||
| 7015 | } | |||
| 7016 | void Assembler::vminpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 7017 | assert(vector_len >= AVX_512bit ? VM_Version::supports_evex() : VM_Version::supports_avx(), "")do { if (!(vector_len >= AVX_512bit ? VM_Version::supports_evex () : VM_Version::supports_avx())) { (*g_assert_poison) = 'X'; ; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7017, "assert(" "vector_len >= AVX_512bit ? VM_Version::supports_evex() : VM_Version::supports_avx()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 7018 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7019 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7020 | emit_int16(0x5D, (0xC0 | encode)); | |||
| 7021 | } | |||
| 7022 | ||||
| 7023 | void Assembler::pmaxsb(XMMRegister dst, XMMRegister src) { | |||
| 7024 | assert(VM_Version::supports_sse4_1(), "")do { if (!(VM_Version::supports_sse4_1())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7024, "assert(" "VM_Version::supports_sse4_1()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 7025 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7026 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 7027 | emit_int16(0x3C, (0xC0 | encode)); | |||
| 7028 | } | |||
| 7029 | ||||
| 7030 | void Assembler::vpmaxsb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 7031 | assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :do { if (!(vector_len == AVX_128bit ? VM_Version::supports_avx () : (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_avx512bw()))) { (*g_assert_poison) = 'X' ;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7032, "assert(" "vector_len == AVX_128bit ? VM_Version::supports_avx() : (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_avx512bw())" ") failed", ""); ::breakpoint(); } } while (0) | |||
| 7032 | (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_avx512bw()), "")do { if (!(vector_len == AVX_128bit ? VM_Version::supports_avx () : (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_avx512bw()))) { (*g_assert_poison) = 'X' ;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7032, "assert(" "vector_len == AVX_128bit ? VM_Version::supports_avx() : (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_avx512bw())" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 7033 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7034 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 7035 | emit_int16(0x3C, (0xC0 | encode)); | |||
| 7036 | } | |||
| 7037 | ||||
| 7038 | void Assembler::pmaxsw(XMMRegister dst, XMMRegister src) { | |||
| 7039 | assert(VM_Version::supports_sse2(), "")do { if (!(VM_Version::supports_sse2())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7039, "assert(" "VM_Version::supports_sse2()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 7040 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7041 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7042 | emit_int16((unsigned char)0xEE, (0xC0 | encode)); | |||
| 7043 | } | |||
| 7044 | ||||
| 7045 | void Assembler::vpmaxsw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 7046 | assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :do { if (!(vector_len == AVX_128bit ? VM_Version::supports_avx () : (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_avx512bw()))) { (*g_assert_poison) = 'X' ;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7047, "assert(" "vector_len == AVX_128bit ? VM_Version::supports_avx() : (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_avx512bw())" ") failed", ""); ::breakpoint(); } } while (0) | |||
| 7047 | (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_avx512bw()), "")do { if (!(vector_len == AVX_128bit ? VM_Version::supports_avx () : (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_avx512bw()))) { (*g_assert_poison) = 'X' ;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7047, "assert(" "vector_len == AVX_128bit ? VM_Version::supports_avx() : (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_avx512bw())" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 7048 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7049 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7050 | emit_int16((unsigned char)0xEE, (0xC0 | encode)); | |||
| 7051 | } | |||
| 7052 | ||||
| 7053 | void Assembler::pmaxsd(XMMRegister dst, XMMRegister src) { | |||
| 7054 | assert(VM_Version::supports_sse4_1(), "")do { if (!(VM_Version::supports_sse4_1())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7054, "assert(" "VM_Version::supports_sse4_1()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 7055 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7056 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 7057 | emit_int16(0x3D, (0xC0 | encode)); | |||
| 7058 | } | |||
| 7059 | ||||
| 7060 | void Assembler::vpmaxsd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 7061 | assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :do { if (!(vector_len == AVX_128bit ? VM_Version::supports_avx () : (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_evex()))) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7062, "assert(" "vector_len == AVX_128bit ? VM_Version::supports_avx() : (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_evex())" ") failed", ""); ::breakpoint(); } } while (0) | |||
| 7062 | (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_evex()), "")do { if (!(vector_len == AVX_128bit ? VM_Version::supports_avx () : (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_evex()))) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7062, "assert(" "vector_len == AVX_128bit ? VM_Version::supports_avx() : (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_evex())" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 7063 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7064 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 7065 | emit_int16(0x3D, (0xC0 | encode)); | |||
| 7066 | } | |||
| 7067 | ||||
| 7068 | void Assembler::vpmaxsq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 7069 | assert(UseAVX > 2, "requires AVX512F")do { if (!(UseAVX > 2)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7069, "assert(" "UseAVX > 2" ") failed", "requires AVX512F" ); ::breakpoint(); } } while (0); | |||
| 7070 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7071 | attributes.set_is_evex_instruction(); | |||
| 7072 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 7073 | emit_int16(0x3D, (0xC0 | encode)); | |||
| 7074 | } | |||
| 7075 | ||||
| 7076 | void Assembler::maxps(XMMRegister dst, XMMRegister src) { | |||
| 7077 | NOT_LP64(assert(VM_Version::supports_sse(), "")); | |||
| 7078 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7079 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 7080 | emit_int16(0x5F, (0xC0 | encode)); | |||
| 7081 | } | |||
| 7082 | ||||
| 7083 | void Assembler::vmaxps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 7084 | assert(vector_len >= AVX_512bit ? VM_Version::supports_evex() : VM_Version::supports_avx(), "")do { if (!(vector_len >= AVX_512bit ? VM_Version::supports_evex () : VM_Version::supports_avx())) { (*g_assert_poison) = 'X'; ; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7084, "assert(" "vector_len >= AVX_512bit ? VM_Version::supports_evex() : VM_Version::supports_avx()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 7085 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7086 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 7087 | emit_int16(0x5F, (0xC0 | encode)); | |||
| 7088 | } | |||
| 7089 | ||||
| 7090 | void Assembler::maxpd(XMMRegister dst, XMMRegister src) { | |||
| 7091 | NOT_LP64(assert(VM_Version::supports_sse(), "")); | |||
| 7092 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7093 | int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7094 | emit_int16(0x5F, (0xC0 | encode)); | |||
| 7095 | } | |||
| 7096 | ||||
| 7097 | void Assembler::vmaxpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 7098 | assert(vector_len >= AVX_512bit ? VM_Version::supports_evex() : VM_Version::supports_avx(), "")do { if (!(vector_len >= AVX_512bit ? VM_Version::supports_evex () : VM_Version::supports_avx())) { (*g_assert_poison) = 'X'; ; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7098, "assert(" "vector_len >= AVX_512bit ? VM_Version::supports_evex() : VM_Version::supports_avx()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 7099 | InstructionAttr attributes(vector_len, /* vex_w */true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7100 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7101 | emit_int16(0x5F, (0xC0 | encode)); | |||
| 7102 | } | |||
| 7103 | ||||
| 7104 | // Shift packed integers left by specified number of bits. | |||
| 7105 | void Assembler::psllw(XMMRegister dst, int shift) { | |||
| 7106 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 7107 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7108 | // XMM6 is for /6 encoding: 66 0F 71 /6 ib | |||
| 7109 | int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7110 | emit_int24(0x71, (0xC0 | encode), shift & 0xFF); | |||
| 7111 | } | |||
| 7112 | ||||
| 7113 | void Assembler::pslld(XMMRegister dst, int shift) { | |||
| 7114 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 7115 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7116 | // XMM6 is for /6 encoding: 66 0F 72 /6 ib | |||
| 7117 | int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7118 | emit_int24(0x72, (0xC0 | encode), shift & 0xFF); | |||
| 7119 | } | |||
| 7120 | ||||
| 7121 | void Assembler::psllq(XMMRegister dst, int shift) { | |||
| 7122 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 7123 | InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7124 | // XMM6 is for /6 encoding: 66 0F 73 /6 ib | |||
| 7125 | int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7126 | emit_int24(0x73, (0xC0 | encode), shift & 0xFF); | |||
| 7127 | } | |||
| 7128 | ||||
| 7129 | void Assembler::psllw(XMMRegister dst, XMMRegister shift) { | |||
| 7130 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 7131 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7132 | int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7133 | emit_int16((unsigned char)0xF1, (0xC0 | encode)); | |||
| 7134 | } | |||
| 7135 | ||||
| 7136 | void Assembler::pslld(XMMRegister dst, XMMRegister shift) { | |||
| 7137 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 7138 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7139 | int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7140 | emit_int16((unsigned char)0xF2, (0xC0 | encode)); | |||
| 7141 | } | |||
| 7142 | ||||
| 7143 | void Assembler::psllq(XMMRegister dst, XMMRegister shift) { | |||
| 7144 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 7145 | InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7146 | attributes.set_rex_vex_w_reverted(); | |||
| 7147 | int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7148 | emit_int16((unsigned char)0xF3, (0xC0 | encode)); | |||
| 7149 | } | |||
| 7150 | ||||
| 7151 | void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len) { | |||
| 7152 | assert(UseAVX > 0, "requires some form of AVX")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7152, "assert(" "UseAVX > 0" ") failed", "requires some form of AVX" ); ::breakpoint(); } } while (0); | |||
| 7153 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7154 | // XMM6 is for /6 encoding: 66 0F 71 /6 ib | |||
| 7155 | int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7156 | emit_int24(0x71, (0xC0 | encode), shift & 0xFF); | |||
| 7157 | } | |||
| 7158 | ||||
| 7159 | void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len) { | |||
| 7160 | assert(UseAVX > 0, "requires some form of AVX")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7160, "assert(" "UseAVX > 0" ") failed", "requires some form of AVX" ); ::breakpoint(); } } while (0); | |||
| 7161 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 7162 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7163 | // XMM6 is for /6 encoding: 66 0F 72 /6 ib | |||
| 7164 | int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7165 | emit_int24(0x72, (0xC0 | encode), shift & 0xFF); | |||
| 7166 | } | |||
| 7167 | ||||
| 7168 | void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len) { | |||
| 7169 | assert(UseAVX > 0, "requires some form of AVX")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7169, "assert(" "UseAVX > 0" ") failed", "requires some form of AVX" ); ::breakpoint(); } } while (0); | |||
| 7170 | InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7171 | attributes.set_rex_vex_w_reverted(); | |||
| 7172 | // XMM6 is for /6 encoding: 66 0F 73 /6 ib | |||
| 7173 | int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7174 | emit_int24(0x73, (0xC0 | encode), shift & 0xFF); | |||
| 7175 | } | |||
| 7176 | ||||
| 7177 | void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { | |||
| 7178 | assert(UseAVX > 0, "requires some form of AVX")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7178, "assert(" "UseAVX > 0" ") failed", "requires some form of AVX" ); ::breakpoint(); } } while (0); | |||
| 7179 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7180 | int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7181 | emit_int16((unsigned char)0xF1, (0xC0 | encode)); | |||
| 7182 | } | |||
| 7183 | ||||
| 7184 | void Assembler::vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { | |||
| 7185 | assert(UseAVX > 0, "requires some form of AVX")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7185, "assert(" "UseAVX > 0" ") failed", "requires some form of AVX" ); ::breakpoint(); } } while (0); | |||
| 7186 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7187 | int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7188 | emit_int16((unsigned char)0xF2, (0xC0 | encode)); | |||
| 7189 | } | |||
| 7190 | ||||
| 7191 | void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { | |||
| 7192 | assert(UseAVX > 0, "requires some form of AVX")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7192, "assert(" "UseAVX > 0" ") failed", "requires some form of AVX" ); ::breakpoint(); } } while (0); | |||
| 7193 | InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7194 | attributes.set_rex_vex_w_reverted(); | |||
| 7195 | int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7196 | emit_int16((unsigned char)0xF3, (0xC0 | encode)); | |||
| 7197 | } | |||
| 7198 | ||||
| 7199 | // Shift packed integers logically right by specified number of bits. | |||
| 7200 | void Assembler::psrlw(XMMRegister dst, int shift) { | |||
| 7201 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 7202 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7203 | // XMM2 is for /2 encoding: 66 0F 71 /2 ib | |||
| 7204 | int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7205 | emit_int24(0x71, (0xC0 | encode), shift & 0xFF); | |||
| 7206 | } | |||
| 7207 | ||||
| 7208 | void Assembler::psrld(XMMRegister dst, int shift) { | |||
| 7209 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 7210 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7211 | // XMM2 is for /2 encoding: 66 0F 72 /2 ib | |||
| 7212 | int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7213 | emit_int24(0x72, (0xC0 | encode), shift & 0xFF); | |||
| 7214 | } | |||
| 7215 | ||||
| 7216 | void Assembler::psrlq(XMMRegister dst, int shift) { | |||
| 7217 | // Do not confuse it with psrldq SSE2 instruction which | |||
| 7218 | // shifts 128 bit value in xmm register by number of bytes. | |||
| 7219 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 7220 | InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7221 | attributes.set_rex_vex_w_reverted(); | |||
| 7222 | // XMM2 is for /2 encoding: 66 0F 73 /2 ib | |||
| 7223 | int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7224 | emit_int24(0x73, (0xC0 | encode), shift & 0xFF); | |||
| 7225 | } | |||
| 7226 | ||||
| 7227 | void Assembler::psrlw(XMMRegister dst, XMMRegister shift) { | |||
| 7228 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 7229 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7230 | int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7231 | emit_int16((unsigned char)0xD1, (0xC0 | encode)); | |||
| 7232 | } | |||
| 7233 | ||||
| 7234 | void Assembler::psrld(XMMRegister dst, XMMRegister shift) { | |||
| 7235 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 7236 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7237 | int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7238 | emit_int16((unsigned char)0xD2, (0xC0 | encode)); | |||
| 7239 | } | |||
| 7240 | ||||
| 7241 | void Assembler::psrlq(XMMRegister dst, XMMRegister shift) { | |||
| 7242 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 7243 | InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7244 | attributes.set_rex_vex_w_reverted(); | |||
| 7245 | int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7246 | emit_int16((unsigned char)0xD3, (0xC0 | encode)); | |||
| 7247 | } | |||
| 7248 | ||||
| 7249 | void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len) { | |||
| 7250 | assert(UseAVX > 0, "requires some form of AVX")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7250, "assert(" "UseAVX > 0" ") failed", "requires some form of AVX" ); ::breakpoint(); } } while (0); | |||
| 7251 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7252 | // XMM2 is for /2 encoding: 66 0F 71 /2 ib | |||
| 7253 | int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7254 | emit_int24(0x71, (0xC0 | encode), shift & 0xFF); | |||
| 7255 | } | |||
| 7256 | ||||
| 7257 | void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len) { | |||
| 7258 | assert(UseAVX > 0, "requires some form of AVX")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7258, "assert(" "UseAVX > 0" ") failed", "requires some form of AVX" ); ::breakpoint(); } } while (0); | |||
| 7259 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7260 | // XMM2 is for /2 encoding: 66 0F 72 /2 ib | |||
| 7261 | int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7262 | emit_int24(0x72, (0xC0 | encode), shift & 0xFF); | |||
| 7263 | } | |||
| 7264 | ||||
| 7265 | void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len) { | |||
| 7266 | assert(UseAVX > 0, "requires some form of AVX")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7266, "assert(" "UseAVX > 0" ") failed", "requires some form of AVX" ); ::breakpoint(); } } while (0); | |||
| 7267 | InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7268 | attributes.set_rex_vex_w_reverted(); | |||
| 7269 | // XMM2 is for /2 encoding: 66 0F 73 /2 ib | |||
| 7270 | int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7271 | emit_int24(0x73, (0xC0 | encode), shift & 0xFF); | |||
| 7272 | } | |||
| 7273 | ||||
| 7274 | void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { | |||
| 7275 | assert(UseAVX > 0, "requires some form of AVX")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7275, "assert(" "UseAVX > 0" ") failed", "requires some form of AVX" ); ::breakpoint(); } } while (0); | |||
| 7276 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7277 | int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7278 | emit_int16((unsigned char)0xD1, (0xC0 | encode)); | |||
| 7279 | } | |||
| 7280 | ||||
| 7281 | void Assembler::vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { | |||
| 7282 | assert(UseAVX > 0, "requires some form of AVX")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7282, "assert(" "UseAVX > 0" ") failed", "requires some form of AVX" ); ::breakpoint(); } } while (0); | |||
| 7283 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7284 | int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7285 | emit_int16((unsigned char)0xD2, (0xC0 | encode)); | |||
| 7286 | } | |||
| 7287 | ||||
| 7288 | void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { | |||
| 7289 | assert(UseAVX > 0, "requires some form of AVX")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7289, "assert(" "UseAVX > 0" ") failed", "requires some form of AVX" ); ::breakpoint(); } } while (0); | |||
| 7290 | InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7291 | attributes.set_rex_vex_w_reverted(); | |||
| 7292 | int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7293 | emit_int16((unsigned char)0xD3, (0xC0 | encode)); | |||
| 7294 | } | |||
| 7295 | ||||
| 7296 | void Assembler::evpsrlvw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 7297 | assert(VM_Version::supports_avx512bw(), "")do { if (!(VM_Version::supports_avx512bw())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7297, "assert(" "VM_Version::supports_avx512bw()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 7298 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7299 | attributes.set_is_evex_instruction(); | |||
| 7300 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 7301 | emit_int16(0x10, (0xC0 | encode)); | |||
| 7302 | } | |||
| 7303 | ||||
| 7304 | void Assembler::evpsllvw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 7305 | assert(VM_Version::supports_avx512bw(), "")do { if (!(VM_Version::supports_avx512bw())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7305, "assert(" "VM_Version::supports_avx512bw()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 7306 | InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7307 | attributes.set_is_evex_instruction(); | |||
| 7308 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 7309 | emit_int16(0x12, (0xC0 | encode)); | |||
| 7310 | } | |||
| 7311 | ||||
| 7312 | // Shift packed integers arithmetically right by specified number of bits. | |||
| 7313 | void Assembler::psraw(XMMRegister dst, int shift) { | |||
| 7314 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 7315 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7316 | // XMM4 is for /4 encoding: 66 0F 71 /4 ib | |||
| 7317 | int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7318 | emit_int24(0x71, (0xC0 | encode), shift & 0xFF); | |||
| 7319 | } | |||
| 7320 | ||||
| 7321 | void Assembler::psrad(XMMRegister dst, int shift) { | |||
| 7322 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 7323 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7324 | // XMM4 is for /4 encoding: 66 0F 72 /4 ib | |||
| 7325 | int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7326 | emit_int8(0x72); | |||
| 7327 | emit_int8((0xC0 | encode)); | |||
| 7328 | emit_int8(shift & 0xFF); | |||
| 7329 | } | |||
| 7330 | ||||
| 7331 | void Assembler::psraw(XMMRegister dst, XMMRegister shift) { | |||
| 7332 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 7333 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7334 | int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7335 | emit_int16((unsigned char)0xE1, (0xC0 | encode)); | |||
| 7336 | } | |||
| 7337 | ||||
| 7338 | void Assembler::psrad(XMMRegister dst, XMMRegister shift) { | |||
| 7339 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 7340 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7341 | int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7342 | emit_int16((unsigned char)0xE2, (0xC0 | encode)); | |||
| 7343 | } | |||
| 7344 | ||||
| 7345 | void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len) { | |||
| 7346 | assert(UseAVX > 0, "requires some form of AVX")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7346, "assert(" "UseAVX > 0" ") failed", "requires some form of AVX" ); ::breakpoint(); } } while (0); | |||
| 7347 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7348 | // XMM4 is for /4 encoding: 66 0F 71 /4 ib | |||
| 7349 | int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7350 | emit_int24(0x71, (0xC0 | encode), shift & 0xFF); | |||
| 7351 | } | |||
| 7352 | ||||
| 7353 | void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len) { | |||
| 7354 | assert(UseAVX > 0, "requires some form of AVX")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7354, "assert(" "UseAVX > 0" ") failed", "requires some form of AVX" ); ::breakpoint(); } } while (0); | |||
| 7355 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7356 | // XMM4 is for /4 encoding: 66 0F 71 /4 ib | |||
| 7357 | int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7358 | emit_int24(0x72, (0xC0 | encode), shift & 0xFF); | |||
| 7359 | } | |||
| 7360 | ||||
| 7361 | void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { | |||
| 7362 | assert(UseAVX > 0, "requires some form of AVX")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7362, "assert(" "UseAVX > 0" ") failed", "requires some form of AVX" ); ::breakpoint(); } } while (0); | |||
| 7363 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7364 | int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7365 | emit_int16((unsigned char)0xE1, (0xC0 | encode)); | |||
| 7366 | } | |||
| 7367 | ||||
| 7368 | void Assembler::vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { | |||
| 7369 | assert(UseAVX > 0, "requires some form of AVX")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7369, "assert(" "UseAVX > 0" ") failed", "requires some form of AVX" ); ::breakpoint(); } } while (0); | |||
| 7370 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7371 | int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7372 | emit_int16((unsigned char)0xE2, (0xC0 | encode)); | |||
| 7373 | } | |||
| 7374 | ||||
| 7375 | void Assembler::evpsraq(XMMRegister dst, XMMRegister src, int shift, int vector_len) { | |||
| 7376 | assert(UseAVX > 2, "requires AVX512")do { if (!(UseAVX > 2)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7376, "assert(" "UseAVX > 2" ") failed", "requires AVX512" ); ::breakpoint(); } } while (0); | |||
| 7377 | assert ((VM_Version::supports_avx512vl() || vector_len == 2), "requires AVX512vl")do { if (!((VM_Version::supports_avx512vl() || vector_len == 2 ))) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7377, "assert(" "(VM_Version::supports_avx512vl() || vector_len == 2)" ") failed", "requires AVX512vl"); ::breakpoint(); } } while ( 0); | |||
| 7378 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7379 | attributes.set_is_evex_instruction(); | |||
| 7380 | int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7381 | emit_int24((unsigned char)0x72, (0xC0 | encode), shift & 0xFF); | |||
| 7382 | } | |||
| 7383 | ||||
| 7384 | void Assembler::evpsraq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { | |||
| 7385 | assert(UseAVX > 2, "requires AVX512")do { if (!(UseAVX > 2)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7385, "assert(" "UseAVX > 2" ") failed", "requires AVX512" ); ::breakpoint(); } } while (0); | |||
| 7386 | assert ((VM_Version::supports_avx512vl() || vector_len == 2), "requires AVX512vl")do { if (!((VM_Version::supports_avx512vl() || vector_len == 2 ))) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7386, "assert(" "(VM_Version::supports_avx512vl() || vector_len == 2)" ") failed", "requires AVX512vl"); ::breakpoint(); } } while ( 0); | |||
| 7387 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7388 | attributes.set_is_evex_instruction(); | |||
| 7389 | int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7390 | emit_int16((unsigned char)0xE2, (0xC0 | encode)); | |||
| 7391 | } | |||
| 7392 | ||||
| 7393 | // logical operations packed integers | |||
| 7394 | void Assembler::pand(XMMRegister dst, XMMRegister src) { | |||
| 7395 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 7396 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7397 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7398 | emit_int16((unsigned char)0xDB, (0xC0 | encode)); | |||
| 7399 | } | |||
| 7400 | ||||
| 7401 | void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 7402 | assert(UseAVX > 0, "requires some form of AVX")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7402, "assert(" "UseAVX > 0" ") failed", "requires some form of AVX" ); ::breakpoint(); } } while (0); | |||
| 7403 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7404 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7405 | emit_int16((unsigned char)0xDB, (0xC0 | encode)); | |||
| 7406 | } | |||
| 7407 | ||||
| 7408 | void Assembler::vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { | |||
| 7409 | assert(UseAVX > 0, "requires some form of AVX")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7409, "assert(" "UseAVX > 0" ") failed", "requires some form of AVX" ); ::breakpoint(); } } while (0); | |||
| 7410 | InstructionMark im(this); | |||
| 7411 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7412 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); | |||
| 7413 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7414 | emit_int8((unsigned char)0xDB); | |||
| 7415 | emit_operand(dst, src); | |||
| 7416 | } | |||
| 7417 | ||||
| 7418 | void Assembler::vpandq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 7419 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7419, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 7420 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7421 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7422 | emit_int16((unsigned char)0xDB, (0xC0 | encode)); | |||
| 7423 | } | |||
| 7424 | ||||
| 7425 | //Variable Shift packed integers logically left. | |||
| 7426 | void Assembler::vpsllvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { | |||
| 7427 | assert(UseAVX > 1, "requires AVX2")do { if (!(UseAVX > 1)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7427, "assert(" "UseAVX > 1" ") failed", "requires AVX2" ); ::breakpoint(); } } while (0); | |||
| 7428 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7429 | int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 7430 | emit_int16(0x47, (0xC0 | encode)); | |||
| 7431 | } | |||
| 7432 | ||||
| 7433 | void Assembler::vpsllvq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { | |||
| 7434 | assert(UseAVX > 1, "requires AVX2")do { if (!(UseAVX > 1)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7434, "assert(" "UseAVX > 1" ") failed", "requires AVX2" ); ::breakpoint(); } } while (0); | |||
| 7435 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7436 | int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 7437 | emit_int16(0x47, (0xC0 | encode)); | |||
| 7438 | } | |||
| 7439 | ||||
| 7440 | //Variable Shift packed integers logically right. | |||
| 7441 | void Assembler::vpsrlvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { | |||
| 7442 | assert(UseAVX > 1, "requires AVX2")do { if (!(UseAVX > 1)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7442, "assert(" "UseAVX > 1" ") failed", "requires AVX2" ); ::breakpoint(); } } while (0); | |||
| 7443 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7444 | int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 7445 | emit_int16(0x45, (0xC0 | encode)); | |||
| 7446 | } | |||
| 7447 | ||||
| 7448 | void Assembler::vpsrlvq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { | |||
| 7449 | assert(UseAVX > 1, "requires AVX2")do { if (!(UseAVX > 1)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7449, "assert(" "UseAVX > 1" ") failed", "requires AVX2" ); ::breakpoint(); } } while (0); | |||
| 7450 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7451 | int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 7452 | emit_int16(0x45, (0xC0 | encode)); | |||
| 7453 | } | |||
| 7454 | ||||
| 7455 | //Variable right Shift arithmetic packed integers . | |||
| 7456 | void Assembler::vpsravd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { | |||
| 7457 | assert(UseAVX > 1, "requires AVX2")do { if (!(UseAVX > 1)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7457, "assert(" "UseAVX > 1" ") failed", "requires AVX2" ); ::breakpoint(); } } while (0); | |||
| 7458 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7459 | int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 7460 | emit_int16(0x46, (0xC0 | encode)); | |||
| 7461 | } | |||
| 7462 | ||||
| 7463 | void Assembler::evpsravw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 7464 | assert(VM_Version::supports_avx512bw(), "")do { if (!(VM_Version::supports_avx512bw())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7464, "assert(" "VM_Version::supports_avx512bw()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 7465 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7466 | attributes.set_is_evex_instruction(); | |||
| 7467 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 7468 | emit_int16(0x11, (0xC0 | encode)); | |||
| 7469 | } | |||
| 7470 | ||||
| 7471 | void Assembler::evpsravq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { | |||
| 7472 | assert(UseAVX > 2, "requires AVX512")do { if (!(UseAVX > 2)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7472, "assert(" "UseAVX > 2" ") failed", "requires AVX512" ); ::breakpoint(); } } while (0); | |||
| 7473 | assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires AVX512VL")do { if (!(vector_len == Assembler::AVX_512bit || VM_Version:: supports_avx512vl())) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7473, "assert(" "vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl()" ") failed", "requires AVX512VL"); ::breakpoint(); } } while ( 0); | |||
| 7474 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7475 | attributes.set_is_evex_instruction(); | |||
| 7476 | int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 7477 | emit_int16(0x46, (0xC0 | encode)); | |||
| 7478 | } | |||
| 7479 | ||||
| 7480 | void Assembler::vpshldvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { | |||
| 7481 | assert(VM_Version::supports_avx512_vbmi2(), "requires vbmi2")do { if (!(VM_Version::supports_avx512_vbmi2())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7481, "assert(" "VM_Version::supports_avx512_vbmi2()" ") failed" , "requires vbmi2"); ::breakpoint(); } } while (0); | |||
| 7482 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7483 | attributes.set_is_evex_instruction(); | |||
| 7484 | int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 7485 | emit_int16(0x71, (0xC0 | encode)); | |||
| 7486 | } | |||
| 7487 | ||||
| 7488 | void Assembler::vpshrdvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { | |||
| 7489 | assert(VM_Version::supports_avx512_vbmi2(), "requires vbmi2")do { if (!(VM_Version::supports_avx512_vbmi2())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7489, "assert(" "VM_Version::supports_avx512_vbmi2()" ") failed" , "requires vbmi2"); ::breakpoint(); } } while (0); | |||
| 7490 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7491 | attributes.set_is_evex_instruction(); | |||
| 7492 | int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 7493 | emit_int16(0x73, (0xC0 | encode)); | |||
| 7494 | } | |||
| 7495 | ||||
| 7496 | void Assembler::pandn(XMMRegister dst, XMMRegister src) { | |||
| 7497 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 7498 | InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7499 | attributes.set_rex_vex_w_reverted(); | |||
| 7500 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7501 | emit_int16((unsigned char)0xDF, (0xC0 | encode)); | |||
| 7502 | } | |||
| 7503 | ||||
| 7504 | void Assembler::vpandn(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 7505 | assert(UseAVX > 0, "requires some form of AVX")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7505, "assert(" "UseAVX > 0" ") failed", "requires some form of AVX" ); ::breakpoint(); } } while (0); | |||
| 7506 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7507 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7508 | emit_int16((unsigned char)0xDF, (0xC0 | encode)); | |||
| 7509 | } | |||
| 7510 | ||||
| 7511 | void Assembler::por(XMMRegister dst, XMMRegister src) { | |||
| 7512 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 7513 | InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7514 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7515 | emit_int16((unsigned char)0xEB, (0xC0 | encode)); | |||
| 7516 | } | |||
| 7517 | ||||
| 7518 | void Assembler::vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 7519 | assert(UseAVX > 0, "requires some form of AVX")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7519, "assert(" "UseAVX > 0" ") failed", "requires some form of AVX" ); ::breakpoint(); } } while (0); | |||
| 7520 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7521 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7522 | emit_int16((unsigned char)0xEB, (0xC0 | encode)); | |||
| 7523 | } | |||
| 7524 | ||||
| 7525 | void Assembler::vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { | |||
| 7526 | assert(UseAVX > 0, "requires some form of AVX")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7526, "assert(" "UseAVX > 0" ") failed", "requires some form of AVX" ); ::breakpoint(); } } while (0); | |||
| 7527 | InstructionMark im(this); | |||
| 7528 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7529 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); | |||
| 7530 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7531 | emit_int8((unsigned char)0xEB); | |||
| 7532 | emit_operand(dst, src); | |||
| 7533 | } | |||
| 7534 | ||||
| 7535 | void Assembler::vporq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 7536 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7536, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 7537 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7538 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7539 | emit_int16((unsigned char)0xEB, (0xC0 | encode)); | |||
| 7540 | } | |||
| 7541 | ||||
| 7542 | ||||
| 7543 | void Assembler::evpord(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 7544 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7544, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 7545 | // Encoding: EVEX.NDS.XXX.66.0F.W0 EB /r | |||
| 7546 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 7547 | attributes.set_is_evex_instruction(); | |||
| 7548 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 7549 | if (merge) { | |||
| 7550 | attributes.reset_is_clear_context(); | |||
| 7551 | } | |||
| 7552 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7553 | emit_int16((unsigned char)0xEB, (0xC0 | encode)); | |||
| 7554 | } | |||
| 7555 | ||||
| 7556 | void Assembler::evpord(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) { | |||
| 7557 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7557, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 7558 | // Encoding: EVEX.NDS.XXX.66.0F.W0 EB /r | |||
| 7559 | InstructionMark im(this); | |||
| 7560 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 7561 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_NObit); | |||
| 7562 | attributes.set_is_evex_instruction(); | |||
| 7563 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 7564 | if (merge) { | |||
| 7565 | attributes.reset_is_clear_context(); | |||
| 7566 | } | |||
| 7567 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7568 | emit_int8((unsigned char)0xEB); | |||
| 7569 | emit_operand(dst, src); | |||
| 7570 | } | |||
| 7571 | ||||
| 7572 | void Assembler::pxor(XMMRegister dst, XMMRegister src) { | |||
| 7573 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 7574 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7575 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7576 | emit_int16((unsigned char)0xEF, (0xC0 | encode)); | |||
| 7577 | } | |||
| 7578 | ||||
| 7579 | void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 7580 | assert(UseAVX > 0, "requires some form of AVX")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7580, "assert(" "UseAVX > 0" ") failed", "requires some form of AVX" ); ::breakpoint(); } } while (0); | |||
| 7581 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7582 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7583 | emit_int16((unsigned char)0xEF, (0xC0 | encode)); | |||
| 7584 | } | |||
| 7585 | ||||
| 7586 | void Assembler::vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { | |||
| 7587 | assert(UseAVX > 0, "requires some form of AVX")do { if (!(UseAVX > 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7587, "assert(" "UseAVX > 0" ") failed", "requires some form of AVX" ); ::breakpoint(); } } while (0); | |||
| 7588 | InstructionMark im(this); | |||
| 7589 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7590 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); | |||
| 7591 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7592 | emit_int8((unsigned char)0xEF); | |||
| 7593 | emit_operand(dst, src); | |||
| 7594 | } | |||
| 7595 | ||||
| 7596 | void Assembler::vpxorq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 7597 | assert(UseAVX > 2, "requires some form of EVEX")do { if (!(UseAVX > 2)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7597, "assert(" "UseAVX > 2" ") failed", "requires some form of EVEX" ); ::breakpoint(); } } while (0); | |||
| 7598 | InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7599 | attributes.set_rex_vex_w_reverted(); | |||
| 7600 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7601 | emit_int16((unsigned char)0xEF, (0xC0 | encode)); | |||
| 7602 | } | |||
| 7603 | ||||
| 7604 | void Assembler::evpxord(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 7605 | // Encoding: EVEX.NDS.XXX.66.0F.W0 EF /r | |||
| 7606 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7606, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 7607 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 7608 | attributes.set_is_evex_instruction(); | |||
| 7609 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 7610 | if (merge) { | |||
| 7611 | attributes.reset_is_clear_context(); | |||
| 7612 | } | |||
| 7613 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7614 | emit_int16((unsigned char)0xEF, (0xC0 | encode)); | |||
| 7615 | } | |||
| 7616 | ||||
| 7617 | void Assembler::evpxord(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) { | |||
| 7618 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7618, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 7619 | InstructionMark im(this); | |||
| 7620 | InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true); | |||
| 7621 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit); | |||
| 7622 | attributes.set_is_evex_instruction(); | |||
| 7623 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 7624 | if (merge) { | |||
| 7625 | attributes.reset_is_clear_context(); | |||
| 7626 | } | |||
| 7627 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7628 | emit_int8((unsigned char)0xEF); | |||
| 7629 | emit_operand(dst, src); | |||
| 7630 | } | |||
| 7631 | ||||
| 7632 | void Assembler::evpxorq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 7633 | // Encoding: EVEX.NDS.XXX.66.0F.W1 EF /r | |||
| 7634 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7634, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 7635 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 7636 | attributes.set_is_evex_instruction(); | |||
| 7637 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 7638 | if (merge) { | |||
| 7639 | attributes.reset_is_clear_context(); | |||
| 7640 | } | |||
| 7641 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7642 | emit_int16((unsigned char)0xEF, (0xC0 | encode)); | |||
| 7643 | } | |||
| 7644 | ||||
| 7645 | void Assembler::evpxorq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) { | |||
| 7646 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7646, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 7647 | InstructionMark im(this); | |||
| 7648 | InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true); | |||
| 7649 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit); | |||
| 7650 | attributes.set_is_evex_instruction(); | |||
| 7651 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 7652 | if (merge) { | |||
| 7653 | attributes.reset_is_clear_context(); | |||
| 7654 | } | |||
| 7655 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7656 | emit_int8((unsigned char)0xEF); | |||
| 7657 | emit_operand(dst, src); | |||
| 7658 | } | |||
| 7659 | ||||
| 7660 | void Assembler::evpandd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) { | |||
| 7661 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7661, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 7662 | InstructionMark im(this); | |||
| 7663 | InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true); | |||
| 7664 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit); | |||
| 7665 | attributes.set_is_evex_instruction(); | |||
| 7666 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 7667 | if (merge) { | |||
| 7668 | attributes.reset_is_clear_context(); | |||
| 7669 | } | |||
| 7670 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7671 | emit_int8((unsigned char)0xDB); | |||
| 7672 | emit_operand(dst, src); | |||
| 7673 | } | |||
| 7674 | ||||
| 7675 | void Assembler::evpandq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 7676 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7676, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 7677 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 7678 | attributes.set_is_evex_instruction(); | |||
| 7679 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 7680 | if (merge) { | |||
| 7681 | attributes.reset_is_clear_context(); | |||
| 7682 | } | |||
| 7683 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7684 | emit_int16((unsigned char)0xDB, (0xC0 | encode)); | |||
| 7685 | } | |||
| 7686 | ||||
| 7687 | void Assembler::evpandq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) { | |||
| 7688 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7688, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 7689 | InstructionMark im(this); | |||
| 7690 | InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true); | |||
| 7691 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit); | |||
| 7692 | attributes.set_is_evex_instruction(); | |||
| 7693 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 7694 | if (merge) { | |||
| 7695 | attributes.reset_is_clear_context(); | |||
| 7696 | } | |||
| 7697 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7698 | emit_int8((unsigned char)0xDB); | |||
| 7699 | emit_operand(dst, src); | |||
| 7700 | } | |||
| 7701 | ||||
| 7702 | void Assembler::evporq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 7703 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7703, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 7704 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 7705 | attributes.set_is_evex_instruction(); | |||
| 7706 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 7707 | if (merge) { | |||
| 7708 | attributes.reset_is_clear_context(); | |||
| 7709 | } | |||
| 7710 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7711 | emit_int16((unsigned char)0xEB, (0xC0 | encode)); | |||
| 7712 | } | |||
| 7713 | ||||
| 7714 | void Assembler::evporq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) { | |||
| 7715 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7715, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 7716 | InstructionMark im(this); | |||
| 7717 | InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true); | |||
| 7718 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit); | |||
| 7719 | attributes.set_is_evex_instruction(); | |||
| 7720 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 7721 | if (merge) { | |||
| 7722 | attributes.reset_is_clear_context(); | |||
| 7723 | } | |||
| 7724 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7725 | emit_int8((unsigned char)0xEB); | |||
| 7726 | emit_operand(dst, src); | |||
| 7727 | } | |||
| 7728 | ||||
| 7729 | void Assembler::evpxorq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 7730 | assert(VM_Version::supports_evex(), "requires EVEX support")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7730, "assert(" "VM_Version::supports_evex()" ") failed", "requires EVEX support" ); ::breakpoint(); } } while (0); | |||
| 7731 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7732 | attributes.set_is_evex_instruction(); | |||
| 7733 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7734 | emit_int16((unsigned char)0xEF, (0xC0 | encode)); | |||
| 7735 | } | |||
| 7736 | ||||
| 7737 | void Assembler::evpxorq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { | |||
| 7738 | assert(VM_Version::supports_evex(), "requires EVEX support")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7738, "assert(" "VM_Version::supports_evex()" ") failed", "requires EVEX support" ); ::breakpoint(); } } while (0); | |||
| 7739 | assert(dst != xnoreg, "sanity")do { if (!(dst != xnoreg)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7739, "assert(" "dst != xnoreg" ") failed", "sanity"); ::breakpoint (); } } while (0); | |||
| 7740 | InstructionMark im(this); | |||
| 7741 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7742 | attributes.set_is_evex_instruction(); | |||
| 7743 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); | |||
| 7744 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7745 | emit_int8((unsigned char)0xEF); | |||
| 7746 | emit_operand(dst, src); | |||
| 7747 | } | |||
| 7748 | ||||
| 7749 | void Assembler::evprold(XMMRegister dst, XMMRegister src, int shift, int vector_len) { | |||
| 7750 | assert(VM_Version::supports_evex(), "requires EVEX support")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7750, "assert(" "VM_Version::supports_evex()" ") failed", "requires EVEX support" ); ::breakpoint(); } } while (0); | |||
| 7751 | assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support")do { if (!(vector_len == Assembler::AVX_512bit || VM_Version:: supports_avx512vl())) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7751, "assert(" "vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl()" ") failed", "requires VL support"); ::breakpoint(); } } while (0); | |||
| 7752 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7753 | attributes.set_is_evex_instruction(); | |||
| 7754 | int encode = vex_prefix_and_encode(xmm1->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7755 | emit_int24(0x72, (0xC0 | encode), shift & 0xFF); | |||
| 7756 | } | |||
| 7757 | ||||
| 7758 | void Assembler::evprolq(XMMRegister dst, XMMRegister src, int shift, int vector_len) { | |||
| 7759 | assert(VM_Version::supports_evex(), "requires EVEX support")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7759, "assert(" "VM_Version::supports_evex()" ") failed", "requires EVEX support" ); ::breakpoint(); } } while (0); | |||
| 7760 | assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support")do { if (!(vector_len == Assembler::AVX_512bit || VM_Version:: supports_avx512vl())) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7760, "assert(" "vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl()" ") failed", "requires VL support"); ::breakpoint(); } } while (0); | |||
| 7761 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7762 | attributes.set_is_evex_instruction(); | |||
| 7763 | int encode = vex_prefix_and_encode(xmm1->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7764 | emit_int24(0x72, (0xC0 | encode), shift & 0xFF); | |||
| 7765 | } | |||
| 7766 | ||||
| 7767 | // Register is a class, but it would be assigned numerical value. | |||
| 7768 | // "0" is assigned for xmm0. Thus we need to ignore -Wnonnull. | |||
| 7769 | PRAGMA_DIAG_PUSHGCC diagnostic push | |||
| 7770 | PRAGMA_NONNULL_IGNOREDGCC diagnostic ignored "-Wnonnull" | |||
| 7771 | void Assembler::evprord(XMMRegister dst, XMMRegister src, int shift, int vector_len) { | |||
| 7772 | assert(VM_Version::supports_evex(), "requires EVEX support")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7772, "assert(" "VM_Version::supports_evex()" ") failed", "requires EVEX support" ); ::breakpoint(); } } while (0); | |||
| 7773 | assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support")do { if (!(vector_len == Assembler::AVX_512bit || VM_Version:: supports_avx512vl())) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7773, "assert(" "vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl()" ") failed", "requires VL support"); ::breakpoint(); } } while (0); | |||
| 7774 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7775 | attributes.set_is_evex_instruction(); | |||
| 7776 | int encode = vex_prefix_and_encode(xmm0->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7777 | emit_int24(0x72, (0xC0 | encode), shift & 0xFF); | |||
| 7778 | } | |||
| 7779 | ||||
| 7780 | void Assembler::evprorq(XMMRegister dst, XMMRegister src, int shift, int vector_len) { | |||
| 7781 | assert(VM_Version::supports_evex(), "requires EVEX support")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7781, "assert(" "VM_Version::supports_evex()" ") failed", "requires EVEX support" ); ::breakpoint(); } } while (0); | |||
| 7782 | assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support")do { if (!(vector_len == Assembler::AVX_512bit || VM_Version:: supports_avx512vl())) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7782, "assert(" "vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl()" ") failed", "requires VL support"); ::breakpoint(); } } while (0); | |||
| 7783 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7784 | attributes.set_is_evex_instruction(); | |||
| 7785 | int encode = vex_prefix_and_encode(xmm0->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 7786 | emit_int24(0x72, (0xC0 | encode), shift & 0xFF); | |||
| 7787 | } | |||
| 7788 | PRAGMA_DIAG_POPGCC diagnostic pop | |||
| 7789 | ||||
| 7790 | void Assembler::evprolvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { | |||
| 7791 | assert(VM_Version::supports_evex(), "requires EVEX support")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7791, "assert(" "VM_Version::supports_evex()" ") failed", "requires EVEX support" ); ::breakpoint(); } } while (0); | |||
| 7792 | assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support")do { if (!(vector_len == Assembler::AVX_512bit || VM_Version:: supports_avx512vl())) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7792, "assert(" "vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl()" ") failed", "requires VL support"); ::breakpoint(); } } while (0); | |||
| 7793 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7794 | attributes.set_is_evex_instruction(); | |||
| 7795 | int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 7796 | emit_int16(0x15, (unsigned char)(0xC0 | encode)); | |||
| 7797 | } | |||
| 7798 | ||||
| 7799 | void Assembler::evprolvq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { | |||
| 7800 | assert(VM_Version::supports_evex(), "requires EVEX support")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7800, "assert(" "VM_Version::supports_evex()" ") failed", "requires EVEX support" ); ::breakpoint(); } } while (0); | |||
| 7801 | assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support")do { if (!(vector_len == Assembler::AVX_512bit || VM_Version:: supports_avx512vl())) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7801, "assert(" "vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl()" ") failed", "requires VL support"); ::breakpoint(); } } while (0); | |||
| 7802 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7803 | attributes.set_is_evex_instruction(); | |||
| 7804 | int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 7805 | emit_int16(0x15, (unsigned char)(0xC0 | encode)); | |||
| 7806 | } | |||
| 7807 | ||||
| 7808 | void Assembler::evprorvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { | |||
| 7809 | assert(VM_Version::supports_evex(), "requires EVEX support")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7809, "assert(" "VM_Version::supports_evex()" ") failed", "requires EVEX support" ); ::breakpoint(); } } while (0); | |||
| 7810 | assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support")do { if (!(vector_len == Assembler::AVX_512bit || VM_Version:: supports_avx512vl())) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7810, "assert(" "vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl()" ") failed", "requires VL support"); ::breakpoint(); } } while (0); | |||
| 7811 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7812 | attributes.set_is_evex_instruction(); | |||
| 7813 | int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 7814 | emit_int16(0x14, (unsigned char)(0xC0 | encode)); | |||
| 7815 | } | |||
| 7816 | ||||
| 7817 | void Assembler::evprorvq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { | |||
| 7818 | assert(VM_Version::supports_evex(), "requires EVEX support")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7818, "assert(" "VM_Version::supports_evex()" ") failed", "requires EVEX support" ); ::breakpoint(); } } while (0); | |||
| 7819 | assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support")do { if (!(vector_len == Assembler::AVX_512bit || VM_Version:: supports_avx512vl())) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7819, "assert(" "vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl()" ") failed", "requires VL support"); ::breakpoint(); } } while (0); | |||
| 7820 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7821 | attributes.set_is_evex_instruction(); | |||
| 7822 | int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 7823 | emit_int16(0x14, (unsigned char)(0xC0 | encode)); | |||
| 7824 | } | |||
| 7825 | ||||
| 7826 | void Assembler::vpternlogd(XMMRegister dst, int imm8, XMMRegister src2, XMMRegister src3, int vector_len) { | |||
| 7827 | assert(VM_Version::supports_evex(), "requires EVEX support")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7827, "assert(" "VM_Version::supports_evex()" ") failed", "requires EVEX support" ); ::breakpoint(); } } while (0); | |||
| 7828 | assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support")do { if (!(vector_len == Assembler::AVX_512bit || VM_Version:: supports_avx512vl())) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7828, "assert(" "vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl()" ") failed", "requires VL support"); ::breakpoint(); } } while (0); | |||
| 7829 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7830 | attributes.set_is_evex_instruction(); | |||
| 7831 | int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src3->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 7832 | emit_int8(0x25); | |||
| 7833 | emit_int8((unsigned char)(0xC0 | encode)); | |||
| 7834 | emit_int8(imm8); | |||
| 7835 | } | |||
| 7836 | ||||
| 7837 | void Assembler::vpternlogd(XMMRegister dst, int imm8, XMMRegister src2, Address src3, int vector_len) { | |||
| 7838 | assert(VM_Version::supports_evex(), "requires EVEX support")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7838, "assert(" "VM_Version::supports_evex()" ") failed", "requires EVEX support" ); ::breakpoint(); } } while (0); | |||
| 7839 | assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support")do { if (!(vector_len == Assembler::AVX_512bit || VM_Version:: supports_avx512vl())) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7839, "assert(" "vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl()" ") failed", "requires VL support"); ::breakpoint(); } } while (0); | |||
| 7840 | assert(dst != xnoreg, "sanity")do { if (!(dst != xnoreg)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7840, "assert(" "dst != xnoreg" ") failed", "sanity"); ::breakpoint (); } } while (0); | |||
| 7841 | InstructionMark im(this); | |||
| 7842 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7843 | attributes.set_is_evex_instruction(); | |||
| 7844 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); | |||
| 7845 | vex_prefix(src3, src2->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 7846 | emit_int8(0x25); | |||
| 7847 | emit_operand(dst, src3); | |||
| 7848 | emit_int8(imm8); | |||
| 7849 | } | |||
| 7850 | ||||
| 7851 | void Assembler::vpternlogq(XMMRegister dst, int imm8, XMMRegister src2, XMMRegister src3, int vector_len) { | |||
| 7852 | assert(VM_Version::supports_evex(), "requires EVEX support")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7852, "assert(" "VM_Version::supports_evex()" ") failed", "requires EVEX support" ); ::breakpoint(); } } while (0); | |||
| 7853 | assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support")do { if (!(vector_len == Assembler::AVX_512bit || VM_Version:: supports_avx512vl())) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7853, "assert(" "vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl()" ") failed", "requires VL support"); ::breakpoint(); } } while (0); | |||
| 7854 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7855 | attributes.set_is_evex_instruction(); | |||
| 7856 | int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src3->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 7857 | emit_int8(0x25); | |||
| 7858 | emit_int8((unsigned char)(0xC0 | encode)); | |||
| 7859 | emit_int8(imm8); | |||
| 7860 | } | |||
| 7861 | ||||
| 7862 | // vinserti forms | |||
| 7863 | ||||
| 7864 | void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) { | |||
| 7865 | assert(VM_Version::supports_avx2(), "")do { if (!(VM_Version::supports_avx2())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7865, "assert(" "VM_Version::supports_avx2()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 7866 | assert(imm8 <= 0x01, "imm8: %u", imm8)do { if (!(imm8 <= 0x01)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7866, "assert(" "imm8 <= 0x01" ") failed", "imm8: %u", imm8 ); ::breakpoint(); } } while (0); | |||
| 7867 | InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7868 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 7869 | // last byte: | |||
| 7870 | // 0x00 - insert into lower 128 bits | |||
| 7871 | // 0x01 - insert into upper 128 bits | |||
| 7872 | emit_int24(0x38, (0xC0 | encode), imm8 & 0x01); | |||
| 7873 | } | |||
| 7874 | ||||
| 7875 | void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) { | |||
| 7876 | assert(VM_Version::supports_avx2(), "")do { if (!(VM_Version::supports_avx2())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7876, "assert(" "VM_Version::supports_avx2()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 7877 | assert(dst != xnoreg, "sanity")do { if (!(dst != xnoreg)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7877, "assert(" "dst != xnoreg" ") failed", "sanity"); ::breakpoint (); } } while (0); | |||
| 7878 | assert(imm8 <= 0x01, "imm8: %u", imm8)do { if (!(imm8 <= 0x01)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7878, "assert(" "imm8 <= 0x01" ") failed", "imm8: %u", imm8 ); ::breakpoint(); } } while (0); | |||
| 7879 | InstructionMark im(this); | |||
| 7880 | InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7881 | attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit); | |||
| 7882 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 7883 | emit_int8(0x38); | |||
| 7884 | emit_operand(dst, src); | |||
| 7885 | // 0x00 - insert into lower 128 bits | |||
| 7886 | // 0x01 - insert into upper 128 bits | |||
| 7887 | emit_int8(imm8 & 0x01); | |||
| 7888 | } | |||
| 7889 | ||||
| 7890 | void Assembler::vinserti32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) { | |||
| 7891 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7891, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 7892 | assert(imm8 <= 0x03, "imm8: %u", imm8)do { if (!(imm8 <= 0x03)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7892, "assert(" "imm8 <= 0x03" ") failed", "imm8: %u", imm8 ); ::breakpoint(); } } while (0); | |||
| 7893 | InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7894 | attributes.set_is_evex_instruction(); | |||
| 7895 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 7896 | // imm8: | |||
| 7897 | // 0x00 - insert into q0 128 bits (0..127) | |||
| 7898 | // 0x01 - insert into q1 128 bits (128..255) | |||
| 7899 | // 0x02 - insert into q2 128 bits (256..383) | |||
| 7900 | // 0x03 - insert into q3 128 bits (384..511) | |||
| 7901 | emit_int24(0x38, (0xC0 | encode), imm8 & 0x03); | |||
| 7902 | } | |||
| 7903 | ||||
| 7904 | void Assembler::vinserti32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) { | |||
| 7905 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7905, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 7906 | assert(dst != xnoreg, "sanity")do { if (!(dst != xnoreg)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7906, "assert(" "dst != xnoreg" ") failed", "sanity"); ::breakpoint (); } } while (0); | |||
| 7907 | assert(imm8 <= 0x03, "imm8: %u", imm8)do { if (!(imm8 <= 0x03)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7907, "assert(" "imm8 <= 0x03" ") failed", "imm8: %u", imm8 ); ::breakpoint(); } } while (0); | |||
| 7908 | InstructionMark im(this); | |||
| 7909 | InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7910 | attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit); | |||
| 7911 | attributes.set_is_evex_instruction(); | |||
| 7912 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 7913 | emit_int8(0x18); | |||
| 7914 | emit_operand(dst, src); | |||
| 7915 | // 0x00 - insert into q0 128 bits (0..127) | |||
| 7916 | // 0x01 - insert into q1 128 bits (128..255) | |||
| 7917 | // 0x02 - insert into q2 128 bits (256..383) | |||
| 7918 | // 0x03 - insert into q3 128 bits (384..511) | |||
| 7919 | emit_int8(imm8 & 0x03); | |||
| 7920 | } | |||
| 7921 | ||||
| 7922 | void Assembler::vinserti64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) { | |||
| 7923 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7923, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 7924 | assert(imm8 <= 0x01, "imm8: %u", imm8)do { if (!(imm8 <= 0x01)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7924, "assert(" "imm8 <= 0x01" ") failed", "imm8: %u", imm8 ); ::breakpoint(); } } while (0); | |||
| 7925 | InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7926 | attributes.set_is_evex_instruction(); | |||
| 7927 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 7928 | //imm8: | |||
| 7929 | // 0x00 - insert into lower 256 bits | |||
| 7930 | // 0x01 - insert into upper 256 bits | |||
| 7931 | emit_int24(0x3A, (0xC0 | encode), imm8 & 0x01); | |||
| 7932 | } | |||
| 7933 | ||||
| 7934 | ||||
| 7935 | // vinsertf forms | |||
| 7936 | ||||
| 7937 | void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) { | |||
| 7938 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7938, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 7939 | assert(imm8 <= 0x01, "imm8: %u", imm8)do { if (!(imm8 <= 0x01)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7939, "assert(" "imm8 <= 0x01" ") failed", "imm8: %u", imm8 ); ::breakpoint(); } } while (0); | |||
| 7940 | InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7941 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 7942 | // imm8: | |||
| 7943 | // 0x00 - insert into lower 128 bits | |||
| 7944 | // 0x01 - insert into upper 128 bits | |||
| 7945 | emit_int24(0x18, (0xC0 | encode), imm8 & 0x01); | |||
| 7946 | } | |||
| 7947 | ||||
| 7948 | void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) { | |||
| 7949 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7949, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 7950 | assert(dst != xnoreg, "sanity")do { if (!(dst != xnoreg)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7950, "assert(" "dst != xnoreg" ") failed", "sanity"); ::breakpoint (); } } while (0); | |||
| 7951 | assert(imm8 <= 0x01, "imm8: %u", imm8)do { if (!(imm8 <= 0x01)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7951, "assert(" "imm8 <= 0x01" ") failed", "imm8: %u", imm8 ); ::breakpoint(); } } while (0); | |||
| 7952 | InstructionMark im(this); | |||
| 7953 | InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7954 | attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit); | |||
| 7955 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 7956 | emit_int8(0x18); | |||
| 7957 | emit_operand(dst, src); | |||
| 7958 | // 0x00 - insert into lower 128 bits | |||
| 7959 | // 0x01 - insert into upper 128 bits | |||
| 7960 | emit_int8(imm8 & 0x01); | |||
| 7961 | } | |||
| 7962 | ||||
| 7963 | void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) { | |||
| 7964 | assert(VM_Version::supports_avx2(), "")do { if (!(VM_Version::supports_avx2())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7964, "assert(" "VM_Version::supports_avx2()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 7965 | assert(imm8 <= 0x03, "imm8: %u", imm8)do { if (!(imm8 <= 0x03)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7965, "assert(" "imm8 <= 0x03" ") failed", "imm8: %u", imm8 ); ::breakpoint(); } } while (0); | |||
| 7966 | InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7967 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 7968 | // imm8: | |||
| 7969 | // 0x00 - insert into q0 128 bits (0..127) | |||
| 7970 | // 0x01 - insert into q1 128 bits (128..255) | |||
| 7971 | // 0x02 - insert into q0 128 bits (256..383) | |||
| 7972 | // 0x03 - insert into q1 128 bits (384..512) | |||
| 7973 | emit_int24(0x18, (0xC0 | encode), imm8 & 0x03); | |||
| 7974 | } | |||
| 7975 | ||||
| 7976 | void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) { | |||
| 7977 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7977, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 7978 | assert(dst != xnoreg, "sanity")do { if (!(dst != xnoreg)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7978, "assert(" "dst != xnoreg" ") failed", "sanity"); ::breakpoint (); } } while (0); | |||
| 7979 | assert(imm8 <= 0x03, "imm8: %u", imm8)do { if (!(imm8 <= 0x03)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7979, "assert(" "imm8 <= 0x03" ") failed", "imm8: %u", imm8 ); ::breakpoint(); } } while (0); | |||
| 7980 | InstructionMark im(this); | |||
| 7981 | InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7982 | attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit); | |||
| 7983 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 7984 | emit_int8(0x18); | |||
| 7985 | emit_operand(dst, src); | |||
| 7986 | // 0x00 - insert into q0 128 bits (0..127) | |||
| 7987 | // 0x01 - insert into q1 128 bits (128..255) | |||
| 7988 | // 0x02 - insert into q0 128 bits (256..383) | |||
| 7989 | // 0x03 - insert into q1 128 bits (384..512) | |||
| 7990 | emit_int8(imm8 & 0x03); | |||
| 7991 | } | |||
| 7992 | ||||
| 7993 | void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) { | |||
| 7994 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7994, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 7995 | assert(imm8 <= 0x01, "imm8: %u", imm8)do { if (!(imm8 <= 0x01)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 7995, "assert(" "imm8 <= 0x01" ") failed", "imm8: %u", imm8 ); ::breakpoint(); } } while (0); | |||
| 7996 | InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 7997 | attributes.set_is_evex_instruction(); | |||
| 7998 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 7999 | // imm8: | |||
| 8000 | // 0x00 - insert into lower 256 bits | |||
| 8001 | // 0x01 - insert into upper 256 bits | |||
| 8002 | emit_int24(0x1A, (0xC0 | encode), imm8 & 0x01); | |||
| 8003 | } | |||
| 8004 | ||||
| 8005 | void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) { | |||
| 8006 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8006, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 8007 | assert(dst != xnoreg, "sanity")do { if (!(dst != xnoreg)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8007, "assert(" "dst != xnoreg" ") failed", "sanity"); ::breakpoint (); } } while (0); | |||
| 8008 | assert(imm8 <= 0x01, "imm8: %u", imm8)do { if (!(imm8 <= 0x01)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8008, "assert(" "imm8 <= 0x01" ") failed", "imm8: %u", imm8 ); ::breakpoint(); } } while (0); | |||
| 8009 | InstructionMark im(this); | |||
| 8010 | InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 8011 | attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_64bit); | |||
| 8012 | attributes.set_is_evex_instruction(); | |||
| 8013 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 8014 | emit_int8(0x1A); | |||
| 8015 | emit_operand(dst, src); | |||
| 8016 | // 0x00 - insert into lower 256 bits | |||
| 8017 | // 0x01 - insert into upper 256 bits | |||
| 8018 | emit_int8(imm8 & 0x01); | |||
| 8019 | } | |||
| 8020 | ||||
| 8021 | ||||
| 8022 | // vextracti forms | |||
| 8023 | ||||
| 8024 | void Assembler::vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) { | |||
| 8025 | assert(VM_Version::supports_avx2(), "")do { if (!(VM_Version::supports_avx2())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8025, "assert(" "VM_Version::supports_avx2()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 8026 | assert(imm8 <= 0x01, "imm8: %u", imm8)do { if (!(imm8 <= 0x01)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8026, "assert(" "imm8 <= 0x01" ") failed", "imm8: %u", imm8 ); ::breakpoint(); } } while (0); | |||
| 8027 | InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 8028 | int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 8029 | // imm8: | |||
| 8030 | // 0x00 - extract from lower 128 bits | |||
| 8031 | // 0x01 - extract from upper 128 bits | |||
| 8032 | emit_int24(0x39, (0xC0 | encode), imm8 & 0x01); | |||
| 8033 | } | |||
| 8034 | ||||
| 8035 | void Assembler::vextracti128(Address dst, XMMRegister src, uint8_t imm8) { | |||
| 8036 | assert(VM_Version::supports_avx2(), "")do { if (!(VM_Version::supports_avx2())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8036, "assert(" "VM_Version::supports_avx2()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 8037 | assert(src != xnoreg, "sanity")do { if (!(src != xnoreg)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8037, "assert(" "src != xnoreg" ") failed", "sanity"); ::breakpoint (); } } while (0); | |||
| 8038 | assert(imm8 <= 0x01, "imm8: %u", imm8)do { if (!(imm8 <= 0x01)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8038, "assert(" "imm8 <= 0x01" ") failed", "imm8: %u", imm8 ); ::breakpoint(); } } while (0); | |||
| 8039 | InstructionMark im(this); | |||
| 8040 | InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 8041 | attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit); | |||
| 8042 | attributes.reset_is_clear_context(); | |||
| 8043 | vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 8044 | emit_int8(0x39); | |||
| 8045 | emit_operand(src, dst); | |||
| 8046 | // 0x00 - extract from lower 128 bits | |||
| 8047 | // 0x01 - extract from upper 128 bits | |||
| 8048 | emit_int8(imm8 & 0x01); | |||
| 8049 | } | |||
| 8050 | ||||
| 8051 | void Assembler::vextracti32x4(XMMRegister dst, XMMRegister src, uint8_t imm8) { | |||
| 8052 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8052, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 8053 | assert(imm8 <= 0x03, "imm8: %u", imm8)do { if (!(imm8 <= 0x03)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8053, "assert(" "imm8 <= 0x03" ") failed", "imm8: %u", imm8 ); ::breakpoint(); } } while (0); | |||
| 8054 | InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 8055 | attributes.set_is_evex_instruction(); | |||
| 8056 | int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 8057 | // imm8: | |||
| 8058 | // 0x00 - extract from bits 127:0 | |||
| 8059 | // 0x01 - extract from bits 255:128 | |||
| 8060 | // 0x02 - extract from bits 383:256 | |||
| 8061 | // 0x03 - extract from bits 511:384 | |||
| 8062 | emit_int24(0x39, (0xC0 | encode), imm8 & 0x03); | |||
| 8063 | } | |||
| 8064 | ||||
| 8065 | void Assembler::vextracti32x4(Address dst, XMMRegister src, uint8_t imm8) { | |||
| 8066 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8066, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 8067 | assert(src != xnoreg, "sanity")do { if (!(src != xnoreg)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8067, "assert(" "src != xnoreg" ") failed", "sanity"); ::breakpoint (); } } while (0); | |||
| 8068 | assert(imm8 <= 0x03, "imm8: %u", imm8)do { if (!(imm8 <= 0x03)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8068, "assert(" "imm8 <= 0x03" ") failed", "imm8: %u", imm8 ); ::breakpoint(); } } while (0); | |||
| 8069 | InstructionMark im(this); | |||
| 8070 | InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 8071 | attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit); | |||
| 8072 | attributes.reset_is_clear_context(); | |||
| 8073 | attributes.set_is_evex_instruction(); | |||
| 8074 | vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 8075 | emit_int8(0x39); | |||
| 8076 | emit_operand(src, dst); | |||
| 8077 | // 0x00 - extract from bits 127:0 | |||
| 8078 | // 0x01 - extract from bits 255:128 | |||
| 8079 | // 0x02 - extract from bits 383:256 | |||
| 8080 | // 0x03 - extract from bits 511:384 | |||
| 8081 | emit_int8(imm8 & 0x03); | |||
| 8082 | } | |||
| 8083 | ||||
| 8084 | void Assembler::vextracti64x2(XMMRegister dst, XMMRegister src, uint8_t imm8) { | |||
| 8085 | assert(VM_Version::supports_avx512dq(), "")do { if (!(VM_Version::supports_avx512dq())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8085, "assert(" "VM_Version::supports_avx512dq()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 8086 | assert(imm8 <= 0x03, "imm8: %u", imm8)do { if (!(imm8 <= 0x03)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8086, "assert(" "imm8 <= 0x03" ") failed", "imm8: %u", imm8 ); ::breakpoint(); } } while (0); | |||
| 8087 | InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 8088 | attributes.set_is_evex_instruction(); | |||
| 8089 | int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 8090 | // imm8: | |||
| 8091 | // 0x00 - extract from bits 127:0 | |||
| 8092 | // 0x01 - extract from bits 255:128 | |||
| 8093 | // 0x02 - extract from bits 383:256 | |||
| 8094 | // 0x03 - extract from bits 511:384 | |||
| 8095 | emit_int24(0x39, (0xC0 | encode), imm8 & 0x03); | |||
| 8096 | } | |||
| 8097 | ||||
| 8098 | void Assembler::vextracti64x4(XMMRegister dst, XMMRegister src, uint8_t imm8) { | |||
| 8099 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8099, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 8100 | assert(imm8 <= 0x01, "imm8: %u", imm8)do { if (!(imm8 <= 0x01)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8100, "assert(" "imm8 <= 0x01" ") failed", "imm8: %u", imm8 ); ::breakpoint(); } } while (0); | |||
| 8101 | InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 8102 | attributes.set_is_evex_instruction(); | |||
| 8103 | int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 8104 | // imm8: | |||
| 8105 | // 0x00 - extract from lower 256 bits | |||
| 8106 | // 0x01 - extract from upper 256 bits | |||
| 8107 | emit_int24(0x3B, (0xC0 | encode), imm8 & 0x01); | |||
| 8108 | } | |||
| 8109 | ||||
| 8110 | void Assembler::vextracti64x4(Address dst, XMMRegister src, uint8_t imm8) { | |||
| 8111 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8111, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 8112 | assert(src != xnoreg, "sanity")do { if (!(src != xnoreg)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8112, "assert(" "src != xnoreg" ") failed", "sanity"); ::breakpoint (); } } while (0); | |||
| 8113 | assert(imm8 <= 0x01, "imm8: %u", imm8)do { if (!(imm8 <= 0x01)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8113, "assert(" "imm8 <= 0x01" ") failed", "imm8: %u", imm8 ); ::breakpoint(); } } while (0); | |||
| 8114 | InstructionMark im(this); | |||
| 8115 | InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 8116 | attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_64bit); | |||
| 8117 | attributes.reset_is_clear_context(); | |||
| 8118 | attributes.set_is_evex_instruction(); | |||
| 8119 | vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 8120 | emit_int8(0x38); | |||
| 8121 | emit_operand(src, dst); | |||
| 8122 | // 0x00 - extract from lower 256 bits | |||
| 8123 | // 0x01 - extract from upper 256 bits | |||
| 8124 | emit_int8(imm8 & 0x01); | |||
| 8125 | } | |||
| 8126 | // vextractf forms | |||
| 8127 | ||||
| 8128 | void Assembler::vextractf128(XMMRegister dst, XMMRegister src, uint8_t imm8) { | |||
| 8129 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8129, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 8130 | assert(imm8 <= 0x01, "imm8: %u", imm8)do { if (!(imm8 <= 0x01)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8130, "assert(" "imm8 <= 0x01" ") failed", "imm8: %u", imm8 ); ::breakpoint(); } } while (0); | |||
| 8131 | InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 8132 | int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 8133 | // imm8: | |||
| 8134 | // 0x00 - extract from lower 128 bits | |||
| 8135 | // 0x01 - extract from upper 128 bits | |||
| 8136 | emit_int24(0x19, (0xC0 | encode), imm8 & 0x01); | |||
| 8137 | } | |||
| 8138 | ||||
| 8139 | void Assembler::vextractf128(Address dst, XMMRegister src, uint8_t imm8) { | |||
| 8140 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8140, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 8141 | assert(src != xnoreg, "sanity")do { if (!(src != xnoreg)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8141, "assert(" "src != xnoreg" ") failed", "sanity"); ::breakpoint (); } } while (0); | |||
| 8142 | assert(imm8 <= 0x01, "imm8: %u", imm8)do { if (!(imm8 <= 0x01)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8142, "assert(" "imm8 <= 0x01" ") failed", "imm8: %u", imm8 ); ::breakpoint(); } } while (0); | |||
| 8143 | InstructionMark im(this); | |||
| 8144 | InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 8145 | attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit); | |||
| 8146 | attributes.reset_is_clear_context(); | |||
| 8147 | vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 8148 | emit_int8(0x19); | |||
| 8149 | emit_operand(src, dst); | |||
| 8150 | // 0x00 - extract from lower 128 bits | |||
| 8151 | // 0x01 - extract from upper 128 bits | |||
| 8152 | emit_int8(imm8 & 0x01); | |||
| 8153 | } | |||
| 8154 | ||||
| 8155 | void Assembler::vextractf32x4(XMMRegister dst, XMMRegister src, uint8_t imm8) { | |||
| 8156 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8156, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 8157 | assert(imm8 <= 0x03, "imm8: %u", imm8)do { if (!(imm8 <= 0x03)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8157, "assert(" "imm8 <= 0x03" ") failed", "imm8: %u", imm8 ); ::breakpoint(); } } while (0); | |||
| 8158 | InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 8159 | attributes.set_is_evex_instruction(); | |||
| 8160 | int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 8161 | // imm8: | |||
| 8162 | // 0x00 - extract from bits 127:0 | |||
| 8163 | // 0x01 - extract from bits 255:128 | |||
| 8164 | // 0x02 - extract from bits 383:256 | |||
| 8165 | // 0x03 - extract from bits 511:384 | |||
| 8166 | emit_int24(0x19, (0xC0 | encode), imm8 & 0x03); | |||
| 8167 | } | |||
| 8168 | ||||
| 8169 | void Assembler::vextractf32x4(Address dst, XMMRegister src, uint8_t imm8) { | |||
| 8170 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8170, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 8171 | assert(src != xnoreg, "sanity")do { if (!(src != xnoreg)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8171, "assert(" "src != xnoreg" ") failed", "sanity"); ::breakpoint (); } } while (0); | |||
| 8172 | assert(imm8 <= 0x03, "imm8: %u", imm8)do { if (!(imm8 <= 0x03)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8172, "assert(" "imm8 <= 0x03" ") failed", "imm8: %u", imm8 ); ::breakpoint(); } } while (0); | |||
| 8173 | InstructionMark im(this); | |||
| 8174 | InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 8175 | attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit); | |||
| 8176 | attributes.reset_is_clear_context(); | |||
| 8177 | attributes.set_is_evex_instruction(); | |||
| 8178 | vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 8179 | emit_int8(0x19); | |||
| 8180 | emit_operand(src, dst); | |||
| 8181 | // 0x00 - extract from bits 127:0 | |||
| 8182 | // 0x01 - extract from bits 255:128 | |||
| 8183 | // 0x02 - extract from bits 383:256 | |||
| 8184 | // 0x03 - extract from bits 511:384 | |||
| 8185 | emit_int8(imm8 & 0x03); | |||
| 8186 | } | |||
| 8187 | ||||
| 8188 | void Assembler::vextractf64x2(XMMRegister dst, XMMRegister src, uint8_t imm8) { | |||
| 8189 | assert(VM_Version::supports_avx512dq(), "")do { if (!(VM_Version::supports_avx512dq())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8189, "assert(" "VM_Version::supports_avx512dq()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 8190 | assert(imm8 <= 0x03, "imm8: %u", imm8)do { if (!(imm8 <= 0x03)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8190, "assert(" "imm8 <= 0x03" ") failed", "imm8: %u", imm8 ); ::breakpoint(); } } while (0); | |||
| 8191 | InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 8192 | attributes.set_is_evex_instruction(); | |||
| 8193 | int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 8194 | // imm8: | |||
| 8195 | // 0x00 - extract from bits 127:0 | |||
| 8196 | // 0x01 - extract from bits 255:128 | |||
| 8197 | // 0x02 - extract from bits 383:256 | |||
| 8198 | // 0x03 - extract from bits 511:384 | |||
| 8199 | emit_int24(0x19, (0xC0 | encode), imm8 & 0x03); | |||
| 8200 | } | |||
| 8201 | ||||
| 8202 | void Assembler::vextractf64x4(XMMRegister dst, XMMRegister src, uint8_t imm8) { | |||
| 8203 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8203, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 8204 | assert(imm8 <= 0x01, "imm8: %u", imm8)do { if (!(imm8 <= 0x01)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8204, "assert(" "imm8 <= 0x01" ") failed", "imm8: %u", imm8 ); ::breakpoint(); } } while (0); | |||
| 8205 | InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 8206 | attributes.set_is_evex_instruction(); | |||
| 8207 | int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 8208 | // imm8: | |||
| 8209 | // 0x00 - extract from lower 256 bits | |||
| 8210 | // 0x01 - extract from upper 256 bits | |||
| 8211 | emit_int24(0x1B, (0xC0 | encode), imm8 & 0x01); | |||
| 8212 | } | |||
| 8213 | ||||
| 8214 | void Assembler::vextractf64x4(Address dst, XMMRegister src, uint8_t imm8) { | |||
| 8215 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8215, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 8216 | assert(src != xnoreg, "sanity")do { if (!(src != xnoreg)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8216, "assert(" "src != xnoreg" ") failed", "sanity"); ::breakpoint (); } } while (0); | |||
| 8217 | assert(imm8 <= 0x01, "imm8: %u", imm8)do { if (!(imm8 <= 0x01)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8217, "assert(" "imm8 <= 0x01" ") failed", "imm8: %u", imm8 ); ::breakpoint(); } } while (0); | |||
| 8218 | InstructionMark im(this); | |||
| 8219 | InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 8220 | attributes.set_address_attributes(/* tuple_type */ EVEX_T4,/* input_size_in_bits */ EVEX_64bit); | |||
| 8221 | attributes.reset_is_clear_context(); | |||
| 8222 | attributes.set_is_evex_instruction(); | |||
| 8223 | vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 8224 | emit_int8(0x1B); | |||
| 8225 | emit_operand(src, dst); | |||
| 8226 | // 0x00 - extract from lower 256 bits | |||
| 8227 | // 0x01 - extract from upper 256 bits | |||
| 8228 | emit_int8(imm8 & 0x01); | |||
| 8229 | } | |||
| 8230 | ||||
| 8231 | // duplicate 1-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL | |||
| 8232 | void Assembler::vpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len) { | |||
| 8233 | assert(VM_Version::supports_avx2(), "")do { if (!(VM_Version::supports_avx2())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8233, "assert(" "VM_Version::supports_avx2()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 8234 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 8235 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 8236 | emit_int16(0x78, (0xC0 | encode)); | |||
| 8237 | } | |||
| 8238 | ||||
| 8239 | void Assembler::vpbroadcastb(XMMRegister dst, Address src, int vector_len) { | |||
| 8240 | assert(VM_Version::supports_avx2(), "")do { if (!(VM_Version::supports_avx2())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8240, "assert(" "VM_Version::supports_avx2()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 8241 | assert(dst != xnoreg, "sanity")do { if (!(dst != xnoreg)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8241, "assert(" "dst != xnoreg" ") failed", "sanity"); ::breakpoint (); } } while (0); | |||
| 8242 | InstructionMark im(this); | |||
| 8243 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 8244 | attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit); | |||
| 8245 | // swap src<->dst for encoding | |||
| 8246 | vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 8247 | emit_int8(0x78); | |||
| 8248 | emit_operand(dst, src); | |||
| 8249 | } | |||
| 8250 | ||||
| 8251 | // duplicate 2-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL | |||
| 8252 | void Assembler::vpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len) { | |||
| 8253 | assert(VM_Version::supports_avx2(), "")do { if (!(VM_Version::supports_avx2())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8253, "assert(" "VM_Version::supports_avx2()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 8254 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 8255 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 8256 | emit_int16(0x79, (0xC0 | encode)); | |||
| 8257 | } | |||
| 8258 | ||||
| 8259 | void Assembler::vpbroadcastw(XMMRegister dst, Address src, int vector_len) { | |||
| 8260 | assert(VM_Version::supports_avx2(), "")do { if (!(VM_Version::supports_avx2())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8260, "assert(" "VM_Version::supports_avx2()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 8261 | assert(dst != xnoreg, "sanity")do { if (!(dst != xnoreg)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8261, "assert(" "dst != xnoreg" ") failed", "sanity"); ::breakpoint (); } } while (0); | |||
| 8262 | InstructionMark im(this); | |||
| 8263 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 8264 | attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit); | |||
| 8265 | // swap src<->dst for encoding | |||
| 8266 | vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 8267 | emit_int8(0x79); | |||
| 8268 | emit_operand(dst, src); | |||
| 8269 | } | |||
| 8270 | ||||
| 8271 | // xmm/mem sourced byte/word/dword/qword replicate | |||
| 8272 | ||||
| 8273 | void Assembler::evpaddb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 8274 | assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "")do { if (!(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()))) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8274, "assert(" "VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl())" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 8275 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true); | |||
| 8276 | attributes.set_is_evex_instruction(); | |||
| 8277 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 8278 | if (merge) { | |||
| 8279 | attributes.reset_is_clear_context(); | |||
| 8280 | } | |||
| 8281 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 8282 | emit_int16((unsigned char)0xFC, (0xC0 | encode)); | |||
| 8283 | } | |||
| 8284 | ||||
| 8285 | void Assembler::evpaddb(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) { | |||
| 8286 | InstructionMark im(this); | |||
| 8287 | assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "")do { if (!(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()))) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8287, "assert(" "VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl())" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 8288 | InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true); | |||
| 8289 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit); | |||
| 8290 | attributes.set_is_evex_instruction(); | |||
| 8291 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 8292 | if (merge) { | |||
| 8293 | attributes.reset_is_clear_context(); | |||
| 8294 | } | |||
| 8295 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 8296 | emit_int8((unsigned char)0xFC); | |||
| 8297 | emit_operand(dst, src); | |||
| 8298 | } | |||
| 8299 | ||||
| 8300 | void Assembler::evpaddw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 8301 | assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "")do { if (!(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()))) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8301, "assert(" "VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl())" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 8302 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true); | |||
| 8303 | attributes.set_is_evex_instruction(); | |||
| 8304 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 8305 | if (merge) { | |||
| 8306 | attributes.reset_is_clear_context(); | |||
| 8307 | } | |||
| 8308 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 8309 | emit_int16((unsigned char)0xFD, (0xC0 | encode)); | |||
| 8310 | } | |||
| 8311 | ||||
| 8312 | void Assembler::evpaddw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) { | |||
| 8313 | InstructionMark im(this); | |||
| 8314 | assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "")do { if (!(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()))) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8314, "assert(" "VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl())" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 8315 | InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true); | |||
| 8316 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit); | |||
| 8317 | attributes.set_is_evex_instruction(); | |||
| 8318 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 8319 | if (merge) { | |||
| 8320 | attributes.reset_is_clear_context(); | |||
| 8321 | } | |||
| 8322 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 8323 | emit_int8((unsigned char)0xFD); | |||
| 8324 | emit_operand(dst, src); | |||
| 8325 | } | |||
| 8326 | ||||
| 8327 | void Assembler::evpaddd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 8328 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8328, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 8329 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8329, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 8330 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true); | |||
| 8331 | attributes.set_is_evex_instruction(); | |||
| 8332 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 8333 | if (merge) { | |||
| 8334 | attributes.reset_is_clear_context(); | |||
| 8335 | } | |||
| 8336 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 8337 | emit_int16((unsigned char)0xFE, (0xC0 | encode)); | |||
| 8338 | } | |||
| 8339 | ||||
| 8340 | void Assembler::evpaddd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) { | |||
| 8341 | InstructionMark im(this); | |||
| 8342 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8342, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 8343 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8343, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 8344 | InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true); | |||
| 8345 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit); | |||
| 8346 | attributes.set_is_evex_instruction(); | |||
| 8347 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 8348 | if (merge) { | |||
| 8349 | attributes.reset_is_clear_context(); | |||
| 8350 | } | |||
| 8351 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 8352 | emit_int8((unsigned char)0xFE); | |||
| 8353 | emit_operand(dst, src); | |||
| 8354 | } | |||
| 8355 | ||||
| 8356 | void Assembler::evpaddq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 8357 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8357, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 8358 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8358, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 8359 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true); | |||
| 8360 | attributes.set_is_evex_instruction(); | |||
| 8361 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 8362 | if (merge) { | |||
| 8363 | attributes.reset_is_clear_context(); | |||
| 8364 | } | |||
| 8365 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 8366 | emit_int16((unsigned char)0xD4, (0xC0 | encode)); | |||
| 8367 | } | |||
| 8368 | ||||
| 8369 | void Assembler::evpaddq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) { | |||
| 8370 | InstructionMark im(this); | |||
| 8371 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8371, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 8372 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8372, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 8373 | InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true); | |||
| 8374 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit); | |||
| 8375 | attributes.set_is_evex_instruction(); | |||
| 8376 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 8377 | if (merge) { | |||
| 8378 | attributes.reset_is_clear_context(); | |||
| 8379 | } | |||
| 8380 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 8381 | emit_int8((unsigned char)0xD4); | |||
| 8382 | emit_operand(dst, src); | |||
| 8383 | } | |||
| 8384 | ||||
| 8385 | void Assembler::evaddps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 8386 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8386, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 8387 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8387, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 8388 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true); | |||
| 8389 | attributes.set_is_evex_instruction(); | |||
| 8390 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 8391 | if (merge) { | |||
| 8392 | attributes.reset_is_clear_context(); | |||
| 8393 | } | |||
| 8394 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 8395 | emit_int16(0x58, (0xC0 | encode)); | |||
| 8396 | } | |||
| 8397 | ||||
| 8398 | void Assembler::evaddps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) { | |||
| 8399 | InstructionMark im(this); | |||
| 8400 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8400, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 8401 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8401, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 8402 | InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true); | |||
| 8403 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit); | |||
| 8404 | attributes.set_is_evex_instruction(); | |||
| 8405 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 8406 | if (merge) { | |||
| 8407 | attributes.reset_is_clear_context(); | |||
| 8408 | } | |||
| 8409 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 8410 | emit_int8(0x58); | |||
| 8411 | emit_operand(dst, src); | |||
| 8412 | } | |||
| 8413 | ||||
| 8414 | void Assembler::evaddpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 8415 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8415, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 8416 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8416, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 8417 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true); | |||
| 8418 | attributes.set_is_evex_instruction(); | |||
| 8419 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 8420 | if (merge) { | |||
| 8421 | attributes.reset_is_clear_context(); | |||
| 8422 | } | |||
| 8423 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 8424 | emit_int16(0x58, (0xC0 | encode)); | |||
| 8425 | } | |||
| 8426 | ||||
| 8427 | void Assembler::evaddpd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) { | |||
| 8428 | InstructionMark im(this); | |||
| 8429 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8429, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 8430 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8430, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 8431 | InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true); | |||
| 8432 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit); | |||
| 8433 | attributes.set_is_evex_instruction(); | |||
| 8434 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 8435 | if (merge) { | |||
| 8436 | attributes.reset_is_clear_context(); | |||
| 8437 | } | |||
| 8438 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 8439 | emit_int8(0x58); | |||
| 8440 | emit_operand(dst, src); | |||
| 8441 | } | |||
| 8442 | ||||
| 8443 | void Assembler::evpsubb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 8444 | assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "")do { if (!(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()))) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8444, "assert(" "VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl())" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 8445 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true); | |||
| 8446 | attributes.set_is_evex_instruction(); | |||
| 8447 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 8448 | if (merge) { | |||
| 8449 | attributes.reset_is_clear_context(); | |||
| 8450 | } | |||
| 8451 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 8452 | emit_int16((unsigned char)0xF8, (0xC0 | encode)); | |||
| 8453 | } | |||
| 8454 | ||||
| 8455 | void Assembler::evpsubb(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) { | |||
| 8456 | InstructionMark im(this); | |||
| 8457 | assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "")do { if (!(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()))) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8457, "assert(" "VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl())" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 8458 | InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true); | |||
| 8459 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit); | |||
| 8460 | attributes.set_is_evex_instruction(); | |||
| 8461 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 8462 | if (merge) { | |||
| 8463 | attributes.reset_is_clear_context(); | |||
| 8464 | } | |||
| 8465 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 8466 | emit_int8((unsigned char)0xF8); | |||
| 8467 | emit_operand(dst, src); | |||
| 8468 | } | |||
| 8469 | ||||
| 8470 | void Assembler::evpsubw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 8471 | assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "")do { if (!(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()))) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8471, "assert(" "VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl())" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 8472 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true); | |||
| 8473 | attributes.set_is_evex_instruction(); | |||
| 8474 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 8475 | if (merge) { | |||
| 8476 | attributes.reset_is_clear_context(); | |||
| 8477 | } | |||
| 8478 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 8479 | emit_int16((unsigned char)0xF9, (0xC0 | encode)); | |||
| 8480 | } | |||
| 8481 | ||||
| 8482 | void Assembler::evpsubw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) { | |||
| 8483 | InstructionMark im(this); | |||
| 8484 | assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "")do { if (!(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()))) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8484, "assert(" "VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl())" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 8485 | InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true); | |||
| 8486 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit); | |||
| 8487 | attributes.set_is_evex_instruction(); | |||
| 8488 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 8489 | if (merge) { | |||
| 8490 | attributes.reset_is_clear_context(); | |||
| 8491 | } | |||
| 8492 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 8493 | emit_int8((unsigned char)0xF9); | |||
| 8494 | emit_operand(dst, src); | |||
| 8495 | } | |||
| 8496 | ||||
| 8497 | void Assembler::evpsubd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 8498 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8498, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 8499 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8499, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 8500 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true); | |||
| 8501 | attributes.set_is_evex_instruction(); | |||
| 8502 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 8503 | if (merge) { | |||
| 8504 | attributes.reset_is_clear_context(); | |||
| 8505 | } | |||
| 8506 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 8507 | emit_int16((unsigned char)0xFA, (0xC0 | encode)); | |||
| 8508 | } | |||
| 8509 | ||||
| 8510 | void Assembler::evpsubd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) { | |||
| 8511 | InstructionMark im(this); | |||
| 8512 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8512, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 8513 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8513, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 8514 | InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true); | |||
| 8515 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit); | |||
| 8516 | attributes.set_is_evex_instruction(); | |||
| 8517 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 8518 | if (merge) { | |||
| 8519 | attributes.reset_is_clear_context(); | |||
| 8520 | } | |||
| 8521 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 8522 | emit_int8((unsigned char)0xFA); | |||
| 8523 | emit_operand(dst, src); | |||
| 8524 | } | |||
| 8525 | ||||
| 8526 | void Assembler::evpsubq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 8527 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8527, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 8528 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8528, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 8529 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true); | |||
| 8530 | attributes.set_is_evex_instruction(); | |||
| 8531 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 8532 | if (merge) { | |||
| 8533 | attributes.reset_is_clear_context(); | |||
| 8534 | } | |||
| 8535 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 8536 | emit_int16((unsigned char)0xFB, (0xC0 | encode)); | |||
| 8537 | } | |||
| 8538 | ||||
| 8539 | void Assembler::evpsubq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) { | |||
| 8540 | InstructionMark im(this); | |||
| 8541 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8541, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 8542 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8542, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 8543 | InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true); | |||
| 8544 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit); | |||
| 8545 | attributes.set_is_evex_instruction(); | |||
| 8546 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 8547 | if (merge) { | |||
| 8548 | attributes.reset_is_clear_context(); | |||
| 8549 | } | |||
| 8550 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 8551 | emit_int8((unsigned char)0xFB); | |||
| 8552 | emit_operand(dst, src); | |||
| 8553 | } | |||
| 8554 | ||||
| 8555 | void Assembler::evsubps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 8556 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8556, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 8557 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8557, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 8558 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true); | |||
| 8559 | attributes.set_is_evex_instruction(); | |||
| 8560 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 8561 | if (merge) { | |||
| 8562 | attributes.reset_is_clear_context(); | |||
| 8563 | } | |||
| 8564 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 8565 | emit_int16(0x5C, (0xC0 | encode)); | |||
| 8566 | } | |||
| 8567 | ||||
| 8568 | void Assembler::evsubps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) { | |||
| 8569 | InstructionMark im(this); | |||
| 8570 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8570, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 8571 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8571, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 8572 | InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true); | |||
| 8573 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit); | |||
| 8574 | attributes.set_is_evex_instruction(); | |||
| 8575 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 8576 | if (merge) { | |||
| 8577 | attributes.reset_is_clear_context(); | |||
| 8578 | } | |||
| 8579 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 8580 | emit_int8(0x5C); | |||
| 8581 | emit_operand(dst, src); | |||
| 8582 | } | |||
| 8583 | ||||
| 8584 | void Assembler::evsubpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 8585 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8585, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 8586 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8586, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 8587 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true); | |||
| 8588 | attributes.set_is_evex_instruction(); | |||
| 8589 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 8590 | if (merge) { | |||
| 8591 | attributes.reset_is_clear_context(); | |||
| 8592 | } | |||
| 8593 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 8594 | emit_int16(0x5C, (0xC0 | encode)); | |||
| 8595 | } | |||
| 8596 | ||||
| 8597 | void Assembler::evsubpd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) { | |||
| 8598 | InstructionMark im(this); | |||
| 8599 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8599, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 8600 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8600, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 8601 | InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true); | |||
| 8602 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit); | |||
| 8603 | attributes.set_is_evex_instruction(); | |||
| 8604 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 8605 | if (merge) { | |||
| 8606 | attributes.reset_is_clear_context(); | |||
| 8607 | } | |||
| 8608 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 8609 | emit_int8(0x5C); | |||
| 8610 | emit_operand(dst, src); | |||
| 8611 | } | |||
| 8612 | ||||
| 8613 | void Assembler::evpmullw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 8614 | assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "")do { if (!(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()))) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8614, "assert(" "VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl())" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 8615 | InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true); | |||
| 8616 | attributes.set_is_evex_instruction(); | |||
| 8617 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 8618 | if (merge) { | |||
| 8619 | attributes.reset_is_clear_context(); | |||
| 8620 | } | |||
| 8621 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 8622 | emit_int16((unsigned char)0xD5, (0xC0 | encode)); | |||
| 8623 | } | |||
| 8624 | ||||
| 8625 | void Assembler::evpmullw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) { | |||
| 8626 | InstructionMark im(this); | |||
| 8627 | assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "")do { if (!(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()))) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8627, "assert(" "VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl())" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 8628 | InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true); | |||
| 8629 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit); | |||
| 8630 | attributes.set_is_evex_instruction(); | |||
| 8631 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 8632 | if (merge) { | |||
| 8633 | attributes.reset_is_clear_context(); | |||
| 8634 | } | |||
| 8635 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 8636 | emit_int8((unsigned char)0xD5); | |||
| 8637 | emit_operand(dst, src); | |||
| 8638 | } | |||
| 8639 | ||||
| 8640 | void Assembler::evpmulld(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 8641 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8641, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 8642 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8642, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 8643 | InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true); | |||
| 8644 | attributes.set_is_evex_instruction(); | |||
| 8645 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 8646 | if (merge) { | |||
| 8647 | attributes.reset_is_clear_context(); | |||
| 8648 | } | |||
| 8649 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 8650 | emit_int16(0x40, (0xC0 | encode)); | |||
| 8651 | } | |||
| 8652 | ||||
| 8653 | void Assembler::evpmulld(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) { | |||
| 8654 | InstructionMark im(this); | |||
| 8655 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8655, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 8656 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8656, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 8657 | InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true); | |||
| 8658 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit); | |||
| 8659 | attributes.set_is_evex_instruction(); | |||
| 8660 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 8661 | if (merge) { | |||
| 8662 | attributes.reset_is_clear_context(); | |||
| 8663 | } | |||
| 8664 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 8665 | emit_int8(0x40); | |||
| 8666 | emit_operand(dst, src); | |||
| 8667 | } | |||
| 8668 | ||||
| 8669 | void Assembler::evpmullq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 8670 | assert(VM_Version::supports_avx512dq() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "")do { if (!(VM_Version::supports_avx512dq() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()))) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8670, "assert(" "VM_Version::supports_avx512dq() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl())" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 8671 | InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true); | |||
| 8672 | attributes.set_is_evex_instruction(); | |||
| 8673 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 8674 | if (merge) { | |||
| 8675 | attributes.reset_is_clear_context(); | |||
| 8676 | } | |||
| 8677 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 8678 | emit_int16(0x40, (0xC0 | encode)); | |||
| 8679 | } | |||
| 8680 | ||||
| 8681 | void Assembler::evpmullq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) { | |||
| 8682 | InstructionMark im(this); | |||
| 8683 | assert(VM_Version::supports_avx512dq() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "")do { if (!(VM_Version::supports_avx512dq() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()))) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8683, "assert(" "VM_Version::supports_avx512dq() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl())" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 8684 | InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true); | |||
| 8685 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit); | |||
| 8686 | attributes.set_is_evex_instruction(); | |||
| 8687 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 8688 | if (merge) { | |||
| 8689 | attributes.reset_is_clear_context(); | |||
| 8690 | } | |||
| 8691 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 8692 | emit_int8(0x40); | |||
| 8693 | emit_operand(dst, src); | |||
| 8694 | } | |||
| 8695 | ||||
| 8696 | void Assembler::evmulps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 8697 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8697, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 8698 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8698, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 8699 | InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true); | |||
| 8700 | attributes.set_is_evex_instruction(); | |||
| 8701 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 8702 | if (merge) { | |||
| 8703 | attributes.reset_is_clear_context(); | |||
| 8704 | } | |||
| 8705 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 8706 | emit_int16(0x59, (0xC0 | encode)); | |||
| 8707 | } | |||
| 8708 | ||||
| 8709 | void Assembler::evmulps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) { | |||
| 8710 | InstructionMark im(this); | |||
| 8711 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8711, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 8712 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8712, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 8713 | InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true); | |||
| 8714 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit); | |||
| 8715 | attributes.set_is_evex_instruction(); | |||
| 8716 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 8717 | if (merge) { | |||
| 8718 | attributes.reset_is_clear_context(); | |||
| 8719 | } | |||
| 8720 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 8721 | emit_int8(0x59); | |||
| 8722 | emit_operand(dst, src); | |||
| 8723 | } | |||
| 8724 | ||||
| 8725 | void Assembler::evmulpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 8726 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8726, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 8727 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8727, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 8728 | InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true); | |||
| 8729 | attributes.set_is_evex_instruction(); | |||
| 8730 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 8731 | if (merge) { | |||
| 8732 | attributes.reset_is_clear_context(); | |||
| 8733 | } | |||
| 8734 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 8735 | emit_int16(0x59, (0xC0 | encode)); | |||
| 8736 | } | |||
| 8737 | ||||
| 8738 | void Assembler::evmulpd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) { | |||
| 8739 | InstructionMark im(this); | |||
| 8740 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8740, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 8741 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8741, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 8742 | InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true); | |||
| 8743 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit); | |||
| 8744 | attributes.set_is_evex_instruction(); | |||
| 8745 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 8746 | if (merge) { | |||
| 8747 | attributes.reset_is_clear_context(); | |||
| 8748 | } | |||
| 8749 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 8750 | emit_int8(0x59); | |||
| 8751 | emit_operand(dst, src); | |||
| 8752 | } | |||
| 8753 | ||||
| 8754 | void Assembler::evsqrtps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 8755 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8755, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 8756 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8756, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 8757 | InstructionAttr attributes(vector_len,/* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true); | |||
| 8758 | attributes.set_is_evex_instruction(); | |||
| 8759 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 8760 | if (merge) { | |||
| 8761 | attributes.reset_is_clear_context(); | |||
| 8762 | } | |||
| 8763 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 8764 | emit_int16(0x51, (0xC0 | encode)); | |||
| 8765 | } | |||
| 8766 | ||||
| 8767 | void Assembler::evsqrtps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) { | |||
| 8768 | InstructionMark im(this); | |||
| 8769 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8769, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 8770 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8770, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 8771 | InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true); | |||
| 8772 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit); | |||
| 8773 | attributes.set_is_evex_instruction(); | |||
| 8774 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 8775 | if (merge) { | |||
| 8776 | attributes.reset_is_clear_context(); | |||
| 8777 | } | |||
| 8778 | vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 8779 | emit_int8(0x51); | |||
| 8780 | emit_operand(dst, src); | |||
| 8781 | } | |||
| 8782 | ||||
| 8783 | void Assembler::evsqrtpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 8784 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8784, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 8785 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8785, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 8786 | InstructionAttr attributes(vector_len,/* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true); | |||
| 8787 | attributes.set_is_evex_instruction(); | |||
| 8788 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 8789 | if (merge) { | |||
| 8790 | attributes.reset_is_clear_context(); | |||
| 8791 | } | |||
| 8792 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 8793 | emit_int16(0x51, (0xC0 | encode)); | |||
| 8794 | } | |||
| 8795 | ||||
| 8796 | void Assembler::evsqrtpd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) { | |||
| 8797 | InstructionMark im(this); | |||
| 8798 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8798, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 8799 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8799, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 8800 | InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true); | |||
| 8801 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit); | |||
| 8802 | attributes.set_is_evex_instruction(); | |||
| 8803 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 8804 | if (merge) { | |||
| 8805 | attributes.reset_is_clear_context(); | |||
| 8806 | } | |||
| 8807 | vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 8808 | emit_int8(0x51); | |||
| 8809 | emit_operand(dst, src); | |||
| 8810 | } | |||
| 8811 | ||||
| 8812 | ||||
| 8813 | void Assembler::evdivps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 8814 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8814, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 8815 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8815, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 8816 | InstructionAttr attributes(vector_len,/* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true); | |||
| 8817 | attributes.set_is_evex_instruction(); | |||
| 8818 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 8819 | if (merge) { | |||
| 8820 | attributes.reset_is_clear_context(); | |||
| 8821 | } | |||
| 8822 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 8823 | emit_int16(0x5E, (0xC0 | encode)); | |||
| 8824 | } | |||
| 8825 | ||||
| 8826 | void Assembler::evdivps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) { | |||
| 8827 | InstructionMark im(this); | |||
| 8828 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8828, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 8829 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8829, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 8830 | InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true); | |||
| 8831 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit); | |||
| 8832 | attributes.set_is_evex_instruction(); | |||
| 8833 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 8834 | if (merge) { | |||
| 8835 | attributes.reset_is_clear_context(); | |||
| 8836 | } | |||
| 8837 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 8838 | emit_int8(0x5E); | |||
| 8839 | emit_operand(dst, src); | |||
| 8840 | } | |||
| 8841 | ||||
| 8842 | void Assembler::evdivpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 8843 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8843, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 8844 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8844, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 8845 | InstructionAttr attributes(vector_len,/* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true); | |||
| 8846 | attributes.set_is_evex_instruction(); | |||
| 8847 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 8848 | if (merge) { | |||
| 8849 | attributes.reset_is_clear_context(); | |||
| 8850 | } | |||
| 8851 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 8852 | emit_int16(0x5E, (0xC0 | encode)); | |||
| 8853 | } | |||
| 8854 | ||||
| 8855 | void Assembler::evdivpd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) { | |||
| 8856 | InstructionMark im(this); | |||
| 8857 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8857, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 8858 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8858, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 8859 | InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true); | |||
| 8860 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit); | |||
| 8861 | attributes.set_is_evex_instruction(); | |||
| 8862 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 8863 | if (merge) { | |||
| 8864 | attributes.reset_is_clear_context(); | |||
| 8865 | } | |||
| 8866 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 8867 | emit_int8(0x5E); | |||
| 8868 | emit_operand(dst, src); | |||
| 8869 | } | |||
| 8870 | ||||
| 8871 | void Assembler::evpabsb(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) { | |||
| 8872 | assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "")do { if (!(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()))) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8872, "assert(" "VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl())" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 8873 | InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true); | |||
| 8874 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit); | |||
| 8875 | attributes.set_is_evex_instruction(); | |||
| 8876 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 8877 | if (merge) { | |||
| 8878 | attributes.reset_is_clear_context(); | |||
| 8879 | } | |||
| 8880 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 8881 | emit_int16(0x1C, (0xC0 | encode)); | |||
| 8882 | } | |||
| 8883 | ||||
| 8884 | ||||
| 8885 | void Assembler::evpabsb(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) { | |||
| 8886 | InstructionMark im(this); | |||
| 8887 | assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "")do { if (!(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()))) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8887, "assert(" "VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl())" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 8888 | InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true); | |||
| 8889 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit); | |||
| 8890 | attributes.set_is_evex_instruction(); | |||
| 8891 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 8892 | if (merge) { | |||
| 8893 | attributes.reset_is_clear_context(); | |||
| 8894 | } | |||
| 8895 | vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 8896 | emit_int8(0x1C); | |||
| 8897 | emit_operand(dst, src); | |||
| 8898 | } | |||
| 8899 | ||||
| 8900 | void Assembler::evpabsw(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) { | |||
| 8901 | assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "")do { if (!(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()))) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8901, "assert(" "VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl())" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 8902 | InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true); | |||
| 8903 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit); | |||
| 8904 | attributes.set_is_evex_instruction(); | |||
| 8905 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 8906 | if (merge) { | |||
| 8907 | attributes.reset_is_clear_context(); | |||
| 8908 | } | |||
| 8909 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 8910 | emit_int16(0x1D, (0xC0 | encode)); | |||
| 8911 | } | |||
| 8912 | ||||
| 8913 | ||||
| 8914 | void Assembler::evpabsw(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) { | |||
| 8915 | InstructionMark im(this); | |||
| 8916 | assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "")do { if (!(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()))) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8916, "assert(" "VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl())" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 8917 | InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true); | |||
| 8918 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit); | |||
| 8919 | attributes.set_is_evex_instruction(); | |||
| 8920 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 8921 | if (merge) { | |||
| 8922 | attributes.reset_is_clear_context(); | |||
| 8923 | } | |||
| 8924 | vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 8925 | emit_int8(0x1D); | |||
| 8926 | emit_operand(dst, src); | |||
| 8927 | } | |||
| 8928 | ||||
| 8929 | void Assembler::evpabsd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) { | |||
| 8930 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8930, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 8931 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8931, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 8932 | InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true); | |||
| 8933 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit); | |||
| 8934 | attributes.set_is_evex_instruction(); | |||
| 8935 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 8936 | if (merge) { | |||
| 8937 | attributes.reset_is_clear_context(); | |||
| 8938 | } | |||
| 8939 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 8940 | emit_int16(0x1E, (0xC0 | encode)); | |||
| 8941 | } | |||
| 8942 | ||||
| 8943 | ||||
| 8944 | void Assembler::evpabsd(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) { | |||
| 8945 | InstructionMark im(this); | |||
| 8946 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8946, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 8947 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8947, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 8948 | InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true); | |||
| 8949 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit); | |||
| 8950 | attributes.set_is_evex_instruction(); | |||
| 8951 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 8952 | if (merge) { | |||
| 8953 | attributes.reset_is_clear_context(); | |||
| 8954 | } | |||
| 8955 | vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 8956 | emit_int8(0x1E); | |||
| 8957 | emit_operand(dst, src); | |||
| 8958 | } | |||
| 8959 | ||||
| 8960 | void Assembler::evpabsq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) { | |||
| 8961 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8961, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 8962 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8962, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 8963 | InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true); | |||
| 8964 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit); | |||
| 8965 | attributes.set_is_evex_instruction(); | |||
| 8966 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 8967 | if (merge) { | |||
| 8968 | attributes.reset_is_clear_context(); | |||
| 8969 | } | |||
| 8970 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 8971 | emit_int16(0x1F, (0xC0 | encode)); | |||
| 8972 | } | |||
| 8973 | ||||
| 8974 | ||||
| 8975 | void Assembler::evpabsq(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) { | |||
| 8976 | InstructionMark im(this); | |||
| 8977 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8977, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 8978 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8978, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 8979 | InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true); | |||
| 8980 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit); | |||
| 8981 | attributes.set_is_evex_instruction(); | |||
| 8982 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 8983 | if (merge) { | |||
| 8984 | attributes.reset_is_clear_context(); | |||
| 8985 | } | |||
| 8986 | vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 8987 | emit_int8(0x1F); | |||
| 8988 | emit_operand(dst, src); | |||
| 8989 | } | |||
| 8990 | ||||
| 8991 | void Assembler::evpfma213ps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 8992 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8992, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 8993 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 8993, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 8994 | InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true); | |||
| 8995 | attributes.set_is_evex_instruction(); | |||
| 8996 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 8997 | if (merge) { | |||
| 8998 | attributes.reset_is_clear_context(); | |||
| 8999 | } | |||
| 9000 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 9001 | emit_int16((unsigned char)0xA8, (0xC0 | encode)); | |||
| 9002 | } | |||
| 9003 | ||||
| 9004 | void Assembler::evpfma213ps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) { | |||
| 9005 | InstructionMark im(this); | |||
| 9006 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9006, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 9007 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9007, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 9008 | InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true); | |||
| 9009 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit); | |||
| 9010 | attributes.set_is_evex_instruction(); | |||
| 9011 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 9012 | if (merge) { | |||
| 9013 | attributes.reset_is_clear_context(); | |||
| 9014 | } | |||
| 9015 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 9016 | emit_int8((unsigned char)0xA8); | |||
| 9017 | emit_operand(dst, src); | |||
| 9018 | } | |||
| 9019 | ||||
| 9020 | void Assembler::evpfma213pd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 9021 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9021, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 9022 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9022, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 9023 | InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true); | |||
| 9024 | attributes.set_is_evex_instruction(); | |||
| 9025 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 9026 | if (merge) { | |||
| 9027 | attributes.reset_is_clear_context(); | |||
| 9028 | } | |||
| 9029 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 9030 | emit_int16((unsigned char)0xA8, (0xC0 | encode)); | |||
| 9031 | } | |||
| 9032 | ||||
| 9033 | void Assembler::evpfma213pd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) { | |||
| 9034 | InstructionMark im(this); | |||
| 9035 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9035, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 9036 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9036, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 9037 | InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true); | |||
| 9038 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit); | |||
| 9039 | attributes.set_is_evex_instruction(); | |||
| 9040 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 9041 | if (merge) { | |||
| 9042 | attributes.reset_is_clear_context(); | |||
| 9043 | } | |||
| 9044 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 9045 | emit_int8((unsigned char)0xA8); | |||
| 9046 | emit_operand(dst, src); | |||
| 9047 | } | |||
| 9048 | ||||
| 9049 | void Assembler::evpermb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 9050 | assert(VM_Version::supports_avx512_vbmi() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "")do { if (!(VM_Version::supports_avx512_vbmi() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()))) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9050, "assert(" "VM_Version::supports_avx512_vbmi() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl())" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 9051 | InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 9052 | attributes.set_is_evex_instruction(); | |||
| 9053 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 9054 | if (merge) { | |||
| 9055 | attributes.reset_is_clear_context(); | |||
| 9056 | } | |||
| 9057 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 9058 | emit_int16((unsigned char)0x8D, (0xC0 | encode)); | |||
| 9059 | } | |||
| 9060 | ||||
| 9061 | void Assembler::evpermb(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) { | |||
| 9062 | assert(VM_Version::supports_avx512_vbmi() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "")do { if (!(VM_Version::supports_avx512_vbmi() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()))) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9062, "assert(" "VM_Version::supports_avx512_vbmi() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl())" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 9063 | InstructionMark im(this); | |||
| 9064 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 9065 | attributes.set_is_evex_instruction(); | |||
| 9066 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 9067 | if (merge) { | |||
| 9068 | attributes.reset_is_clear_context(); | |||
| 9069 | } | |||
| 9070 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 9071 | emit_int8((unsigned char)0x8D); | |||
| 9072 | emit_operand(dst, src); | |||
| 9073 | } | |||
| 9074 | ||||
| 9075 | void Assembler::evpermw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 9076 | assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "")do { if (!(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()))) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9076, "assert(" "VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl())" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 9077 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 9078 | attributes.set_is_evex_instruction(); | |||
| 9079 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 9080 | if (merge) { | |||
| 9081 | attributes.reset_is_clear_context(); | |||
| 9082 | } | |||
| 9083 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 9084 | emit_int16((unsigned char)0x8D, (0xC0 | encode)); | |||
| 9085 | } | |||
| 9086 | ||||
| 9087 | void Assembler::evpermw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) { | |||
| 9088 | assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "")do { if (!(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()))) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9088, "assert(" "VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl())" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 9089 | InstructionMark im(this); | |||
| 9090 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 9091 | attributes.set_is_evex_instruction(); | |||
| 9092 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 9093 | if (merge) { | |||
| 9094 | attributes.reset_is_clear_context(); | |||
| 9095 | } | |||
| 9096 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 9097 | emit_int8((unsigned char)0x8D); | |||
| 9098 | emit_operand(dst, src); | |||
| 9099 | } | |||
| 9100 | ||||
| 9101 | void Assembler::evpermd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 9102 | assert(VM_Version::supports_evex() && vector_len > AVX_128bit, "")do { if (!(VM_Version::supports_evex() && vector_len > AVX_128bit)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9102, "assert(" "VM_Version::supports_evex() && vector_len > AVX_128bit" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 9103 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 9104 | attributes.set_is_evex_instruction(); | |||
| 9105 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 9106 | if (merge) { | |||
| 9107 | attributes.reset_is_clear_context(); | |||
| 9108 | } | |||
| 9109 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 9110 | emit_int16(0x36, (0xC0 | encode)); | |||
| 9111 | } | |||
| 9112 | ||||
| 9113 | void Assembler::evpermd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) { | |||
| 9114 | assert(VM_Version::supports_evex() && vector_len > AVX_128bit, "")do { if (!(VM_Version::supports_evex() && vector_len > AVX_128bit)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9114, "assert(" "VM_Version::supports_evex() && vector_len > AVX_128bit" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 9115 | InstructionMark im(this); | |||
| 9116 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 9117 | attributes.set_is_evex_instruction(); | |||
| 9118 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 9119 | if (merge) { | |||
| 9120 | attributes.reset_is_clear_context(); | |||
| 9121 | } | |||
| 9122 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 9123 | emit_int8(0x36); | |||
| 9124 | emit_operand(dst, src); | |||
| 9125 | } | |||
| 9126 | ||||
| 9127 | void Assembler::evpermq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 9128 | assert(VM_Version::supports_evex() && vector_len > AVX_128bit, "")do { if (!(VM_Version::supports_evex() && vector_len > AVX_128bit)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9128, "assert(" "VM_Version::supports_evex() && vector_len > AVX_128bit" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 9129 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 9130 | attributes.set_is_evex_instruction(); | |||
| 9131 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 9132 | if (merge) { | |||
| 9133 | attributes.reset_is_clear_context(); | |||
| 9134 | } | |||
| 9135 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 9136 | emit_int16(0x36, (0xC0 | encode)); | |||
| 9137 | } | |||
| 9138 | ||||
| 9139 | void Assembler::evpermq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) { | |||
| 9140 | assert(VM_Version::supports_evex() && vector_len > AVX_128bit, "")do { if (!(VM_Version::supports_evex() && vector_len > AVX_128bit)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9140, "assert(" "VM_Version::supports_evex() && vector_len > AVX_128bit" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 9141 | InstructionMark im(this); | |||
| 9142 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 9143 | attributes.set_is_evex_instruction(); | |||
| 9144 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 9145 | if (merge) { | |||
| 9146 | attributes.reset_is_clear_context(); | |||
| 9147 | } | |||
| 9148 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 9149 | emit_int8(0x36); | |||
| 9150 | emit_operand(dst, src); | |||
| 9151 | } | |||
| 9152 | ||||
| 9153 | void Assembler::evpsllw(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) { | |||
| 9154 | assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "")do { if (!(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()))) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9154, "assert(" "VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl())" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 9155 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 9156 | attributes.set_is_evex_instruction(); | |||
| 9157 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 9158 | if (merge) { | |||
| 9159 | attributes.reset_is_clear_context(); | |||
| 9160 | } | |||
| 9161 | int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 9162 | emit_int24(0x71, (0xC0 | encode), shift & 0xFF); | |||
| 9163 | } | |||
| 9164 | ||||
| 9165 | void Assembler::evpslld(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) { | |||
| 9166 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9166, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 9167 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9167, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 9168 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 9169 | attributes.set_is_evex_instruction(); | |||
| 9170 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 9171 | if (merge) { | |||
| 9172 | attributes.reset_is_clear_context(); | |||
| 9173 | } | |||
| 9174 | int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 9175 | emit_int24(0x72, (0xC0 | encode), shift & 0xFF); | |||
| 9176 | } | |||
| 9177 | ||||
| 9178 | void Assembler::evpsllq(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) { | |||
| 9179 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9179, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 9180 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9180, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 9181 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 9182 | attributes.set_is_evex_instruction(); | |||
| 9183 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 9184 | if (merge) { | |||
| 9185 | attributes.reset_is_clear_context(); | |||
| 9186 | } | |||
| 9187 | int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 9188 | emit_int24(0x73, (0xC0 | encode), shift & 0xFF); | |||
| 9189 | } | |||
| 9190 | ||||
| 9191 | void Assembler::evpsrlw(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) { | |||
| 9192 | assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "")do { if (!(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()))) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9192, "assert(" "VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl())" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 9193 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 9194 | attributes.set_is_evex_instruction(); | |||
| 9195 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 9196 | if (merge) { | |||
| 9197 | attributes.reset_is_clear_context(); | |||
| 9198 | } | |||
| 9199 | int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 9200 | emit_int24(0x71, (0xC0 | encode), shift & 0xFF); | |||
| 9201 | } | |||
| 9202 | ||||
| 9203 | void Assembler::evpsrld(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) { | |||
| 9204 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9204, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 9205 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9205, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 9206 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 9207 | attributes.set_is_evex_instruction(); | |||
| 9208 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 9209 | if (merge) { | |||
| 9210 | attributes.reset_is_clear_context(); | |||
| 9211 | } | |||
| 9212 | int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 9213 | emit_int24(0x72, (0xC0 | encode), shift & 0xFF); | |||
| 9214 | } | |||
| 9215 | ||||
| 9216 | void Assembler::evpsrlq(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) { | |||
| 9217 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9217, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 9218 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9218, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 9219 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 9220 | attributes.set_is_evex_instruction(); | |||
| 9221 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 9222 | if (merge) { | |||
| 9223 | attributes.reset_is_clear_context(); | |||
| 9224 | } | |||
| 9225 | int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 9226 | emit_int24(0x73, (0xC0 | encode), shift & 0xFF); | |||
| 9227 | } | |||
| 9228 | ||||
| 9229 | void Assembler::evpsraw(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) { | |||
| 9230 | assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "")do { if (!(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()))) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9230, "assert(" "VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl())" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 9231 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 9232 | attributes.set_is_evex_instruction(); | |||
| 9233 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 9234 | if (merge) { | |||
| 9235 | attributes.reset_is_clear_context(); | |||
| 9236 | } | |||
| 9237 | int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 9238 | emit_int24(0x71, (0xC0 | encode), shift & 0xFF); | |||
| 9239 | } | |||
| 9240 | ||||
| 9241 | void Assembler::evpsrad(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) { | |||
| 9242 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9242, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 9243 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9243, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 9244 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 9245 | attributes.set_is_evex_instruction(); | |||
| 9246 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 9247 | if (merge) { | |||
| 9248 | attributes.reset_is_clear_context(); | |||
| 9249 | } | |||
| 9250 | int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 9251 | emit_int24(0x72, (0xC0 | encode), shift & 0xFF); | |||
| 9252 | } | |||
| 9253 | ||||
| 9254 | void Assembler::evpsraq(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) { | |||
| 9255 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9255, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 9256 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9256, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 9257 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 9258 | attributes.set_is_evex_instruction(); | |||
| 9259 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 9260 | if (merge) { | |||
| 9261 | attributes.reset_is_clear_context(); | |||
| 9262 | } | |||
| 9263 | int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 9264 | emit_int24(0x73, (0xC0 | encode), shift & 0xFF); | |||
| 9265 | } | |||
| 9266 | ||||
| 9267 | void Assembler::evpsllw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 9268 | assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "")do { if (!(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()))) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9268, "assert(" "VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl())" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 9269 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 9270 | attributes.set_is_evex_instruction(); | |||
| 9271 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 9272 | if (merge) { | |||
| 9273 | attributes.reset_is_clear_context(); | |||
| 9274 | } | |||
| 9275 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 9276 | emit_int16((unsigned char)0xF1, (0xC0 | encode)); | |||
| 9277 | } | |||
| 9278 | ||||
| 9279 | void Assembler::evpslld(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 9280 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9280, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 9281 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9281, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 9282 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 9283 | attributes.set_is_evex_instruction(); | |||
| 9284 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 9285 | if (merge) { | |||
| 9286 | attributes.reset_is_clear_context(); | |||
| 9287 | } | |||
| 9288 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 9289 | emit_int16((unsigned char)0xF2, (0xC0 | encode)); | |||
| 9290 | } | |||
| 9291 | ||||
| 9292 | void Assembler::evpsllq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 9293 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9293, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 9294 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9294, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 9295 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 9296 | attributes.set_is_evex_instruction(); | |||
| 9297 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 9298 | if (merge) { | |||
| 9299 | attributes.reset_is_clear_context(); | |||
| 9300 | } | |||
| 9301 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 9302 | emit_int16((unsigned char)0xF3, (0xC0 | encode)); | |||
| 9303 | } | |||
| 9304 | ||||
| 9305 | void Assembler::evpsrlw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 9306 | assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "")do { if (!(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()))) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9306, "assert(" "VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl())" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 9307 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 9308 | attributes.set_is_evex_instruction(); | |||
| 9309 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 9310 | if (merge) { | |||
| 9311 | attributes.reset_is_clear_context(); | |||
| 9312 | } | |||
| 9313 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 9314 | emit_int16((unsigned char)0xD1, (0xC0 | encode)); | |||
| 9315 | } | |||
| 9316 | ||||
| 9317 | void Assembler::evpsrld(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 9318 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9318, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 9319 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9319, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 9320 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 9321 | attributes.set_is_evex_instruction(); | |||
| 9322 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 9323 | if (merge) { | |||
| 9324 | attributes.reset_is_clear_context(); | |||
| 9325 | } | |||
| 9326 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 9327 | emit_int16((unsigned char)0xD2, (0xC0 | encode)); | |||
| 9328 | } | |||
| 9329 | ||||
| 9330 | void Assembler::evpsrlq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 9331 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9331, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 9332 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9332, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 9333 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 9334 | attributes.set_is_evex_instruction(); | |||
| 9335 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 9336 | if (merge) { | |||
| 9337 | attributes.reset_is_clear_context(); | |||
| 9338 | } | |||
| 9339 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 9340 | emit_int16((unsigned char)0xD3, (0xC0 | encode)); | |||
| 9341 | } | |||
| 9342 | ||||
| 9343 | void Assembler::evpsraw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 9344 | assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "")do { if (!(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()))) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9344, "assert(" "VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl())" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 9345 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 9346 | attributes.set_is_evex_instruction(); | |||
| 9347 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 9348 | if (merge) { | |||
| 9349 | attributes.reset_is_clear_context(); | |||
| 9350 | } | |||
| 9351 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 9352 | emit_int16((unsigned char)0xE1, (0xC0 | encode)); | |||
| 9353 | } | |||
| 9354 | ||||
| 9355 | void Assembler::evpsrad(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 9356 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9356, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 9357 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9357, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 9358 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 9359 | attributes.set_is_evex_instruction(); | |||
| 9360 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 9361 | if (merge) { | |||
| 9362 | attributes.reset_is_clear_context(); | |||
| 9363 | } | |||
| 9364 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 9365 | emit_int16((unsigned char)0xE2, (0xC0 | encode)); | |||
| 9366 | } | |||
| 9367 | ||||
| 9368 | void Assembler::evpsraq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 9369 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9369, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 9370 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9370, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 9371 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 9372 | attributes.set_is_evex_instruction(); | |||
| 9373 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 9374 | if (merge) { | |||
| 9375 | attributes.reset_is_clear_context(); | |||
| 9376 | } | |||
| 9377 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 9378 | emit_int16((unsigned char)0xE2, (0xC0 | encode)); | |||
| 9379 | } | |||
| 9380 | ||||
| 9381 | void Assembler::evpsllvw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 9382 | assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "")do { if (!(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()))) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9382, "assert(" "VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl())" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 9383 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 9384 | attributes.set_is_evex_instruction(); | |||
| 9385 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 9386 | if (merge) { | |||
| 9387 | attributes.reset_is_clear_context(); | |||
| 9388 | } | |||
| 9389 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 9390 | emit_int16(0x12, (0xC0 | encode)); | |||
| 9391 | } | |||
| 9392 | ||||
| 9393 | void Assembler::evpsllvd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 9394 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9394, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 9395 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9395, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 9396 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 9397 | attributes.set_is_evex_instruction(); | |||
| 9398 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 9399 | if (merge) { | |||
| 9400 | attributes.reset_is_clear_context(); | |||
| 9401 | } | |||
| 9402 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 9403 | emit_int16(0x47, (0xC0 | encode)); | |||
| 9404 | } | |||
| 9405 | ||||
| 9406 | void Assembler::evpsllvq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 9407 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9407, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 9408 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9408, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 9409 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 9410 | attributes.set_is_evex_instruction(); | |||
| 9411 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 9412 | if (merge) { | |||
| 9413 | attributes.reset_is_clear_context(); | |||
| 9414 | } | |||
| 9415 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 9416 | emit_int16(0x47, (0xC0 | encode)); | |||
| 9417 | } | |||
| 9418 | ||||
| 9419 | void Assembler::evpsrlvw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 9420 | assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "")do { if (!(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()))) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9420, "assert(" "VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl())" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 9421 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 9422 | attributes.set_is_evex_instruction(); | |||
| 9423 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 9424 | if (merge) { | |||
| 9425 | attributes.reset_is_clear_context(); | |||
| 9426 | } | |||
| 9427 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 9428 | emit_int16(0x10, (0xC0 | encode)); | |||
| 9429 | } | |||
| 9430 | ||||
| 9431 | void Assembler::evpsrlvd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 9432 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9432, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 9433 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9433, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 9434 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 9435 | attributes.set_is_evex_instruction(); | |||
| 9436 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 9437 | if (merge) { | |||
| 9438 | attributes.reset_is_clear_context(); | |||
| 9439 | } | |||
| 9440 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 9441 | emit_int16(0x45, (0xC0 | encode)); | |||
| 9442 | } | |||
| 9443 | ||||
| 9444 | void Assembler::evpsrlvq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 9445 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9445, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 9446 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9446, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 9447 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 9448 | attributes.set_is_evex_instruction(); | |||
| 9449 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 9450 | if (merge) { | |||
| 9451 | attributes.reset_is_clear_context(); | |||
| 9452 | } | |||
| 9453 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 9454 | emit_int16(0x45, (0xC0 | encode)); | |||
| 9455 | } | |||
| 9456 | ||||
| 9457 | void Assembler::evpsravw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 9458 | assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "")do { if (!(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()))) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9458, "assert(" "VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl())" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 9459 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 9460 | attributes.set_is_evex_instruction(); | |||
| 9461 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 9462 | if (merge) { | |||
| 9463 | attributes.reset_is_clear_context(); | |||
| 9464 | } | |||
| 9465 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 9466 | emit_int16(0x11, (0xC0 | encode)); | |||
| 9467 | } | |||
| 9468 | ||||
| 9469 | void Assembler::evpsravd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 9470 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9470, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 9471 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9471, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 9472 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 9473 | attributes.set_is_evex_instruction(); | |||
| 9474 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 9475 | if (merge) { | |||
| 9476 | attributes.reset_is_clear_context(); | |||
| 9477 | } | |||
| 9478 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 9479 | emit_int16(0x46, (0xC0 | encode)); | |||
| 9480 | } | |||
| 9481 | ||||
| 9482 | void Assembler::evpsravq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 9483 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9483, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 9484 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9484, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 9485 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 9486 | attributes.set_is_evex_instruction(); | |||
| 9487 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 9488 | if (merge) { | |||
| 9489 | attributes.reset_is_clear_context(); | |||
| 9490 | } | |||
| 9491 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 9492 | emit_int16(0x46, (0xC0 | encode)); | |||
| 9493 | } | |||
| 9494 | ||||
| 9495 | void Assembler::evpminsb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 9496 | assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "")do { if (!(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()))) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9496, "assert(" "VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl())" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 9497 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 9498 | attributes.set_is_evex_instruction(); | |||
| 9499 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 9500 | if (merge) { | |||
| 9501 | attributes.reset_is_clear_context(); | |||
| 9502 | } | |||
| 9503 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 9504 | emit_int16(0x38, (0xC0 | encode)); | |||
| 9505 | } | |||
| 9506 | ||||
| 9507 | void Assembler::evpminsb(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) { | |||
| 9508 | assert(VM_Version::supports_avx512bw(), "")do { if (!(VM_Version::supports_avx512bw())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9508, "assert(" "VM_Version::supports_avx512bw()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 9509 | InstructionMark im(this); | |||
| 9510 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 9511 | attributes.set_is_evex_instruction(); | |||
| 9512 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 9513 | if (merge) { | |||
| 9514 | attributes.reset_is_clear_context(); | |||
| 9515 | } | |||
| 9516 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 9517 | emit_int8(0x38); | |||
| 9518 | emit_operand(dst, src); | |||
| 9519 | } | |||
| 9520 | ||||
| 9521 | void Assembler::evpminsw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 9522 | assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "")do { if (!(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()))) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9522, "assert(" "VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl())" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 9523 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 9524 | attributes.set_is_evex_instruction(); | |||
| 9525 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 9526 | if (merge) { | |||
| 9527 | attributes.reset_is_clear_context(); | |||
| 9528 | } | |||
| 9529 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 9530 | emit_int16((unsigned char)0xEA, (0xC0 | encode)); | |||
| 9531 | } | |||
| 9532 | ||||
| 9533 | void Assembler::evpminsw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) { | |||
| 9534 | assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "")do { if (!(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()))) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9534, "assert(" "VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl())" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 9535 | InstructionMark im(this); | |||
| 9536 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 9537 | attributes.set_is_evex_instruction(); | |||
| 9538 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 9539 | if (merge) { | |||
| 9540 | attributes.reset_is_clear_context(); | |||
| 9541 | } | |||
| 9542 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 9543 | emit_int8((unsigned char)0xEA); | |||
| 9544 | emit_operand(dst, src); | |||
| 9545 | } | |||
| 9546 | ||||
| 9547 | void Assembler::evpminsd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 9548 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9548, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 9549 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9549, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 9550 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 9551 | attributes.set_is_evex_instruction(); | |||
| 9552 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 9553 | if (merge) { | |||
| 9554 | attributes.reset_is_clear_context(); | |||
| 9555 | } | |||
| 9556 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 9557 | emit_int16(0x39, (0xC0 | encode)); | |||
| 9558 | } | |||
| 9559 | ||||
| 9560 | void Assembler::evpminsd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) { | |||
| 9561 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9561, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 9562 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9562, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 9563 | InstructionMark im(this); | |||
| 9564 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 9565 | attributes.set_is_evex_instruction(); | |||
| 9566 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 9567 | if (merge) { | |||
| 9568 | attributes.reset_is_clear_context(); | |||
| 9569 | } | |||
| 9570 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 9571 | emit_int8(0x39); | |||
| 9572 | emit_operand(dst, src); | |||
| 9573 | } | |||
| 9574 | ||||
| 9575 | void Assembler::evpminsq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 9576 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9576, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 9577 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9577, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 9578 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 9579 | attributes.set_is_evex_instruction(); | |||
| 9580 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 9581 | if (merge) { | |||
| 9582 | attributes.reset_is_clear_context(); | |||
| 9583 | } | |||
| 9584 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 9585 | emit_int16(0x39, (0xC0 | encode)); | |||
| 9586 | } | |||
| 9587 | ||||
| 9588 | void Assembler::evpminsq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) { | |||
| 9589 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9589, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 9590 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9590, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 9591 | InstructionMark im(this); | |||
| 9592 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 9593 | attributes.set_is_evex_instruction(); | |||
| 9594 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 9595 | if (merge) { | |||
| 9596 | attributes.reset_is_clear_context(); | |||
| 9597 | } | |||
| 9598 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 9599 | emit_int8(0x39); | |||
| 9600 | emit_operand(dst, src); | |||
| 9601 | } | |||
| 9602 | ||||
| 9603 | ||||
| 9604 | void Assembler::evpmaxsb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 9605 | assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "")do { if (!(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()))) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9605, "assert(" "VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl())" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 9606 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 9607 | attributes.set_is_evex_instruction(); | |||
| 9608 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 9609 | if (merge) { | |||
| 9610 | attributes.reset_is_clear_context(); | |||
| 9611 | } | |||
| 9612 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 9613 | emit_int16(0x3C, (0xC0 | encode)); | |||
| 9614 | } | |||
| 9615 | ||||
| 9616 | void Assembler::evpmaxsb(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) { | |||
| 9617 | assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "")do { if (!(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()))) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9617, "assert(" "VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl())" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 9618 | InstructionMark im(this); | |||
| 9619 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 9620 | attributes.set_is_evex_instruction(); | |||
| 9621 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 9622 | if (merge) { | |||
| 9623 | attributes.reset_is_clear_context(); | |||
| 9624 | } | |||
| 9625 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 9626 | emit_int8(0x3C); | |||
| 9627 | emit_operand(dst, src); | |||
| 9628 | } | |||
| 9629 | ||||
| 9630 | void Assembler::evpmaxsw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 9631 | assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "")do { if (!(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()))) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9631, "assert(" "VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl())" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 9632 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 9633 | attributes.set_is_evex_instruction(); | |||
| 9634 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 9635 | if (merge) { | |||
| 9636 | attributes.reset_is_clear_context(); | |||
| 9637 | } | |||
| 9638 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 9639 | emit_int16((unsigned char)0xEE, (0xC0 | encode)); | |||
| 9640 | } | |||
| 9641 | ||||
| 9642 | void Assembler::evpmaxsw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) { | |||
| 9643 | assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "")do { if (!(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()))) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9643, "assert(" "VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl())" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 9644 | InstructionMark im(this); | |||
| 9645 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 9646 | attributes.set_is_evex_instruction(); | |||
| 9647 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 9648 | if (merge) { | |||
| 9649 | attributes.reset_is_clear_context(); | |||
| 9650 | } | |||
| 9651 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 9652 | emit_int8((unsigned char)0xEE); | |||
| 9653 | emit_operand(dst, src); | |||
| 9654 | } | |||
| 9655 | ||||
| 9656 | void Assembler::evpmaxsd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 9657 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9657, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 9658 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9658, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 9659 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 9660 | attributes.set_is_evex_instruction(); | |||
| 9661 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 9662 | if (merge) { | |||
| 9663 | attributes.reset_is_clear_context(); | |||
| 9664 | } | |||
| 9665 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 9666 | emit_int16(0x3D, (0xC0 | encode)); | |||
| 9667 | } | |||
| 9668 | ||||
| 9669 | void Assembler::evpmaxsd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) { | |||
| 9670 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9670, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 9671 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9671, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 9672 | InstructionMark im(this); | |||
| 9673 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 9674 | attributes.set_is_evex_instruction(); | |||
| 9675 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 9676 | if (merge) { | |||
| 9677 | attributes.reset_is_clear_context(); | |||
| 9678 | } | |||
| 9679 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 9680 | emit_int8(0x3D); | |||
| 9681 | emit_operand(dst, src); | |||
| 9682 | } | |||
| 9683 | ||||
| 9684 | void Assembler::evpmaxsq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 9685 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9685, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 9686 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9686, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 9687 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 9688 | attributes.set_is_evex_instruction(); | |||
| 9689 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 9690 | if (merge) { | |||
| 9691 | attributes.reset_is_clear_context(); | |||
| 9692 | } | |||
| 9693 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 9694 | emit_int16(0x3D, (0xC0 | encode)); | |||
| 9695 | } | |||
| 9696 | ||||
| 9697 | void Assembler::evpmaxsq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) { | |||
| 9698 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9698, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 9699 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9699, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 9700 | InstructionMark im(this); | |||
| 9701 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 9702 | attributes.set_is_evex_instruction(); | |||
| 9703 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 9704 | if (merge) { | |||
| 9705 | attributes.reset_is_clear_context(); | |||
| 9706 | } | |||
| 9707 | vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 9708 | emit_int8(0x3D); | |||
| 9709 | emit_operand(dst, src); | |||
| 9710 | } | |||
| 9711 | ||||
| 9712 | // duplicate 4-byte integer data from src into programmed locations in dest : requires AVX512VL | |||
| 9713 | void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len) { | |||
| 9714 | assert(UseAVX >= 2, "")do { if (!(UseAVX >= 2)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9714, "assert(" "UseAVX >= 2" ") failed", ""); ::breakpoint (); } } while (0); | |||
| 9715 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 9716 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 9717 | emit_int16(0x58, (0xC0 | encode)); | |||
| 9718 | } | |||
| 9719 | ||||
| 9720 | void Assembler::vpbroadcastd(XMMRegister dst, Address src, int vector_len) { | |||
| 9721 | assert(VM_Version::supports_avx2(), "")do { if (!(VM_Version::supports_avx2())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9721, "assert(" "VM_Version::supports_avx2()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 9722 | assert(dst != xnoreg, "sanity")do { if (!(dst != xnoreg)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9722, "assert(" "dst != xnoreg" ") failed", "sanity"); ::breakpoint (); } } while (0); | |||
| 9723 | InstructionMark im(this); | |||
| 9724 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 9725 | attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); | |||
| 9726 | // swap src<->dst for encoding | |||
| 9727 | vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 9728 | emit_int8(0x58); | |||
| 9729 | emit_operand(dst, src); | |||
| 9730 | } | |||
| 9731 | ||||
| 9732 | // duplicate 8-byte integer data from src into programmed locations in dest : requires AVX512VL | |||
| 9733 | void Assembler::vpbroadcastq(XMMRegister dst, XMMRegister src, int vector_len) { | |||
| 9734 | assert(VM_Version::supports_avx2(), "")do { if (!(VM_Version::supports_avx2())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9734, "assert(" "VM_Version::supports_avx2()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 9735 | InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 9736 | attributes.set_rex_vex_w_reverted(); | |||
| 9737 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 9738 | emit_int16(0x59, (0xC0 | encode)); | |||
| 9739 | } | |||
| 9740 | ||||
| 9741 | void Assembler::vpbroadcastq(XMMRegister dst, Address src, int vector_len) { | |||
| 9742 | assert(VM_Version::supports_avx2(), "")do { if (!(VM_Version::supports_avx2())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9742, "assert(" "VM_Version::supports_avx2()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 9743 | assert(dst != xnoreg, "sanity")do { if (!(dst != xnoreg)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9743, "assert(" "dst != xnoreg" ") failed", "sanity"); ::breakpoint (); } } while (0); | |||
| 9744 | InstructionMark im(this); | |||
| 9745 | InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 9746 | attributes.set_rex_vex_w_reverted(); | |||
| 9747 | attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); | |||
| 9748 | // swap src<->dst for encoding | |||
| 9749 | vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 9750 | emit_int8(0x59); | |||
| 9751 | emit_operand(dst, src); | |||
| 9752 | } | |||
| 9753 | ||||
| 9754 | void Assembler::evbroadcasti32x4(XMMRegister dst, Address src, int vector_len) { | |||
| 9755 | assert(vector_len != Assembler::AVX_128bit, "")do { if (!(vector_len != Assembler::AVX_128bit)) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9755, "assert(" "vector_len != Assembler::AVX_128bit" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 9756 | assert(VM_Version::supports_avx512dq(), "")do { if (!(VM_Version::supports_avx512dq())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9756, "assert(" "VM_Version::supports_avx512dq()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 9757 | assert(dst != xnoreg, "sanity")do { if (!(dst != xnoreg)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9757, "assert(" "dst != xnoreg" ") failed", "sanity"); ::breakpoint (); } } while (0); | |||
| 9758 | InstructionMark im(this); | |||
| 9759 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 9760 | attributes.set_rex_vex_w_reverted(); | |||
| 9761 | attributes.set_address_attributes(/* tuple_type */ EVEX_T2, /* input_size_in_bits */ EVEX_64bit); | |||
| 9762 | // swap src<->dst for encoding | |||
| 9763 | vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 9764 | emit_int8(0x5A); | |||
| 9765 | emit_operand(dst, src); | |||
| 9766 | } | |||
| 9767 | ||||
| 9768 | void Assembler::evbroadcasti64x2(XMMRegister dst, XMMRegister src, int vector_len) { | |||
| 9769 | assert(vector_len != Assembler::AVX_128bit, "")do { if (!(vector_len != Assembler::AVX_128bit)) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9769, "assert(" "vector_len != Assembler::AVX_128bit" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 9770 | assert(VM_Version::supports_avx512dq(), "")do { if (!(VM_Version::supports_avx512dq())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9770, "assert(" "VM_Version::supports_avx512dq()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 9771 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 9772 | attributes.set_rex_vex_w_reverted(); | |||
| 9773 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 9774 | emit_int16(0x5A, (0xC0 | encode)); | |||
| 9775 | } | |||
| 9776 | ||||
| 9777 | void Assembler::evbroadcasti64x2(XMMRegister dst, Address src, int vector_len) { | |||
| 9778 | assert(vector_len != Assembler::AVX_128bit, "")do { if (!(vector_len != Assembler::AVX_128bit)) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9778, "assert(" "vector_len != Assembler::AVX_128bit" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 9779 | assert(VM_Version::supports_avx512dq(), "")do { if (!(VM_Version::supports_avx512dq())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9779, "assert(" "VM_Version::supports_avx512dq()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 9780 | assert(dst != xnoreg, "sanity")do { if (!(dst != xnoreg)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9780, "assert(" "dst != xnoreg" ") failed", "sanity"); ::breakpoint (); } } while (0); | |||
| 9781 | InstructionMark im(this); | |||
| 9782 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 9783 | attributes.set_rex_vex_w_reverted(); | |||
| 9784 | attributes.set_address_attributes(/* tuple_type */ EVEX_T2, /* input_size_in_bits */ EVEX_64bit); | |||
| 9785 | // swap src<->dst for encoding | |||
| 9786 | vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 9787 | emit_int8(0x5A); | |||
| 9788 | emit_operand(dst, src); | |||
| 9789 | } | |||
| 9790 | ||||
| 9791 | // scalar single/double precision replicate | |||
| 9792 | ||||
| 9793 | // duplicate single precision data from src into programmed locations in dest : requires AVX512VL | |||
| 9794 | void Assembler::vbroadcastss(XMMRegister dst, XMMRegister src, int vector_len) { | |||
| 9795 | assert(VM_Version::supports_avx2(), "")do { if (!(VM_Version::supports_avx2())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9795, "assert(" "VM_Version::supports_avx2()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 9796 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 9797 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 9798 | emit_int16(0x18, (0xC0 | encode)); | |||
| 9799 | } | |||
| 9800 | ||||
| 9801 | void Assembler::vbroadcastss(XMMRegister dst, Address src, int vector_len) { | |||
| 9802 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9802, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 9803 | assert(dst != xnoreg, "sanity")do { if (!(dst != xnoreg)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9803, "assert(" "dst != xnoreg" ") failed", "sanity"); ::breakpoint (); } } while (0); | |||
| 9804 | InstructionMark im(this); | |||
| 9805 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 9806 | attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); | |||
| 9807 | // swap src<->dst for encoding | |||
| 9808 | vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 9809 | emit_int8(0x18); | |||
| 9810 | emit_operand(dst, src); | |||
| 9811 | } | |||
| 9812 | ||||
| 9813 | // duplicate double precision data from src into programmed locations in dest : requires AVX512VL | |||
| 9814 | void Assembler::vbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len) { | |||
| 9815 | assert(VM_Version::supports_avx2(), "")do { if (!(VM_Version::supports_avx2())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9815, "assert(" "VM_Version::supports_avx2()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 9816 | assert(vector_len == AVX_256bit || vector_len == AVX_512bit, "")do { if (!(vector_len == AVX_256bit || vector_len == AVX_512bit )) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9816, "assert(" "vector_len == AVX_256bit || vector_len == AVX_512bit" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 9817 | InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 9818 | attributes.set_rex_vex_w_reverted(); | |||
| 9819 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 9820 | emit_int16(0x19, (0xC0 | encode)); | |||
| 9821 | } | |||
| 9822 | ||||
| 9823 | void Assembler::vbroadcastsd(XMMRegister dst, Address src, int vector_len) { | |||
| 9824 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9824, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 9825 | assert(vector_len == AVX_256bit || vector_len == AVX_512bit, "")do { if (!(vector_len == AVX_256bit || vector_len == AVX_512bit )) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9825, "assert(" "vector_len == AVX_256bit || vector_len == AVX_512bit" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 9826 | assert(dst != xnoreg, "sanity")do { if (!(dst != xnoreg)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9826, "assert(" "dst != xnoreg" ") failed", "sanity"); ::breakpoint (); } } while (0); | |||
| 9827 | InstructionMark im(this); | |||
| 9828 | InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 9829 | attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); | |||
| 9830 | attributes.set_rex_vex_w_reverted(); | |||
| 9831 | // swap src<->dst for encoding | |||
| 9832 | vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 9833 | emit_int8(0x19); | |||
| 9834 | emit_operand(dst, src); | |||
| 9835 | } | |||
| 9836 | ||||
| 9837 | void Assembler::vbroadcastf128(XMMRegister dst, Address src, int vector_len) { | |||
| 9838 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9838, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 9839 | assert(vector_len == AVX_256bit, "")do { if (!(vector_len == AVX_256bit)) { (*g_assert_poison) = 'X' ;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9839, "assert(" "vector_len == AVX_256bit" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 9840 | assert(dst != xnoreg, "sanity")do { if (!(dst != xnoreg)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9840, "assert(" "dst != xnoreg" ") failed", "sanity"); ::breakpoint (); } } while (0); | |||
| 9841 | InstructionMark im(this); | |||
| 9842 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 9843 | attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit); | |||
| 9844 | // swap src<->dst for encoding | |||
| 9845 | vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 9846 | emit_int8(0x1A); | |||
| 9847 | emit_operand(dst, src); | |||
| 9848 | } | |||
| 9849 | ||||
| 9850 | // gpr source broadcast forms | |||
| 9851 | ||||
| 9852 | // duplicate 1-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL | |||
| 9853 | void Assembler::evpbroadcastb(XMMRegister dst, Register src, int vector_len) { | |||
| 9854 | assert(VM_Version::supports_avx512bw(), "")do { if (!(VM_Version::supports_avx512bw())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9854, "assert(" "VM_Version::supports_avx512bw()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 9855 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 9856 | attributes.set_is_evex_instruction(); | |||
| 9857 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 9858 | emit_int16(0x7A, (0xC0 | encode)); | |||
| 9859 | } | |||
| 9860 | ||||
| 9861 | // duplicate 2-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL | |||
| 9862 | void Assembler::evpbroadcastw(XMMRegister dst, Register src, int vector_len) { | |||
| 9863 | assert(VM_Version::supports_avx512bw(), "")do { if (!(VM_Version::supports_avx512bw())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9863, "assert(" "VM_Version::supports_avx512bw()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 9864 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 9865 | attributes.set_is_evex_instruction(); | |||
| 9866 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 9867 | emit_int16(0x7B, (0xC0 | encode)); | |||
| 9868 | } | |||
| 9869 | ||||
| 9870 | // duplicate 4-byte integer data from src into programmed locations in dest : requires AVX512VL | |||
| 9871 | void Assembler::evpbroadcastd(XMMRegister dst, Register src, int vector_len) { | |||
| 9872 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9872, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 9873 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 9874 | attributes.set_is_evex_instruction(); | |||
| 9875 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 9876 | emit_int16(0x7C, (0xC0 | encode)); | |||
| 9877 | } | |||
| 9878 | ||||
| 9879 | // duplicate 8-byte integer data from src into programmed locations in dest : requires AVX512VL | |||
| 9880 | void Assembler::evpbroadcastq(XMMRegister dst, Register src, int vector_len) { | |||
| 9881 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9881, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 9882 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 9883 | attributes.set_is_evex_instruction(); | |||
| 9884 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 9885 | emit_int16(0x7C, (0xC0 | encode)); | |||
| 9886 | } | |||
| 9887 | ||||
| 9888 | void Assembler::vpgatherdd(XMMRegister dst, Address src, XMMRegister mask, int vector_len) { | |||
| 9889 | assert(VM_Version::supports_avx2(), "")do { if (!(VM_Version::supports_avx2())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9889, "assert(" "VM_Version::supports_avx2()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 9890 | assert(vector_len == Assembler::AVX_128bit || vector_len == Assembler::AVX_256bit, "")do { if (!(vector_len == Assembler::AVX_128bit || vector_len == Assembler::AVX_256bit)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9890, "assert(" "vector_len == Assembler::AVX_128bit || vector_len == Assembler::AVX_256bit" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 9891 | assert(dst != xnoreg, "sanity")do { if (!(dst != xnoreg)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9891, "assert(" "dst != xnoreg" ") failed", "sanity"); ::breakpoint (); } } while (0); | |||
| 9892 | assert(src.isxmmindex(),"expected to be xmm index")do { if (!(src.isxmmindex())) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9892, "assert(" "src.isxmmindex()" ") failed", "expected to be xmm index" ); ::breakpoint(); } } while (0); | |||
| 9893 | assert(dst != src.xmmindex(), "instruction will #UD if dst and index are the same")do { if (!(dst != src.xmmindex())) { (*g_assert_poison) = 'X' ;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9893, "assert(" "dst != src.xmmindex()" ") failed", "instruction will #UD if dst and index are the same" ); ::breakpoint(); } } while (0); | |||
| 9894 | InstructionMark im(this); | |||
| 9895 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 9896 | vex_prefix(src, mask->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 9897 | emit_int8((unsigned char)0x90); | |||
| 9898 | emit_operand(dst, src); | |||
| 9899 | } | |||
| 9900 | ||||
| 9901 | void Assembler::vpgatherdq(XMMRegister dst, Address src, XMMRegister mask, int vector_len) { | |||
| 9902 | assert(VM_Version::supports_avx2(), "")do { if (!(VM_Version::supports_avx2())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9902, "assert(" "VM_Version::supports_avx2()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 9903 | assert(vector_len == Assembler::AVX_128bit || vector_len == Assembler::AVX_256bit, "")do { if (!(vector_len == Assembler::AVX_128bit || vector_len == Assembler::AVX_256bit)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9903, "assert(" "vector_len == Assembler::AVX_128bit || vector_len == Assembler::AVX_256bit" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 9904 | assert(dst != xnoreg, "sanity")do { if (!(dst != xnoreg)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9904, "assert(" "dst != xnoreg" ") failed", "sanity"); ::breakpoint (); } } while (0); | |||
| 9905 | assert(src.isxmmindex(),"expected to be xmm index")do { if (!(src.isxmmindex())) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9905, "assert(" "src.isxmmindex()" ") failed", "expected to be xmm index" ); ::breakpoint(); } } while (0); | |||
| 9906 | assert(dst != src.xmmindex(), "instruction will #UD if dst and index are the same")do { if (!(dst != src.xmmindex())) { (*g_assert_poison) = 'X' ;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9906, "assert(" "dst != src.xmmindex()" ") failed", "instruction will #UD if dst and index are the same" ); ::breakpoint(); } } while (0); | |||
| 9907 | InstructionMark im(this); | |||
| 9908 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 9909 | vex_prefix(src, mask->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 9910 | emit_int8((unsigned char)0x90); | |||
| 9911 | emit_operand(dst, src); | |||
| 9912 | } | |||
| 9913 | ||||
| 9914 | void Assembler::vgatherdpd(XMMRegister dst, Address src, XMMRegister mask, int vector_len) { | |||
| 9915 | assert(VM_Version::supports_avx2(), "")do { if (!(VM_Version::supports_avx2())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9915, "assert(" "VM_Version::supports_avx2()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 9916 | assert(vector_len == Assembler::AVX_128bit || vector_len == Assembler::AVX_256bit, "")do { if (!(vector_len == Assembler::AVX_128bit || vector_len == Assembler::AVX_256bit)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9916, "assert(" "vector_len == Assembler::AVX_128bit || vector_len == Assembler::AVX_256bit" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 9917 | assert(dst != xnoreg, "sanity")do { if (!(dst != xnoreg)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9917, "assert(" "dst != xnoreg" ") failed", "sanity"); ::breakpoint (); } } while (0); | |||
| 9918 | assert(src.isxmmindex(),"expected to be xmm index")do { if (!(src.isxmmindex())) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9918, "assert(" "src.isxmmindex()" ") failed", "expected to be xmm index" ); ::breakpoint(); } } while (0); | |||
| 9919 | assert(dst != src.xmmindex(), "instruction will #UD if dst and index are the same")do { if (!(dst != src.xmmindex())) { (*g_assert_poison) = 'X' ;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9919, "assert(" "dst != src.xmmindex()" ") failed", "instruction will #UD if dst and index are the same" ); ::breakpoint(); } } while (0); | |||
| 9920 | InstructionMark im(this); | |||
| 9921 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 9922 | vex_prefix(src, mask->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 9923 | emit_int8((unsigned char)0x92); | |||
| 9924 | emit_operand(dst, src); | |||
| 9925 | } | |||
| 9926 | ||||
| 9927 | void Assembler::vgatherdps(XMMRegister dst, Address src, XMMRegister mask, int vector_len) { | |||
| 9928 | assert(VM_Version::supports_avx2(), "")do { if (!(VM_Version::supports_avx2())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9928, "assert(" "VM_Version::supports_avx2()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 9929 | assert(vector_len == Assembler::AVX_128bit || vector_len == Assembler::AVX_256bit, "")do { if (!(vector_len == Assembler::AVX_128bit || vector_len == Assembler::AVX_256bit)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9929, "assert(" "vector_len == Assembler::AVX_128bit || vector_len == Assembler::AVX_256bit" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 9930 | assert(dst != xnoreg, "sanity")do { if (!(dst != xnoreg)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9930, "assert(" "dst != xnoreg" ") failed", "sanity"); ::breakpoint (); } } while (0); | |||
| 9931 | assert(src.isxmmindex(),"expected to be xmm index")do { if (!(src.isxmmindex())) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9931, "assert(" "src.isxmmindex()" ") failed", "expected to be xmm index" ); ::breakpoint(); } } while (0); | |||
| 9932 | assert(dst != src.xmmindex(), "instruction will #UD if dst and index are the same")do { if (!(dst != src.xmmindex())) { (*g_assert_poison) = 'X' ;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9932, "assert(" "dst != src.xmmindex()" ") failed", "instruction will #UD if dst and index are the same" ); ::breakpoint(); } } while (0); | |||
| 9933 | InstructionMark im(this); | |||
| 9934 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 9935 | vex_prefix(src, mask->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 9936 | emit_int8((unsigned char)0x92); | |||
| 9937 | emit_operand(dst, src); | |||
| 9938 | } | |||
| 9939 | void Assembler::evpgatherdd(XMMRegister dst, KRegister mask, Address src, int vector_len) { | |||
| 9940 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9940, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 9941 | assert(dst != xnoreg, "sanity")do { if (!(dst != xnoreg)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9941, "assert(" "dst != xnoreg" ") failed", "sanity"); ::breakpoint (); } } while (0); | |||
| 9942 | assert(src.isxmmindex(),"expected to be xmm index")do { if (!(src.isxmmindex())) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9942, "assert(" "src.isxmmindex()" ") failed", "expected to be xmm index" ); ::breakpoint(); } } while (0); | |||
| 9943 | assert(dst != src.xmmindex(), "instruction will #UD if dst and index are the same")do { if (!(dst != src.xmmindex())) { (*g_assert_poison) = 'X' ;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9943, "assert(" "dst != src.xmmindex()" ") failed", "instruction will #UD if dst and index are the same" ); ::breakpoint(); } } while (0); | |||
| 9944 | assert(mask != k0, "instruction will #UD if mask is in k0")do { if (!(mask != k0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9944, "assert(" "mask != k0" ") failed", "instruction will #UD if mask is in k0" ); ::breakpoint(); } } while (0); | |||
| 9945 | InstructionMark im(this); | |||
| 9946 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 9947 | attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); | |||
| 9948 | attributes.reset_is_clear_context(); | |||
| 9949 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 9950 | attributes.set_is_evex_instruction(); | |||
| 9951 | // swap src<->dst for encoding | |||
| 9952 | vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 9953 | emit_int8((unsigned char)0x90); | |||
| 9954 | emit_operand(dst, src); | |||
| 9955 | } | |||
| 9956 | ||||
| 9957 | void Assembler::evpgatherdq(XMMRegister dst, KRegister mask, Address src, int vector_len) { | |||
| 9958 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9958, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 9959 | assert(dst != xnoreg, "sanity")do { if (!(dst != xnoreg)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9959, "assert(" "dst != xnoreg" ") failed", "sanity"); ::breakpoint (); } } while (0); | |||
| 9960 | assert(src.isxmmindex(),"expected to be xmm index")do { if (!(src.isxmmindex())) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9960, "assert(" "src.isxmmindex()" ") failed", "expected to be xmm index" ); ::breakpoint(); } } while (0); | |||
| 9961 | assert(dst != src.xmmindex(), "instruction will #UD if dst and index are the same")do { if (!(dst != src.xmmindex())) { (*g_assert_poison) = 'X' ;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9961, "assert(" "dst != src.xmmindex()" ") failed", "instruction will #UD if dst and index are the same" ); ::breakpoint(); } } while (0); | |||
| 9962 | assert(mask != k0, "instruction will #UD if mask is in k0")do { if (!(mask != k0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9962, "assert(" "mask != k0" ") failed", "instruction will #UD if mask is in k0" ); ::breakpoint(); } } while (0); | |||
| 9963 | InstructionMark im(this); | |||
| 9964 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 9965 | attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); | |||
| 9966 | attributes.reset_is_clear_context(); | |||
| 9967 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 9968 | attributes.set_is_evex_instruction(); | |||
| 9969 | // swap src<->dst for encoding | |||
| 9970 | vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 9971 | emit_int8((unsigned char)0x90); | |||
| 9972 | emit_operand(dst, src); | |||
| 9973 | } | |||
| 9974 | ||||
| 9975 | void Assembler::evgatherdpd(XMMRegister dst, KRegister mask, Address src, int vector_len) { | |||
| 9976 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9976, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 9977 | assert(dst != xnoreg, "sanity")do { if (!(dst != xnoreg)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9977, "assert(" "dst != xnoreg" ") failed", "sanity"); ::breakpoint (); } } while (0); | |||
| 9978 | assert(src.isxmmindex(),"expected to be xmm index")do { if (!(src.isxmmindex())) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9978, "assert(" "src.isxmmindex()" ") failed", "expected to be xmm index" ); ::breakpoint(); } } while (0); | |||
| 9979 | assert(dst != src.xmmindex(), "instruction will #UD if dst and index are the same")do { if (!(dst != src.xmmindex())) { (*g_assert_poison) = 'X' ;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9979, "assert(" "dst != src.xmmindex()" ") failed", "instruction will #UD if dst and index are the same" ); ::breakpoint(); } } while (0); | |||
| 9980 | assert(mask != k0, "instruction will #UD if mask is in k0")do { if (!(mask != k0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9980, "assert(" "mask != k0" ") failed", "instruction will #UD if mask is in k0" ); ::breakpoint(); } } while (0); | |||
| 9981 | InstructionMark im(this); | |||
| 9982 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 9983 | attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); | |||
| 9984 | attributes.reset_is_clear_context(); | |||
| 9985 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 9986 | attributes.set_is_evex_instruction(); | |||
| 9987 | // swap src<->dst for encoding | |||
| 9988 | vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 9989 | emit_int8((unsigned char)0x92); | |||
| 9990 | emit_operand(dst, src); | |||
| 9991 | } | |||
| 9992 | ||||
| 9993 | void Assembler::evgatherdps(XMMRegister dst, KRegister mask, Address src, int vector_len) { | |||
| 9994 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9994, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 9995 | assert(dst != xnoreg, "sanity")do { if (!(dst != xnoreg)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9995, "assert(" "dst != xnoreg" ") failed", "sanity"); ::breakpoint (); } } while (0); | |||
| 9996 | assert(src.isxmmindex(),"expected to be xmm index")do { if (!(src.isxmmindex())) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9996, "assert(" "src.isxmmindex()" ") failed", "expected to be xmm index" ); ::breakpoint(); } } while (0); | |||
| 9997 | assert(dst != src.xmmindex(), "instruction will #UD if dst and index are the same")do { if (!(dst != src.xmmindex())) { (*g_assert_poison) = 'X' ;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9997, "assert(" "dst != src.xmmindex()" ") failed", "instruction will #UD if dst and index are the same" ); ::breakpoint(); } } while (0); | |||
| 9998 | assert(mask != k0, "instruction will #UD if mask is in k0")do { if (!(mask != k0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 9998, "assert(" "mask != k0" ") failed", "instruction will #UD if mask is in k0" ); ::breakpoint(); } } while (0); | |||
| 9999 | InstructionMark im(this); | |||
| 10000 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 10001 | attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); | |||
| 10002 | attributes.reset_is_clear_context(); | |||
| 10003 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 10004 | attributes.set_is_evex_instruction(); | |||
| 10005 | // swap src<->dst for encoding | |||
| 10006 | vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 10007 | emit_int8((unsigned char)0x92); | |||
| 10008 | emit_operand(dst, src); | |||
| 10009 | } | |||
| 10010 | ||||
| 10011 | void Assembler::evpscatterdd(Address dst, KRegister mask, XMMRegister src, int vector_len) { | |||
| 10012 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 10012, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 10013 | assert(mask != k0, "instruction will #UD if mask is in k0")do { if (!(mask != k0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 10013, "assert(" "mask != k0" ") failed", "instruction will #UD if mask is in k0" ); ::breakpoint(); } } while (0); | |||
| 10014 | InstructionMark im(this); | |||
| 10015 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 10016 | attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); | |||
| 10017 | attributes.reset_is_clear_context(); | |||
| 10018 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 10019 | attributes.set_is_evex_instruction(); | |||
| 10020 | vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 10021 | emit_int8((unsigned char)0xA0); | |||
| 10022 | emit_operand(src, dst); | |||
| 10023 | } | |||
| 10024 | ||||
| 10025 | void Assembler::evpscatterdq(Address dst, KRegister mask, XMMRegister src, int vector_len) { | |||
| 10026 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 10026, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 10027 | assert(mask != k0, "instruction will #UD if mask is in k0")do { if (!(mask != k0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 10027, "assert(" "mask != k0" ") failed", "instruction will #UD if mask is in k0" ); ::breakpoint(); } } while (0); | |||
| 10028 | InstructionMark im(this); | |||
| 10029 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 10030 | attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); | |||
| 10031 | attributes.reset_is_clear_context(); | |||
| 10032 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 10033 | attributes.set_is_evex_instruction(); | |||
| 10034 | vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 10035 | emit_int8((unsigned char)0xA0); | |||
| 10036 | emit_operand(src, dst); | |||
| 10037 | } | |||
| 10038 | ||||
| 10039 | void Assembler::evscatterdps(Address dst, KRegister mask, XMMRegister src, int vector_len) { | |||
| 10040 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 10040, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 10041 | assert(mask != k0, "instruction will #UD if mask is in k0")do { if (!(mask != k0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 10041, "assert(" "mask != k0" ") failed", "instruction will #UD if mask is in k0" ); ::breakpoint(); } } while (0); | |||
| 10042 | InstructionMark im(this); | |||
| 10043 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 10044 | attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); | |||
| 10045 | attributes.reset_is_clear_context(); | |||
| 10046 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 10047 | attributes.set_is_evex_instruction(); | |||
| 10048 | vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 10049 | emit_int8((unsigned char)0xA2); | |||
| 10050 | emit_operand(src, dst); | |||
| 10051 | } | |||
| 10052 | ||||
| 10053 | void Assembler::evscatterdpd(Address dst, KRegister mask, XMMRegister src, int vector_len) { | |||
| 10054 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 10054, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 10055 | assert(mask != k0, "instruction will #UD if mask is in k0")do { if (!(mask != k0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 10055, "assert(" "mask != k0" ") failed", "instruction will #UD if mask is in k0" ); ::breakpoint(); } } while (0); | |||
| 10056 | InstructionMark im(this); | |||
| 10057 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 10058 | attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); | |||
| 10059 | attributes.reset_is_clear_context(); | |||
| 10060 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 10061 | attributes.set_is_evex_instruction(); | |||
| 10062 | vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 10063 | emit_int8((unsigned char)0xA2); | |||
| 10064 | emit_operand(src, dst); | |||
| 10065 | } | |||
| 10066 | // Carry-Less Multiplication Quadword | |||
| 10067 | void Assembler::pclmulqdq(XMMRegister dst, XMMRegister src, int mask) { | |||
| 10068 | assert(VM_Version::supports_clmul(), "")do { if (!(VM_Version::supports_clmul())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 10068, "assert(" "VM_Version::supports_clmul()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 10069 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 10070 | int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 10071 | emit_int24(0x44, (0xC0 | encode), (unsigned char)mask); | |||
| 10072 | } | |||
| 10073 | ||||
| 10074 | // Carry-Less Multiplication Quadword | |||
| 10075 | void Assembler::vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask) { | |||
| 10076 | assert(VM_Version::supports_avx() && VM_Version::supports_clmul(), "")do { if (!(VM_Version::supports_avx() && VM_Version:: supports_clmul())) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 10076, "assert(" "VM_Version::supports_avx() && VM_Version::supports_clmul()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 10077 | InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 10078 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 10079 | emit_int24(0x44, (0xC0 | encode), (unsigned char)mask); | |||
| 10080 | } | |||
| 10081 | ||||
| 10082 | void Assembler::evpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask, int vector_len) { | |||
| 10083 | assert(VM_Version::supports_avx512_vpclmulqdq(), "Requires vector carryless multiplication support")do { if (!(VM_Version::supports_avx512_vpclmulqdq())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 10083, "assert(" "VM_Version::supports_avx512_vpclmulqdq()" ") failed", "Requires vector carryless multiplication support" ); ::breakpoint(); } } while (0); | |||
| 10084 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 10085 | attributes.set_is_evex_instruction(); | |||
| 10086 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 10087 | emit_int24(0x44, (0xC0 | encode), (unsigned char)mask); | |||
| 10088 | } | |||
| 10089 | ||||
| 10090 | void Assembler::vzeroupper_uncached() { | |||
| 10091 | if (VM_Version::supports_vzeroupper()) { | |||
| 10092 | InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 10093 | (void)vex_prefix_and_encode(0, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 10094 | emit_int8(0x77); | |||
| 10095 | } | |||
| 10096 | } | |||
| 10097 | ||||
| 10098 | void Assembler::fld_x(Address adr) { | |||
| 10099 | InstructionMark im(this); | |||
| 10100 | emit_int8((unsigned char)0xDB); | |||
| 10101 | emit_operand32(rbp, adr); | |||
| 10102 | } | |||
| 10103 | ||||
| 10104 | void Assembler::fstp_x(Address adr) { | |||
| 10105 | InstructionMark im(this); | |||
| 10106 | emit_int8((unsigned char)0xDB); | |||
| 10107 | emit_operand32(rdi, adr); | |||
| 10108 | } | |||
| 10109 | ||||
| 10110 | void Assembler::emit_operand32(Register reg, Address adr) { | |||
| 10111 | assert(reg->encoding() < 8, "no extended registers")do { if (!(reg->encoding() < 8)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 10111, "assert(" "reg->encoding() < 8" ") failed", "no extended registers" ); ::breakpoint(); } } while (0); | |||
| 10112 | assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers")do { if (!(!adr.base_needs_rex() && !adr.index_needs_rex ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 10112, "assert(" "!adr.base_needs_rex() && !adr.index_needs_rex()" ") failed", "no extended registers"); ::breakpoint(); } } while (0); | |||
| 10113 | emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, | |||
| 10114 | adr._rspec); | |||
| 10115 | } | |||
| 10116 | ||||
| 10117 | #ifndef _LP641 | |||
| 10118 | // 32bit only pieces of the assembler | |||
| 10119 | ||||
| 10120 | void Assembler::emms() { | |||
| 10121 | NOT_LP64(assert(VM_Version::supports_mmx(), "")); | |||
| 10122 | emit_int16(0x0F, 0x77); | |||
| 10123 | } | |||
| 10124 | ||||
| 10125 | void Assembler::vzeroupper() { | |||
| 10126 | vzeroupper_uncached(); | |||
| 10127 | } | |||
| 10128 | ||||
| 10129 | void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) { | |||
| 10130 | // NO PREFIX AS NEVER 64BIT | |||
| 10131 | InstructionMark im(this); | |||
| 10132 | emit_int16((unsigned char)0x81, (0xF8 | src1->encoding())); | |||
| 10133 | emit_data(imm32, rspec, 0); | |||
| 10134 | } | |||
| 10135 | ||||
| 10136 | void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) { | |||
| 10137 | // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs | |||
| 10138 | InstructionMark im(this); | |||
| 10139 | emit_int8((unsigned char)0x81); | |||
| 10140 | emit_operand(rdi, src1); | |||
| 10141 | emit_data(imm32, rspec, 0); | |||
| 10142 | } | |||
| 10143 | ||||
| 10144 | // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax, | |||
| 10145 | // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded | |||
| 10146 | // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise. | |||
| 10147 | void Assembler::cmpxchg8(Address adr) { | |||
| 10148 | InstructionMark im(this); | |||
| 10149 | emit_int16(0x0F, (unsigned char)0xC7); | |||
| 10150 | emit_operand(rcx, adr); | |||
| 10151 | } | |||
| 10152 | ||||
| 10153 | void Assembler::decl(Register dst) { | |||
| 10154 | // Don't use it directly. Use MacroAssembler::decrementl() instead. | |||
| 10155 | emit_int8(0x48 | dst->encoding()); | |||
| 10156 | } | |||
| 10157 | ||||
| 10158 | // 64bit doesn't use the x87 | |||
| 10159 | ||||
| 10160 | void Assembler::emit_farith(int b1, int b2, int i) { | |||
| 10161 | assert(isByte(b1) && isByte(b2), "wrong opcode")do { if (!(isByte(b1) && isByte(b2))) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 10161, "assert(" "isByte(b1) && isByte(b2)" ") failed" , "wrong opcode"); ::breakpoint(); } } while (0); | |||
| 10162 | assert(0 <= i && i < 8, "illegal stack offset")do { if (!(0 <= i && i < 8)) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 10162, "assert(" "0 <= i && i < 8" ") failed" , "illegal stack offset"); ::breakpoint(); } } while (0); | |||
| 10163 | emit_int16(b1, b2 + i); | |||
| 10164 | } | |||
| 10165 | ||||
| 10166 | void Assembler::fabs() { | |||
| 10167 | emit_int16((unsigned char)0xD9, (unsigned char)0xE1); | |||
| 10168 | } | |||
| 10169 | ||||
| 10170 | void Assembler::fadd(int i) { | |||
| 10171 | emit_farith(0xD8, 0xC0, i); | |||
| 10172 | } | |||
| 10173 | ||||
| 10174 | void Assembler::fadd_d(Address src) { | |||
| 10175 | InstructionMark im(this); | |||
| 10176 | emit_int8((unsigned char)0xDC); | |||
| 10177 | emit_operand32(rax, src); | |||
| 10178 | } | |||
| 10179 | ||||
| 10180 | void Assembler::fadd_s(Address src) { | |||
| 10181 | InstructionMark im(this); | |||
| 10182 | emit_int8((unsigned char)0xD8); | |||
| 10183 | emit_operand32(rax, src); | |||
| 10184 | } | |||
| 10185 | ||||
| 10186 | void Assembler::fadda(int i) { | |||
| 10187 | emit_farith(0xDC, 0xC0, i); | |||
| 10188 | } | |||
| 10189 | ||||
| 10190 | void Assembler::faddp(int i) { | |||
| 10191 | emit_farith(0xDE, 0xC0, i); | |||
| 10192 | } | |||
| 10193 | ||||
| 10194 | void Assembler::fchs() { | |||
| 10195 | emit_int16((unsigned char)0xD9, (unsigned char)0xE0); | |||
| 10196 | } | |||
| 10197 | ||||
| 10198 | void Assembler::fcom(int i) { | |||
| 10199 | emit_farith(0xD8, 0xD0, i); | |||
| 10200 | } | |||
| 10201 | ||||
| 10202 | void Assembler::fcomp(int i) { | |||
| 10203 | emit_farith(0xD8, 0xD8, i); | |||
| 10204 | } | |||
| 10205 | ||||
| 10206 | void Assembler::fcomp_d(Address src) { | |||
| 10207 | InstructionMark im(this); | |||
| 10208 | emit_int8((unsigned char)0xDC); | |||
| 10209 | emit_operand32(rbx, src); | |||
| 10210 | } | |||
| 10211 | ||||
| 10212 | void Assembler::fcomp_s(Address src) { | |||
| 10213 | InstructionMark im(this); | |||
| 10214 | emit_int8((unsigned char)0xD8); | |||
| 10215 | emit_operand32(rbx, src); | |||
| 10216 | } | |||
| 10217 | ||||
| 10218 | void Assembler::fcompp() { | |||
| 10219 | emit_int16((unsigned char)0xDE, (unsigned char)0xD9); | |||
| 10220 | } | |||
| 10221 | ||||
| 10222 | void Assembler::fcos() { | |||
| 10223 | emit_int16((unsigned char)0xD9, (unsigned char)0xFF); | |||
| 10224 | } | |||
| 10225 | ||||
| 10226 | void Assembler::fdecstp() { | |||
| 10227 | emit_int16((unsigned char)0xD9, (unsigned char)0xF6); | |||
| 10228 | } | |||
| 10229 | ||||
| 10230 | void Assembler::fdiv(int i) { | |||
| 10231 | emit_farith(0xD8, 0xF0, i); | |||
| 10232 | } | |||
| 10233 | ||||
| 10234 | void Assembler::fdiv_d(Address src) { | |||
| 10235 | InstructionMark im(this); | |||
| 10236 | emit_int8((unsigned char)0xDC); | |||
| 10237 | emit_operand32(rsi, src); | |||
| 10238 | } | |||
| 10239 | ||||
| 10240 | void Assembler::fdiv_s(Address src) { | |||
| 10241 | InstructionMark im(this); | |||
| 10242 | emit_int8((unsigned char)0xD8); | |||
| 10243 | emit_operand32(rsi, src); | |||
| 10244 | } | |||
| 10245 | ||||
| 10246 | void Assembler::fdiva(int i) { | |||
| 10247 | emit_farith(0xDC, 0xF8, i); | |||
| 10248 | } | |||
| 10249 | ||||
| 10250 | // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994) | |||
| 10251 | // is erroneous for some of the floating-point instructions below. | |||
| 10252 | ||||
| 10253 | void Assembler::fdivp(int i) { | |||
| 10254 | emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong) | |||
| 10255 | } | |||
| 10256 | ||||
| 10257 | void Assembler::fdivr(int i) { | |||
| 10258 | emit_farith(0xD8, 0xF8, i); | |||
| 10259 | } | |||
| 10260 | ||||
| 10261 | void Assembler::fdivr_d(Address src) { | |||
| 10262 | InstructionMark im(this); | |||
| 10263 | emit_int8((unsigned char)0xDC); | |||
| 10264 | emit_operand32(rdi, src); | |||
| 10265 | } | |||
| 10266 | ||||
| 10267 | void Assembler::fdivr_s(Address src) { | |||
| 10268 | InstructionMark im(this); | |||
| 10269 | emit_int8((unsigned char)0xD8); | |||
| 10270 | emit_operand32(rdi, src); | |||
| 10271 | } | |||
| 10272 | ||||
| 10273 | void Assembler::fdivra(int i) { | |||
| 10274 | emit_farith(0xDC, 0xF0, i); | |||
| 10275 | } | |||
| 10276 | ||||
| 10277 | void Assembler::fdivrp(int i) { | |||
| 10278 | emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong) | |||
| 10279 | } | |||
| 10280 | ||||
| 10281 | void Assembler::ffree(int i) { | |||
| 10282 | emit_farith(0xDD, 0xC0, i); | |||
| 10283 | } | |||
| 10284 | ||||
| 10285 | void Assembler::fild_d(Address adr) { | |||
| 10286 | InstructionMark im(this); | |||
| 10287 | emit_int8((unsigned char)0xDF); | |||
| 10288 | emit_operand32(rbp, adr); | |||
| 10289 | } | |||
| 10290 | ||||
| 10291 | void Assembler::fild_s(Address adr) { | |||
| 10292 | InstructionMark im(this); | |||
| 10293 | emit_int8((unsigned char)0xDB); | |||
| 10294 | emit_operand32(rax, adr); | |||
| 10295 | } | |||
| 10296 | ||||
| 10297 | void Assembler::fincstp() { | |||
| 10298 | emit_int16((unsigned char)0xD9, (unsigned char)0xF7); | |||
| 10299 | } | |||
| 10300 | ||||
| 10301 | void Assembler::finit() { | |||
| 10302 | emit_int24((unsigned char)0x9B, (unsigned char)0xDB, (unsigned char)0xE3); | |||
| 10303 | } | |||
| 10304 | ||||
| 10305 | void Assembler::fist_s(Address adr) { | |||
| 10306 | InstructionMark im(this); | |||
| 10307 | emit_int8((unsigned char)0xDB); | |||
| 10308 | emit_operand32(rdx, adr); | |||
| 10309 | } | |||
| 10310 | ||||
| 10311 | void Assembler::fistp_d(Address adr) { | |||
| 10312 | InstructionMark im(this); | |||
| 10313 | emit_int8((unsigned char)0xDF); | |||
| 10314 | emit_operand32(rdi, adr); | |||
| 10315 | } | |||
| 10316 | ||||
| 10317 | void Assembler::fistp_s(Address adr) { | |||
| 10318 | InstructionMark im(this); | |||
| 10319 | emit_int8((unsigned char)0xDB); | |||
| 10320 | emit_operand32(rbx, adr); | |||
| 10321 | } | |||
| 10322 | ||||
| 10323 | void Assembler::fld1() { | |||
| 10324 | emit_int16((unsigned char)0xD9, (unsigned char)0xE8); | |||
| 10325 | } | |||
| 10326 | ||||
| 10327 | void Assembler::fld_d(Address adr) { | |||
| 10328 | InstructionMark im(this); | |||
| 10329 | emit_int8((unsigned char)0xDD); | |||
| 10330 | emit_operand32(rax, adr); | |||
| 10331 | } | |||
| 10332 | ||||
| 10333 | void Assembler::fld_s(Address adr) { | |||
| 10334 | InstructionMark im(this); | |||
| 10335 | emit_int8((unsigned char)0xD9); | |||
| 10336 | emit_operand32(rax, adr); | |||
| 10337 | } | |||
| 10338 | ||||
| 10339 | ||||
| 10340 | void Assembler::fld_s(int index) { | |||
| 10341 | emit_farith(0xD9, 0xC0, index); | |||
| 10342 | } | |||
| 10343 | ||||
| 10344 | void Assembler::fldcw(Address src) { | |||
| 10345 | InstructionMark im(this); | |||
| 10346 | emit_int8((unsigned char)0xD9); | |||
| 10347 | emit_operand32(rbp, src); | |||
| 10348 | } | |||
| 10349 | ||||
| 10350 | void Assembler::fldenv(Address src) { | |||
| 10351 | InstructionMark im(this); | |||
| 10352 | emit_int8((unsigned char)0xD9); | |||
| 10353 | emit_operand32(rsp, src); | |||
| 10354 | } | |||
| 10355 | ||||
| 10356 | void Assembler::fldlg2() { | |||
| 10357 | emit_int16((unsigned char)0xD9, (unsigned char)0xEC); | |||
| 10358 | } | |||
| 10359 | ||||
| 10360 | void Assembler::fldln2() { | |||
| 10361 | emit_int16((unsigned char)0xD9, (unsigned char)0xED); | |||
| 10362 | } | |||
| 10363 | ||||
| 10364 | void Assembler::fldz() { | |||
| 10365 | emit_int16((unsigned char)0xD9, (unsigned char)0xEE); | |||
| 10366 | } | |||
| 10367 | ||||
| 10368 | void Assembler::flog() { | |||
| 10369 | fldln2(); | |||
| 10370 | fxch(); | |||
| 10371 | fyl2x(); | |||
| 10372 | } | |||
| 10373 | ||||
| 10374 | void Assembler::flog10() { | |||
| 10375 | fldlg2(); | |||
| 10376 | fxch(); | |||
| 10377 | fyl2x(); | |||
| 10378 | } | |||
| 10379 | ||||
| 10380 | void Assembler::fmul(int i) { | |||
| 10381 | emit_farith(0xD8, 0xC8, i); | |||
| 10382 | } | |||
| 10383 | ||||
| 10384 | void Assembler::fmul_d(Address src) { | |||
| 10385 | InstructionMark im(this); | |||
| 10386 | emit_int8((unsigned char)0xDC); | |||
| 10387 | emit_operand32(rcx, src); | |||
| 10388 | } | |||
| 10389 | ||||
| 10390 | void Assembler::fmul_s(Address src) { | |||
| 10391 | InstructionMark im(this); | |||
| 10392 | emit_int8((unsigned char)0xD8); | |||
| 10393 | emit_operand32(rcx, src); | |||
| 10394 | } | |||
| 10395 | ||||
| 10396 | void Assembler::fmula(int i) { | |||
| 10397 | emit_farith(0xDC, 0xC8, i); | |||
| 10398 | } | |||
| 10399 | ||||
| 10400 | void Assembler::fmulp(int i) { | |||
| 10401 | emit_farith(0xDE, 0xC8, i); | |||
| 10402 | } | |||
| 10403 | ||||
| 10404 | void Assembler::fnsave(Address dst) { | |||
| 10405 | InstructionMark im(this); | |||
| 10406 | emit_int8((unsigned char)0xDD); | |||
| 10407 | emit_operand32(rsi, dst); | |||
| 10408 | } | |||
| 10409 | ||||
| 10410 | void Assembler::fnstcw(Address src) { | |||
| 10411 | InstructionMark im(this); | |||
| 10412 | emit_int16((unsigned char)0x9B, (unsigned char)0xD9); | |||
| 10413 | emit_operand32(rdi, src); | |||
| 10414 | } | |||
| 10415 | ||||
| 10416 | void Assembler::fnstsw_ax() { | |||
| 10417 | emit_int16((unsigned char)0xDF, (unsigned char)0xE0); | |||
| 10418 | } | |||
| 10419 | ||||
| 10420 | void Assembler::fprem() { | |||
| 10421 | emit_int16((unsigned char)0xD9, (unsigned char)0xF8); | |||
| 10422 | } | |||
| 10423 | ||||
| 10424 | void Assembler::fprem1() { | |||
| 10425 | emit_int16((unsigned char)0xD9, (unsigned char)0xF5); | |||
| 10426 | } | |||
| 10427 | ||||
| 10428 | void Assembler::frstor(Address src) { | |||
| 10429 | InstructionMark im(this); | |||
| 10430 | emit_int8((unsigned char)0xDD); | |||
| 10431 | emit_operand32(rsp, src); | |||
| 10432 | } | |||
| 10433 | ||||
| 10434 | void Assembler::fsin() { | |||
| 10435 | emit_int16((unsigned char)0xD9, (unsigned char)0xFE); | |||
| 10436 | } | |||
| 10437 | ||||
| 10438 | void Assembler::fsqrt() { | |||
| 10439 | emit_int16((unsigned char)0xD9, (unsigned char)0xFA); | |||
| 10440 | } | |||
| 10441 | ||||
| 10442 | void Assembler::fst_d(Address adr) { | |||
| 10443 | InstructionMark im(this); | |||
| 10444 | emit_int8((unsigned char)0xDD); | |||
| 10445 | emit_operand32(rdx, adr); | |||
| 10446 | } | |||
| 10447 | ||||
| 10448 | void Assembler::fst_s(Address adr) { | |||
| 10449 | InstructionMark im(this); | |||
| 10450 | emit_int8((unsigned char)0xD9); | |||
| 10451 | emit_operand32(rdx, adr); | |||
| 10452 | } | |||
| 10453 | ||||
| 10454 | void Assembler::fstp_d(Address adr) { | |||
| 10455 | InstructionMark im(this); | |||
| 10456 | emit_int8((unsigned char)0xDD); | |||
| 10457 | emit_operand32(rbx, adr); | |||
| 10458 | } | |||
| 10459 | ||||
| 10460 | void Assembler::fstp_d(int index) { | |||
| 10461 | emit_farith(0xDD, 0xD8, index); | |||
| 10462 | } | |||
| 10463 | ||||
| 10464 | void Assembler::fstp_s(Address adr) { | |||
| 10465 | InstructionMark im(this); | |||
| 10466 | emit_int8((unsigned char)0xD9); | |||
| 10467 | emit_operand32(rbx, adr); | |||
| 10468 | } | |||
| 10469 | ||||
| 10470 | void Assembler::fsub(int i) { | |||
| 10471 | emit_farith(0xD8, 0xE0, i); | |||
| 10472 | } | |||
| 10473 | ||||
| 10474 | void Assembler::fsub_d(Address src) { | |||
| 10475 | InstructionMark im(this); | |||
| 10476 | emit_int8((unsigned char)0xDC); | |||
| 10477 | emit_operand32(rsp, src); | |||
| 10478 | } | |||
| 10479 | ||||
| 10480 | void Assembler::fsub_s(Address src) { | |||
| 10481 | InstructionMark im(this); | |||
| 10482 | emit_int8((unsigned char)0xD8); | |||
| 10483 | emit_operand32(rsp, src); | |||
| 10484 | } | |||
| 10485 | ||||
| 10486 | void Assembler::fsuba(int i) { | |||
| 10487 | emit_farith(0xDC, 0xE8, i); | |||
| 10488 | } | |||
| 10489 | ||||
| 10490 | void Assembler::fsubp(int i) { | |||
| 10491 | emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong) | |||
| 10492 | } | |||
| 10493 | ||||
| 10494 | void Assembler::fsubr(int i) { | |||
| 10495 | emit_farith(0xD8, 0xE8, i); | |||
| 10496 | } | |||
| 10497 | ||||
| 10498 | void Assembler::fsubr_d(Address src) { | |||
| 10499 | InstructionMark im(this); | |||
| 10500 | emit_int8((unsigned char)0xDC); | |||
| 10501 | emit_operand32(rbp, src); | |||
| 10502 | } | |||
| 10503 | ||||
| 10504 | void Assembler::fsubr_s(Address src) { | |||
| 10505 | InstructionMark im(this); | |||
| 10506 | emit_int8((unsigned char)0xD8); | |||
| 10507 | emit_operand32(rbp, src); | |||
| 10508 | } | |||
| 10509 | ||||
| 10510 | void Assembler::fsubra(int i) { | |||
| 10511 | emit_farith(0xDC, 0xE0, i); | |||
| 10512 | } | |||
| 10513 | ||||
| 10514 | void Assembler::fsubrp(int i) { | |||
| 10515 | emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong) | |||
| 10516 | } | |||
| 10517 | ||||
| 10518 | void Assembler::ftan() { | |||
| 10519 | emit_int32((unsigned char)0xD9, (unsigned char)0xF2, (unsigned char)0xDD, (unsigned char)0xD8); | |||
| 10520 | } | |||
| 10521 | ||||
| 10522 | void Assembler::ftst() { | |||
| 10523 | emit_int16((unsigned char)0xD9, (unsigned char)0xE4); | |||
| 10524 | } | |||
| 10525 | ||||
| 10526 | void Assembler::fucomi(int i) { | |||
| 10527 | // make sure the instruction is supported (introduced for P6, together with cmov) | |||
| 10528 | guarantee(VM_Version::supports_cmov(), "illegal instruction")do { if (!(VM_Version::supports_cmov())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 10528, "guarantee(" "VM_Version::supports_cmov()" ") failed" , "illegal instruction"); ::breakpoint(); } } while (0); | |||
| 10529 | emit_farith(0xDB, 0xE8, i); | |||
| 10530 | } | |||
| 10531 | ||||
| 10532 | void Assembler::fucomip(int i) { | |||
| 10533 | // make sure the instruction is supported (introduced for P6, together with cmov) | |||
| 10534 | guarantee(VM_Version::supports_cmov(), "illegal instruction")do { if (!(VM_Version::supports_cmov())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 10534, "guarantee(" "VM_Version::supports_cmov()" ") failed" , "illegal instruction"); ::breakpoint(); } } while (0); | |||
| 10535 | emit_farith(0xDF, 0xE8, i); | |||
| 10536 | } | |||
| 10537 | ||||
| 10538 | void Assembler::fwait() { | |||
| 10539 | emit_int8((unsigned char)0x9B); | |||
| 10540 | } | |||
| 10541 | ||||
| 10542 | void Assembler::fxch(int i) { | |||
| 10543 | emit_farith(0xD9, 0xC8, i); | |||
| 10544 | } | |||
| 10545 | ||||
| 10546 | void Assembler::fyl2x() { | |||
| 10547 | emit_int16((unsigned char)0xD9, (unsigned char)0xF1); | |||
| 10548 | } | |||
| 10549 | ||||
| 10550 | void Assembler::frndint() { | |||
| 10551 | emit_int16((unsigned char)0xD9, (unsigned char)0xFC); | |||
| 10552 | } | |||
| 10553 | ||||
| 10554 | void Assembler::f2xm1() { | |||
| 10555 | emit_int16((unsigned char)0xD9, (unsigned char)0xF0); | |||
| 10556 | } | |||
| 10557 | ||||
| 10558 | void Assembler::fldl2e() { | |||
| 10559 | emit_int16((unsigned char)0xD9, (unsigned char)0xEA); | |||
| 10560 | } | |||
| 10561 | #endif // !_LP64 | |||
| 10562 | ||||
| 10563 | // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding. | |||
| 10564 | static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 }; | |||
| 10565 | // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding. | |||
| 10566 | static int simd_opc[4] = { 0, 0, 0x38, 0x3A }; | |||
| 10567 | ||||
| 10568 | // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding. | |||
| 10569 | void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) { | |||
| 10570 | if (pre > 0) { | |||
| 10571 | emit_int8(simd_pre[pre]); | |||
| 10572 | } | |||
| 10573 | if (rex_w) { | |||
| 10574 | prefixq(adr, xreg); | |||
| 10575 | } else { | |||
| 10576 | prefix(adr, xreg); | |||
| 10577 | } | |||
| 10578 | if (opc > 0) { | |||
| 10579 | emit_int8(0x0F); | |||
| 10580 | int opc2 = simd_opc[opc]; | |||
| 10581 | if (opc2 > 0) { | |||
| 10582 | emit_int8(opc2); | |||
| 10583 | } | |||
| 10584 | } | |||
| 10585 | } | |||
| 10586 | ||||
| 10587 | int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) { | |||
| 10588 | if (pre > 0) { | |||
| 10589 | emit_int8(simd_pre[pre]); | |||
| 10590 | } | |||
| 10591 | int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) : prefix_and_encode(dst_enc, src_enc); | |||
| 10592 | if (opc > 0) { | |||
| 10593 | emit_int8(0x0F); | |||
| 10594 | int opc2 = simd_opc[opc]; | |||
| 10595 | if (opc2 > 0) { | |||
| 10596 | emit_int8(opc2); | |||
| 10597 | } | |||
| 10598 | } | |||
| 10599 | return encode; | |||
| 10600 | } | |||
| 10601 | ||||
| 10602 | ||||
| 10603 | void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, int nds_enc, VexSimdPrefix pre, VexOpcode opc) { | |||
| 10604 | int vector_len = _attributes->get_vector_len(); | |||
| 10605 | bool vex_w = _attributes->is_rex_vex_w(); | |||
| 10606 | if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) { | |||
| 10607 | int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0); | |||
| 10608 | byte1 = (~byte1) & 0xE0; | |||
| 10609 | byte1 |= opc; | |||
| 10610 | ||||
| 10611 | int byte2 = ((~nds_enc) & 0xf) << 3; | |||
| 10612 | byte2 |= (vex_w ? VEX_W : 0) | ((vector_len > 0) ? 4 : 0) | pre; | |||
| 10613 | ||||
| 10614 | emit_int24((unsigned char)VEX_3bytes, byte1, byte2); | |||
| 10615 | } else { | |||
| 10616 | int byte1 = vex_r ? VEX_R : 0; | |||
| 10617 | byte1 = (~byte1) & 0x80; | |||
| 10618 | byte1 |= ((~nds_enc) & 0xf) << 3; | |||
| 10619 | byte1 |= ((vector_len > 0 ) ? 4 : 0) | pre; | |||
| 10620 | emit_int16((unsigned char)VEX_2bytes, byte1); | |||
| 10621 | } | |||
| 10622 | } | |||
| 10623 | ||||
| 10624 | // This is a 4 byte encoding | |||
| 10625 | void Assembler::evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool evex_r, bool evex_v, int nds_enc, VexSimdPrefix pre, VexOpcode opc){ | |||
| 10626 | // EVEX 0x62 prefix | |||
| 10627 | // byte1 = EVEX_4bytes; | |||
| 10628 | ||||
| 10629 | bool vex_w = _attributes->is_rex_vex_w(); | |||
| 10630 | int evex_encoding = (vex_w ? VEX_W : 0); | |||
| 10631 | // EVEX.b is not currently used for broadcast of single element or data rounding modes | |||
| 10632 | _attributes->set_evex_encoding(evex_encoding); | |||
| 10633 | ||||
| 10634 | // P0: byte 2, initialized to RXBR`00mm | |||
| 10635 | // instead of not'd | |||
| 10636 | int byte2 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0) | (evex_r ? EVEX_Rb : 0); | |||
| 10637 | byte2 = (~byte2) & 0xF0; | |||
| 10638 | // confine opc opcode extensions in mm bits to lower two bits | |||
| 10639 | // of form {0F, 0F_38, 0F_3A} | |||
| 10640 | byte2 |= opc; | |||
| 10641 | ||||
| 10642 | // P1: byte 3 as Wvvvv1pp | |||
| 10643 | int byte3 = ((~nds_enc) & 0xf) << 3; | |||
| 10644 | // p[10] is always 1 | |||
| 10645 | byte3 |= EVEX_F; | |||
| 10646 | byte3 |= (vex_w & 1) << 7; | |||
| 10647 | // confine pre opcode extensions in pp bits to lower two bits | |||
| 10648 | // of form {66, F3, F2} | |||
| 10649 | byte3 |= pre; | |||
| 10650 | ||||
| 10651 | // P2: byte 4 as zL'Lbv'aaa | |||
| 10652 | // kregs are implemented in the low 3 bits as aaa | |||
| 10653 | int byte4 = (_attributes->is_no_reg_mask()) ? | |||
| 10654 | 0 : | |||
| 10655 | _attributes->get_embedded_opmask_register_specifier(); | |||
| 10656 | // EVEX.v` for extending EVEX.vvvv or VIDX | |||
| 10657 | byte4 |= (evex_v ? 0: EVEX_V); | |||
| 10658 | // third EXEC.b for broadcast actions | |||
| 10659 | byte4 |= (_attributes->is_extended_context() ? EVEX_Rb : 0); | |||
| 10660 | // fourth EVEX.L'L for vector length : 0 is 128, 1 is 256, 2 is 512, currently we do not support 1024 | |||
| 10661 | byte4 |= ((_attributes->get_vector_len())& 0x3) << 5; | |||
| 10662 | // last is EVEX.z for zero/merge actions | |||
| 10663 | if (_attributes->is_no_reg_mask() == false && | |||
| 10664 | _attributes->get_embedded_opmask_register_specifier() != 0) { | |||
| 10665 | byte4 |= (_attributes->is_clear_context() ? EVEX_Z : 0); | |||
| 10666 | } | |||
| 10667 | ||||
| 10668 | emit_int32(EVEX_4bytes, byte2, byte3, byte4); | |||
| 10669 | } | |||
| 10670 | ||||
| 10671 | void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) { | |||
| 10672 | bool vex_r = (xreg_enc & 8) == 8; | |||
| 10673 | bool vex_b = adr.base_needs_rex(); | |||
| 10674 | bool vex_x; | |||
| 10675 | if (adr.isxmmindex()) { | |||
| 10676 | vex_x = adr.xmmindex_needs_rex(); | |||
| 10677 | } else { | |||
| 10678 | vex_x = adr.index_needs_rex(); | |||
| 10679 | } | |||
| 10680 | set_attributes(attributes); | |||
| 10681 | attributes->set_current_assembler(this); | |||
| 10682 | ||||
| 10683 | // For EVEX instruction (which is not marked as pure EVEX instruction) check and see if this instruction | |||
| 10684 | // is allowed in legacy mode and has resources which will fit in it. | |||
| 10685 | // Pure EVEX instructions will have is_evex_instruction set in their definition. | |||
| 10686 | if (!attributes->is_legacy_mode()) { | |||
| 10687 | if (UseAVX > 2 && !attributes->is_evex_instruction() && !is_managed()) { | |||
| 10688 | if ((attributes->get_vector_len() != AVX_512bit) && (nds_enc < 16) && (xreg_enc < 16)) { | |||
| 10689 | attributes->set_is_legacy_mode(); | |||
| 10690 | } | |||
| 10691 | } | |||
| 10692 | } | |||
| 10693 | ||||
| 10694 | if (UseAVX > 2) { | |||
| 10695 | assert(((!attributes->uses_vl()) ||do { if (!(((!attributes->uses_vl()) || (attributes->get_vector_len () == AVX_512bit) || (!_legacy_mode_vl) || (attributes->is_legacy_mode ())))) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 10698, "assert(" "((!attributes->uses_vl()) || (attributes->get_vector_len() == AVX_512bit) || (!_legacy_mode_vl) || (attributes->is_legacy_mode()))" ") failed", "XMM register should be 0-15"); ::breakpoint(); } } while (0) | |||
| 10696 | (attributes->get_vector_len() == AVX_512bit) ||do { if (!(((!attributes->uses_vl()) || (attributes->get_vector_len () == AVX_512bit) || (!_legacy_mode_vl) || (attributes->is_legacy_mode ())))) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 10698, "assert(" "((!attributes->uses_vl()) || (attributes->get_vector_len() == AVX_512bit) || (!_legacy_mode_vl) || (attributes->is_legacy_mode()))" ") failed", "XMM register should be 0-15"); ::breakpoint(); } } while (0) | |||
| 10697 | (!_legacy_mode_vl) ||do { if (!(((!attributes->uses_vl()) || (attributes->get_vector_len () == AVX_512bit) || (!_legacy_mode_vl) || (attributes->is_legacy_mode ())))) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 10698, "assert(" "((!attributes->uses_vl()) || (attributes->get_vector_len() == AVX_512bit) || (!_legacy_mode_vl) || (attributes->is_legacy_mode()))" ") failed", "XMM register should be 0-15"); ::breakpoint(); } } while (0) | |||
| 10698 | (attributes->is_legacy_mode())),"XMM register should be 0-15")do { if (!(((!attributes->uses_vl()) || (attributes->get_vector_len () == AVX_512bit) || (!_legacy_mode_vl) || (attributes->is_legacy_mode ())))) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 10698, "assert(" "((!attributes->uses_vl()) || (attributes->get_vector_len() == AVX_512bit) || (!_legacy_mode_vl) || (attributes->is_legacy_mode()))" ") failed", "XMM register should be 0-15"); ::breakpoint(); } } while (0); | |||
| 10699 | assert(((nds_enc < 16 && xreg_enc < 16) || (!attributes->is_legacy_mode())),"XMM register should be 0-15")do { if (!(((nds_enc < 16 && xreg_enc < 16) || ( !attributes->is_legacy_mode())))) { (*g_assert_poison) = 'X' ;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 10699, "assert(" "((nds_enc < 16 && xreg_enc < 16) || (!attributes->is_legacy_mode()))" ") failed", "XMM register should be 0-15"); ::breakpoint(); } } while (0); | |||
| 10700 | } | |||
| 10701 | ||||
| 10702 | clear_managed(); | |||
| 10703 | if (UseAVX > 2 && !attributes->is_legacy_mode()) | |||
| 10704 | { | |||
| 10705 | bool evex_r = (xreg_enc >= 16); | |||
| 10706 | bool evex_v; | |||
| 10707 | // EVEX.V' is set to true when VSIB is used as we may need to use higher order XMM registers (16-31) | |||
| 10708 | if (adr.isxmmindex()) { | |||
| 10709 | evex_v = ((adr._xmmindex->encoding() > 15) ? true : false); | |||
| 10710 | } else { | |||
| 10711 | evex_v = (nds_enc >= 16); | |||
| 10712 | } | |||
| 10713 | attributes->set_is_evex_instruction(); | |||
| 10714 | evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc); | |||
| 10715 | } else { | |||
| 10716 | if (UseAVX > 2 && attributes->is_rex_vex_w_reverted()) { | |||
| 10717 | attributes->set_rex_vex_w(false); | |||
| 10718 | } | |||
| 10719 | vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc); | |||
| 10720 | } | |||
| 10721 | } | |||
| 10722 | ||||
| 10723 | int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) { | |||
| 10724 | bool vex_r = (dst_enc & 8) == 8; | |||
| 10725 | bool vex_b = (src_enc & 8) == 8; | |||
| 10726 | bool vex_x = false; | |||
| 10727 | set_attributes(attributes); | |||
| 10728 | attributes->set_current_assembler(this); | |||
| 10729 | ||||
| 10730 | // For EVEX instruction (which is not marked as pure EVEX instruction) check and see if this instruction | |||
| 10731 | // is allowed in legacy mode and has resources which will fit in it. | |||
| 10732 | // Pure EVEX instructions will have is_evex_instruction set in their definition. | |||
| 10733 | if (!attributes->is_legacy_mode()) { | |||
| 10734 | if (UseAVX > 2 && !attributes->is_evex_instruction() && !is_managed()) { | |||
| 10735 | if ((!attributes->uses_vl() || (attributes->get_vector_len() != AVX_512bit)) && | |||
| 10736 | (dst_enc < 16) && (nds_enc < 16) && (src_enc < 16)) { | |||
| 10737 | attributes->set_is_legacy_mode(); | |||
| 10738 | } | |||
| 10739 | } | |||
| 10740 | } | |||
| 10741 | ||||
| 10742 | if (UseAVX > 2) { | |||
| 10743 | // All the scalar fp instructions (with uses_vl as false) can have legacy_mode as false | |||
| 10744 | // Instruction with uses_vl true are vector instructions | |||
| 10745 | // All the vector instructions with AVX_512bit length can have legacy_mode as false | |||
| 10746 | // All the vector instructions with < AVX_512bit length can have legacy_mode as false if AVX512vl() is supported | |||
| 10747 | // Rest all should have legacy_mode set as true | |||
| 10748 | assert(((!attributes->uses_vl()) ||do { if (!(((!attributes->uses_vl()) || (attributes->get_vector_len () == AVX_512bit) || (!_legacy_mode_vl) || (attributes->is_legacy_mode ())))) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 10751, "assert(" "((!attributes->uses_vl()) || (attributes->get_vector_len() == AVX_512bit) || (!_legacy_mode_vl) || (attributes->is_legacy_mode()))" ") failed", "XMM register should be 0-15"); ::breakpoint(); } } while (0) | |||
| 10749 | (attributes->get_vector_len() == AVX_512bit) ||do { if (!(((!attributes->uses_vl()) || (attributes->get_vector_len () == AVX_512bit) || (!_legacy_mode_vl) || (attributes->is_legacy_mode ())))) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 10751, "assert(" "((!attributes->uses_vl()) || (attributes->get_vector_len() == AVX_512bit) || (!_legacy_mode_vl) || (attributes->is_legacy_mode()))" ") failed", "XMM register should be 0-15"); ::breakpoint(); } } while (0) | |||
| 10750 | (!_legacy_mode_vl) ||do { if (!(((!attributes->uses_vl()) || (attributes->get_vector_len () == AVX_512bit) || (!_legacy_mode_vl) || (attributes->is_legacy_mode ())))) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 10751, "assert(" "((!attributes->uses_vl()) || (attributes->get_vector_len() == AVX_512bit) || (!_legacy_mode_vl) || (attributes->is_legacy_mode()))" ") failed", "XMM register should be 0-15"); ::breakpoint(); } } while (0) | |||
| 10751 | (attributes->is_legacy_mode())),"XMM register should be 0-15")do { if (!(((!attributes->uses_vl()) || (attributes->get_vector_len () == AVX_512bit) || (!_legacy_mode_vl) || (attributes->is_legacy_mode ())))) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 10751, "assert(" "((!attributes->uses_vl()) || (attributes->get_vector_len() == AVX_512bit) || (!_legacy_mode_vl) || (attributes->is_legacy_mode()))" ") failed", "XMM register should be 0-15"); ::breakpoint(); } } while (0); | |||
| 10752 | // Instruction with legacy_mode true should have dst, nds and src < 15 | |||
| 10753 | assert(((dst_enc < 16 && nds_enc < 16 && src_enc < 16) || (!attributes->is_legacy_mode())),"XMM register should be 0-15")do { if (!(((dst_enc < 16 && nds_enc < 16 && src_enc < 16) || (!attributes->is_legacy_mode())))) { ( *g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 10753, "assert(" "((dst_enc < 16 && nds_enc < 16 && src_enc < 16) || (!attributes->is_legacy_mode()))" ") failed", "XMM register should be 0-15"); ::breakpoint(); } } while (0); | |||
| 10754 | } | |||
| 10755 | ||||
| 10756 | clear_managed(); | |||
| 10757 | if (UseAVX > 2 && !attributes->is_legacy_mode()) | |||
| 10758 | { | |||
| 10759 | bool evex_r = (dst_enc >= 16); | |||
| 10760 | bool evex_v = (nds_enc >= 16); | |||
| 10761 | // can use vex_x as bank extender on rm encoding | |||
| 10762 | vex_x = (src_enc >= 16); | |||
| 10763 | attributes->set_is_evex_instruction(); | |||
| 10764 | evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc); | |||
| 10765 | } else { | |||
| 10766 | if (UseAVX > 2 && attributes->is_rex_vex_w_reverted()) { | |||
| 10767 | attributes->set_rex_vex_w(false); | |||
| 10768 | } | |||
| 10769 | vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc); | |||
| 10770 | } | |||
| 10771 | ||||
| 10772 | // return modrm byte components for operands | |||
| 10773 | return (((dst_enc & 7) << 3) | (src_enc & 7)); | |||
| 10774 | } | |||
| 10775 | ||||
| 10776 | ||||
| 10777 | void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre, | |||
| 10778 | VexOpcode opc, InstructionAttr *attributes) { | |||
| 10779 | if (UseAVX > 0) { | |||
| 10780 | int xreg_enc = xreg->encoding(); | |||
| 10781 | int nds_enc = nds->is_valid() ? nds->encoding() : 0; | |||
| 10782 | vex_prefix(adr, nds_enc, xreg_enc, pre, opc, attributes); | |||
| 10783 | } else { | |||
| 10784 | assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding")do { if (!((nds == xreg) || (nds == xnoreg))) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 10784, "assert(" "(nds == xreg) || (nds == xnoreg)" ") failed" , "wrong sse encoding"); ::breakpoint(); } } while (0); | |||
| 10785 | rex_prefix(adr, xreg, pre, opc, attributes->is_rex_vex_w()); | |||
| 10786 | } | |||
| 10787 | } | |||
| 10788 | ||||
| 10789 | int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre, | |||
| 10790 | VexOpcode opc, InstructionAttr *attributes) { | |||
| 10791 | int dst_enc = dst->encoding(); | |||
| 10792 | int src_enc = src->encoding(); | |||
| 10793 | if (UseAVX > 0) { | |||
| 10794 | int nds_enc = nds->is_valid() ? nds->encoding() : 0; | |||
| 10795 | return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, attributes); | |||
| 10796 | } else { | |||
| 10797 | assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding")do { if (!((nds == dst) || (nds == src) || (nds == xnoreg))) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 10797, "assert(" "(nds == dst) || (nds == src) || (nds == xnoreg)" ") failed", "wrong sse encoding"); ::breakpoint(); } } while (0); | |||
| 10798 | return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, attributes->is_rex_vex_w()); | |||
| 10799 | } | |||
| 10800 | } | |||
| 10801 | ||||
| 10802 | void Assembler::vmaxss(XMMRegister dst, XMMRegister nds, XMMRegister src) { | |||
| 10803 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 10803, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 10804 | InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 10805 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); | |||
| 10806 | emit_int16(0x5F, (0xC0 | encode)); | |||
| 10807 | } | |||
| 10808 | ||||
| 10809 | void Assembler::vmaxsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { | |||
| 10810 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 10810, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 10811 | InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 10812 | attributes.set_rex_vex_w_reverted(); | |||
| 10813 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); | |||
| 10814 | emit_int16(0x5F, (0xC0 | encode)); | |||
| 10815 | } | |||
| 10816 | ||||
| 10817 | void Assembler::vminss(XMMRegister dst, XMMRegister nds, XMMRegister src) { | |||
| 10818 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 10818, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 10819 | InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 10820 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); | |||
| 10821 | emit_int16(0x5D, (0xC0 | encode)); | |||
| 10822 | } | |||
| 10823 | ||||
| 10824 | void Assembler::vminsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { | |||
| 10825 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 10825, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 10826 | InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 10827 | attributes.set_rex_vex_w_reverted(); | |||
| 10828 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); | |||
| 10829 | emit_int16(0x5D, (0xC0 | encode)); | |||
| 10830 | } | |||
| 10831 | ||||
| 10832 | void Assembler::vcmppd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len) { | |||
| 10833 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 10833, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 10834 | assert(vector_len <= AVX_256bit, "")do { if (!(vector_len <= AVX_256bit)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 10834, "assert(" "vector_len <= AVX_256bit" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 10835 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 10836 | int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 10837 | emit_int24((unsigned char)0xC2, (0xC0 | encode), (0xF & cop)); | |||
| 10838 | } | |||
| 10839 | ||||
| 10840 | void Assembler::blendvpb(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) { | |||
| 10841 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 10841, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 10842 | assert(vector_len <= AVX_256bit, "")do { if (!(vector_len <= AVX_256bit)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 10842, "assert(" "vector_len <= AVX_256bit" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 10843 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 10844 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 10845 | int src2_enc = src2->encoding(); | |||
| 10846 | emit_int24(0x4C, (0xC0 | encode), (0xF0 & src2_enc << 4)); | |||
| 10847 | } | |||
| 10848 | ||||
| 10849 | void Assembler::vblendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) { | |||
| 10850 | assert(UseAVX > 0 && (vector_len == AVX_128bit || vector_len == AVX_256bit), "")do { if (!(UseAVX > 0 && (vector_len == AVX_128bit || vector_len == AVX_256bit))) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 10850, "assert(" "UseAVX > 0 && (vector_len == AVX_128bit || vector_len == AVX_256bit)" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 10851 | assert(vector_len <= AVX_256bit, "")do { if (!(vector_len <= AVX_256bit)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 10851, "assert(" "vector_len <= AVX_256bit" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 10852 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 10853 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 10854 | int src2_enc = src2->encoding(); | |||
| 10855 | emit_int24(0x4B, (0xC0 | encode), (0xF0 & src2_enc << 4)); | |||
| 10856 | } | |||
| 10857 | ||||
| 10858 | void Assembler::vpblendd(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) { | |||
| 10859 | assert(VM_Version::supports_avx2(), "")do { if (!(VM_Version::supports_avx2())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 10859, "assert(" "VM_Version::supports_avx2()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 10860 | assert(vector_len <= AVX_256bit, "")do { if (!(vector_len <= AVX_256bit)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 10860, "assert(" "vector_len <= AVX_256bit" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 10861 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 10862 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 10863 | emit_int24(0x02, (0xC0 | encode), (unsigned char)imm8); | |||
| 10864 | } | |||
| 10865 | ||||
| 10866 | void Assembler::vcmpps(XMMRegister dst, XMMRegister nds, XMMRegister src, int comparison, int vector_len) { | |||
| 10867 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 10867, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 10868 | assert(vector_len <= AVX_256bit, "")do { if (!(vector_len <= AVX_256bit)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 10868, "assert(" "vector_len <= AVX_256bit" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 10869 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 10870 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 10871 | emit_int24((unsigned char)0xC2, (0xC0 | encode), (unsigned char)comparison); | |||
| 10872 | } | |||
| 10873 | ||||
| 10874 | void Assembler::evcmpps(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, | |||
| 10875 | ComparisonPredicateFP comparison, int vector_len) { | |||
| 10876 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 10876, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 10877 | // Encoding: EVEX.NDS.XXX.0F.W0 C2 /r ib | |||
| 10878 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 10879 | attributes.set_is_evex_instruction(); | |||
| 10880 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 10881 | attributes.reset_is_clear_context(); | |||
| 10882 | int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); | |||
| 10883 | emit_int24((unsigned char)0xC2, (0xC0 | encode), comparison); | |||
| 10884 | } | |||
| 10885 | ||||
| 10886 | void Assembler::evcmppd(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, | |||
| 10887 | ComparisonPredicateFP comparison, int vector_len) { | |||
| 10888 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 10888, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 10889 | // Encoding: EVEX.NDS.XXX.66.0F.W1 C2 /r ib | |||
| 10890 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 10891 | attributes.set_is_evex_instruction(); | |||
| 10892 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 10893 | attributes.reset_is_clear_context(); | |||
| 10894 | int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 10895 | emit_int24((unsigned char)0xC2, (0xC0 | encode), comparison); | |||
| 10896 | } | |||
| 10897 | ||||
| 10898 | void Assembler::blendvps(XMMRegister dst, XMMRegister src) { | |||
| 10899 | assert(VM_Version::supports_sse4_1(), "")do { if (!(VM_Version::supports_sse4_1())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 10899, "assert(" "VM_Version::supports_sse4_1()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 10900 | assert(UseAVX <= 0, "sse encoding is inconsistent with avx encoding")do { if (!(UseAVX <= 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 10900, "assert(" "UseAVX <= 0" ") failed", "sse encoding is inconsistent with avx encoding" ); ::breakpoint(); } } while (0); | |||
| 10901 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 10902 | int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 10903 | emit_int16(0x14, (0xC0 | encode)); | |||
| 10904 | } | |||
| 10905 | ||||
| 10906 | void Assembler::blendvpd(XMMRegister dst, XMMRegister src) { | |||
| 10907 | assert(VM_Version::supports_sse4_1(), "")do { if (!(VM_Version::supports_sse4_1())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 10907, "assert(" "VM_Version::supports_sse4_1()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 10908 | assert(UseAVX <= 0, "sse encoding is inconsistent with avx encoding")do { if (!(UseAVX <= 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 10908, "assert(" "UseAVX <= 0" ") failed", "sse encoding is inconsistent with avx encoding" ); ::breakpoint(); } } while (0); | |||
| 10909 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 10910 | int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 10911 | emit_int16(0x15, (0xC0 | encode)); | |||
| 10912 | } | |||
| 10913 | ||||
| 10914 | void Assembler::pblendvb(XMMRegister dst, XMMRegister src) { | |||
| 10915 | assert(VM_Version::supports_sse4_1(), "")do { if (!(VM_Version::supports_sse4_1())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 10915, "assert(" "VM_Version::supports_sse4_1()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 10916 | assert(UseAVX <= 0, "sse encoding is inconsistent with avx encoding")do { if (!(UseAVX <= 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 10916, "assert(" "UseAVX <= 0" ") failed", "sse encoding is inconsistent with avx encoding" ); ::breakpoint(); } } while (0); | |||
| 10917 | InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 10918 | int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 10919 | emit_int16(0x10, (0xC0 | encode)); | |||
| 10920 | } | |||
| 10921 | ||||
| 10922 | void Assembler::vblendvps(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) { | |||
| 10923 | assert(UseAVX > 0 && (vector_len == AVX_128bit || vector_len == AVX_256bit), "")do { if (!(UseAVX > 0 && (vector_len == AVX_128bit || vector_len == AVX_256bit))) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 10923, "assert(" "UseAVX > 0 && (vector_len == AVX_128bit || vector_len == AVX_256bit)" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 10924 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 10925 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 10926 | int src2_enc = src2->encoding(); | |||
| 10927 | emit_int24(0x4A, (0xC0 | encode), (0xF0 & src2_enc << 4)); | |||
| 10928 | } | |||
| 10929 | ||||
| 10930 | void Assembler::vblendps(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) { | |||
| 10931 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 10932 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 10933 | emit_int24(0x0C, (0xC0 | encode), imm8); | |||
| 10934 | } | |||
| 10935 | ||||
| 10936 | void Assembler::vpcmpgtb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 10937 | assert(vector_len == AVX_128bit ? VM_Version::supports_avx() : VM_Version::supports_avx2(), "")do { if (!(vector_len == AVX_128bit ? VM_Version::supports_avx () : VM_Version::supports_avx2())) { (*g_assert_poison) = 'X' ;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 10937, "assert(" "vector_len == AVX_128bit ? VM_Version::supports_avx() : VM_Version::supports_avx2()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 10938 | assert(vector_len <= AVX_256bit, "evex encoding is different - has k register as dest")do { if (!(vector_len <= AVX_256bit)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 10938, "assert(" "vector_len <= AVX_256bit" ") failed", "evex encoding is different - has k register as dest" ); ::breakpoint(); } } while (0); | |||
| 10939 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 10940 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 10941 | emit_int16(0x64, (0xC0 | encode)); | |||
| 10942 | } | |||
| 10943 | ||||
| 10944 | void Assembler::vpcmpgtw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 10945 | assert(vector_len == AVX_128bit ? VM_Version::supports_avx() : VM_Version::supports_avx2(), "")do { if (!(vector_len == AVX_128bit ? VM_Version::supports_avx () : VM_Version::supports_avx2())) { (*g_assert_poison) = 'X' ;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 10945, "assert(" "vector_len == AVX_128bit ? VM_Version::supports_avx() : VM_Version::supports_avx2()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 10946 | assert(vector_len <= AVX_256bit, "evex encoding is different - has k register as dest")do { if (!(vector_len <= AVX_256bit)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 10946, "assert(" "vector_len <= AVX_256bit" ") failed", "evex encoding is different - has k register as dest" ); ::breakpoint(); } } while (0); | |||
| 10947 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 10948 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 10949 | emit_int16(0x65, (0xC0 | encode)); | |||
| 10950 | } | |||
| 10951 | ||||
| 10952 | void Assembler::vpcmpgtd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 10953 | assert(vector_len == AVX_128bit ? VM_Version::supports_avx() : VM_Version::supports_avx2(), "")do { if (!(vector_len == AVX_128bit ? VM_Version::supports_avx () : VM_Version::supports_avx2())) { (*g_assert_poison) = 'X' ;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 10953, "assert(" "vector_len == AVX_128bit ? VM_Version::supports_avx() : VM_Version::supports_avx2()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 10954 | assert(vector_len <= AVX_256bit, "evex encoding is different - has k register as dest")do { if (!(vector_len <= AVX_256bit)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 10954, "assert(" "vector_len <= AVX_256bit" ") failed", "evex encoding is different - has k register as dest" ); ::breakpoint(); } } while (0); | |||
| 10955 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 10956 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 10957 | emit_int16(0x66, (0xC0 | encode)); | |||
| 10958 | } | |||
| 10959 | ||||
| 10960 | void Assembler::vpcmpgtq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { | |||
| 10961 | assert(vector_len == AVX_128bit ? VM_Version::supports_avx() : VM_Version::supports_avx2(), "")do { if (!(vector_len == AVX_128bit ? VM_Version::supports_avx () : VM_Version::supports_avx2())) { (*g_assert_poison) = 'X' ;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 10961, "assert(" "vector_len == AVX_128bit ? VM_Version::supports_avx() : VM_Version::supports_avx2()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 10962 | assert(vector_len <= AVX_256bit, "evex encoding is different - has k register as dest")do { if (!(vector_len <= AVX_256bit)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 10962, "assert(" "vector_len <= AVX_256bit" ") failed", "evex encoding is different - has k register as dest" ); ::breakpoint(); } } while (0); | |||
| 10963 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 10964 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 10965 | emit_int16(0x37, (0xC0 | encode)); | |||
| 10966 | } | |||
| 10967 | ||||
| 10968 | void Assembler::evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, | |||
| 10969 | int comparison, bool is_signed, int vector_len) { | |||
| 10970 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 10970, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 10971 | assert(comparison >= Assembler::eq && comparison <= Assembler::_true, "")do { if (!(comparison >= Assembler::eq && comparison <= Assembler::_true)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 10971, "assert(" "comparison >= Assembler::eq && comparison <= Assembler::_true" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 10972 | // Encoding: EVEX.NDS.XXX.66.0F3A.W0 1F /r ib | |||
| 10973 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 10974 | attributes.set_is_evex_instruction(); | |||
| 10975 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 10976 | attributes.reset_is_clear_context(); | |||
| 10977 | int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 10978 | int opcode = is_signed ? 0x1F : 0x1E; | |||
| 10979 | emit_int24(opcode, (0xC0 | encode), comparison); | |||
| 10980 | } | |||
| 10981 | ||||
| 10982 | void Assembler::evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, Address src, | |||
| 10983 | int comparison, bool is_signed, int vector_len) { | |||
| 10984 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 10984, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 10985 | assert(comparison >= Assembler::eq && comparison <= Assembler::_true, "")do { if (!(comparison >= Assembler::eq && comparison <= Assembler::_true)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 10985, "assert(" "comparison >= Assembler::eq && comparison <= Assembler::_true" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 10986 | // Encoding: EVEX.NDS.XXX.66.0F3A.W0 1F /r ib | |||
| 10987 | InstructionMark im(this); | |||
| 10988 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 10989 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_NObit); | |||
| 10990 | attributes.set_is_evex_instruction(); | |||
| 10991 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 10992 | attributes.reset_is_clear_context(); | |||
| 10993 | int dst_enc = kdst->encoding(); | |||
| 10994 | vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 10995 | int opcode = is_signed ? 0x1F : 0x1E; | |||
| 10996 | emit_int8((unsigned char)opcode); | |||
| 10997 | emit_operand(as_Register(dst_enc), src); | |||
| 10998 | emit_int8((unsigned char)comparison); | |||
| 10999 | } | |||
| 11000 | ||||
| 11001 | void Assembler::evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, | |||
| 11002 | int comparison, bool is_signed, int vector_len) { | |||
| 11003 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11003, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 11004 | assert(comparison >= Assembler::eq && comparison <= Assembler::_true, "")do { if (!(comparison >= Assembler::eq && comparison <= Assembler::_true)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11004, "assert(" "comparison >= Assembler::eq && comparison <= Assembler::_true" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 11005 | // Encoding: EVEX.NDS.XXX.66.0F3A.W1 1F /r ib | |||
| 11006 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 11007 | attributes.set_is_evex_instruction(); | |||
| 11008 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 11009 | attributes.reset_is_clear_context(); | |||
| 11010 | int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 11011 | int opcode = is_signed ? 0x1F : 0x1E; | |||
| 11012 | emit_int24(opcode, (0xC0 | encode), comparison); | |||
| 11013 | } | |||
| 11014 | ||||
| 11015 | void Assembler::evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, Address src, | |||
| 11016 | int comparison, bool is_signed, int vector_len) { | |||
| 11017 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11017, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 11018 | assert(comparison >= Assembler::eq && comparison <= Assembler::_true, "")do { if (!(comparison >= Assembler::eq && comparison <= Assembler::_true)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11018, "assert(" "comparison >= Assembler::eq && comparison <= Assembler::_true" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 11019 | // Encoding: EVEX.NDS.XXX.66.0F3A.W1 1F /r ib | |||
| 11020 | InstructionMark im(this); | |||
| 11021 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 11022 | attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_NObit); | |||
| 11023 | attributes.set_is_evex_instruction(); | |||
| 11024 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 11025 | attributes.reset_is_clear_context(); | |||
| 11026 | int dst_enc = kdst->encoding(); | |||
| 11027 | vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 11028 | int opcode = is_signed ? 0x1F : 0x1E; | |||
| 11029 | emit_int8((unsigned char)opcode); | |||
| 11030 | emit_operand(as_Register(dst_enc), src); | |||
| 11031 | emit_int8((unsigned char)comparison); | |||
| 11032 | } | |||
| 11033 | ||||
| 11034 | void Assembler::evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, | |||
| 11035 | int comparison, bool is_signed, int vector_len) { | |||
| 11036 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11036, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 11037 | assert(VM_Version::supports_avx512bw(), "")do { if (!(VM_Version::supports_avx512bw())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11037, "assert(" "VM_Version::supports_avx512bw()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 11038 | assert(comparison >= Assembler::eq && comparison <= Assembler::_true, "")do { if (!(comparison >= Assembler::eq && comparison <= Assembler::_true)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11038, "assert(" "comparison >= Assembler::eq && comparison <= Assembler::_true" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 11039 | // Encoding: EVEX.NDS.XXX.66.0F3A.W0 3F /r ib | |||
| 11040 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 11041 | attributes.set_is_evex_instruction(); | |||
| 11042 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 11043 | attributes.reset_is_clear_context(); | |||
| 11044 | int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 11045 | int opcode = is_signed ? 0x3F : 0x3E; | |||
| 11046 | emit_int24(opcode, (0xC0 | encode), comparison); | |||
| 11047 | } | |||
| 11048 | ||||
| 11049 | void Assembler::evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, | |||
| 11050 | int comparison, bool is_signed, int vector_len) { | |||
| 11051 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11051, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 11052 | assert(VM_Version::supports_avx512bw(), "")do { if (!(VM_Version::supports_avx512bw())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11052, "assert(" "VM_Version::supports_avx512bw()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 11053 | assert(comparison >= Assembler::eq && comparison <= Assembler::_true, "")do { if (!(comparison >= Assembler::eq && comparison <= Assembler::_true)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11053, "assert(" "comparison >= Assembler::eq && comparison <= Assembler::_true" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 11054 | // Encoding: EVEX.NDS.XXX.66.0F3A.W0 3F /r ib | |||
| 11055 | InstructionMark im(this); | |||
| 11056 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 11057 | attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); | |||
| 11058 | attributes.set_is_evex_instruction(); | |||
| 11059 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 11060 | attributes.reset_is_clear_context(); | |||
| 11061 | int dst_enc = kdst->encoding(); | |||
| 11062 | vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 11063 | int opcode = is_signed ? 0x3F : 0x3E; | |||
| 11064 | emit_int8((unsigned char)opcode); | |||
| 11065 | emit_operand(as_Register(dst_enc), src); | |||
| 11066 | emit_int8((unsigned char)comparison); | |||
| 11067 | } | |||
| 11068 | ||||
| 11069 | void Assembler::evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, | |||
| 11070 | int comparison, bool is_signed, int vector_len) { | |||
| 11071 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11071, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 11072 | assert(VM_Version::supports_avx512bw(), "")do { if (!(VM_Version::supports_avx512bw())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11072, "assert(" "VM_Version::supports_avx512bw()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 11073 | assert(comparison >= Assembler::eq && comparison <= Assembler::_true, "")do { if (!(comparison >= Assembler::eq && comparison <= Assembler::_true)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11073, "assert(" "comparison >= Assembler::eq && comparison <= Assembler::_true" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 11074 | // Encoding: EVEX.NDS.XXX.66.0F3A.W1 3F /r ib | |||
| 11075 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 11076 | attributes.set_is_evex_instruction(); | |||
| 11077 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 11078 | attributes.reset_is_clear_context(); | |||
| 11079 | int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 11080 | int opcode = is_signed ? 0x3F : 0x3E; | |||
| 11081 | emit_int24(opcode, (0xC0 | encode), comparison); | |||
| 11082 | } | |||
| 11083 | ||||
| 11084 | void Assembler::evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, Address src, | |||
| 11085 | int comparison, bool is_signed, int vector_len) { | |||
| 11086 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11086, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 11087 | assert(VM_Version::supports_avx512bw(), "")do { if (!(VM_Version::supports_avx512bw())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11087, "assert(" "VM_Version::supports_avx512bw()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 11088 | assert(comparison >= Assembler::eq && comparison <= Assembler::_true, "")do { if (!(comparison >= Assembler::eq && comparison <= Assembler::_true)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11088, "assert(" "comparison >= Assembler::eq && comparison <= Assembler::_true" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 11089 | // Encoding: EVEX.NDS.XXX.66.0F3A.W1 3F /r ib | |||
| 11090 | InstructionMark im(this); | |||
| 11091 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 11092 | attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); | |||
| 11093 | attributes.set_is_evex_instruction(); | |||
| 11094 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 11095 | attributes.reset_is_clear_context(); | |||
| 11096 | int dst_enc = kdst->encoding(); | |||
| 11097 | vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 11098 | int opcode = is_signed ? 0x3F : 0x3E; | |||
| 11099 | emit_int8((unsigned char)opcode); | |||
| 11100 | emit_operand(as_Register(dst_enc), src); | |||
| 11101 | emit_int8((unsigned char)comparison); | |||
| 11102 | } | |||
| 11103 | ||||
| 11104 | // Register is a class, but it would be assigned numerical value. | |||
| 11105 | // "0" is assigned for xmm0. Thus we need to ignore -Wnonnull. | |||
| 11106 | PRAGMA_DIAG_PUSHGCC diagnostic push | |||
| 11107 | PRAGMA_NONNULL_IGNOREDGCC diagnostic ignored "-Wnonnull" | |||
| 11108 | void Assembler::evprord(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) { | |||
| 11109 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11109, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 11110 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 11111 | attributes.set_is_evex_instruction(); | |||
| 11112 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 11113 | if (merge) { | |||
| 11114 | attributes.reset_is_clear_context(); | |||
| 11115 | } | |||
| 11116 | int encode = vex_prefix_and_encode(xmm0->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 11117 | emit_int24(0x72, (0xC0 | encode), shift & 0xFF); | |||
| 11118 | } | |||
| 11119 | ||||
| 11120 | void Assembler::evprorq(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) { | |||
| 11121 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11121, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 11122 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 11123 | attributes.set_is_evex_instruction(); | |||
| 11124 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 11125 | if (merge) { | |||
| 11126 | attributes.reset_is_clear_context(); | |||
| 11127 | } | |||
| 11128 | int encode = vex_prefix_and_encode(xmm0->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 11129 | emit_int24(0x72, (0xC0 | encode), shift & 0xFF); | |||
| 11130 | } | |||
| 11131 | PRAGMA_DIAG_POPGCC diagnostic pop | |||
| 11132 | ||||
| 11133 | void Assembler::evprorvd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 11134 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11134, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 11135 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 11136 | attributes.set_is_evex_instruction(); | |||
| 11137 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 11138 | if (merge) { | |||
| 11139 | attributes.reset_is_clear_context(); | |||
| 11140 | } | |||
| 11141 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 11142 | emit_int16(0x14, (0xC0 | encode)); | |||
| 11143 | } | |||
| 11144 | ||||
| 11145 | void Assembler::evprorvq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 11146 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11146, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 11147 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 11148 | attributes.set_is_evex_instruction(); | |||
| 11149 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 11150 | if (merge) { | |||
| 11151 | attributes.reset_is_clear_context(); | |||
| 11152 | } | |||
| 11153 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 11154 | emit_int16(0x14, (0xC0 | encode)); | |||
| 11155 | } | |||
| 11156 | ||||
| 11157 | void Assembler::evprold(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) { | |||
| 11158 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11158, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 11159 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 11160 | attributes.set_is_evex_instruction(); | |||
| 11161 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 11162 | if (merge) { | |||
| 11163 | attributes.reset_is_clear_context(); | |||
| 11164 | } | |||
| 11165 | int encode = vex_prefix_and_encode(xmm1->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 11166 | emit_int24(0x72, (0xC0 | encode), shift & 0xFF); | |||
| 11167 | } | |||
| 11168 | ||||
| 11169 | void Assembler::evprolq(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) { | |||
| 11170 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11170, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 11171 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 11172 | attributes.set_is_evex_instruction(); | |||
| 11173 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 11174 | if (merge) { | |||
| 11175 | attributes.reset_is_clear_context(); | |||
| 11176 | } | |||
| 11177 | int encode = vex_prefix_and_encode(xmm1->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 11178 | emit_int24(0x72, (0xC0 | encode), shift & 0xFF); | |||
| 11179 | } | |||
| 11180 | ||||
| 11181 | void Assembler::evprolvd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 11182 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11182, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 11183 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 11184 | attributes.set_is_evex_instruction(); | |||
| 11185 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 11186 | if (merge) { | |||
| 11187 | attributes.reset_is_clear_context(); | |||
| 11188 | } | |||
| 11189 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 11190 | emit_int16(0x15, (0xC0 | encode)); | |||
| 11191 | } | |||
| 11192 | ||||
| 11193 | void Assembler::evprolvq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 11194 | assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "")do { if (!(vector_len == AVX_512bit || VM_Version::supports_avx512vl ())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11194, "assert(" "vector_len == AVX_512bit || VM_Version::supports_avx512vl()" ") failed", ""); ::breakpoint(); } } while (0); | |||
| 11195 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 11196 | attributes.set_is_evex_instruction(); | |||
| 11197 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 11198 | if (merge) { | |||
| 11199 | attributes.reset_is_clear_context(); | |||
| 11200 | } | |||
| 11201 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 11202 | emit_int16(0x15, (0xC0 | encode)); | |||
| 11203 | } | |||
| 11204 | ||||
| 11205 | void Assembler::vpblendvb(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len) { | |||
| 11206 | assert(VM_Version::supports_avx(), "")do { if (!(VM_Version::supports_avx())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11206, "assert(" "VM_Version::supports_avx()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 11207 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 11208 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); | |||
| 11209 | int mask_enc = mask->encoding(); | |||
| 11210 | emit_int24(0x4C, (0xC0 | encode), 0xF0 & mask_enc << 4); | |||
| 11211 | } | |||
| 11212 | ||||
| 11213 | void Assembler::evblendmpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 11214 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11214, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 11215 | // Encoding: EVEX.NDS.XXX.66.0F38.W1 65 /r | |||
| 11216 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 11217 | attributes.set_is_evex_instruction(); | |||
| 11218 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 11219 | if (merge) { | |||
| 11220 | attributes.reset_is_clear_context(); | |||
| 11221 | } | |||
| 11222 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 11223 | emit_int16(0x65, (0xC0 | encode)); | |||
| 11224 | } | |||
| 11225 | ||||
| 11226 | void Assembler::evblendmps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 11227 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11227, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 11228 | // Encoding: EVEX.NDS.XXX.66.0F38.W0 65 /r | |||
| 11229 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 11230 | attributes.set_is_evex_instruction(); | |||
| 11231 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 11232 | if (merge) { | |||
| 11233 | attributes.reset_is_clear_context(); | |||
| 11234 | } | |||
| 11235 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 11236 | emit_int16(0x65, (0xC0 | encode)); | |||
| 11237 | } | |||
| 11238 | ||||
| 11239 | void Assembler::evpblendmb (XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 11240 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11240, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 11241 | assert(VM_Version::supports_avx512bw(), "")do { if (!(VM_Version::supports_avx512bw())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11241, "assert(" "VM_Version::supports_avx512bw()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 11242 | // Encoding: EVEX.NDS.512.66.0F38.W0 66 /r | |||
| 11243 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 11244 | attributes.set_is_evex_instruction(); | |||
| 11245 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 11246 | if (merge) { | |||
| 11247 | attributes.reset_is_clear_context(); | |||
| 11248 | } | |||
| 11249 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 11250 | emit_int16(0x66, (0xC0 | encode)); | |||
| 11251 | } | |||
| 11252 | ||||
| 11253 | void Assembler::evpblendmw (XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 11254 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11254, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 11255 | assert(VM_Version::supports_avx512bw(), "")do { if (!(VM_Version::supports_avx512bw())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11255, "assert(" "VM_Version::supports_avx512bw()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 11256 | // Encoding: EVEX.NDS.512.66.0F38.W1 66 /r | |||
| 11257 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 11258 | attributes.set_is_evex_instruction(); | |||
| 11259 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 11260 | if (merge) { | |||
| 11261 | attributes.reset_is_clear_context(); | |||
| 11262 | } | |||
| 11263 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 11264 | emit_int16(0x66, (0xC0 | encode)); | |||
| 11265 | } | |||
| 11266 | ||||
| 11267 | void Assembler::evpblendmd (XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 11268 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11268, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 11269 | //Encoding: EVEX.NDS.512.66.0F38.W0 64 /r | |||
| 11270 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 11271 | attributes.set_is_evex_instruction(); | |||
| 11272 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 11273 | if (merge) { | |||
| 11274 | attributes.reset_is_clear_context(); | |||
| 11275 | } | |||
| 11276 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 11277 | emit_int16(0x64, (0xC0 | encode)); | |||
| 11278 | } | |||
| 11279 | ||||
| 11280 | void Assembler::evpblendmq (XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { | |||
| 11281 | assert(VM_Version::supports_evex(), "")do { if (!(VM_Version::supports_evex())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11281, "assert(" "VM_Version::supports_evex()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 11282 | //Encoding: EVEX.NDS.512.66.0F38.W1 64 /r | |||
| 11283 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); | |||
| 11284 | attributes.set_is_evex_instruction(); | |||
| 11285 | attributes.set_embedded_opmask_register_specifier(mask); | |||
| 11286 | if (merge) { | |||
| 11287 | attributes.reset_is_clear_context(); | |||
| 11288 | } | |||
| 11289 | int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 11290 | emit_int16(0x64, (0xC0 | encode)); | |||
| 11291 | } | |||
| 11292 | ||||
| 11293 | void Assembler::bzhiq(Register dst, Register src1, Register src2) { | |||
| 11294 | assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported")do { if (!(VM_Version::supports_bmi2())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11294, "assert(" "VM_Version::supports_bmi2()" ") failed", "bit manipulation instructions not supported" ); ::breakpoint(); } } while (0); | |||
| 11295 | InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 11296 | int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); | |||
| 11297 | emit_int16((unsigned char)0xF5, (0xC0 | encode)); | |||
| 11298 | } | |||
| 11299 | ||||
| 11300 | void Assembler::pext(Register dst, Register src1, Register src2) { | |||
| 11301 | assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported")do { if (!(VM_Version::supports_bmi2())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11301, "assert(" "VM_Version::supports_bmi2()" ") failed", "bit manipulation instructions not supported" ); ::breakpoint(); } } while (0); | |||
| 11302 | InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 11303 | int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes); | |||
| 11304 | emit_int16((unsigned char)0xF5, (0xC0 | encode)); | |||
| 11305 | } | |||
| 11306 | ||||
| 11307 | void Assembler::pdep(Register dst, Register src1, Register src2) { | |||
| 11308 | assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported")do { if (!(VM_Version::supports_bmi2())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11308, "assert(" "VM_Version::supports_bmi2()" ") failed", "bit manipulation instructions not supported" ); ::breakpoint(); } } while (0); | |||
| 11309 | InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 11310 | int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes); | |||
| 11311 | emit_int16((unsigned char)0xF5, (0xC0 | encode)); | |||
| 11312 | } | |||
| 11313 | ||||
| 11314 | void Assembler::shlxl(Register dst, Register src1, Register src2) { | |||
| 11315 | assert(VM_Version::supports_bmi2(), "")do { if (!(VM_Version::supports_bmi2())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11315, "assert(" "VM_Version::supports_bmi2()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 11316 | InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 11317 | int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 11318 | emit_int16((unsigned char)0xF7, (0xC0 | encode)); | |||
| 11319 | } | |||
| 11320 | ||||
| 11321 | void Assembler::shlxq(Register dst, Register src1, Register src2) { | |||
| 11322 | assert(VM_Version::supports_bmi2(), "")do { if (!(VM_Version::supports_bmi2())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11322, "assert(" "VM_Version::supports_bmi2()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 11323 | InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 11324 | int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); | |||
| 11325 | emit_int16((unsigned char)0xF7, (0xC0 | encode)); | |||
| 11326 | } | |||
| 11327 | ||||
| 11328 | void Assembler::shrxl(Register dst, Register src1, Register src2) { | |||
| 11329 | assert(VM_Version::supports_bmi2(), "")do { if (!(VM_Version::supports_bmi2())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11329, "assert(" "VM_Version::supports_bmi2()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 11330 | InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 11331 | int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes); | |||
| 11332 | emit_int16((unsigned char)0xF7, (0xC0 | encode)); | |||
| 11333 | } | |||
| 11334 | ||||
| 11335 | void Assembler::shrxq(Register dst, Register src1, Register src2) { | |||
| 11336 | assert(VM_Version::supports_bmi2(), "")do { if (!(VM_Version::supports_bmi2())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11336, "assert(" "VM_Version::supports_bmi2()" ") failed", "" ); ::breakpoint(); } } while (0); | |||
| 11337 | InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 11338 | int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes); | |||
| 11339 | emit_int16((unsigned char)0xF7, (0xC0 | encode)); | |||
| 11340 | } | |||
| 11341 | ||||
| 11342 | void Assembler::evpmovq2m(KRegister dst, XMMRegister src, int vector_len) { | |||
| 11343 | assert(VM_Version::supports_avx512vldq(), "")do { if (!(VM_Version::supports_avx512vldq())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11343, "assert(" "VM_Version::supports_avx512vldq()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 11344 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 11345 | attributes.set_is_evex_instruction(); | |||
| 11346 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes); | |||
| 11347 | emit_int16(0x39, (0xC0 | encode)); | |||
| 11348 | } | |||
| 11349 | ||||
| 11350 | void Assembler::evpmovd2m(KRegister dst, XMMRegister src, int vector_len) { | |||
| 11351 | assert(VM_Version::supports_avx512vldq(), "")do { if (!(VM_Version::supports_avx512vldq())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11351, "assert(" "VM_Version::supports_avx512vldq()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 11352 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 11353 | attributes.set_is_evex_instruction(); | |||
| 11354 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes); | |||
| 11355 | emit_int16(0x39, (0xC0 | encode)); | |||
| 11356 | } | |||
| 11357 | ||||
| 11358 | void Assembler::evpmovw2m(KRegister dst, XMMRegister src, int vector_len) { | |||
| 11359 | assert(VM_Version::supports_avx512vlbw(), "")do { if (!(VM_Version::supports_avx512vlbw())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11359, "assert(" "VM_Version::supports_avx512vlbw()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 11360 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 11361 | attributes.set_is_evex_instruction(); | |||
| 11362 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes); | |||
| 11363 | emit_int16(0x29, (0xC0 | encode)); | |||
| 11364 | } | |||
| 11365 | ||||
| 11366 | void Assembler::evpmovb2m(KRegister dst, XMMRegister src, int vector_len) { | |||
| 11367 | assert(VM_Version::supports_avx512vlbw(), "")do { if (!(VM_Version::supports_avx512vlbw())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11367, "assert(" "VM_Version::supports_avx512vlbw()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 11368 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 11369 | attributes.set_is_evex_instruction(); | |||
| 11370 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes); | |||
| 11371 | emit_int16(0x29, (0xC0 | encode)); | |||
| 11372 | } | |||
| 11373 | ||||
| 11374 | void Assembler::evpmovm2q(XMMRegister dst, KRegister src, int vector_len) { | |||
| 11375 | assert(VM_Version::supports_avx512vldq(), "")do { if (!(VM_Version::supports_avx512vldq())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11375, "assert(" "VM_Version::supports_avx512vldq()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 11376 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 11377 | attributes.set_is_evex_instruction(); | |||
| 11378 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes); | |||
| 11379 | emit_int16(0x38, (0xC0 | encode)); | |||
| 11380 | } | |||
| 11381 | ||||
| 11382 | void Assembler::evpmovm2d(XMMRegister dst, KRegister src, int vector_len) { | |||
| 11383 | assert(VM_Version::supports_avx512vldq(), "")do { if (!(VM_Version::supports_avx512vldq())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11383, "assert(" "VM_Version::supports_avx512vldq()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 11384 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 11385 | attributes.set_is_evex_instruction(); | |||
| 11386 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes); | |||
| 11387 | emit_int16(0x38, (0xC0 | encode)); | |||
| 11388 | } | |||
| 11389 | ||||
| 11390 | void Assembler::evpmovm2w(XMMRegister dst, KRegister src, int vector_len) { | |||
| 11391 | assert(VM_Version::supports_avx512vlbw(), "")do { if (!(VM_Version::supports_avx512vlbw())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11391, "assert(" "VM_Version::supports_avx512vlbw()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 11392 | InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 11393 | attributes.set_is_evex_instruction(); | |||
| 11394 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes); | |||
| 11395 | emit_int16(0x28, (0xC0 | encode)); | |||
| 11396 | } | |||
| 11397 | ||||
| 11398 | void Assembler::evpmovm2b(XMMRegister dst, KRegister src, int vector_len) { | |||
| 11399 | assert(VM_Version::supports_avx512vlbw(), "")do { if (!(VM_Version::supports_avx512vlbw())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11399, "assert(" "VM_Version::supports_avx512vlbw()" ") failed" , ""); ::breakpoint(); } } while (0); | |||
| 11400 | InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); | |||
| 11401 | attributes.set_is_evex_instruction(); | |||
| 11402 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes); | |||
| 11403 | emit_int16(0x28, (0xC0 | encode)); | |||
| 11404 | } | |||
| 11405 | #ifndef _LP641 | |||
| 11406 | ||||
| 11407 | void Assembler::incl(Register dst) { | |||
| 11408 | // Don't use it directly. Use MacroAssembler::incrementl() instead. | |||
| 11409 | emit_int8(0x40 | dst->encoding()); | |||
| 11410 | } | |||
| 11411 | ||||
| 11412 | void Assembler::lea(Register dst, Address src) { | |||
| 11413 | leal(dst, src); | |||
| 11414 | } | |||
| 11415 | ||||
| 11416 | void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) { | |||
| 11417 | InstructionMark im(this); | |||
| 11418 | emit_int8((unsigned char)0xC7); | |||
| 11419 | emit_operand(rax, dst); | |||
| 11420 | emit_data((int)imm32, rspec, 0); | |||
| 11421 | } | |||
| 11422 | ||||
| 11423 | void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) { | |||
| 11424 | InstructionMark im(this); | |||
| 11425 | int encode = prefix_and_encode(dst->encoding()); | |||
| 11426 | emit_int8((0xB8 | encode)); | |||
| 11427 | emit_data((int)imm32, rspec, 0); | |||
| 11428 | } | |||
| 11429 | ||||
| 11430 | void Assembler::popa() { // 32bit | |||
| 11431 | emit_int8(0x61); | |||
| 11432 | } | |||
| 11433 | ||||
| 11434 | void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) { | |||
| 11435 | InstructionMark im(this); | |||
| 11436 | emit_int8(0x68); | |||
| 11437 | emit_data(imm32, rspec, 0); | |||
| 11438 | } | |||
| 11439 | ||||
| 11440 | void Assembler::pusha() { // 32bit | |||
| 11441 | emit_int8(0x60); | |||
| 11442 | } | |||
| 11443 | ||||
| 11444 | void Assembler::set_byte_if_not_zero(Register dst) { | |||
| 11445 | emit_int24(0x0F, (unsigned char)0x95, (0xC0 | dst->encoding())); | |||
| 11446 | } | |||
| 11447 | ||||
| 11448 | #else // LP64 | |||
| 11449 | ||||
| 11450 | void Assembler::set_byte_if_not_zero(Register dst) { | |||
| 11451 | int enc = prefix_and_encode(dst->encoding(), true); | |||
| 11452 | emit_int24(0x0F, (unsigned char)0x95, (0xC0 | enc)); | |||
| 11453 | } | |||
| 11454 | ||||
| 11455 | // 64bit only pieces of the assembler | |||
| 11456 | // This should only be used by 64bit instructions that can use rip-relative | |||
| 11457 | // it cannot be used by instructions that want an immediate value. | |||
| 11458 | ||||
| 11459 | bool Assembler::reachable(AddressLiteral adr) { | |||
| 11460 | int64_t disp; | |||
| 11461 | relocInfo::relocType relocType = adr.reloc(); | |||
| 11462 | ||||
| 11463 | // None will force a 64bit literal to the code stream. Likely a placeholder | |||
| 11464 | // for something that will be patched later and we need to certain it will | |||
| 11465 | // always be reachable. | |||
| 11466 | if (relocType == relocInfo::none) { | |||
| 11467 | return false; | |||
| 11468 | } | |||
| 11469 | if (relocType == relocInfo::internal_word_type) { | |||
| 11470 | // This should be rip relative and easily reachable. | |||
| 11471 | return true; | |||
| 11472 | } | |||
| 11473 | if (relocType == relocInfo::virtual_call_type || | |||
| 11474 | relocType == relocInfo::opt_virtual_call_type || | |||
| 11475 | relocType == relocInfo::static_call_type || | |||
| 11476 | relocType == relocInfo::static_stub_type ) { | |||
| 11477 | // This should be rip relative within the code cache and easily | |||
| 11478 | // reachable until we get huge code caches. (At which point | |||
| 11479 | // ic code is going to have issues). | |||
| 11480 | return true; | |||
| 11481 | } | |||
| 11482 | if (relocType != relocInfo::external_word_type && | |||
| 11483 | relocType != relocInfo::poll_return_type && // these are really external_word but need special | |||
| 11484 | relocType != relocInfo::poll_type && // relocs to identify them | |||
| 11485 | relocType != relocInfo::runtime_call_type ) { | |||
| 11486 | return false; | |||
| 11487 | } | |||
| 11488 | ||||
| 11489 | // Stress the correction code | |||
| 11490 | if (ForceUnreachable) { | |||
| 11491 | // Must be runtimecall reloc, see if it is in the codecache | |||
| 11492 | // Flipping stuff in the codecache to be unreachable causes issues | |||
| 11493 | // with things like inline caches where the additional instructions | |||
| 11494 | // are not handled. | |||
| 11495 | if (CodeCache::find_blob(adr._target) == NULL__null) { | |||
| 11496 | return false; | |||
| 11497 | } | |||
| 11498 | } | |||
| 11499 | // For external_word_type/runtime_call_type if it is reachable from where we | |||
| 11500 | // are now (possibly a temp buffer) and where we might end up | |||
| 11501 | // anywhere in the codeCache then we are always reachable. | |||
| 11502 | // This would have to change if we ever save/restore shared code | |||
| 11503 | // to be more pessimistic. | |||
| 11504 | disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int)); | |||
| 11505 | if (!is_simm32(disp)) return false; | |||
| 11506 | disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int)); | |||
| 11507 | if (!is_simm32(disp)) return false; | |||
| 11508 | ||||
| 11509 | disp = (int64_t)adr._target - ((int64_t)pc() + sizeof(int)); | |||
| 11510 | ||||
| 11511 | // Because rip relative is a disp + address_of_next_instruction and we | |||
| 11512 | // don't know the value of address_of_next_instruction we apply a fudge factor | |||
| 11513 | // to make sure we will be ok no matter the size of the instruction we get placed into. | |||
| 11514 | // We don't have to fudge the checks above here because they are already worst case. | |||
| 11515 | ||||
| 11516 | // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal | |||
| 11517 | // + 4 because better safe than sorry. | |||
| 11518 | const int fudge = 12 + 4; | |||
| 11519 | if (disp < 0) { | |||
| 11520 | disp -= fudge; | |||
| 11521 | } else { | |||
| 11522 | disp += fudge; | |||
| 11523 | } | |||
| 11524 | return is_simm32(disp); | |||
| 11525 | } | |||
| 11526 | ||||
| 11527 | void Assembler::emit_data64(jlong data, | |||
| 11528 | relocInfo::relocType rtype, | |||
| 11529 | int format) { | |||
| 11530 | if (rtype == relocInfo::none) { | |||
| 11531 | emit_int64(data); | |||
| 11532 | } else { | |||
| 11533 | emit_data64(data, Relocation::spec_simple(rtype), format); | |||
| 11534 | } | |||
| 11535 | } | |||
| 11536 | ||||
| 11537 | void Assembler::emit_data64(jlong data, | |||
| 11538 | RelocationHolder const& rspec, | |||
| 11539 | int format) { | |||
| 11540 | assert(imm_operand == 0, "default format must be immediate in this file")do { if (!(imm_operand == 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11540, "assert(" "imm_operand == 0" ") failed", "default format must be immediate in this file" ); ::breakpoint(); } } while (0); | |||
| 11541 | assert(imm_operand == format, "must be immediate")do { if (!(imm_operand == format)) { (*g_assert_poison) = 'X' ;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11541, "assert(" "imm_operand == format" ") failed", "must be immediate" ); ::breakpoint(); } } while (0); | |||
| 11542 | assert(inst_mark() != NULL, "must be inside InstructionMark")do { if (!(inst_mark() != __null)) { (*g_assert_poison) = 'X' ;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11542, "assert(" "inst_mark() != __null" ") failed", "must be inside InstructionMark" ); ::breakpoint(); } } while (0); | |||
| 11543 | // Do not use AbstractAssembler::relocate, which is not intended for | |||
| 11544 | // embedded words. Instead, relocate to the enclosing instruction. | |||
| 11545 | code_section()->relocate(inst_mark(), rspec, format); | |||
| 11546 | #ifdef ASSERT1 | |||
| 11547 | check_relocation(rspec, format); | |||
| 11548 | #endif | |||
| 11549 | emit_int64(data); | |||
| 11550 | } | |||
| 11551 | ||||
| 11552 | void Assembler::prefix(Register reg) { | |||
| 11553 | if (reg->encoding() >= 8) { | |||
| 11554 | prefix(REX_B); | |||
| 11555 | } | |||
| 11556 | } | |||
| 11557 | ||||
| 11558 | void Assembler::prefix(Register dst, Register src, Prefix p) { | |||
| 11559 | if (src->encoding() >= 8) { | |||
| 11560 | p = (Prefix)(p | REX_B); | |||
| 11561 | } | |||
| 11562 | if (dst->encoding() >= 8) { | |||
| 11563 | p = (Prefix)(p | REX_R); | |||
| 11564 | } | |||
| 11565 | if (p != Prefix_EMPTY) { | |||
| 11566 | // do not generate an empty prefix | |||
| 11567 | prefix(p); | |||
| 11568 | } | |||
| 11569 | } | |||
| 11570 | ||||
| 11571 | void Assembler::prefix(Register dst, Address adr, Prefix p) { | |||
| 11572 | if (adr.base_needs_rex()) { | |||
| 11573 | if (adr.index_needs_rex()) { | |||
| 11574 | assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X")do { if (!(false)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11574, "assert(" "false" ") failed", "prefix(Register dst, Address adr, Prefix p) does not support handling of an X" ); ::breakpoint(); } } while (0); | |||
| 11575 | } else { | |||
| 11576 | prefix(REX_B); | |||
| 11577 | } | |||
| 11578 | } else { | |||
| 11579 | if (adr.index_needs_rex()) { | |||
| 11580 | assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X")do { if (!(false)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11580, "assert(" "false" ") failed", "prefix(Register dst, Address adr, Prefix p) does not support handling of an X" ); ::breakpoint(); } } while (0); | |||
| 11581 | } | |||
| 11582 | } | |||
| 11583 | if (dst->encoding() >= 8) { | |||
| 11584 | p = (Prefix)(p | REX_R); | |||
| 11585 | } | |||
| 11586 | if (p != Prefix_EMPTY) { | |||
| 11587 | // do not generate an empty prefix | |||
| 11588 | prefix(p); | |||
| 11589 | } | |||
| 11590 | } | |||
| 11591 | ||||
| 11592 | void Assembler::prefix(Address adr) { | |||
| 11593 | if (adr.base_needs_rex()) { | |||
| 11594 | if (adr.index_needs_rex()) { | |||
| 11595 | prefix(REX_XB); | |||
| 11596 | } else { | |||
| 11597 | prefix(REX_B); | |||
| 11598 | } | |||
| 11599 | } else { | |||
| 11600 | if (adr.index_needs_rex()) { | |||
| 11601 | prefix(REX_X); | |||
| 11602 | } | |||
| 11603 | } | |||
| 11604 | } | |||
| 11605 | ||||
| 11606 | void Assembler::prefix(Address adr, Register reg, bool byteinst) { | |||
| 11607 | if (reg->encoding() < 8) { | |||
| 11608 | if (adr.base_needs_rex()) { | |||
| 11609 | if (adr.index_needs_rex()) { | |||
| 11610 | prefix(REX_XB); | |||
| 11611 | } else { | |||
| 11612 | prefix(REX_B); | |||
| 11613 | } | |||
| 11614 | } else { | |||
| 11615 | if (adr.index_needs_rex()) { | |||
| 11616 | prefix(REX_X); | |||
| 11617 | } else if (byteinst && reg->encoding() >= 4) { | |||
| 11618 | prefix(REX); | |||
| 11619 | } | |||
| 11620 | } | |||
| 11621 | } else { | |||
| 11622 | if (adr.base_needs_rex()) { | |||
| 11623 | if (adr.index_needs_rex()) { | |||
| 11624 | prefix(REX_RXB); | |||
| 11625 | } else { | |||
| 11626 | prefix(REX_RB); | |||
| 11627 | } | |||
| 11628 | } else { | |||
| 11629 | if (adr.index_needs_rex()) { | |||
| 11630 | prefix(REX_RX); | |||
| 11631 | } else { | |||
| 11632 | prefix(REX_R); | |||
| 11633 | } | |||
| 11634 | } | |||
| 11635 | } | |||
| 11636 | } | |||
| 11637 | ||||
| 11638 | void Assembler::prefix(Address adr, XMMRegister reg) { | |||
| 11639 | if (reg->encoding() < 8) { | |||
| 11640 | if (adr.base_needs_rex()) { | |||
| 11641 | if (adr.index_needs_rex()) { | |||
| 11642 | prefix(REX_XB); | |||
| 11643 | } else { | |||
| 11644 | prefix(REX_B); | |||
| 11645 | } | |||
| 11646 | } else { | |||
| 11647 | if (adr.index_needs_rex()) { | |||
| 11648 | prefix(REX_X); | |||
| 11649 | } | |||
| 11650 | } | |||
| 11651 | } else { | |||
| 11652 | if (adr.base_needs_rex()) { | |||
| 11653 | if (adr.index_needs_rex()) { | |||
| 11654 | prefix(REX_RXB); | |||
| 11655 | } else { | |||
| 11656 | prefix(REX_RB); | |||
| 11657 | } | |||
| 11658 | } else { | |||
| 11659 | if (adr.index_needs_rex()) { | |||
| 11660 | prefix(REX_RX); | |||
| 11661 | } else { | |||
| 11662 | prefix(REX_R); | |||
| 11663 | } | |||
| 11664 | } | |||
| 11665 | } | |||
| 11666 | } | |||
| 11667 | ||||
| 11668 | int Assembler::prefix_and_encode(int reg_enc, bool byteinst) { | |||
| 11669 | if (reg_enc >= 8) { | |||
| 11670 | prefix(REX_B); | |||
| 11671 | reg_enc -= 8; | |||
| 11672 | } else if (byteinst && reg_enc >= 4) { | |||
| 11673 | prefix(REX); | |||
| 11674 | } | |||
| 11675 | return reg_enc; | |||
| 11676 | } | |||
| 11677 | ||||
| 11678 | int Assembler::prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte) { | |||
| 11679 | if (dst_enc < 8) { | |||
| 11680 | if (src_enc >= 8) { | |||
| 11681 | prefix(REX_B); | |||
| 11682 | src_enc -= 8; | |||
| 11683 | } else if ((src_is_byte && src_enc >= 4) || (dst_is_byte && dst_enc >= 4)) { | |||
| 11684 | prefix(REX); | |||
| 11685 | } | |||
| 11686 | } else { | |||
| 11687 | if (src_enc < 8) { | |||
| 11688 | prefix(REX_R); | |||
| 11689 | } else { | |||
| 11690 | prefix(REX_RB); | |||
| 11691 | src_enc -= 8; | |||
| 11692 | } | |||
| 11693 | dst_enc -= 8; | |||
| 11694 | } | |||
| 11695 | return dst_enc << 3 | src_enc; | |||
| 11696 | } | |||
| 11697 | ||||
| 11698 | int8_t Assembler::get_prefixq(Address adr) { | |||
| 11699 | int8_t prfx = get_prefixq(adr, rax); | |||
| 11700 | assert(REX_W <= prfx && prfx <= REX_WXB, "must be")do { if (!(REX_W <= prfx && prfx <= REX_WXB)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11700, "assert(" "REX_W <= prfx && prfx <= REX_WXB" ") failed", "must be"); ::breakpoint(); } } while (0); | |||
| 11701 | return prfx; | |||
| 11702 | } | |||
| 11703 | ||||
| 11704 | int8_t Assembler::get_prefixq(Address adr, Register src) { | |||
| 11705 | int8_t prfx = (int8_t)(REX_W + | |||
| 11706 | ((int)adr.base_needs_rex()) + | |||
| 11707 | ((int)adr.index_needs_rex() << 1) + | |||
| 11708 | ((int)(src->encoding() >= 8) << 2)); | |||
| ||||
| 11709 | #ifdef ASSERT1 | |||
| 11710 | if (src->encoding() < 8) { | |||
| 11711 | if (adr.base_needs_rex()) { | |||
| 11712 | if (adr.index_needs_rex()) { | |||
| 11713 | assert(prfx == REX_WXB, "must be")do { if (!(prfx == REX_WXB)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11713, "assert(" "prfx == REX_WXB" ") failed", "must be"); :: breakpoint(); } } while (0); | |||
| 11714 | } else { | |||
| 11715 | assert(prfx == REX_WB, "must be")do { if (!(prfx == REX_WB)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11715, "assert(" "prfx == REX_WB" ") failed", "must be"); :: breakpoint(); } } while (0); | |||
| 11716 | } | |||
| 11717 | } else { | |||
| 11718 | if (adr.index_needs_rex()) { | |||
| 11719 | assert(prfx == REX_WX, "must be")do { if (!(prfx == REX_WX)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11719, "assert(" "prfx == REX_WX" ") failed", "must be"); :: breakpoint(); } } while (0); | |||
| 11720 | } else { | |||
| 11721 | assert(prfx == REX_W, "must be")do { if (!(prfx == REX_W)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11721, "assert(" "prfx == REX_W" ") failed", "must be"); :: breakpoint(); } } while (0); | |||
| 11722 | } | |||
| 11723 | } | |||
| 11724 | } else { | |||
| 11725 | if (adr.base_needs_rex()) { | |||
| 11726 | if (adr.index_needs_rex()) { | |||
| 11727 | assert(prfx == REX_WRXB, "must be")do { if (!(prfx == REX_WRXB)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11727, "assert(" "prfx == REX_WRXB" ") failed", "must be"); ::breakpoint(); } } while (0); | |||
| 11728 | } else { | |||
| 11729 | assert(prfx == REX_WRB, "must be")do { if (!(prfx == REX_WRB)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11729, "assert(" "prfx == REX_WRB" ") failed", "must be"); :: breakpoint(); } } while (0); | |||
| 11730 | } | |||
| 11731 | } else { | |||
| 11732 | if (adr.index_needs_rex()) { | |||
| 11733 | assert(prfx == REX_WRX, "must be")do { if (!(prfx == REX_WRX)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11733, "assert(" "prfx == REX_WRX" ") failed", "must be"); :: breakpoint(); } } while (0); | |||
| 11734 | } else { | |||
| 11735 | assert(prfx == REX_WR, "must be")do { if (!(prfx == REX_WR)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11735, "assert(" "prfx == REX_WR" ") failed", "must be"); :: breakpoint(); } } while (0); | |||
| 11736 | } | |||
| 11737 | } | |||
| 11738 | } | |||
| 11739 | #endif | |||
| 11740 | return prfx; | |||
| 11741 | } | |||
| 11742 | ||||
| 11743 | void Assembler::prefixq(Address adr) { | |||
| 11744 | emit_int8(get_prefixq(adr)); | |||
| 11745 | } | |||
| 11746 | ||||
| 11747 | void Assembler::prefixq(Address adr, Register src) { | |||
| 11748 | emit_int8(get_prefixq(adr, src)); | |||
| 11749 | } | |||
| 11750 | ||||
| 11751 | void Assembler::prefixq(Address adr, XMMRegister src) { | |||
| 11752 | if (src->encoding() < 8) { | |||
| 11753 | if (adr.base_needs_rex()) { | |||
| 11754 | if (adr.index_needs_rex()) { | |||
| 11755 | prefix(REX_WXB); | |||
| 11756 | } else { | |||
| 11757 | prefix(REX_WB); | |||
| 11758 | } | |||
| 11759 | } else { | |||
| 11760 | if (adr.index_needs_rex()) { | |||
| 11761 | prefix(REX_WX); | |||
| 11762 | } else { | |||
| 11763 | prefix(REX_W); | |||
| 11764 | } | |||
| 11765 | } | |||
| 11766 | } else { | |||
| 11767 | if (adr.base_needs_rex()) { | |||
| 11768 | if (adr.index_needs_rex()) { | |||
| 11769 | prefix(REX_WRXB); | |||
| 11770 | } else { | |||
| 11771 | prefix(REX_WRB); | |||
| 11772 | } | |||
| 11773 | } else { | |||
| 11774 | if (adr.index_needs_rex()) { | |||
| 11775 | prefix(REX_WRX); | |||
| 11776 | } else { | |||
| 11777 | prefix(REX_WR); | |||
| 11778 | } | |||
| 11779 | } | |||
| 11780 | } | |||
| 11781 | } | |||
| 11782 | ||||
| 11783 | int Assembler::prefixq_and_encode(int reg_enc) { | |||
| 11784 | if (reg_enc < 8) { | |||
| 11785 | prefix(REX_W); | |||
| 11786 | } else { | |||
| 11787 | prefix(REX_WB); | |||
| 11788 | reg_enc -= 8; | |||
| 11789 | } | |||
| 11790 | return reg_enc; | |||
| 11791 | } | |||
| 11792 | ||||
| 11793 | int Assembler::prefixq_and_encode(int dst_enc, int src_enc) { | |||
| 11794 | if (dst_enc < 8) { | |||
| 11795 | if (src_enc < 8) { | |||
| 11796 | prefix(REX_W); | |||
| 11797 | } else { | |||
| 11798 | prefix(REX_WB); | |||
| 11799 | src_enc -= 8; | |||
| 11800 | } | |||
| 11801 | } else { | |||
| 11802 | if (src_enc < 8) { | |||
| 11803 | prefix(REX_WR); | |||
| 11804 | } else { | |||
| 11805 | prefix(REX_WRB); | |||
| 11806 | src_enc -= 8; | |||
| 11807 | } | |||
| 11808 | dst_enc -= 8; | |||
| 11809 | } | |||
| 11810 | return dst_enc << 3 | src_enc; | |||
| 11811 | } | |||
| 11812 | ||||
| 11813 | void Assembler::adcq(Register dst, int32_t imm32) { | |||
| 11814 | (void) prefixq_and_encode(dst->encoding()); | |||
| 11815 | emit_arith(0x81, 0xD0, dst, imm32); | |||
| 11816 | } | |||
| 11817 | ||||
| 11818 | void Assembler::adcq(Register dst, Address src) { | |||
| 11819 | InstructionMark im(this); | |||
| 11820 | emit_int16(get_prefixq(src, dst), 0x13); | |||
| 11821 | emit_operand(dst, src); | |||
| 11822 | } | |||
| 11823 | ||||
| 11824 | void Assembler::adcq(Register dst, Register src) { | |||
| 11825 | (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |||
| 11826 | emit_arith(0x13, 0xC0, dst, src); | |||
| 11827 | } | |||
| 11828 | ||||
| 11829 | void Assembler::addq(Address dst, int32_t imm32) { | |||
| 11830 | InstructionMark im(this); | |||
| 11831 | prefixq(dst); | |||
| 11832 | emit_arith_operand(0x81, rax, dst, imm32); | |||
| 11833 | } | |||
| 11834 | ||||
| 11835 | void Assembler::addq(Address dst, Register src) { | |||
| 11836 | InstructionMark im(this); | |||
| 11837 | emit_int16(get_prefixq(dst, src), 0x01); | |||
| 11838 | emit_operand(src, dst); | |||
| 11839 | } | |||
| 11840 | ||||
| 11841 | void Assembler::addq(Register dst, int32_t imm32) { | |||
| 11842 | (void) prefixq_and_encode(dst->encoding()); | |||
| 11843 | emit_arith(0x81, 0xC0, dst, imm32); | |||
| 11844 | } | |||
| 11845 | ||||
| 11846 | void Assembler::addq(Register dst, Address src) { | |||
| 11847 | InstructionMark im(this); | |||
| 11848 | emit_int16(get_prefixq(src, dst), 0x03); | |||
| 11849 | emit_operand(dst, src); | |||
| 11850 | } | |||
| 11851 | ||||
| 11852 | void Assembler::addq(Register dst, Register src) { | |||
| 11853 | (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |||
| 11854 | emit_arith(0x03, 0xC0, dst, src); | |||
| 11855 | } | |||
| 11856 | ||||
| 11857 | void Assembler::adcxq(Register dst, Register src) { | |||
| 11858 | //assert(VM_Version::supports_adx(), "adx instructions not supported"); | |||
| 11859 | emit_int8(0x66); | |||
| 11860 | int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |||
| 11861 | emit_int32(0x0F, | |||
| 11862 | 0x38, | |||
| 11863 | (unsigned char)0xF6, | |||
| 11864 | (0xC0 | encode)); | |||
| 11865 | } | |||
| 11866 | ||||
| 11867 | void Assembler::adoxq(Register dst, Register src) { | |||
| 11868 | //assert(VM_Version::supports_adx(), "adx instructions not supported"); | |||
| 11869 | emit_int8((unsigned char)0xF3); | |||
| 11870 | int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |||
| 11871 | emit_int32(0x0F, | |||
| 11872 | 0x38, | |||
| 11873 | (unsigned char)0xF6, | |||
| 11874 | (0xC0 | encode)); | |||
| 11875 | } | |||
| 11876 | ||||
| 11877 | void Assembler::andq(Address dst, int32_t imm32) { | |||
| 11878 | InstructionMark im(this); | |||
| 11879 | prefixq(dst); | |||
| 11880 | emit_arith_operand(0x81, as_Register(4), dst, imm32); | |||
| 11881 | } | |||
| 11882 | ||||
| 11883 | void Assembler::andq(Register dst, int32_t imm32) { | |||
| 11884 | (void) prefixq_and_encode(dst->encoding()); | |||
| 11885 | emit_arith(0x81, 0xE0, dst, imm32); | |||
| 11886 | } | |||
| 11887 | ||||
| 11888 | void Assembler::andq(Register dst, Address src) { | |||
| 11889 | InstructionMark im(this); | |||
| 11890 | emit_int16(get_prefixq(src, dst), 0x23); | |||
| 11891 | emit_operand(dst, src); | |||
| 11892 | } | |||
| 11893 | ||||
| 11894 | void Assembler::andq(Register dst, Register src) { | |||
| 11895 | (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |||
| 11896 | emit_arith(0x23, 0xC0, dst, src); | |||
| 11897 | } | |||
| 11898 | ||||
| 11899 | void Assembler::andq(Address dst, Register src) { | |||
| 11900 | InstructionMark im(this); | |||
| 11901 | emit_int16(get_prefixq(dst, src), 0x21); | |||
| 11902 | emit_operand(src, dst); | |||
| 11903 | } | |||
| 11904 | ||||
| 11905 | void Assembler::andnq(Register dst, Register src1, Register src2) { | |||
| 11906 | assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported")do { if (!(VM_Version::supports_bmi1())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11906, "assert(" "VM_Version::supports_bmi1()" ") failed", "bit manipulation instructions not supported" ); ::breakpoint(); } } while (0); | |||
| 11907 | InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 11908 | int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); | |||
| 11909 | emit_int16((unsigned char)0xF2, (0xC0 | encode)); | |||
| 11910 | } | |||
| 11911 | ||||
| 11912 | void Assembler::andnq(Register dst, Register src1, Address src2) { | |||
| 11913 | assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported")do { if (!(VM_Version::supports_bmi1())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11913, "assert(" "VM_Version::supports_bmi1()" ") failed", "bit manipulation instructions not supported" ); ::breakpoint(); } } while (0); | |||
| 11914 | InstructionMark im(this); | |||
| 11915 | InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 11916 | vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); | |||
| 11917 | emit_int8((unsigned char)0xF2); | |||
| 11918 | emit_operand(dst, src2); | |||
| 11919 | } | |||
| 11920 | ||||
| 11921 | void Assembler::bsfq(Register dst, Register src) { | |||
| 11922 | int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |||
| 11923 | emit_int24(0x0F, (unsigned char)0xBC, (0xC0 | encode)); | |||
| 11924 | } | |||
| 11925 | ||||
| 11926 | void Assembler::bsrq(Register dst, Register src) { | |||
| 11927 | int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |||
| 11928 | emit_int24(0x0F, (unsigned char)0xBD, (0xC0 | encode)); | |||
| 11929 | } | |||
| 11930 | ||||
| 11931 | void Assembler::bswapq(Register reg) { | |||
| 11932 | int encode = prefixq_and_encode(reg->encoding()); | |||
| 11933 | emit_int16(0x0F, (0xC8 | encode)); | |||
| 11934 | } | |||
| 11935 | ||||
| 11936 | void Assembler::blsiq(Register dst, Register src) { | |||
| 11937 | assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported")do { if (!(VM_Version::supports_bmi1())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11937, "assert(" "VM_Version::supports_bmi1()" ") failed", "bit manipulation instructions not supported" ); ::breakpoint(); } } while (0); | |||
| 11938 | InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 11939 | int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); | |||
| 11940 | emit_int16((unsigned char)0xF3, (0xC0 | encode)); | |||
| 11941 | } | |||
| 11942 | ||||
| 11943 | void Assembler::blsiq(Register dst, Address src) { | |||
| 11944 | assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported")do { if (!(VM_Version::supports_bmi1())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11944, "assert(" "VM_Version::supports_bmi1()" ") failed", "bit manipulation instructions not supported" ); ::breakpoint(); } } while (0); | |||
| 11945 | InstructionMark im(this); | |||
| 11946 | InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 11947 | vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); | |||
| 11948 | emit_int8((unsigned char)0xF3); | |||
| 11949 | emit_operand(rbx, src); | |||
| 11950 | } | |||
| 11951 | ||||
| 11952 | void Assembler::blsmskq(Register dst, Register src) { | |||
| 11953 | assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported")do { if (!(VM_Version::supports_bmi1())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11953, "assert(" "VM_Version::supports_bmi1()" ") failed", "bit manipulation instructions not supported" ); ::breakpoint(); } } while (0); | |||
| 11954 | InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 11955 | int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); | |||
| 11956 | emit_int16((unsigned char)0xF3, (0xC0 | encode)); | |||
| 11957 | } | |||
| 11958 | ||||
| 11959 | void Assembler::blsmskq(Register dst, Address src) { | |||
| 11960 | assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported")do { if (!(VM_Version::supports_bmi1())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11960, "assert(" "VM_Version::supports_bmi1()" ") failed", "bit manipulation instructions not supported" ); ::breakpoint(); } } while (0); | |||
| 11961 | InstructionMark im(this); | |||
| 11962 | InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 11963 | vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); | |||
| 11964 | emit_int8((unsigned char)0xF3); | |||
| 11965 | emit_operand(rdx, src); | |||
| 11966 | } | |||
| 11967 | ||||
| 11968 | void Assembler::blsrq(Register dst, Register src) { | |||
| 11969 | assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported")do { if (!(VM_Version::supports_bmi1())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11969, "assert(" "VM_Version::supports_bmi1()" ") failed", "bit manipulation instructions not supported" ); ::breakpoint(); } } while (0); | |||
| 11970 | InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 11971 | int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); | |||
| 11972 | emit_int16((unsigned char)0xF3, (0xC0 | encode)); | |||
| 11973 | } | |||
| 11974 | ||||
| 11975 | void Assembler::blsrq(Register dst, Address src) { | |||
| 11976 | assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported")do { if (!(VM_Version::supports_bmi1())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11976, "assert(" "VM_Version::supports_bmi1()" ") failed", "bit manipulation instructions not supported" ); ::breakpoint(); } } while (0); | |||
| 11977 | InstructionMark im(this); | |||
| 11978 | InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 11979 | vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); | |||
| 11980 | emit_int8((unsigned char)0xF3); | |||
| 11981 | emit_operand(rcx, src); | |||
| 11982 | } | |||
| 11983 | ||||
| 11984 | void Assembler::cdqq() { | |||
| 11985 | emit_int16(REX_W, (unsigned char)0x99); | |||
| 11986 | } | |||
| 11987 | ||||
| 11988 | void Assembler::clflush(Address adr) { | |||
| 11989 | assert(VM_Version::supports_clflush(), "should do")do { if (!(VM_Version::supports_clflush())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11989, "assert(" "VM_Version::supports_clflush()" ") failed" , "should do"); ::breakpoint(); } } while (0); | |||
| 11990 | prefix(adr); | |||
| 11991 | emit_int16(0x0F, (unsigned char)0xAE); | |||
| 11992 | emit_operand(rdi, adr); | |||
| 11993 | } | |||
| 11994 | ||||
| 11995 | void Assembler::clflushopt(Address adr) { | |||
| 11996 | assert(VM_Version::supports_clflushopt(), "should do!")do { if (!(VM_Version::supports_clflushopt())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11996, "assert(" "VM_Version::supports_clflushopt()" ") failed" , "should do!"); ::breakpoint(); } } while (0); | |||
| 11997 | // adr should be base reg only with no index or offset | |||
| 11998 | assert(adr.index() == noreg, "index should be noreg")do { if (!(adr.index() == noreg)) { (*g_assert_poison) = 'X'; ; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11998, "assert(" "adr.index() == noreg" ") failed", "index should be noreg" ); ::breakpoint(); } } while (0); | |||
| 11999 | assert(adr.scale() == Address::no_scale, "scale should be no_scale")do { if (!(adr.scale() == Address::no_scale)) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 11999, "assert(" "adr.scale() == Address::no_scale" ") failed" , "scale should be no_scale"); ::breakpoint(); } } while (0); | |||
| 12000 | assert(adr.disp() == 0, "displacement should be 0")do { if (!(adr.disp() == 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 12000, "assert(" "adr.disp() == 0" ") failed", "displacement should be 0" ); ::breakpoint(); } } while (0); | |||
| 12001 | // instruction prefix is 0x66 | |||
| 12002 | emit_int8(0x66); | |||
| 12003 | prefix(adr); | |||
| 12004 | // opcode family is 0x0F 0xAE | |||
| 12005 | emit_int16(0x0F, (unsigned char)0xAE); | |||
| 12006 | // extended opcode byte is 7 == rdi | |||
| 12007 | emit_operand(rdi, adr); | |||
| 12008 | } | |||
| 12009 | ||||
| 12010 | void Assembler::clwb(Address adr) { | |||
| 12011 | assert(VM_Version::supports_clwb(), "should do!")do { if (!(VM_Version::supports_clwb())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 12011, "assert(" "VM_Version::supports_clwb()" ") failed", "should do!" ); ::breakpoint(); } } while (0); | |||
| 12012 | // adr should be base reg only with no index or offset | |||
| 12013 | assert(adr.index() == noreg, "index should be noreg")do { if (!(adr.index() == noreg)) { (*g_assert_poison) = 'X'; ; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 12013, "assert(" "adr.index() == noreg" ") failed", "index should be noreg" ); ::breakpoint(); } } while (0); | |||
| 12014 | assert(adr.scale() == Address::no_scale, "scale should be no_scale")do { if (!(adr.scale() == Address::no_scale)) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 12014, "assert(" "adr.scale() == Address::no_scale" ") failed" , "scale should be no_scale"); ::breakpoint(); } } while (0); | |||
| 12015 | assert(adr.disp() == 0, "displacement should be 0")do { if (!(adr.disp() == 0)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 12015, "assert(" "adr.disp() == 0" ") failed", "displacement should be 0" ); ::breakpoint(); } } while (0); | |||
| 12016 | // instruction prefix is 0x66 | |||
| 12017 | emit_int8(0x66); | |||
| 12018 | prefix(adr); | |||
| 12019 | // opcode family is 0x0f 0xAE | |||
| 12020 | emit_int16(0x0F, (unsigned char)0xAE); | |||
| 12021 | // extended opcode byte is 6 == rsi | |||
| 12022 | emit_operand(rsi, adr); | |||
| 12023 | } | |||
| 12024 | ||||
| 12025 | void Assembler::cmovq(Condition cc, Register dst, Register src) { | |||
| 12026 | int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |||
| 12027 | emit_int24(0x0F, (0x40 | cc), (0xC0 | encode)); | |||
| 12028 | } | |||
| 12029 | ||||
| 12030 | void Assembler::cmovq(Condition cc, Register dst, Address src) { | |||
| 12031 | InstructionMark im(this); | |||
| 12032 | emit_int24(get_prefixq(src, dst), 0x0F, (0x40 | cc)); | |||
| 12033 | emit_operand(dst, src); | |||
| 12034 | } | |||
| 12035 | ||||
| 12036 | void Assembler::cmpq(Address dst, int32_t imm32) { | |||
| 12037 | InstructionMark im(this); | |||
| 12038 | emit_int16(get_prefixq(dst), (unsigned char)0x81); | |||
| 12039 | emit_operand(rdi, dst, 4); | |||
| 12040 | emit_int32(imm32); | |||
| 12041 | } | |||
| 12042 | ||||
| 12043 | void Assembler::cmpq(Register dst, int32_t imm32) { | |||
| 12044 | (void) prefixq_and_encode(dst->encoding()); | |||
| 12045 | emit_arith(0x81, 0xF8, dst, imm32); | |||
| 12046 | } | |||
| 12047 | ||||
| 12048 | void Assembler::cmpq(Address dst, Register src) { | |||
| 12049 | InstructionMark im(this); | |||
| 12050 | emit_int16(get_prefixq(dst, src), 0x39); | |||
| 12051 | emit_operand(src, dst); | |||
| 12052 | } | |||
| 12053 | ||||
| 12054 | void Assembler::cmpq(Register dst, Register src) { | |||
| 12055 | (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |||
| 12056 | emit_arith(0x3B, 0xC0, dst, src); | |||
| 12057 | } | |||
| 12058 | ||||
| 12059 | void Assembler::cmpq(Register dst, Address src) { | |||
| 12060 | InstructionMark im(this); | |||
| 12061 | emit_int16(get_prefixq(src, dst), 0x3B); | |||
| 12062 | emit_operand(dst, src); | |||
| 12063 | } | |||
| 12064 | ||||
| 12065 | void Assembler::cmpxchgq(Register reg, Address adr) { | |||
| 12066 | InstructionMark im(this); | |||
| 12067 | emit_int24(get_prefixq(adr, reg), 0x0F, (unsigned char)0xB1); | |||
| 12068 | emit_operand(reg, adr); | |||
| 12069 | } | |||
| 12070 | ||||
| 12071 | void Assembler::cvtsi2sdq(XMMRegister dst, Register src) { | |||
| 12072 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 12073 | InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 12074 | int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); | |||
| 12075 | emit_int16(0x2A, (0xC0 | encode)); | |||
| 12076 | } | |||
| 12077 | ||||
| 12078 | void Assembler::cvtsi2sdq(XMMRegister dst, Address src) { | |||
| 12079 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 12080 | InstructionMark im(this); | |||
| 12081 | InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 12082 | attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); | |||
| 12083 | simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); | |||
| 12084 | emit_int8(0x2A); | |||
| 12085 | emit_operand(dst, src); | |||
| 12086 | } | |||
| 12087 | ||||
| 12088 | void Assembler::cvtsi2ssq(XMMRegister dst, Address src) { | |||
| 12089 | NOT_LP64(assert(VM_Version::supports_sse(), "")); | |||
| 12090 | InstructionMark im(this); | |||
| 12091 | InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 12092 | attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); | |||
| 12093 | simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); | |||
| 12094 | emit_int8(0x2A); | |||
| 12095 | emit_operand(dst, src); | |||
| 12096 | } | |||
| 12097 | ||||
| 12098 | void Assembler::cvttsd2siq(Register dst, Address src) { | |||
| 12099 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 12100 | // F2 REX.W 0F 2C /r | |||
| 12101 | // CVTTSD2SI r64, xmm1/m64 | |||
| 12102 | InstructionMark im(this); | |||
| 12103 | emit_int32((unsigned char)0xF2, REX_W, 0x0F, 0x2C); | |||
| 12104 | emit_operand(dst, src); | |||
| 12105 | } | |||
| 12106 | ||||
| 12107 | void Assembler::cvttsd2siq(Register dst, XMMRegister src) { | |||
| 12108 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 12109 | InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 12110 | int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); | |||
| 12111 | emit_int16(0x2C, (0xC0 | encode)); | |||
| 12112 | } | |||
| 12113 | ||||
| 12114 | void Assembler::cvttss2siq(Register dst, XMMRegister src) { | |||
| 12115 | NOT_LP64(assert(VM_Version::supports_sse(), "")); | |||
| 12116 | InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 12117 | int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); | |||
| 12118 | emit_int16(0x2C, (0xC0 | encode)); | |||
| 12119 | } | |||
| 12120 | ||||
| 12121 | void Assembler::decl(Register dst) { | |||
| 12122 | // Don't use it directly. Use MacroAssembler::decrementl() instead. | |||
| 12123 | // Use two-byte form (one-byte form is a REX prefix in 64-bit mode) | |||
| 12124 | int encode = prefix_and_encode(dst->encoding()); | |||
| 12125 | emit_int16((unsigned char)0xFF, (0xC8 | encode)); | |||
| 12126 | } | |||
| 12127 | ||||
| 12128 | void Assembler::decq(Register dst) { | |||
| 12129 | // Don't use it directly. Use MacroAssembler::decrementq() instead. | |||
| 12130 | // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) | |||
| 12131 | int encode = prefixq_and_encode(dst->encoding()); | |||
| 12132 | emit_int16((unsigned char)0xFF, 0xC8 | encode); | |||
| 12133 | } | |||
| 12134 | ||||
| 12135 | void Assembler::decq(Address dst) { | |||
| 12136 | // Don't use it directly. Use MacroAssembler::decrementq() instead. | |||
| 12137 | InstructionMark im(this); | |||
| 12138 | emit_int16(get_prefixq(dst), (unsigned char)0xFF); | |||
| 12139 | emit_operand(rcx, dst); | |||
| 12140 | } | |||
| 12141 | ||||
| 12142 | void Assembler::fxrstor(Address src) { | |||
| 12143 | emit_int24(get_prefixq(src), 0x0F, (unsigned char)0xAE); | |||
| 12144 | emit_operand(as_Register(1), src); | |||
| 12145 | } | |||
| 12146 | ||||
| 12147 | void Assembler::xrstor(Address src) { | |||
| 12148 | emit_int24(get_prefixq(src), 0x0F, (unsigned char)0xAE); | |||
| 12149 | emit_operand(as_Register(5), src); | |||
| 12150 | } | |||
| 12151 | ||||
| 12152 | void Assembler::fxsave(Address dst) { | |||
| 12153 | emit_int24(get_prefixq(dst), 0x0F, (unsigned char)0xAE); | |||
| 12154 | emit_operand(as_Register(0), dst); | |||
| 12155 | } | |||
| 12156 | ||||
| 12157 | void Assembler::xsave(Address dst) { | |||
| 12158 | emit_int24(get_prefixq(dst), 0x0F, (unsigned char)0xAE); | |||
| 12159 | emit_operand(as_Register(4), dst); | |||
| 12160 | } | |||
| 12161 | ||||
| 12162 | void Assembler::idivq(Register src) { | |||
| 12163 | int encode = prefixq_and_encode(src->encoding()); | |||
| 12164 | emit_int16((unsigned char)0xF7, (0xF8 | encode)); | |||
| 12165 | } | |||
| 12166 | ||||
| 12167 | void Assembler::imulq(Register dst, Register src) { | |||
| 12168 | int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |||
| 12169 | emit_int24(0x0F, (unsigned char)0xAF, (0xC0 | encode)); | |||
| 12170 | } | |||
| 12171 | ||||
| 12172 | void Assembler::imulq(Register src) { | |||
| 12173 | int encode = prefixq_and_encode(src->encoding()); | |||
| 12174 | emit_int16((unsigned char)0xF7, (0xE8 | encode)); | |||
| 12175 | } | |||
| 12176 | ||||
| 12177 | void Assembler::imulq(Register dst, Address src, int32_t value) { | |||
| 12178 | InstructionMark im(this); | |||
| 12179 | prefixq(src, dst); | |||
| 12180 | if (is8bit(value)) { | |||
| 12181 | emit_int8((unsigned char)0x6B); | |||
| 12182 | emit_operand(dst, src); | |||
| 12183 | emit_int8(value); | |||
| 12184 | } else { | |||
| 12185 | emit_int8((unsigned char)0x69); | |||
| 12186 | emit_operand(dst, src); | |||
| 12187 | emit_int32(value); | |||
| 12188 | } | |||
| 12189 | } | |||
| 12190 | ||||
| 12191 | void Assembler::imulq(Register dst, Register src, int value) { | |||
| 12192 | int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |||
| 12193 | if (is8bit(value)) { | |||
| 12194 | emit_int24(0x6B, (0xC0 | encode), (value & 0xFF)); | |||
| 12195 | } else { | |||
| 12196 | emit_int16(0x69, (0xC0 | encode)); | |||
| 12197 | emit_int32(value); | |||
| 12198 | } | |||
| 12199 | } | |||
| 12200 | ||||
| 12201 | void Assembler::imulq(Register dst, Address src) { | |||
| 12202 | InstructionMark im(this); | |||
| 12203 | emit_int24(get_prefixq(src, dst), 0x0F, (unsigned char)0xAF); | |||
| 12204 | emit_operand(dst, src); | |||
| 12205 | } | |||
| 12206 | ||||
| 12207 | void Assembler::incl(Register dst) { | |||
| 12208 | // Don't use it directly. Use MacroAssembler::incrementl() instead. | |||
| 12209 | // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) | |||
| 12210 | int encode = prefix_and_encode(dst->encoding()); | |||
| 12211 | emit_int16((unsigned char)0xFF, (0xC0 | encode)); | |||
| 12212 | } | |||
| 12213 | ||||
| 12214 | void Assembler::incq(Register dst) { | |||
| 12215 | // Don't use it directly. Use MacroAssembler::incrementq() instead. | |||
| 12216 | // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) | |||
| 12217 | int encode = prefixq_and_encode(dst->encoding()); | |||
| 12218 | emit_int16((unsigned char)0xFF, (0xC0 | encode)); | |||
| 12219 | } | |||
| 12220 | ||||
| 12221 | void Assembler::incq(Address dst) { | |||
| 12222 | // Don't use it directly. Use MacroAssembler::incrementq() instead. | |||
| 12223 | InstructionMark im(this); | |||
| 12224 | emit_int16(get_prefixq(dst), (unsigned char)0xFF); | |||
| 12225 | emit_operand(rax, dst); | |||
| 12226 | } | |||
| 12227 | ||||
| 12228 | void Assembler::lea(Register dst, Address src) { | |||
| 12229 | leaq(dst, src); | |||
| 12230 | } | |||
| 12231 | ||||
| 12232 | void Assembler::leaq(Register dst, Address src) { | |||
| 12233 | InstructionMark im(this); | |||
| 12234 | emit_int16(get_prefixq(src, dst), (unsigned char)0x8D); | |||
| 12235 | emit_operand(dst, src); | |||
| 12236 | } | |||
| 12237 | ||||
| 12238 | void Assembler::mov64(Register dst, int64_t imm64) { | |||
| 12239 | InstructionMark im(this); | |||
| 12240 | int encode = prefixq_and_encode(dst->encoding()); | |||
| 12241 | emit_int8(0xB8 | encode); | |||
| 12242 | emit_int64(imm64); | |||
| 12243 | } | |||
| 12244 | ||||
| 12245 | void Assembler::mov64(Register dst, int64_t imm64, relocInfo::relocType rtype, int format) { | |||
| 12246 | InstructionMark im(this); | |||
| 12247 | int encode = prefixq_and_encode(dst->encoding()); | |||
| 12248 | emit_int8(0xB8 | encode); | |||
| 12249 | emit_data64(imm64, rtype, format); | |||
| 12250 | } | |||
| 12251 | ||||
| 12252 | void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) { | |||
| 12253 | InstructionMark im(this); | |||
| 12254 | int encode = prefixq_and_encode(dst->encoding()); | |||
| 12255 | emit_int8(0xB8 | encode); | |||
| 12256 | emit_data64(imm64, rspec); | |||
| 12257 | } | |||
| 12258 | ||||
| 12259 | void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) { | |||
| 12260 | InstructionMark im(this); | |||
| 12261 | int encode = prefix_and_encode(dst->encoding()); | |||
| 12262 | emit_int8(0xB8 | encode); | |||
| 12263 | emit_data((int)imm32, rspec, narrow_oop_operand); | |||
| 12264 | } | |||
| 12265 | ||||
| 12266 | void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) { | |||
| 12267 | InstructionMark im(this); | |||
| 12268 | prefix(dst); | |||
| 12269 | emit_int8((unsigned char)0xC7); | |||
| 12270 | emit_operand(rax, dst, 4); | |||
| 12271 | emit_data((int)imm32, rspec, narrow_oop_operand); | |||
| 12272 | } | |||
| 12273 | ||||
| 12274 | void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) { | |||
| 12275 | InstructionMark im(this); | |||
| 12276 | int encode = prefix_and_encode(src1->encoding()); | |||
| 12277 | emit_int16((unsigned char)0x81, (0xF8 | encode)); | |||
| 12278 | emit_data((int)imm32, rspec, narrow_oop_operand); | |||
| 12279 | } | |||
| 12280 | ||||
| 12281 | void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) { | |||
| 12282 | InstructionMark im(this); | |||
| 12283 | prefix(src1); | |||
| 12284 | emit_int8((unsigned char)0x81); | |||
| 12285 | emit_operand(rax, src1, 4); | |||
| 12286 | emit_data((int)imm32, rspec, narrow_oop_operand); | |||
| 12287 | } | |||
| 12288 | ||||
| 12289 | void Assembler::lzcntq(Register dst, Register src) { | |||
| 12290 | assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR")do { if (!(VM_Version::supports_lzcnt())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 12290, "assert(" "VM_Version::supports_lzcnt()" ") failed", "encoding is treated as BSR"); ::breakpoint(); } } while (0); | |||
| 12291 | emit_int8((unsigned char)0xF3); | |||
| 12292 | int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |||
| 12293 | emit_int24(0x0F, (unsigned char)0xBD, (0xC0 | encode)); | |||
| 12294 | } | |||
| 12295 | ||||
| 12296 | void Assembler::movdq(XMMRegister dst, Register src) { | |||
| 12297 | // table D-1 says MMX/SSE2 | |||
| 12298 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 12299 | InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 12300 | int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 12301 | emit_int16(0x6E, (0xC0 | encode)); | |||
| 12302 | } | |||
| 12303 | ||||
| 12304 | void Assembler::movdq(Register dst, XMMRegister src) { | |||
| 12305 | // table D-1 says MMX/SSE2 | |||
| 12306 | NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |||
| 12307 | InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 12308 | // swap src/dst to get correct prefix | |||
| 12309 | int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); | |||
| 12310 | emit_int16(0x7E, | |||
| 12311 | (0xC0 | encode)); | |||
| 12312 | } | |||
| 12313 | ||||
| 12314 | void Assembler::movq(Register dst, Register src) { | |||
| 12315 | int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |||
| 12316 | emit_int16((unsigned char)0x8B, | |||
| 12317 | (0xC0 | encode)); | |||
| 12318 | } | |||
| 12319 | ||||
| 12320 | void Assembler::movq(Register dst, Address src) { | |||
| 12321 | InstructionMark im(this); | |||
| 12322 | emit_int16(get_prefixq(src, dst), (unsigned char)0x8B); | |||
| 12323 | emit_operand(dst, src); | |||
| 12324 | } | |||
| 12325 | ||||
| 12326 | void Assembler::movq(Address dst, Register src) { | |||
| 12327 | InstructionMark im(this); | |||
| 12328 | emit_int16(get_prefixq(dst, src), (unsigned char)0x89); | |||
| 12329 | emit_operand(src, dst); | |||
| 12330 | } | |||
| 12331 | ||||
| 12332 | void Assembler::movq(Address dst, int32_t imm32) { | |||
| 12333 | InstructionMark im(this); | |||
| 12334 | emit_int16(get_prefixq(dst), (unsigned char)0xC7); | |||
| 12335 | emit_operand(as_Register(0), dst); | |||
| 12336 | emit_int32(imm32); | |||
| 12337 | } | |||
| 12338 | ||||
| 12339 | void Assembler::movq(Register dst, int32_t imm32) { | |||
| 12340 | int encode = prefixq_and_encode(dst->encoding()); | |||
| 12341 | emit_int16((unsigned char)0xC7, (0xC0 | encode)); | |||
| 12342 | emit_int32(imm32); | |||
| 12343 | } | |||
| 12344 | ||||
| 12345 | void Assembler::movsbq(Register dst, Address src) { | |||
| 12346 | InstructionMark im(this); | |||
| 12347 | emit_int24(get_prefixq(src, dst), | |||
| 12348 | 0x0F, | |||
| 12349 | (unsigned char)0xBE); | |||
| 12350 | emit_operand(dst, src); | |||
| 12351 | } | |||
| 12352 | ||||
| 12353 | void Assembler::movsbq(Register dst, Register src) { | |||
| 12354 | int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |||
| 12355 | emit_int24(0x0F, (unsigned char)0xBE, (0xC0 | encode)); | |||
| 12356 | } | |||
| 12357 | ||||
| 12358 | void Assembler::movslq(Register dst, int32_t imm32) { | |||
| 12359 | // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx) | |||
| 12360 | // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx) | |||
| 12361 | // as a result we shouldn't use until tested at runtime... | |||
| 12362 | ShouldNotReachHere()do { (*g_assert_poison) = 'X';; report_should_not_reach_here( "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 12362); ::breakpoint(); } while (0); | |||
| 12363 | InstructionMark im(this); | |||
| 12364 | int encode = prefixq_and_encode(dst->encoding()); | |||
| 12365 | emit_int8(0xC7 | encode); | |||
| 12366 | emit_int32(imm32); | |||
| 12367 | } | |||
| 12368 | ||||
| 12369 | void Assembler::movslq(Address dst, int32_t imm32) { | |||
| 12370 | assert(is_simm32(imm32), "lost bits")do { if (!(is_simm32(imm32))) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 12370, "assert(" "is_simm32(imm32)" ") failed", "lost bits" ); ::breakpoint(); } } while (0); | |||
| 12371 | InstructionMark im(this); | |||
| 12372 | emit_int16(get_prefixq(dst), (unsigned char)0xC7); | |||
| 12373 | emit_operand(rax, dst, 4); | |||
| 12374 | emit_int32(imm32); | |||
| 12375 | } | |||
| 12376 | ||||
| 12377 | void Assembler::movslq(Register dst, Address src) { | |||
| 12378 | InstructionMark im(this); | |||
| 12379 | emit_int16(get_prefixq(src, dst), 0x63); | |||
| 12380 | emit_operand(dst, src); | |||
| 12381 | } | |||
| 12382 | ||||
| 12383 | void Assembler::movslq(Register dst, Register src) { | |||
| 12384 | int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |||
| 12385 | emit_int16(0x63, (0xC0 | encode)); | |||
| 12386 | } | |||
| 12387 | ||||
| 12388 | void Assembler::movswq(Register dst, Address src) { | |||
| 12389 | InstructionMark im(this); | |||
| 12390 | emit_int24(get_prefixq(src, dst), | |||
| 12391 | 0x0F, | |||
| 12392 | (unsigned char)0xBF); | |||
| 12393 | emit_operand(dst, src); | |||
| 12394 | } | |||
| 12395 | ||||
| 12396 | void Assembler::movswq(Register dst, Register src) { | |||
| 12397 | int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |||
| 12398 | emit_int24(0x0F, (unsigned char)0xBF, (0xC0 | encode)); | |||
| 12399 | } | |||
| 12400 | ||||
| 12401 | void Assembler::movzbq(Register dst, Address src) { | |||
| 12402 | InstructionMark im(this); | |||
| 12403 | emit_int24(get_prefixq(src, dst), | |||
| 12404 | 0x0F, | |||
| 12405 | (unsigned char)0xB6); | |||
| 12406 | emit_operand(dst, src); | |||
| 12407 | } | |||
| 12408 | ||||
| 12409 | void Assembler::movzbq(Register dst, Register src) { | |||
| 12410 | int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |||
| 12411 | emit_int24(0x0F, (unsigned char)0xB6, (0xC0 | encode)); | |||
| 12412 | } | |||
| 12413 | ||||
| 12414 | void Assembler::movzwq(Register dst, Address src) { | |||
| 12415 | InstructionMark im(this); | |||
| 12416 | emit_int24(get_prefixq(src, dst), | |||
| 12417 | 0x0F, | |||
| 12418 | (unsigned char)0xB7); | |||
| 12419 | emit_operand(dst, src); | |||
| 12420 | } | |||
| 12421 | ||||
| 12422 | void Assembler::movzwq(Register dst, Register src) { | |||
| 12423 | int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |||
| 12424 | emit_int24(0x0F, (unsigned char)0xB7, (0xC0 | encode)); | |||
| 12425 | } | |||
| 12426 | ||||
| 12427 | void Assembler::mulq(Address src) { | |||
| 12428 | InstructionMark im(this); | |||
| 12429 | emit_int16(get_prefixq(src), (unsigned char)0xF7); | |||
| 12430 | emit_operand(rsp, src); | |||
| 12431 | } | |||
| 12432 | ||||
| 12433 | void Assembler::mulq(Register src) { | |||
| 12434 | int encode = prefixq_and_encode(src->encoding()); | |||
| 12435 | emit_int16((unsigned char)0xF7, (0xE0 | encode)); | |||
| 12436 | } | |||
| 12437 | ||||
| 12438 | void Assembler::mulxq(Register dst1, Register dst2, Register src) { | |||
| 12439 | assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported")do { if (!(VM_Version::supports_bmi2())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 12439, "assert(" "VM_Version::supports_bmi2()" ") failed", "bit manipulation instructions not supported" ); ::breakpoint(); } } while (0); | |||
| 12440 | InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 12441 | int encode = vex_prefix_and_encode(dst1->encoding(), dst2->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes); | |||
| 12442 | emit_int16((unsigned char)0xF6, (0xC0 | encode)); | |||
| 12443 | } | |||
| 12444 | ||||
| 12445 | void Assembler::negq(Register dst) { | |||
| 12446 | int encode = prefixq_and_encode(dst->encoding()); | |||
| 12447 | emit_int16((unsigned char)0xF7, (0xD8 | encode)); | |||
| 12448 | } | |||
| 12449 | ||||
| 12450 | void Assembler::negq(Address dst) { | |||
| 12451 | InstructionMark im(this); | |||
| 12452 | emit_int16(get_prefixq(dst), (unsigned char)0xF7); | |||
| 12453 | emit_operand(as_Register(3), dst); | |||
| 12454 | } | |||
| 12455 | ||||
| 12456 | void Assembler::notq(Register dst) { | |||
| 12457 | int encode = prefixq_and_encode(dst->encoding()); | |||
| 12458 | emit_int16((unsigned char)0xF7, (0xD0 | encode)); | |||
| 12459 | } | |||
| 12460 | ||||
| 12461 | void Assembler::btsq(Address dst, int imm8) { | |||
| 12462 | assert(isByte(imm8), "not a byte")do { if (!(isByte(imm8))) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 12462, "assert(" "isByte(imm8)" ") failed", "not a byte"); :: breakpoint(); } } while (0); | |||
| 12463 | InstructionMark im(this); | |||
| 12464 | emit_int24(get_prefixq(dst), | |||
| 12465 | 0x0F, | |||
| 12466 | (unsigned char)0xBA); | |||
| 12467 | emit_operand(rbp /* 5 */, dst, 1); | |||
| 12468 | emit_int8(imm8); | |||
| 12469 | } | |||
| 12470 | ||||
| 12471 | void Assembler::btrq(Address dst, int imm8) { | |||
| 12472 | assert(isByte(imm8), "not a byte")do { if (!(isByte(imm8))) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 12472, "assert(" "isByte(imm8)" ") failed", "not a byte"); :: breakpoint(); } } while (0); | |||
| 12473 | InstructionMark im(this); | |||
| 12474 | emit_int24(get_prefixq(dst), | |||
| 12475 | 0x0F, | |||
| 12476 | (unsigned char)0xBA); | |||
| 12477 | emit_operand(rsi /* 6 */, dst, 1); | |||
| 12478 | emit_int8(imm8); | |||
| 12479 | } | |||
| 12480 | ||||
| 12481 | void Assembler::orq(Address dst, int32_t imm32) { | |||
| 12482 | InstructionMark im(this); | |||
| 12483 | prefixq(dst); | |||
| 12484 | emit_arith_operand(0x81, as_Register(1), dst, imm32); | |||
| 12485 | } | |||
| 12486 | ||||
| 12487 | void Assembler::orq(Address dst, Register src) { | |||
| 12488 | InstructionMark im(this); | |||
| 12489 | emit_int16(get_prefixq(dst, src), (unsigned char)0x09); | |||
| 12490 | emit_operand(src, dst); | |||
| 12491 | } | |||
| 12492 | ||||
| 12493 | void Assembler::orq(Register dst, int32_t imm32) { | |||
| 12494 | (void) prefixq_and_encode(dst->encoding()); | |||
| 12495 | emit_arith(0x81, 0xC8, dst, imm32); | |||
| 12496 | } | |||
| 12497 | ||||
| 12498 | void Assembler::orq(Register dst, Address src) { | |||
| 12499 | InstructionMark im(this); | |||
| 12500 | emit_int16(get_prefixq(src, dst), 0x0B); | |||
| 12501 | emit_operand(dst, src); | |||
| 12502 | } | |||
| 12503 | ||||
| 12504 | void Assembler::orq(Register dst, Register src) { | |||
| 12505 | (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |||
| 12506 | emit_arith(0x0B, 0xC0, dst, src); | |||
| 12507 | } | |||
| 12508 | ||||
| 12509 | void Assembler::popcntq(Register dst, Address src) { | |||
| 12510 | assert(VM_Version::supports_popcnt(), "must support")do { if (!(VM_Version::supports_popcnt())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 12510, "assert(" "VM_Version::supports_popcnt()" ") failed" , "must support"); ::breakpoint(); } } while (0); | |||
| 12511 | InstructionMark im(this); | |||
| 12512 | emit_int32((unsigned char)0xF3, | |||
| 12513 | get_prefixq(src, dst), | |||
| 12514 | 0x0F, | |||
| 12515 | (unsigned char)0xB8); | |||
| 12516 | emit_operand(dst, src); | |||
| 12517 | } | |||
| 12518 | ||||
| 12519 | void Assembler::popcntq(Register dst, Register src) { | |||
| 12520 | assert(VM_Version::supports_popcnt(), "must support")do { if (!(VM_Version::supports_popcnt())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 12520, "assert(" "VM_Version::supports_popcnt()" ") failed" , "must support"); ::breakpoint(); } } while (0); | |||
| 12521 | emit_int8((unsigned char)0xF3); | |||
| 12522 | int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |||
| 12523 | emit_int24(0x0F, (unsigned char)0xB8, (0xC0 | encode)); | |||
| 12524 | } | |||
| 12525 | ||||
| 12526 | void Assembler::popq(Address dst) { | |||
| 12527 | InstructionMark im(this); | |||
| 12528 | emit_int16(get_prefixq(dst), (unsigned char)0x8F); | |||
| 12529 | emit_operand(rax, dst); | |||
| 12530 | } | |||
| 12531 | ||||
| 12532 | void Assembler::popq(Register dst) { | |||
| 12533 | emit_int8((unsigned char)0x58 | dst->encoding()); | |||
| 12534 | } | |||
| 12535 | ||||
| 12536 | // Precomputable: popa, pusha, vzeroupper | |||
| 12537 | ||||
| 12538 | // The result of these routines are invariant from one invocation to another | |||
| 12539 | // invocation for the duration of a run. Caching the result on bootstrap | |||
| 12540 | // and copying it out on subsequent invocations can thus be beneficial | |||
| 12541 | static bool precomputed = false; | |||
| 12542 | ||||
| 12543 | static u_char* popa_code = NULL__null; | |||
| 12544 | static int popa_len = 0; | |||
| 12545 | ||||
| 12546 | static u_char* pusha_code = NULL__null; | |||
| 12547 | static int pusha_len = 0; | |||
| 12548 | ||||
| 12549 | static u_char* vzup_code = NULL__null; | |||
| 12550 | static int vzup_len = 0; | |||
| 12551 | ||||
| 12552 | void Assembler::precompute_instructions() { | |||
| 12553 | assert(!Universe::is_fully_initialized(), "must still be single threaded")do { if (!(!Universe::is_fully_initialized())) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 12553, "assert(" "!Universe::is_fully_initialized()" ") failed" , "must still be single threaded"); ::breakpoint(); } } while (0); | |||
| 12554 | guarantee(!precomputed, "only once")do { if (!(!precomputed)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 12554, "guarantee(" "!precomputed" ") failed", "only once") ; ::breakpoint(); } } while (0); | |||
| 12555 | precomputed = true; | |||
| 12556 | ResourceMark rm; | |||
| 12557 | ||||
| 12558 | // Make a temporary buffer big enough for the routines we're capturing | |||
| 12559 | int size = 256; | |||
| 12560 | char* tmp_code = NEW_RESOURCE_ARRAY(char, size)(char*) resource_allocate_bytes((size) * sizeof(char)); | |||
| 12561 | CodeBuffer buffer((address)tmp_code, size); | |||
| 12562 | MacroAssembler masm(&buffer); | |||
| 12563 | ||||
| 12564 | address begin_popa = masm.code_section()->end(); | |||
| 12565 | masm.popa_uncached(); | |||
| 12566 | address end_popa = masm.code_section()->end(); | |||
| 12567 | masm.pusha_uncached(); | |||
| 12568 | address end_pusha = masm.code_section()->end(); | |||
| 12569 | masm.vzeroupper_uncached(); | |||
| 12570 | address end_vzup = masm.code_section()->end(); | |||
| 12571 | ||||
| 12572 | // Save the instructions to permanent buffers. | |||
| 12573 | popa_len = (int)(end_popa - begin_popa); | |||
| 12574 | popa_code = NEW_C_HEAP_ARRAY(u_char, popa_len, mtInternal)(u_char*) (AllocateHeap((popa_len) * sizeof(u_char), mtInternal )); | |||
| 12575 | memcpy(popa_code, begin_popa, popa_len); | |||
| 12576 | ||||
| 12577 | pusha_len = (int)(end_pusha - end_popa); | |||
| 12578 | pusha_code = NEW_C_HEAP_ARRAY(u_char, pusha_len, mtInternal)(u_char*) (AllocateHeap((pusha_len) * sizeof(u_char), mtInternal )); | |||
| 12579 | memcpy(pusha_code, end_popa, pusha_len); | |||
| 12580 | ||||
| 12581 | vzup_len = (int)(end_vzup - end_pusha); | |||
| 12582 | if (vzup_len > 0) { | |||
| 12583 | vzup_code = NEW_C_HEAP_ARRAY(u_char, vzup_len, mtInternal)(u_char*) (AllocateHeap((vzup_len) * sizeof(u_char), mtInternal )); | |||
| 12584 | memcpy(vzup_code, end_pusha, vzup_len); | |||
| 12585 | } else { | |||
| 12586 | vzup_code = pusha_code; // dummy | |||
| 12587 | } | |||
| 12588 | ||||
| 12589 | assert(masm.code()->total_oop_size() == 0 &&do { if (!(masm.code()->total_oop_size() == 0 && masm .code()->total_metadata_size() == 0 && masm.code() ->total_relocation_size() == 0)) { (*g_assert_poison) = 'X' ;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 12592, "assert(" "masm.code()->total_oop_size() == 0 && masm.code()->total_metadata_size() == 0 && masm.code()->total_relocation_size() == 0" ") failed", "pre-computed code can't reference oops, metadata or contain relocations" ); ::breakpoint(); } } while (0) | |||
| 12590 | masm.code()->total_metadata_size() == 0 &&do { if (!(masm.code()->total_oop_size() == 0 && masm .code()->total_metadata_size() == 0 && masm.code() ->total_relocation_size() == 0)) { (*g_assert_poison) = 'X' ;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 12592, "assert(" "masm.code()->total_oop_size() == 0 && masm.code()->total_metadata_size() == 0 && masm.code()->total_relocation_size() == 0" ") failed", "pre-computed code can't reference oops, metadata or contain relocations" ); ::breakpoint(); } } while (0) | |||
| 12591 | masm.code()->total_relocation_size() == 0,do { if (!(masm.code()->total_oop_size() == 0 && masm .code()->total_metadata_size() == 0 && masm.code() ->total_relocation_size() == 0)) { (*g_assert_poison) = 'X' ;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 12592, "assert(" "masm.code()->total_oop_size() == 0 && masm.code()->total_metadata_size() == 0 && masm.code()->total_relocation_size() == 0" ") failed", "pre-computed code can't reference oops, metadata or contain relocations" ); ::breakpoint(); } } while (0) | |||
| 12592 | "pre-computed code can't reference oops, metadata or contain relocations")do { if (!(masm.code()->total_oop_size() == 0 && masm .code()->total_metadata_size() == 0 && masm.code() ->total_relocation_size() == 0)) { (*g_assert_poison) = 'X' ;; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 12592, "assert(" "masm.code()->total_oop_size() == 0 && masm.code()->total_metadata_size() == 0 && masm.code()->total_relocation_size() == 0" ") failed", "pre-computed code can't reference oops, metadata or contain relocations" ); ::breakpoint(); } } while (0); | |||
| 12593 | } | |||
| 12594 | ||||
| 12595 | static void emit_copy(CodeSection* code_section, u_char* src, int src_len) { | |||
| 12596 | assert(src != NULL, "code to copy must have been pre-computed")do { if (!(src != __null)) { (*g_assert_poison) = 'X';; report_vm_error ("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 12596, "assert(" "src != __null" ") failed", "code to copy must have been pre-computed" ); ::breakpoint(); } } while (0); | |||
| 12597 | assert(code_section->limit() - code_section->end() > src_len, "code buffer not large enough")do { if (!(code_section->limit() - code_section->end() > src_len)) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 12597, "assert(" "code_section->limit() - code_section->end() > src_len" ") failed", "code buffer not large enough"); ::breakpoint(); } } while (0); | |||
| 12598 | address end = code_section->end(); | |||
| 12599 | memcpy(end, src, src_len); | |||
| 12600 | code_section->set_end(end + src_len); | |||
| 12601 | } | |||
| 12602 | ||||
| 12603 | void Assembler::popa() { // 64bit | |||
| 12604 | emit_copy(code_section(), popa_code, popa_len); | |||
| 12605 | } | |||
| 12606 | ||||
| 12607 | void Assembler::popa_uncached() { // 64bit | |||
| 12608 | movq(r15, Address(rsp, 0)); | |||
| 12609 | movq(r14, Address(rsp, wordSize)); | |||
| 12610 | movq(r13, Address(rsp, 2 * wordSize)); | |||
| 12611 | movq(r12, Address(rsp, 3 * wordSize)); | |||
| 12612 | movq(r11, Address(rsp, 4 * wordSize)); | |||
| 12613 | movq(r10, Address(rsp, 5 * wordSize)); | |||
| 12614 | movq(r9, Address(rsp, 6 * wordSize)); | |||
| 12615 | movq(r8, Address(rsp, 7 * wordSize)); | |||
| 12616 | movq(rdi, Address(rsp, 8 * wordSize)); | |||
| 12617 | movq(rsi, Address(rsp, 9 * wordSize)); | |||
| 12618 | movq(rbp, Address(rsp, 10 * wordSize)); | |||
| 12619 | // Skip rsp as it is restored automatically to the value | |||
| 12620 | // before the corresponding pusha when popa is done. | |||
| 12621 | movq(rbx, Address(rsp, 12 * wordSize)); | |||
| 12622 | movq(rdx, Address(rsp, 13 * wordSize)); | |||
| 12623 | movq(rcx, Address(rsp, 14 * wordSize)); | |||
| 12624 | movq(rax, Address(rsp, 15 * wordSize)); | |||
| 12625 | ||||
| 12626 | addq(rsp, 16 * wordSize); | |||
| 12627 | } | |||
| 12628 | ||||
| 12629 | // Does not actually store the value of rsp on the stack. | |||
| 12630 | // The slot for rsp just contains an arbitrary value. | |||
| 12631 | void Assembler::pusha() { // 64bit | |||
| 12632 | emit_copy(code_section(), pusha_code, pusha_len); | |||
| 12633 | } | |||
| 12634 | ||||
| 12635 | // Does not actually store the value of rsp on the stack. | |||
| 12636 | // The slot for rsp just contains an arbitrary value. | |||
| 12637 | void Assembler::pusha_uncached() { // 64bit | |||
| 12638 | subq(rsp, 16 * wordSize); | |||
| 12639 | ||||
| 12640 | movq(Address(rsp, 15 * wordSize), rax); | |||
| 12641 | movq(Address(rsp, 14 * wordSize), rcx); | |||
| 12642 | movq(Address(rsp, 13 * wordSize), rdx); | |||
| 12643 | movq(Address(rsp, 12 * wordSize), rbx); | |||
| 12644 | // Skip rsp as the value is normally not used. There are a few places where | |||
| 12645 | // the original value of rsp needs to be known but that can be computed | |||
| 12646 | // from the value of rsp immediately after pusha (rsp + 16 * wordSize). | |||
| 12647 | movq(Address(rsp, 10 * wordSize), rbp); | |||
| 12648 | movq(Address(rsp, 9 * wordSize), rsi); | |||
| 12649 | movq(Address(rsp, 8 * wordSize), rdi); | |||
| 12650 | movq(Address(rsp, 7 * wordSize), r8); | |||
| 12651 | movq(Address(rsp, 6 * wordSize), r9); | |||
| 12652 | movq(Address(rsp, 5 * wordSize), r10); | |||
| 12653 | movq(Address(rsp, 4 * wordSize), r11); | |||
| 12654 | movq(Address(rsp, 3 * wordSize), r12); | |||
| 12655 | movq(Address(rsp, 2 * wordSize), r13); | |||
| 12656 | movq(Address(rsp, wordSize), r14); | |||
| 12657 | movq(Address(rsp, 0), r15); | |||
| 12658 | } | |||
| 12659 | ||||
| 12660 | void Assembler::vzeroupper() { | |||
| 12661 | emit_copy(code_section(), vzup_code, vzup_len); | |||
| 12662 | } | |||
| 12663 | ||||
| 12664 | void Assembler::pushq(Address src) { | |||
| 12665 | InstructionMark im(this); | |||
| 12666 | emit_int16(get_prefixq(src), (unsigned char)0xFF); | |||
| 12667 | emit_operand(rsi, src); | |||
| 12668 | } | |||
| 12669 | ||||
| 12670 | void Assembler::rclq(Register dst, int imm8) { | |||
| 12671 | assert(isShiftCount(imm8 >> 1), "illegal shift count")do { if (!(isShiftCount(imm8 >> 1))) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 12671, "assert(" "isShiftCount(imm8 >> 1)" ") failed" , "illegal shift count"); ::breakpoint(); } } while (0); | |||
| 12672 | int encode = prefixq_and_encode(dst->encoding()); | |||
| 12673 | if (imm8 == 1) { | |||
| 12674 | emit_int16((unsigned char)0xD1, (0xD0 | encode)); | |||
| 12675 | } else { | |||
| 12676 | emit_int24((unsigned char)0xC1, (0xD0 | encode), imm8); | |||
| 12677 | } | |||
| 12678 | } | |||
| 12679 | ||||
| 12680 | void Assembler::rcrq(Register dst, int imm8) { | |||
| 12681 | assert(isShiftCount(imm8 >> 1), "illegal shift count")do { if (!(isShiftCount(imm8 >> 1))) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 12681, "assert(" "isShiftCount(imm8 >> 1)" ") failed" , "illegal shift count"); ::breakpoint(); } } while (0); | |||
| 12682 | int encode = prefixq_and_encode(dst->encoding()); | |||
| 12683 | if (imm8 == 1) { | |||
| 12684 | emit_int16((unsigned char)0xD1, (0xD8 | encode)); | |||
| 12685 | } else { | |||
| 12686 | emit_int24((unsigned char)0xC1, (0xD8 | encode), imm8); | |||
| 12687 | } | |||
| 12688 | } | |||
| 12689 | ||||
| 12690 | ||||
| 12691 | void Assembler::rorxq(Register dst, Register src, int imm8) { | |||
| 12692 | assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported")do { if (!(VM_Version::supports_bmi2())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 12692, "assert(" "VM_Version::supports_bmi2()" ") failed", "bit manipulation instructions not supported" ); ::breakpoint(); } } while (0); | |||
| 12693 | InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 12694 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes); | |||
| 12695 | emit_int24((unsigned char)0xF0, (0xC0 | encode), imm8); | |||
| 12696 | } | |||
| 12697 | ||||
| 12698 | void Assembler::rorxd(Register dst, Register src, int imm8) { | |||
| 12699 | assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported")do { if (!(VM_Version::supports_bmi2())) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 12699, "assert(" "VM_Version::supports_bmi2()" ") failed", "bit manipulation instructions not supported" ); ::breakpoint(); } } while (0); | |||
| 12700 | InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); | |||
| 12701 | int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes); | |||
| 12702 | emit_int24((unsigned char)0xF0, (0xC0 | encode), imm8); | |||
| 12703 | } | |||
| 12704 | ||||
| 12705 | #ifdef _LP641 | |||
| 12706 | void Assembler::salq(Address dst, int imm8) { | |||
| 12707 | InstructionMark im(this); | |||
| 12708 | assert(isShiftCount(imm8 >> 1), "illegal shift count")do { if (!(isShiftCount(imm8 >> 1))) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 12708, "assert(" "isShiftCount(imm8 >> 1)" ") failed" , "illegal shift count"); ::breakpoint(); } } while (0); | |||
| 12709 | if (imm8 == 1) { | |||
| 12710 | emit_int16(get_prefixq(dst), (unsigned char)0xD1); | |||
| 12711 | emit_operand(as_Register(4), dst); | |||
| 12712 | } | |||
| 12713 | else { | |||
| 12714 | emit_int16(get_prefixq(dst), (unsigned char)0xC1); | |||
| 12715 | emit_operand(as_Register(4), dst); | |||
| 12716 | emit_int8(imm8); | |||
| 12717 | } | |||
| 12718 | } | |||
| 12719 | ||||
| 12720 | void Assembler::salq(Address dst) { | |||
| 12721 | InstructionMark im(this); | |||
| 12722 | emit_int16(get_prefixq(dst), (unsigned char)0xD3); | |||
| 12723 | emit_operand(as_Register(4), dst); | |||
| 12724 | } | |||
| 12725 | ||||
| 12726 | void Assembler::salq(Register dst, int imm8) { | |||
| 12727 | assert(isShiftCount(imm8 >> 1), "illegal shift count")do { if (!(isShiftCount(imm8 >> 1))) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 12727, "assert(" "isShiftCount(imm8 >> 1)" ") failed" , "illegal shift count"); ::breakpoint(); } } while (0); | |||
| 12728 | int encode = prefixq_and_encode(dst->encoding()); | |||
| 12729 | if (imm8 == 1) { | |||
| 12730 | emit_int16((unsigned char)0xD1, (0xE0 | encode)); | |||
| 12731 | } else { | |||
| 12732 | emit_int24((unsigned char)0xC1, (0xE0 | encode), imm8); | |||
| 12733 | } | |||
| 12734 | } | |||
| 12735 | ||||
| 12736 | void Assembler::salq(Register dst) { | |||
| 12737 | int encode = prefixq_and_encode(dst->encoding()); | |||
| 12738 | emit_int16((unsigned char)0xD3, (0xE0 | encode)); | |||
| 12739 | } | |||
| 12740 | ||||
| 12741 | void Assembler::sarq(Address dst, int imm8) { | |||
| 12742 | InstructionMark im(this); | |||
| 12743 | assert(isShiftCount(imm8 >> 1), "illegal shift count")do { if (!(isShiftCount(imm8 >> 1))) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 12743, "assert(" "isShiftCount(imm8 >> 1)" ") failed" , "illegal shift count"); ::breakpoint(); } } while (0); | |||
| 12744 | if (imm8 == 1) { | |||
| 12745 | emit_int16(get_prefixq(dst), (unsigned char)0xD1); | |||
| 12746 | emit_operand(as_Register(7), dst); | |||
| 12747 | } | |||
| 12748 | else { | |||
| 12749 | emit_int16(get_prefixq(dst), (unsigned char)0xC1); | |||
| 12750 | emit_operand(as_Register(7), dst); | |||
| 12751 | emit_int8(imm8); | |||
| 12752 | } | |||
| 12753 | } | |||
| 12754 | ||||
| 12755 | void Assembler::sarq(Address dst) { | |||
| 12756 | InstructionMark im(this); | |||
| 12757 | emit_int16(get_prefixq(dst), (unsigned char)0xD3); | |||
| 12758 | emit_operand(as_Register(7), dst); | |||
| 12759 | } | |||
| 12760 | ||||
| 12761 | void Assembler::sarq(Register dst, int imm8) { | |||
| 12762 | assert(isShiftCount(imm8 >> 1), "illegal shift count")do { if (!(isShiftCount(imm8 >> 1))) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 12762, "assert(" "isShiftCount(imm8 >> 1)" ") failed" , "illegal shift count"); ::breakpoint(); } } while (0); | |||
| 12763 | int encode = prefixq_and_encode(dst->encoding()); | |||
| 12764 | if (imm8 == 1) { | |||
| 12765 | emit_int16((unsigned char)0xD1, (0xF8 | encode)); | |||
| 12766 | } else { | |||
| 12767 | emit_int24((unsigned char)0xC1, (0xF8 | encode), imm8); | |||
| 12768 | } | |||
| 12769 | } | |||
| 12770 | ||||
| 12771 | void Assembler::sarq(Register dst) { | |||
| 12772 | int encode = prefixq_and_encode(dst->encoding()); | |||
| 12773 | emit_int16((unsigned char)0xD3, (0xF8 | encode)); | |||
| 12774 | } | |||
| 12775 | #endif | |||
| 12776 | ||||
| 12777 | void Assembler::sbbq(Address dst, int32_t imm32) { | |||
| 12778 | InstructionMark im(this); | |||
| 12779 | prefixq(dst); | |||
| 12780 | emit_arith_operand(0x81, rbx, dst, imm32); | |||
| 12781 | } | |||
| 12782 | ||||
| 12783 | void Assembler::sbbq(Register dst, int32_t imm32) { | |||
| 12784 | (void) prefixq_and_encode(dst->encoding()); | |||
| 12785 | emit_arith(0x81, 0xD8, dst, imm32); | |||
| 12786 | } | |||
| 12787 | ||||
| 12788 | void Assembler::sbbq(Register dst, Address src) { | |||
| 12789 | InstructionMark im(this); | |||
| 12790 | emit_int16(get_prefixq(src, dst), 0x1B); | |||
| 12791 | emit_operand(dst, src); | |||
| 12792 | } | |||
| 12793 | ||||
| 12794 | void Assembler::sbbq(Register dst, Register src) { | |||
| 12795 | (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |||
| 12796 | emit_arith(0x1B, 0xC0, dst, src); | |||
| 12797 | } | |||
| 12798 | ||||
| 12799 | void Assembler::shlq(Register dst, int imm8) { | |||
| 12800 | assert(isShiftCount(imm8 >> 1), "illegal shift count")do { if (!(isShiftCount(imm8 >> 1))) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 12800, "assert(" "isShiftCount(imm8 >> 1)" ") failed" , "illegal shift count"); ::breakpoint(); } } while (0); | |||
| 12801 | int encode = prefixq_and_encode(dst->encoding()); | |||
| 12802 | if (imm8 == 1) { | |||
| 12803 | emit_int16((unsigned char)0xD1, (0xE0 | encode)); | |||
| 12804 | } else { | |||
| 12805 | emit_int24((unsigned char)0xC1, (0xE0 | encode), imm8); | |||
| 12806 | } | |||
| 12807 | } | |||
| 12808 | ||||
| 12809 | void Assembler::shlq(Register dst) { | |||
| 12810 | int encode = prefixq_and_encode(dst->encoding()); | |||
| 12811 | emit_int16((unsigned char)0xD3, (0xE0 | encode)); | |||
| 12812 | } | |||
| 12813 | ||||
| 12814 | void Assembler::shrq(Register dst, int imm8) { | |||
| 12815 | assert(isShiftCount(imm8 >> 1), "illegal shift count")do { if (!(isShiftCount(imm8 >> 1))) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 12815, "assert(" "isShiftCount(imm8 >> 1)" ") failed" , "illegal shift count"); ::breakpoint(); } } while (0); | |||
| 12816 | int encode = prefixq_and_encode(dst->encoding()); | |||
| 12817 | if (imm8 == 1) { | |||
| 12818 | emit_int16((unsigned char)0xD1, (0xE8 | encode)); | |||
| 12819 | } | |||
| 12820 | else { | |||
| 12821 | emit_int24((unsigned char)0xC1, (0xE8 | encode), imm8); | |||
| 12822 | } | |||
| 12823 | } | |||
| 12824 | ||||
| 12825 | void Assembler::shrq(Register dst) { | |||
| 12826 | int encode = prefixq_and_encode(dst->encoding()); | |||
| 12827 | emit_int16((unsigned char)0xD3, 0xE8 | encode); | |||
| 12828 | } | |||
| 12829 | ||||
| 12830 | void Assembler::shrq(Address dst) { | |||
| 12831 | InstructionMark im(this); | |||
| 12832 | emit_int16(get_prefixq(dst), (unsigned char)0xD3); | |||
| 12833 | emit_operand(as_Register(5), dst); | |||
| 12834 | } | |||
| 12835 | ||||
| 12836 | void Assembler::shrq(Address dst, int imm8) { | |||
| 12837 | InstructionMark im(this); | |||
| 12838 | assert(isShiftCount(imm8 >> 1), "illegal shift count")do { if (!(isShiftCount(imm8 >> 1))) { (*g_assert_poison ) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.cpp" , 12838, "assert(" "isShiftCount(imm8 >> 1)" ") failed" , "illegal shift count"); ::breakpoint(); } } while (0); | |||
| 12839 | if (imm8 == 1) { | |||
| 12840 | emit_int16(get_prefixq(dst), (unsigned char)0xD1); | |||
| 12841 | emit_operand(as_Register(5), dst); | |||
| 12842 | } | |||
| 12843 | else { | |||
| 12844 | emit_int16(get_prefixq(dst), (unsigned char)0xC1); | |||
| 12845 | emit_operand(as_Register(5), dst); | |||
| 12846 | emit_int8(imm8); | |||
| 12847 | } | |||
| 12848 | } | |||
| 12849 | ||||
| 12850 | void Assembler::subq(Address dst, int32_t imm32) { | |||
| 12851 | InstructionMark im(this); | |||
| 12852 | prefixq(dst); | |||
| 12853 | emit_arith_operand(0x81, rbp, dst, imm32); | |||
| 12854 | } | |||
| 12855 | ||||
| 12856 | void Assembler::subq(Address dst, Register src) { | |||
| 12857 | InstructionMark im(this); | |||
| 12858 | emit_int16(get_prefixq(dst, src), 0x29); | |||
| 12859 | emit_operand(src, dst); | |||
| 12860 | } | |||
| 12861 | ||||
| 12862 | void Assembler::subq(Register dst, int32_t imm32) { | |||
| 12863 | (void) prefixq_and_encode(dst->encoding()); | |||
| 12864 | emit_arith(0x81, 0xE8, dst, imm32); | |||
| 12865 | } | |||
| 12866 | ||||
| 12867 | // Force generation of a 4 byte immediate value even if it fits into 8bit | |||
| 12868 | void Assembler::subq_imm32(Register dst, int32_t imm32) { | |||
| 12869 | (void) prefixq_and_encode(dst->encoding()); | |||
| 12870 | emit_arith_imm32(0x81, 0xE8, dst, imm32); | |||
| 12871 | } | |||
| 12872 | ||||
| 12873 | void Assembler::subq(Register dst, Address src) { | |||
| 12874 | InstructionMark im(this); | |||
| 12875 | emit_int16(get_prefixq(src, dst), 0x2B); | |||
| 12876 | emit_operand(dst, src); | |||
| 12877 | } | |||
| 12878 | ||||
| 12879 | void Assembler::subq(Register dst, Register src) { | |||
| 12880 | (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |||
| 12881 | emit_arith(0x2B, 0xC0, dst, src); | |||
| 12882 | } | |||
| 12883 | ||||
| 12884 | void Assembler::testq(Address dst, int32_t imm32) { | |||
| 12885 | InstructionMark im(this); | |||
| 12886 | emit_int16(get_prefixq(dst), (unsigned char)0xF7); | |||
| 12887 | emit_operand(as_Register(0), dst); | |||
| 12888 | emit_int32(imm32); | |||
| 12889 | } | |||
| 12890 | ||||
| 12891 | void Assembler::testq(Register dst, int32_t imm32) { | |||
| 12892 | // not using emit_arith because test | |||
| 12893 | // doesn't support sign-extension of | |||
| 12894 | // 8bit operands | |||
| 12895 | int encode = dst->encoding(); | |||
| 12896 | encode = prefixq_and_encode(encode); | |||
| 12897 | emit_int16((unsigned char)0xF7, (0xC0 | encode)); | |||
| 12898 | emit_int32(imm32); | |||
| 12899 | } | |||
| 12900 | ||||
| 12901 | void Assembler::testq(Register dst, Register src) { | |||
| 12902 | (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |||
| 12903 | emit_arith(0x85, 0xC0, dst, src); | |||
| 12904 | } | |||
| 12905 | ||||
| 12906 | void Assembler::testq(Register dst, Address src) { | |||
| 12907 | InstructionMark im(this); | |||
| 12908 | emit_int16(get_prefixq(src, dst), (unsigned char)0x85); | |||
| 12909 | emit_operand(dst, src); | |||
| 12910 | } | |||
| 12911 | ||||
| 12912 | void Assembler::xaddq(Address dst, Register src) { | |||
| 12913 | InstructionMark im(this); | |||
| 12914 | emit_int24(get_prefixq(dst, src), 0x0F, (unsigned char)0xC1); | |||
| 12915 | emit_operand(src, dst); | |||
| 12916 | } | |||
| 12917 | ||||
| 12918 | void Assembler::xchgq(Register dst, Address src) { | |||
| 12919 | InstructionMark im(this); | |||
| 12920 | emit_int16(get_prefixq(src, dst), (unsigned char)0x87); | |||
| 12921 | emit_operand(dst, src); | |||
| 12922 | } | |||
| 12923 | ||||
| 12924 | void Assembler::xchgq(Register dst, Register src) { | |||
| 12925 | int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |||
| 12926 | emit_int16((unsigned char)0x87, (0xc0 | encode)); | |||
| 12927 | } | |||
| 12928 | ||||
| 12929 | void Assembler::xorq(Register dst, Register src) { | |||
| 12930 | (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |||
| 12931 | emit_arith(0x33, 0xC0, dst, src); | |||
| 12932 | } | |||
| 12933 | ||||
| 12934 | void Assembler::xorq(Register dst, Address src) { | |||
| 12935 | InstructionMark im(this); | |||
| 12936 | emit_int16(get_prefixq(src, dst), 0x33); | |||
| 12937 | emit_operand(dst, src); | |||
| 12938 | } | |||
| 12939 | ||||
| 12940 | void Assembler::xorq(Register dst, int32_t imm32) { | |||
| 12941 | (void) prefixq_and_encode(dst->encoding()); | |||
| 12942 | emit_arith(0x81, 0xF0, dst, imm32); | |||
| 12943 | } | |||
| 12944 | ||||
| 12945 | void Assembler::xorq(Address dst, int32_t imm32) { | |||
| 12946 | InstructionMark im(this); | |||
| 12947 | prefixq(dst); | |||
| ||||
| 12948 | emit_arith_operand(0x81, as_Register(6), dst, imm32); | |||
| 12949 | } | |||
| 12950 | ||||
| 12951 | void Assembler::xorq(Address dst, Register src) { | |||
| 12952 | InstructionMark im(this); | |||
| 12953 | emit_int16(get_prefixq(dst, src), 0x31); | |||
| 12954 | emit_operand(src, dst); | |||
| 12955 | } | |||
| 12956 | ||||
| 12957 | #endif // !LP64 | |||
| 12958 | ||||
| 12959 | void InstructionAttr::set_address_attributes(int tuple_type, int input_size_in_bits) { | |||
| 12960 | if (VM_Version::supports_evex()) { | |||
| 12961 | _tuple_type = tuple_type; | |||
| 12962 | _input_size_in_bits = input_size_in_bits; | |||
| 12963 | } | |||
| 12964 | } |