/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler

Bug Summary

File:	jdk/src/hotspot/cpu/x86/assembler_x86.hpp
Warning:	line 233, column 5 Called C++ object pointer is null

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name macroAssembler_x86_aes.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model pic -pic-level 2 -mthread-model posix -fno-delete-null-pointer-checks -mframe-pointer=all -relaxed-aliasing -fmath-errno -fno-rounding-math -masm-verbose -mconstructor-aliases -munwind-tables -target-cpu x86-64 -dwarf-column-info -fno-split-dwarf-inlining -debugger-tuning=gdb -resource-dir /usr/lib/llvm-10/lib/clang/10.0.0 -I /home/daniel/Projects/java/jdk/build/linux-x86_64-server-fastdebug/hotspot/variant-server/libjvm/objs/precompiled -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -D __STDC_CONSTANT_MACROS -D _GNU_SOURCE -D _REENTRANT -D LIBC=gnu -D LINUX -D VM_LITTLE_ENDIAN -D _LP64=1 -D ASSERT -D CHECK_UNHANDLED_OOPS -D TARGET_ARCH_x86 -D INCLUDE_SUFFIX_OS=_linux -D INCLUDE_SUFFIX_CPU=_x86 -D INCLUDE_SUFFIX_COMPILER=_gcc -D TARGET_COMPILER_gcc -D AMD64 -D HOTSPOT_LIB_ARCH="amd64" -D COMPILER1 -D COMPILER2 -I /home/daniel/Projects/java/jdk/build/linux-x86_64-server-fastdebug/hotspot/variant-server/gensrc/adfiles -I /home/daniel/Projects/java/jdk/src/hotspot/share -I /home/daniel/Projects/java/jdk/src/hotspot/os/linux -I /home/daniel/Projects/java/jdk/src/hotspot/os/posix -I /home/daniel/Projects/java/jdk/src/hotspot/cpu/x86 -I /home/daniel/Projects/java/jdk/src/hotspot/os_cpu/linux_x86 -I /home/daniel/Projects/java/jdk/build/linux-x86_64-server-fastdebug/hotspot/variant-server/gensrc -I /home/daniel/Projects/java/jdk/src/hotspot/share/precompiled -I /home/daniel/Projects/java/jdk/src/hotspot/share/include -I /home/daniel/Projects/java/jdk/src/hotspot/os/posix/include -I /home/daniel/Projects/java/jdk/build/linux-x86_64-server-fastdebug/support/modules_include/java.base -I /home/daniel/Projects/java/jdk/build/linux-x86_64-server-fastdebug/support/modules_include/java.base/linux -I /home/daniel/Projects/java/jdk/src/java.base/share/native/libjimage -I /home/daniel/Projects/java/jdk/build/linux-x86_64-server-fastdebug/hotspot/variant-server/gensrc/adfiles -I /home/daniel/Projects/java/jdk/src/hotspot/share -I /home/daniel/Projects/java/jdk/src/hotspot/os/linux -I /home/daniel/Projects/java/jdk/src/hotspot/os/posix -I /home/daniel/Projects/java/jdk/src/hotspot/cpu/x86 -I /home/daniel/Projects/java/jdk/src/hotspot/os_cpu/linux_x86 -I /home/daniel/Projects/java/jdk/build/linux-x86_64-server-fastdebug/hotspot/variant-server/gensrc -D _FORTIFY_SOURCE=2 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.5.0/../../../../include/c++/7.5.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.5.0/../../../../include/x86_64-linux-gnu/c++/7.5.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.5.0/../../../../include/x86_64-linux-gnu/c++/7.5.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.5.0/../../../../include/c++/7.5.0/backward -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-10/lib/clang/10.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O3 -Wno-format-zero-length -Wno-unused-parameter -Wno-unused -Wno-parentheses -Wno-comment -Wno-unknown-pragmas -Wno-address -Wno-delete-non-virtual-dtor -Wno-char-subscripts -Wno-array-bounds -Wno-int-in-bool-context -Wno-ignored-qualifiers -Wno-missing-field-initializers -Wno-implicit-fallthrough -Wno-empty-body -Wno-strict-overflow -Wno-sequence-point -Wno-maybe-uninitialized -Wno-misleading-indentation -Wno-cast-function-type -Wno-shift-negative-value -std=c++14 -fdeprecated-macro -fdebug-compilation-dir /home/daniel/Projects/java/jdk/make/hotspot -ferror-limit 19 -fmessage-length 0 -fvisibility hidden -stack-protector 1 -fno-rtti -fgnuc-version=4.2.1 -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -faddrsig -o /home/daniel/Projects/java/scan/2021-12-21-193737-8510-1 -x c++ /home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/macroAssembler_x86_aes.cpp

/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/macroAssembler_x86_aes.cpp

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1/*
2* Copyright (c) 2019, 2021, Intel Corporation. All rights reserved.
3*
4* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5*
6* This code is free software; you can redistribute it and/or modify it
7* under the terms of the GNU General Public License version 2 only, as
8* published by the Free Software Foundation.
9*
10* This code is distributed in the hope that it will be useful, but WITHOUT
11* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12* FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
13* version 2 for more details (a copy is included in the LICENSE file that
14* accompanied this code).
15*
16* You should have received a copy of the GNU General Public License version
17* 2 along with this work; if not, write to the Free Software Foundation,
18* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19*
20* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21* or visit www.oracle.com if you need additional information or have any
22* questions.
23*
24*/

26#include "precompiled.hpp"
27#include "asm/assembler.hpp"
28#include "asm/assembler.inline.hpp"
29#include "runtime/stubRoutines.hpp"
30#include "macroAssembler_x86.hpp"

32#ifdef _LP641

34void MacroAssembler::roundEnc(XMMRegister key, int rnum) {
  for (int xmm_reg_no = 0; xmm_reg_no <=rnum; xmm_reg_no++) {
    vaesenc(as_XMMRegister(xmm_reg_no), as_XMMRegister(xmm_reg_no), key, Assembler::AVX_512bit);
  }
38}

40void MacroAssembler::lastroundEnc(XMMRegister key, int rnum) {
  for (int xmm_reg_no = 0; xmm_reg_no <=rnum; xmm_reg_no++) {
    vaesenclast(as_XMMRegister(xmm_reg_no), as_XMMRegister(xmm_reg_no), key, Assembler::AVX_512bit);
  }
44}

46void MacroAssembler::roundDec(XMMRegister key, int rnum) {
  for (int xmm_reg_no = 0; xmm_reg_no <=rnum; xmm_reg_no++) {
    vaesdec(as_XMMRegister(xmm_reg_no), as_XMMRegister(xmm_reg_no), key, Assembler::AVX_512bit);
  }
50}

52void MacroAssembler::lastroundDec(XMMRegister key, int rnum) {
  for (int xmm_reg_no = 0; xmm_reg_no <=rnum; xmm_reg_no++) {
    vaesdeclast(as_XMMRegister(xmm_reg_no), as_XMMRegister(xmm_reg_no), key, Assembler::AVX_512bit);
  }
56}

58// Load key and shuffle operation
59void MacroAssembler::ev_load_key(XMMRegister xmmdst, Register key, int offset, XMMRegister xmm_shuf_mask=NULL__null) {
  movdqu(xmmdst, Address(key, offset));
  if (xmm_shuf_mask != NULL__null) {
      pshufb(xmmdst, xmm_shuf_mask);
  } else {
     pshufb(xmmdst, ExternalAddress(StubRoutines::x86::key_shuffle_mask_addr()));
  }
 evshufi64x2(xmmdst, xmmdst, xmmdst, 0x0, Assembler::AVX_512bit);
67}

69// AES-ECB Encrypt Operation
70void MacroAssembler::aesecb_encrypt(Register src_addr, Register dest_addr, Register key, Register len) {

  const Register pos = rax;
  const Register rounds = r12;

  Label NO_PARTS, LOOP, Loop_start, LOOP2, AES192, END_LOOP, AES256, REMAINDER, LAST2, END, KEY_192, KEY_256, EXIT;
  push(r13);
  push(r12);

  // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
  // context for the registers used, where all instructions below are using 128-bit mode
  // On EVEX without VL and BW, these instructions will all be AVX.
  if (VM_Version::supports_avx512vlbw()) {
     movl(rax, 0xffff);
     kmovql(k1, rax);
  }
  push(len); // Save
  push(rbx);

  vzeroupper();

  xorptr(pos, pos);

  // Calculate number of rounds based on key length(128, 192, 256):44 for 10-rounds, 52 for 12-rounds, 60 for 14-rounds
  movl(rounds, Address(key, arrayOopDesc::length_offset_in_bytes() - arrayOopDesc::base_offset_in_bytes(T_INT)));

  // Load Key shuf mask
  const XMMRegister xmm_key_shuf_mask = xmm31;  // used temporarily to swap key bytes up front
  movdqu(xmm_key_shuf_mask, ExternalAddress(StubRoutines::x86::key_shuffle_mask_addr()));

  // Load and shuffle key based on number of rounds
  ev_load_key(xmm8, key, 0 * 16, xmm_key_shuf_mask);
  ev_load_key(xmm9, key, 1 * 16, xmm_key_shuf_mask);
  ev_load_key(xmm10, key, 2 * 16, xmm_key_shuf_mask);
  ev_load_key(xmm23, key, 3 * 16, xmm_key_shuf_mask);
  ev_load_key(xmm12, key, 4 * 16, xmm_key_shuf_mask);
  ev_load_key(xmm13, key, 5 * 16, xmm_key_shuf_mask);
  ev_load_key(xmm14, key, 6 * 16, xmm_key_shuf_mask);
  ev_load_key(xmm15, key, 7 * 16, xmm_key_shuf_mask);
  ev_load_key(xmm16, key, 8 * 16, xmm_key_shuf_mask);
  ev_load_key(xmm17, key, 9 * 16, xmm_key_shuf_mask);
  ev_load_key(xmm24, key, 10 * 16, xmm_key_shuf_mask);
  cmpl(rounds, 52);
  jcc(Assembler::greaterEqual, KEY_192);
  jmp(Loop_start);

  bind(KEY_192);
  ev_load_key(xmm19, key, 11 * 16, xmm_key_shuf_mask);
  ev_load_key(xmm20, key, 12 * 16, xmm_key_shuf_mask);
  cmpl(rounds, 60);
  jcc(Assembler::equal, KEY_256);
  jmp(Loop_start);

  bind(KEY_256);
  ev_load_key(xmm21, key, 13 * 16, xmm_key_shuf_mask);
  ev_load_key(xmm22, key, 14 * 16, xmm_key_shuf_mask);

  bind(Loop_start);
  movq(rbx, len);
  // Divide length by 16 to convert it to number of blocks
  shrq(len, 4);
  shlq(rbx, 60);
  jcc(Assembler::equal, NO_PARTS);
  addq(len, 1);
  // Check if number of blocks is greater than or equal to 32
  // If true, 512 bytes are processed at a time (code marked by label LOOP)
  // If not, 16 bytes are processed (code marked by REMAINDER label)
  bind(NO_PARTS);
  movq(rbx, len);
  shrq(len, 5);
  jcc(Assembler::equal, REMAINDER);
  movl(r13, len);
  // Compute number of blocks that will be processed 512 bytes at a time
  // Subtract this from the total number of blocks which will then be processed by REMAINDER loop
  shlq(r13, 5);
  subq(rbx, r13);
  //Begin processing 512 bytes
  bind(LOOP);
  // Move 64 bytes of PT data into a zmm register, as a result 512 bytes of PT loaded in zmm0-7
  evmovdquq(xmm0, Address(src_addr, pos, Address::times_1, 0 * 64), Assembler::AVX_512bit);
  evmovdquq(xmm1, Address(src_addr, pos, Address::times_1, 1 * 64), Assembler::AVX_512bit);
  evmovdquq(xmm2, Address(src_addr, pos, Address::times_1, 2 * 64), Assembler::AVX_512bit);
  evmovdquq(xmm3, Address(src_addr, pos, Address::times_1, 3 * 64), Assembler::AVX_512bit);
  evmovdquq(xmm4, Address(src_addr, pos, Address::times_1, 4 * 64), Assembler::AVX_512bit);
  evmovdquq(xmm5, Address(src_addr, pos, Address::times_1, 5 * 64), Assembler::AVX_512bit);
  evmovdquq(xmm6, Address(src_addr, pos, Address::times_1, 6 * 64), Assembler::AVX_512bit);
  evmovdquq(xmm7, Address(src_addr, pos, Address::times_1, 7 * 64), Assembler::AVX_512bit);
  // Xor with the first round key
  evpxorq(xmm0, xmm0, xmm8, Assembler::AVX_512bit);
  evpxorq(xmm1, xmm1, xmm8, Assembler::AVX_512bit);
  evpxorq(xmm2, xmm2, xmm8, Assembler::AVX_512bit);
  evpxorq(xmm3, xmm3, xmm8, Assembler::AVX_512bit);
  evpxorq(xmm4, xmm4, xmm8, Assembler::AVX_512bit);
  evpxorq(xmm5, xmm5, xmm8, Assembler::AVX_512bit);
  evpxorq(xmm6, xmm6, xmm8, Assembler::AVX_512bit);
  evpxorq(xmm7, xmm7, xmm8, Assembler::AVX_512bit);
  // 9 Aes encode round operations
  roundEnc(xmm9,  7);
  roundEnc(xmm10, 7);
  roundEnc(xmm23, 7);
  roundEnc(xmm12, 7);
  roundEnc(xmm13, 7);
  roundEnc(xmm14, 7);
  roundEnc(xmm15, 7);
  roundEnc(xmm16, 7);
  roundEnc(xmm17, 7);
  cmpl(rounds, 52);
  jcc(Assembler::aboveEqual, AES192);
  // Aesenclast round operation for keysize = 128
  lastroundEnc(xmm24, 7);
  jmp(END_LOOP);
  //Additional 2 rounds of Aesenc operation for keysize = 192
  bind(AES192);
  roundEnc(xmm24, 7);
  roundEnc(xmm19, 7);
  cmpl(rounds, 60);
  jcc(Assembler::aboveEqual, AES256);
  // Aesenclast round for keysize = 192
  lastroundEnc(xmm20, 7);
  jmp(END_LOOP);
  // 2 rounds of Aesenc operation and Aesenclast for keysize = 256
  bind(AES256);
  roundEnc(xmm20, 7);
  roundEnc(xmm21, 7);
  lastroundEnc(xmm22, 7);

  bind(END_LOOP);
  // Move 512 bytes of CT to destination
  evmovdquq(Address(dest_addr, pos, Address::times_1, 0 * 64), xmm0, Assembler::AVX_512bit);
  evmovdquq(Address(dest_addr, pos, Address::times_1, 1 * 64), xmm1, Assembler::AVX_512bit);
  evmovdquq(Address(dest_addr, pos, Address::times_1, 2 * 64), xmm2, Assembler::AVX_512bit);
  evmovdquq(Address(dest_addr, pos, Address::times_1, 3 * 64), xmm3, Assembler::AVX_512bit);
  evmovdquq(Address(dest_addr, pos, Address::times_1, 4 * 64), xmm4, Assembler::AVX_512bit);
  evmovdquq(Address(dest_addr, pos, Address::times_1, 5 * 64), xmm5, Assembler::AVX_512bit);
  evmovdquq(Address(dest_addr, pos, Address::times_1, 6 * 64), xmm6, Assembler::AVX_512bit);
  evmovdquq(Address(dest_addr, pos, Address::times_1, 7 * 64), xmm7, Assembler::AVX_512bit);

  addq(pos, 512);
  decq(len);
  jcc(Assembler::notEqual, LOOP);

  bind(REMAINDER);
  vzeroupper();
  cmpq(rbx, 0);
  jcc(Assembler::equal, END);
  // Process 16 bytes at a time
  bind(LOOP2);
  movdqu(xmm1, Address(src_addr, pos, Address::times_1, 0));
  vpxor(xmm1, xmm1, xmm8, Assembler::AVX_128bit);
  // xmm2 contains shuffled key for Aesenclast operation.
  vmovdqu(xmm2, xmm24);

  vaesenc(xmm1, xmm1, xmm9, Assembler::AVX_128bit);
  vaesenc(xmm1, xmm1, xmm10, Assembler::AVX_128bit);
  vaesenc(xmm1, xmm1, xmm23, Assembler::AVX_128bit);
  vaesenc(xmm1, xmm1, xmm12, Assembler::AVX_128bit);
  vaesenc(xmm1, xmm1, xmm13, Assembler::AVX_128bit);
  vaesenc(xmm1, xmm1, xmm14, Assembler::AVX_128bit);
  vaesenc(xmm1, xmm1, xmm15, Assembler::AVX_128bit);
  vaesenc(xmm1, xmm1, xmm16, Assembler::AVX_128bit);
  vaesenc(xmm1, xmm1, xmm17, Assembler::AVX_128bit);

  cmpl(rounds, 52);
  jcc(Assembler::below, LAST2);
  vmovdqu(xmm2, xmm20);
  vaesenc(xmm1, xmm1, xmm24, Assembler::AVX_128bit);
  vaesenc(xmm1, xmm1, xmm19, Assembler::AVX_128bit);
  cmpl(rounds, 60);
  jcc(Assembler::below, LAST2);
  vmovdqu(xmm2, xmm22);
  vaesenc(xmm1, xmm1, xmm20, Assembler::AVX_128bit);
  vaesenc(xmm1, xmm1, xmm21, Assembler::AVX_128bit);

  bind(LAST2);
  // Aesenclast round
  vaesenclast(xmm1, xmm1, xmm2, Assembler::AVX_128bit);
  // Write 16 bytes of CT to destination
  movdqu(Address(dest_addr, pos, Address::times_1, 0), xmm1);
  addq(pos, 16);
  decq(rbx);
  jcc(Assembler::notEqual, LOOP2);

  bind(END);
  // Zero out the round keys
  evpxorq(xmm8, xmm8, xmm8, Assembler::AVX_512bit);
  evpxorq(xmm9, xmm9, xmm9, Assembler::AVX_512bit);
  evpxorq(xmm10, xmm10, xmm10, Assembler::AVX_512bit);
  evpxorq(xmm23, xmm23, xmm23, Assembler::AVX_512bit);
  evpxorq(xmm12, xmm12, xmm12, Assembler::AVX_512bit);
  evpxorq(xmm13, xmm13, xmm13, Assembler::AVX_512bit);
  evpxorq(xmm14, xmm14, xmm14, Assembler::AVX_512bit);
  evpxorq(xmm15, xmm15, xmm15, Assembler::AVX_512bit);
  evpxorq(xmm16, xmm16, xmm16, Assembler::AVX_512bit);
  evpxorq(xmm17, xmm17, xmm17, Assembler::AVX_512bit);
  evpxorq(xmm24, xmm24, xmm24, Assembler::AVX_512bit);
  cmpl(rounds, 44);
  jcc(Assembler::belowEqual, EXIT);
  evpxorq(xmm19, xmm19, xmm19, Assembler::AVX_512bit);
  evpxorq(xmm20, xmm20, xmm20, Assembler::AVX_512bit);
  cmpl(rounds, 52);
  jcc(Assembler::belowEqual, EXIT);
  evpxorq(xmm21, xmm21, xmm21, Assembler::AVX_512bit);
  evpxorq(xmm22, xmm22, xmm22, Assembler::AVX_512bit);
  bind(EXIT);
  pop(rbx);
  pop(rax); // return length
  pop(r12);
  pop(r13);
278}

280// AES-ECB Decrypt Operation
281void MacroAssembler::aesecb_decrypt(Register src_addr, Register dest_addr, Register key, Register len)  {

  Label NO_PARTS, LOOP, Loop_start, LOOP2, AES192, END_LOOP, AES256, REMAINDER, LAST2, END, KEY_192, KEY_256, EXIT;
  const Register pos = rax;
  const Register rounds = r12;
  push(r13);
  push(r12);

  // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
  // context for the registers used, where all instructions below are using 128-bit mode
  // On EVEX without VL and BW, these instructions will all be AVX.
  if (VM_Version::supports_avx512vlbw()) {
     movl(rax, 0xffff);
     kmovql(k1, rax);
  }

  push(len); // Save
  push(rbx);

  vzeroupper();

  xorptr(pos, pos);
  // Calculate number of rounds i.e. based on key length(128, 192, 256):44 for 10-rounds, 52 for 12-rounds, 60 for 14-rounds
  movl(rounds, Address(key, arrayOopDesc::length_offset_in_bytes() - arrayOopDesc::base_offset_in_bytes(T_INT)));

  // Load Key shuf mask
  const XMMRegister xmm_key_shuf_mask = xmm31;  // used temporarily to swap key bytes up front
  movdqu(xmm_key_shuf_mask, ExternalAddress(StubRoutines::x86::key_shuffle_mask_addr()));

  // Load and shuffle round keys. The java expanded key ordering is rotated one position in decryption.
  // So the first round key is loaded from 1*16 here and last round key is loaded from 0*16
  ev_load_key(xmm9,  key, 1 * 16, xmm_key_shuf_mask);
  ev_load_key(xmm10, key, 2 * 16, xmm_key_shuf_mask);
  ev_load_key(xmm11, key, 3 * 16, xmm_key_shuf_mask);
  ev_load_key(xmm12, key, 4 * 16, xmm_key_shuf_mask);
  ev_load_key(xmm13, key, 5 * 16, xmm_key_shuf_mask);
  ev_load_key(xmm14, key, 6 * 16, xmm_key_shuf_mask);
  ev_load_key(xmm15, key, 7 * 16, xmm_key_shuf_mask);
  ev_load_key(xmm16, key, 8 * 16, xmm_key_shuf_mask);
  ev_load_key(xmm17, key, 9 * 16, xmm_key_shuf_mask);
  ev_load_key(xmm18, key, 10 * 16, xmm_key_shuf_mask);
  ev_load_key(xmm27, key, 0 * 16, xmm_key_shuf_mask);
  cmpl(rounds, 52);
  jcc(Assembler::greaterEqual, KEY_192);
  jmp(Loop_start);

  bind(KEY_192);
  ev_load_key(xmm19, key, 11 * 16, xmm_key_shuf_mask);
  ev_load_key(xmm20, key, 12 * 16, xmm_key_shuf_mask);
  cmpl(rounds, 60);
  jcc(Assembler::equal, KEY_256);
  jmp(Loop_start);

  bind(KEY_256);
  ev_load_key(xmm21, key, 13 * 16, xmm_key_shuf_mask);
  ev_load_key(xmm22, key, 14 * 16, xmm_key_shuf_mask);
  bind(Loop_start);
  movq(rbx, len);
  // Convert input length to number of blocks
  shrq(len, 4);
  shlq(rbx, 60);
  jcc(Assembler::equal, NO_PARTS);
  addq(len, 1);
  // Check if number of blocks is greater than/ equal to 32
  // If true, blocks then 512 bytes are processed at a time (code marked by label LOOP)
  // If not, 16 bytes are processed (code marked by label REMAINDER)
  bind(NO_PARTS);
  movq(rbx, len);
  shrq(len, 5);
  jcc(Assembler::equal, REMAINDER);
  movl(r13, len);
  // Compute number of blocks that will be processed as 512 bytes at a time
  // Subtract this from the total number of blocks, which will then be processed by REMAINDER loop.
  shlq(r13, 5);
  subq(rbx, r13);

  bind(LOOP);
  // Move 64 bytes of CT data into a zmm register, as a result 512 bytes of CT loaded in zmm0-7
  evmovdquq(xmm0, Address(src_addr, pos, Address::times_1, 0 * 64), Assembler::AVX_512bit);
  evmovdquq(xmm1, Address(src_addr, pos, Address::times_1, 1 * 64), Assembler::AVX_512bit);
  evmovdquq(xmm2, Address(src_addr, pos, Address::times_1, 2 * 64), Assembler::AVX_512bit);
  evmovdquq(xmm3, Address(src_addr, pos, Address::times_1, 3 * 64), Assembler::AVX_512bit);
  evmovdquq(xmm4, Address(src_addr, pos, Address::times_1, 4 * 64), Assembler::AVX_512bit);
  evmovdquq(xmm5, Address(src_addr, pos, Address::times_1, 5 * 64), Assembler::AVX_512bit);
  evmovdquq(xmm6, Address(src_addr, pos, Address::times_1, 6 * 64), Assembler::AVX_512bit);
  evmovdquq(xmm7, Address(src_addr, pos, Address::times_1, 7 * 64), Assembler::AVX_512bit);
  // Xor with the first round key
  evpxorq(xmm0, xmm0, xmm9, Assembler::AVX_512bit);
  evpxorq(xmm1, xmm1, xmm9, Assembler::AVX_512bit);
  evpxorq(xmm2, xmm2, xmm9, Assembler::AVX_512bit);
  evpxorq(xmm3, xmm3, xmm9, Assembler::AVX_512bit);
  evpxorq(xmm4, xmm4, xmm9, Assembler::AVX_512bit);
  evpxorq(xmm5, xmm5, xmm9, Assembler::AVX_512bit);
  evpxorq(xmm6, xmm6, xmm9, Assembler::AVX_512bit);
  evpxorq(xmm7, xmm7, xmm9, Assembler::AVX_512bit);
  // 9 rounds of Aesdec
  roundDec(xmm10, 7);
  roundDec(xmm11, 7);
  roundDec(xmm12, 7);
  roundDec(xmm13, 7);
  roundDec(xmm14, 7);
  roundDec(xmm15, 7);
  roundDec(xmm16, 7);
  roundDec(xmm17, 7);
  roundDec(xmm18, 7);
  cmpl(rounds, 52);
  jcc(Assembler::aboveEqual, AES192);
  // Aesdeclast round for keysize = 128
  lastroundDec(xmm27, 7);
  jmp(END_LOOP);

  bind(AES192);
  // 2 Additional rounds for keysize = 192
  roundDec(xmm19, 7);
  roundDec(xmm20, 7);
  cmpl(rounds, 60);
  jcc(Assembler::aboveEqual, AES256);
  // Aesdeclast round for keysize = 192
  lastroundDec(xmm27, 7);
  jmp(END_LOOP);
  bind(AES256);
  // 2 Additional rounds and Aesdeclast for keysize = 256
  roundDec(xmm21, 7);
  roundDec(xmm22, 7);
  lastroundDec(xmm27, 7);

  bind(END_LOOP);
  // Write 512 bytes of PT to the destination
  evmovdquq(Address(dest_addr, pos, Address::times_1, 0 * 64), xmm0, Assembler::AVX_512bit);
  evmovdquq(Address(dest_addr, pos, Address::times_1, 1 * 64), xmm1, Assembler::AVX_512bit);
  evmovdquq(Address(dest_addr, pos, Address::times_1, 2 * 64), xmm2, Assembler::AVX_512bit);
  evmovdquq(Address(dest_addr, pos, Address::times_1, 3 * 64), xmm3, Assembler::AVX_512bit);
  evmovdquq(Address(dest_addr, pos, Address::times_1, 4 * 64), xmm4, Assembler::AVX_512bit);
  evmovdquq(Address(dest_addr, pos, Address::times_1, 5 * 64), xmm5, Assembler::AVX_512bit);
  evmovdquq(Address(dest_addr, pos, Address::times_1, 6 * 64), xmm6, Assembler::AVX_512bit);
  evmovdquq(Address(dest_addr, pos, Address::times_1, 7 * 64), xmm7, Assembler::AVX_512bit);

  addq(pos, 512);
  decq(len);
  jcc(Assembler::notEqual, LOOP);

  bind(REMAINDER);
  vzeroupper();
  cmpq(rbx, 0);
  jcc(Assembler::equal, END);
  // Process 16 bytes at a time
  bind(LOOP2);
  movdqu(xmm1, Address(src_addr, pos, Address::times_1, 0));
  vpxor(xmm1, xmm1, xmm9, Assembler::AVX_128bit);
  // xmm2 contains shuffled key for Aesdeclast operation.
  vmovdqu(xmm2, xmm27);

  vaesdec(xmm1, xmm1, xmm10, Assembler::AVX_128bit);
  vaesdec(xmm1, xmm1, xmm11, Assembler::AVX_128bit);
  vaesdec(xmm1, xmm1, xmm12, Assembler::AVX_128bit);
  vaesdec(xmm1, xmm1, xmm13, Assembler::AVX_128bit);
  vaesdec(xmm1, xmm1, xmm14, Assembler::AVX_128bit);
  vaesdec(xmm1, xmm1, xmm15, Assembler::AVX_128bit);
  vaesdec(xmm1, xmm1, xmm16, Assembler::AVX_128bit);
  vaesdec(xmm1, xmm1, xmm17, Assembler::AVX_128bit);
  vaesdec(xmm1, xmm1, xmm18, Assembler::AVX_128bit);

  cmpl(rounds, 52);
  jcc(Assembler::below, LAST2);
  vaesdec(xmm1, xmm1, xmm19, Assembler::AVX_128bit);
  vaesdec(xmm1, xmm1, xmm20, Assembler::AVX_128bit);
  cmpl(rounds, 60);
  jcc(Assembler::below, LAST2);
  vaesdec(xmm1, xmm1, xmm21, Assembler::AVX_128bit);
  vaesdec(xmm1, xmm1, xmm22, Assembler::AVX_128bit);

  bind(LAST2);
  // Aesdeclast round
  vaesdeclast(xmm1, xmm1, xmm2, Assembler::AVX_128bit);
  // Write 16 bytes of PT to destination
  movdqu(Address(dest_addr, pos, Address::times_1, 0), xmm1);
  addq(pos, 16);
  decq(rbx);
  jcc(Assembler::notEqual, LOOP2);

  bind(END);
  // Zero out the round keys
  evpxorq(xmm8, xmm8, xmm8, Assembler::AVX_512bit);
  evpxorq(xmm9, xmm9, xmm9, Assembler::AVX_512bit);
  evpxorq(xmm10, xmm10, xmm10, Assembler::AVX_512bit);
  evpxorq(xmm11, xmm11, xmm11, Assembler::AVX_512bit);
  evpxorq(xmm12, xmm12, xmm12, Assembler::AVX_512bit);
  evpxorq(xmm13, xmm13, xmm13, Assembler::AVX_512bit);
  evpxorq(xmm14, xmm14, xmm14, Assembler::AVX_512bit);
  evpxorq(xmm15, xmm15, xmm15, Assembler::AVX_512bit);
  evpxorq(xmm16, xmm16, xmm16, Assembler::AVX_512bit);
  evpxorq(xmm17, xmm17, xmm17, Assembler::AVX_512bit);
  evpxorq(xmm18, xmm18, xmm18, Assembler::AVX_512bit);
  evpxorq(xmm27, xmm27, xmm27, Assembler::AVX_512bit);
  cmpl(rounds, 44);
  jcc(Assembler::belowEqual, EXIT);
  evpxorq(xmm19, xmm19, xmm19, Assembler::AVX_512bit);
  evpxorq(xmm20, xmm20, xmm20, Assembler::AVX_512bit);
  cmpl(rounds, 52);
  jcc(Assembler::belowEqual, EXIT);
  evpxorq(xmm21, xmm21, xmm21, Assembler::AVX_512bit);
  evpxorq(xmm22, xmm22, xmm22, Assembler::AVX_512bit);
  bind(EXIT);
  pop(rbx);
  pop(rax); // return length
  pop(r12);
  pop(r13);
488}

490// Multiply 128 x 128 bits, using 4 pclmulqdq operations
491void MacroAssembler::schoolbookAAD(int i, Register htbl, XMMRegister data,
  XMMRegister tmp0, XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3) {
  movdqu(xmm15, Address(htbl, i * 16));
  vpclmulhqlqdq(tmp3, data, xmm15); // 0x01
  vpxor(tmp2, tmp2, tmp3, Assembler::AVX_128bit);
  vpclmulldq(tmp3, data, xmm15); // 0x00
  vpxor(tmp0, tmp0, tmp3, Assembler::AVX_128bit);
  vpclmulhdq(tmp3, data, xmm15); // 0x11
  vpxor(tmp1, tmp1, tmp3, Assembler::AVX_128bit);
  vpclmullqhqdq(tmp3, data, xmm15); // 0x10
  vpxor(tmp2, tmp2, tmp3, Assembler::AVX_128bit);
502}

504// Multiply two 128 bit numbers resulting in a 256 bit value
505// Result of the multiplication followed by reduction stored in state
506void MacroAssembler::gfmul(XMMRegister tmp0, XMMRegister state) {
  const XMMRegister tmp1 = xmm4;
  const XMMRegister tmp2 = xmm5;
  const XMMRegister tmp3 = xmm6;
  const XMMRegister tmp4 = xmm7;

  vpclmulldq(tmp1, state, tmp0); //0x00  (a0 * b0)
  vpclmulhdq(tmp4, state, tmp0);//0x11 (a1 * b1)
  vpclmullqhqdq(tmp2, state, tmp0);//0x10 (a1 * b0)
  vpclmulhqlqdq(tmp3, state, tmp0); //0x01 (a0 * b1)

  vpxor(tmp2, tmp2, tmp3, Assembler::AVX_128bit); // (a0 * b1) + (a1 * b0)

  vpslldq(tmp3, tmp2, 8, Assembler::AVX_128bit);
  vpsrldq(tmp2, tmp2, 8, Assembler::AVX_128bit);
  vpxor(tmp1, tmp1, tmp3, Assembler::AVX_128bit); // tmp1 and tmp4 hold the result
  vpxor(tmp4, tmp4, tmp2, Assembler::AVX_128bit); // of carryless multiplication
  // Follows the reduction technique mentioned in
  // Shift-XOR reduction described in Gueron-Kounavis May 2010
  // First phase of reduction
  //
  vpslld(xmm8, tmp1, 31, Assembler::AVX_128bit); // packed right shift shifting << 31
  vpslld(xmm9, tmp1, 30, Assembler::AVX_128bit); // packed right shift shifting << 30
  vpslld(xmm10, tmp1, 25, Assembler::AVX_128bit);// packed right shift shifting << 25
  // xor the shifted versions
  vpxor(xmm8, xmm8, xmm9, Assembler::AVX_128bit);
  vpxor(xmm8, xmm8, xmm10, Assembler::AVX_128bit);
  vpslldq(xmm9, xmm8, 12, Assembler::AVX_128bit);
  vpsrldq(xmm8, xmm8, 4, Assembler::AVX_128bit);
  vpxor(tmp1, tmp1, xmm9, Assembler::AVX_128bit);// first phase of the reduction complete
  //
  // Second phase of the reduction
  //
  vpsrld(xmm9, tmp1, 1, Assembler::AVX_128bit);// packed left shifting >> 1
  vpsrld(xmm10, tmp1, 2, Assembler::AVX_128bit);// packed left shifting >> 2
  vpsrld(xmm11, tmp1, 7, Assembler::AVX_128bit);// packed left shifting >> 7
  vpxor(xmm9, xmm9, xmm10, Assembler::AVX_128bit);// xor the shifted versions
  vpxor(xmm9, xmm9, xmm11, Assembler::AVX_128bit);
  vpxor(xmm9, xmm9, xmm8, Assembler::AVX_128bit);
  vpxor(tmp1, tmp1, xmm9, Assembler::AVX_128bit);
  vpxor(state, tmp4, tmp1, Assembler::AVX_128bit);// the result is in state
  ret(0);
548}

550// This method takes the subkey after expansion as input and generates 1 * 16 power of subkey H.
551// The power of H is used in reduction process for one block ghash
552void MacroAssembler::generateHtbl_one_block(Register htbl) {
  const XMMRegister t = xmm13;

  // load the original subkey hash
  movdqu(t, Address(htbl, 0));
  // shuffle using long swap mask
  movdqu(xmm10, ExternalAddress(StubRoutines::x86::ghash_long_swap_mask_addr()));
  vpshufb(t, t, xmm10, Assembler::AVX_128bit);

  // Compute H' = GFMUL(H, 2)
  vpsrld(xmm3, t, 7, Assembler::AVX_128bit);
  movdqu(xmm4, ExternalAddress(StubRoutines::x86::ghash_shufflemask_addr()));
  vpshufb(xmm3, xmm3, xmm4, Assembler::AVX_128bit);
  movl(rax, 0xff00);
  movdl(xmm4, rax);
  vpshufb(xmm4, xmm4, xmm3, Assembler::AVX_128bit);
  movdqu(xmm5, ExternalAddress(StubRoutines::x86::ghash_polynomial_addr()));
  vpand(xmm5, xmm5, xmm4, Assembler::AVX_128bit);
  vpsrld(xmm3, t, 31, Assembler::AVX_128bit);
  vpslld(xmm4, t, 1, Assembler::AVX_128bit);
  vpslldq(xmm3, xmm3, 4, Assembler::AVX_128bit);
  vpxor(t, xmm4, xmm3, Assembler::AVX_128bit);// t holds p(x) <<1 or H * 2

  //Adding p(x)<<1 to xmm5 which holds the reduction polynomial
  vpxor(t, t, xmm5, Assembler::AVX_128bit);
  movdqu(Address(htbl, 1 * 16), t); // H * 2

  ret(0);
580}

582// This method takes the subkey after expansion as input and generates the remaining powers of subkey H.
583// The power of H is used in reduction process for eight block ghash
584void MacroAssembler::generateHtbl_eight_blocks(Register htbl) {
  const XMMRegister t = xmm13;
  const XMMRegister tmp0 = xmm1;
  Label GFMUL;

  movdqu(t, Address(htbl, 1 * 16));
  movdqu(tmp0, t);

  // tmp0 and t hold H. Now we compute powers of H by using GFMUL(H, H)
  call(GFMUL, relocInfo::none);
  movdqu(Address(htbl, 2 * 16), t); //H ^ 2 * 2
  call(GFMUL, relocInfo::none);
  movdqu(Address(htbl, 3 * 16), t); //H ^ 3 * 2
  call(GFMUL, relocInfo::none);
  movdqu(Address(htbl, 4 * 16), t); //H ^ 4 * 2
  call(GFMUL, relocInfo::none);
  movdqu(Address(htbl, 5 * 16), t); //H ^ 5 * 2
  call(GFMUL, relocInfo::none);
  movdqu(Address(htbl, 6 * 16), t); //H ^ 6 * 2
  call(GFMUL, relocInfo::none);
  movdqu(Address(htbl, 7 * 16), t); //H ^ 7 * 2
  call(GFMUL, relocInfo::none);
  movdqu(Address(htbl, 8 * 16), t); //H ^ 8 * 2
  ret(0);

  bind(GFMUL);
  gfmul(tmp0, t);
611}

613// Multiblock and single block GHASH computation using Shift XOR reduction technique
614void MacroAssembler::avx_ghash(Register input_state, Register htbl,
  Register input_data, Register blocks) {

  // temporary variables to hold input data and input state
  const XMMRegister data = xmm1;
  const XMMRegister state = xmm0;
  // temporary variables to hold intermediate results
  const XMMRegister tmp0 = xmm3;
  const XMMRegister tmp1 = xmm4;
  const XMMRegister tmp2 = xmm5;
  const XMMRegister tmp3 = xmm6;
  // temporary variables to hold byte and long swap masks
  const XMMRegister bswap_mask = xmm2;
  const XMMRegister lswap_mask = xmm14;

  Label GENERATE_HTBL_1_BLK, GENERATE_HTBL_8_BLKS, BEGIN_PROCESS, GFMUL, BLOCK8_REDUCTION,
        ONE_BLK_INIT, PROCESS_1_BLOCK, PROCESS_8_BLOCKS, SAVE_STATE, EXIT_GHASH;

  testptr(blocks, blocks);
  jcc(Assembler::zero, EXIT_GHASH);

  // Check if Hashtable (1*16) has been already generated
  // For anything less than 8 blocks, we generate only the first power of H.
  movdqu(tmp2, Address(htbl, 1 * 16));
  ptest(tmp2, tmp2);
  jcc(Assembler::notZero, BEGIN_PROCESS);
  call(GENERATE_HTBL_1_BLK, relocInfo::none);

  // Shuffle the input state
  bind(BEGIN_PROCESS);
  movdqu(lswap_mask, ExternalAddress(StubRoutines::x86::ghash_long_swap_mask_addr()));
  movdqu(state, Address(input_state, 0));
  vpshufb(state, state, lswap_mask, Assembler::AVX_128bit);

  cmpl(blocks, 8);
  jcc(Assembler::below, ONE_BLK_INIT);
  // If we have 8 blocks or more data, then generate remaining powers of H
  movdqu(tmp2, Address(htbl, 8 * 16));
  ptest(tmp2, tmp2);
  jcc(Assembler::notZero, PROCESS_8_BLOCKS);
  call(GENERATE_HTBL_8_BLKS, relocInfo::none);

  //Do 8 multiplies followed by a reduction processing 8 blocks of data at a time
  //Each block = 16 bytes.
  bind(PROCESS_8_BLOCKS);
  subl(blocks, 8);
  movdqu(bswap_mask, ExternalAddress(StubRoutines::x86::ghash_byte_swap_mask_addr()));
  movdqu(data, Address(input_data, 16 * 7));
  vpshufb(data, data, bswap_mask, Assembler::AVX_128bit);
  //Loading 1*16 as calculated powers of H required starts at that location.
  movdqu(xmm15, Address(htbl, 1 * 16));
  //Perform carryless multiplication of (H*2, data block #7)
  vpclmulhqlqdq(tmp2, data, xmm15);//a0 * b1
  vpclmulldq(tmp0, data, xmm15);//a0 * b0
  vpclmulhdq(tmp1, data, xmm15);//a1 * b1
  vpclmullqhqdq(tmp3, data, xmm15);//a1* b0
  vpxor(tmp2, tmp2, tmp3, Assembler::AVX_128bit);// (a0 * b1) + (a1 * b0)

  movdqu(data, Address(input_data, 16 * 6));
  vpshufb(data, data, bswap_mask, Assembler::AVX_128bit);
  // Perform carryless multiplication of (H^2 * 2, data block #6)
  schoolbookAAD(2, htbl, data, tmp0, tmp1, tmp2, tmp3);

  movdqu(data, Address(input_data, 16 * 5));
  vpshufb(data, data, bswap_mask, Assembler::AVX_128bit);
  // Perform carryless multiplication of (H^3 * 2, data block #5)
  schoolbookAAD(3, htbl, data, tmp0, tmp1, tmp2, tmp3);
  movdqu(data, Address(input_data, 16 * 4));
  vpshufb(data, data, bswap_mask, Assembler::AVX_128bit);
  // Perform carryless multiplication of (H^4 * 2, data block #4)
  schoolbookAAD(4, htbl, data, tmp0, tmp1, tmp2, tmp3);
  movdqu(data, Address(input_data, 16 * 3));
  vpshufb(data, data, bswap_mask, Assembler::AVX_128bit);
  // Perform carryless multiplication of (H^5 * 2, data block #3)
  schoolbookAAD(5, htbl, data, tmp0, tmp1, tmp2, tmp3);
  movdqu(data, Address(input_data, 16 * 2));
  vpshufb(data, data, bswap_mask, Assembler::AVX_128bit);
  // Perform carryless multiplication of (H^6 * 2, data block #2)
  schoolbookAAD(6, htbl, data, tmp0, tmp1, tmp2, tmp3);
  movdqu(data, Address(input_data, 16 * 1));
  vpshufb(data, data, bswap_mask, Assembler::AVX_128bit);
  // Perform carryless multiplication of (H^7 * 2, data block #1)
  schoolbookAAD(7, htbl, data, tmp0, tmp1, tmp2, tmp3);
  movdqu(data, Address(input_data, 16 * 0));
  // xor data block#0 with input state before perfoming carry-less multiplication
  vpshufb(data, data, bswap_mask, Assembler::AVX_128bit);
  vpxor(data, data, state, Assembler::AVX_128bit);
  // Perform carryless multiplication of (H^8 * 2, data block #0)
  schoolbookAAD(8, htbl, data, tmp0, tmp1, tmp2, tmp3);
  vpslldq(tmp3, tmp2, 8, Assembler::AVX_128bit);
  vpsrldq(tmp2, tmp2, 8, Assembler::AVX_128bit);
  vpxor(tmp0, tmp0, tmp3, Assembler::AVX_128bit);// tmp0, tmp1 contains aggregated results of
  vpxor(tmp1, tmp1, tmp2, Assembler::AVX_128bit);// the multiplication operation

  // we have the 2 128-bit partially accumulated multiplication results in tmp0:tmp1
  // with higher 128-bit in tmp1 and lower 128-bit in corresponding tmp0
  // Follows the reduction technique mentioned in
  // Shift-XOR reduction described in Gueron-Kounavis May 2010
  bind(BLOCK8_REDUCTION);
  // First Phase of the reduction
  vpslld(xmm8, tmp0, 31, Assembler::AVX_128bit); // packed right shifting << 31
  vpslld(xmm9, tmp0, 30, Assembler::AVX_128bit); // packed right shifting << 30
  vpslld(xmm10, tmp0, 25, Assembler::AVX_128bit); // packed right shifting << 25
  // xor the shifted versions
  vpxor(xmm8, xmm8, xmm10, Assembler::AVX_128bit);
  vpxor(xmm8, xmm8, xmm9, Assembler::AVX_128bit);

  vpslldq(xmm9, xmm8, 12, Assembler::AVX_128bit);
  vpsrldq(xmm8, xmm8, 4, Assembler::AVX_128bit);

  vpxor(tmp0, tmp0, xmm9, Assembler::AVX_128bit); // first phase of reduction is complete
  // second phase of the reduction
  vpsrld(xmm9, tmp0, 1, Assembler::AVX_128bit); // packed left shifting >> 1
  vpsrld(xmm10, tmp0, 2, Assembler::AVX_128bit); // packed left shifting >> 2
  vpsrld(tmp2, tmp0, 7, Assembler::AVX_128bit); // packed left shifting >> 7
  // xor the shifted versions
  vpxor(xmm9, xmm9, xmm10, Assembler::AVX_128bit);
  vpxor(xmm9, xmm9, tmp2, Assembler::AVX_128bit);
  vpxor(xmm9, xmm9, xmm8, Assembler::AVX_128bit);
  vpxor(tmp0, xmm9, tmp0, Assembler::AVX_128bit);
  // Final result is in state
  vpxor(state, tmp0, tmp1, Assembler::AVX_128bit);

  lea(input_data, Address(input_data, 16 * 8));
  cmpl(blocks, 8);
  jcc(Assembler::below, ONE_BLK_INIT);
  jmp(PROCESS_8_BLOCKS);

  // Since this is one block operation we will only use H * 2 i.e. the first power of H
  bind(ONE_BLK_INIT);
  movdqu(tmp0, Address(htbl, 1 * 16));
  movdqu(bswap_mask, ExternalAddress(StubRoutines::x86::ghash_byte_swap_mask_addr()));

  //Do one (128 bit x 128 bit) carry-less multiplication at a time followed by a reduction.
  bind(PROCESS_1_BLOCK);
  cmpl(blocks, 0);
  jcc(Assembler::equal, SAVE_STATE);
  subl(blocks, 1);
  movdqu(data, Address(input_data, 0));
  vpshufb(data, data, bswap_mask, Assembler::AVX_128bit);
  vpxor(state, state, data, Assembler::AVX_128bit);
  // gfmul(H*2, state)
  call(GFMUL, relocInfo::none);
  addptr(input_data, 16);
  jmp(PROCESS_1_BLOCK);

  bind(SAVE_STATE);
  vpshufb(state, state, lswap_mask, Assembler::AVX_128bit);
  movdqu(Address(input_state, 0), state);
  jmp(EXIT_GHASH);

  bind(GFMUL);
  gfmul(tmp0, state);

  bind(GENERATE_HTBL_1_BLK);
  generateHtbl_one_block(htbl);

  bind(GENERATE_HTBL_8_BLKS);
  generateHtbl_eight_blocks(htbl);

  bind(EXIT_GHASH);
  // zero out xmm registers used for Htbl storage
  vpxor(xmm0, xmm0, xmm0, Assembler::AVX_128bit);
  vpxor(xmm1, xmm1, xmm1, Assembler::AVX_128bit);
  vpxor(xmm3, xmm3, xmm3, Assembler::AVX_128bit);
  vpxor(xmm15, xmm15, xmm15, Assembler::AVX_128bit);
780}

782// AES Counter Mode using VAES instructions
783void MacroAssembler::aesctr_encrypt(Register src_addr, Register dest_addr, Register key, Register counter,
  Register len_reg, Register used, Register used_addr, Register saved_encCounter_start) {

  const Register rounds = 0;
  const Register pos = r12;

  Label PRELOOP_START, EXIT_PRELOOP, REMAINDER, REMAINDER_16, LOOP, END, EXIT, END_LOOP,
  AES192, AES256, AES192_REMAINDER16, REMAINDER16_END_LOOP, AES256_REMAINDER16,
  REMAINDER_8, REMAINDER_4, AES192_REMAINDER8, REMAINDER_LOOP, AES256_REMINDER,
  AES192_REMAINDER, END_REMAINDER_LOOP, AES256_REMAINDER8, REMAINDER8_END_LOOP,
  AES192_REMAINDER4, AES256_REMAINDER4, AES256_REMAINDER, END_REMAINDER4, EXTRACT_TAILBYTES,
  EXTRACT_TAIL_4BYTES, EXTRACT_TAIL_2BYTES, EXTRACT_TAIL_1BYTE, STORE_CTR;

  cmpl(len_reg, 0);
  jcc(Assembler::belowEqual, EXIT);

  movl(pos, 0);
  // if the number of used encrypted counter bytes < 16,
  // XOR PT with saved encrypted counter to obtain CT
  bind(PRELOOP_START);
  cmpl(used, 16);
  jcc(Assembler::aboveEqual, EXIT_PRELOOP);
  movb(rbx, Address(saved_encCounter_start, used));
  xorb(rbx, Address(src_addr, pos));
  movb(Address(dest_addr, pos), rbx);
  addptr(pos, 1);
  addptr(used, 1);
  decrement(len_reg);
  jmp(PRELOOP_START);

  bind(EXIT_PRELOOP);
  movl(Address(used_addr, 0), used);

  // Calculate number of rounds i.e. 10, 12, 14,  based on key length(128, 192, 256).
  movl(rounds, Address(key, arrayOopDesc::length_offset_in_bytes() - arrayOopDesc::base_offset_in_bytes(T_INT)));

  vpxor(xmm0, xmm0, xmm0, Assembler::AVX_128bit);
  // Move initial counter value in xmm0
  movdqu(xmm0, Address(counter, 0));
  // broadcast counter value to zmm8
  evshufi64x2(xmm8, xmm0, xmm0, 0, Assembler::AVX_512bit);

  // load lbswap mask
  evmovdquq(xmm16, ExternalAddress(StubRoutines::x86::counter_mask_addr()), Assembler::AVX_512bit, r15);

  //shuffle counter using lbswap_mask
  vpshufb(xmm8, xmm8, xmm16, Assembler::AVX_512bit);

  // pre-increment and propagate counter values to zmm9-zmm15 registers.
  // Linc0 increments the zmm8 by 1 (initial value being 0), Linc4 increments the counters zmm9-zmm15 by 4
  // The counter is incremented after each block i.e. 16 bytes is processed;
  // each zmm register has 4 counter values as its MSB
  // the counters are incremented in parallel
  vpaddd(xmm8, xmm8, ExternalAddress(StubRoutines::x86::counter_mask_addr() + 64), Assembler::AVX_512bit, r15);//linc0
  vpaddd(xmm9, xmm8, ExternalAddress(StubRoutines::x86::counter_mask_addr() + 128), Assembler::AVX_512bit, r15);//linc4(rip)
  vpaddd(xmm10, xmm9, ExternalAddress(StubRoutines::x86::counter_mask_addr() + 128), Assembler::AVX_512bit, r15);//Linc4(rip)
  vpaddd(xmm11, xmm10, ExternalAddress(StubRoutines::x86::counter_mask_addr() + 128), Assembler::AVX_512bit, r15);//Linc4(rip)
  vpaddd(xmm12, xmm11, ExternalAddress(StubRoutines::x86::counter_mask_addr() + 128), Assembler::AVX_512bit, r15);//Linc4(rip)
  vpaddd(xmm13, xmm12, ExternalAddress(StubRoutines::x86::counter_mask_addr() + 128), Assembler::AVX_512bit, r15);//Linc4(rip)
  vpaddd(xmm14, xmm13, ExternalAddress(StubRoutines::x86::counter_mask_addr() + 128), Assembler::AVX_512bit, r15);//Linc4(rip)
  vpaddd(xmm15, xmm14, ExternalAddress(StubRoutines::x86::counter_mask_addr() + 128), Assembler::AVX_512bit, r15);//Linc4(rip)

  // load linc32 mask in zmm register.linc32 increments counter by 32
  evmovdquq(xmm19, ExternalAddress(StubRoutines::x86::counter_mask_addr() + 256), Assembler::AVX_512bit, r15);//Linc32

  // xmm31 contains the key shuffle mask.
  movdqu(xmm31, ExternalAddress(StubRoutines::x86::key_shuffle_mask_addr()));
  // Load key function loads 128 bit key and shuffles it. Then we broadcast the shuffled key to convert it into a 512 bit value.
  // For broadcasting the values to ZMM, vshufi64 is used instead of evbroadcasti64x2 as the source in this case is ZMM register
  // that holds shuffled key value.
  ev_load_key(xmm20, key, 0, xmm31);
  ev_load_key(xmm21, key, 1 * 16, xmm31);
  ev_load_key(xmm22, key, 2 * 16, xmm31);
  ev_load_key(xmm23, key, 3 * 16, xmm31);
  ev_load_key(xmm24, key, 4 * 16, xmm31);
  ev_load_key(xmm25, key, 5 * 16, xmm31);
  ev_load_key(xmm26, key, 6 * 16, xmm31);
  ev_load_key(xmm27, key, 7 * 16, xmm31);
  ev_load_key(xmm28, key, 8 * 16, xmm31);
  ev_load_key(xmm29, key, 9 * 16, xmm31);
  ev_load_key(xmm30, key, 10 * 16, xmm31);

  // Process 32 blocks or 512 bytes of data
  bind(LOOP);
  cmpl(len_reg, 512);
  jcc(Assembler::less, REMAINDER);
  subq(len_reg, 512);
  //Shuffle counter and Exor it with roundkey1. Result is stored in zmm0-7
  vpshufb(xmm0, xmm8, xmm16, Assembler::AVX_512bit);
  evpxorq(xmm0, xmm0, xmm20, Assembler::AVX_512bit);
  vpshufb(xmm1, xmm9, xmm16, Assembler::AVX_512bit);
  evpxorq(xmm1, xmm1, xmm20, Assembler::AVX_512bit);
  vpshufb(xmm2, xmm10, xmm16, Assembler::AVX_512bit);
  evpxorq(xmm2, xmm2, xmm20, Assembler::AVX_512bit);
  vpshufb(xmm3, xmm11, xmm16, Assembler::AVX_512bit);
  evpxorq(xmm3, xmm3, xmm20, Assembler::AVX_512bit);
  vpshufb(xmm4, xmm12, xmm16, Assembler::AVX_512bit);
  evpxorq(xmm4, xmm4, xmm20, Assembler::AVX_512bit);
  vpshufb(xmm5, xmm13, xmm16, Assembler::AVX_512bit);
  evpxorq(xmm5, xmm5, xmm20, Assembler::AVX_512bit);
  vpshufb(xmm6, xmm14, xmm16, Assembler::AVX_512bit);
  evpxorq(xmm6, xmm6, xmm20, Assembler::AVX_512bit);
  vpshufb(xmm7, xmm15, xmm16, Assembler::AVX_512bit);
  evpxorq(xmm7, xmm7, xmm20, Assembler::AVX_512bit);
  // Perform AES encode operations and put results in zmm0-zmm7.
  // This is followed by incrementing counter values in zmm8-zmm15.
  // Since we will be processing 32 blocks at a time, the counter is incremented by 32.
  roundEnc(xmm21, 7);
  vpaddq(xmm8, xmm8, xmm19, Assembler::AVX_512bit);
  roundEnc(xmm22, 7);
  vpaddq(xmm9, xmm9, xmm19, Assembler::AVX_512bit);
  roundEnc(xmm23, 7);
  vpaddq(xmm10, xmm10, xmm19, Assembler::AVX_512bit);
  roundEnc(xmm24, 7);
  vpaddq(xmm11, xmm11, xmm19, Assembler::AVX_512bit);
  roundEnc(xmm25, 7);
  vpaddq(xmm12, xmm12, xmm19, Assembler::AVX_512bit);
  roundEnc(xmm26, 7);
  vpaddq(xmm13, xmm13, xmm19, Assembler::AVX_512bit);
  roundEnc(xmm27, 7);
  vpaddq(xmm14, xmm14, xmm19, Assembler::AVX_512bit);
  roundEnc(xmm28, 7);
  vpaddq(xmm15, xmm15, xmm19, Assembler::AVX_512bit);
  roundEnc(xmm29, 7);

  cmpl(rounds, 52);
  jcc(Assembler::aboveEqual, AES192);
  lastroundEnc(xmm30, 7);
  jmp(END_LOOP);

  bind(AES192);
  roundEnc(xmm30, 7);
  ev_load_key(xmm18, key, 11 * 16, xmm31);
  roundEnc(xmm18, 7);
  cmpl(rounds, 60);
  jcc(Assembler::aboveEqual, AES256);
  ev_load_key(xmm18, key, 12 * 16, xmm31);
  lastroundEnc(xmm18, 7);
  jmp(END_LOOP);

  bind(AES256);
  ev_load_key(xmm18, key, 12 * 16, xmm31);
  roundEnc(xmm18, 7);
  ev_load_key(xmm18, key, 13 * 16, xmm31);
  roundEnc(xmm18, 7);
  ev_load_key(xmm18, key, 14 * 16, xmm31);
  lastroundEnc(xmm18, 7);

  // After AES encode rounds, the encrypted block cipher lies in zmm0-zmm7
  // xor encrypted block cipher and input plaintext and store resultant ciphertext
  bind(END_LOOP);
  evpxorq(xmm0, xmm0, Address(src_addr, pos, Address::times_1, 0 * 64), Assembler::AVX_512bit);
  evmovdquq(Address(dest_addr, pos, Address::times_1, 0), xmm0, Assembler::AVX_512bit);
  evpxorq(xmm1, xmm1, Address(src_addr, pos, Address::times_1, 1 * 64), Assembler::AVX_512bit);
  evmovdquq(Address(dest_addr, pos, Address::times_1, 64), xmm1, Assembler::AVX_512bit);
  evpxorq(xmm2, xmm2, Address(src_addr, pos, Address::times_1, 2 * 64), Assembler::AVX_512bit);
  evmovdquq(Address(dest_addr, pos, Address::times_1, 2 * 64), xmm2, Assembler::AVX_512bit);
  evpxorq(xmm3, xmm3, Address(src_addr, pos, Address::times_1, 3 * 64), Assembler::AVX_512bit);
  evmovdquq(Address(dest_addr, pos, Address::times_1, 3 * 64), xmm3, Assembler::AVX_512bit);
  evpxorq(xmm4, xmm4, Address(src_addr, pos, Address::times_1, 4 * 64), Assembler::AVX_512bit);
  evmovdquq(Address(dest_addr, pos, Address::times_1, 4 * 64), xmm4, Assembler::AVX_512bit);
  evpxorq(xmm5, xmm5, Address(src_addr, pos, Address::times_1, 5 * 64), Assembler::AVX_512bit);
  evmovdquq(Address(dest_addr, pos, Address::times_1, 5 * 64), xmm5, Assembler::AVX_512bit);
  evpxorq(xmm6, xmm6, Address(src_addr, pos, Address::times_1, 6 * 64), Assembler::AVX_512bit);
  evmovdquq(Address(dest_addr, pos, Address::times_1, 6 * 64), xmm6, Assembler::AVX_512bit);
  evpxorq(xmm7, xmm7, Address(src_addr, pos, Address::times_1, 7 * 64), Assembler::AVX_512bit);
  evmovdquq(Address(dest_addr, pos, Address::times_1, 7 * 64), xmm7, Assembler::AVX_512bit);
  addq(pos, 512);
  jmp(LOOP);

  // Encode 256, 128, 64 or 16 bytes at a time if length is less than 512 bytes
  bind(REMAINDER);
  cmpl(len_reg, 0);
  jcc(Assembler::equal, END);
  cmpl(len_reg, 256);
  jcc(Assembler::aboveEqual, REMAINDER_16);
  cmpl(len_reg, 128);
  jcc(Assembler::aboveEqual, REMAINDER_8);
  cmpl(len_reg, 64);
  jcc(Assembler::aboveEqual, REMAINDER_4);
  // At this point, we will process 16 bytes of data at a time.
  // So load xmm19 with counter increment value as 1
  evmovdquq(xmm19, ExternalAddress(StubRoutines::x86::counter_mask_addr() + 80), Assembler::AVX_128bit, r15);
  jmp(REMAINDER_LOOP);

  // Each ZMM register can be used to encode 64 bytes of data, so we have 4 ZMM registers to encode 256 bytes of data
  bind(REMAINDER_16);
  subq(len_reg, 256);
  // As we process 16 blocks at a time, load mask for incrementing the counter value by 16
  evmovdquq(xmm19, ExternalAddress(StubRoutines::x86::counter_mask_addr() + 320), Assembler::AVX_512bit, r15);//Linc16(rip)
  // shuffle counter and XOR counter with roundkey1
  vpshufb(xmm0, xmm8, xmm16, Assembler::AVX_512bit);
  evpxorq(xmm0, xmm0, xmm20, Assembler::AVX_512bit);
  vpshufb(xmm1, xmm9, xmm16, Assembler::AVX_512bit);
  evpxorq(xmm1, xmm1, xmm20, Assembler::AVX_512bit);
  vpshufb(xmm2, xmm10, xmm16, Assembler::AVX_512bit);
  evpxorq(xmm2, xmm2, xmm20, Assembler::AVX_512bit);
  vpshufb(xmm3, xmm11, xmm16, Assembler::AVX_512bit);
  evpxorq(xmm3, xmm3, xmm20, Assembler::AVX_512bit);
  // Increment counter values by 16
  vpaddq(xmm8, xmm8, xmm19, Assembler::AVX_512bit);
  vpaddq(xmm9, xmm9, xmm19, Assembler::AVX_512bit);
  // AES encode rounds
  roundEnc(xmm21, 3);
  roundEnc(xmm22, 3);
  roundEnc(xmm23, 3);
  roundEnc(xmm24, 3);
  roundEnc(xmm25, 3);
  roundEnc(xmm26, 3);
  roundEnc(xmm27, 3);
  roundEnc(xmm28, 3);
  roundEnc(xmm29, 3);

  cmpl(rounds, 52);
  jcc(Assembler::aboveEqual, AES192_REMAINDER16);
  lastroundEnc(xmm30, 3);
  jmp(REMAINDER16_END_LOOP);

  bind(AES192_REMAINDER16);
  roundEnc(xmm30, 3);
  ev_load_key(xmm18, key, 11 * 16, xmm31);
  roundEnc(xmm18, 3);
  ev_load_key(xmm5, key, 12 * 16, xmm31);

  cmpl(rounds, 60);
  jcc(Assembler::aboveEqual, AES256_REMAINDER16);
  lastroundEnc(xmm5, 3);
  jmp(REMAINDER16_END_LOOP);
  bind(AES256_REMAINDER16);
  roundEnc(xmm5, 3);
  ev_load_key(xmm6, key, 13 * 16, xmm31);
  roundEnc(xmm6, 3);
  ev_load_key(xmm7, key, 14 * 16, xmm31);
  lastroundEnc(xmm7, 3);

  // After AES encode rounds, the encrypted block cipher lies in zmm0-zmm3
  // xor 256 bytes of PT with the encrypted counters to produce CT.
  bind(REMAINDER16_END_LOOP);
  evpxorq(xmm0, xmm0, Address(src_addr, pos, Address::times_1, 0), Assembler::AVX_512bit);
  evmovdquq(Address(dest_addr, pos, Address::times_1, 0), xmm0, Assembler::AVX_512bit);
  evpxorq(xmm1, xmm1, Address(src_addr, pos, Address::times_1, 1 * 64), Assembler::AVX_512bit);
  evmovdquq(Address(dest_addr, pos, Address::times_1, 1 * 64), xmm1, Assembler::AVX_512bit);
  evpxorq(xmm2, xmm2, Address(src_addr, pos, Address::times_1, 2 * 64), Assembler::AVX_512bit);
  evmovdquq(Address(dest_addr, pos, Address::times_1, 2 * 64), xmm2, Assembler::AVX_512bit);
  evpxorq(xmm3, xmm3, Address(src_addr, pos, Address::times_1, 3 * 64), Assembler::AVX_512bit);
  evmovdquq(Address(dest_addr, pos, Address::times_1, 3 * 64), xmm3, Assembler::AVX_512bit);
  addq(pos, 256);

  cmpl(len_reg, 128);
  jcc(Assembler::aboveEqual, REMAINDER_8);

  cmpl(len_reg, 64);
  jcc(Assembler::aboveEqual, REMAINDER_4);
  //load mask for incrementing the counter value by 1
  evmovdquq(xmm19, ExternalAddress(StubRoutines::x86::counter_mask_addr() + 80), Assembler::AVX_128bit, r15);//Linc0 + 16(rip)
  jmp(REMAINDER_LOOP);

  // Each ZMM register can be used to encode 64 bytes of data, so we have 2 ZMM registers to encode 128 bytes of data
  bind(REMAINDER_8);
  subq(len_reg, 128);
  // As we process 8 blocks at a time, load mask for incrementing the counter value by 8
  evmovdquq(xmm19, ExternalAddress(StubRoutines::x86::counter_mask_addr() + 192), Assembler::AVX_512bit, r15);//Linc8(rip)
  // shuffle counters and xor with roundkey1
  vpshufb(xmm0, xmm8, xmm16, Assembler::AVX_512bit);
  evpxorq(xmm0, xmm0, xmm20, Assembler::AVX_512bit);
  vpshufb(xmm1, xmm9, xmm16, Assembler::AVX_512bit);
  evpxorq(xmm1, xmm1, xmm20, Assembler::AVX_512bit);
  // increment counter by 8
  vpaddq(xmm8, xmm8, xmm19, Assembler::AVX_512bit);
  // AES encode
  roundEnc(xmm21, 1);
  roundEnc(xmm22, 1);
  roundEnc(xmm23, 1);
  roundEnc(xmm24, 1);
  roundEnc(xmm25, 1);
  roundEnc(xmm26, 1);
  roundEnc(xmm27, 1);
  roundEnc(xmm28, 1);
  roundEnc(xmm29, 1);

  cmpl(rounds, 52);
  jcc(Assembler::aboveEqual, AES192_REMAINDER8);
  lastroundEnc(xmm30, 1);
  jmp(REMAINDER8_END_LOOP);

  bind(AES192_REMAINDER8);
  roundEnc(xmm30, 1);
  ev_load_key(xmm18, key, 11 * 16, xmm31);
  roundEnc(xmm18, 1);
  ev_load_key(xmm5, key, 12 * 16, xmm31);
  cmpl(rounds, 60);
  jcc(Assembler::aboveEqual, AES256_REMAINDER8);
  lastroundEnc(xmm5, 1);
  jmp(REMAINDER8_END_LOOP);

  bind(AES256_REMAINDER8);
  roundEnc(xmm5, 1);
  ev_load_key(xmm6, key, 13 * 16, xmm31);
  roundEnc(xmm6, 1);
  ev_load_key(xmm7, key, 14 * 16, xmm31);
  lastroundEnc(xmm7, 1);

  bind(REMAINDER8_END_LOOP);
  // After AES encode rounds, the encrypted block cipher lies in zmm0-zmm1
  // XOR PT with the encrypted counter and store as CT
  evpxorq(xmm0, xmm0, Address(src_addr, pos, Address::times_1, 0 * 64), Assembler::AVX_512bit);
  evmovdquq(Address(dest_addr, pos, Address::times_1, 0 * 64), xmm0, Assembler::AVX_512bit);
  evpxorq(xmm1, xmm1, Address(src_addr, pos, Address::times_1, 1 * 64), Assembler::AVX_512bit);
  evmovdquq(Address(dest_addr, pos, Address::times_1, 1 * 64), xmm1, Assembler::AVX_512bit);
  addq(pos, 128);

  cmpl(len_reg, 64);
  jcc(Assembler::aboveEqual, REMAINDER_4);
  // load mask for incrementing the counter value by 1
  evmovdquq(xmm19, ExternalAddress(StubRoutines::x86::counter_mask_addr() + 80), Assembler::AVX_128bit, r15);//Linc0 + 16(rip)
  jmp(REMAINDER_LOOP);

  // Each ZMM register can be used to encode 64 bytes of data, so we have 1 ZMM register used in this block of code
  bind(REMAINDER_4);
  subq(len_reg, 64);
  // As we process 4 blocks at a time, load mask for incrementing the counter value by 4
  evmovdquq(xmm19, ExternalAddress(StubRoutines::x86::counter_mask_addr() + 128), Assembler::AVX_512bit, r15);//Linc4(rip)
  // XOR counter with first roundkey
  vpshufb(xmm0, xmm8, xmm16, Assembler::AVX_512bit);
  evpxorq(xmm0, xmm0, xmm20, Assembler::AVX_512bit);
  // Increment counter
  vpaddq(xmm8, xmm8, xmm19, Assembler::AVX_512bit);
  vaesenc(xmm0, xmm0, xmm21, Assembler::AVX_512bit);
  vaesenc(xmm0, xmm0, xmm22, Assembler::AVX_512bit);
  vaesenc(xmm0, xmm0, xmm23, Assembler::AVX_512bit);
  vaesenc(xmm0, xmm0, xmm24, Assembler::AVX_512bit);
  vaesenc(xmm0, xmm0, xmm25, Assembler::AVX_512bit);
  vaesenc(xmm0, xmm0, xmm26, Assembler::AVX_512bit);
  vaesenc(xmm0, xmm0, xmm27, Assembler::AVX_512bit);
  vaesenc(xmm0, xmm0, xmm28, Assembler::AVX_512bit);
  vaesenc(xmm0, xmm0, xmm29, Assembler::AVX_512bit);
  cmpl(rounds, 52);
  jcc(Assembler::aboveEqual, AES192_REMAINDER4);
  vaesenclast(xmm0, xmm0, xmm30, Assembler::AVX_512bit);
  jmp(END_REMAINDER4);

  bind(AES192_REMAINDER4);
  vaesenc(xmm0, xmm0, xmm30, Assembler::AVX_512bit);
  ev_load_key(xmm18, key, 11 * 16, xmm31);
  vaesenc(xmm0, xmm0, xmm18, Assembler::AVX_512bit);
  ev_load_key(xmm5, key, 12 * 16, xmm31);

  cmpl(rounds, 60);
  jcc(Assembler::aboveEqual, AES256_REMAINDER4);
  vaesenclast(xmm0, xmm0, xmm5, Assembler::AVX_512bit);
  jmp(END_REMAINDER4);

  bind(AES256_REMAINDER4);
  vaesenc(xmm0, xmm0, xmm5, Assembler::AVX_512bit);
  ev_load_key(xmm6, key, 13 * 16, xmm31);
  vaesenc(xmm0, xmm0, xmm6, Assembler::AVX_512bit);
  ev_load_key(xmm7, key, 14 * 16, xmm31);
  vaesenclast(xmm0, xmm0, xmm7, Assembler::AVX_512bit);
  // After AES encode rounds, the encrypted block cipher lies in zmm0.
  // XOR encrypted block cipher with PT and store 64 bytes of ciphertext
  bind(END_REMAINDER4);
  evpxorq(xmm0, xmm0, Address(src_addr, pos, Address::times_1, 0 * 64), Assembler::AVX_512bit);
  evmovdquq(Address(dest_addr, pos, Address::times_1, 0), xmm0, Assembler::AVX_512bit);
  addq(pos, 64);
  // load mask for incrementing the counter value by 1
  evmovdquq(xmm19, ExternalAddress(StubRoutines::x86::counter_mask_addr() + 80), Assembler::AVX_128bit, r15);//Linc0 + 16(rip)

  // For a single block, the AES rounds start here.
  bind(REMAINDER_LOOP);
  cmpl(len_reg, 0);
  jcc(Assembler::belowEqual, END);
  // XOR counter with first roundkey
  vpshufb(xmm0, xmm8, xmm16, Assembler::AVX_128bit);
  evpxorq(xmm0, xmm0, xmm20, Assembler::AVX_128bit);
  vaesenc(xmm0, xmm0, xmm21, Assembler::AVX_128bit);
  // Increment counter by 1
  vpaddq(xmm8, xmm8, xmm19, Assembler::AVX_128bit);
  vaesenc(xmm0, xmm0, xmm22, Assembler::AVX_128bit);
  vaesenc(xmm0, xmm0, xmm23, Assembler::AVX_128bit);
  vaesenc(xmm0, xmm0, xmm24, Assembler::AVX_128bit);
  vaesenc(xmm0, xmm0, xmm25, Assembler::AVX_128bit);
  vaesenc(xmm0, xmm0, xmm26, Assembler::AVX_128bit);
  vaesenc(xmm0, xmm0, xmm27, Assembler::AVX_128bit);
  vaesenc(xmm0, xmm0, xmm28, Assembler::AVX_128bit);
  vaesenc(xmm0, xmm0, xmm29, Assembler::AVX_128bit);

  cmpl(rounds, 52);
  jcc(Assembler::aboveEqual, AES192_REMAINDER);
  vaesenclast(xmm0, xmm0, xmm30, Assembler::AVX_128bit);
  jmp(END_REMAINDER_LOOP);

  bind(AES192_REMAINDER);
  vaesenc(xmm0, xmm0, xmm30, Assembler::AVX_128bit);
  ev_load_key(xmm18, key, 11 * 16, xmm31);
  vaesenc(xmm0, xmm0, xmm18, Assembler::AVX_128bit);
  ev_load_key(xmm5, key, 12 * 16, xmm31);
  cmpl(rounds, 60);
  jcc(Assembler::aboveEqual, AES256_REMAINDER);
  vaesenclast(xmm0, xmm0, xmm5, Assembler::AVX_128bit);
  jmp(END_REMAINDER_LOOP);

  bind(AES256_REMAINDER);
  vaesenc(xmm0, xmm0, xmm5, Assembler::AVX_128bit);
  ev_load_key(xmm6, key, 13 * 16, xmm31);
  vaesenc(xmm0, xmm0, xmm6, Assembler::AVX_128bit);
  ev_load_key(xmm7, key, 14 * 16, xmm31);
  vaesenclast(xmm0, xmm0, xmm7, Assembler::AVX_128bit);

  bind(END_REMAINDER_LOOP);
  // If the length register is less than the blockSize i.e. 16
  // then we store only those bytes of the CT to the destination
  // corresponding to the length register value
  // extracting the exact number of bytes is handled by EXTRACT_TAILBYTES
  cmpl(len_reg, 16);
  jcc(Assembler::less, EXTRACT_TAILBYTES);
  subl(len_reg, 16);
  // After AES encode rounds, the encrypted block cipher lies in xmm0.
  // If the length register is equal to 16 bytes, store CT in dest after XOR operation.
  evpxorq(xmm0, xmm0, Address(src_addr, pos, Address::times_1, 0), Assembler::AVX_128bit);
  evmovdquq(Address(dest_addr, pos, Address::times_1, 0), xmm0, Assembler::AVX_128bit);
  addl(pos, 16);

  jmp(REMAINDER_LOOP);

  bind(EXTRACT_TAILBYTES);
  // Save encrypted counter value in xmm0 for next invocation, before XOR operation
  movdqu(Address(saved_encCounter_start, 0), xmm0);
  // XOR encryted block cipher in xmm0 with PT to produce CT
  evpxorq(xmm0, xmm0, Address(src_addr, pos, Address::times_1, 0), Assembler::AVX_128bit);
  // extract upto 15 bytes of CT from xmm0 as specified by length register
  testptr(len_reg, 8);
  jcc(Assembler::zero, EXTRACT_TAIL_4BYTES);
  pextrq(Address(dest_addr, pos), xmm0, 0);
  psrldq(xmm0, 8);
  addl(pos, 8);
  bind(EXTRACT_TAIL_4BYTES);
  testptr(len_reg, 4);
  jcc(Assembler::zero, EXTRACT_TAIL_2BYTES);
  pextrd(Address(dest_addr, pos), xmm0, 0);
  psrldq(xmm0, 4);
  addq(pos, 4);
  bind(EXTRACT_TAIL_2BYTES);
  testptr(len_reg, 2);
  jcc(Assembler::zero, EXTRACT_TAIL_1BYTE);
  pextrw(Address(dest_addr, pos), xmm0, 0);
  psrldq(xmm0, 2);
  addl(pos, 2);
  bind(EXTRACT_TAIL_1BYTE);
  testptr(len_reg, 1);
  jcc(Assembler::zero, END);
  pextrb(Address(dest_addr, pos), xmm0, 0);
  addl(pos, 1);

  bind(END);
  // If there are no tail bytes, store counter value and exit
  cmpl(len_reg, 0);
  jcc(Assembler::equal, STORE_CTR);
  movl(Address(used_addr, 0), len_reg);

  bind(STORE_CTR);
  //shuffle updated counter and store it
  vpshufb(xmm8, xmm8, xmm16, Assembler::AVX_128bit);
  movdqu(Address(counter, 0), xmm8);
  // Zero out counter and key registers
  evpxorq(xmm8, xmm8, xmm8, Assembler::AVX_512bit);
  evpxorq(xmm20, xmm20, xmm20, Assembler::AVX_512bit);
  evpxorq(xmm21, xmm21, xmm21, Assembler::AVX_512bit);
  evpxorq(xmm22, xmm22, xmm22, Assembler::AVX_512bit);
  evpxorq(xmm23, xmm23, xmm23, Assembler::AVX_512bit);
  evpxorq(xmm24, xmm24, xmm24, Assembler::AVX_512bit);
  evpxorq(xmm25, xmm25, xmm25, Assembler::AVX_512bit);
  evpxorq(xmm26, xmm26, xmm26, Assembler::AVX_512bit);
  evpxorq(xmm27, xmm27, xmm27, Assembler::AVX_512bit);
  evpxorq(xmm28, xmm28, xmm28, Assembler::AVX_512bit);
  evpxorq(xmm29, xmm29, xmm29, Assembler::AVX_512bit);
  evpxorq(xmm30, xmm30, xmm30, Assembler::AVX_512bit);
  cmpl(rounds, 44);
  jcc(Assembler::belowEqual, EXIT);
  evpxorq(xmm18, xmm18, xmm18, Assembler::AVX_512bit);
  evpxorq(xmm5, xmm5, xmm5, Assembler::AVX_512bit);
  cmpl(rounds, 52);
  jcc(Assembler::belowEqual, EXIT);
  evpxorq(xmm6, xmm6, xmm6, Assembler::AVX_512bit);
  evpxorq(xmm7, xmm7, xmm7, Assembler::AVX_512bit);
  bind(EXIT);
1268}

1270void MacroAssembler::gfmul_avx512(XMMRegister GH, XMMRegister HK) {
  const XMMRegister TMP1 = xmm0;
  const XMMRegister TMP2 = xmm1;
  const XMMRegister TMP3 = xmm2;

  evpclmulqdq(TMP1, GH, HK, 0x11, Assembler::AVX_512bit);
  evpclmulqdq(TMP2, GH, HK, 0x00, Assembler::AVX_512bit);
  evpclmulqdq(TMP3, GH, HK, 0x01, Assembler::AVX_512bit);
  evpclmulqdq(GH, GH, HK, 0x10, Assembler::AVX_512bit);
  evpxorq(GH, GH, TMP3, Assembler::AVX_512bit);
  vpsrldq(TMP3, GH, 8, Assembler::AVX_512bit);
  vpslldq(GH, GH, 8, Assembler::AVX_512bit);
  evpxorq(TMP1, TMP1, TMP3, Assembler::AVX_512bit);
  evpxorq(GH, GH, TMP2, Assembler::AVX_512bit);

  evmovdquq(TMP3, ExternalAddress(StubRoutines::x86::ghash_polynomial512_addr()), Assembler::AVX_512bit, r15);
  evpclmulqdq(TMP2, TMP3, GH, 0x01, Assembler::AVX_512bit);
  vpslldq(TMP2, TMP2, 8, Assembler::AVX_512bit);
  evpxorq(GH, GH, TMP2, Assembler::AVX_512bit);
  evpclmulqdq(TMP2, TMP3, GH, 0x00, Assembler::AVX_512bit);
  vpsrldq(TMP2, TMP2, 4, Assembler::AVX_512bit);
  evpclmulqdq(GH, TMP3, GH, 0x10, Assembler::AVX_512bit);
  vpslldq(GH, GH, 4, Assembler::AVX_512bit);
  vpternlogq(GH, 0x96, TMP1, TMP2, Assembler::AVX_512bit);
1294}

1296void MacroAssembler::generateHtbl_48_block_zmm(Register htbl, Register avx512_htbl) {
  const XMMRegister HK = xmm6;
  const XMMRegister ZT5 = xmm4;
  const XMMRegister ZT7 = xmm7;
  const XMMRegister ZT8 = xmm8;

  Label GFMUL_AVX512;

  movdqu(HK, Address(htbl, 0));
  movdqu(xmm10, ExternalAddress(StubRoutines::x86::ghash_long_swap_mask_addr()));
  vpshufb(HK, HK, xmm10, Assembler::AVX_128bit);

  movdqu(xmm11, ExternalAddress(StubRoutines::x86::ghash_polynomial512_addr() + 64)); // Poly
  movdqu(xmm12, ExternalAddress(StubRoutines::x86::ghash_polynomial512_addr() + 80)); // Twoone
  // Compute H ^ 2 from the input subkeyH
  movdqu(xmm2, xmm6);
  vpsllq(xmm6, xmm6, 1, Assembler::AVX_128bit);
  vpsrlq(xmm2, xmm2, 63, Assembler::AVX_128bit);
  movdqu(xmm1, xmm2);
  vpslldq(xmm2, xmm2, 8, Assembler::AVX_128bit);
  vpsrldq(xmm1, xmm1, 8, Assembler::AVX_128bit);
  vpor(xmm6, xmm6, xmm2, Assembler::AVX_128bit);

  vpshufd(xmm2, xmm1, 0x24, Assembler::AVX_128bit);
  vpcmpeqd(xmm2, xmm2, xmm12, AVX_128bit);
  vpand(xmm2, xmm2, xmm11, Assembler::AVX_128bit);
  vpxor(xmm6, xmm6, xmm2, Assembler::AVX_128bit);
  movdqu(Address(avx512_htbl, 16 * 47), xmm6); // H ^ 2
  // Compute the remaining three powers of H using XMM registers and all following powers using ZMM
  movdqu(ZT5, HK);
  vinserti32x4(ZT7, ZT7, HK, 3);

  gfmul_avx512(ZT5, HK);
  movdqu(Address(avx512_htbl, 16 * 46), ZT5); // H ^ 2 * 2
  vinserti32x4(ZT7, ZT7, ZT5, 2);

  gfmul_avx512(ZT5, HK);
  movdqu(Address(avx512_htbl, 16 * 45), ZT5); // H ^ 2 * 3
  vinserti32x4(ZT7, ZT7, ZT5, 1);

  gfmul_avx512(ZT5, HK);
  movdqu(Address(avx512_htbl, 16 * 44), ZT5); // H ^ 2 * 4
  vinserti32x4(ZT7, ZT7, ZT5, 0);

  evshufi64x2(ZT5, ZT5, ZT5, 0x00, Assembler::AVX_512bit);
  evmovdquq(ZT8, ZT7, Assembler::AVX_512bit);
  gfmul_avx512(ZT7, ZT5);
  evmovdquq(Address(avx512_htbl, 16 * 40), ZT7, Assembler::AVX_512bit);
  evshufi64x2(ZT5, ZT7, ZT7, 0x00, Assembler::AVX_512bit);
  gfmul_avx512(ZT8, ZT5);
  evmovdquq(Address(avx512_htbl, 16 * 36), ZT8, Assembler::AVX_512bit);
  gfmul_avx512(ZT7, ZT5);
  evmovdquq(Address(avx512_htbl, 16 * 32), ZT7, Assembler::AVX_512bit);
  gfmul_avx512(ZT8, ZT5);
  evmovdquq(Address(avx512_htbl, 16 * 28), ZT8, Assembler::AVX_512bit);
  gfmul_avx512(ZT7, ZT5);
  evmovdquq(Address(avx512_htbl, 16 * 24), ZT7, Assembler::AVX_512bit);
  gfmul_avx512(ZT8, ZT5);
  evmovdquq(Address(avx512_htbl, 16 * 20), ZT8, Assembler::AVX_512bit);
  gfmul_avx512(ZT7, ZT5);
  evmovdquq(Address(avx512_htbl, 16 * 16), ZT7, Assembler::AVX_512bit);
  gfmul_avx512(ZT8, ZT5);
  evmovdquq(Address(avx512_htbl, 16 * 12), ZT8, Assembler::AVX_512bit);
  gfmul_avx512(ZT7, ZT5);
  evmovdquq(Address(avx512_htbl, 16 * 8), ZT7, Assembler::AVX_512bit);
  gfmul_avx512(ZT8, ZT5);
  evmovdquq(Address(avx512_htbl, 16 * 4), ZT8, Assembler::AVX_512bit);
  gfmul_avx512(ZT7, ZT5);
  evmovdquq(Address(avx512_htbl, 16 * 0), ZT7, Assembler::AVX_512bit);
  ret(0);
1366}

1368#define vclmul_reduce(out, poly, hi128, lo128, tmp0, tmp1)evpclmulqdq(tmp0, poly, lo128, 0x01, Assembler::AVX_512bit); vpslldq
(tmp0, tmp0, 8, Assembler::AVX_512bit); evpxorq(tmp0, lo128, tmp0
, Assembler::AVX_512bit); evpclmulqdq(tmp1, poly, tmp0, 0x00,
 Assembler::AVX_512bit); vpsrldq(tmp1, tmp1, 4, Assembler::AVX_512bit
); evpclmulqdq(out, poly, tmp0, 0x10, Assembler::AVX_512bit);
 vpslldq(out, out, 4, Assembler::AVX_512bit); vpternlogq(out,
 0x96, tmp1, hi128, Assembler::AVX_512bit); \
1369evpclmulqdq(tmp0, poly, lo128, 0x01, Assembler::AVX_512bit); \
1370vpslldq(tmp0, tmp0, 8, Assembler::AVX_512bit); \
1371evpxorq(tmp0, lo128, tmp0, Assembler::AVX_512bit); \
1372evpclmulqdq(tmp1, poly, tmp0, 0x00, Assembler::AVX_512bit); \
1373vpsrldq(tmp1, tmp1, 4, Assembler::AVX_512bit); \
1374evpclmulqdq(out, poly, tmp0, 0x10, Assembler::AVX_512bit); \
1375vpslldq(out, out, 4, Assembler::AVX_512bit); \
1376vpternlogq(out, 0x96, tmp1, hi128, Assembler::AVX_512bit); \

1378#define vhpxori4x128(reg, tmp)vextracti64x4(tmp, reg, 1); evpxorq(reg, reg, tmp, Assembler::
AVX_256bit); vextracti32x4(tmp, reg, 1); evpxorq(reg, reg, tmp
, Assembler::AVX_128bit); \
1379vextracti64x4(tmp, reg, 1); \
1380evpxorq(reg, reg, tmp, Assembler::AVX_256bit); \
1381vextracti32x4(tmp, reg, 1); \
1382evpxorq(reg, reg, tmp, Assembler::AVX_128bit); \

1384#define roundEncode(key, dst1, dst2, dst3, dst4)vaesenc(dst1, dst1, key, Assembler::AVX_512bit); vaesenc(dst2
, dst2, key, Assembler::AVX_512bit); vaesenc(dst3, dst3, key,
 Assembler::AVX_512bit); vaesenc(dst4, dst4, key, Assembler::
AVX_512bit); \
1385vaesenc(dst1, dst1, key, Assembler::AVX_512bit); \
1386vaesenc(dst2, dst2, key, Assembler::AVX_512bit); \
1387vaesenc(dst3, dst3, key, Assembler::AVX_512bit); \
1388vaesenc(dst4, dst4, key, Assembler::AVX_512bit); \

1390#define lastroundEncode(key, dst1, dst2, dst3, dst4)vaesenclast(dst1, dst1, key, Assembler::AVX_512bit); vaesenclast
(dst2, dst2, key, Assembler::AVX_512bit); vaesenclast(dst3, dst3
, key, Assembler::AVX_512bit); vaesenclast(dst4, dst4, key, Assembler
::AVX_512bit); \
1391vaesenclast(dst1, dst1, key, Assembler::AVX_512bit); \
1392vaesenclast(dst2, dst2, key, Assembler::AVX_512bit); \
1393vaesenclast(dst3, dst3, key, Assembler::AVX_512bit); \
1394vaesenclast(dst4, dst4, key, Assembler::AVX_512bit); \

1396#define storeData(dst, position, src1, src2, src3, src4)evmovdquq(Address(dst, position, Address::times_1, 0 * 64), src1
, Assembler::AVX_512bit); evmovdquq(Address(dst, position, Address
::times_1, 1 * 64), src2, Assembler::AVX_512bit); evmovdquq(Address
(dst, position, Address::times_1, 2 * 64), src3, Assembler::AVX_512bit
); evmovdquq(Address(dst, position, Address::times_1, 3 * 64)
, src4, Assembler::AVX_512bit); \
1397evmovdquq(Address(dst, position, Address::times_1, 0 * 64), src1, Assembler::AVX_512bit); \
1398evmovdquq(Address(dst, position, Address::times_1, 1 * 64), src2, Assembler::AVX_512bit); \
1399evmovdquq(Address(dst, position, Address::times_1, 2 * 64), src3, Assembler::AVX_512bit); \
1400evmovdquq(Address(dst, position, Address::times_1, 3 * 64), src4, Assembler::AVX_512bit); \

1402#define loadData(src, position, dst1, dst2, dst3, dst4)evmovdquq(dst1, Address(src, position, Address::times_1, 0 * 64
), Assembler::AVX_512bit); evmovdquq(dst2, Address(src, position
, Address::times_1, 1 * 64), Assembler::AVX_512bit); evmovdquq
(dst3, Address(src, position, Address::times_1, 2 * 64), Assembler
::AVX_512bit); evmovdquq(dst4, Address(src, position, Address
::times_1, 3 * 64), Assembler::AVX_512bit); \
1403evmovdquq(dst1, Address(src, position, Address::times_1, 0 * 64), Assembler::AVX_512bit); \
1404evmovdquq(dst2, Address(src, position, Address::times_1, 1 * 64), Assembler::AVX_512bit); \
1405evmovdquq(dst3, Address(src, position, Address::times_1, 2 * 64), Assembler::AVX_512bit); \
1406evmovdquq(dst4, Address(src, position, Address::times_1, 3 * 64), Assembler::AVX_512bit); \

1408#define carrylessMultiply(dst00, dst01, dst10, dst11, ghdata, hkey)evpclmulqdq(dst00, ghdata, hkey, 0x00, Assembler::AVX_512bit)
; evpclmulqdq(dst01, ghdata, hkey, 0x01, Assembler::AVX_512bit
); evpclmulqdq(dst10, ghdata, hkey, 0x10, Assembler::AVX_512bit
); evpclmulqdq(dst11, ghdata, hkey, 0x11, Assembler::AVX_512bit
); \
1409evpclmulqdq(dst00, ghdata, hkey, 0x00, Assembler::AVX_512bit); \
1410evpclmulqdq(dst01, ghdata, hkey, 0x01, Assembler::AVX_512bit); \
1411evpclmulqdq(dst10, ghdata, hkey, 0x10, Assembler::AVX_512bit); \
1412evpclmulqdq(dst11, ghdata, hkey, 0x11, Assembler::AVX_512bit); \

1414#define shuffleExorRnd1Key(dst0, dst1, dst2, dst3, shufmask, rndkey)vpshufb(dst0, dst0, shufmask, Assembler::AVX_512bit); evpxorq
(dst0, dst0, rndkey, Assembler::AVX_512bit); vpshufb(dst1, dst1
, shufmask, Assembler::AVX_512bit); evpxorq(dst1, dst1, rndkey
, Assembler::AVX_512bit); vpshufb(dst2, dst2, shufmask, Assembler
::AVX_512bit); evpxorq(dst2, dst2, rndkey, Assembler::AVX_512bit
); vpshufb(dst3, dst3, shufmask, Assembler::AVX_512bit); evpxorq
(dst3, dst3, rndkey, Assembler::AVX_512bit); \
1415vpshufb(dst0, dst0, shufmask, Assembler::AVX_512bit); \
1416evpxorq(dst0, dst0, rndkey, Assembler::AVX_512bit); \
1417vpshufb(dst1, dst1, shufmask, Assembler::AVX_512bit); \
1418evpxorq(dst1, dst1, rndkey, Assembler::AVX_512bit); \
1419vpshufb(dst2, dst2, shufmask, Assembler::AVX_512bit); \
1420evpxorq(dst2, dst2, rndkey, Assembler::AVX_512bit); \
1421vpshufb(dst3, dst3, shufmask, Assembler::AVX_512bit); \
1422evpxorq(dst3, dst3, rndkey, Assembler::AVX_512bit); \

1424#define xorBeforeStore(dst0, dst1, dst2, dst3, src0, src1, src2, src3)evpxorq(dst0, dst0, src0, Assembler::AVX_512bit); evpxorq(dst1
, dst1, src1, Assembler::AVX_512bit); evpxorq(dst2, dst2, src2
, Assembler::AVX_512bit); evpxorq(dst3, dst3, src3, Assembler
::AVX_512bit); \
1425evpxorq(dst0, dst0, src0, Assembler::AVX_512bit); \
1426evpxorq(dst1, dst1, src1, Assembler::AVX_512bit); \
1427evpxorq(dst2, dst2, src2, Assembler::AVX_512bit); \
1428evpxorq(dst3, dst3, src3, Assembler::AVX_512bit); \

1430#define xorGHASH(dst0, dst1, dst2, dst3, src02, src03, src12, src13, src22, src23, src32, src33)vpternlogq(dst0, 0x96, src02, src03, Assembler::AVX_512bit); vpternlogq
(dst1, 0x96, src12, src13, Assembler::AVX_512bit); vpternlogq
(dst2, 0x96, src22, src23, Assembler::AVX_512bit); vpternlogq
(dst3, 0x96, src32, src33, Assembler::AVX_512bit); \
1431vpternlogq(dst0, 0x96, src02, src03, Assembler::AVX_512bit); \
1432vpternlogq(dst1, 0x96, src12, src13, Assembler::AVX_512bit); \
1433vpternlogq(dst2, 0x96, src22, src23, Assembler::AVX_512bit); \
1434vpternlogq(dst3, 0x96, src32, src33, Assembler::AVX_512bit); \

1436void MacroAssembler::ghash16_encrypt16_parallel(Register key, Register subkeyHtbl, XMMRegister ctr_blockx, XMMRegister aad_hashx,
  Register in, Register out, Register data, Register pos, bool first_time_reduction, XMMRegister addmask, bool ghash_input, Register rounds,
  Register ghash_pos, bool final_reduction, int i, XMMRegister counter_inc_mask) {

  Label AES_192, AES_256, LAST_AES_RND;
  const XMMRegister ZTMP0 = xmm0;
  const XMMRegister ZTMP1 = xmm3;
  const XMMRegister ZTMP2 = xmm4;
  const XMMRegister ZTMP3 = xmm5;
  const XMMRegister ZTMP5 = xmm7;
  const XMMRegister ZTMP6 = xmm10;
  const XMMRegister ZTMP7 = xmm11;
  const XMMRegister ZTMP8 = xmm12;
  const XMMRegister ZTMP9 = xmm13;
  const XMMRegister ZTMP10 = xmm15;
  const XMMRegister ZTMP11 = xmm16;
  const XMMRegister ZTMP12 = xmm17;

  const XMMRegister ZTMP13 = xmm19;
  const XMMRegister ZTMP14 = xmm20;
  const XMMRegister ZTMP15 = xmm21;
  const XMMRegister ZTMP16 = xmm30;
  const XMMRegister ZTMP17 = xmm31;
  const XMMRegister ZTMP18 = xmm1;
  const XMMRegister ZTMP19 = xmm2;
  const XMMRegister ZTMP20 = xmm8;
  const XMMRegister ZTMP21 = xmm22;
  const XMMRegister ZTMP22 = xmm23;

  // Pre increment counters
  vpaddd(ZTMP0, ctr_blockx, counter_inc_mask, Assembler::AVX_512bit);
  vpaddd(ZTMP1, ZTMP0, counter_inc_mask, Assembler::AVX_512bit);
  vpaddd(ZTMP2, ZTMP1, counter_inc_mask, Assembler::AVX_512bit);
  vpaddd(ZTMP3, ZTMP2, counter_inc_mask, Assembler::AVX_512bit);
  // Save counter value
  evmovdquq(ctr_blockx, ZTMP3, Assembler::AVX_512bit);

  // Reuse ZTMP17 / ZTMP18 for loading AES Keys
  // Pre-load AES round keys
  ev_load_key(ZTMP17, key, 0, xmm29);
  ev_load_key(ZTMP18, key, 1 * 16, xmm29);

  // ZTMP19 & ZTMP20 used for loading hash key
  // Pre-load hash key
  evmovdquq(ZTMP19, Address(subkeyHtbl, i * 64), Assembler::AVX_512bit);
  evmovdquq(ZTMP20, Address(subkeyHtbl, ++i * 64), Assembler::AVX_512bit);
  // Load data for computing ghash
  evmovdquq(ZTMP21, Address(data, ghash_pos, Address::times_1, 0 * 64), Assembler::AVX_512bit);
  vpshufb(ZTMP21, ZTMP21, xmm24, Assembler::AVX_512bit);

  // Xor cipher block 0 with input ghash, if available
  if (ghash_input) {
      evpxorq(ZTMP21, ZTMP21, aad_hashx, Assembler::AVX_512bit);
  }
  // Load data for computing ghash
  evmovdquq(ZTMP22, Address(data, ghash_pos, Address::times_1, 1 * 64), Assembler::AVX_512bit);
  vpshufb(ZTMP22, ZTMP22, xmm24, Assembler::AVX_512bit);

  // stitch AES rounds with GHASH
  // AES round 0, xmm24 has shuffle mask
  shuffleExorRnd1Key(ZTMP0, ZTMP1, ZTMP2, ZTMP3, xmm24, ZTMP17)vpshufb(ZTMP0, ZTMP0, xmm24, Assembler::AVX_512bit); evpxorq(
ZTMP0, ZTMP0, ZTMP17, Assembler::AVX_512bit); vpshufb(ZTMP1, ZTMP1
, xmm24, Assembler::AVX_512bit); evpxorq(ZTMP1, ZTMP1, ZTMP17
, Assembler::AVX_512bit); vpshufb(ZTMP2, ZTMP2, xmm24, Assembler
::AVX_512bit); evpxorq(ZTMP2, ZTMP2, ZTMP17, Assembler::AVX_512bit
); vpshufb(ZTMP3, ZTMP3, xmm24, Assembler::AVX_512bit); evpxorq
(ZTMP3, ZTMP3, ZTMP17, Assembler::AVX_512bit);;
  // Reuse ZTMP17 / ZTMP18 for loading remaining AES Keys
  ev_load_key(ZTMP17, key, 2 * 16, xmm29);
  // GHASH 4 blocks
  carrylessMultiply(ZTMP6, ZTMP7, ZTMP8, ZTMP5, ZTMP21, ZTMP19)evpclmulqdq(ZTMP6, ZTMP21, ZTMP19, 0x00, Assembler::AVX_512bit
); evpclmulqdq(ZTMP7, ZTMP21, ZTMP19, 0x01, Assembler::AVX_512bit
); evpclmulqdq(ZTMP8, ZTMP21, ZTMP19, 0x10, Assembler::AVX_512bit
); evpclmulqdq(ZTMP5, ZTMP21, ZTMP19, 0x11, Assembler::AVX_512bit
);;
  // Load the next hkey and Ghash data
  evmovdquq(ZTMP19, Address(subkeyHtbl, ++i * 64), Assembler::AVX_512bit);
  evmovdquq(ZTMP21, Address(data, ghash_pos, Address::times_1, 2 * 64), Assembler::AVX_512bit);
  vpshufb(ZTMP21, ZTMP21, xmm24, Assembler::AVX_512bit);

  // AES round 1
  roundEncode(ZTMP18, ZTMP0, ZTMP1, ZTMP2, ZTMP3)vaesenc(ZTMP0, ZTMP0, ZTMP18, Assembler::AVX_512bit); vaesenc
(ZTMP1, ZTMP1, ZTMP18, Assembler::AVX_512bit); vaesenc(ZTMP2,
 ZTMP2, ZTMP18, Assembler::AVX_512bit); vaesenc(ZTMP3, ZTMP3,
 ZTMP18, Assembler::AVX_512bit);;
  ev_load_key(ZTMP18, key, 3 * 16, xmm29);

  // GHASH 4 blocks(11 to 8)
  carrylessMultiply(ZTMP10, ZTMP12, ZTMP11, ZTMP9, ZTMP22, ZTMP20)evpclmulqdq(ZTMP10, ZTMP22, ZTMP20, 0x00, Assembler::AVX_512bit
); evpclmulqdq(ZTMP12, ZTMP22, ZTMP20, 0x01, Assembler::AVX_512bit
); evpclmulqdq(ZTMP11, ZTMP22, ZTMP20, 0x10, Assembler::AVX_512bit
); evpclmulqdq(ZTMP9, ZTMP22, ZTMP20, 0x11, Assembler::AVX_512bit
);;
  // Load the next hkey and GDATA
  evmovdquq(ZTMP20, Address(subkeyHtbl, ++i * 64), Assembler::AVX_512bit);
  evmovdquq(ZTMP22, Address(data, ghash_pos, Address::times_1, 3 * 64), Assembler::AVX_512bit);
  vpshufb(ZTMP22, ZTMP22, xmm24, Assembler::AVX_512bit);

  // AES round 2
  roundEncode(ZTMP17, ZTMP0, ZTMP1, ZTMP2, ZTMP3)vaesenc(ZTMP0, ZTMP0, ZTMP17, Assembler::AVX_512bit); vaesenc
(ZTMP1, ZTMP1, ZTMP17, Assembler::AVX_512bit); vaesenc(ZTMP2,
 ZTMP2, ZTMP17, Assembler::AVX_512bit); vaesenc(ZTMP3, ZTMP3,
 ZTMP17, Assembler::AVX_512bit);;
  ev_load_key(ZTMP17, key, 4 * 16, xmm29);

  // GHASH 4 blocks(7 to 4)
  carrylessMultiply(ZTMP14, ZTMP16, ZTMP15, ZTMP13, ZTMP21, ZTMP19)evpclmulqdq(ZTMP14, ZTMP21, ZTMP19, 0x00, Assembler::AVX_512bit
); evpclmulqdq(ZTMP16, ZTMP21, ZTMP19, 0x01, Assembler::AVX_512bit
); evpclmulqdq(ZTMP15, ZTMP21, ZTMP19, 0x10, Assembler::AVX_512bit
); evpclmulqdq(ZTMP13, ZTMP21, ZTMP19, 0x11, Assembler::AVX_512bit
);;
  // AES rounds 3
  roundEncode(ZTMP18, ZTMP0, ZTMP1, ZTMP2, ZTMP3)vaesenc(ZTMP0, ZTMP0, ZTMP18, Assembler::AVX_512bit); vaesenc
(ZTMP1, ZTMP1, ZTMP18, Assembler::AVX_512bit); vaesenc(ZTMP2,
 ZTMP2, ZTMP18, Assembler::AVX_512bit); vaesenc(ZTMP3, ZTMP3,
 ZTMP18, Assembler::AVX_512bit);;
  ev_load_key(ZTMP18, key, 5 * 16, xmm29);

  // Gather(XOR) GHASH for 12 blocks
  xorGHASH(ZTMP5, ZTMP6, ZTMP8, ZTMP7, ZTMP9, ZTMP13, ZTMP10, ZTMP14, ZTMP12, ZTMP16, ZTMP11, ZTMP15)vpternlogq(ZTMP5, 0x96, ZTMP9, ZTMP13, Assembler::AVX_512bit)
; vpternlogq(ZTMP6, 0x96, ZTMP10, ZTMP14, Assembler::AVX_512bit
); vpternlogq(ZTMP8, 0x96, ZTMP12, ZTMP16, Assembler::AVX_512bit
); vpternlogq(ZTMP7, 0x96, ZTMP11, ZTMP15, Assembler::AVX_512bit
);;

  // AES rounds 4
  roundEncode(ZTMP17, ZTMP0, ZTMP1, ZTMP2, ZTMP3)vaesenc(ZTMP0, ZTMP0, ZTMP17, Assembler::AVX_512bit); vaesenc
(ZTMP1, ZTMP1, ZTMP17, Assembler::AVX_512bit); vaesenc(ZTMP2,
 ZTMP2, ZTMP17, Assembler::AVX_512bit); vaesenc(ZTMP3, ZTMP3,
 ZTMP17, Assembler::AVX_512bit);;
  ev_load_key(ZTMP17, key, 6 * 16, xmm29);

  // load plain / cipher text(recycle registers)
  loadData(in, pos, ZTMP13, ZTMP14, ZTMP15, ZTMP16)evmovdquq(ZTMP13, Address(in, pos, Address::times_1, 0 * 64),
 Assembler::AVX_512bit); evmovdquq(ZTMP14, Address(in, pos, Address
::times_1, 1 * 64), Assembler::AVX_512bit); evmovdquq(ZTMP15,
 Address(in, pos, Address::times_1, 2 * 64), Assembler::AVX_512bit
); evmovdquq(ZTMP16, Address(in, pos, Address::times_1, 3 * 64
), Assembler::AVX_512bit);;

  // AES rounds 5
  roundEncode(ZTMP18, ZTMP0, ZTMP1, ZTMP2, ZTMP3)vaesenc(ZTMP0, ZTMP0, ZTMP18, Assembler::AVX_512bit); vaesenc
(ZTMP1, ZTMP1, ZTMP18, Assembler::AVX_512bit); vaesenc(ZTMP2,
 ZTMP2, ZTMP18, Assembler::AVX_512bit); vaesenc(ZTMP3, ZTMP3,
 ZTMP18, Assembler::AVX_512bit);;
  ev_load_key(ZTMP18, key, 7 * 16, xmm29);
  // GHASH 4 blocks(3 to 0)
  carrylessMultiply(ZTMP10, ZTMP12, ZTMP11, ZTMP9, ZTMP22, ZTMP20)evpclmulqdq(ZTMP10, ZTMP22, ZTMP20, 0x00, Assembler::AVX_512bit
); evpclmulqdq(ZTMP12, ZTMP22, ZTMP20, 0x01, Assembler::AVX_512bit
); evpclmulqdq(ZTMP11, ZTMP22, ZTMP20, 0x10, Assembler::AVX_512bit
); evpclmulqdq(ZTMP9, ZTMP22, ZTMP20, 0x11, Assembler::AVX_512bit
);;

  //  AES round 6
  roundEncode(ZTMP17, ZTMP0, ZTMP1, ZTMP2, ZTMP3)vaesenc(ZTMP0, ZTMP0, ZTMP17, Assembler::AVX_512bit); vaesenc
(ZTMP1, ZTMP1, ZTMP17, Assembler::AVX_512bit); vaesenc(ZTMP2,
 ZTMP2, ZTMP17, Assembler::AVX_512bit); vaesenc(ZTMP3, ZTMP3,
 ZTMP17, Assembler::AVX_512bit);;
  ev_load_key(ZTMP17, key, 8 * 16, xmm29);

  // gather GHASH in ZTMP6(low) and ZTMP5(high)
  if (first_time_reduction) {
      vpternlogq(ZTMP7, 0x96, ZTMP8, ZTMP12, Assembler::AVX_512bit);
      evpxorq(xmm25, ZTMP7, ZTMP11, Assembler::AVX_512bit);
      evpxorq(xmm27, ZTMP5, ZTMP9, Assembler::AVX_512bit);
      evpxorq(xmm26, ZTMP6, ZTMP10, Assembler::AVX_512bit);
  }
  else if (!first_time_reduction && !final_reduction) {
      xorGHASH(ZTMP7, xmm25, xmm27, xmm26, ZTMP8, ZTMP12, ZTMP7, ZTMP11, ZTMP5, ZTMP9, ZTMP6, ZTMP10)vpternlogq(ZTMP7, 0x96, ZTMP8, ZTMP12, Assembler::AVX_512bit)
; vpternlogq(xmm25, 0x96, ZTMP7, ZTMP11, Assembler::AVX_512bit
); vpternlogq(xmm27, 0x96, ZTMP5, ZTMP9, Assembler::AVX_512bit
); vpternlogq(xmm26, 0x96, ZTMP6, ZTMP10, Assembler::AVX_512bit
);;
  }

  if (final_reduction) {
      // Phase one: Add mid products together
      // Also load polynomial constant for reduction
      vpternlogq(ZTMP7, 0x96, ZTMP8, ZTMP12, Assembler::AVX_512bit);
      vpternlogq(ZTMP7, 0x96, xmm25, ZTMP11, Assembler::AVX_512bit);
      vpsrldq(ZTMP11, ZTMP7, 8, Assembler::AVX_512bit);
      vpslldq(ZTMP7, ZTMP7, 8, Assembler::AVX_512bit);
      evmovdquq(ZTMP12, ExternalAddress(StubRoutines::x86::ghash_polynomial512_addr()), Assembler::AVX_512bit, rbx);
  }
  // AES round 7
  roundEncode(ZTMP18, ZTMP0, ZTMP1, ZTMP2, ZTMP3)vaesenc(ZTMP0, ZTMP0, ZTMP18, Assembler::AVX_512bit); vaesenc
(ZTMP1, ZTMP1, ZTMP18, Assembler::AVX_512bit); vaesenc(ZTMP2,
 ZTMP2, ZTMP18, Assembler::AVX_512bit); vaesenc(ZTMP3, ZTMP3,
 ZTMP18, Assembler::AVX_512bit);;
  ev_load_key(ZTMP18, key, 9 * 16, xmm29);
  if (final_reduction) {
      vpternlogq(ZTMP5, 0x96, ZTMP9, ZTMP11, Assembler::AVX_512bit);
      evpxorq(ZTMP5, ZTMP5, xmm27, Assembler::AVX_512bit);
      vpternlogq(ZTMP6, 0x96, ZTMP10, ZTMP7, Assembler::AVX_512bit);
      evpxorq(ZTMP6, ZTMP6, xmm26, Assembler::AVX_512bit);
  }
  // AES round 8
  roundEncode(ZTMP17, ZTMP0, ZTMP1, ZTMP2, ZTMP3)vaesenc(ZTMP0, ZTMP0, ZTMP17, Assembler::AVX_512bit); vaesenc
(ZTMP1, ZTMP1, ZTMP17, Assembler::AVX_512bit); vaesenc(ZTMP2,
 ZTMP2, ZTMP17, Assembler::AVX_512bit); vaesenc(ZTMP3, ZTMP3,
 ZTMP17, Assembler::AVX_512bit);;
  ev_load_key(ZTMP17, key, 10 * 16, xmm29);

  // Horizontal xor of low and high 4*128
  if (final_reduction) {
      vhpxori4x128(ZTMP5, ZTMP9)vextracti64x4(ZTMP9, ZTMP5, 1); evpxorq(ZTMP5, ZTMP5, ZTMP9, Assembler
::AVX_256bit); vextracti32x4(ZTMP9, ZTMP5, 1); evpxorq(ZTMP5,
 ZTMP5, ZTMP9, Assembler::AVX_128bit);;
      vhpxori4x128(ZTMP6, ZTMP10)vextracti64x4(ZTMP10, ZTMP6, 1); evpxorq(ZTMP6, ZTMP6, ZTMP10
, Assembler::AVX_256bit); vextracti32x4(ZTMP10, ZTMP6, 1); evpxorq
(ZTMP6, ZTMP6, ZTMP10, Assembler::AVX_128bit);;
  }
  // AES round 9
  roundEncode(ZTMP18, ZTMP0, ZTMP1, ZTMP2, ZTMP3)vaesenc(ZTMP0, ZTMP0, ZTMP18, Assembler::AVX_512bit); vaesenc
(ZTMP1, ZTMP1, ZTMP18, Assembler::AVX_512bit); vaesenc(ZTMP2,
 ZTMP2, ZTMP18, Assembler::AVX_512bit); vaesenc(ZTMP3, ZTMP3,
 ZTMP18, Assembler::AVX_512bit);;
  // First phase of reduction
  if (final_reduction) {
      evpclmulqdq(ZTMP10, ZTMP12, ZTMP6, 0x01, Assembler::AVX_128bit);
      vpslldq(ZTMP10, ZTMP10, 8, Assembler::AVX_128bit);
      evpxorq(ZTMP10, ZTMP6, ZTMP10, Assembler::AVX_128bit);
  }
  cmpl(rounds, 52);
  jcc(Assembler::greaterEqual, AES_192);
  jmp(LAST_AES_RND);
  // AES rounds upto 11 (AES192) or 13 (AES256)
  bind(AES_192);
  roundEncode(ZTMP17, ZTMP0, ZTMP1, ZTMP2, ZTMP3)vaesenc(ZTMP0, ZTMP0, ZTMP17, Assembler::AVX_512bit); vaesenc
(ZTMP1, ZTMP1, ZTMP17, Assembler::AVX_512bit); vaesenc(ZTMP2,
 ZTMP2, ZTMP17, Assembler::AVX_512bit); vaesenc(ZTMP3, ZTMP3,
 ZTMP17, Assembler::AVX_512bit);;
  ev_load_key(ZTMP18, key, 11 * 16, xmm29);
  roundEncode(ZTMP18, ZTMP0, ZTMP1, ZTMP2, ZTMP3)vaesenc(ZTMP0, ZTMP0, ZTMP18, Assembler::AVX_512bit); vaesenc
(ZTMP1, ZTMP1, ZTMP18, Assembler::AVX_512bit); vaesenc(ZTMP2,
 ZTMP2, ZTMP18, Assembler::AVX_512bit); vaesenc(ZTMP3, ZTMP3,
 ZTMP18, Assembler::AVX_512bit);;
  ev_load_key(ZTMP17, key, 12 * 16, xmm29);
  cmpl(rounds, 60);
  jcc(Assembler::aboveEqual, AES_256);
  jmp(LAST_AES_RND);

  bind(AES_256);
  roundEncode(ZTMP17, ZTMP0, ZTMP1, ZTMP2, ZTMP3)vaesenc(ZTMP0, ZTMP0, ZTMP17, Assembler::AVX_512bit); vaesenc
(ZTMP1, ZTMP1, ZTMP17, Assembler::AVX_512bit); vaesenc(ZTMP2,
 ZTMP2, ZTMP17, Assembler::AVX_512bit); vaesenc(ZTMP3, ZTMP3,
 ZTMP17, Assembler::AVX_512bit);;
  ev_load_key(ZTMP18, key, 13 * 16, xmm29);
  roundEncode(ZTMP18, ZTMP0, ZTMP1, ZTMP2, ZTMP3)vaesenc(ZTMP0, ZTMP0, ZTMP18, Assembler::AVX_512bit); vaesenc
(ZTMP1, ZTMP1, ZTMP18, Assembler::AVX_512bit); vaesenc(ZTMP2,
 ZTMP2, ZTMP18, Assembler::AVX_512bit); vaesenc(ZTMP3, ZTMP3,
 ZTMP18, Assembler::AVX_512bit);;
  ev_load_key(ZTMP17, key, 14 * 16, xmm29);

  bind(LAST_AES_RND);
  // Second phase of reduction
  if (final_reduction) {
      evpclmulqdq(ZTMP9, ZTMP12, ZTMP10, 0x00, Assembler::AVX_128bit);
      vpsrldq(ZTMP9, ZTMP9, 4, Assembler::AVX_128bit); // Shift-R 1-DW to obtain 2-DWs shift-R
      evpclmulqdq(ZTMP11, ZTMP12, ZTMP10, 0x10, Assembler::AVX_128bit);
      vpslldq(ZTMP11, ZTMP11, 4, Assembler::AVX_128bit); // Shift-L 1-DW for result
      // ZTMP5 = ZTMP5 X ZTMP11 X ZTMP9
      vpternlogq(ZTMP5, 0x96, ZTMP11, ZTMP9, Assembler::AVX_128bit);
  }
  // Last AES round
  lastroundEncode(ZTMP17, ZTMP0, ZTMP1, ZTMP2, ZTMP3)vaesenclast(ZTMP0, ZTMP0, ZTMP17, Assembler::AVX_512bit); vaesenclast
(ZTMP1, ZTMP1, ZTMP17, Assembler::AVX_512bit); vaesenclast(ZTMP2
, ZTMP2, ZTMP17, Assembler::AVX_512bit); vaesenclast(ZTMP3, ZTMP3
, ZTMP17, Assembler::AVX_512bit);;
  // XOR against plain / cipher text
  xorBeforeStore(ZTMP0, ZTMP1, ZTMP2, ZTMP3, ZTMP13, ZTMP14, ZTMP15, ZTMP16)evpxorq(ZTMP0, ZTMP0, ZTMP13, Assembler::AVX_512bit); evpxorq
(ZTMP1, ZTMP1, ZTMP14, Assembler::AVX_512bit); evpxorq(ZTMP2,
 ZTMP2, ZTMP15, Assembler::AVX_512bit); evpxorq(ZTMP3, ZTMP3,
 ZTMP16, Assembler::AVX_512bit);;
  // store cipher / plain text
  storeData(out, pos, ZTMP0, ZTMP1, ZTMP2, ZTMP3)evmovdquq(Address(out, pos, Address::times_1, 0 * 64), ZTMP0,
 Assembler::AVX_512bit); evmovdquq(Address(out, pos, Address::
times_1, 1 * 64), ZTMP1, Assembler::AVX_512bit); evmovdquq(Address
(out, pos, Address::times_1, 2 * 64), ZTMP2, Assembler::AVX_512bit
); evmovdquq(Address(out, pos, Address::times_1, 3 * 64), ZTMP3
, Assembler::AVX_512bit);;
1628}

1630void MacroAssembler::aesgcm_encrypt(Register in, Register len, Register ct, Register out, Register key,
                                  Register state, Register subkeyHtbl, Register avx512_subkeyHtbl, Register counter) {
  Label ENC_DEC_DONE, GENERATE_HTBL_48_BLKS, AES_192, AES_256, STORE_CT, GHASH_LAST_32,
        AES_32_BLOCKS, GHASH_AES_PARALLEL, LOOP, ACCUMULATE, GHASH_16_AES_16;
  const XMMRegister CTR_BLOCKx = xmm9;
  const XMMRegister AAD_HASHx = xmm14;
  const Register pos = rax;
1
'pos' initialized to a null pointer value→
  const Register rounds = r15;
  Register ghash_pos;
1639#ifndef _WIN64
  ghash_pos = r14;
1641#else
  ghash_pos = r11;
1643#endif // !_WIN64
  const XMMRegister ZTMP0 = xmm0;
  const XMMRegister ZTMP1 = xmm3;
  const XMMRegister ZTMP2 = xmm4;
  const XMMRegister ZTMP3 = xmm5;
  const XMMRegister ZTMP4 = xmm6;
  const XMMRegister ZTMP5 = xmm7;
  const XMMRegister ZTMP6 = xmm10;
  const XMMRegister ZTMP7 = xmm11;
  const XMMRegister ZTMP8 = xmm12;
  const XMMRegister ZTMP9 = xmm13;
  const XMMRegister ZTMP10 = xmm15;
  const XMMRegister ZTMP11 = xmm16;
  const XMMRegister ZTMP12 = xmm17;
  const XMMRegister ZTMP13 = xmm19;
  const XMMRegister ZTMP14 = xmm20;
  const XMMRegister ZTMP15 = xmm21;
  const XMMRegister ZTMP16 = xmm30;
  const XMMRegister COUNTER_INC_MASK = xmm18;

  movl(pos, 0); // Total length processed
  // Min data size processed = 768 bytes
  cmpl(len, 768);
  jcc(Assembler::less, ENC_DEC_DONE);

  // Generate 48 constants for htbl
  call(GENERATE_HTBL_48_BLKS, relocInfo::none);
  int index = 0; // Index for choosing subkeyHtbl entry
  movl(ghash_pos, 0); // Pointer for ghash read and store operations

  // Move initial counter value and STATE value into variables
  movdqu(CTR_BLOCKx, Address(counter, 0));
  movdqu(AAD_HASHx, Address(state, 0));
  // Load lswap mask for ghash
  movdqu(xmm24, ExternalAddress(StubRoutines::x86::ghash_long_swap_mask_addr()), rbx);
  // Shuffle input state using lswap mask
  vpshufb(AAD_HASHx, AAD_HASHx, xmm24, Assembler::AVX_128bit);

  // Compute #rounds for AES based on the length of the key array
  movl(rounds, Address(key, arrayOopDesc::length_offset_in_bytes() - arrayOopDesc::base_offset_in_bytes(T_INT)));

  // Broadcast counter value to 512 bit register
  evshufi64x2(CTR_BLOCKx, CTR_BLOCKx, CTR_BLOCKx, 0, Assembler::AVX_512bit);
  // Load counter shuffle mask
  evmovdquq(xmm24, ExternalAddress(StubRoutines::x86::counter_mask_addr()), Assembler::AVX_512bit, rbx);
  // Shuffle counter
  vpshufb(CTR_BLOCKx, CTR_BLOCKx, xmm24, Assembler::AVX_512bit);

  // Load mask for incrementing counter
  evmovdquq(COUNTER_INC_MASK, ExternalAddress(StubRoutines::x86::counter_mask_addr() + 128), Assembler::AVX_512bit, rbx);
  // Pre-increment counter
  vpaddd(ZTMP5, CTR_BLOCKx, ExternalAddress(StubRoutines::x86::counter_mask_addr() + 64), Assembler::AVX_512bit, rbx);
  vpaddd(ZTMP6, ZTMP5, COUNTER_INC_MASK, Assembler::AVX_512bit);
  vpaddd(ZTMP7, ZTMP6, COUNTER_INC_MASK, Assembler::AVX_512bit);
  vpaddd(ZTMP8, ZTMP7, COUNTER_INC_MASK, Assembler::AVX_512bit);

  // Begin 32 blocks of AES processing
  bind(AES_32_BLOCKS);
  // Save incremented counter before overwriting it with AES data
  evmovdquq(CTR_BLOCKx, ZTMP8, Assembler::AVX_512bit);

  // Move 256 bytes of data
  loadData(in, pos, ZTMP0, ZTMP1, ZTMP2, ZTMP3)evmovdquq(ZTMP0, Address(in, pos, Address::times_1, 0 * 64), Assembler
::AVX_512bit); evmovdquq(ZTMP1, Address(in, pos, Address::times_1
, 1 * 64), Assembler::AVX_512bit); evmovdquq(ZTMP2, Address(in
, pos, Address::times_1, 2 * 64), Assembler::AVX_512bit); evmovdquq
(ZTMP3, Address(in, pos, Address::times_1, 3 * 64), Assembler
::AVX_512bit);;
2
←
Passing null pointer value via 2nd parameter 'index'→
3
←
Calling constructor for 'Address'→
  // Load key shuffle mask
  movdqu(xmm29, ExternalAddress(StubRoutines::x86::key_shuffle_mask_addr()), rbx);
  // Load 0th AES round key
  ev_load_key(ZTMP4, key, 0, xmm29);
  // AES-ROUND0, xmm24 has the shuffle mask
  shuffleExorRnd1Key(ZTMP5, ZTMP6, ZTMP7, ZTMP8, xmm24, ZTMP4)vpshufb(ZTMP5, ZTMP5, xmm24, Assembler::AVX_512bit); evpxorq(
ZTMP5, ZTMP5, ZTMP4, Assembler::AVX_512bit); vpshufb(ZTMP6, ZTMP6
, xmm24, Assembler::AVX_512bit); evpxorq(ZTMP6, ZTMP6, ZTMP4,
 Assembler::AVX_512bit); vpshufb(ZTMP7, ZTMP7, xmm24, Assembler
::AVX_512bit); evpxorq(ZTMP7, ZTMP7, ZTMP4, Assembler::AVX_512bit
); vpshufb(ZTMP8, ZTMP8, xmm24, Assembler::AVX_512bit); evpxorq
(ZTMP8, ZTMP8, ZTMP4, Assembler::AVX_512bit);;

  for (int j = 1; j < 10; j++) {
      ev_load_key(ZTMP4, key, j * 16, xmm29);
      roundEncode(ZTMP4, ZTMP5, ZTMP6, ZTMP7, ZTMP8)vaesenc(ZTMP5, ZTMP5, ZTMP4, Assembler::AVX_512bit); vaesenc(
ZTMP6, ZTMP6, ZTMP4, Assembler::AVX_512bit); vaesenc(ZTMP7, ZTMP7
, ZTMP4, Assembler::AVX_512bit); vaesenc(ZTMP8, ZTMP8, ZTMP4,
 Assembler::AVX_512bit);;
  }
  ev_load_key(ZTMP4, key, 10 * 16, xmm29);
  // AES rounds upto 11 (AES192) or 13 (AES256)
  cmpl(rounds, 52);
  jcc(Assembler::greaterEqual, AES_192);
  lastroundEncode(ZTMP4, ZTMP5, ZTMP6, ZTMP7, ZTMP8)vaesenclast(ZTMP5, ZTMP5, ZTMP4, Assembler::AVX_512bit); vaesenclast
(ZTMP6, ZTMP6, ZTMP4, Assembler::AVX_512bit); vaesenclast(ZTMP7
, ZTMP7, ZTMP4, Assembler::AVX_512bit); vaesenclast(ZTMP8, ZTMP8
, ZTMP4, Assembler::AVX_512bit);;
  jmp(STORE_CT);

  bind(AES_192);
  roundEncode(ZTMP4, ZTMP5, ZTMP6, ZTMP7, ZTMP8)vaesenc(ZTMP5, ZTMP5, ZTMP4, Assembler::AVX_512bit); vaesenc(
ZTMP6, ZTMP6, ZTMP4, Assembler::AVX_512bit); vaesenc(ZTMP7, ZTMP7
, ZTMP4, Assembler::AVX_512bit); vaesenc(ZTMP8, ZTMP8, ZTMP4,
 Assembler::AVX_512bit);;
  ev_load_key(ZTMP4, key, 11 * 16, xmm29);
  roundEncode(ZTMP4, ZTMP5, ZTMP6, ZTMP7, ZTMP8)vaesenc(ZTMP5, ZTMP5, ZTMP4, Assembler::AVX_512bit); vaesenc(
ZTMP6, ZTMP6, ZTMP4, Assembler::AVX_512bit); vaesenc(ZTMP7, ZTMP7
, ZTMP4, Assembler::AVX_512bit); vaesenc(ZTMP8, ZTMP8, ZTMP4,
 Assembler::AVX_512bit);;
  cmpl(rounds, 60);
  jcc(Assembler::aboveEqual, AES_256);
  ev_load_key(ZTMP4, key, 12 * 16, xmm29);
  lastroundEncode(ZTMP4, ZTMP5, ZTMP6, ZTMP7, ZTMP8)vaesenclast(ZTMP5, ZTMP5, ZTMP4, Assembler::AVX_512bit); vaesenclast
(ZTMP6, ZTMP6, ZTMP4, Assembler::AVX_512bit); vaesenclast(ZTMP7
, ZTMP7, ZTMP4, Assembler::AVX_512bit); vaesenclast(ZTMP8, ZTMP8
, ZTMP4, Assembler::AVX_512bit);;
  jmp(STORE_CT);

  bind(AES_256);
  ev_load_key(ZTMP4, key, 12 * 16, xmm29);
  roundEncode(ZTMP4, ZTMP5, ZTMP6, ZTMP7, ZTMP8)vaesenc(ZTMP5, ZTMP5, ZTMP4, Assembler::AVX_512bit); vaesenc(
ZTMP6, ZTMP6, ZTMP4, Assembler::AVX_512bit); vaesenc(ZTMP7, ZTMP7
, ZTMP4, Assembler::AVX_512bit); vaesenc(ZTMP8, ZTMP8, ZTMP4,
 Assembler::AVX_512bit);;
  ev_load_key(ZTMP4, key, 13 * 16, xmm29);
  roundEncode(ZTMP4, ZTMP5, ZTMP6, ZTMP7, ZTMP8)vaesenc(ZTMP5, ZTMP5, ZTMP4, Assembler::AVX_512bit); vaesenc(
ZTMP6, ZTMP6, ZTMP4, Assembler::AVX_512bit); vaesenc(ZTMP7, ZTMP7
, ZTMP4, Assembler::AVX_512bit); vaesenc(ZTMP8, ZTMP8, ZTMP4,
 Assembler::AVX_512bit);;
  ev_load_key(ZTMP4, key, 14 * 16, xmm29);
  // Last AES round
  lastroundEncode(ZTMP4, ZTMP5, ZTMP6, ZTMP7, ZTMP8)vaesenclast(ZTMP5, ZTMP5, ZTMP4, Assembler::AVX_512bit); vaesenclast
(ZTMP6, ZTMP6, ZTMP4, Assembler::AVX_512bit); vaesenclast(ZTMP7
, ZTMP7, ZTMP4, Assembler::AVX_512bit); vaesenclast(ZTMP8, ZTMP8
, ZTMP4, Assembler::AVX_512bit);;

  bind(STORE_CT);
  // Xor the encrypted key with PT to obtain CT
  xorBeforeStore(ZTMP5, ZTMP6, ZTMP7, ZTMP8, ZTMP0, ZTMP1, ZTMP2, ZTMP3)evpxorq(ZTMP5, ZTMP5, ZTMP0, Assembler::AVX_512bit); evpxorq(
ZTMP6, ZTMP6, ZTMP1, Assembler::AVX_512bit); evpxorq(ZTMP7, ZTMP7
, ZTMP2, Assembler::AVX_512bit); evpxorq(ZTMP8, ZTMP8, ZTMP3,
 Assembler::AVX_512bit);;
  storeData(out, pos, ZTMP5, ZTMP6, ZTMP7, ZTMP8)evmovdquq(Address(out, pos, Address::times_1, 0 * 64), ZTMP5,
 Assembler::AVX_512bit); evmovdquq(Address(out, pos, Address::
times_1, 1 * 64), ZTMP6, Assembler::AVX_512bit); evmovdquq(Address
(out, pos, Address::times_1, 2 * 64), ZTMP7, Assembler::AVX_512bit
); evmovdquq(Address(out, pos, Address::times_1, 3 * 64), ZTMP8
, Assembler::AVX_512bit);;
  // 16 blocks encryption completed
  addl(pos, 256);
  cmpl(pos, 512);
  jcc(Assembler::aboveEqual, GHASH_AES_PARALLEL);
  vpaddd(ZTMP5, CTR_BLOCKx, COUNTER_INC_MASK, Assembler::AVX_512bit);
  vpaddd(ZTMP6, ZTMP5, COUNTER_INC_MASK, Assembler::AVX_512bit);
  vpaddd(ZTMP7, ZTMP6, COUNTER_INC_MASK, Assembler::AVX_512bit);
  vpaddd(ZTMP8, ZTMP7, COUNTER_INC_MASK, Assembler::AVX_512bit);
  jmp(AES_32_BLOCKS);

  bind(GHASH_AES_PARALLEL);
  // Ghash16_encrypt16_parallel takes place in the order with three reduction values:
  // 1) First time -> cipher xor input ghash
  // 2) No reduction -> accumulate multiplication values
  // 3) Final reduction post 48 blocks -> new ghash value is computed for the next round
  // Reduction value = first time
  ghash16_encrypt16_parallel(key, avx512_subkeyHtbl, CTR_BLOCKx, AAD_HASHx, in, out, ct, pos, true, xmm24, true, rounds, ghash_pos, false, index, COUNTER_INC_MASK);
  addl(pos, 256);
  addl(ghash_pos, 256);
  index += 4;

  // At this point we have processed 768 bytes of AES and 256 bytes of GHASH.
  // If the remaining length is less than 768, process remaining 512 bytes of ghash in GHASH_LAST_32 code
  subl(len, 768);
  cmpl(len, 768);
  jcc(Assembler::less, GHASH_LAST_32);

  // AES 16 blocks and GHASH 16 blocks in parallel
  // For multiples of 48 blocks we will do ghash16_encrypt16 interleaved multiple times
  // Reduction value = no reduction means that the carryless multiplication values are accumulated for further calculations
  // Each call uses 4 subkeyHtbl values, so increment the index by 4.
  bind(GHASH_16_AES_16);
  // Reduction value = no reduction
  ghash16_encrypt16_parallel(key, avx512_subkeyHtbl, CTR_BLOCKx, AAD_HASHx, in, out, ct, pos, false, xmm24, false, rounds, ghash_pos, false, index, COUNTER_INC_MASK);
  addl(pos, 256);
  addl(ghash_pos, 256);
  index += 4;
  // Reduction value = final reduction means that the accumulated values have to be reduced as we have completed 48 blocks of ghash
  ghash16_encrypt16_parallel(key, avx512_subkeyHtbl, CTR_BLOCKx, AAD_HASHx, in, out, ct, pos, false, xmm24, false, rounds, ghash_pos, true, index, COUNTER_INC_MASK);
  addl(pos, 256);
  addl(ghash_pos, 256);
  // Calculated ghash value needs to be moved to AAD_HASHX so that we can restart the ghash16-aes16 pipeline
  movdqu(AAD_HASHx, ZTMP5);
  index = 0; // Reset subkeyHtbl index

  // Restart the pipeline
  // Reduction value = first time
  ghash16_encrypt16_parallel(key, avx512_subkeyHtbl, CTR_BLOCKx, AAD_HASHx, in, out, ct, pos, true, xmm24, true, rounds, ghash_pos, false, index, COUNTER_INC_MASK);
  addl(pos, 256);
  addl(ghash_pos, 256);
  index += 4;

  subl(len, 768);
  cmpl(len, 768);
  jcc(Assembler::greaterEqual, GHASH_16_AES_16);

  // GHASH last 32 blocks processed here
  // GHASH products accumulated in ZMM27, ZMM25 and ZMM26 during GHASH16-AES16 operation is used
  bind(GHASH_LAST_32);
  // Use rbx as a pointer to the htbl; For last 32 blocks of GHASH, use key# 4-11 entry in subkeyHtbl
  movl(rbx, 256);
  // Load cipher blocks
  evmovdquq(ZTMP13, Address(ct, ghash_pos, Address::times_1, 0 * 64), Assembler::AVX_512bit);
  evmovdquq(ZTMP14, Address(ct, ghash_pos, Address::times_1, 1 * 64), Assembler::AVX_512bit);
  vpshufb(ZTMP13, ZTMP13, xmm24, Assembler::AVX_512bit);
  vpshufb(ZTMP14, ZTMP14, xmm24, Assembler::AVX_512bit);
  // Load ghash keys
  evmovdquq(ZTMP15, Address(avx512_subkeyHtbl, rbx, Address::times_1, 0 * 64), Assembler::AVX_512bit);
  evmovdquq(ZTMP16, Address(avx512_subkeyHtbl, rbx, Address::times_1, 1 * 64), Assembler::AVX_512bit);

  // Ghash blocks 0 - 3
  carrylessMultiply(ZTMP2, ZTMP3, ZTMP4, ZTMP1, ZTMP13, ZTMP15)evpclmulqdq(ZTMP2, ZTMP13, ZTMP15, 0x00, Assembler::AVX_512bit
); evpclmulqdq(ZTMP3, ZTMP13, ZTMP15, 0x01, Assembler::AVX_512bit
); evpclmulqdq(ZTMP4, ZTMP13, ZTMP15, 0x10, Assembler::AVX_512bit
); evpclmulqdq(ZTMP1, ZTMP13, ZTMP15, 0x11, Assembler::AVX_512bit
);;
  // Ghash blocks 4 - 7
  carrylessMultiply(ZTMP6, ZTMP7, ZTMP8, ZTMP5, ZTMP14, ZTMP16)evpclmulqdq(ZTMP6, ZTMP14, ZTMP16, 0x00, Assembler::AVX_512bit
); evpclmulqdq(ZTMP7, ZTMP14, ZTMP16, 0x01, Assembler::AVX_512bit
); evpclmulqdq(ZTMP8, ZTMP14, ZTMP16, 0x10, Assembler::AVX_512bit
); evpclmulqdq(ZTMP5, ZTMP14, ZTMP16, 0x11, Assembler::AVX_512bit
);;

  vpternlogq(ZTMP1, 0x96, ZTMP5, xmm27, Assembler::AVX_512bit); // ZTMP1 = ZTMP1 + ZTMP5 + zmm27
  vpternlogq(ZTMP2, 0x96, ZTMP6, xmm26, Assembler::AVX_512bit); // ZTMP2 = ZTMP2 + ZTMP6 + zmm26
  vpternlogq(ZTMP3, 0x96, ZTMP7, xmm25, Assembler::AVX_512bit); // ZTMP3 = ZTMP3 + ZTMP7 + zmm25
  evpxorq(ZTMP4, ZTMP4, ZTMP8, Assembler::AVX_512bit);          // ZTMP4 = ZTMP4 + ZTMP8

  addl(ghash_pos, 128);
  addl(rbx, 128);

  // Ghash remaining blocks
  bind(LOOP);
  cmpl(ghash_pos, pos);
  jcc(Assembler::aboveEqual, ACCUMULATE);
  // Load next cipher blocks and corresponding ghash keys
  evmovdquq(ZTMP13, Address(ct, ghash_pos, Address::times_1, 0 * 64), Assembler::AVX_512bit);
  evmovdquq(ZTMP14, Address(ct, ghash_pos, Address::times_1, 1 * 64), Assembler::AVX_512bit);
  vpshufb(ZTMP13, ZTMP13, xmm24, Assembler::AVX_512bit);
  vpshufb(ZTMP14, ZTMP14, xmm24, Assembler::AVX_512bit);
  evmovdquq(ZTMP15, Address(avx512_subkeyHtbl, rbx, Address::times_1, 0 * 64), Assembler::AVX_512bit);
  evmovdquq(ZTMP16, Address(avx512_subkeyHtbl, rbx, Address::times_1, 1 * 64), Assembler::AVX_512bit);

  // ghash blocks 0 - 3
  carrylessMultiply(ZTMP6, ZTMP7, ZTMP8, ZTMP5, ZTMP13, ZTMP15)evpclmulqdq(ZTMP6, ZTMP13, ZTMP15, 0x00, Assembler::AVX_512bit
); evpclmulqdq(ZTMP7, ZTMP13, ZTMP15, 0x01, Assembler::AVX_512bit
); evpclmulqdq(ZTMP8, ZTMP13, ZTMP15, 0x10, Assembler::AVX_512bit
); evpclmulqdq(ZTMP5, ZTMP13, ZTMP15, 0x11, Assembler::AVX_512bit
);;

  // ghash blocks 4 - 7
  carrylessMultiply(ZTMP10, ZTMP11, ZTMP12, ZTMP9, ZTMP14, ZTMP16)evpclmulqdq(ZTMP10, ZTMP14, ZTMP16, 0x00, Assembler::AVX_512bit
); evpclmulqdq(ZTMP11, ZTMP14, ZTMP16, 0x01, Assembler::AVX_512bit
); evpclmulqdq(ZTMP12, ZTMP14, ZTMP16, 0x10, Assembler::AVX_512bit
); evpclmulqdq(ZTMP9, ZTMP14, ZTMP16, 0x11, Assembler::AVX_512bit
);;

  // update sums
  // ZTMP1 = ZTMP1 + ZTMP5 + ZTMP9
  // ZTMP2 = ZTMP2 + ZTMP6 + ZTMP10
  // ZTMP3 = ZTMP3 + ZTMP7 xor ZTMP11
  // ZTMP4 = ZTMP4 + ZTMP8 xor ZTMP12
  xorGHASH(ZTMP1, ZTMP2, ZTMP3, ZTMP4, ZTMP5, ZTMP9, ZTMP6, ZTMP10, ZTMP7, ZTMP11, ZTMP8, ZTMP12)vpternlogq(ZTMP1, 0x96, ZTMP5, ZTMP9, Assembler::AVX_512bit);
 vpternlogq(ZTMP2, 0x96, ZTMP6, ZTMP10, Assembler::AVX_512bit
); vpternlogq(ZTMP3, 0x96, ZTMP7, ZTMP11, Assembler::AVX_512bit
); vpternlogq(ZTMP4, 0x96, ZTMP8, ZTMP12, Assembler::AVX_512bit
);;
  addl(ghash_pos, 128);
  addl(rbx, 128);
  jmp(LOOP);

  // Integrate ZTMP3/ZTMP4 into ZTMP1 and ZTMP2
  bind(ACCUMULATE);
  evpxorq(ZTMP3, ZTMP3, ZTMP4, Assembler::AVX_512bit);
  vpsrldq(ZTMP7, ZTMP3, 8, Assembler::AVX_512bit);
  vpslldq(ZTMP8, ZTMP3, 8, Assembler::AVX_512bit);
  evpxorq(ZTMP1, ZTMP1, ZTMP7, Assembler::AVX_512bit);
  evpxorq(ZTMP2, ZTMP2, ZTMP8, Assembler::AVX_512bit);

  // Add ZTMP1 and ZTMP2 128 - bit words horizontally
  vhpxori4x128(ZTMP1, ZTMP11)vextracti64x4(ZTMP11, ZTMP1, 1); evpxorq(ZTMP1, ZTMP1, ZTMP11
, Assembler::AVX_256bit); vextracti32x4(ZTMP11, ZTMP1, 1); evpxorq
(ZTMP1, ZTMP1, ZTMP11, Assembler::AVX_128bit);;
  vhpxori4x128(ZTMP2, ZTMP12)vextracti64x4(ZTMP12, ZTMP2, 1); evpxorq(ZTMP2, ZTMP2, ZTMP12
, Assembler::AVX_256bit); vextracti32x4(ZTMP12, ZTMP2, 1); evpxorq
(ZTMP2, ZTMP2, ZTMP12, Assembler::AVX_128bit);;
  // Load reduction polynomial and compute final reduction
  evmovdquq(ZTMP15, ExternalAddress(StubRoutines::x86::ghash_polynomial512_addr()), Assembler::AVX_512bit, rbx);
  vclmul_reduce(AAD_HASHx, ZTMP15, ZTMP1, ZTMP2, ZTMP3, ZTMP4)evpclmulqdq(ZTMP3, ZTMP15, ZTMP2, 0x01, Assembler::AVX_512bit
); vpslldq(ZTMP3, ZTMP3, 8, Assembler::AVX_512bit); evpxorq(ZTMP3
, ZTMP2, ZTMP3, Assembler::AVX_512bit); evpclmulqdq(ZTMP4, ZTMP15
, ZTMP3, 0x00, Assembler::AVX_512bit); vpsrldq(ZTMP4, ZTMP4, 4
, Assembler::AVX_512bit); evpclmulqdq(AAD_HASHx, ZTMP15, ZTMP3
, 0x10, Assembler::AVX_512bit); vpslldq(AAD_HASHx, AAD_HASHx,
 4, Assembler::AVX_512bit); vpternlogq(AAD_HASHx, 0x96, ZTMP4
, ZTMP1, Assembler::AVX_512bit);;

  // Pre-increment counter for next operation
  vpaddd(CTR_BLOCKx, CTR_BLOCKx, xmm18, Assembler::AVX_128bit);
  // Shuffle counter and save the updated value
  vpshufb(CTR_BLOCKx, CTR_BLOCKx, xmm24, Assembler::AVX_512bit);
  movdqu(Address(counter, 0), CTR_BLOCKx);
  // Load ghash lswap mask
  movdqu(xmm24, ExternalAddress(StubRoutines::x86::ghash_long_swap_mask_addr()));
  // Shuffle ghash using lbswap_mask and store it
  vpshufb(AAD_HASHx, AAD_HASHx, xmm24, Assembler::AVX_128bit);
  movdqu(Address(state, 0), AAD_HASHx);
  jmp(ENC_DEC_DONE);

  bind(GENERATE_HTBL_48_BLKS);
  generateHtbl_48_block_zmm(subkeyHtbl, avx512_subkeyHtbl);

  bind(ENC_DEC_DONE);
  movq(rax, pos);
1890}

1892#endif // _LP64

←

/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.hpp

1/*
* Copyright (c) 1997, 2021, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
* version 2 for more details (a copy is included in the LICENSE file that
* accompanied this code).
*
* You should have received a copy of the GNU General Public License version
* 2 along with this work; if not, write to the Free Software Foundation,
* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
* or visit www.oracle.com if you need additional information or have any
* questions.
*
*/

25#ifndef CPU_X86_ASSEMBLER_X86_HPP
26#define CPU_X86_ASSEMBLER_X86_HPP

28#include "asm/register.hpp"
29#include "utilities/powerOfTwo.hpp"

31// Contains all the definitions needed for x86 assembly code generation.

33// Calling convention
34class Argument {
public:
enum {
37#ifdef _LP641
38#ifdef _WIN64
  n_int_register_parameters_c   = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...)
  n_float_register_parameters_c = 4,  // xmm0 - xmm3 (c_farg0, c_farg1, ... )
  n_int_register_returns_c = 1, // rax
  n_float_register_returns_c = 1, // xmm0
43#else
  n_int_register_parameters_c   = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...)
  n_float_register_parameters_c = 8,  // xmm0 - xmm7 (c_farg0, c_farg1, ... )
  n_int_register_returns_c = 2, // rax, rdx
  n_float_register_returns_c = 2, // xmm0, xmm1
48#endif // _WIN64
  n_int_register_parameters_j   = 6, // j_rarg0, j_rarg1, ...
  n_float_register_parameters_j = 8  // j_farg0, j_farg1, ...
51#else
  n_register_parameters = 0   // 0 registers used to pass arguments
53#endif // _LP64
};
55};


58#ifdef _LP641
59// Symbolically name the register arguments used by the c calling convention.
60// Windows is different from linux/solaris. So much for standards...

62#ifdef _WIN64

64REGISTER_DECLARATION(Register, c_rarg0, rcx)const Register c_rarg0 = ((Register)rcx);
65REGISTER_DECLARATION(Register, c_rarg1, rdx)const Register c_rarg1 = ((Register)rdx);
66REGISTER_DECLARATION(Register, c_rarg2, r8)const Register c_rarg2 = ((Register)r8);
67REGISTER_DECLARATION(Register, c_rarg3, r9)const Register c_rarg3 = ((Register)r9);

69REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0)const XMMRegister c_farg0 = ((XMMRegister)xmm0);
70REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1)const XMMRegister c_farg1 = ((XMMRegister)xmm1);
71REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2)const XMMRegister c_farg2 = ((XMMRegister)xmm2);
72REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3)const XMMRegister c_farg3 = ((XMMRegister)xmm3);

74#else

76REGISTER_DECLARATION(Register, c_rarg0, rdi)const Register c_rarg0 = ((Register)rdi);
77REGISTER_DECLARATION(Register, c_rarg1, rsi)const Register c_rarg1 = ((Register)rsi);
78REGISTER_DECLARATION(Register, c_rarg2, rdx)const Register c_rarg2 = ((Register)rdx);
79REGISTER_DECLARATION(Register, c_rarg3, rcx)const Register c_rarg3 = ((Register)rcx);
80REGISTER_DECLARATION(Register, c_rarg4, r8)const Register c_rarg4 = ((Register)r8);
81REGISTER_DECLARATION(Register, c_rarg5, r9)const Register c_rarg5 = ((Register)r9);

83REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0)const XMMRegister c_farg0 = ((XMMRegister)xmm0);
84REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1)const XMMRegister c_farg1 = ((XMMRegister)xmm1);
85REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2)const XMMRegister c_farg2 = ((XMMRegister)xmm2);
86REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3)const XMMRegister c_farg3 = ((XMMRegister)xmm3);
87REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4)const XMMRegister c_farg4 = ((XMMRegister)xmm4);
88REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5)const XMMRegister c_farg5 = ((XMMRegister)xmm5);
89REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6)const XMMRegister c_farg6 = ((XMMRegister)xmm6);
90REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7)const XMMRegister c_farg7 = ((XMMRegister)xmm7);

92#endif // _WIN64

94// Symbolically name the register arguments used by the Java calling convention.
95// We have control over the convention for java so we can do what we please.
96// What pleases us is to offset the java calling convention so that when
97// we call a suitable jni method the arguments are lined up and we don't
98// have to do little shuffling. A suitable jni method is non-static and a
99// small number of arguments (two fewer args on windows)
100//
101//        |-------------------------------------------------------|
102//        | c_rarg0   c_rarg1  c_rarg2 c_rarg3 c_rarg4 c_rarg5    |
103//        |-------------------------------------------------------|
104//        | rcx       rdx      r8      r9      rdi*    rsi*       | windows (* not a c_rarg)
105//        | rdi       rsi      rdx     rcx     r8      r9         | solaris/linux
106//        |-------------------------------------------------------|
107//        | j_rarg5   j_rarg0  j_rarg1 j_rarg2 j_rarg3 j_rarg4    |
108//        |-------------------------------------------------------|

110REGISTER_DECLARATION(Register, j_rarg0, c_rarg1)const Register j_rarg0 = ((Register)c_rarg1);
111REGISTER_DECLARATION(Register, j_rarg1, c_rarg2)const Register j_rarg1 = ((Register)c_rarg2);
112REGISTER_DECLARATION(Register, j_rarg2, c_rarg3)const Register j_rarg2 = ((Register)c_rarg3);
113// Windows runs out of register args here
114#ifdef _WIN64
115REGISTER_DECLARATION(Register, j_rarg3, rdi)const Register j_rarg3 = ((Register)rdi);
116REGISTER_DECLARATION(Register, j_rarg4, rsi)const Register j_rarg4 = ((Register)rsi);
117#else
118REGISTER_DECLARATION(Register, j_rarg3, c_rarg4)const Register j_rarg3 = ((Register)c_rarg4);
119REGISTER_DECLARATION(Register, j_rarg4, c_rarg5)const Register j_rarg4 = ((Register)c_rarg5);
120#endif /* _WIN64 */
121REGISTER_DECLARATION(Register, j_rarg5, c_rarg0)const Register j_rarg5 = ((Register)c_rarg0);

123REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0)const XMMRegister j_farg0 = ((XMMRegister)xmm0);
124REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1)const XMMRegister j_farg1 = ((XMMRegister)xmm1);
125REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2)const XMMRegister j_farg2 = ((XMMRegister)xmm2);
126REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3)const XMMRegister j_farg3 = ((XMMRegister)xmm3);
127REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4)const XMMRegister j_farg4 = ((XMMRegister)xmm4);
128REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5)const XMMRegister j_farg5 = ((XMMRegister)xmm5);
129REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6)const XMMRegister j_farg6 = ((XMMRegister)xmm6);
130REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7)const XMMRegister j_farg7 = ((XMMRegister)xmm7);

132REGISTER_DECLARATION(Register, rscratch1, r10)const Register rscratch1 = ((Register)r10);  // volatile
133REGISTER_DECLARATION(Register, rscratch2, r11)const Register rscratch2 = ((Register)r11);  // volatile

135REGISTER_DECLARATION(Register, r12_heapbase, r12)const Register r12_heapbase = ((Register)r12); // callee-saved
136REGISTER_DECLARATION(Register, r15_thread, r15)const Register r15_thread = ((Register)r15); // callee-saved

138#else
139// rscratch1 will apear in 32bit code that is dead but of course must compile
140// Using noreg ensures if the dead code is incorrectly live and executed it
141// will cause an assertion failure
142#define rscratch1 noreg
143#define rscratch2 noreg

145#endif // _LP64

147// JSR 292
148// On x86, the SP does not have to be saved when invoking method handle intrinsics
149// or compiled lambda forms. We indicate that by setting rbp_mh_SP_save to noreg.
150REGISTER_DECLARATION(Register, rbp_mh_SP_save, noreg)const Register rbp_mh_SP_save = ((Register)noreg);

152// Address is an abstraction used to represent a memory location
153// using any of the amd64 addressing modes with one object.
154//
155// Note: A register location is represented via a Register, not
156//       via an address for efficiency & simplicity reasons.

158class ArrayAddress;

160class Address {
public:
enum ScaleFactor {
  no_scale = -1,
  times_1  =  0,
  times_2  =  1,
  times_4  =  2,
  times_8  =  3,
  times_ptr = LP64_ONLY(times_8)times_8 NOT_LP64(times_4)
};
static ScaleFactor times(int size) {
  assert(size >= 1 && size <= 8 && is_power_of_2(size), "bad scale size")do { if (!(size >= 1 && size <= 8 && is_power_of_2
(size))) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.hpp"
, 171, "assert(" "size >= 1 && size <= 8 && is_power_of_2(size)"
 ") failed", "bad scale size"); ::breakpoint(); } } while (0);
  if (size == 8)  return times_8;
  if (size == 4)  return times_4;
  if (size == 2)  return times_2;
  return times_1;
}
static int scale_size(ScaleFactor scale) {
  assert(scale != no_scale, "")do { if (!(scale != no_scale)) { (*g_assert_poison) = 'X';; report_vm_error
("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.hpp"
, 178, "assert(" "scale != no_scale" ") failed", ""); ::breakpoint
(); } } while (0);
  assert(((1 << (int)times_1) == 1 &&do { if (!(((1 << (int)times_1) == 1 && (1 <<
 (int)times_2) == 2 && (1 << (int)times_4) == 4
 && (1 << (int)times_8) == 8))) { (*g_assert_poison
) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.hpp"
, 182, "assert(" "((1 << (int)times_1) == 1 && (1 << (int)times_2) == 2 && (1 << (int)times_4) == 4 && (1 << (int)times_8) == 8)"
 ") failed", ""); ::breakpoint(); } } while (0)
          (1 << (int)times_2) == 2 &&do { if (!(((1 << (int)times_1) == 1 && (1 <<
 (int)times_2) == 2 && (1 << (int)times_4) == 4
 && (1 << (int)times_8) == 8))) { (*g_assert_poison
) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.hpp"
, 182, "assert(" "((1 << (int)times_1) == 1 && (1 << (int)times_2) == 2 && (1 << (int)times_4) == 4 && (1 << (int)times_8) == 8)"
 ") failed", ""); ::breakpoint(); } } while (0)
          (1 << (int)times_4) == 4 &&do { if (!(((1 << (int)times_1) == 1 && (1 <<
 (int)times_2) == 2 && (1 << (int)times_4) == 4
 && (1 << (int)times_8) == 8))) { (*g_assert_poison
) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.hpp"
, 182, "assert(" "((1 << (int)times_1) == 1 && (1 << (int)times_2) == 2 && (1 << (int)times_4) == 4 && (1 << (int)times_8) == 8)"
 ") failed", ""); ::breakpoint(); } } while (0)
          (1 << (int)times_8) == 8), "")do { if (!(((1 << (int)times_1) == 1 && (1 <<
 (int)times_2) == 2 && (1 << (int)times_4) == 4
 && (1 << (int)times_8) == 8))) { (*g_assert_poison
) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.hpp"
, 182, "assert(" "((1 << (int)times_1) == 1 && (1 << (int)times_2) == 2 && (1 << (int)times_4) == 4 && (1 << (int)times_8) == 8)"
 ") failed", ""); ::breakpoint(); } } while (0);
  return (1 << (int)scale);
}

private:
Register         _base;
Register         _index;
XMMRegister      _xmmindex;
ScaleFactor      _scale;
int              _disp;
bool             _isxmmindex;
RelocationHolder _rspec;

// Easily misused constructors make them private
// %%% can we make these go away?
NOT_LP64(Address(address loc, RelocationHolder spec);)
Address(int disp, address loc, relocInfo::relocType rtype);
Address(int disp, address loc, RelocationHolder spec);

public:

int disp() { return _disp; }
// creation
Address()
  : _base(noreg),
    _index(noreg),
    _xmmindex(xnoreg),
    _scale(no_scale),
    _disp(0),
    _isxmmindex(false){
}

// No default displacement otherwise Register can be implicitly
// converted to 0(Register) which is quite a different animal.

Address(Register base, int disp)
  : _base(base),
    _index(noreg),
    _xmmindex(xnoreg),
    _scale(no_scale),
    _disp(disp),
    _isxmmindex(false){
}

Address(Register base, Register index, ScaleFactor scale, int disp = 0)
  : _base (base),
    _index(index),
    _xmmindex(xnoreg),
    _scale(scale),
    _disp (disp),
    _isxmmindex(false) {
  assert(!index->is_valid() == (scale == Address::no_scale),do { if (!(!index->is_valid() == (scale == Address::no_scale
))) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.hpp"
, 234, "assert(" "!index->is_valid() == (scale == Address::no_scale)"
 ") failed", "inconsistent address"); ::breakpoint(); } } while
 (0)
4
←
Called C++ object pointer is null
         "inconsistent address")do { if (!(!index->is_valid() == (scale == Address::no_scale
))) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.hpp"
, 234, "assert(" "!index->is_valid() == (scale == Address::no_scale)"
 ") failed", "inconsistent address"); ::breakpoint(); } } while
 (0);
}

Address(Register base, RegisterOrConstant index, ScaleFactor scale = times_1, int disp = 0)
  : _base (base),
    _index(index.register_or_noreg()),
    _xmmindex(xnoreg),
    _scale(scale),
    _disp (disp + (index.constant_or_zero() * scale_size(scale))),
    _isxmmindex(false){
  if (!index.is_register())  scale = Address::no_scale;
  assert(!_index->is_valid() == (scale == Address::no_scale),do { if (!(!_index->is_valid() == (scale == Address::no_scale
))) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.hpp"
, 246, "assert(" "!_index->is_valid() == (scale == Address::no_scale)"
 ") failed", "inconsistent address"); ::breakpoint(); } } while
 (0)
         "inconsistent address")do { if (!(!_index->is_valid() == (scale == Address::no_scale
))) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.hpp"
, 246, "assert(" "!_index->is_valid() == (scale == Address::no_scale)"
 ") failed", "inconsistent address"); ::breakpoint(); } } while
 (0);
}

Address(Register base, XMMRegister index, ScaleFactor scale, int disp = 0)
  : _base (base),
    _index(noreg),
    _xmmindex(index),
    _scale(scale),
    _disp(disp),
    _isxmmindex(true) {
    assert(!index->is_valid() == (scale == Address::no_scale),do { if (!(!index->is_valid() == (scale == Address::no_scale
))) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.hpp"
, 257, "assert(" "!index->is_valid() == (scale == Address::no_scale)"
 ") failed", "inconsistent address"); ::breakpoint(); } } while
 (0)
           "inconsistent address")do { if (!(!index->is_valid() == (scale == Address::no_scale
))) { (*g_assert_poison) = 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.hpp"
, 257, "assert(" "!index->is_valid() == (scale == Address::no_scale)"
 ") failed", "inconsistent address"); ::breakpoint(); } } while
 (0);
}

// The following overloads are used in connection with the
// ByteSize type (see sizes.hpp).  They simplify the use of
// ByteSize'd arguments in assembly code.

Address(Register base, ByteSize disp)
  : Address(base, in_bytes(disp)) {}

Address(Register base, Register index, ScaleFactor scale, ByteSize disp)
  : Address(base, index, scale, in_bytes(disp)) {}

Address(Register base, RegisterOrConstant index, ScaleFactor scale, ByteSize disp)
  : Address(base, index, scale, in_bytes(disp)) {}

Address plus_disp(int disp) const {
  Address a = (*this);
  a._disp += disp;
  return a;
}
Address plus_disp(RegisterOrConstant disp, ScaleFactor scale = times_1) const {
  Address a = (*this);
  a._disp += disp.constant_or_zero() * scale_size(scale);
  if (disp.is_register()) {
    assert(!a.index()->is_valid(), "competing indexes")do { if (!(!a.index()->is_valid())) { (*g_assert_poison) =
 'X';; report_vm_error("/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.hpp"
, 282, "assert(" "!a.index()->is_valid()" ") failed", "competing indexes"
); ::breakpoint(); } } while (0);
    a._index = disp.as_register();
    a._scale = scale;
  }
  return a;
}
bool is_same_address(Address a) const {
  // disregard _rspec
  return _base == a._base && _disp == a._disp && _index == a._index && _scale == a._scale;
}

// accessors
bool        uses(Register reg) const { return _base == reg || _index == reg; }
Register    base()             const { return _base;  }
Register    index()            const { return _index; }
XMMRegister xmmindex()         const { return _xmmindex; }
ScaleFactor scale()            const { return _scale; }
int         disp()             const { return _disp;  }
bool        isxmmindex()       const { return _isxmmindex; }

// Convert the raw encoding form into the form expected by the constructor for
// Address.  An index of 4 (rsp) corresponds to having no index, so convert
// that to noreg for the Address constructor.
static Address make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc);

static Address make_array(ArrayAddress);

private:
bool base_needs_rex() const {
  return _base->is_valid() && _base->encoding() >= 8;
}

bool index_needs_rex() const {
  return _index->is_valid() &&_index->encoding() >= 8;
}

bool xmmindex_needs_rex() const {
  return _xmmindex->is_valid() && _xmmindex->encoding() >= 8;
}

relocInfo::relocType reloc() const { return _rspec.type(); }

friend class Assembler;
friend class MacroAssembler;
friend class LIR_Assembler; // base/index/scale/disp
327};

329//
330// AddressLiteral has been split out from Address because operands of this type
331// need to be treated specially on 32bit vs. 64bit platforms. By splitting it out
332// the few instructions that need to deal with address literals are unique and the
333// MacroAssembler does not have to implement every instruction in the Assembler
334// in order to search for address literals that may need special handling depending
335// on the instruction and the platform. As small step on the way to merging i486/amd64
336// directories.
337//
338class AddressLiteral {
friend class ArrayAddress;
RelocationHolder _rspec;
// Typically we use AddressLiterals we want to use their rval
// However in some situations we want the lval (effect address) of the item.
// We provide a special factory for making those lvals.
bool _is_lval;

// If the target is far we'll need to load the ea of this to
// a register to reach it. Otherwise if near we can do rip
// relative addressing.

address          _target;

protected:
// creation
AddressLiteral()
  : _is_lval(false),
    _target(NULL__null)
{}

public:


AddressLiteral(address target, relocInfo::relocType rtype);

AddressLiteral(address target, RelocationHolder const& rspec)
  : _rspec(rspec),
    _is_lval(false),
    _target(target)
{}

AddressLiteral addr() {
  AddressLiteral ret = *this;
  ret._is_lval = true;
  return ret;
}


private:

address target() { return _target; }
bool is_lval() { return _is_lval; }

relocInfo::relocType reloc() const { return _rspec.type(); }
const RelocationHolder& rspec() const { return _rspec; }

friend class Assembler;
friend class MacroAssembler;
friend class Address;
friend class LIR_Assembler;
389};

391// Convience classes
392class RuntimeAddress: public AddressLiteral {

public:

RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {}

398};

400class ExternalAddress: public AddressLiteral {
private:
static relocInfo::relocType reloc_for_target(address target) {
  // Sometimes ExternalAddress is used for values which aren't
  // exactly addresses, like the card table base.
  // external_word_type can't be used for values in the first page
  // so just skip the reloc in that case.
  return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none;
}

public:

ExternalAddress(address target) : AddressLiteral(target, reloc_for_target(target)) {}

414};

416class InternalAddress: public AddressLiteral {

public:

InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {}

422};

424// x86 can do array addressing as a single operation since disp can be an absolute
425// address amd64 can't. We create a class that expresses the concept but does extra
426// magic on amd64 to get the final result

428class ArrayAddress {
private:

AddressLiteral _base;
Address        _index;

public:

ArrayAddress() {};
ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {};
AddressLiteral base() { return _base; }
Address index() { return _index; }

441};

443class InstructionAttr;

445// 64-bit refect the fxsave size which is 512 bytes and the new xsave area on EVEX which is another 2176 bytes
446// See fxsave and xsave(EVEX enabled) documentation for layout
447const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY(2688 / wordSize)2688 / wordSize;

449// The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction
450// level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write
451// is what you get. The Assembler is generating code into a CodeBuffer.

453class Assembler : public AbstractAssembler  {
friend class AbstractAssembler; // for the non-virtual hack
friend class LIR_Assembler; // as_Address()
friend class StubGenerator;

public:
enum Condition {                     // The x86 condition codes used for conditional jumps/moves.
  zero          = 0x4,
  notZero       = 0x5,
  equal         = 0x4,
  notEqual      = 0x5,
  less          = 0xc,
  lessEqual     = 0xe,
  greater       = 0xf,
  greaterEqual  = 0xd,
  below         = 0x2,
  belowEqual    = 0x6,
  above         = 0x7,
  aboveEqual    = 0x3,
  overflow      = 0x0,
  noOverflow    = 0x1,
  carrySet      = 0x2,
  carryClear    = 0x3,
  negative      = 0x8,
  positive      = 0x9,
  parity        = 0xa,
  noParity      = 0xb
};

enum Prefix {
  // segment overrides
  CS_segment = 0x2e,
  SS_segment = 0x36,
  DS_segment = 0x3e,
  ES_segment = 0x26,
  FS_segment = 0x64,
  GS_segment = 0x65,

  REX        = 0x40,

  REX_B      = 0x41,
  REX_X      = 0x42,
  REX_XB     = 0x43,
  REX_R      = 0x44,
  REX_RB     = 0x45,
  REX_RX     = 0x46,
  REX_RXB    = 0x47,

  REX_W      = 0x48,

  REX_WB     = 0x49,
  REX_WX     = 0x4A,
  REX_WXB    = 0x4B,
  REX_WR     = 0x4C,
  REX_WRB    = 0x4D,
  REX_WRX    = 0x4E,
  REX_WRXB   = 0x4F,

  VEX_3bytes = 0xC4,
  VEX_2bytes = 0xC5,
  EVEX_4bytes = 0x62,
  Prefix_EMPTY = 0x0
};

enum VexPrefix {
  VEX_B = 0x20,
  VEX_X = 0x40,
  VEX_R = 0x80,
  VEX_W = 0x80
};

enum ExexPrefix {
  EVEX_F  = 0x04,
  EVEX_V  = 0x08,
  EVEX_Rb = 0x10,
  EVEX_X  = 0x40,
  EVEX_Z  = 0x80
};

enum VexSimdPrefix {
  VEX_SIMD_NONE = 0x0,
  VEX_SIMD_66   = 0x1,
  VEX_SIMD_F3   = 0x2,
  VEX_SIMD_F2   = 0x3
};

enum VexOpcode {
  VEX_OPCODE_NONE  = 0x0,
  VEX_OPCODE_0F    = 0x1,
  VEX_OPCODE_0F_38 = 0x2,
  VEX_OPCODE_0F_3A = 0x3,
  VEX_OPCODE_MASK  = 0x1F
};

enum AvxVectorLen {
  AVX_128bit = 0x0,
  AVX_256bit = 0x1,
  AVX_512bit = 0x2,
  AVX_NoVec  = 0x4
};

enum EvexTupleType {
  EVEX_FV   = 0,
  EVEX_HV   = 4,
  EVEX_FVM  = 6,
  EVEX_T1S  = 7,
  EVEX_T1F  = 11,
  EVEX_T2   = 13,
  EVEX_T4   = 15,
  EVEX_T8   = 17,
  EVEX_HVM  = 18,
  EVEX_QVM  = 19,
  EVEX_OVM  = 20,
  EVEX_M128 = 21,
  EVEX_DUP  = 22,
  EVEX_ETUP = 23
};

enum EvexInputSizeInBits {
  EVEX_8bit  = 0,
  EVEX_16bit = 1,
  EVEX_32bit = 2,
  EVEX_64bit = 3,
  EVEX_NObit = 4
};

enum WhichOperand {
  // input to locate_operand, and format code for relocations
  imm_operand  = 0,            // embedded 32-bit|64-bit immediate operand
  disp32_operand = 1,          // embedded 32-bit displacement or address
  call32_operand = 2,          // embedded 32-bit self-relative displacement
584#ifndef _LP641
  _WhichOperand_limit = 3
586#else
   narrow_oop_operand = 3,     // embedded 32-bit immediate narrow oop
  _WhichOperand_limit = 4
589#endif
};

// Comparison predicates for integral types & FP types when using SSE
enum ComparisonPredicate {
  eq = 0,
  lt = 1,
  le = 2,
  _false = 3,
  neq = 4,
  nlt = 5,
  nle = 6,
  _true = 7
};

// Comparison predicates for FP types when using AVX
// O means ordered. U is unordered. When using ordered, any NaN comparison is false. Otherwise, it is true.
// S means signaling. Q means non-signaling. When signaling is true, instruction signals #IA on NaN.
enum ComparisonPredicateFP {
  EQ_OQ = 0,
  LT_OS = 1,
  LE_OS = 2,
  UNORD_Q = 3,
  NEQ_UQ = 4,
  NLT_US = 5,
  NLE_US = 6,
  ORD_Q = 7,
  EQ_UQ = 8,
  NGE_US = 9,
  NGT_US = 0xA,
  FALSE_OQ = 0XB,
  NEQ_OQ = 0xC,
  GE_OS = 0xD,
  GT_OS = 0xE,
  TRUE_UQ = 0xF,
  EQ_OS = 0x10,
  LT_OQ = 0x11,
  LE_OQ = 0x12,
  UNORD_S = 0x13,
  NEQ_US = 0x14,
  NLT_UQ = 0x15,
  NLE_UQ = 0x16,
  ORD_S = 0x17,
  EQ_US = 0x18,
  NGE_UQ = 0x19,
  NGT_UQ = 0x1A,
  FALSE_OS = 0x1B,
  NEQ_OS = 0x1C,
  GE_OQ = 0x1D,
  GT_OQ = 0x1E,
  TRUE_US =0x1F
};

enum Width {
  B = 0,
  W = 1,
  D = 2,
  Q = 3
};

//---<  calculate length of instruction  >---
// As instruction size can't be found out easily on x86/x64,
// we just use '4' for len and maxlen.
// instruction must start at passed address
static unsigned int instr_len(unsigned char *instr) { return 4; }

//---<  longest instructions  >---
// Max instruction length is not specified in architecture documentation.
// We could use a "safe enough" estimate (15), but just default to
// instruction length guess from above.
static unsigned int instr_maxlen() { return 4; }

// NOTE: The general philopsophy of the declarations here is that 64bit versions
// of instructions are freely declared without the need for wrapping them an ifdef.
// (Some dangerous instructions are ifdef's out of inappropriate jvm's.)
// In the .cpp file the implementations are wrapped so that they are dropped out
// of the resulting jvm. This is done mostly to keep the footprint of MINIMAL
// to the size it was prior to merging up the 32bit and 64bit assemblers.
//
// This does mean you'll get a linker/runtime error if you use a 64bit only instruction
// in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down.

671private:

bool _legacy_mode_bw;
bool _legacy_mode_dq;
bool _legacy_mode_vl;
bool _legacy_mode_vlbw;
NOT_LP64(bool _is_managed;)

class InstructionAttr *_attributes;

// 64bit prefixes
void prefix(Register reg);
void prefix(Register dst, Register src, Prefix p);
void prefix(Register dst, Address adr, Prefix p);

void prefix(Address adr);
void prefix(Address adr, Register reg,  bool byteinst = false);
void prefix(Address adr, XMMRegister reg);

int prefix_and_encode(int reg_enc, bool byteinst = false);
int prefix_and_encode(int dst_enc, int src_enc) {
  return prefix_and_encode(dst_enc, false, src_enc, false);
}
int prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte);

// Some prefixq variants always emit exactly one prefix byte, so besides a
// prefix-emitting method we provide a method to get the prefix byte to emit,
// which can then be folded into a byte stream.
int8_t get_prefixq(Address adr);
int8_t get_prefixq(Address adr, Register reg);

void prefixq(Address adr);
void prefixq(Address adr, Register reg);
void prefixq(Address adr, XMMRegister reg);

int prefixq_and_encode(int reg_enc);
int prefixq_and_encode(int dst_enc, int src_enc);

void rex_prefix(Address adr, XMMRegister xreg,
                VexSimdPrefix pre, VexOpcode opc, bool rex_w);
int  rex_prefix_and_encode(int dst_enc, int src_enc,
                           VexSimdPrefix pre, VexOpcode opc, bool rex_w);

void vex_prefix(bool vex_r, bool vex_b, bool vex_x, int nds_enc, VexSimdPrefix pre, VexOpcode opc);

void evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool evex_r, bool evex_v,
                 int nds_enc, VexSimdPrefix pre, VexOpcode opc);

void vex_prefix(Address adr, int nds_enc, int xreg_enc,
                VexSimdPrefix pre, VexOpcode opc,
                InstructionAttr *attributes);

int  vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc,
                           VexSimdPrefix pre, VexOpcode opc,
                           InstructionAttr *attributes);

void simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre,
                 VexOpcode opc, InstructionAttr *attributes);

int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre,
                           VexOpcode opc, InstructionAttr *attributes);

// Helper functions for groups of instructions
void emit_arith_b(int op1, int op2, Register dst, int imm8);

void emit_arith(int op1, int op2, Register dst, int32_t imm32);
// Force generation of a 4 byte immediate value even if it fits into 8bit
void emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32);
void emit_arith(int op1, int op2, Register dst, Register src);

bool emit_compressed_disp_byte(int &disp);

void emit_modrm(int mod, int dst_enc, int src_enc);
void emit_modrm_disp8(int mod, int dst_enc, int src_enc,
                      int disp);
void emit_modrm_sib(int mod, int dst_enc, int src_enc,
                    Address::ScaleFactor scale, int index_enc, int base_enc);
void emit_modrm_sib_disp8(int mod, int dst_enc, int src_enc,
                          Address::ScaleFactor scale, int index_enc, int base_enc,
                          int disp);

void emit_operand_helper(int reg_enc,
                         int base_enc, int index_enc, Address::ScaleFactor scale,
                         int disp,
                         RelocationHolder const& rspec,
                         int rip_relative_correction = 0);

void emit_operand(Register reg,
                  Register base, Register index, Address::ScaleFactor scale,
                  int disp,
                  RelocationHolder const& rspec,
                  int rip_relative_correction = 0);

void emit_operand(Register reg,
                  Register base, XMMRegister index, Address::ScaleFactor scale,
                  int disp,
                  RelocationHolder const& rspec);

void emit_operand(XMMRegister xreg,
                  Register base, XMMRegister xindex, Address::ScaleFactor scale,
                  int disp,
                  RelocationHolder const& rspec);

void emit_operand(Register reg, Address adr,
                  int rip_relative_correction = 0);

void emit_operand(XMMRegister reg,
                  Register base, Register index, Address::ScaleFactor scale,
                  int disp,
                  RelocationHolder const& rspec);

void emit_operand(XMMRegister reg, Address adr);

// Immediate-to-memory forms
void emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32);

protected:
#ifdef ASSERT1
void check_relocation(RelocationHolder const& rspec, int format);
#endif

void emit_data(jint data, relocInfo::relocType    rtype, int format);
void emit_data(jint data, RelocationHolder const& rspec, int format);
void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);

bool reachable(AddressLiteral adr) NOT_LP64({ return true;});

// These are all easily abused and hence protected

// 32BIT ONLY SECTION
802#ifndef _LP641
// Make these disappear in 64bit mode since they would never be correct
void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec);   // 32BIT ONLY
void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec);    // 32BIT ONLY

void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec);    // 32BIT ONLY
void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec);     // 32BIT ONLY

void push_literal32(int32_t imm32, RelocationHolder const& rspec);                 // 32BIT ONLY
811#else
// 64BIT ONLY SECTION
void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec);   // 64BIT ONLY

void cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec);
void cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec);

void mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec);
void mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec);
820#endif // _LP64

// These are unique in that we are ensured by the caller that the 32bit
// relative in these instructions will always be able to reach the potentially
// 64bit address described by entry. Since they can take a 64bit address they
// don't have the 32 suffix like the other instructions in this class.

void call_literal(address entry, RelocationHolder const& rspec);
void jmp_literal(address entry, RelocationHolder const& rspec);

// Avoid using directly section
// Instructions in this section are actually usable by anyone without danger
// of failure but have performance issues that are addressed my enhanced
// instructions which will do the proper thing base on the particular cpu.
// We protect them because we don't trust you...

// Don't use next inc() and dec() methods directly. INC & DEC instructions
// could cause a partial flag stall since they don't set CF flag.
// Use MacroAssembler::decrement() & MacroAssembler::increment() methods
// which call inc() & dec() or add() & sub() in accordance with
// the product flag UseIncDec value.

void decl(Register dst);
void decl(Address dst);
void decq(Address dst);

void incl(Register dst);
void incl(Address dst);
void incq(Register dst);
void incq(Address dst);

// New cpus require use of movsd and movss to avoid partial register stall
// when loading from memory. But for old Opteron use movlpd instead of movsd.
// The selection is done in MacroAssembler::movdbl() and movflt().

// Move Scalar Single-Precision Floating-Point Values
void movss(XMMRegister dst, Address src);
void movss(XMMRegister dst, XMMRegister src);
void movss(Address dst, XMMRegister src);

// Move Scalar Double-Precision Floating-Point Values
void movsd(XMMRegister dst, Address src);
void movsd(XMMRegister dst, XMMRegister src);
void movsd(Address dst, XMMRegister src);
void movlpd(XMMRegister dst, Address src);

// New cpus require use of movaps and movapd to avoid partial register stall
// when moving between registers.
void movaps(XMMRegister dst, XMMRegister src);
void movapd(XMMRegister dst, XMMRegister src);

// End avoid using directly


// Instruction prefixes
void prefix(Prefix p);

public:

// Creation
Assembler(CodeBuffer* code) : AbstractAssembler(code) {
  init_attributes();
}

// Decoding
static address locate_operand(address inst, WhichOperand which);
static address locate_next_instruction(address inst);

// Utilities
static bool query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len,
                                       int cur_tuple_type, int in_size_in_bits, int cur_encoding);

// Generic instructions
// Does 32bit or 64bit as needed for the platform. In some sense these
// belong in macro assembler but there is no need for both varieties to exist

void init_attributes(void);

void set_attributes(InstructionAttr *attributes) { _attributes = attributes; }
void clear_attributes(void) { _attributes = NULL__null; }

void set_managed(void) { NOT_LP64(_is_managed = true;) }
void clear_managed(void) { NOT_LP64(_is_managed = false;) }
bool is_managed(void) {
  NOT_LP64(return _is_managed;)
  LP64_ONLY(return false;)return false; }

void lea(Register dst, Address src);

void mov(Register dst, Register src);

911#ifdef _LP641
// support caching the result of some routines

// must be called before pusha(), popa(), vzeroupper() - checked with asserts
static void precompute_instructions();

void pusha_uncached();
void popa_uncached();
919#endif
void vzeroupper_uncached();
void decq(Register dst);

void pusha();
void popa();

void pushf();
void popf();

void push(int32_t imm32);

void push(Register src);

void pop(Register dst);

// These are dummies to prevent surprise implicit conversions to Register
void push(void* v);
void pop(void* v);

// These do register sized moves/scans
void rep_mov();
void rep_stos();
void rep_stosb();
void repne_scan();
944#ifdef _LP641
void repne_scanl();
946#endif

// Vanilla instructions in lexical order

void adcl(Address dst, int32_t imm32);
void adcl(Address dst, Register src);
void adcl(Register dst, int32_t imm32);
void adcl(Register dst, Address src);
void adcl(Register dst, Register src);

void adcq(Register dst, int32_t imm32);
void adcq(Register dst, Address src);
void adcq(Register dst, Register src);

void addb(Address dst, int imm8);
void addw(Register dst, Register src);
void addw(Address dst, int imm16);

void addl(Address dst, int32_t imm32);
void addl(Address dst, Register src);
void addl(Register dst, int32_t imm32);
void addl(Register dst, Address src);
void addl(Register dst, Register src);

void addq(Address dst, int32_t imm32);
void addq(Address dst, Register src);
void addq(Register dst, int32_t imm32);
void addq(Register dst, Address src);
void addq(Register dst, Register src);

976#ifdef _LP641
//Add Unsigned Integers with Carry Flag
void adcxq(Register dst, Register src);

//Add Unsigned Integers with Overflow Flag
void adoxq(Register dst, Register src);
982#endif

void addr_nop_4();
void addr_nop_5();
void addr_nop_7();
void addr_nop_8();

// Add Scalar Double-Precision Floating-Point Values
void addsd(XMMRegister dst, Address src);
void addsd(XMMRegister dst, XMMRegister src);

// Add Scalar Single-Precision Floating-Point Values
void addss(XMMRegister dst, Address src);
void addss(XMMRegister dst, XMMRegister src);

// AES instructions
void aesdec(XMMRegister dst, Address src);
void aesdec(XMMRegister dst, XMMRegister src);
void aesdeclast(XMMRegister dst, Address src);
void aesdeclast(XMMRegister dst, XMMRegister src);
void aesenc(XMMRegister dst, Address src);
void aesenc(XMMRegister dst, XMMRegister src);
void aesenclast(XMMRegister dst, Address src);
void aesenclast(XMMRegister dst, XMMRegister src);
// Vector AES instructions
void vaesenc(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
void vaesenclast(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
void vaesdec(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
void vaesdeclast(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);

void andw(Register dst, Register src);
void andb(Address dst, Register src);

void andl(Address  dst, int32_t imm32);
void andl(Register dst, int32_t imm32);
void andl(Register dst, Address src);
void andl(Register dst, Register src);
void andl(Address dst, Register src);

void andq(Address  dst, int32_t imm32);
void andq(Register dst, int32_t imm32);
void andq(Register dst, Address src);
void andq(Register dst, Register src);
void andq(Address dst, Register src);

// BMI instructions
void andnl(Register dst, Register src1, Register src2);
void andnl(Register dst, Register src1, Address src2);
void andnq(Register dst, Register src1, Register src2);
void andnq(Register dst, Register src1, Address src2);

void blsil(Register dst, Register src);
void blsil(Register dst, Address src);
void blsiq(Register dst, Register src);
void blsiq(Register dst, Address src);

void blsmskl(Register dst, Register src);
void blsmskl(Register dst, Address src);
void blsmskq(Register dst, Register src);
void blsmskq(Register dst, Address src);

void blsrl(Register dst, Register src);
void blsrl(Register dst, Address src);
void blsrq(Register dst, Register src);
void blsrq(Register dst, Address src);

void bsfl(Register dst, Register src);
void bsrl(Register dst, Register src);

1051#ifdef _LP641
void bsfq(Register dst, Register src);
void bsrq(Register dst, Register src);
1054#endif

void bswapl(Register reg);

void bswapq(Register reg);

void call(Label& L, relocInfo::relocType rtype);
void call(Register reg);  // push pc; pc <- reg
void call(Address adr);   // push pc; pc <- adr

void cdql();

void cdqq();

void cld();

void clflush(Address adr);
void clflushopt(Address adr);
void clwb(Address adr);

void cmovl(Condition cc, Register dst, Register src);
void cmovl(Condition cc, Register dst, Address src);

void cmovq(Condition cc, Register dst, Register src);
void cmovq(Condition cc, Register dst, Address src);


void cmpb(Address dst, int imm8);

void cmpl(Address dst, int32_t imm32);

void cmp(Register dst, int32_t imm32);
void cmpl(Register dst, int32_t imm32);
void cmpl(Register dst, Register src);
void cmpl(Register dst, Address src);

void cmpq(Address dst, int32_t imm32);
void cmpq(Address dst, Register src);

void cmpq(Register dst, int32_t imm32);
void cmpq(Register dst, Register src);
void cmpq(Register dst, Address src);

// these are dummies used to catch attempting to convert NULL to Register
void cmpl(Register dst, void* junk); // dummy
void cmpq(Register dst, void* junk); // dummy

void cmpw(Address dst, int imm16);

void cmpxchg8 (Address adr);

void cmpxchgb(Register reg, Address adr);
void cmpxchgl(Register reg, Address adr);

void cmpxchgq(Register reg, Address adr);
void cmpxchgw(Register reg, Address adr);

// Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
void comisd(XMMRegister dst, Address src);
void comisd(XMMRegister dst, XMMRegister src);

// Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
void comiss(XMMRegister dst, Address src);
void comiss(XMMRegister dst, XMMRegister src);

// Identify processor type and features
void cpuid();

// CRC32C
void crc32(Register crc, Register v, int8_t sizeInBytes);
void crc32(Register crc, Address adr, int8_t sizeInBytes);

// Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
void cvtsd2ss(XMMRegister dst, XMMRegister src);
void cvtsd2ss(XMMRegister dst, Address src);

// Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
void cvtsi2sdl(XMMRegister dst, Register src);
void cvtsi2sdl(XMMRegister dst, Address src);
void cvtsi2sdq(XMMRegister dst, Register src);
void cvtsi2sdq(XMMRegister dst, Address src);

// Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value
void cvtsi2ssl(XMMRegister dst, Register src);
void cvtsi2ssl(XMMRegister dst, Address src);
void cvtsi2ssq(XMMRegister dst, Register src);
void cvtsi2ssq(XMMRegister dst, Address src);

// Convert Packed Signed Doubleword Integers to Packed Double-Precision Floating-Point Value
void cvtdq2pd(XMMRegister dst, XMMRegister src);
void vcvtdq2pd(XMMRegister dst, XMMRegister src, int vector_len);

// Convert Packed Signed Doubleword Integers to Packed Single-Precision Floating-Point Value
void cvtdq2ps(XMMRegister dst, XMMRegister src);
void vcvtdq2ps(XMMRegister dst, XMMRegister src, int vector_len);

// Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
void cvtss2sd(XMMRegister dst, XMMRegister src);
void cvtss2sd(XMMRegister dst, Address src);

// Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
void cvttsd2sil(Register dst, Address src);
void cvttsd2sil(Register dst, XMMRegister src);
void cvttsd2siq(Register dst, Address src);
void cvttsd2siq(Register dst, XMMRegister src);

// Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer
void cvttss2sil(Register dst, XMMRegister src);
void cvttss2siq(Register dst, XMMRegister src);

// Convert vector double to int
void cvttpd2dq(XMMRegister dst, XMMRegister src);

// Convert vector float and double
void vcvtps2pd(XMMRegister dst, XMMRegister src, int vector_len);
void vcvtpd2ps(XMMRegister dst, XMMRegister src, int vector_len);

// Convert vector float and int
void vcvttps2dq(XMMRegister dst, XMMRegister src, int vector_len);

// Convert vector long to vector FP
void evcvtqq2ps(XMMRegister dst, XMMRegister src, int vector_len);
void evcvtqq2pd(XMMRegister dst, XMMRegister src, int vector_len);

// Convert vector double to long
void evcvttpd2qq(XMMRegister dst, XMMRegister src, int vector_len);

// Evex casts with truncation
void evpmovwb(XMMRegister dst, XMMRegister src, int vector_len);
void evpmovdw(XMMRegister dst, XMMRegister src, int vector_len);
void evpmovdb(XMMRegister dst, XMMRegister src, int vector_len);
void evpmovqd(XMMRegister dst, XMMRegister src, int vector_len);
void evpmovqb(XMMRegister dst, XMMRegister src, int vector_len);
void evpmovqw(XMMRegister dst, XMMRegister src, int vector_len);

//Abs of packed Integer values
void pabsb(XMMRegister dst, XMMRegister src);
void pabsw(XMMRegister dst, XMMRegister src);
void pabsd(XMMRegister dst, XMMRegister src);
void vpabsb(XMMRegister dst, XMMRegister src, int vector_len);
void vpabsw(XMMRegister dst, XMMRegister src, int vector_len);
void vpabsd(XMMRegister dst, XMMRegister src, int vector_len);
void evpabsq(XMMRegister dst, XMMRegister src, int vector_len);

// Divide Scalar Double-Precision Floating-Point Values
void divsd(XMMRegister dst, Address src);
void divsd(XMMRegister dst, XMMRegister src);

// Divide Scalar Single-Precision Floating-Point Values
void divss(XMMRegister dst, Address src);
void divss(XMMRegister dst, XMMRegister src);


1207#ifndef _LP641
private:

void emit_farith(int b1, int b2, int i);

public:
void emms();

void fabs();

void fadd(int i);

void fadd_d(Address src);
void fadd_s(Address src);

// "Alternate" versions of x87 instructions place result down in FPU
// stack instead of on TOS

void fadda(int i); // "alternate" fadd
void faddp(int i = 1);

void fchs();

void fcom(int i);

void fcomp(int i = 1);
void fcomp_d(Address src);
void fcomp_s(Address src);

void fcompp();

void fcos();

void fdecstp();

void fdiv(int i);
void fdiv_d(Address src);
void fdivr_s(Address src);
void fdiva(int i);  // "alternate" fdiv
void fdivp(int i = 1);

void fdivr(int i);
void fdivr_d(Address src);
void fdiv_s(Address src);

void fdivra(int i); // "alternate" reversed fdiv

void fdivrp(int i = 1);

void ffree(int i = 0);

void fild_d(Address adr);
void fild_s(Address adr);

void fincstp();

void finit();

void fist_s (Address adr);
void fistp_d(Address adr);
void fistp_s(Address adr);

void fld1();

void fld_d(Address adr);
void fld_s(Address adr);
void fld_s(int index);

void fldcw(Address src);

void fldenv(Address src);

void fldlg2();

void fldln2();

void fldz();

void flog();
void flog10();

void fmul(int i);

void fmul_d(Address src);
void fmul_s(Address src);

void fmula(int i);  // "alternate" fmul

void fmulp(int i = 1);

void fnsave(Address dst);

void fnstcw(Address src);

void fnstsw_ax();

void fprem();
void fprem1();

void frstor(Address src);

void fsin();

void fsqrt();

void fst_d(Address adr);
void fst_s(Address adr);

void fstp_d(Address adr);
void fstp_d(int index);
void fstp_s(Address adr);

void fsub(int i);
void fsub_d(Address src);
void fsub_s(Address src);

void fsuba(int i);  // "alternate" fsub

void fsubp(int i = 1);

void fsubr(int i);
void fsubr_d(Address src);
void fsubr_s(Address src);

void fsubra(int i); // "alternate" reversed fsub

void fsubrp(int i = 1);

void ftan();

void ftst();

void fucomi(int i = 1);
void fucomip(int i = 1);

void fwait();

void fxch(int i = 1);

void fyl2x();
void frndint();
void f2xm1();
void fldl2e();
1350#endif // !_LP64

// operands that only take the original 32bit registers
void emit_operand32(Register reg, Address adr);

void fld_x(Address adr);  // extended-precision (80-bit) format
void fstp_x(Address adr); // extended-precision (80-bit) format
void fxrstor(Address src);
void xrstor(Address src);

void fxsave(Address dst);
void xsave(Address dst);

void hlt();

void idivl(Register src);
void divl(Register src); // Unsigned division

1368#ifdef _LP641
void idivq(Register src);
1370#endif

void imull(Register src);
void imull(Register dst, Register src);
void imull(Register dst, Register src, int value);
void imull(Register dst, Address src, int value);
void imull(Register dst, Address src);

1378#ifdef _LP641
void imulq(Register dst, Register src);
void imulq(Register dst, Register src, int value);
void imulq(Register dst, Address src, int value);
void imulq(Register dst, Address src);
void imulq(Register dst);
1384#endif

// jcc is the generic conditional branch generator to run-
// time routines, jcc is used for branches to labels. jcc
// takes a branch opcode (cc) and a label (L) and generates
// either a backward branch or a forward branch and links it
// to the label fixup chain. Usage:
//
// Label L;      // unbound label
// jcc(cc, L);   // forward branch to unbound label
// bind(L);      // bind label to the current pc
// jcc(cc, L);   // backward branch to bound label
// bind(L);      // illegal: a label may be bound only once
//
// Note: The same Label can be used for forward and backward branches
// but it may be bound only once.

void jcc(Condition cc, Label& L, bool maybe_short = true);

// Conditional jump to a 8-bit offset to L.
// WARNING: be very careful using this for forward jumps.  If the label is
// not bound within an 8-bit offset of this instruction, a run-time error
// will occur.

// Use macro to record file and line number.
#define jccb(cc, L)jccb_0(cc, L, "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.hpp"
, 1409) jccb_0(cc, L, __FILE__"/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.hpp", __LINE__1409)

void jccb_0(Condition cc, Label& L, const char* file, int line);

void jmp(Address entry);    // pc <- entry

// Label operations & relative jumps (PPUM Appendix D)
void jmp(Label& L, bool maybe_short = true);   // unconditional jump to L

void jmp(Register entry); // pc <- entry

// Unconditional 8-bit offset jump to L.
// WARNING: be very careful using this for forward jumps.  If the label is
// not bound within an 8-bit offset of this instruction, a run-time error
// will occur.

// Use macro to record file and line number.
#define jmpb(L)jmpb_0(L, "/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.hpp"
, 1426) jmpb_0(L, __FILE__"/home/daniel/Projects/java/jdk/src/hotspot/cpu/x86/assembler_x86.hpp", __LINE__1426)

void jmpb_0(Label& L, const char* file, int line);

void ldmxcsr( Address src );

void leal(Register dst, Address src);

void leaq(Register dst, Address src);

void lfence();

void lock();
void size_prefix();

void lzcntl(Register dst, Register src);

1443#ifdef _LP641
void lzcntq(Register dst, Register src);
1445#endif

enum Membar_mask_bits {
  StoreStore = 1 << 3,
  LoadStore  = 1 << 2,
  StoreLoad  = 1 << 1,
  LoadLoad   = 1 << 0
};

// Serializes memory and blows flags
void membar(Membar_mask_bits order_constraint);

void mfence();
void sfence();

// Moves

void mov64(Register dst, int64_t imm64);
void mov64(Register dst, int64_t imm64, relocInfo::relocType rtype, int format);

void movb(Address dst, Register src);
void movb(Address dst, int imm8);
void movb(Register dst, Address src);

void movddup(XMMRegister dst, XMMRegister src);

void kandbl(KRegister dst, KRegister src1, KRegister src2);
void kandwl(KRegister dst, KRegister src1, KRegister src2);
void kanddl(KRegister dst, KRegister src1, KRegister src2);
void kandql(KRegister dst, KRegister src1, KRegister src2);

void korbl(KRegister dst, KRegister src1, KRegister src2);
void korwl(KRegister dst, KRegister src1, KRegister src2);
void kordl(KRegister dst, KRegister src1, KRegister src2);
void korql(KRegister dst, KRegister src1, KRegister src2);

void kxorbl(KRegister dst, KRegister src1, KRegister src2);
void kxorwl(KRegister dst, KRegister src1, KRegister src2);
void kxordl(KRegister dst, KRegister src1, KRegister src2);
void kxorql(KRegister dst, KRegister src1, KRegister src2);
void kmovbl(KRegister dst, Register src);
void kmovbl(Register dst, KRegister src);
void kmovbl(KRegister dst, KRegister src);
void kmovwl(KRegister dst, Register src);
void kmovwl(KRegister dst, Address src);
void kmovwl(Register dst, KRegister src);
void kmovwl(Address dst, KRegister src);
void kmovwl(KRegister dst, KRegister src);
void kmovdl(KRegister dst, Register src);
void kmovdl(Register dst, KRegister src);
void kmovql(KRegister dst, KRegister src);
void kmovql(Address dst, KRegister src);
void kmovql(KRegister dst, Address src);
void kmovql(KRegister dst, Register src);
void kmovql(Register dst, KRegister src);

void knotbl(KRegister dst, KRegister src);
void knotwl(KRegister dst, KRegister src);
void knotdl(KRegister dst, KRegister src);
void knotql(KRegister dst, KRegister src);

void kortestbl(KRegister dst, KRegister src);
void kortestwl(KRegister dst, KRegister src);
void kortestdl(KRegister dst, KRegister src);
void kortestql(KRegister dst, KRegister src);

void kxnorbl(KRegister dst, KRegister src1, KRegister src2);
void kshiftlbl(KRegister dst, KRegister src, int imm8);
void kshiftrbl(KRegister dst, KRegister src, int imm8);
void kshiftrwl(KRegister dst, KRegister src, int imm8);
void kshiftrdl(KRegister dst, KRegister src, int imm8);
void kshiftrql(KRegister dst, KRegister src, int imm8);
void ktestq(KRegister src1, KRegister src2);
void ktestd(KRegister src1, KRegister src2);

void ktestql(KRegister dst, KRegister src);
void ktestdl(KRegister dst, KRegister src);
void ktestwl(KRegister dst, KRegister src);
void ktestbl(KRegister dst, KRegister src);

void movdl(XMMRegister dst, Register src);
void movdl(Register dst, XMMRegister src);
void movdl(XMMRegister dst, Address src);
void movdl(Address dst, XMMRegister src);

// Move Double Quadword
void movdq(XMMRegister dst, Register src);
void movdq(Register dst, XMMRegister src);

// Move Aligned Double Quadword
void movdqa(XMMRegister dst, XMMRegister src);
void movdqa(XMMRegister dst, Address src);

// Move Unaligned Double Quadword
void movdqu(Address     dst, XMMRegister src);
void movdqu(XMMRegister dst, Address src);
void movdqu(XMMRegister dst, XMMRegister src);

// Move Unaligned 256bit Vector
void vmovdqu(Address dst, XMMRegister src);
void vmovdqu(XMMRegister dst, Address src);
void vmovdqu(XMMRegister dst, XMMRegister src);

 // Move Unaligned 512bit Vector
void evmovdqub(Address dst, XMMRegister src, bool merge, int vector_len);
void evmovdqub(XMMRegister dst, Address src, bool merge, int vector_len);
void evmovdqub(XMMRegister dst, XMMRegister src, bool merge, int vector_len);
void evmovdqub(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len);
void evmovdqub(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
void evmovdquw(Address dst, XMMRegister src, bool merge, int vector_len);
void evmovdquw(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
void evmovdquw(XMMRegister dst, Address src, bool merge, int vector_len);
void evmovdquw(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len);
void evmovdqul(Address dst, XMMRegister src, int vector_len);
void evmovdqul(XMMRegister dst, Address src, int vector_len);
void evmovdqul(XMMRegister dst, XMMRegister src, int vector_len);
void evmovdqul(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
void evmovdqul(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len);
void evmovdqul(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
void evmovdquq(Address dst, XMMRegister src, int vector_len);
void evmovdquq(XMMRegister dst, Address src, int vector_len);
void evmovdquq(XMMRegister dst, XMMRegister src, int vector_len);
void evmovdquq(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
void evmovdquq(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len);
void evmovdquq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);

// Move lower 64bit to high 64bit in 128bit register
void movlhps(XMMRegister dst, XMMRegister src);

void movl(Register dst, int32_t imm32);
void movl(Address dst, int32_t imm32);
void movl(Register dst, Register src);
void movl(Register dst, Address src);
void movl(Address dst, Register src);

// These dummies prevent using movl from converting a zero (like NULL) into Register
// by giving the compiler two choices it can't resolve

void movl(Address  dst, void* junk);
void movl(Register dst, void* junk);

1586#ifdef _LP641
void movq(Register dst, Register src);
void movq(Register dst, Address src);
void movq(Address  dst, Register src);
void movq(Address  dst, int32_t imm32);
void movq(Register  dst, int32_t imm32);

// These dummies prevent using movq from converting a zero (like NULL) into Register
// by giving the compiler two choices it can't resolve

void movq(Address  dst, void* dummy);
void movq(Register dst, void* dummy);
1598#endif

// Move Quadword
void movq(Address     dst, XMMRegister src);
void movq(XMMRegister dst, Address src);
void movq(XMMRegister dst, XMMRegister src);
void movq(Register dst, XMMRegister src);
void movq(XMMRegister dst, Register src);

void movsbl(Register dst, Address src);
void movsbl(Register dst, Register src);

1610#ifdef _LP641
void movsbq(Register dst, Address src);
void movsbq(Register dst, Register src);

// Move signed 32bit immediate to 64bit extending sign
void movslq(Address  dst, int32_t imm64);
void movslq(Register dst, int32_t imm64);

void movslq(Register dst, Address src);
void movslq(Register dst, Register src);
void movslq(Register dst, void* src); // Dummy declaration to cause NULL to be ambiguous
1621#endif

void movswl(Register dst, Address src);
void movswl(Register dst, Register src);

1626#ifdef _LP641
void movswq(Register dst, Address src);
void movswq(Register dst, Register src);
1629#endif

void movw(Address dst, int imm16);
void movw(Register dst, Address src);
void movw(Address dst, Register src);

void movzbl(Register dst, Address src);
void movzbl(Register dst, Register src);

1638#ifdef _LP641
void movzbq(Register dst, Address src);
void movzbq(Register dst, Register src);
1641#endif

void movzwl(Register dst, Address src);
void movzwl(Register dst, Register src);

1646#ifdef _LP641
void movzwq(Register dst, Address src);
void movzwq(Register dst, Register src);
1649#endif

// Unsigned multiply with RAX destination register
void mull(Address src);
void mull(Register src);

1655#ifdef _LP641
void mulq(Address src);
void mulq(Register src);
void mulxq(Register dst1, Register dst2, Register src);
1659#endif

// Multiply Scalar Double-Precision Floating-Point Values
void mulsd(XMMRegister dst, Address src);
void mulsd(XMMRegister dst, XMMRegister src);

// Multiply Scalar Single-Precision Floating-Point Values
void mulss(XMMRegister dst, Address src);
void mulss(XMMRegister dst, XMMRegister src);

void negl(Register dst);
void negl(Address dst);

1672#ifdef _LP641
void negq(Register dst);
void negq(Address dst);
1675#endif

void nop(int i = 1);

void notl(Register dst);

1681#ifdef _LP641
void notq(Register dst);

void btsq(Address dst, int imm8);
void btrq(Address dst, int imm8);
1686#endif

void orw(Register dst, Register src);

void orl(Address dst, int32_t imm32);
void orl(Register dst, int32_t imm32);
void orl(Register dst, Address src);
void orl(Register dst, Register src);
void orl(Address dst, Register src);

void orb(Address dst, int imm8);
void orb(Address dst, Register src);

void orq(Address dst, int32_t imm32);
void orq(Address dst, Register src);
void orq(Register dst, int32_t imm32);
void orq(Register dst, Address src);
void orq(Register dst, Register src);

// Pack with signed saturation
void packsswb(XMMRegister dst, XMMRegister src);
void vpacksswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
void packssdw(XMMRegister dst, XMMRegister src);
void vpackssdw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);

// Pack with unsigned saturation
void packuswb(XMMRegister dst, XMMRegister src);
void packuswb(XMMRegister dst, Address src);
void packusdw(XMMRegister dst, XMMRegister src);
void vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
void vpackusdw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);

// Permutations
void vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len);
void vpermq(XMMRegister dst, XMMRegister src, int imm8);
void vpermq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
void vpermb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
void vpermb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
void vpermw(XMMRegister dst,  XMMRegister nds, XMMRegister src, int vector_len);
void vpermd(XMMRegister dst,  XMMRegister nds, Address src, int vector_len);
void vpermd(XMMRegister dst,  XMMRegister nds, XMMRegister src, int vector_len);
void vperm2i128(XMMRegister dst,  XMMRegister nds, XMMRegister src, int imm8);
void vperm2f128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8);
void vpermilps(XMMRegister dst, XMMRegister src, int imm8, int vector_len);
void vpermilpd(XMMRegister dst, XMMRegister src, int imm8, int vector_len);
void vpermpd(XMMRegister dst, XMMRegister src, int imm8, int vector_len);
void evpermi2q(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
void evpermt2b(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
void evpmultishiftqb(XMMRegister dst, XMMRegister ctl, XMMRegister src, int vector_len);

void pause();

// Undefined Instruction
void ud2();

// SSE4.2 string instructions
void pcmpestri(XMMRegister xmm1, XMMRegister xmm2, int imm8);
void pcmpestri(XMMRegister xmm1, Address src, int imm8);

void pcmpeqb(XMMRegister dst, XMMRegister src);
void vpcmpCCbwd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, int vector_len);

void vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
void evpcmpeqb(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len);
void evpcmpeqb(KRegister kdst, XMMRegister nds, Address src, int vector_len);
void evpcmpeqb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len);

void vpcmpgtb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
void evpcmpgtb(KRegister kdst, XMMRegister nds, Address src, int vector_len);
void evpcmpgtb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len);

void evpcmpuw(KRegister kdst, XMMRegister nds, XMMRegister src, ComparisonPredicate vcc, int vector_len);
void evpcmpuw(KRegister kdst, XMMRegister nds, Address src, ComparisonPredicate vcc, int vector_len);

void pcmpeqw(XMMRegister dst, XMMRegister src);
void vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
void evpcmpeqw(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len);
void evpcmpeqw(KRegister kdst, XMMRegister nds, Address src, int vector_len);

void vpcmpgtw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);

void pcmpeqd(XMMRegister dst, XMMRegister src);
void vpcmpeqd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
void evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, int vector_len);
void evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len);

void pcmpeqq(XMMRegister dst, XMMRegister src);
void vpcmpCCq(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, int vector_len);
void vpcmpeqq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
void evpcmpeqq(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len);
void evpcmpeqq(KRegister kdst, XMMRegister nds, Address src, int vector_len);

void pcmpgtq(XMMRegister dst, XMMRegister src);
void vpcmpgtq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);

void pmovmskb(Register dst, XMMRegister src);
void vpmovmskb(Register dst, XMMRegister src, int vec_enc);
void vmovmskps(Register dst, XMMRegister src, int vec_enc);
void vmovmskpd(Register dst, XMMRegister src, int vec_enc);
void vpmaskmovd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);

// SSE 4.1 extract
void pextrd(Register dst, XMMRegister src, int imm8);
void pextrq(Register dst, XMMRegister src, int imm8);
void pextrd(Address dst, XMMRegister src, int imm8);
void pextrq(Address dst, XMMRegister src, int imm8);
void pextrb(Register dst, XMMRegister src, int imm8);
void pextrb(Address dst, XMMRegister src, int imm8);
// SSE 2 extract
void pextrw(Register dst, XMMRegister src, int imm8);
void pextrw(Address dst, XMMRegister src, int imm8);

// SSE 4.1 insert
void pinsrd(XMMRegister dst, Register src, int imm8);
void pinsrq(XMMRegister dst, Register src, int imm8);
void pinsrb(XMMRegister dst, Register src, int imm8);
void pinsrd(XMMRegister dst, Address src, int imm8);
void pinsrq(XMMRegister dst, Address src, int imm8);
void pinsrb(XMMRegister dst, Address src, int imm8);
void insertps(XMMRegister dst, XMMRegister src, int imm8);
// SSE 2 insert
void pinsrw(XMMRegister dst, Register src, int imm8);
void pinsrw(XMMRegister dst, Address src, int imm8);

// AVX insert
void vpinsrd(XMMRegister dst, XMMRegister nds, Register src, int imm8);
void vpinsrb(XMMRegister dst, XMMRegister nds, Register src, int imm8);
void vpinsrq(XMMRegister dst, XMMRegister nds, Register src, int imm8);
void vpinsrw(XMMRegister dst, XMMRegister nds, Register src, int imm8);
void vinsertps(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8);

// Zero extend moves
void pmovzxbw(XMMRegister dst, XMMRegister src);
void pmovzxbw(XMMRegister dst, Address src);
void pmovzxbd(XMMRegister dst, XMMRegister src);
void vpmovzxbw( XMMRegister dst, Address src, int vector_len);
void pmovzxdq(XMMRegister dst, XMMRegister src);
void vpmovzxbw(XMMRegister dst, XMMRegister src, int vector_len);
void vpmovzxdq(XMMRegister dst, XMMRegister src, int vector_len);
void vpmovzxbd(XMMRegister dst, XMMRegister src, int vector_len);
void vpmovzxbq(XMMRegister dst, XMMRegister src, int vector_len);
void evpmovzxbw(XMMRegister dst, KRegister mask, Address src, int vector_len);

// Sign extend moves
void pmovsxbd(XMMRegister dst, XMMRegister src);
void pmovsxbq(XMMRegister dst, XMMRegister src);
void pmovsxbw(XMMRegister dst, XMMRegister src);
void pmovsxwd(XMMRegister dst, XMMRegister src);
void vpmovsxbd(XMMRegister dst, XMMRegister src, int vector_len);
void vpmovsxbq(XMMRegister dst, XMMRegister src, int vector_len);
void vpmovsxbw(XMMRegister dst, XMMRegister src, int vector_len);
void vpmovsxwd(XMMRegister dst, XMMRegister src, int vector_len);
void vpmovsxwq(XMMRegister dst, XMMRegister src, int vector_len);
void vpmovsxdq(XMMRegister dst, XMMRegister src, int vector_len);

void evpmovwb(Address dst, XMMRegister src, int vector_len);
void evpmovwb(Address dst, KRegister mask, XMMRegister src, int vector_len);

void vpmovzxwd(XMMRegister dst, XMMRegister src, int vector_len);

void evpmovdb(Address dst, XMMRegister src, int vector_len);

// Multiply add
void pmaddwd(XMMRegister dst, XMMRegister src);
void vpmaddwd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
void vpmaddubsw(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);

// Multiply add accumulate
void evpdpwssd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);

1856#ifndef _LP641 // no 32bit push/pop on amd64
void popl(Address dst);
1858#endif

1860#ifdef _LP641
void popq(Address dst);
void popq(Register dst);
1863#endif

void popcntl(Register dst, Address src);
void popcntl(Register dst, Register src);

void vpopcntd(XMMRegister dst, XMMRegister src, int vector_len);

1870#ifdef _LP641
void popcntq(Register dst, Address src);
void popcntq(Register dst, Register src);
1873#endif

// Prefetches (SSE, SSE2, 3DNOW only)

void prefetchnta(Address src);
void prefetchr(Address src);
void prefetcht0(Address src);
void prefetcht1(Address src);
void prefetcht2(Address src);
void prefetchw(Address src);

// Shuffle Bytes
void pshufb(XMMRegister dst, XMMRegister src);
void pshufb(XMMRegister dst, Address src);
void vpshufb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);

// Shuffle Packed Doublewords
void pshufd(XMMRegister dst, XMMRegister src, int mode);
void pshufd(XMMRegister dst, Address src,     int mode);
void vpshufd(XMMRegister dst, XMMRegister src, int mode, int vector_len);

// Shuffle Packed High/Low Words
void pshufhw(XMMRegister dst, XMMRegister src, int mode);
void pshuflw(XMMRegister dst, XMMRegister src, int mode);
void pshuflw(XMMRegister dst, Address src,     int mode);

//shuffle floats and doubles
void pshufps(XMMRegister, XMMRegister, int);
void pshufpd(XMMRegister, XMMRegister, int);
void vpshufps(XMMRegister, XMMRegister, XMMRegister, int, int);
void vpshufpd(XMMRegister, XMMRegister, XMMRegister, int, int);

// Shuffle packed values at 128 bit granularity
void evshufi64x2(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len);

// Shift Right by bytes Logical DoubleQuadword Immediate
void psrldq(XMMRegister dst, int shift);
// Shift Left by bytes Logical DoubleQuadword Immediate
void pslldq(XMMRegister dst, int shift);

// Logical Compare 128bit
void ptest(XMMRegister dst, XMMRegister src);
void ptest(XMMRegister dst, Address src);
// Logical Compare 256bit
void vptest(XMMRegister dst, XMMRegister src);
void vptest(XMMRegister dst, Address src);

void evptestmb(KRegister dst, XMMRegister nds, XMMRegister src, int vector_len);

// Vector compare
void vptest(XMMRegister dst, XMMRegister src, int vector_len);

// Interleave Low Bytes
void punpcklbw(XMMRegister dst, XMMRegister src);
void punpcklbw(XMMRegister dst, Address src);

// Interleave Low Doublewords
void punpckldq(XMMRegister dst, XMMRegister src);
void punpckldq(XMMRegister dst, Address src);

// Interleave Low Quadwords
void punpcklqdq(XMMRegister dst, XMMRegister src);

1936#ifndef _LP641 // no 32bit push/pop on amd64
void pushl(Address src);
1938#endif

void pushq(Address src);

void rcll(Register dst, int imm8);

void rclq(Register dst, int imm8);

void rcrq(Register dst, int imm8);

void rcpps(XMMRegister dst, XMMRegister src);

void rcpss(XMMRegister dst, XMMRegister src);

void rdtsc();

void ret(int imm16);

void roll(Register dst);

void roll(Register dst, int imm8);

void rorl(Register dst);

void rorl(Register dst, int imm8);

1964#ifdef _LP641
void rolq(Register dst);
void rolq(Register dst, int imm8);
void rorq(Register dst);
void rorq(Register dst, int imm8);
void rorxq(Register dst, Register src, int imm8);
void rorxd(Register dst, Register src, int imm8);
1971#endif

void sahf();

void sall(Register dst, int imm8);
void sall(Register dst);
void sall(Address dst, int imm8);
void sall(Address dst);

void sarl(Address dst, int imm8);
void sarl(Address dst);
void sarl(Register dst, int imm8);
void sarl(Register dst);

1985#ifdef _LP641
void salq(Register dst, int imm8);
void salq(Register dst);
void salq(Address dst, int imm8);
void salq(Address dst);

void sarq(Address dst, int imm8);
void sarq(Address dst);
void sarq(Register dst, int imm8);
void sarq(Register dst);
1995#endif

void sbbl(Address dst, int32_t imm32);
void sbbl(Register dst, int32_t imm32);
void sbbl(Register dst, Address src);
void sbbl(Register dst, Register src);

void sbbq(Address dst, int32_t imm32);
void sbbq(Register dst, int32_t imm32);
void sbbq(Register dst, Address src);
void sbbq(Register dst, Register src);

void setb(Condition cc, Register dst);

void sete(Register dst);
void setl(Register dst);
void setne(Register dst);

void palignr(XMMRegister dst, XMMRegister src, int imm8);
void vpalignr(XMMRegister dst, XMMRegister src1, XMMRegister src2, int imm8, int vector_len);
void evalignq(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);

void pblendw(XMMRegister dst, XMMRegister src, int imm8);
void vblendps(XMMRegister dst, XMMRegister src1, XMMRegister src2, int imm8, int vector_len);

void sha1rnds4(XMMRegister dst, XMMRegister src, int imm8);
void sha1nexte(XMMRegister dst, XMMRegister src);
void sha1msg1(XMMRegister dst, XMMRegister src);
void sha1msg2(XMMRegister dst, XMMRegister src);
// xmm0 is implicit additional source to the following instruction.
void sha256rnds2(XMMRegister dst, XMMRegister src);
void sha256msg1(XMMRegister dst, XMMRegister src);
void sha256msg2(XMMRegister dst, XMMRegister src);

void shldl(Register dst, Register src);
void shldl(Register dst, Register src, int8_t imm8);
void shrdl(Register dst, Register src);
void shrdl(Register dst, Register src, int8_t imm8);

void shll(Register dst, int imm8);
void shll(Register dst);

void shlq(Register dst, int imm8);
void shlq(Register dst);

void shrl(Register dst, int imm8);
void shrl(Register dst);
void shrl(Address dst);
void shrl(Address dst, int imm8);

void shrq(Register dst, int imm8);
void shrq(Register dst);
void shrq(Address dst);
void shrq(Address dst, int imm8);

void smovl(); // QQQ generic?

// Compute Square Root of Scalar Double-Precision Floating-Point Value
void sqrtsd(XMMRegister dst, Address src);
void sqrtsd(XMMRegister dst, XMMRegister src);

void roundsd(XMMRegister dst, Address src, int32_t rmode);
void roundsd(XMMRegister dst, XMMRegister src, int32_t rmode);

// Compute Square Root of Scalar Single-Precision Floating-Point Value
void sqrtss(XMMRegister dst, Address src);
void sqrtss(XMMRegister dst, XMMRegister src);

void std();

void stmxcsr( Address dst );

void subl(Address dst, int32_t imm32);
void subl(Address dst, Register src);
void subl(Register dst, int32_t imm32);
void subl(Register dst, Address src);
void subl(Register dst, Register src);

void subq(Address dst, int32_t imm32);
void subq(Address dst, Register src);
void subq(Register dst, int32_t imm32);
void subq(Register dst, Address src);
void subq(Register dst, Register src);

// Force generation of a 4 byte immediate value even if it fits into 8bit
void subl_imm32(Register dst, int32_t imm32);
void subq_imm32(Register dst, int32_t imm32);

// Subtract Scalar Double-Precision Floating-Point Values
void subsd(XMMRegister dst, Address src);
void subsd(XMMRegister dst, XMMRegister src);

// Subtract Scalar Single-Precision Floating-Point Values
void subss(XMMRegister dst, Address src);
void subss(XMMRegister dst, XMMRegister src);

void testb(Register dst, int imm8);
void testb(Address dst, int imm8);

void testl(Register dst, int32_t imm32);
void testl(Register dst, Register src);
void testl(Register dst, Address src);

void testq(Address dst, int32_t imm32);
void testq(Register dst, int32_t imm32);
void testq(Register dst, Register src);
void testq(Register dst, Address src);

// BMI - count trailing zeros
void tzcntl(Register dst, Register src);
void tzcntq(Register dst, Register src);

// Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
void ucomisd(XMMRegister dst, Address src);
void ucomisd(XMMRegister dst, XMMRegister src);

// Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
void ucomiss(XMMRegister dst, Address src);
void ucomiss(XMMRegister dst, XMMRegister src);

void xabort(int8_t imm8);

void xaddb(Address dst, Register src);
void xaddw(Address dst, Register src);
void xaddl(Address dst, Register src);
void xaddq(Address dst, Register src);

void xbegin(Label& abort, relocInfo::relocType rtype = relocInfo::none);

void xchgb(Register reg, Address adr);
void xchgw(Register reg, Address adr);
void xchgl(Register reg, Address adr);
void xchgl(Register dst, Register src);

void xchgq(Register reg, Address adr);
void xchgq(Register dst, Register src);

void xend();

// Get Value of Extended Control Register
void xgetbv();

void xorl(Register dst, int32_t imm32);
void xorl(Address dst, int32_t imm32);
void xorl(Register dst, Address src);
void xorl(Register dst, Register src);
void xorl(Address dst, Register src);

void xorb(Address dst, Register src);
void xorb(Register dst, Address src);
void xorw(Register dst, Register src);

void xorq(Register dst, Address src);
void xorq(Address dst, int32_t imm32);
void xorq(Register dst, Register src);
void xorq(Register dst, int32_t imm32);
void xorq(Address dst, Register src);

void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0

// AVX 3-operands scalar instructions (encoded with VEX prefix)

void vaddsd(XMMRegister dst, XMMRegister nds, Address src);
void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
void vaddss(XMMRegister dst, XMMRegister nds, Address src);
void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src);
void vdivsd(XMMRegister dst, XMMRegister nds, Address src);
void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
void vdivss(XMMRegister dst, XMMRegister nds, Address src);
void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src);
void vfmadd231sd(XMMRegister dst, XMMRegister nds, XMMRegister src);
void vfmadd231ss(XMMRegister dst, XMMRegister nds, XMMRegister src);
void vmulsd(XMMRegister dst, XMMRegister nds, Address src);
void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
void vmulss(XMMRegister dst, XMMRegister nds, Address src);
void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src);
void vsubsd(XMMRegister dst, XMMRegister nds, Address src);
void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
void vsubss(XMMRegister dst, XMMRegister nds, Address src);
void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src);

void vmaxss(XMMRegister dst, XMMRegister nds, XMMRegister src);
void vmaxsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
void vminss(XMMRegister dst, XMMRegister nds, XMMRegister src);
void vminsd(XMMRegister dst, XMMRegister nds, XMMRegister src);

void shlxl(Register dst, Register src1, Register src2);
void shlxq(Register dst, Register src1, Register src2);
void shrxl(Register dst, Register src1, Register src2);
void shrxq(Register dst, Register src1, Register src2);

void bzhiq(Register dst, Register src1, Register src2);
void pdep(Register dst, Register src1, Register src2);
void pext(Register dst, Register src1, Register src2);


//====================VECTOR ARITHMETIC=====================================
// Add Packed Floating-Point Values
void addpd(XMMRegister dst, XMMRegister src);
void addpd(XMMRegister dst, Address src);
void addps(XMMRegister dst, XMMRegister src);
void vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
void vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
void vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
void vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);

// Subtract Packed Floating-Point Values
void subpd(XMMRegister dst, XMMRegister src);
void subps(XMMRegister dst, XMMRegister src);
void vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
void vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
void vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
void vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);

// Multiply Packed Floating-Point Values
void mulpd(XMMRegister dst, XMMRegister src);
void mulpd(XMMRegister dst, Address src);
void mulps(XMMRegister dst, XMMRegister src);
void vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
void vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
void vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
void vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);

void vfmadd231pd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
void vfmadd231ps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
void vfmadd231pd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
void vfmadd231ps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);

// Divide Packed Floating-Point Values
void divpd(XMMRegister dst, XMMRegister src);
void divps(XMMRegister dst, XMMRegister src);
void vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
void vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
void vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
void vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);

// Sqrt Packed Floating-Point Values
void vsqrtpd(XMMRegister dst, XMMRegister src, int vector_len);
void vsqrtpd(XMMRegister dst, Address src, int vector_len);
void vsqrtps(XMMRegister dst, XMMRegister src, int vector_len);
void vsqrtps(XMMRegister dst, Address src, int vector_len);

// Round Packed Double precision value.
void vroundpd(XMMRegister dst, XMMRegister src, int32_t rmode, int vector_len);
void vroundpd(XMMRegister dst, Address src, int32_t rmode, int vector_len);
void vrndscalepd(XMMRegister dst,  XMMRegister src,  int32_t rmode, int vector_len);
void vrndscalepd(XMMRegister dst, Address src, int32_t rmode, int vector_len);

// Bitwise Logical AND of Packed Floating-Point Values
void andpd(XMMRegister dst, XMMRegister src);
void andps(XMMRegister dst, XMMRegister src);
void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);

void unpckhpd(XMMRegister dst, XMMRegister src);
void unpcklpd(XMMRegister dst, XMMRegister src);

// Bitwise Logical XOR of Packed Floating-Point Values
void xorpd(XMMRegister dst, XMMRegister src);
void xorps(XMMRegister dst, XMMRegister src);
void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);

// Add horizontal packed integers
void vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
void vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
void phaddw(XMMRegister dst, XMMRegister src);
void phaddd(XMMRegister dst, XMMRegister src);

// Add packed integers
void paddb(XMMRegister dst, XMMRegister src);
void paddw(XMMRegister dst, XMMRegister src);
void paddd(XMMRegister dst, XMMRegister src);
void paddd(XMMRegister dst, Address src);
void paddq(XMMRegister dst, XMMRegister src);
void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
void vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
void vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
void vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
void vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
void vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
void vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);

// Leaf level assembler routines for masked operations.
void evpaddb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evpaddb(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
void evpaddw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evpaddw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
void evpaddd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evpaddd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
void evpaddq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evpaddq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
void evaddps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evaddps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
void evaddpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evaddpd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
void evpsubb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evpsubb(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
void evpsubw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evpsubw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
void evpsubd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evpsubd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
void evpsubq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evpsubq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
void evsubps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evsubps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
void evsubpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evsubpd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
void evpmullw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evpmullw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
void evpmulld(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evpmulld(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
void evpmullq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evpmullq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
void evmulps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evmulps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
void evmulpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evmulpd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
void evdivps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evdivps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
void evdivpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evdivpd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
void evpabsb(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
void evpabsb(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len);
void evpabsw(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
void evpabsw(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len);
void evpabsd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
void evpabsd(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len);
void evpabsq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
void evpabsq(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len);
void evpfma213ps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evpfma213ps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
void evpfma213pd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evpfma213pd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
void evpermb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evpermb(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
void evpermw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evpermw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
void evpermd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evpermd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
void evpermq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evpermq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
void evpsllw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evpslld(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evpsllq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evpsrlw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evpsrld(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evpsrlq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evpsraw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evpsrad(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evpsraq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evsqrtps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evsqrtps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
void evsqrtpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evsqrtpd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);

void evpsllw(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);
void evpslld(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);
void evpsllq(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);
void evpsrlw(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);
void evpsrld(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);
void evpsrlq(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);
void evpsraw(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);
void evpsrad(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);
void evpsraq(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);

void evpsllvw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evpsllvd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evpsllvq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evpsrlvw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evpsrlvd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evpsrlvq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evpsravw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evpsravd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evpsravq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evpmaxsb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evpmaxsw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evpmaxsd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evpmaxsq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evpminsb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evpminsw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evpminsd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evpminsq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evpmaxsb(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
void evpmaxsw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
void evpmaxsd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
void evpmaxsq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
void evpminsb(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
void evpminsw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
void evpminsd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
void evpminsq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
void evpord(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evpord(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
void evporq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evporq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
void evpandd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evpandd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
void evpandq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evpandq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
void evpxord(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evpxord(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
void evpxorq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evpxorq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);

void evprold(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);
void evprolq(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);
void evprolvd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evprolvq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evprord(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);
void evprorq(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);
void evprorvd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evprorvq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);

// Sub packed integers
void psubb(XMMRegister dst, XMMRegister src);
void psubw(XMMRegister dst, XMMRegister src);
void psubd(XMMRegister dst, XMMRegister src);
void psubq(XMMRegister dst, XMMRegister src);
void vpsubusb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
void vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
void vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
void vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
void vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
void vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
void vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);

// Multiply packed integers (only shorts and ints)
void pmullw(XMMRegister dst, XMMRegister src);
void pmulld(XMMRegister dst, XMMRegister src);
void pmuludq(XMMRegister dst, XMMRegister src);
void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
void vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
void vpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
void vpmuludq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
void vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
void vpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
void vpmulhuw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);

// Minimum of packed integers
void pminsb(XMMRegister dst, XMMRegister src);
void vpminsb(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
void pminsw(XMMRegister dst, XMMRegister src);
void vpminsw(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
void pminsd(XMMRegister dst, XMMRegister src);
void vpminsd(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
void vpminsq(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
void minps(XMMRegister dst, XMMRegister src);
void vminps(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
void minpd(XMMRegister dst, XMMRegister src);
void vminpd(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);

// Maximum of packed integers
void pmaxsb(XMMRegister dst, XMMRegister src);
void vpmaxsb(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
void pmaxsw(XMMRegister dst, XMMRegister src);
void vpmaxsw(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
void pmaxsd(XMMRegister dst, XMMRegister src);
void vpmaxsd(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
void vpmaxsq(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
void maxps(XMMRegister dst, XMMRegister src);
void vmaxps(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
void maxpd(XMMRegister dst, XMMRegister src);
void vmaxpd(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);

// Shift left packed integers
void psllw(XMMRegister dst, int shift);
void pslld(XMMRegister dst, int shift);
void psllq(XMMRegister dst, int shift);
void psllw(XMMRegister dst, XMMRegister shift);
void pslld(XMMRegister dst, XMMRegister shift);
void psllq(XMMRegister dst, XMMRegister shift);
void vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len);
void vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len);
void vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
void vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
void vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
void vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
void vpslldq(XMMRegister dst, XMMRegister src, int shift, int vector_len);

// Logical shift right packed integers
void psrlw(XMMRegister dst, int shift);
void psrld(XMMRegister dst, int shift);
void psrlq(XMMRegister dst, int shift);
void psrlw(XMMRegister dst, XMMRegister shift);
void psrld(XMMRegister dst, XMMRegister shift);
void psrlq(XMMRegister dst, XMMRegister shift);
void vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len);
void vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len);
void vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
void vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
void vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
void vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
void vpsrldq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
void evpsrlvw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
void evpsllvw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);

// Arithmetic shift right packed integers (only shorts and ints, no instructions for longs)
void psraw(XMMRegister dst, int shift);
void psrad(XMMRegister dst, int shift);
void psraw(XMMRegister dst, XMMRegister shift);
void psrad(XMMRegister dst, XMMRegister shift);
void vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len);
void vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len);
void vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
void vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
void evpsravw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
void evpsraq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
void evpsraq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);

// Variable shift left packed integers
void vpsllvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
void vpsllvq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);

// Variable shift right packed integers
void vpsrlvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
void vpsrlvq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);

// Variable shift right arithmetic packed integers
void vpsravd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
void evpsravq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);

void vpshldvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
void vpshrdvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);

// And packed integers
void pand(XMMRegister dst, XMMRegister src);
void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
void vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
void vpandq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);

// Andn packed integers
void pandn(XMMRegister dst, XMMRegister src);
void vpandn(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);

// Or packed integers
void por(XMMRegister dst, XMMRegister src);
void vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
void vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
void vporq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);

// Xor packed integers
void pxor(XMMRegister dst, XMMRegister src);
void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
void vpxorq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
void evpxorq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
void evpxorq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);

// Ternary logic instruction.
void vpternlogd(XMMRegister dst, int imm8, XMMRegister src2, XMMRegister src3, int vector_len);
void vpternlogd(XMMRegister dst, int imm8, XMMRegister src2, Address     src3, int vector_len);
void vpternlogq(XMMRegister dst, int imm8, XMMRegister src2, XMMRegister src3, int vector_len);

// Vector Rotate Left/Right instruction.
void evprolvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
void evprolvq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
void evprorvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
void evprorvq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
void evprold(XMMRegister dst, XMMRegister src, int shift, int vector_len);
void evprolq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
void evprord(XMMRegister dst, XMMRegister src, int shift, int vector_len);
void evprorq(XMMRegister dst, XMMRegister src, int shift, int vector_len);

// vinserti forms
void vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
void vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8);
void vinserti32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
void vinserti32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8);
void vinserti64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);

// vinsertf forms
void vinsertf128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
void vinsertf128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8);
void vinsertf32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
void vinsertf32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8);
void vinsertf64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
void vinsertf64x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8);

// vextracti forms
void vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8);
void vextracti128(Address dst, XMMRegister src, uint8_t imm8);
void vextracti32x4(XMMRegister dst, XMMRegister src, uint8_t imm8);
void vextracti32x4(Address dst, XMMRegister src, uint8_t imm8);
void vextracti64x2(XMMRegister dst, XMMRegister src, uint8_t imm8);
void vextracti64x4(XMMRegister dst, XMMRegister src, uint8_t imm8);
void vextracti64x4(Address dst, XMMRegister src, uint8_t imm8);

// vextractf forms
void vextractf128(XMMRegister dst, XMMRegister src, uint8_t imm8);
void vextractf128(Address dst, XMMRegister src, uint8_t imm8);
void vextractf32x4(XMMRegister dst, XMMRegister src, uint8_t imm8);
void vextractf32x4(Address dst, XMMRegister src, uint8_t imm8);
void vextractf64x2(XMMRegister dst, XMMRegister src, uint8_t imm8);
void vextractf64x4(XMMRegister dst, XMMRegister src, uint8_t imm8);
void vextractf64x4(Address dst, XMMRegister src, uint8_t imm8);

// xmm/mem sourced byte/word/dword/qword replicate
void vpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len);
void vpbroadcastb(XMMRegister dst, Address src, int vector_len);
void vpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len);
void vpbroadcastw(XMMRegister dst, Address src, int vector_len);
void vpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len);
void vpbroadcastd(XMMRegister dst, Address src, int vector_len);
void vpbroadcastq(XMMRegister dst, XMMRegister src, int vector_len);
void vpbroadcastq(XMMRegister dst, Address src, int vector_len);

void evbroadcasti32x4(XMMRegister dst, Address src, int vector_len);
void evbroadcasti64x2(XMMRegister dst, XMMRegister src, int vector_len);
void evbroadcasti64x2(XMMRegister dst, Address src, int vector_len);

// scalar single/double/128bit precision replicate
void vbroadcastss(XMMRegister dst, XMMRegister src, int vector_len);
void vbroadcastss(XMMRegister dst, Address src, int vector_len);
void vbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len);
void vbroadcastsd(XMMRegister dst, Address src, int vector_len);
void vbroadcastf128(XMMRegister dst, Address src, int vector_len);

// gpr sourced byte/word/dword/qword replicate
void evpbroadcastb(XMMRegister dst, Register src, int vector_len);
void evpbroadcastw(XMMRegister dst, Register src, int vector_len);
void evpbroadcastd(XMMRegister dst, Register src, int vector_len);
void evpbroadcastq(XMMRegister dst, Register src, int vector_len);

// Gather AVX2 and AVX3
void vpgatherdd(XMMRegister dst, Address src, XMMRegister mask, int vector_len);
void vpgatherdq(XMMRegister dst, Address src, XMMRegister mask, int vector_len);
void vgatherdpd(XMMRegister dst, Address src, XMMRegister mask, int vector_len);
void vgatherdps(XMMRegister dst, Address src, XMMRegister mask, int vector_len);
void evpgatherdd(XMMRegister dst, KRegister mask, Address src, int vector_len);
void evpgatherdq(XMMRegister dst, KRegister mask, Address src, int vector_len);
void evgatherdpd(XMMRegister dst, KRegister mask, Address src, int vector_len);
void evgatherdps(XMMRegister dst, KRegister mask, Address src, int vector_len);

//Scatter AVX3 only
void evpscatterdd(Address dst, KRegister mask, XMMRegister src, int vector_len);
void evpscatterdq(Address dst, KRegister mask, XMMRegister src, int vector_len);
void evscatterdps(Address dst, KRegister mask, XMMRegister src, int vector_len);
void evscatterdpd(Address dst, KRegister mask, XMMRegister src, int vector_len);

// Carry-Less Multiplication Quadword
void pclmulqdq(XMMRegister dst, XMMRegister src, int mask);
void vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask);
void evpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask, int vector_len);
// AVX instruction which is used to clear upper 128 bits of YMM registers and
// to avoid transaction penalty between AVX and SSE states. There is no
// penalty if legacy SSE instructions are encoded using VEX prefix because
// they always clear upper 128 bits. It should be used before calling
// runtime code and native libraries.
void vzeroupper();

// Vector double compares
void vcmppd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len);
void evcmppd(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
             ComparisonPredicateFP comparison, int vector_len);

// Vector float compares
void vcmpps(XMMRegister dst, XMMRegister nds, XMMRegister src, int comparison, int vector_len);
void evcmpps(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
             ComparisonPredicateFP comparison, int vector_len);

// Vector integer compares
void vpcmpgtd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
void evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
             int comparison, bool is_signed, int vector_len);
void evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, Address src,
             int comparison, bool is_signed, int vector_len);

// Vector long compares
void evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
             int comparison, bool is_signed, int vector_len);
void evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, Address src,
             int comparison, bool is_signed, int vector_len);

// Vector byte compares
void evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
             int comparison, bool is_signed, int vector_len);
void evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, Address src,
             int comparison, bool is_signed, int vector_len);

// Vector short compares
void evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
             int comparison, bool is_signed, int vector_len);
void evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, Address src,
             int comparison, bool is_signed, int vector_len);

void evpmovb2m(KRegister dst, XMMRegister src, int vector_len);
void evpmovw2m(KRegister dst, XMMRegister src, int vector_len);
void evpmovd2m(KRegister dst, XMMRegister src, int vector_len);
void evpmovq2m(KRegister dst, XMMRegister src, int vector_len);
void evpmovm2b(XMMRegister dst, KRegister src, int vector_len);
void evpmovm2w(XMMRegister dst, KRegister src, int vector_len);
void evpmovm2d(XMMRegister dst, KRegister src, int vector_len);
void evpmovm2q(XMMRegister dst, KRegister src, int vector_len);

// Vector blends
void blendvps(XMMRegister dst, XMMRegister src);
void blendvpd(XMMRegister dst, XMMRegister src);
void pblendvb(XMMRegister dst, XMMRegister src);
void blendvpb(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len);
void vblendvps(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len);
void vblendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len);
void vpblendvb(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len);
void vpblendd(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len);
void evblendmpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evblendmps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evpblendmb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evpblendmw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evpblendmd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
void evpblendmq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
protected:
// Next instructions require address alignment 16 bytes SSE mode.
// They should be called only from corresponding MacroAssembler instructions.
void andpd(XMMRegister dst, Address src);
void andps(XMMRegister dst, Address src);
void xorpd(XMMRegister dst, Address src);
void xorps(XMMRegister dst, Address src);

2720};

2722// The Intel x86/Amd64 Assembler attributes: All fields enclosed here are to guide encoding level decisions.
2723// Specific set functions are for specialized use, else defaults or whatever was supplied to object construction
2724// are applied.
2725class InstructionAttr {
2726public:
InstructionAttr(
  int vector_len,     // The length of vector to be applied in encoding - for both AVX and EVEX
  bool rex_vex_w,     // Width of data: if 32-bits or less, false, else if 64-bit or specially defined, true
  bool legacy_mode,   // Details if either this instruction is conditionally encoded to AVX or earlier if true else possibly EVEX
  bool no_reg_mask,   // when true, k0 is used when EVEX encoding is chosen, else embedded_opmask_register_specifier is used
  bool uses_vl)       // This instruction may have legacy constraints based on vector length for EVEX
  :
    _rex_vex_w(rex_vex_w),
    _legacy_mode(legacy_mode || UseAVX < 3),
    _no_reg_mask(no_reg_mask),
    _uses_vl(uses_vl),
    _rex_vex_w_reverted(false),
    _is_evex_instruction(false),
    _is_clear_context(true),
    _is_extended_context(false),
    _avx_vector_len(vector_len),
    _tuple_type(Assembler::EVEX_ETUP),
    _input_size_in_bits(Assembler::EVEX_NObit),
    _evex_encoding(0),
    _embedded_opmask_register_specifier(0), // hard code k0
    _current_assembler(NULL__null) { }

~InstructionAttr() {
  if (_current_assembler != NULL__null) {
    _current_assembler->clear_attributes();
  }
  _current_assembler = NULL__null;
}

2756private:
bool _rex_vex_w;
bool _legacy_mode;
bool _no_reg_mask;
bool _uses_vl;
bool _rex_vex_w_reverted;
bool _is_evex_instruction;
bool _is_clear_context;
bool _is_extended_context;
int  _avx_vector_len;
int  _tuple_type;
int  _input_size_in_bits;
int  _evex_encoding;
int _embedded_opmask_register_specifier;

Assembler *_current_assembler;

2773public:
// query functions for field accessors
bool is_rex_vex_w(void) const { return _rex_vex_w; }
bool is_legacy_mode(void) const { return _legacy_mode; }
bool is_no_reg_mask(void) const { return _no_reg_mask; }
bool uses_vl(void) const { return _uses_vl; }
bool is_rex_vex_w_reverted(void) { return _rex_vex_w_reverted; }
bool is_evex_instruction(void) const { return _is_evex_instruction; }
bool is_clear_context(void) const { return _is_clear_context; }
bool is_extended_context(void) const { return _is_extended_context; }
int  get_vector_len(void) const { return _avx_vector_len; }
int  get_tuple_type(void) const { return _tuple_type; }
int  get_input_size(void) const { return _input_size_in_bits; }
int  get_evex_encoding(void) const { return _evex_encoding; }
int  get_embedded_opmask_register_specifier(void) const { return _embedded_opmask_register_specifier; }

// Set the vector len manually
void set_vector_len(int vector_len) { _avx_vector_len = vector_len; }

// Set revert rex_vex_w for avx encoding
void set_rex_vex_w_reverted(void) { _rex_vex_w_reverted = true; }

// Set rex_vex_w based on state
void set_rex_vex_w(bool state) { _rex_vex_w = state; }

// Set the instruction to be encoded in AVX mode
void set_is_legacy_mode(void) { _legacy_mode = true; }

// Set the current instuction to be encoded as an EVEX instuction
void set_is_evex_instruction(void) { _is_evex_instruction = true; }

// Internal encoding data used in compressed immediate offset programming
void set_evex_encoding(int value) { _evex_encoding = value; }

// When the Evex.Z field is set (true), it is used to clear all non directed XMM/YMM/ZMM components.
// This method unsets it so that merge semantics are used instead.
void reset_is_clear_context(void) { _is_clear_context = false; }

// Map back to current asembler so that we can manage object level assocation
void set_current_assembler(Assembler *current_assembler) { _current_assembler = current_assembler; }

// Address modifiers used for compressed displacement calculation
void set_address_attributes(int tuple_type, int input_size_in_bits);

// Set embedded opmask register specifier.
void set_embedded_opmask_register_specifier(KRegister mask) {
  _embedded_opmask_register_specifier = (*mask).encoding() & 0x7;
}

2822};

2824#endif // CPU_X86_ASSEMBLER_X86_HPP